drivers/net/ethernet/intel/igb/igb_ethtool.c

   1 /* Intel(R) Gigabit Ethernet Linux driver
   2  * Copyright(c) 2007-2014 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, see <http://www.gnu.org/licenses/>.
  15  *
  16  * The full GNU General Public License is included in this distribution in
  17  * the file called "COPYING".
  18  *
  19  * Contact Information:
  20  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  */
  23
  24 /* ethtool support for igb */
  25
  26 #include <linux/vmalloc.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/if_ether.h>
  32 #include <linux/ethtool.h>
  33 #include <linux/sched.h>
  34 #include <linux/slab.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/highmem.h>
  37 #include <linux/mdio.h>
  38
  39 #include "igb.h"
  40
  41 struct igb_stats {
  42         char stat_string[ETH_GSTRING_LEN];
  43         int sizeof_stat;
  44         int stat_offset;
  45 };
  46
  47 #define IGB_STAT(_name, _stat) { \
  48         .stat_string = _name, \
  49         .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
  50         .stat_offset = offsetof(struct igb_adapter, _stat) \
  51 }
  52 static const struct igb_stats igb_gstrings_stats[] = {
  53         IGB_STAT("rx_packets", stats.gprc),
  54         IGB_STAT("tx_packets", stats.gptc),
  55         IGB_STAT("rx_bytes", stats.gorc),
  56         IGB_STAT("tx_bytes", stats.gotc),
  57         IGB_STAT("rx_broadcast", stats.bprc),
  58         IGB_STAT("tx_broadcast", stats.bptc),
  59         IGB_STAT("rx_multicast", stats.mprc),
  60         IGB_STAT("tx_multicast", stats.mptc),
  61         IGB_STAT("multicast", stats.mprc),
  62         IGB_STAT("collisions", stats.colc),
  63         IGB_STAT("rx_crc_errors", stats.crcerrs),
  64         IGB_STAT("rx_no_buffer_count", stats.rnbc),
  65         IGB_STAT("rx_missed_errors", stats.mpc),
  66         IGB_STAT("tx_aborted_errors", stats.ecol),
  67         IGB_STAT("tx_carrier_errors", stats.tncrs),
  68         IGB_STAT("tx_window_errors", stats.latecol),
  69         IGB_STAT("tx_abort_late_coll", stats.latecol),
  70         IGB_STAT("tx_deferred_ok", stats.dc),
  71         IGB_STAT("tx_single_coll_ok", stats.scc),
  72         IGB_STAT("tx_multi_coll_ok", stats.mcc),
  73         IGB_STAT("tx_timeout_count", tx_timeout_count),
  74         IGB_STAT("rx_long_length_errors", stats.roc),
  75         IGB_STAT("rx_short_length_errors", stats.ruc),
  76         IGB_STAT("rx_align_errors", stats.algnerrc),
  77         IGB_STAT("tx_tcp_seg_good", stats.tsctc),
  78         IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
  79         IGB_STAT("rx_flow_control_xon", stats.xonrxc),
  80         IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
  81         IGB_STAT("tx_flow_control_xon", stats.xontxc),
  82         IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
  83         IGB_STAT("rx_long_byte_count", stats.gorc),
  84         IGB_STAT("tx_dma_out_of_sync", stats.doosync),
  85         IGB_STAT("tx_smbus", stats.mgptc),
  86         IGB_STAT("rx_smbus", stats.mgprc),
  87         IGB_STAT("dropped_smbus", stats.mgpdc),
  88         IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
  89         IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
  90         IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
  91         IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
  92         IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
  93         IGB_STAT("tx_hwtstamp_skipped", tx_hwtstamp_skipped),
  94         IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
  95 };
  96
  97 #define IGB_NETDEV_STAT(_net_stat) { \
  98         .stat_string = __stringify(_net_stat), \
  99         .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
 100         .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
 101 }
 102 static const struct igb_stats igb_gstrings_net_stats[] = {
 103         IGB_NETDEV_STAT(rx_errors),
 104         IGB_NETDEV_STAT(tx_errors),
 105         IGB_NETDEV_STAT(tx_dropped),
 106         IGB_NETDEV_STAT(rx_length_errors),
 107         IGB_NETDEV_STAT(rx_over_errors),
 108         IGB_NETDEV_STAT(rx_frame_errors),
 109         IGB_NETDEV_STAT(rx_fifo_errors),
 110         IGB_NETDEV_STAT(tx_fifo_errors),
 111         IGB_NETDEV_STAT(tx_heartbeat_errors)
 112 };
 113
 114 #define IGB_GLOBAL_STATS_LEN    \
 115         (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
 116 #define IGB_NETDEV_STATS_LEN    \
 117         (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
 118 #define IGB_RX_QUEUE_STATS_LEN \
 119         (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
 120
 121 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
 122
 123 #define IGB_QUEUE_STATS_LEN \
 124         ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
 125           IGB_RX_QUEUE_STATS_LEN) + \
 126          (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
 127           IGB_TX_QUEUE_STATS_LEN))
 128 #define IGB_STATS_LEN \
 129         (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
 130
 131 enum igb_diagnostics_results {
 132         TEST_REG = 0,
 133         TEST_EEP,
 134         TEST_IRQ,
 135         TEST_LOOP,
 136         TEST_LINK
 137 };
 138
 139 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
 140         [TEST_REG]  = "Register test  (offline)",
 141         [TEST_EEP]  = "Eeprom test    (offline)",
 142         [TEST_IRQ]  = "Interrupt test (offline)",
 143         [TEST_LOOP] = "Loopback test  (offline)",
 144         [TEST_LINK] = "Link test   (on/offline)"
 145 };
 146 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
 147
 148 static const char igb_priv_flags_strings[][ETH_GSTRING_LEN] = {
 149 #define IGB_PRIV_FLAGS_LEGACY_RX        BIT(0)
 150         "legacy-rx",
 151 };
 152
 153 #define IGB_PRIV_FLAGS_STR_LEN ARRAY_SIZE(igb_priv_flags_strings)
 154
 155 static int igb_get_link_ksettings(struct net_device *netdev,
 156                                   struct ethtool_link_ksettings *cmd)
 157 {
 158         struct igb_adapter *adapter = netdev_priv(netdev);
 159         struct e1000_hw *hw = &adapter->hw;
 160         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 161         struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
 162         u32 status;
 163         u32 speed;
 164         u32 supported, advertising;
 165
 166         status = pm_runtime_suspended(&adapter->pdev->dev) ?
 167                  0 : rd32(E1000_STATUS);
 168         if (hw->phy.media_type == e1000_media_type_copper) {
 169
 170                 supported = (SUPPORTED_10baseT_Half |
 171                              SUPPORTED_10baseT_Full |
 172                              SUPPORTED_100baseT_Half |
 173                              SUPPORTED_100baseT_Full |
 174                              SUPPORTED_1000baseT_Full|
 175                              SUPPORTED_Autoneg |
 176                              SUPPORTED_TP |
 177                              SUPPORTED_Pause);
 178                 advertising = ADVERTISED_TP;
 179
 180                 if (hw->mac.autoneg == 1) {
 181                         advertising |= ADVERTISED_Autoneg;
 182                         /* the e1000 autoneg seems to match ethtool nicely */
 183                         advertising |= hw->phy.autoneg_advertised;
 184                 }
 185
 186                 cmd->base.port = PORT_TP;
 187                 cmd->base.phy_address = hw->phy.addr;
 188         } else {
 189                 supported = (SUPPORTED_FIBRE |
 190                              SUPPORTED_1000baseKX_Full |
 191                              SUPPORTED_Autoneg |
 192                              SUPPORTED_Pause);
 193                 advertising = (ADVERTISED_FIBRE |
 194                                ADVERTISED_1000baseKX_Full);
 195                 if (hw->mac.type == e1000_i354) {
 196                         if ((hw->device_id ==
 197                              E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) &&
 198                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
 199                                 supported |= SUPPORTED_2500baseX_Full;
 200                                 supported &= ~SUPPORTED_1000baseKX_Full;
 201                                 advertising |= ADVERTISED_2500baseX_Full;
 202                                 advertising &= ~ADVERTISED_1000baseKX_Full;
 203                         }
 204                 }
 205                 if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) {
 206                         supported |= SUPPORTED_100baseT_Full;
 207                         advertising |= ADVERTISED_100baseT_Full;
 208                 }
 209                 if (hw->mac.autoneg == 1)
 210                         advertising |= ADVERTISED_Autoneg;
 211
 212                 cmd->base.port = PORT_FIBRE;
 213         }
 214         if (hw->mac.autoneg != 1)
 215                 advertising &= ~(ADVERTISED_Pause |
 216                                  ADVERTISED_Asym_Pause);
 217
 218         switch (hw->fc.requested_mode) {
 219         case e1000_fc_full:
 220                 advertising |= ADVERTISED_Pause;
 221                 break;
 222         case e1000_fc_rx_pause:
 223                 advertising |= (ADVERTISED_Pause |
 224                                 ADVERTISED_Asym_Pause);
 225                 break;
 226         case e1000_fc_tx_pause:
 227                 advertising |=  ADVERTISED_Asym_Pause;
 228                 break;
 229         default:
 230                 advertising &= ~(ADVERTISED_Pause |
 231                                  ADVERTISED_Asym_Pause);
 232         }
 233         if (status & E1000_STATUS_LU) {
 234                 if ((status & E1000_STATUS_2P5_SKU) &&
 235                     !(status & E1000_STATUS_2P5_SKU_OVER)) {
 236                         speed = SPEED_2500;
 237                 } else if (status & E1000_STATUS_SPEED_1000) {
 238                         speed = SPEED_1000;
 239                 } else if (status & E1000_STATUS_SPEED_100) {
 240                         speed = SPEED_100;
 241                 } else {
 242                         speed = SPEED_10;
 243                 }
 244                 if ((status & E1000_STATUS_FD) ||
 245                     hw->phy.media_type != e1000_media_type_copper)
 246                         cmd->base.duplex = DUPLEX_FULL;
 247                 else
 248                         cmd->base.duplex = DUPLEX_HALF;
 249         } else {
 250                 speed = SPEED_UNKNOWN;
 251                 cmd->base.duplex = DUPLEX_UNKNOWN;
 252         }
 253         cmd->base.speed = speed;
 254         if ((hw->phy.media_type == e1000_media_type_fiber) ||
 255             hw->mac.autoneg)
 256                 cmd->base.autoneg = AUTONEG_ENABLE;
 257         else
 258                 cmd->base.autoneg = AUTONEG_DISABLE;
 259
 260         /* MDI-X => 2; MDI =>1; Invalid =>0 */
 261         if (hw->phy.media_type == e1000_media_type_copper)
 262                 cmd->base.eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
 263                                                       ETH_TP_MDI;
 264         else
 265                 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
 266
 267         if (hw->phy.mdix == AUTO_ALL_MODES)
 268                 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
 269         else
 270                 cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix;
 271
 272         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
 273                                                 supported);
 274         ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
 275                                                 advertising);
 276
 277         return 0;
 278 }
 279
 280 static int igb_set_link_ksettings(struct net_device *netdev,
 281                                   const struct ethtool_link_ksettings *cmd)
 282 {
 283         struct igb_adapter *adapter = netdev_priv(netdev);
 284         struct e1000_hw *hw = &adapter->hw;
 285         u32 advertising;
 286
 287         /* When SoL/IDER sessions are active, autoneg/speed/duplex
 288          * cannot be changed
 289          */
 290         if (igb_check_reset_block(hw)) {
 291                 dev_err(&adapter->pdev->dev,
 292                         "Cannot change link characteristics when SoL/IDER is active.\n");
 293                 return -EINVAL;
 294         }
 295
 296         /* MDI setting is only allowed when autoneg enabled because
 297          * some hardware doesn't allow MDI setting when speed or
 298          * duplex is forced.
 299          */
 300         if (cmd->base.eth_tp_mdix_ctrl) {
 301                 if (hw->phy.media_type != e1000_media_type_copper)
 302                         return -EOPNOTSUPP;
 303
 304                 if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
 305                     (cmd->base.autoneg != AUTONEG_ENABLE)) {
 306                         dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
 307                         return -EINVAL;
 308                 }
 309         }
 310
 311         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 312                 usleep_range(1000, 2000);
 313
 314         ethtool_convert_link_mode_to_legacy_u32(&advertising,
 315                                                 cmd->link_modes.advertising);
 316
 317         if (cmd->base.autoneg == AUTONEG_ENABLE) {
 318                 hw->mac.autoneg = 1;
 319                 if (hw->phy.media_type == e1000_media_type_fiber) {
 320                         hw->phy.autoneg_advertised = advertising |
 321                                                      ADVERTISED_FIBRE |
 322                                                      ADVERTISED_Autoneg;
 323                         switch (adapter->link_speed) {
 324                         case SPEED_2500:
 325                                 hw->phy.autoneg_advertised =
 326                                         ADVERTISED_2500baseX_Full;
 327                                 break;
 328                         case SPEED_1000:
 329                                 hw->phy.autoneg_advertised =
 330                                         ADVERTISED_1000baseT_Full;
 331                                 break;
 332                         case SPEED_100:
 333                                 hw->phy.autoneg_advertised =
 334                                         ADVERTISED_100baseT_Full;
 335                                 break;
 336                         default:
 337                                 break;
 338                         }
 339                 } else {
 340                         hw->phy.autoneg_advertised = advertising |
 341                                                      ADVERTISED_TP |
 342                                                      ADVERTISED_Autoneg;
 343                 }
 344                 advertising = hw->phy.autoneg_advertised;
 345                 if (adapter->fc_autoneg)
 346                         hw->fc.requested_mode = e1000_fc_default;
 347         } else {
 348                 u32 speed = cmd->base.speed;
 349                 /* calling this overrides forced MDI setting */
 350                 if (igb_set_spd_dplx(adapter, speed, cmd->base.duplex)) {
 351                         clear_bit(__IGB_RESETTING, &adapter->state);
 352                         return -EINVAL;
 353                 }
 354         }
 355
 356         /* MDI-X => 2; MDI => 1; Auto => 3 */
 357         if (cmd->base.eth_tp_mdix_ctrl) {
 358                 /* fix up the value for auto (3 => 0) as zero is mapped
 359                  * internally to auto
 360                  */
 361                 if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
 362                         hw->phy.mdix = AUTO_ALL_MODES;
 363                 else
 364                         hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl;
 365         }
 366
 367         /* reset the link */
 368         if (netif_running(adapter->netdev)) {
 369                 igb_down(adapter);
 370                 igb_up(adapter);
 371         } else
 372                 igb_reset(adapter);
 373
 374         clear_bit(__IGB_RESETTING, &adapter->state);
 375         return 0;
 376 }
 377
 378 static u32 igb_get_link(struct net_device *netdev)
 379 {
 380         struct igb_adapter *adapter = netdev_priv(netdev);
 381         struct e1000_mac_info *mac = &adapter->hw.mac;
 382
 383         /* If the link is not reported up to netdev, interrupts are disabled,
 384          * and so the physical link state may have changed since we last
 385          * looked. Set get_link_status to make sure that the true link
 386          * state is interrogated, rather than pulling a cached and possibly
 387          * stale link state from the driver.
 388          */
 389         if (!netif_carrier_ok(netdev))
 390                 mac->get_link_status = 1;
 391
 392         return igb_has_link(adapter);
 393 }
 394
 395 static void igb_get_pauseparam(struct net_device *netdev,
 396                                struct ethtool_pauseparam *pause)
 397 {
 398         struct igb_adapter *adapter = netdev_priv(netdev);
 399         struct e1000_hw *hw = &adapter->hw;
 400
 401         pause->autoneg =
 402                 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
 403
 404         if (hw->fc.current_mode == e1000_fc_rx_pause)
 405                 pause->rx_pause = 1;
 406         else if (hw->fc.current_mode == e1000_fc_tx_pause)
 407                 pause->tx_pause = 1;
 408         else if (hw->fc.current_mode == e1000_fc_full) {
 409                 pause->rx_pause = 1;
 410                 pause->tx_pause = 1;
 411         }
 412 }
 413
 414 static int igb_set_pauseparam(struct net_device *netdev,
 415                               struct ethtool_pauseparam *pause)
 416 {
 417         struct igb_adapter *adapter = netdev_priv(netdev);
 418         struct e1000_hw *hw = &adapter->hw;
 419         int retval = 0;
 420
 421         /* 100basefx does not support setting link flow control */
 422         if (hw->dev_spec._82575.eth_flags.e100_base_fx)
 423                 return -EINVAL;
 424
 425         adapter->fc_autoneg = pause->autoneg;
 426
 427         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 428                 usleep_range(1000, 2000);
 429
 430         if (adapter->fc_autoneg == AUTONEG_ENABLE) {
 431                 hw->fc.requested_mode = e1000_fc_default;
 432                 if (netif_running(adapter->netdev)) {
 433                         igb_down(adapter);
 434                         igb_up(adapter);
 435                 } else {
 436                         igb_reset(adapter);
 437                 }
 438         } else {
 439                 if (pause->rx_pause && pause->tx_pause)
 440                         hw->fc.requested_mode = e1000_fc_full;
 441                 else if (pause->rx_pause && !pause->tx_pause)
 442                         hw->fc.requested_mode = e1000_fc_rx_pause;
 443                 else if (!pause->rx_pause && pause->tx_pause)
 444                         hw->fc.requested_mode = e1000_fc_tx_pause;
 445                 else if (!pause->rx_pause && !pause->tx_pause)
 446                         hw->fc.requested_mode = e1000_fc_none;
 447
 448                 hw->fc.current_mode = hw->fc.requested_mode;
 449
 450                 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
 451                           igb_force_mac_fc(hw) : igb_setup_link(hw));
 452         }
 453
 454         clear_bit(__IGB_RESETTING, &adapter->state);
 455         return retval;
 456 }
 457
 458 static u32 igb_get_msglevel(struct net_device *netdev)
 459 {
 460         struct igb_adapter *adapter = netdev_priv(netdev);
 461         return adapter->msg_enable;
 462 }
 463
 464 static void igb_set_msglevel(struct net_device *netdev, u32 data)
 465 {
 466         struct igb_adapter *adapter = netdev_priv(netdev);
 467         adapter->msg_enable = data;
 468 }
 469
 470 static int igb_get_regs_len(struct net_device *netdev)
 471 {
 472 #define IGB_REGS_LEN 739
 473         return IGB_REGS_LEN * sizeof(u32);
 474 }
 475
 476 static void igb_get_regs(struct net_device *netdev,
 477                          struct ethtool_regs *regs, void *p)
 478 {
 479         struct igb_adapter *adapter = netdev_priv(netdev);
 480         struct e1000_hw *hw = &adapter->hw;
 481         u32 *regs_buff = p;
 482         u8 i;
 483
 484         memset(p, 0, IGB_REGS_LEN * sizeof(u32));
 485
 486         regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id;
 487
 488         /* General Registers */
 489         regs_buff[0] = rd32(E1000_CTRL);
 490         regs_buff[1] = rd32(E1000_STATUS);
 491         regs_buff[2] = rd32(E1000_CTRL_EXT);
 492         regs_buff[3] = rd32(E1000_MDIC);
 493         regs_buff[4] = rd32(E1000_SCTL);
 494         regs_buff[5] = rd32(E1000_CONNSW);
 495         regs_buff[6] = rd32(E1000_VET);
 496         regs_buff[7] = rd32(E1000_LEDCTL);
 497         regs_buff[8] = rd32(E1000_PBA);
 498         regs_buff[9] = rd32(E1000_PBS);
 499         regs_buff[10] = rd32(E1000_FRTIMER);
 500         regs_buff[11] = rd32(E1000_TCPTIMER);
 501
 502         /* NVM Register */
 503         regs_buff[12] = rd32(E1000_EECD);
 504
 505         /* Interrupt */
 506         /* Reading EICS for EICR because they read the
 507          * same but EICS does not clear on read
 508          */
 509         regs_buff[13] = rd32(E1000_EICS);
 510         regs_buff[14] = rd32(E1000_EICS);
 511         regs_buff[15] = rd32(E1000_EIMS);
 512         regs_buff[16] = rd32(E1000_EIMC);
 513         regs_buff[17] = rd32(E1000_EIAC);
 514         regs_buff[18] = rd32(E1000_EIAM);
 515         /* Reading ICS for ICR because they read the
 516          * same but ICS does not clear on read
 517          */
 518         regs_buff[19] = rd32(E1000_ICS);
 519         regs_buff[20] = rd32(E1000_ICS);
 520         regs_buff[21] = rd32(E1000_IMS);
 521         regs_buff[22] = rd32(E1000_IMC);
 522         regs_buff[23] = rd32(E1000_IAC);
 523         regs_buff[24] = rd32(E1000_IAM);
 524         regs_buff[25] = rd32(E1000_IMIRVP);
 525
 526         /* Flow Control */
 527         regs_buff[26] = rd32(E1000_FCAL);
 528         regs_buff[27] = rd32(E1000_FCAH);
 529         regs_buff[28] = rd32(E1000_FCTTV);
 530         regs_buff[29] = rd32(E1000_FCRTL);
 531         regs_buff[30] = rd32(E1000_FCRTH);
 532         regs_buff[31] = rd32(E1000_FCRTV);
 533
 534         /* Receive */
 535         regs_buff[32] = rd32(E1000_RCTL);
 536         regs_buff[33] = rd32(E1000_RXCSUM);
 537         regs_buff[34] = rd32(E1000_RLPML);
 538         regs_buff[35] = rd32(E1000_RFCTL);
 539         regs_buff[36] = rd32(E1000_MRQC);
 540         regs_buff[37] = rd32(E1000_VT_CTL);
 541
 542         /* Transmit */
 543         regs_buff[38] = rd32(E1000_TCTL);
 544         regs_buff[39] = rd32(E1000_TCTL_EXT);
 545         regs_buff[40] = rd32(E1000_TIPG);
 546         regs_buff[41] = rd32(E1000_DTXCTL);
 547
 548         /* Wake Up */
 549         regs_buff[42] = rd32(E1000_WUC);
 550         regs_buff[43] = rd32(E1000_WUFC);
 551         regs_buff[44] = rd32(E1000_WUS);
 552         regs_buff[45] = rd32(E1000_IPAV);
 553         regs_buff[46] = rd32(E1000_WUPL);
 554
 555         /* MAC */
 556         regs_buff[47] = rd32(E1000_PCS_CFG0);
 557         regs_buff[48] = rd32(E1000_PCS_LCTL);
 558         regs_buff[49] = rd32(E1000_PCS_LSTAT);
 559         regs_buff[50] = rd32(E1000_PCS_ANADV);
 560         regs_buff[51] = rd32(E1000_PCS_LPAB);
 561         regs_buff[52] = rd32(E1000_PCS_NPTX);
 562         regs_buff[53] = rd32(E1000_PCS_LPABNP);
 563
 564         /* Statistics */
 565         regs_buff[54] = adapter->stats.crcerrs;
 566         regs_buff[55] = adapter->stats.algnerrc;
 567         regs_buff[56] = adapter->stats.symerrs;
 568         regs_buff[57] = adapter->stats.rxerrc;
 569         regs_buff[58] = adapter->stats.mpc;
 570         regs_buff[59] = adapter->stats.scc;
 571         regs_buff[60] = adapter->stats.ecol;
 572         regs_buff[61] = adapter->stats.mcc;
 573         regs_buff[62] = adapter->stats.latecol;
 574         regs_buff[63] = adapter->stats.colc;
 575         regs_buff[64] = adapter->stats.dc;
 576         regs_buff[65] = adapter->stats.tncrs;
 577         regs_buff[66] = adapter->stats.sec;
 578         regs_buff[67] = adapter->stats.htdpmc;
 579         regs_buff[68] = adapter->stats.rlec;
 580         regs_buff[69] = adapter->stats.xonrxc;
 581         regs_buff[70] = adapter->stats.xontxc;
 582         regs_buff[71] = adapter->stats.xoffrxc;
 583         regs_buff[72] = adapter->stats.xofftxc;
 584         regs_buff[73] = adapter->stats.fcruc;
 585         regs_buff[74] = adapter->stats.prc64;
 586         regs_buff[75] = adapter->stats.prc127;
 587         regs_buff[76] = adapter->stats.prc255;
 588         regs_buff[77] = adapter->stats.prc511;
 589         regs_buff[78] = adapter->stats.prc1023;
 590         regs_buff[79] = adapter->stats.prc1522;
 591         regs_buff[80] = adapter->stats.gprc;
 592         regs_buff[81] = adapter->stats.bprc;
 593         regs_buff[82] = adapter->stats.mprc;
 594         regs_buff[83] = adapter->stats.gptc;
 595         regs_buff[84] = adapter->stats.gorc;
 596         regs_buff[86] = adapter->stats.gotc;
 597         regs_buff[88] = adapter->stats.rnbc;
 598         regs_buff[89] = adapter->stats.ruc;
 599         regs_buff[90] = adapter->stats.rfc;
 600         regs_buff[91] = adapter->stats.roc;
 601         regs_buff[92] = adapter->stats.rjc;
 602         regs_buff[93] = adapter->stats.mgprc;
 603         regs_buff[94] = adapter->stats.mgpdc;
 604         regs_buff[95] = adapter->stats.mgptc;
 605         regs_buff[96] = adapter->stats.tor;
 606         regs_buff[98] = adapter->stats.tot;
 607         regs_buff[100] = adapter->stats.tpr;
 608         regs_buff[101] = adapter->stats.tpt;
 609         regs_buff[102] = adapter->stats.ptc64;
 610         regs_buff[103] = adapter->stats.ptc127;
 611         regs_buff[104] = adapter->stats.ptc255;
 612         regs_buff[105] = adapter->stats.ptc511;
 613         regs_buff[106] = adapter->stats.ptc1023;
 614         regs_buff[107] = adapter->stats.ptc1522;
 615         regs_buff[108] = adapter->stats.mptc;
 616         regs_buff[109] = adapter->stats.bptc;
 617         regs_buff[110] = adapter->stats.tsctc;
 618         regs_buff[111] = adapter->stats.iac;
 619         regs_buff[112] = adapter->stats.rpthc;
 620         regs_buff[113] = adapter->stats.hgptc;
 621         regs_buff[114] = adapter->stats.hgorc;
 622         regs_buff[116] = adapter->stats.hgotc;
 623         regs_buff[118] = adapter->stats.lenerrs;
 624         regs_buff[119] = adapter->stats.scvpc;
 625         regs_buff[120] = adapter->stats.hrmpc;
 626
 627         for (i = 0; i < 4; i++)
 628                 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
 629         for (i = 0; i < 4; i++)
 630                 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
 631         for (i = 0; i < 4; i++)
 632                 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
 633         for (i = 0; i < 4; i++)
 634                 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
 635         for (i = 0; i < 4; i++)
 636                 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
 637         for (i = 0; i < 4; i++)
 638                 regs_buff[141 + i] = rd32(E1000_RDH(i));
 639         for (i = 0; i < 4; i++)
 640                 regs_buff[145 + i] = rd32(E1000_RDT(i));
 641         for (i = 0; i < 4; i++)
 642                 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
 643
 644         for (i = 0; i < 10; i++)
 645                 regs_buff[153 + i] = rd32(E1000_EITR(i));
 646         for (i = 0; i < 8; i++)
 647                 regs_buff[163 + i] = rd32(E1000_IMIR(i));
 648         for (i = 0; i < 8; i++)
 649                 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
 650         for (i = 0; i < 16; i++)
 651                 regs_buff[179 + i] = rd32(E1000_RAL(i));
 652         for (i = 0; i < 16; i++)
 653                 regs_buff[195 + i] = rd32(E1000_RAH(i));
 654
 655         for (i = 0; i < 4; i++)
 656                 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
 657         for (i = 0; i < 4; i++)
 658                 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
 659         for (i = 0; i < 4; i++)
 660                 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
 661         for (i = 0; i < 4; i++)
 662                 regs_buff[223 + i] = rd32(E1000_TDH(i));
 663         for (i = 0; i < 4; i++)
 664                 regs_buff[227 + i] = rd32(E1000_TDT(i));
 665         for (i = 0; i < 4; i++)
 666                 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
 667         for (i = 0; i < 4; i++)
 668                 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
 669         for (i = 0; i < 4; i++)
 670                 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
 671         for (i = 0; i < 4; i++)
 672                 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
 673
 674         for (i = 0; i < 4; i++)
 675                 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
 676         for (i = 0; i < 4; i++)
 677                 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
 678         for (i = 0; i < 32; i++)
 679                 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
 680         for (i = 0; i < 128; i++)
 681                 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
 682         for (i = 0; i < 128; i++)
 683                 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
 684         for (i = 0; i < 4; i++)
 685                 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
 686
 687         regs_buff[547] = rd32(E1000_TDFH);
 688         regs_buff[548] = rd32(E1000_TDFT);
 689         regs_buff[549] = rd32(E1000_TDFHS);
 690         regs_buff[550] = rd32(E1000_TDFPC);
 691
 692         if (hw->mac.type > e1000_82580) {
 693                 regs_buff[551] = adapter->stats.o2bgptc;
 694                 regs_buff[552] = adapter->stats.b2ospc;
 695                 regs_buff[553] = adapter->stats.o2bspc;
 696                 regs_buff[554] = adapter->stats.b2ogprc;
 697         }
 698
 699         if (hw->mac.type != e1000_82576)
 700                 return;
 701         for (i = 0; i < 12; i++)
 702                 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
 703         for (i = 0; i < 4; i++)
 704                 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
 705         for (i = 0; i < 12; i++)
 706                 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
 707         for (i = 0; i < 12; i++)
 708                 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
 709         for (i = 0; i < 12; i++)
 710                 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
 711         for (i = 0; i < 12; i++)
 712                 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
 713         for (i = 0; i < 12; i++)
 714                 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
 715         for (i = 0; i < 12; i++)
 716                 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
 717
 718         for (i = 0; i < 12; i++)
 719                 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
 720         for (i = 0; i < 12; i++)
 721                 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
 722         for (i = 0; i < 12; i++)
 723                 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
 724         for (i = 0; i < 12; i++)
 725                 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
 726         for (i = 0; i < 12; i++)
 727                 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
 728         for (i = 0; i < 12; i++)
 729                 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
 730         for (i = 0; i < 12; i++)
 731                 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
 732         for (i = 0; i < 12; i++)
 733                 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
 734 }
 735
 736 static int igb_get_eeprom_len(struct net_device *netdev)
 737 {
 738         struct igb_adapter *adapter = netdev_priv(netdev);
 739         return adapter->hw.nvm.word_size * 2;
 740 }
 741
 742 static int igb_get_eeprom(struct net_device *netdev,
 743                           struct ethtool_eeprom *eeprom, u8 *bytes)
 744 {
 745         struct igb_adapter *adapter = netdev_priv(netdev);
 746         struct e1000_hw *hw = &adapter->hw;
 747         u16 *eeprom_buff;
 748         int first_word, last_word;
 749         int ret_val = 0;
 750         u16 i;
 751
 752         if (eeprom->len == 0)
 753                 return -EINVAL;
 754
 755         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 756
 757         first_word = eeprom->offset >> 1;
 758         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 759
 760         eeprom_buff = kmalloc(sizeof(u16) *
 761                         (last_word - first_word + 1), GFP_KERNEL);
 762         if (!eeprom_buff)
 763                 return -ENOMEM;
 764
 765         if (hw->nvm.type == e1000_nvm_eeprom_spi)
 766                 ret_val = hw->nvm.ops.read(hw, first_word,
 767                                            last_word - first_word + 1,
 768                                            eeprom_buff);
 769         else {
 770                 for (i = 0; i < last_word - first_word + 1; i++) {
 771                         ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
 772                                                    &eeprom_buff[i]);
 773                         if (ret_val)
 774                                 break;
 775                 }
 776         }
 777
 778         /* Device's eeprom is always little-endian, word addressable */
 779         for (i = 0; i < last_word - first_word + 1; i++)
 780                 le16_to_cpus(&eeprom_buff[i]);
 781
 782         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
 783                         eeprom->len);
 784         kfree(eeprom_buff);
 785
 786         return ret_val;
 787 }
 788
 789 static int igb_set_eeprom(struct net_device *netdev,
 790                           struct ethtool_eeprom *eeprom, u8 *bytes)
 791 {
 792         struct igb_adapter *adapter = netdev_priv(netdev);
 793         struct e1000_hw *hw = &adapter->hw;
 794         u16 *eeprom_buff;
 795         void *ptr;
 796         int max_len, first_word, last_word, ret_val = 0;
 797         u16 i;
 798
 799         if (eeprom->len == 0)
 800                 return -EOPNOTSUPP;
 801
 802         if ((hw->mac.type >= e1000_i210) &&
 803             !igb_get_flash_presence_i210(hw)) {
 804                 return -EOPNOTSUPP;
 805         }
 806
 807         if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
 808                 return -EFAULT;
 809
 810         max_len = hw->nvm.word_size * 2;
 811
 812         first_word = eeprom->offset >> 1;
 813         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 814         eeprom_buff = kmalloc(max_len, GFP_KERNEL);
 815         if (!eeprom_buff)
 816                 return -ENOMEM;
 817
 818         ptr = (void *)eeprom_buff;
 819
 820         if (eeprom->offset & 1) {
 821                 /* need read/modify/write of first changed EEPROM word
 822                  * only the second byte of the word is being modified
 823                  */
 824                 ret_val = hw->nvm.ops.read(hw, first_word, 1,
 825                                             &eeprom_buff[0]);
 826                 ptr++;
 827         }
 828         if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
 829                 /* need read/modify/write of last changed EEPROM word
 830                  * only the first byte of the word is being modified
 831                  */
 832                 ret_val = hw->nvm.ops.read(hw, last_word, 1,
 833                                    &eeprom_buff[last_word - first_word]);
 834         }
 835
 836         /* Device's eeprom is always little-endian, word addressable */
 837         for (i = 0; i < last_word - first_word + 1; i++)
 838                 le16_to_cpus(&eeprom_buff[i]);
 839
 840         memcpy(ptr, bytes, eeprom->len);
 841
 842         for (i = 0; i < last_word - first_word + 1; i++)
 843                 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
 844
 845         ret_val = hw->nvm.ops.write(hw, first_word,
 846                                     last_word - first_word + 1, eeprom_buff);
 847
 848         /* Update the checksum if nvm write succeeded */
 849         if (ret_val == 0)
 850                 hw->nvm.ops.update(hw);
 851
 852         igb_set_fw_version(adapter);
 853         kfree(eeprom_buff);
 854         return ret_val;
 855 }
 856
 857 static void igb_get_drvinfo(struct net_device *netdev,
 858                             struct ethtool_drvinfo *drvinfo)
 859 {
 860         struct igb_adapter *adapter = netdev_priv(netdev);
 861
 862         strlcpy(drvinfo->driver,  igb_driver_name, sizeof(drvinfo->driver));
 863         strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
 864
 865         /* EEPROM image version # is reported as firmware version # for
 866          * 82575 controllers
 867          */
 868         strlcpy(drvinfo->fw_version, adapter->fw_version,
 869                 sizeof(drvinfo->fw_version));
 870         strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
 871                 sizeof(drvinfo->bus_info));
 872
 873         drvinfo->n_priv_flags = IGB_PRIV_FLAGS_STR_LEN;
 874 }
 875
 876 static void igb_get_ringparam(struct net_device *netdev,
 877                               struct ethtool_ringparam *ring)
 878 {
 879         struct igb_adapter *adapter = netdev_priv(netdev);
 880
 881         ring->rx_max_pending = IGB_MAX_RXD;
 882         ring->tx_max_pending = IGB_MAX_TXD;
 883         ring->rx_pending = adapter->rx_ring_count;
 884         ring->tx_pending = adapter->tx_ring_count;
 885 }
 886
 887 static int igb_set_ringparam(struct net_device *netdev,
 888                              struct ethtool_ringparam *ring)
 889 {
 890         struct igb_adapter *adapter = netdev_priv(netdev);
 891         struct igb_ring *temp_ring;
 892         int i, err = 0;
 893         u16 new_rx_count, new_tx_count;
 894
 895         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 896                 return -EINVAL;
 897
 898         new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
 899         new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
 900         new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
 901
 902         new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
 903         new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
 904         new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
 905
 906         if ((new_tx_count == adapter->tx_ring_count) &&
 907             (new_rx_count == adapter->rx_ring_count)) {
 908                 /* nothing to do */
 909                 return 0;
 910         }
 911
 912         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 913                 usleep_range(1000, 2000);
 914
 915         if (!netif_running(adapter->netdev)) {
 916                 for (i = 0; i < adapter->num_tx_queues; i++)
 917                         adapter->tx_ring[i]->count = new_tx_count;
 918                 for (i = 0; i < adapter->num_rx_queues; i++)
 919                         adapter->rx_ring[i]->count = new_rx_count;
 920                 adapter->tx_ring_count = new_tx_count;
 921                 adapter->rx_ring_count = new_rx_count;
 922                 goto clear_reset;
 923         }
 924
 925         if (adapter->num_tx_queues > adapter->num_rx_queues)
 926                 temp_ring = vmalloc(adapter->num_tx_queues *
 927                                     sizeof(struct igb_ring));
 928         else
 929                 temp_ring = vmalloc(adapter->num_rx_queues *
 930                                     sizeof(struct igb_ring));
 931
 932         if (!temp_ring) {
 933                 err = -ENOMEM;
 934                 goto clear_reset;
 935         }
 936
 937         igb_down(adapter);
 938
 939         /* We can't just free everything and then setup again,
 940          * because the ISRs in MSI-X mode get passed pointers
 941          * to the Tx and Rx ring structs.
 942          */
 943         if (new_tx_count != adapter->tx_ring_count) {
 944                 for (i = 0; i < adapter->num_tx_queues; i++) {
 945                         memcpy(&temp_ring[i], adapter->tx_ring[i],
 946                                sizeof(struct igb_ring));
 947
 948                         temp_ring[i].count = new_tx_count;
 949                         err = igb_setup_tx_resources(&temp_ring[i]);
 950                         if (err) {
 951                                 while (i) {
 952                                         i--;
 953                                         igb_free_tx_resources(&temp_ring[i]);
 954                                 }
 955                                 goto err_setup;
 956                         }
 957                 }
 958
 959                 for (i = 0; i < adapter->num_tx_queues; i++) {
 960                         igb_free_tx_resources(adapter->tx_ring[i]);
 961
 962                         memcpy(adapter->tx_ring[i], &temp_ring[i],
 963                                sizeof(struct igb_ring));
 964                 }
 965
 966                 adapter->tx_ring_count = new_tx_count;
 967         }
 968
 969         if (new_rx_count != adapter->rx_ring_count) {
 970                 for (i = 0; i < adapter->num_rx_queues; i++) {
 971                         memcpy(&temp_ring[i], adapter->rx_ring[i],
 972                                sizeof(struct igb_ring));
 973
 974                         temp_ring[i].count = new_rx_count;
 975                         err = igb_setup_rx_resources(&temp_ring[i]);
 976                         if (err) {
 977                                 while (i) {
 978                                         i--;
 979                                         igb_free_rx_resources(&temp_ring[i]);
 980                                 }
 981                                 goto err_setup;
 982                         }
 983
 984                 }
 985
 986                 for (i = 0; i < adapter->num_rx_queues; i++) {
 987                         igb_free_rx_resources(adapter->rx_ring[i]);
 988
 989                         memcpy(adapter->rx_ring[i], &temp_ring[i],
 990                                sizeof(struct igb_ring));
 991                 }
 992
 993                 adapter->rx_ring_count = new_rx_count;
 994         }
 995 err_setup:
 996         igb_up(adapter);
 997         vfree(temp_ring);
 998 clear_reset:
 999         clear_bit(__IGB_RESETTING, &adapter->state);
1000         return err;
1001 }
1002
1003 /* ethtool register test data */
1004 struct igb_reg_test {
1005         u16 reg;
1006         u16 reg_offset;
1007         u16 array_len;
1008         u16 test_type;
1009         u32 mask;
1010         u32 write;
1011 };
1012
1013 /* In the hardware, registers are laid out either singly, in arrays
1014  * spaced 0x100 bytes apart, or in contiguous tables.  We assume
1015  * most tests take place on arrays or single registers (handled
1016  * as a single-element array) and special-case the tables.
1017  * Table tests are always pattern tests.
1018  *
1019  * We also make provision for some required setup steps by specifying
1020  * registers to be written without any read-back testing.
1021  */
1022
1023 #define PATTERN_TEST    1
1024 #define SET_READ_TEST   2
1025 #define WRITE_NO_TEST   3
1026 #define TABLE32_TEST    4
1027 #define TABLE64_TEST_LO 5
1028 #define TABLE64_TEST_HI 6
1029
1030 /* i210 reg test */
1031 static struct igb_reg_test reg_test_i210[] = {
1032         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1033         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1034         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1035         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1036         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1037         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1038         /* RDH is read-only for i210, only test RDT. */
1039         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1040         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1041         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1042         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1043         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1044         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1045         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1046         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1047         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1048         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1049         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1050         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1051         { E1000_RA,        0, 16, TABLE64_TEST_LO,
1052                                                 0xFFFFFFFF, 0xFFFFFFFF },
1053         { E1000_RA,        0, 16, TABLE64_TEST_HI,
1054                                                 0x900FFFFF, 0xFFFFFFFF },
1055         { E1000_MTA,       0, 128, TABLE32_TEST,
1056                                                 0xFFFFFFFF, 0xFFFFFFFF },
1057         { 0, 0, 0, 0, 0 }
1058 };
1059
1060 /* i350 reg test */
1061 static struct igb_reg_test reg_test_i350[] = {
1062         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1063         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1064         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1065         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1066         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1067         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1068         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1069         { E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1070         { E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1071         { E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1072         /* RDH is read-only for i350, only test RDT. */
1073         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1074         { E1000_RDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1075         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1076         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1077         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1078         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1079         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1080         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1081         { E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1082         { E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1083         { E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1084         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1085         { E1000_TDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1086         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1087         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1088         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1089         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1090         { E1000_RA,        0, 16, TABLE64_TEST_LO,
1091                                                 0xFFFFFFFF, 0xFFFFFFFF },
1092         { E1000_RA,        0, 16, TABLE64_TEST_HI,
1093                                                 0xC3FFFFFF, 0xFFFFFFFF },
1094         { E1000_RA2,       0, 16, TABLE64_TEST_LO,
1095                                                 0xFFFFFFFF, 0xFFFFFFFF },
1096         { E1000_RA2,       0, 16, TABLE64_TEST_HI,
1097                                                 0xC3FFFFFF, 0xFFFFFFFF },
1098         { E1000_MTA,       0, 128, TABLE32_TEST,
1099                                                 0xFFFFFFFF, 0xFFFFFFFF },
1100         { 0, 0, 0, 0 }
1101 };
1102
1103 /* 82580 reg test */
1104 static struct igb_reg_test reg_test_82580[] = {
1105         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1106         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1107         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1108         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1109         { E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1110         { E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1111         { E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1112         { E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1113         { E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1114         { E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1115         /* RDH is read-only for 82580, only test RDT. */
1116         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1117         { E1000_RDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1118         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1119         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1120         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1121         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1122         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1123         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1124         { E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1125         { E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1126         { E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1127         { E1000_TDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1128         { E1000_TDT(4),    0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1129         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1130         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1131         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1132         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1133         { E1000_RA,        0, 16, TABLE64_TEST_LO,
1134                                                 0xFFFFFFFF, 0xFFFFFFFF },
1135         { E1000_RA,        0, 16, TABLE64_TEST_HI,
1136                                                 0x83FFFFFF, 0xFFFFFFFF },
1137         { E1000_RA2,       0, 8, TABLE64_TEST_LO,
1138                                                 0xFFFFFFFF, 0xFFFFFFFF },
1139         { E1000_RA2,       0, 8, TABLE64_TEST_HI,
1140                                                 0x83FFFFFF, 0xFFFFFFFF },
1141         { E1000_MTA,       0, 128, TABLE32_TEST,
1142                                                 0xFFFFFFFF, 0xFFFFFFFF },
1143         { 0, 0, 0, 0 }
1144 };
1145
1146 /* 82576 reg test */
1147 static struct igb_reg_test reg_test_82576[] = {
1148         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1149         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1150         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1151         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1152         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1153         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1154         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1155         { E1000_RDBAL(4),  0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1156         { E1000_RDBAH(4),  0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1157         { E1000_RDLEN(4),  0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1158         /* Enable all RX queues before testing. */
1159         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1160           E1000_RXDCTL_QUEUE_ENABLE },
1161         { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0,
1162           E1000_RXDCTL_QUEUE_ENABLE },
1163         /* RDH is read-only for 82576, only test RDT. */
1164         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1165         { E1000_RDT(4),    0x40, 12,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1166         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
1167         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, 0 },
1168         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1169         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1170         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1171         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1172         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1173         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1174         { E1000_TDBAL(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1175         { E1000_TDBAH(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1176         { E1000_TDLEN(4),  0x40, 12,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1177         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1178         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1179         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1180         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1181         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1182         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1183         { E1000_RA2,       0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1184         { E1000_RA2,       0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1185         { E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1186         { 0, 0, 0, 0 }
1187 };
1188
1189 /* 82575 register test */
1190 static struct igb_reg_test reg_test_82575[] = {
1191         { E1000_FCAL,      0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1192         { E1000_FCAH,      0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1193         { E1000_FCT,       0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1194         { E1000_VET,       0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1195         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1196         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1197         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1198         /* Enable all four RX queues before testing. */
1199         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1200           E1000_RXDCTL_QUEUE_ENABLE },
1201         /* RDH is read-only for 82575, only test RDT. */
1202         { E1000_RDT(0),    0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1203         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1204         { E1000_FCRTH,     0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1205         { E1000_FCTTV,     0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1206         { E1000_TIPG,      0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1207         { E1000_TDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1208         { E1000_TDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1209         { E1000_TDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1210         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1211         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1212         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1213         { E1000_TCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1214         { E1000_TXCW,      0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1215         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1216         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1217         { E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1218         { 0, 0, 0, 0 }
1219 };
1220
1221 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1222                              int reg, u32 mask, u32 write)
1223 {
1224         struct e1000_hw *hw = &adapter->hw;
1225         u32 pat, val;
1226         static const u32 _test[] = {
1227                 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1228         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1229                 wr32(reg, (_test[pat] & write));
1230                 val = rd32(reg) & mask;
1231                 if (val != (_test[pat] & write & mask)) {
1232                         dev_err(&adapter->pdev->dev,
1233                                 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1234                                 reg, val, (_test[pat] & write & mask));
1235                         *data = reg;
1236                         return true;
1237                 }
1238         }
1239
1240         return false;
1241 }
1242
1243 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1244                               int reg, u32 mask, u32 write)
1245 {
1246         struct e1000_hw *hw = &adapter->hw;
1247         u32 val;
1248
1249         wr32(reg, write & mask);
1250         val = rd32(reg);
1251         if ((write & mask) != (val & mask)) {
1252                 dev_err(&adapter->pdev->dev,
1253                         "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1254                         reg, (val & mask), (write & mask));
1255                 *data = reg;
1256                 return true;
1257         }
1258
1259         return false;
1260 }
1261
1262 #define REG_PATTERN_TEST(reg, mask, write) \
1263         do { \
1264                 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1265                         return 1; \
1266         } while (0)
1267
1268 #define REG_SET_AND_CHECK(reg, mask, write) \
1269         do { \
1270                 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1271                         return 1; \
1272         } while (0)
1273
1274 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1275 {
1276         struct e1000_hw *hw = &adapter->hw;
1277         struct igb_reg_test *test;
1278         u32 value, before, after;
1279         u32 i, toggle;
1280
1281         switch (adapter->hw.mac.type) {
1282         case e1000_i350:
1283         case e1000_i354:
1284                 test = reg_test_i350;
1285                 toggle = 0x7FEFF3FF;
1286                 break;
1287         case e1000_i210:
1288         case e1000_i211:
1289                 test = reg_test_i210;
1290                 toggle = 0x7FEFF3FF;
1291                 break;
1292         case e1000_82580:
1293                 test = reg_test_82580;
1294                 toggle = 0x7FEFF3FF;
1295                 break;
1296         case e1000_82576:
1297                 test = reg_test_82576;
1298                 toggle = 0x7FFFF3FF;
1299                 break;
1300         default:
1301                 test = reg_test_82575;
1302                 toggle = 0x7FFFF3FF;
1303                 break;
1304         }
1305
1306         /* Because the status register is such a special case,
1307          * we handle it separately from the rest of the register
1308          * tests.  Some bits are read-only, some toggle, and some
1309          * are writable on newer MACs.
1310          */
1311         before = rd32(E1000_STATUS);
1312         value = (rd32(E1000_STATUS) & toggle);
1313         wr32(E1000_STATUS, toggle);
1314         after = rd32(E1000_STATUS) & toggle;
1315         if (value != after) {
1316                 dev_err(&adapter->pdev->dev,
1317                         "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1318                         after, value);
1319                 *data = 1;
1320                 return 1;
1321         }
1322         /* restore previous status */
1323         wr32(E1000_STATUS, before);
1324
1325         /* Perform the remainder of the register test, looping through
1326          * the test table until we either fail or reach the null entry.
1327          */
1328         while (test->reg) {
1329                 for (i = 0; i < test->array_len; i++) {
1330                         switch (test->test_type) {
1331                         case PATTERN_TEST:
1332                                 REG_PATTERN_TEST(test->reg +
1333                                                 (i * test->reg_offset),
1334                                                 test->mask,
1335                                                 test->write);
1336                                 break;
1337                         case SET_READ_TEST:
1338                                 REG_SET_AND_CHECK(test->reg +
1339                                                 (i * test->reg_offset),
1340                                                 test->mask,
1341                                                 test->write);
1342                                 break;
1343                         case WRITE_NO_TEST:
1344                                 writel(test->write,
1345                                     (adapter->hw.hw_addr + test->reg)
1346                                         + (i * test->reg_offset));
1347                                 break;
1348                         case TABLE32_TEST:
1349                                 REG_PATTERN_TEST(test->reg + (i * 4),
1350                                                 test->mask,
1351                                                 test->write);
1352                                 break;
1353                         case TABLE64_TEST_LO:
1354                                 REG_PATTERN_TEST(test->reg + (i * 8),
1355                                                 test->mask,
1356                                                 test->write);
1357                                 break;
1358                         case TABLE64_TEST_HI:
1359                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1360                                                 test->mask,
1361                                                 test->write);
1362                                 break;
1363                         }
1364                 }
1365                 test++;
1366         }
1367
1368         *data = 0;
1369         return 0;
1370 }
1371
1372 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1373 {
1374         struct e1000_hw *hw = &adapter->hw;
1375
1376         *data = 0;
1377
1378         /* Validate eeprom on all parts but flashless */
1379         switch (hw->mac.type) {
1380         case e1000_i210:
1381         case e1000_i211:
1382                 if (igb_get_flash_presence_i210(hw)) {
1383                         if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1384                                 *data = 2;
1385                 }
1386                 break;
1387         default:
1388                 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1389                         *data = 2;
1390                 break;
1391         }
1392
1393         return *data;
1394 }
1395
1396 static irqreturn_t igb_test_intr(int irq, void *data)
1397 {
1398         struct igb_adapter *adapter = (struct igb_adapter *) data;
1399         struct e1000_hw *hw = &adapter->hw;
1400
1401         adapter->test_icr |= rd32(E1000_ICR);
1402
1403         return IRQ_HANDLED;
1404 }
1405
1406 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1407 {
1408         struct e1000_hw *hw = &adapter->hw;
1409         struct net_device *netdev = adapter->netdev;
1410         u32 mask, ics_mask, i = 0, shared_int = true;
1411         u32 irq = adapter->pdev->irq;
1412
1413         *data = 0;
1414
1415         /* Hook up test interrupt handler just for this test */
1416         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1417                 if (request_irq(adapter->msix_entries[0].vector,
1418                                 igb_test_intr, 0, netdev->name, adapter)) {
1419                         *data = 1;
1420                         return -1;
1421                 }
1422                 wr32(E1000_IVAR_MISC, E1000_IVAR_VALID << 8);
1423                 wr32(E1000_EIMS, BIT(0));
1424         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1425                 shared_int = false;
1426                 if (request_irq(irq,
1427                                 igb_test_intr, 0, netdev->name, adapter)) {
1428                         *data = 1;
1429                         return -1;
1430                 }
1431         } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1432                                 netdev->name, adapter)) {
1433                 shared_int = false;
1434         } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1435                  netdev->name, adapter)) {
1436                 *data = 1;
1437                 return -1;
1438         }
1439         dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1440                 (shared_int ? "shared" : "unshared"));
1441
1442         /* Disable all the interrupts */
1443         wr32(E1000_IMC, ~0);
1444         wrfl();
1445         usleep_range(10000, 11000);
1446
1447         /* Define all writable bits for ICS */
1448         switch (hw->mac.type) {
1449         case e1000_82575:
1450                 ics_mask = 0x37F47EDD;
1451                 break;
1452         case e1000_82576:
1453                 ics_mask = 0x77D4FBFD;
1454                 break;
1455         case e1000_82580:
1456                 ics_mask = 0x77DCFED5;
1457                 break;
1458         case e1000_i350:
1459         case e1000_i354:
1460         case e1000_i210:
1461         case e1000_i211:
1462                 ics_mask = 0x77DCFED5;
1463                 break;
1464         default:
1465                 ics_mask = 0x7FFFFFFF;
1466                 break;
1467         }
1468
1469         /* Test each interrupt */
1470         for (; i < 31; i++) {
1471                 /* Interrupt to test */
1472                 mask = BIT(i);
1473
1474                 if (!(mask & ics_mask))
1475                         continue;
1476
1477                 if (!shared_int) {
1478                         /* Disable the interrupt to be reported in
1479                          * the cause register and then force the same
1480                          * interrupt and see if one gets posted.  If
1481                          * an interrupt was posted to the bus, the
1482                          * test failed.
1483                          */
1484                         adapter->test_icr = 0;
1485
1486                         /* Flush any pending interrupts */
1487                         wr32(E1000_ICR, ~0);
1488
1489                         wr32(E1000_IMC, mask);
1490                         wr32(E1000_ICS, mask);
1491                         wrfl();
1492                         usleep_range(10000, 11000);
1493
1494                         if (adapter->test_icr & mask) {
1495                                 *data = 3;
1496                                 break;
1497                         }
1498                 }
1499
1500                 /* Enable the interrupt to be reported in
1501                  * the cause register and then force the same
1502                  * interrupt and see if one gets posted.  If
1503                  * an interrupt was not posted to the bus, the
1504                  * test failed.
1505                  */
1506                 adapter->test_icr = 0;
1507
1508                 /* Flush any pending interrupts */
1509                 wr32(E1000_ICR, ~0);
1510
1511                 wr32(E1000_IMS, mask);
1512                 wr32(E1000_ICS, mask);
1513                 wrfl();
1514                 usleep_range(10000, 11000);
1515
1516                 if (!(adapter->test_icr & mask)) {
1517                         *data = 4;
1518                         break;
1519                 }
1520
1521                 if (!shared_int) {
1522                         /* Disable the other interrupts to be reported in
1523                          * the cause register and then force the other
1524                          * interrupts and see if any get posted.  If
1525                          * an interrupt was posted to the bus, the
1526                          * test failed.
1527                          */
1528                         adapter->test_icr = 0;
1529
1530                         /* Flush any pending interrupts */
1531                         wr32(E1000_ICR, ~0);
1532
1533                         wr32(E1000_IMC, ~mask);
1534                         wr32(E1000_ICS, ~mask);
1535                         wrfl();
1536                         usleep_range(10000, 11000);
1537
1538                         if (adapter->test_icr & mask) {
1539                                 *data = 5;
1540                                 break;
1541                         }
1542                 }
1543         }
1544
1545         /* Disable all the interrupts */
1546         wr32(E1000_IMC, ~0);
1547         wrfl();
1548         usleep_range(10000, 11000);
1549
1550         /* Unhook test interrupt handler */
1551         if (adapter->flags & IGB_FLAG_HAS_MSIX)
1552                 free_irq(adapter->msix_entries[0].vector, adapter);
1553         else
1554                 free_irq(irq, adapter);
1555
1556         return *data;
1557 }
1558
1559 static void igb_free_desc_rings(struct igb_adapter *adapter)
1560 {
1561         igb_free_tx_resources(&adapter->test_tx_ring);
1562         igb_free_rx_resources(&adapter->test_rx_ring);
1563 }
1564
1565 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1566 {
1567         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1568         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1569         struct e1000_hw *hw = &adapter->hw;
1570         int ret_val;
1571
1572         /* Setup Tx descriptor ring and Tx buffers */
1573         tx_ring->count = IGB_DEFAULT_TXD;
1574         tx_ring->dev = &adapter->pdev->dev;
1575         tx_ring->netdev = adapter->netdev;
1576         tx_ring->reg_idx = adapter->vfs_allocated_count;
1577
1578         if (igb_setup_tx_resources(tx_ring)) {
1579                 ret_val = 1;
1580                 goto err_nomem;
1581         }
1582
1583         igb_setup_tctl(adapter);
1584         igb_configure_tx_ring(adapter, tx_ring);
1585
1586         /* Setup Rx descriptor ring and Rx buffers */
1587         rx_ring->count = IGB_DEFAULT_RXD;
1588         rx_ring->dev = &adapter->pdev->dev;
1589         rx_ring->netdev = adapter->netdev;
1590         rx_ring->reg_idx = adapter->vfs_allocated_count;
1591
1592         if (igb_setup_rx_resources(rx_ring)) {
1593                 ret_val = 3;
1594                 goto err_nomem;
1595         }
1596
1597         /* set the default queue to queue 0 of PF */
1598         wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1599
1600         /* enable receive ring */
1601         igb_setup_rctl(adapter);
1602         igb_configure_rx_ring(adapter, rx_ring);
1603
1604         igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
1605
1606         return 0;
1607
1608 err_nomem:
1609         igb_free_desc_rings(adapter);
1610         return ret_val;
1611 }
1612
1613 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1614 {
1615         struct e1000_hw *hw = &adapter->hw;
1616
1617         /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1618         igb_write_phy_reg(hw, 29, 0x001F);
1619         igb_write_phy_reg(hw, 30, 0x8FFC);
1620         igb_write_phy_reg(hw, 29, 0x001A);
1621         igb_write_phy_reg(hw, 30, 0x8FF0);
1622 }
1623
1624 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1625 {
1626         struct e1000_hw *hw = &adapter->hw;
1627         u32 ctrl_reg = 0;
1628
1629         hw->mac.autoneg = false;
1630
1631         if (hw->phy.type == e1000_phy_m88) {
1632                 if (hw->phy.id != I210_I_PHY_ID) {
1633                         /* Auto-MDI/MDIX Off */
1634                         igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1635                         /* reset to update Auto-MDI/MDIX */
1636                         igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1637                         /* autoneg off */
1638                         igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1639                 } else {
1640                         /* force 1000, set loopback  */
1641                         igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1642                         igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1643                 }
1644         } else if (hw->phy.type == e1000_phy_82580) {
1645                 /* enable MII loopback */
1646                 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1647         }
1648
1649         /* add small delay to avoid loopback test failure */
1650         msleep(50);
1651
1652         /* force 1000, set loopback */
1653         igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1654
1655         /* Now set up the MAC to the same speed/duplex as the PHY. */
1656         ctrl_reg = rd32(E1000_CTRL);
1657         ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1658         ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1659                      E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1660                      E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1661                      E1000_CTRL_FD |     /* Force Duplex to FULL */
1662                      E1000_CTRL_SLU);    /* Set link up enable bit */
1663
1664         if (hw->phy.type == e1000_phy_m88)
1665                 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1666
1667         wr32(E1000_CTRL, ctrl_reg);
1668
1669         /* Disable the receiver on the PHY so when a cable is plugged in, the
1670          * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1671          */
1672         if (hw->phy.type == e1000_phy_m88)
1673                 igb_phy_disable_receiver(adapter);
1674
1675         mdelay(500);
1676         return 0;
1677 }
1678
1679 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1680 {
1681         return igb_integrated_phy_loopback(adapter);
1682 }
1683
1684 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1685 {
1686         struct e1000_hw *hw = &adapter->hw;
1687         u32 reg;
1688
1689         reg = rd32(E1000_CTRL_EXT);
1690
1691         /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1692         if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1693                 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1694                 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1695                 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1696                 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1697                 (hw->device_id == E1000_DEV_ID_I354_SGMII) ||
1698                 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) {
1699                         /* Enable DH89xxCC MPHY for near end loopback */
1700                         reg = rd32(E1000_MPHY_ADDR_CTL);
1701                         reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1702                         E1000_MPHY_PCS_CLK_REG_OFFSET;
1703                         wr32(E1000_MPHY_ADDR_CTL, reg);
1704
1705                         reg = rd32(E1000_MPHY_DATA);
1706                         reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1707                         wr32(E1000_MPHY_DATA, reg);
1708                 }
1709
1710                 reg = rd32(E1000_RCTL);
1711                 reg |= E1000_RCTL_LBM_TCVR;
1712                 wr32(E1000_RCTL, reg);
1713
1714                 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1715
1716                 reg = rd32(E1000_CTRL);
1717                 reg &= ~(E1000_CTRL_RFCE |
1718                          E1000_CTRL_TFCE |
1719                          E1000_CTRL_LRST);
1720                 reg |= E1000_CTRL_SLU |
1721                        E1000_CTRL_FD;
1722                 wr32(E1000_CTRL, reg);
1723
1724                 /* Unset switch control to serdes energy detect */
1725                 reg = rd32(E1000_CONNSW);
1726                 reg &= ~E1000_CONNSW_ENRGSRC;
1727                 wr32(E1000_CONNSW, reg);
1728
1729                 /* Unset sigdetect for SERDES loopback on
1730                  * 82580 and newer devices.
1731                  */
1732                 if (hw->mac.type >= e1000_82580) {
1733                         reg = rd32(E1000_PCS_CFG0);
1734                         reg |= E1000_PCS_CFG_IGN_SD;
1735                         wr32(E1000_PCS_CFG0, reg);
1736                 }
1737
1738                 /* Set PCS register for forced speed */
1739                 reg = rd32(E1000_PCS_LCTL);
1740                 reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
1741                 reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1742                        E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1743                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1744                        E1000_PCS_LCTL_FSD |           /* Force Speed */
1745                        E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1746                 wr32(E1000_PCS_LCTL, reg);
1747
1748                 return 0;
1749         }
1750
1751         return igb_set_phy_loopback(adapter);
1752 }
1753
1754 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1755 {
1756         struct e1000_hw *hw = &adapter->hw;
1757         u32 rctl;
1758         u16 phy_reg;
1759
1760         if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1761         (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1762         (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1763         (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1764         (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
1765                 u32 reg;
1766
1767                 /* Disable near end loopback on DH89xxCC */
1768                 reg = rd32(E1000_MPHY_ADDR_CTL);
1769                 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1770                 E1000_MPHY_PCS_CLK_REG_OFFSET;
1771                 wr32(E1000_MPHY_ADDR_CTL, reg);
1772
1773                 reg = rd32(E1000_MPHY_DATA);
1774                 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1775                 wr32(E1000_MPHY_DATA, reg);
1776         }
1777
1778         rctl = rd32(E1000_RCTL);
1779         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1780         wr32(E1000_RCTL, rctl);
1781
1782         hw->mac.autoneg = true;
1783         igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1784         if (phy_reg & MII_CR_LOOPBACK) {
1785                 phy_reg &= ~MII_CR_LOOPBACK;
1786                 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1787                 igb_phy_sw_reset(hw);
1788         }
1789 }
1790
1791 static void igb_create_lbtest_frame(struct sk_buff *skb,
1792                                     unsigned int frame_size)
1793 {
1794         memset(skb->data, 0xFF, frame_size);
1795         frame_size /= 2;
1796         memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1797         memset(&skb->data[frame_size + 10], 0xBE, 1);
1798         memset(&skb->data[frame_size + 12], 0xAF, 1);
1799 }
1800
1801 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1802                                   unsigned int frame_size)
1803 {
1804         unsigned char *data;
1805         bool match = true;
1806
1807         frame_size >>= 1;
1808
1809         data = kmap(rx_buffer->page);
1810
1811         if (data[3] != 0xFF ||
1812             data[frame_size + 10] != 0xBE ||
1813             data[frame_size + 12] != 0xAF)
1814                 match = false;
1815
1816         kunmap(rx_buffer->page);
1817
1818         return match;
1819 }
1820
1821 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1822                                 struct igb_ring *tx_ring,
1823                                 unsigned int size)
1824 {
1825         union e1000_adv_rx_desc *rx_desc;
1826         struct igb_rx_buffer *rx_buffer_info;
1827         struct igb_tx_buffer *tx_buffer_info;
1828         u16 rx_ntc, tx_ntc, count = 0;
1829
1830         /* initialize next to clean and descriptor values */
1831         rx_ntc = rx_ring->next_to_clean;
1832         tx_ntc = tx_ring->next_to_clean;
1833         rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1834
1835         while (rx_desc->wb.upper.length) {
1836                 /* check Rx buffer */
1837                 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1838
1839                 /* sync Rx buffer for CPU read */
1840                 dma_sync_single_for_cpu(rx_ring->dev,
1841                                         rx_buffer_info->dma,
1842                                         size,
1843                                         DMA_FROM_DEVICE);
1844
1845                 /* verify contents of skb */
1846                 if (igb_check_lbtest_frame(rx_buffer_info, size))
1847                         count++;
1848
1849                 /* sync Rx buffer for device write */
1850                 dma_sync_single_for_device(rx_ring->dev,
1851                                            rx_buffer_info->dma,
1852                                            size,
1853                                            DMA_FROM_DEVICE);
1854
1855                 /* unmap buffer on Tx side */
1856                 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1857
1858                 /* Free all the Tx ring sk_buffs */
1859                 dev_kfree_skb_any(tx_buffer_info->skb);
1860
1861                 /* unmap skb header data */
1862                 dma_unmap_single(tx_ring->dev,
1863                                  dma_unmap_addr(tx_buffer_info, dma),
1864                                  dma_unmap_len(tx_buffer_info, len),
1865                                  DMA_TO_DEVICE);
1866                 dma_unmap_len_set(tx_buffer_info, len, 0);
1867
1868                 /* increment Rx/Tx next to clean counters */
1869                 rx_ntc++;
1870                 if (rx_ntc == rx_ring->count)
1871                         rx_ntc = 0;
1872                 tx_ntc++;
1873                 if (tx_ntc == tx_ring->count)
1874                         tx_ntc = 0;
1875
1876                 /* fetch next descriptor */
1877                 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1878         }
1879
1880         netdev_tx_reset_queue(txring_txq(tx_ring));
1881
1882         /* re-map buffers to ring, store next to clean values */
1883         igb_alloc_rx_buffers(rx_ring, count);
1884         rx_ring->next_to_clean = rx_ntc;
1885         tx_ring->next_to_clean = tx_ntc;
1886
1887         return count;
1888 }
1889
1890 static int igb_run_loopback_test(struct igb_adapter *adapter)
1891 {
1892         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1893         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1894         u16 i, j, lc, good_cnt;
1895         int ret_val = 0;
1896         unsigned int size = IGB_RX_HDR_LEN;
1897         netdev_tx_t tx_ret_val;
1898         struct sk_buff *skb;
1899
1900         /* allocate test skb */
1901         skb = alloc_skb(size, GFP_KERNEL);
1902         if (!skb)
1903                 return 11;
1904
1905         /* place data into test skb */
1906         igb_create_lbtest_frame(skb, size);
1907         skb_put(skb, size);
1908
1909         /* Calculate the loop count based on the largest descriptor ring
1910          * The idea is to wrap the largest ring a number of times using 64
1911          * send/receive pairs during each loop
1912          */
1913
1914         if (rx_ring->count <= tx_ring->count)
1915                 lc = ((tx_ring->count / 64) * 2) + 1;
1916         else
1917                 lc = ((rx_ring->count / 64) * 2) + 1;
1918
1919         for (j = 0; j <= lc; j++) { /* loop count loop */
1920                 /* reset count of good packets */
1921                 good_cnt = 0;
1922
1923                 /* place 64 packets on the transmit queue*/
1924                 for (i = 0; i < 64; i++) {
1925                         skb_get(skb);
1926                         tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
1927                         if (tx_ret_val == NETDEV_TX_OK)
1928                                 good_cnt++;
1929                 }
1930
1931                 if (good_cnt != 64) {
1932                         ret_val = 12;
1933                         break;
1934                 }
1935
1936                 /* allow 200 milliseconds for packets to go from Tx to Rx */
1937                 msleep(200);
1938
1939                 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1940                 if (good_cnt != 64) {
1941                         ret_val = 13;
1942                         break;
1943                 }
1944         } /* end loop count loop */
1945
1946         /* free the original skb */
1947         kfree_skb(skb);
1948
1949         return ret_val;
1950 }
1951
1952 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1953 {
1954         /* PHY loopback cannot be performed if SoL/IDER
1955          * sessions are active
1956          */
1957         if (igb_check_reset_block(&adapter->hw)) {
1958                 dev_err(&adapter->pdev->dev,
1959                         "Cannot do PHY loopback test when SoL/IDER is active.\n");
1960                 *data = 0;
1961                 goto out;
1962         }
1963
1964         if (adapter->hw.mac.type == e1000_i354) {
1965                 dev_info(&adapter->pdev->dev,
1966                         "Loopback test not supported on i354.\n");
1967                 *data = 0;
1968                 goto out;
1969         }
1970         *data = igb_setup_desc_rings(adapter);
1971         if (*data)
1972                 goto out;
1973         *data = igb_setup_loopback_test(adapter);
1974         if (*data)
1975                 goto err_loopback;
1976         *data = igb_run_loopback_test(adapter);
1977         igb_loopback_cleanup(adapter);
1978
1979 err_loopback:
1980         igb_free_desc_rings(adapter);
1981 out:
1982         return *data;
1983 }
1984
1985 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1986 {
1987         struct e1000_hw *hw = &adapter->hw;
1988         *data = 0;
1989         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1990                 int i = 0;
1991
1992                 hw->mac.serdes_has_link = false;
1993
1994                 /* On some blade server designs, link establishment
1995                  * could take as long as 2-3 minutes
1996                  */
1997                 do {
1998                         hw->mac.ops.check_for_link(&adapter->hw);
1999                         if (hw->mac.serdes_has_link)
2000                                 return *data;
2001                         msleep(20);
2002                 } while (i++ < 3750);
2003
2004                 *data = 1;
2005         } else {
2006                 hw->mac.ops.check_for_link(&adapter->hw);
2007                 if (hw->mac.autoneg)
2008                         msleep(5000);
2009
2010                 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
2011                         *data = 1;
2012         }
2013         return *data;
2014 }
2015
2016 static void igb_diag_test(struct net_device *netdev,
2017                           struct ethtool_test *eth_test, u64 *data)
2018 {
2019         struct igb_adapter *adapter = netdev_priv(netdev);
2020         u16 autoneg_advertised;
2021         u8 forced_speed_duplex, autoneg;
2022         bool if_running = netif_running(netdev);
2023
2024         set_bit(__IGB_TESTING, &adapter->state);
2025
2026         /* can't do offline tests on media switching devices */
2027         if (adapter->hw.dev_spec._82575.mas_capable)
2028                 eth_test->flags &= ~ETH_TEST_FL_OFFLINE;
2029         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2030                 /* Offline tests */
2031
2032                 /* save speed, duplex, autoneg settings */
2033                 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
2034                 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
2035                 autoneg = adapter->hw.mac.autoneg;
2036
2037                 dev_info(&adapter->pdev->dev, "offline testing starting\n");
2038
2039                 /* power up link for link test */
2040                 igb_power_up_link(adapter);
2041
2042                 /* Link test performed before hardware reset so autoneg doesn't
2043                  * interfere with test result
2044                  */
2045                 if (igb_link_test(adapter, &data[TEST_LINK]))
2046                         eth_test->flags |= ETH_TEST_FL_FAILED;
2047
2048                 if (if_running)
2049                         /* indicate we're in test mode */
2050                         igb_close(netdev);
2051                 else
2052                         igb_reset(adapter);
2053
2054                 if (igb_reg_test(adapter, &data[TEST_REG]))
2055                         eth_test->flags |= ETH_TEST_FL_FAILED;
2056
2057                 igb_reset(adapter);
2058                 if (igb_eeprom_test(adapter, &data[TEST_EEP]))
2059                         eth_test->flags |= ETH_TEST_FL_FAILED;
2060
2061                 igb_reset(adapter);
2062                 if (igb_intr_test(adapter, &data[TEST_IRQ]))
2063                         eth_test->flags |= ETH_TEST_FL_FAILED;
2064
2065                 igb_reset(adapter);
2066                 /* power up link for loopback test */
2067                 igb_power_up_link(adapter);
2068                 if (igb_loopback_test(adapter, &data[TEST_LOOP]))
2069                         eth_test->flags |= ETH_TEST_FL_FAILED;
2070
2071                 /* restore speed, duplex, autoneg settings */
2072                 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
2073                 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
2074                 adapter->hw.mac.autoneg = autoneg;
2075
2076                 /* force this routine to wait until autoneg complete/timeout */
2077                 adapter->hw.phy.autoneg_wait_to_complete = true;
2078                 igb_reset(adapter);
2079                 adapter->hw.phy.autoneg_wait_to_complete = false;
2080
2081                 clear_bit(__IGB_TESTING, &adapter->state);
2082                 if (if_running)
2083                         igb_open(netdev);
2084         } else {
2085                 dev_info(&adapter->pdev->dev, "online testing starting\n");
2086
2087                 /* PHY is powered down when interface is down */
2088                 if (if_running && igb_link_test(adapter, &data[TEST_LINK]))
2089                         eth_test->flags |= ETH_TEST_FL_FAILED;
2090                 else
2091                         data[TEST_LINK] = 0;
2092
2093                 /* Online tests aren't run; pass by default */
2094                 data[TEST_REG] = 0;
2095                 data[TEST_EEP] = 0;
2096                 data[TEST_IRQ] = 0;
2097                 data[TEST_LOOP] = 0;
2098
2099                 clear_bit(__IGB_TESTING, &adapter->state);
2100         }
2101         msleep_interruptible(4 * 1000);
2102 }
2103
2104 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2105 {
2106         struct igb_adapter *adapter = netdev_priv(netdev);
2107
2108         wol->wolopts = 0;
2109
2110         if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2111                 return;
2112
2113         wol->supported = WAKE_UCAST | WAKE_MCAST |
2114                          WAKE_BCAST | WAKE_MAGIC |
2115                          WAKE_PHY;
2116
2117         /* apply any specific unsupported masks here */
2118         switch (adapter->hw.device_id) {
2119         default:
2120                 break;
2121         }
2122
2123         if (adapter->wol & E1000_WUFC_EX)
2124                 wol->wolopts |= WAKE_UCAST;
2125         if (adapter->wol & E1000_WUFC_MC)
2126                 wol->wolopts |= WAKE_MCAST;
2127         if (adapter->wol & E1000_WUFC_BC)
2128                 wol->wolopts |= WAKE_BCAST;
2129         if (adapter->wol & E1000_WUFC_MAG)
2130                 wol->wolopts |= WAKE_MAGIC;
2131         if (adapter->wol & E1000_WUFC_LNKC)
2132                 wol->wolopts |= WAKE_PHY;
2133 }
2134
2135 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2136 {
2137         struct igb_adapter *adapter = netdev_priv(netdev);
2138
2139         if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2140                 return -EOPNOTSUPP;
2141
2142         if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2143                 return wol->wolopts ? -EOPNOTSUPP : 0;
2144
2145         /* these settings will always override what we currently have */
2146         adapter->wol = 0;
2147
2148         if (wol->wolopts & WAKE_UCAST)
2149                 adapter->wol |= E1000_WUFC_EX;
2150         if (wol->wolopts & WAKE_MCAST)
2151                 adapter->wol |= E1000_WUFC_MC;
2152         if (wol->wolopts & WAKE_BCAST)
2153                 adapter->wol |= E1000_WUFC_BC;
2154         if (wol->wolopts & WAKE_MAGIC)
2155                 adapter->wol |= E1000_WUFC_MAG;
2156         if (wol->wolopts & WAKE_PHY)
2157                 adapter->wol |= E1000_WUFC_LNKC;
2158         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2159
2160         return 0;
2161 }
2162
2163 /* bit defines for adapter->led_status */
2164 #define IGB_LED_ON              0
2165
2166 static int igb_set_phys_id(struct net_device *netdev,
2167                            enum ethtool_phys_id_state state)
2168 {
2169         struct igb_adapter *adapter = netdev_priv(netdev);
2170         struct e1000_hw *hw = &adapter->hw;
2171
2172         switch (state) {
2173         case ETHTOOL_ID_ACTIVE:
2174                 igb_blink_led(hw);
2175                 return 2;
2176         case ETHTOOL_ID_ON:
2177                 igb_blink_led(hw);
2178                 break;
2179         case ETHTOOL_ID_OFF:
2180                 igb_led_off(hw);
2181                 break;
2182         case ETHTOOL_ID_INACTIVE:
2183                 igb_led_off(hw);
2184                 clear_bit(IGB_LED_ON, &adapter->led_status);
2185                 igb_cleanup_led(hw);
2186                 break;
2187         }
2188
2189         return 0;
2190 }
2191
2192 static int igb_set_coalesce(struct net_device *netdev,
2193                             struct ethtool_coalesce *ec)
2194 {
2195         struct igb_adapter *adapter = netdev_priv(netdev);
2196         int i;
2197
2198         if (ec->rx_max_coalesced_frames ||
2199             ec->rx_coalesce_usecs_irq ||
2200             ec->rx_max_coalesced_frames_irq ||
2201             ec->tx_max_coalesced_frames ||
2202             ec->tx_coalesce_usecs_irq ||
2203             ec->stats_block_coalesce_usecs ||
2204             ec->use_adaptive_rx_coalesce ||
2205             ec->use_adaptive_tx_coalesce ||
2206             ec->pkt_rate_low ||
2207             ec->rx_coalesce_usecs_low ||
2208             ec->rx_max_coalesced_frames_low ||
2209             ec->tx_coalesce_usecs_low ||
2210             ec->tx_max_coalesced_frames_low ||
2211             ec->pkt_rate_high ||
2212             ec->rx_coalesce_usecs_high ||
2213             ec->rx_max_coalesced_frames_high ||
2214             ec->tx_coalesce_usecs_high ||
2215             ec->tx_max_coalesced_frames_high ||
2216             ec->rate_sample_interval)
2217                 return -ENOTSUPP;
2218
2219         if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2220             ((ec->rx_coalesce_usecs > 3) &&
2221              (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2222             (ec->rx_coalesce_usecs == 2))
2223                 return -EINVAL;
2224
2225         if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2226             ((ec->tx_coalesce_usecs > 3) &&
2227              (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2228             (ec->tx_coalesce_usecs == 2))
2229                 return -EINVAL;
2230
2231         if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2232                 return -EINVAL;
2233
2234         /* If ITR is disabled, disable DMAC */
2235         if (ec->rx_coalesce_usecs == 0) {
2236                 if (adapter->flags & IGB_FLAG_DMAC)
2237                         adapter->flags &= ~IGB_FLAG_DMAC;
2238         }
2239
2240         /* convert to rate of irq's per second */
2241         if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2242                 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2243         else
2244                 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2245
2246         /* convert to rate of irq's per second */
2247         if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2248                 adapter->tx_itr_setting = adapter->rx_itr_setting;
2249         else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2250                 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2251         else
2252                 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2253
2254         for (i = 0; i < adapter->num_q_vectors; i++) {
2255                 struct igb_q_vector *q_vector = adapter->q_vector[i];
2256                 q_vector->tx.work_limit = adapter->tx_work_limit;
2257                 if (q_vector->rx.ring)
2258                         q_vector->itr_val = adapter->rx_itr_setting;
2259                 else
2260                         q_vector->itr_val = adapter->tx_itr_setting;
2261                 if (q_vector->itr_val && q_vector->itr_val <= 3)
2262                         q_vector->itr_val = IGB_START_ITR;
2263                 q_vector->set_itr = 1;
2264         }
2265
2266         return 0;
2267 }
2268
2269 static int igb_get_coalesce(struct net_device *netdev,
2270                             struct ethtool_coalesce *ec)
2271 {
2272         struct igb_adapter *adapter = netdev_priv(netdev);
2273
2274         if (adapter->rx_itr_setting <= 3)
2275                 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2276         else
2277                 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2278
2279         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2280                 if (adapter->tx_itr_setting <= 3)
2281                         ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2282                 else
2283                         ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2284         }
2285
2286         return 0;
2287 }
2288
2289 static int igb_nway_reset(struct net_device *netdev)
2290 {
2291         struct igb_adapter *adapter = netdev_priv(netdev);
2292         if (netif_running(netdev))
2293                 igb_reinit_locked(adapter);
2294         return 0;
2295 }
2296
2297 static int igb_get_sset_count(struct net_device *netdev, int sset)
2298 {
2299         switch (sset) {
2300         case ETH_SS_STATS:
2301                 return IGB_STATS_LEN;
2302         case ETH_SS_TEST:
2303                 return IGB_TEST_LEN;
2304         case ETH_SS_PRIV_FLAGS:
2305                 return IGB_PRIV_FLAGS_STR_LEN;
2306         default:
2307                 return -ENOTSUPP;
2308         }
2309 }
2310
2311 static void igb_get_ethtool_stats(struct net_device *netdev,
2312                                   struct ethtool_stats *stats, u64 *data)
2313 {
2314         struct igb_adapter *adapter = netdev_priv(netdev);
2315         struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2316         unsigned int start;
2317         struct igb_ring *ring;
2318         int i, j;
2319         char *p;
2320
2321         spin_lock(&adapter->stats64_lock);
2322         igb_update_stats(adapter);
2323
2324         for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2325                 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2326                 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2327                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2328         }
2329         for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2330                 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2331                 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2332                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2333         }
2334         for (j = 0; j < adapter->num_tx_queues; j++) {
2335                 u64     restart2;
2336
2337                 ring = adapter->tx_ring[j];
2338                 do {
2339                         start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
2340                         data[i]   = ring->tx_stats.packets;
2341                         data[i+1] = ring->tx_stats.bytes;
2342                         data[i+2] = ring->tx_stats.restart_queue;
2343                 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
2344                 do {
2345                         start = u64_stats_fetch_begin_irq(&ring->tx_syncp2);
2346                         restart2  = ring->tx_stats.restart_queue2;
2347                 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start));
2348                 data[i+2] += restart2;
2349
2350                 i += IGB_TX_QUEUE_STATS_LEN;
2351         }
2352         for (j = 0; j < adapter->num_rx_queues; j++) {
2353                 ring = adapter->rx_ring[j];
2354                 do {
2355                         start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
2356                         data[i]   = ring->rx_stats.packets;
2357                         data[i+1] = ring->rx_stats.bytes;
2358                         data[i+2] = ring->rx_stats.drops;
2359                         data[i+3] = ring->rx_stats.csum_err;
2360                         data[i+4] = ring->rx_stats.alloc_failed;
2361                 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
2362                 i += IGB_RX_QUEUE_STATS_LEN;
2363         }
2364         spin_unlock(&adapter->stats64_lock);
2365 }
2366
2367 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2368 {
2369         struct igb_adapter *adapter = netdev_priv(netdev);
2370         u8 *p = data;
2371         int i;
2372
2373         switch (stringset) {
2374         case ETH_SS_TEST:
2375                 memcpy(data, *igb_gstrings_test,
2376                         IGB_TEST_LEN*ETH_GSTRING_LEN);
2377                 break;
2378         case ETH_SS_STATS:
2379                 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2380                         memcpy(p, igb_gstrings_stats[i].stat_string,
2381                                ETH_GSTRING_LEN);
2382                         p += ETH_GSTRING_LEN;
2383                 }
2384                 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2385                         memcpy(p, igb_gstrings_net_stats[i].stat_string,
2386                                ETH_GSTRING_LEN);
2387                         p += ETH_GSTRING_LEN;
2388                 }
2389                 for (i = 0; i < adapter->num_tx_queues; i++) {
2390                         sprintf(p, "tx_queue_%u_packets", i);
2391                         p += ETH_GSTRING_LEN;
2392                         sprintf(p, "tx_queue_%u_bytes", i);
2393                         p += ETH_GSTRING_LEN;
2394                         sprintf(p, "tx_queue_%u_restart", i);
2395                         p += ETH_GSTRING_LEN;
2396                 }
2397                 for (i = 0; i < adapter->num_rx_queues; i++) {
2398                         sprintf(p, "rx_queue_%u_packets", i);
2399                         p += ETH_GSTRING_LEN;
2400                         sprintf(p, "rx_queue_%u_bytes", i);
2401                         p += ETH_GSTRING_LEN;
2402                         sprintf(p, "rx_queue_%u_drops", i);
2403                         p += ETH_GSTRING_LEN;
2404                         sprintf(p, "rx_queue_%u_csum_err", i);
2405                         p += ETH_GSTRING_LEN;
2406                         sprintf(p, "rx_queue_%u_alloc_failed", i);
2407                         p += ETH_GSTRING_LEN;
2408                 }
2409                 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2410                 break;
2411         case ETH_SS_PRIV_FLAGS:
2412                 memcpy(data, igb_priv_flags_strings,
2413                        IGB_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN);
2414                 break;
2415         }
2416 }
2417
2418 static int igb_get_ts_info(struct net_device *dev,
2419                            struct ethtool_ts_info *info)
2420 {
2421         struct igb_adapter *adapter = netdev_priv(dev);
2422
2423         if (adapter->ptp_clock)
2424                 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2425         else
2426                 info->phc_index = -1;
2427
2428         switch (adapter->hw.mac.type) {
2429         case e1000_82575:
2430                 info->so_timestamping =
2431                         SOF_TIMESTAMPING_TX_SOFTWARE |
2432                         SOF_TIMESTAMPING_RX_SOFTWARE |
2433                         SOF_TIMESTAMPING_SOFTWARE;
2434                 return 0;
2435         case e1000_82576:
2436         case e1000_82580:
2437         case e1000_i350:
2438         case e1000_i354:
2439         case e1000_i210:
2440         case e1000_i211:
2441                 info->so_timestamping =
2442                         SOF_TIMESTAMPING_TX_SOFTWARE |
2443                         SOF_TIMESTAMPING_RX_SOFTWARE |
2444                         SOF_TIMESTAMPING_SOFTWARE |
2445                         SOF_TIMESTAMPING_TX_HARDWARE |
2446                         SOF_TIMESTAMPING_RX_HARDWARE |
2447                         SOF_TIMESTAMPING_RAW_HARDWARE;
2448
2449                 info->tx_types =
2450                         BIT(HWTSTAMP_TX_OFF) |
2451                         BIT(HWTSTAMP_TX_ON);
2452
2453                 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
2454
2455                 /* 82576 does not support timestamping all packets. */
2456                 if (adapter->hw.mac.type >= e1000_82580)
2457                         info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
2458                 else
2459                         info->rx_filters |=
2460                                 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2461                                 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2462                                 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
2463
2464                 return 0;
2465         default:
2466                 return -EOPNOTSUPP;
2467         }
2468 }
2469
2470 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2471 static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter,
2472                                      struct ethtool_rxnfc *cmd)
2473 {
2474         struct ethtool_rx_flow_spec *fsp = &cmd->fs;
2475         struct igb_nfc_filter *rule = NULL;
2476
2477         /* report total rule count */
2478         cmd->data = IGB_MAX_RXNFC_FILTERS;
2479
2480         hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2481                 if (fsp->location <= rule->sw_idx)
2482                         break;
2483         }
2484
2485         if (!rule || fsp->location != rule->sw_idx)
2486                 return -EINVAL;
2487
2488         if (rule->filter.match_flags) {
2489                 fsp->flow_type = ETHER_FLOW;
2490                 fsp->ring_cookie = rule->action;
2491                 if (rule->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {
2492                         fsp->h_u.ether_spec.h_proto = rule->filter.etype;
2493                         fsp->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK;
2494                 }
2495                 if (rule->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) {
2496                         fsp->flow_type |= FLOW_EXT;
2497                         fsp->h_ext.vlan_tci = rule->filter.vlan_tci;
2498                         fsp->m_ext.vlan_tci = htons(VLAN_PRIO_MASK);
2499                 }
2500                 return 0;
2501         }
2502         return -EINVAL;
2503 }
2504
2505 static int igb_get_ethtool_nfc_all(struct igb_adapter *adapter,
2506                                    struct ethtool_rxnfc *cmd,
2507                                    u32 *rule_locs)
2508 {
2509         struct igb_nfc_filter *rule;
2510         int cnt = 0;
2511
2512         /* report total rule count */
2513         cmd->data = IGB_MAX_RXNFC_FILTERS;
2514
2515         hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2516                 if (cnt == cmd->rule_cnt)
2517                         return -EMSGSIZE;
2518                 rule_locs[cnt] = rule->sw_idx;
2519                 cnt++;
2520         }
2521
2522         cmd->rule_cnt = cnt;
2523
2524         return 0;
2525 }
2526
2527 static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2528                                  struct ethtool_rxnfc *cmd)
2529 {
2530         cmd->data = 0;
2531
2532         /* Report default options for RSS on igb */
2533         switch (cmd->flow_type) {
2534         case TCP_V4_FLOW:
2535                 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2536                 /* Fall through */
2537         case UDP_V4_FLOW:
2538                 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2539                         cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2540                 /* Fall through */
2541         case SCTP_V4_FLOW:
2542         case AH_ESP_V4_FLOW:
2543         case AH_V4_FLOW:
2544         case ESP_V4_FLOW:
2545         case IPV4_FLOW:
2546                 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2547                 break;
2548         case TCP_V6_FLOW:
2549                 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2550                 /* Fall through */
2551         case UDP_V6_FLOW:
2552                 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2553                         cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2554                 /* Fall through */
2555         case SCTP_V6_FLOW:
2556         case AH_ESP_V6_FLOW:
2557         case AH_V6_FLOW:
2558         case ESP_V6_FLOW:
2559         case IPV6_FLOW:
2560                 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2561                 break;
2562         default:
2563                 return -EINVAL;
2564         }
2565
2566         return 0;
2567 }
2568
2569 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2570                          u32 *rule_locs)
2571 {
2572         struct igb_adapter *adapter = netdev_priv(dev);
2573         int ret = -EOPNOTSUPP;
2574
2575         switch (cmd->cmd) {
2576         case ETHTOOL_GRXRINGS:
2577                 cmd->data = adapter->num_rx_queues;
2578                 ret = 0;
2579                 break;
2580         case ETHTOOL_GRXCLSRLCNT:
2581                 cmd->rule_cnt = adapter->nfc_filter_count;
2582                 ret = 0;
2583                 break;
2584         case ETHTOOL_GRXCLSRULE:
2585                 ret = igb_get_ethtool_nfc_entry(adapter, cmd);
2586                 break;
2587         case ETHTOOL_GRXCLSRLALL:
2588                 ret = igb_get_ethtool_nfc_all(adapter, cmd, rule_locs);
2589                 break;
2590         case ETHTOOL_GRXFH:
2591                 ret = igb_get_rss_hash_opts(adapter, cmd);
2592                 break;
2593         default:
2594                 break;
2595         }
2596
2597         return ret;
2598 }
2599
2600 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2601                        IGB_FLAG_RSS_FIELD_IPV6_UDP)
2602 static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2603                                 struct ethtool_rxnfc *nfc)
2604 {
2605         u32 flags = adapter->flags;
2606
2607         /* RSS does not support anything other than hashing
2608          * to queues on src and dst IPs and ports
2609          */
2610         if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2611                           RXH_L4_B_0_1 | RXH_L4_B_2_3))
2612                 return -EINVAL;
2613
2614         switch (nfc->flow_type) {
2615         case TCP_V4_FLOW:
2616         case TCP_V6_FLOW:
2617                 if (!(nfc->data & RXH_IP_SRC) ||
2618                     !(nfc->data & RXH_IP_DST) ||
2619                     !(nfc->data & RXH_L4_B_0_1) ||
2620                     !(nfc->data & RXH_L4_B_2_3))
2621                         return -EINVAL;
2622                 break;
2623         case UDP_V4_FLOW:
2624                 if (!(nfc->data & RXH_IP_SRC) ||
2625                     !(nfc->data & RXH_IP_DST))
2626                         return -EINVAL;
2627                 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2628                 case 0:
2629                         flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2630                         break;
2631                 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2632                         flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2633                         break;
2634                 default:
2635                         return -EINVAL;
2636                 }
2637                 break;
2638         case UDP_V6_FLOW:
2639                 if (!(nfc->data & RXH_IP_SRC) ||
2640                     !(nfc->data & RXH_IP_DST))
2641                         return -EINVAL;
2642                 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2643                 case 0:
2644                         flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2645                         break;
2646                 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2647                         flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2648                         break;
2649                 default:
2650                         return -EINVAL;
2651                 }
2652                 break;
2653         case AH_ESP_V4_FLOW:
2654         case AH_V4_FLOW:
2655         case ESP_V4_FLOW:
2656         case SCTP_V4_FLOW:
2657         case AH_ESP_V6_FLOW:
2658         case AH_V6_FLOW:
2659         case ESP_V6_FLOW:
2660         case SCTP_V6_FLOW:
2661                 if (!(nfc->data & RXH_IP_SRC) ||
2662                     !(nfc->data & RXH_IP_DST) ||
2663                     (nfc->data & RXH_L4_B_0_1) ||
2664                     (nfc->data & RXH_L4_B_2_3))
2665                         return -EINVAL;
2666                 break;
2667         default:
2668                 return -EINVAL;
2669         }
2670
2671         /* if we changed something we need to update flags */
2672         if (flags != adapter->flags) {
2673                 struct e1000_hw *hw = &adapter->hw;
2674                 u32 mrqc = rd32(E1000_MRQC);
2675
2676                 if ((flags & UDP_RSS_FLAGS) &&
2677                     !(adapter->flags & UDP_RSS_FLAGS))
2678                         dev_err(&adapter->pdev->dev,
2679                                 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2680
2681                 adapter->flags = flags;
2682
2683                 /* Perform hash on these packet types */
2684                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2685                         E1000_MRQC_RSS_FIELD_IPV4_TCP |
2686                         E1000_MRQC_RSS_FIELD_IPV6 |
2687                         E1000_MRQC_RSS_FIELD_IPV6_TCP;
2688
2689                 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2690                           E1000_MRQC_RSS_FIELD_IPV6_UDP);
2691
2692                 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2693                         mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2694
2695                 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2696                         mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2697
2698                 wr32(E1000_MRQC, mrqc);
2699         }
2700
2701         return 0;
2702 }
2703
2704 static int igb_rxnfc_write_etype_filter(struct igb_adapter *adapter,
2705                                         struct igb_nfc_filter *input)
2706 {
2707         struct e1000_hw *hw = &adapter->hw;
2708         u8 i;
2709         u32 etqf;
2710         u16 etype;
2711
2712         /* find an empty etype filter register */
2713         for (i = 0; i < MAX_ETYPE_FILTER; ++i) {
2714                 if (!adapter->etype_bitmap[i])
2715                         break;
2716         }
2717         if (i == MAX_ETYPE_FILTER) {
2718                 dev_err(&adapter->pdev->dev, "ethtool -N: etype filters are all used.\n");
2719                 return -EINVAL;
2720         }
2721
2722         adapter->etype_bitmap[i] = true;
2723
2724         etqf = rd32(E1000_ETQF(i));
2725         etype = ntohs(input->filter.etype & ETHER_TYPE_FULL_MASK);
2726
2727         etqf |= E1000_ETQF_FILTER_ENABLE;
2728         etqf &= ~E1000_ETQF_ETYPE_MASK;
2729         etqf |= (etype & E1000_ETQF_ETYPE_MASK);
2730
2731         etqf &= ~E1000_ETQF_QUEUE_MASK;
2732         etqf |= ((input->action << E1000_ETQF_QUEUE_SHIFT)
2733                 & E1000_ETQF_QUEUE_MASK);
2734         etqf |= E1000_ETQF_QUEUE_ENABLE;
2735
2736         wr32(E1000_ETQF(i), etqf);
2737
2738         input->etype_reg_index = i;
2739
2740         return 0;
2741 }
2742
2743 static int igb_rxnfc_write_vlan_prio_filter(struct igb_adapter *adapter,
2744                                             struct igb_nfc_filter *input)
2745 {
2746         struct e1000_hw *hw = &adapter->hw;
2747         u8 vlan_priority;
2748         u16 queue_index;
2749         u32 vlapqf;
2750
2751         vlapqf = rd32(E1000_VLAPQF);
2752         vlan_priority = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK)
2753                                 >> VLAN_PRIO_SHIFT;
2754         queue_index = (vlapqf >> (vlan_priority * 4)) & E1000_VLAPQF_QUEUE_MASK;
2755
2756         /* check whether this vlan prio is already set */
2757         if ((vlapqf & E1000_VLAPQF_P_VALID(vlan_priority)) &&
2758             (queue_index != input->action)) {
2759                 dev_err(&adapter->pdev->dev, "ethtool rxnfc set vlan prio filter failed.\n");
2760                 return -EEXIST;
2761         }
2762
2763         vlapqf |= E1000_VLAPQF_P_VALID(vlan_priority);
2764         vlapqf |= E1000_VLAPQF_QUEUE_SEL(vlan_priority, input->action);
2765
2766         wr32(E1000_VLAPQF, vlapqf);
2767
2768         return 0;
2769 }
2770
2771 int igb_add_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)
2772 {
2773         int err = -EINVAL;
2774
2775         if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {
2776                 err = igb_rxnfc_write_etype_filter(adapter, input);
2777                 if (err)
2778                         return err;
2779         }
2780
2781         if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)
2782                 err = igb_rxnfc_write_vlan_prio_filter(adapter, input);
2783
2784         return err;
2785 }
2786
2787 static void igb_clear_etype_filter_regs(struct igb_adapter *adapter,
2788                                         u16 reg_index)
2789 {
2790         struct e1000_hw *hw = &adapter->hw;
2791         u32 etqf = rd32(E1000_ETQF(reg_index));
2792
2793         etqf &= ~E1000_ETQF_QUEUE_ENABLE;
2794         etqf &= ~E1000_ETQF_QUEUE_MASK;
2795         etqf &= ~E1000_ETQF_FILTER_ENABLE;
2796
2797         wr32(E1000_ETQF(reg_index), etqf);
2798
2799         adapter->etype_bitmap[reg_index] = false;
2800 }
2801
2802 static void igb_clear_vlan_prio_filter(struct igb_adapter *adapter,
2803                                        u16 vlan_tci)
2804 {
2805         struct e1000_hw *hw = &adapter->hw;
2806         u8 vlan_priority;
2807         u32 vlapqf;
2808
2809         vlan_priority = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
2810
2811         vlapqf = rd32(E1000_VLAPQF);
2812         vlapqf &= ~E1000_VLAPQF_P_VALID(vlan_priority);
2813         vlapqf &= ~E1000_VLAPQF_QUEUE_SEL(vlan_priority,
2814                                                 E1000_VLAPQF_QUEUE_MASK);
2815
2816         wr32(E1000_VLAPQF, vlapqf);
2817 }
2818
2819 int igb_erase_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)
2820 {
2821         if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE)
2822                 igb_clear_etype_filter_regs(adapter,
2823                                             input->etype_reg_index);
2824
2825         if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)
2826                 igb_clear_vlan_prio_filter(adapter,
2827                                            ntohs(input->filter.vlan_tci));
2828
2829         return 0;
2830 }
2831
2832 static int igb_update_ethtool_nfc_entry(struct igb_adapter *adapter,
2833                                         struct igb_nfc_filter *input,
2834                                         u16 sw_idx)
2835 {
2836         struct igb_nfc_filter *rule, *parent;
2837         int err = -EINVAL;
2838
2839         parent = NULL;
2840         rule = NULL;
2841
2842         hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2843                 /* hash found, or no matching entry */
2844                 if (rule->sw_idx >= sw_idx)
2845                         break;
2846                 parent = rule;
2847         }
2848
2849         /* if there is an old rule occupying our place remove it */
2850         if (rule && (rule->sw_idx == sw_idx)) {
2851                 if (!input)
2852                         err = igb_erase_filter(adapter, rule);
2853
2854                 hlist_del(&rule->nfc_node);
2855                 kfree(rule);
2856                 adapter->nfc_filter_count--;
2857         }
2858
2859         /* If no input this was a delete, err should be 0 if a rule was
2860          * successfully found and removed from the list else -EINVAL
2861          */
2862         if (!input)
2863                 return err;
2864
2865         /* initialize node */
2866         INIT_HLIST_NODE(&input->nfc_node);
2867
2868         /* add filter to the list */
2869         if (parent)
2870                 hlist_add_behind(&parent->nfc_node, &input->nfc_node);
2871         else
2872                 hlist_add_head(&input->nfc_node, &adapter->nfc_filter_list);
2873
2874         /* update counts */
2875         adapter->nfc_filter_count++;
2876
2877         return 0;
2878 }
2879
2880 static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter,
2881                                      struct ethtool_rxnfc *cmd)
2882 {
2883         struct net_device *netdev = adapter->netdev;
2884         struct ethtool_rx_flow_spec *fsp =
2885                 (struct ethtool_rx_flow_spec *)&cmd->fs;
2886         struct igb_nfc_filter *input, *rule;
2887         int err = 0;
2888
2889         if (!(netdev->hw_features & NETIF_F_NTUPLE))
2890                 return -EOPNOTSUPP;
2891
2892         /* Don't allow programming if the action is a queue greater than
2893          * the number of online Rx queues.
2894          */
2895         if ((fsp->ring_cookie == RX_CLS_FLOW_DISC) ||
2896             (fsp->ring_cookie >= adapter->num_rx_queues)) {
2897                 dev_err(&adapter->pdev->dev, "ethtool -N: The specified action is invalid\n");
2898                 return -EINVAL;
2899         }
2900
2901         /* Don't allow indexes to exist outside of available space */
2902         if (fsp->location >= IGB_MAX_RXNFC_FILTERS) {
2903                 dev_err(&adapter->pdev->dev, "Location out of range\n");
2904                 return -EINVAL;
2905         }
2906
2907         if ((fsp->flow_type & ~FLOW_EXT) != ETHER_FLOW)
2908                 return -EINVAL;
2909
2910         if (fsp->m_u.ether_spec.h_proto != ETHER_TYPE_FULL_MASK &&
2911             fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK))
2912                 return -EINVAL;
2913
2914         input = kzalloc(sizeof(*input), GFP_KERNEL);
2915         if (!input)
2916                 return -ENOMEM;
2917
2918         if (fsp->m_u.ether_spec.h_proto == ETHER_TYPE_FULL_MASK) {
2919                 input->filter.etype = fsp->h_u.ether_spec.h_proto;
2920                 input->filter.match_flags = IGB_FILTER_FLAG_ETHER_TYPE;
2921         }
2922
2923         if ((fsp->flow_type & FLOW_EXT) && fsp->m_ext.vlan_tci) {
2924                 if (fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) {
2925                         err = -EINVAL;
2926                         goto err_out;
2927                 }
2928                 input->filter.vlan_tci = fsp->h_ext.vlan_tci;
2929                 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2930         }
2931
2932         input->action = fsp->ring_cookie;
2933         input->sw_idx = fsp->location;
2934
2935         spin_lock(&adapter->nfc_lock);
2936
2937         hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2938                 if (!memcmp(&input->filter, &rule->filter,
2939                             sizeof(input->filter))) {
2940                         err = -EEXIST;
2941                         dev_err(&adapter->pdev->dev,
2942                                 "ethtool: this filter is already set\n");
2943                         goto err_out_w_lock;
2944                 }
2945         }
2946
2947         err = igb_add_filter(adapter, input);
2948         if (err)
2949                 goto err_out_w_lock;
2950
2951         igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx);
2952
2953         spin_unlock(&adapter->nfc_lock);
2954         return 0;
2955
2956 err_out_w_lock:
2957         spin_unlock(&adapter->nfc_lock);
2958 err_out:
2959         kfree(input);
2960         return err;
2961 }
2962
2963 static int igb_del_ethtool_nfc_entry(struct igb_adapter *adapter,
2964                                      struct ethtool_rxnfc *cmd)
2965 {
2966         struct ethtool_rx_flow_spec *fsp =
2967                 (struct ethtool_rx_flow_spec *)&cmd->fs;
2968         int err;
2969
2970         spin_lock(&adapter->nfc_lock);
2971         err = igb_update_ethtool_nfc_entry(adapter, NULL, fsp->location);
2972         spin_unlock(&adapter->nfc_lock);
2973
2974         return err;
2975 }
2976
2977 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2978 {
2979         struct igb_adapter *adapter = netdev_priv(dev);
2980         int ret = -EOPNOTSUPP;
2981
2982         switch (cmd->cmd) {
2983         case ETHTOOL_SRXFH:
2984                 ret = igb_set_rss_hash_opt(adapter, cmd);
2985                 break;
2986         case ETHTOOL_SRXCLSRLINS:
2987                 ret = igb_add_ethtool_nfc_entry(adapter, cmd);
2988                 break;
2989         case ETHTOOL_SRXCLSRLDEL:
2990                 ret = igb_del_ethtool_nfc_entry(adapter, cmd);
2991         default:
2992                 break;
2993         }
2994
2995         return ret;
2996 }
2997
2998 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
2999 {
3000         struct igb_adapter *adapter = netdev_priv(netdev);
3001         struct e1000_hw *hw = &adapter->hw;
3002         u32 ret_val;
3003         u16 phy_data;
3004
3005         if ((hw->mac.type < e1000_i350) ||
3006             (hw->phy.media_type != e1000_media_type_copper))
3007                 return -EOPNOTSUPP;
3008
3009         edata->supported = (SUPPORTED_1000baseT_Full |
3010                             SUPPORTED_100baseT_Full);
3011         if (!hw->dev_spec._82575.eee_disable)
3012                 edata->advertised =
3013                         mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert);
3014
3015         /* The IPCNFG and EEER registers are not supported on I354. */
3016         if (hw->mac.type == e1000_i354) {
3017                 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active);
3018         } else {
3019                 u32 eeer;
3020
3021                 eeer = rd32(E1000_EEER);
3022
3023                 /* EEE status on negotiated link */
3024                 if (eeer & E1000_EEER_EEE_NEG)
3025                         edata->eee_active = true;
3026
3027                 if (eeer & E1000_EEER_TX_LPI_EN)
3028                         edata->tx_lpi_enabled = true;
3029         }
3030
3031         /* EEE Link Partner Advertised */
3032         switch (hw->mac.type) {
3033         case e1000_i350:
3034                 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,
3035                                            &phy_data);
3036                 if (ret_val)
3037                         return -ENODATA;
3038
3039                 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
3040                 break;
3041         case e1000_i354:
3042         case e1000_i210:
3043         case e1000_i211:
3044                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,
3045                                              E1000_EEE_LP_ADV_DEV_I210,
3046                                              &phy_data);
3047                 if (ret_val)
3048                         return -ENODATA;
3049
3050                 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
3051
3052                 break;
3053         default:
3054                 break;
3055         }
3056
3057         edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
3058
3059         if ((hw->mac.type == e1000_i354) &&
3060             (edata->eee_enabled))
3061                 edata->tx_lpi_enabled = true;
3062
3063         /* Report correct negotiated EEE status for devices that
3064          * wrongly report EEE at half-duplex
3065          */
3066         if (adapter->link_duplex == HALF_DUPLEX) {
3067                 edata->eee_enabled = false;
3068                 edata->eee_active = false;
3069                 edata->tx_lpi_enabled = false;
3070                 edata->advertised &= ~edata->advertised;
3071         }
3072
3073         return 0;
3074 }
3075
3076 static int igb_set_eee(struct net_device *netdev,
3077                        struct ethtool_eee *edata)
3078 {
3079         struct igb_adapter *adapter = netdev_priv(netdev);
3080         struct e1000_hw *hw = &adapter->hw;
3081         struct ethtool_eee eee_curr;
3082         bool adv1g_eee = true, adv100m_eee = true;
3083         s32 ret_val;
3084
3085         if ((hw->mac.type < e1000_i350) ||
3086             (hw->phy.media_type != e1000_media_type_copper))
3087                 return -EOPNOTSUPP;
3088
3089         memset(&eee_curr, 0, sizeof(struct ethtool_eee));
3090
3091         ret_val = igb_get_eee(netdev, &eee_curr);
3092         if (ret_val)
3093                 return ret_val;
3094
3095         if (eee_curr.eee_enabled) {
3096                 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
3097                         dev_err(&adapter->pdev->dev,
3098                                 "Setting EEE tx-lpi is not supported\n");
3099                         return -EINVAL;
3100                 }
3101
3102                 /* Tx LPI timer is not implemented currently */
3103                 if (edata->tx_lpi_timer) {
3104                         dev_err(&adapter->pdev->dev,
3105                                 "Setting EEE Tx LPI timer is not supported\n");
3106                         return -EINVAL;
3107                 }
3108
3109                 if (!edata->advertised || (edata->advertised &
3110                     ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) {
3111                         dev_err(&adapter->pdev->dev,
3112                                 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n");
3113                         return -EINVAL;
3114                 }
3115                 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL);
3116                 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL);
3117
3118         } else if (!edata->eee_enabled) {
3119                 dev_err(&adapter->pdev->dev,
3120                         "Setting EEE options are not supported with EEE disabled\n");
3121                         return -EINVAL;
3122                 }
3123
3124         adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised);
3125         if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
3126                 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
3127                 adapter->flags |= IGB_FLAG_EEE;
3128
3129                 /* reset link */
3130                 if (netif_running(netdev))
3131                         igb_reinit_locked(adapter);
3132                 else
3133                         igb_reset(adapter);
3134         }
3135
3136         if (hw->mac.type == e1000_i354)
3137                 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee);
3138         else
3139                 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee);
3140
3141         if (ret_val) {
3142                 dev_err(&adapter->pdev->dev,
3143                         "Problem setting EEE advertisement options\n");
3144                 return -EINVAL;
3145         }
3146
3147         return 0;
3148 }
3149
3150 static int igb_get_module_info(struct net_device *netdev,
3151                                struct ethtool_modinfo *modinfo)
3152 {
3153         struct igb_adapter *adapter = netdev_priv(netdev);
3154         struct e1000_hw *hw = &adapter->hw;
3155         u32 status = 0;
3156         u16 sff8472_rev, addr_mode;
3157         bool page_swap = false;
3158
3159         if ((hw->phy.media_type == e1000_media_type_copper) ||
3160             (hw->phy.media_type == e1000_media_type_unknown))
3161                 return -EOPNOTSUPP;
3162
3163         /* Check whether we support SFF-8472 or not */
3164         status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
3165         if (status)
3166                 return -EIO;
3167
3168         /* addressing mode is not supported */
3169         status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
3170         if (status)
3171                 return -EIO;
3172
3173         /* addressing mode is not supported */
3174         if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
3175                 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3176                 page_swap = true;
3177         }
3178
3179         if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
3180                 /* We have an SFP, but it does not support SFF-8472 */
3181                 modinfo->type = ETH_MODULE_SFF_8079;
3182                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3183         } else {
3184                 /* We have an SFP which supports a revision of SFF-8472 */
3185                 modinfo->type = ETH_MODULE_SFF_8472;
3186                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3187         }
3188
3189         return 0;
3190 }
3191
3192 static int igb_get_module_eeprom(struct net_device *netdev,
3193                                  struct ethtool_eeprom *ee, u8 *data)
3194 {
3195         struct igb_adapter *adapter = netdev_priv(netdev);
3196         struct e1000_hw *hw = &adapter->hw;
3197         u32 status = 0;
3198         u16 *dataword;
3199         u16 first_word, last_word;
3200         int i = 0;
3201
3202         if (ee->len == 0)
3203                 return -EINVAL;
3204
3205         first_word = ee->offset >> 1;
3206         last_word = (ee->offset + ee->len - 1) >> 1;
3207
3208         dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1),
3209                            GFP_KERNEL);
3210         if (!dataword)
3211                 return -ENOMEM;
3212
3213         /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
3214         for (i = 0; i < last_word - first_word + 1; i++) {
3215                 status = igb_read_phy_reg_i2c(hw, (first_word + i) * 2,
3216                                               &dataword[i]);
3217                 if (status) {
3218                         /* Error occurred while reading module */
3219                         kfree(dataword);
3220                         return -EIO;
3221                 }
3222
3223                 be16_to_cpus(&dataword[i]);
3224         }
3225
3226         memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
3227         kfree(dataword);
3228
3229         return 0;
3230 }
3231
3232 static int igb_ethtool_begin(struct net_device *netdev)
3233 {
3234         struct igb_adapter *adapter = netdev_priv(netdev);
3235         pm_runtime_get_sync(&adapter->pdev->dev);
3236         return 0;
3237 }
3238
3239 static void igb_ethtool_complete(struct net_device *netdev)
3240 {
3241         struct igb_adapter *adapter = netdev_priv(netdev);
3242         pm_runtime_put(&adapter->pdev->dev);
3243 }
3244
3245 static u32 igb_get_rxfh_indir_size(struct net_device *netdev)
3246 {
3247         return IGB_RETA_SIZE;
3248 }
3249
3250 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
3251                         u8 *hfunc)
3252 {
3253         struct igb_adapter *adapter = netdev_priv(netdev);
3254         int i;
3255
3256         if (hfunc)
3257                 *hfunc = ETH_RSS_HASH_TOP;
3258         if (!indir)
3259                 return 0;
3260         for (i = 0; i < IGB_RETA_SIZE; i++)
3261                 indir[i] = adapter->rss_indir_tbl[i];
3262
3263         return 0;
3264 }
3265
3266 void igb_write_rss_indir_tbl(struct igb_adapter *adapter)
3267 {
3268         struct e1000_hw *hw = &adapter->hw;
3269         u32 reg = E1000_RETA(0);
3270         u32 shift = 0;
3271         int i = 0;
3272
3273         switch (hw->mac.type) {
3274         case e1000_82575:
3275                 shift = 6;
3276                 break;
3277         case e1000_82576:
3278                 /* 82576 supports 2 RSS queues for SR-IOV */
3279                 if (adapter->vfs_allocated_count)
3280                         shift = 3;
3281                 break;
3282         default:
3283                 break;
3284         }
3285
3286         while (i < IGB_RETA_SIZE) {
3287                 u32 val = 0;
3288                 int j;
3289
3290                 for (j = 3; j >= 0; j--) {
3291                         val <<= 8;
3292                         val |= adapter->rss_indir_tbl[i + j];
3293                 }
3294
3295                 wr32(reg, val << shift);
3296                 reg += 4;
3297                 i += 4;
3298         }
3299 }
3300
3301 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir,
3302                         const u8 *key, const u8 hfunc)
3303 {
3304         struct igb_adapter *adapter = netdev_priv(netdev);
3305         struct e1000_hw *hw = &adapter->hw;
3306         int i;
3307         u32 num_queues;
3308
3309         /* We do not allow change in unsupported parameters */
3310         if (key ||
3311             (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3312                 return -EOPNOTSUPP;
3313         if (!indir)
3314                 return 0;
3315
3316         num_queues = adapter->rss_queues;
3317
3318         switch (hw->mac.type) {
3319         case e1000_82576:
3320                 /* 82576 supports 2 RSS queues for SR-IOV */
3321                 if (adapter->vfs_allocated_count)
3322                         num_queues = 2;
3323                 break;
3324         default:
3325                 break;
3326         }
3327
3328         /* Verify user input. */
3329         for (i = 0; i < IGB_RETA_SIZE; i++)
3330                 if (indir[i] >= num_queues)
3331                         return -EINVAL;
3332
3333
3334         for (i = 0; i < IGB_RETA_SIZE; i++)
3335                 adapter->rss_indir_tbl[i] = indir[i];
3336
3337         igb_write_rss_indir_tbl(adapter);
3338
3339         return 0;
3340 }
3341
3342 static unsigned int igb_max_channels(struct igb_adapter *adapter)
3343 {
3344         struct e1000_hw *hw = &adapter->hw;
3345         unsigned int max_combined = 0;
3346
3347         switch (hw->mac.type) {
3348         case e1000_i211:
3349                 max_combined = IGB_MAX_RX_QUEUES_I211;
3350                 break;
3351         case e1000_82575:
3352         case e1000_i210:
3353                 max_combined = IGB_MAX_RX_QUEUES_82575;
3354                 break;
3355         case e1000_i350:
3356                 if (!!adapter->vfs_allocated_count) {
3357                         max_combined = 1;
3358                         break;
3359                 }
3360                 /* fall through */
3361         case e1000_82576:
3362                 if (!!adapter->vfs_allocated_count) {
3363                         max_combined = 2;
3364                         break;
3365                 }
3366                 /* fall through */
3367         case e1000_82580:
3368         case e1000_i354:
3369         default:
3370                 max_combined = IGB_MAX_RX_QUEUES;
3371                 break;
3372         }
3373
3374         return max_combined;
3375 }
3376
3377 static void igb_get_channels(struct net_device *netdev,
3378                              struct ethtool_channels *ch)
3379 {
3380         struct igb_adapter *adapter = netdev_priv(netdev);
3381
3382         /* Report maximum channels */
3383         ch->max_combined = igb_max_channels(adapter);
3384
3385         /* Report info for other vector */
3386         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
3387                 ch->max_other = NON_Q_VECTORS;
3388                 ch->other_count = NON_Q_VECTORS;
3389         }
3390
3391         ch->combined_count = adapter->rss_queues;
3392 }
3393
3394 static int igb_set_channels(struct net_device *netdev,
3395                             struct ethtool_channels *ch)
3396 {
3397         struct igb_adapter *adapter = netdev_priv(netdev);
3398         unsigned int count = ch->combined_count;
3399         unsigned int max_combined = 0;
3400
3401         /* Verify they are not requesting separate vectors */
3402         if (!count || ch->rx_count || ch->tx_count)
3403                 return -EINVAL;
3404
3405         /* Verify other_count is valid and has not been changed */
3406         if (ch->other_count != NON_Q_VECTORS)
3407                 return -EINVAL;
3408
3409         /* Verify the number of channels doesn't exceed hw limits */
3410         max_combined = igb_max_channels(adapter);
3411         if (count > max_combined)
3412                 return -EINVAL;
3413
3414         if (count != adapter->rss_queues) {
3415                 adapter->rss_queues = count;
3416                 igb_set_flag_queue_pairs(adapter, max_combined);
3417
3418                 /* Hardware has to reinitialize queues and interrupts to
3419                  * match the new configuration.
3420                  */
3421                 return igb_reinit_queues(adapter);
3422         }
3423
3424         return 0;
3425 }
3426
3427 static u32 igb_get_priv_flags(struct net_device *netdev)
3428 {
3429         struct igb_adapter *adapter = netdev_priv(netdev);
3430         u32 priv_flags = 0;
3431
3432         if (adapter->flags & IGB_FLAG_RX_LEGACY)
3433                 priv_flags |= IGB_PRIV_FLAGS_LEGACY_RX;
3434
3435         return priv_flags;
3436 }
3437
3438 static int igb_set_priv_flags(struct net_device *netdev, u32 priv_flags)
3439 {
3440         struct igb_adapter *adapter = netdev_priv(netdev);
3441         unsigned int flags = adapter->flags;
3442
3443         flags &= ~IGB_FLAG_RX_LEGACY;
3444         if (priv_flags & IGB_PRIV_FLAGS_LEGACY_RX)
3445                 flags |= IGB_FLAG_RX_LEGACY;
3446
3447         if (flags != adapter->flags) {
3448                 adapter->flags = flags;
3449
3450                 /* reset interface to repopulate queues */
3451                 if (netif_running(netdev))
3452                         igb_reinit_locked(adapter);
3453         }
3454
3455         return 0;
3456 }
3457
3458 static const struct ethtool_ops igb_ethtool_ops = {
3459         .get_drvinfo            = igb_get_drvinfo,
3460         .get_regs_len           = igb_get_regs_len,
3461         .get_regs               = igb_get_regs,
3462         .get_wol                = igb_get_wol,
3463         .set_wol                = igb_set_wol,
3464         .get_msglevel           = igb_get_msglevel,
3465         .set_msglevel           = igb_set_msglevel,
3466         .nway_reset             = igb_nway_reset,
3467         .get_link               = igb_get_link,
3468         .get_eeprom_len         = igb_get_eeprom_len,
3469         .get_eeprom             = igb_get_eeprom,
3470         .set_eeprom             = igb_set_eeprom,
3471         .get_ringparam          = igb_get_ringparam,
3472         .set_ringparam          = igb_set_ringparam,
3473         .get_pauseparam         = igb_get_pauseparam,
3474         .set_pauseparam         = igb_set_pauseparam,
3475         .self_test              = igb_diag_test,
3476         .get_strings            = igb_get_strings,
3477         .set_phys_id            = igb_set_phys_id,
3478         .get_sset_count         = igb_get_sset_count,
3479         .get_ethtool_stats      = igb_get_ethtool_stats,
3480         .get_coalesce           = igb_get_coalesce,
3481         .set_coalesce           = igb_set_coalesce,
3482         .get_ts_info            = igb_get_ts_info,
3483         .get_rxnfc              = igb_get_rxnfc,
3484         .set_rxnfc              = igb_set_rxnfc,
3485         .get_eee                = igb_get_eee,
3486         .set_eee                = igb_set_eee,
3487         .get_module_info        = igb_get_module_info,
3488         .get_module_eeprom      = igb_get_module_eeprom,
3489         .get_rxfh_indir_size    = igb_get_rxfh_indir_size,
3490         .get_rxfh               = igb_get_rxfh,
3491         .set_rxfh               = igb_set_rxfh,
3492         .get_channels           = igb_get_channels,
3493         .set_channels           = igb_set_channels,
3494         .get_priv_flags         = igb_get_priv_flags,
3495         .set_priv_flags         = igb_set_priv_flags,
3496         .begin                  = igb_ethtool_begin,
3497         .complete               = igb_ethtool_complete,
3498         .get_link_ksettings     = igb_get_link_ksettings,
3499         .set_link_ksettings     = igb_set_link_ksettings,
3500 };
3501
3502 void igb_set_ethtool_ops(struct net_device *netdev)
3503 {
3504         netdev->ethtool_ops = &igb_ethtool_ops;
3505 }