1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2015 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 #include <linux/if_ether.h>
25 #include <linux/delay.h>
27 #include "e1000_mac.h"
28 #include "e1000_phy.h"
30 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
31 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
33 static s32 igb_wait_autoneg(struct e1000_hw *hw);
34 static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
36 /* Cable length tables */
37 static const u16 e1000_m88_cable_length_table[] = {
38 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
40 static const u16 e1000_igp_2_cable_length_table[] = {
41 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
42 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
43 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
44 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
45 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
46 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
47 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
48 104, 109, 114, 118, 121, 124};
51 * igb_check_reset_block - Check if PHY reset is blocked
52 * @hw: pointer to the HW structure
54 * Read the PHY management control register and check whether a PHY reset
55 * is blocked. If a reset is not blocked return 0, otherwise
56 * return E1000_BLK_PHY_RESET (12).
58 s32 igb_check_reset_block(struct e1000_hw *hw)
62 manc = rd32(E1000_MANC);
64 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
68 * igb_get_phy_id - Retrieve the PHY ID and revision
69 * @hw: pointer to the HW structure
71 * Reads the PHY registers and stores the PHY ID and possibly the PHY
72 * revision in the hardware structure.
74 s32 igb_get_phy_id(struct e1000_hw *hw)
76 struct e1000_phy_info *phy = &hw->phy;
80 /* ensure PHY page selection to fix misconfigured i210 */
81 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
82 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0);
84 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
88 phy->id = (u32)(phy_id << 16);
90 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
94 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
95 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
102 * igb_phy_reset_dsp - Reset PHY DSP
103 * @hw: pointer to the HW structure
105 * Reset the digital signal processor.
107 static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
111 if (!(hw->phy.ops.write_reg))
114 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
118 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
125 * igb_read_phy_reg_mdic - Read MDI control register
126 * @hw: pointer to the HW structure
127 * @offset: register offset to be read
128 * @data: pointer to the read data
130 * Reads the MDI control regsiter in the PHY at offset and stores the
131 * information read to data.
133 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
135 struct e1000_phy_info *phy = &hw->phy;
139 if (offset > MAX_PHY_REG_ADDRESS) {
140 hw_dbg("PHY Address %d is out of range\n", offset);
141 ret_val = -E1000_ERR_PARAM;
145 /* Set up Op-code, Phy Address, and register offset in the MDI
146 * Control register. The MAC will take care of interfacing with the
147 * PHY to retrieve the desired data.
149 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
150 (phy->addr << E1000_MDIC_PHY_SHIFT) |
151 (E1000_MDIC_OP_READ));
153 wr32(E1000_MDIC, mdic);
155 /* Poll the ready bit to see if the MDI read completed
156 * Increasing the time out as testing showed failures with
159 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
161 mdic = rd32(E1000_MDIC);
162 if (mdic & E1000_MDIC_READY)
165 if (!(mdic & E1000_MDIC_READY)) {
166 hw_dbg("MDI Read did not complete\n");
167 ret_val = -E1000_ERR_PHY;
170 if (mdic & E1000_MDIC_ERROR) {
171 hw_dbg("MDI Error\n");
172 ret_val = -E1000_ERR_PHY;
182 * igb_write_phy_reg_mdic - Write MDI control register
183 * @hw: pointer to the HW structure
184 * @offset: register offset to write to
185 * @data: data to write to register at offset
187 * Writes data to MDI control register in the PHY at offset.
189 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
191 struct e1000_phy_info *phy = &hw->phy;
195 if (offset > MAX_PHY_REG_ADDRESS) {
196 hw_dbg("PHY Address %d is out of range\n", offset);
197 ret_val = -E1000_ERR_PARAM;
201 /* Set up Op-code, Phy Address, and register offset in the MDI
202 * Control register. The MAC will take care of interfacing with the
203 * PHY to retrieve the desired data.
205 mdic = (((u32)data) |
206 (offset << E1000_MDIC_REG_SHIFT) |
207 (phy->addr << E1000_MDIC_PHY_SHIFT) |
208 (E1000_MDIC_OP_WRITE));
210 wr32(E1000_MDIC, mdic);
212 /* Poll the ready bit to see if the MDI read completed
213 * Increasing the time out as testing showed failures with
216 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
218 mdic = rd32(E1000_MDIC);
219 if (mdic & E1000_MDIC_READY)
222 if (!(mdic & E1000_MDIC_READY)) {
223 hw_dbg("MDI Write did not complete\n");
224 ret_val = -E1000_ERR_PHY;
227 if (mdic & E1000_MDIC_ERROR) {
228 hw_dbg("MDI Error\n");
229 ret_val = -E1000_ERR_PHY;
238 * igb_read_phy_reg_i2c - Read PHY register using i2c
239 * @hw: pointer to the HW structure
240 * @offset: register offset to be read
241 * @data: pointer to the read data
243 * Reads the PHY register at offset using the i2c interface and stores the
244 * retrieved information in data.
246 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
248 struct e1000_phy_info *phy = &hw->phy;
251 /* Set up Op-code, Phy Address, and register address in the I2CCMD
252 * register. The MAC will take care of interfacing with the
253 * PHY to retrieve the desired data.
255 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
256 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
257 (E1000_I2CCMD_OPCODE_READ));
259 wr32(E1000_I2CCMD, i2ccmd);
261 /* Poll the ready bit to see if the I2C read completed */
262 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
264 i2ccmd = rd32(E1000_I2CCMD);
265 if (i2ccmd & E1000_I2CCMD_READY)
268 if (!(i2ccmd & E1000_I2CCMD_READY)) {
269 hw_dbg("I2CCMD Read did not complete\n");
270 return -E1000_ERR_PHY;
272 if (i2ccmd & E1000_I2CCMD_ERROR) {
273 hw_dbg("I2CCMD Error bit set\n");
274 return -E1000_ERR_PHY;
277 /* Need to byte-swap the 16-bit value. */
278 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
284 * igb_write_phy_reg_i2c - Write PHY register using i2c
285 * @hw: pointer to the HW structure
286 * @offset: register offset to write to
287 * @data: data to write at register offset
289 * Writes the data to PHY register at the offset using the i2c interface.
291 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
293 struct e1000_phy_info *phy = &hw->phy;
295 u16 phy_data_swapped;
297 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
298 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
299 hw_dbg("PHY I2C Address %d is out of range.\n",
301 return -E1000_ERR_CONFIG;
304 /* Swap the data bytes for the I2C interface */
305 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
307 /* Set up Op-code, Phy Address, and register address in the I2CCMD
308 * register. The MAC will take care of interfacing with the
309 * PHY to retrieve the desired data.
311 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
312 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
313 E1000_I2CCMD_OPCODE_WRITE |
316 wr32(E1000_I2CCMD, i2ccmd);
318 /* Poll the ready bit to see if the I2C read completed */
319 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
321 i2ccmd = rd32(E1000_I2CCMD);
322 if (i2ccmd & E1000_I2CCMD_READY)
325 if (!(i2ccmd & E1000_I2CCMD_READY)) {
326 hw_dbg("I2CCMD Write did not complete\n");
327 return -E1000_ERR_PHY;
329 if (i2ccmd & E1000_I2CCMD_ERROR) {
330 hw_dbg("I2CCMD Error bit set\n");
331 return -E1000_ERR_PHY;
338 * igb_read_sfp_data_byte - Reads SFP module data.
339 * @hw: pointer to the HW structure
340 * @offset: byte location offset to be read
341 * @data: read data buffer pointer
343 * Reads one byte from SFP module data stored
344 * in SFP resided EEPROM memory or SFP diagnostic area.
345 * Function should be called with
346 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
347 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
350 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
356 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
357 hw_dbg("I2CCMD command address exceeds upper limit\n");
358 return -E1000_ERR_PHY;
361 /* Set up Op-code, EEPROM Address,in the I2CCMD
362 * register. The MAC will take care of interfacing with the
363 * EEPROM to retrieve the desired data.
365 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
366 E1000_I2CCMD_OPCODE_READ);
368 wr32(E1000_I2CCMD, i2ccmd);
370 /* Poll the ready bit to see if the I2C read completed */
371 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
373 data_local = rd32(E1000_I2CCMD);
374 if (data_local & E1000_I2CCMD_READY)
377 if (!(data_local & E1000_I2CCMD_READY)) {
378 hw_dbg("I2CCMD Read did not complete\n");
379 return -E1000_ERR_PHY;
381 if (data_local & E1000_I2CCMD_ERROR) {
382 hw_dbg("I2CCMD Error bit set\n");
383 return -E1000_ERR_PHY;
385 *data = (u8) data_local & 0xFF;
391 * igb_read_phy_reg_igp - Read igp PHY register
392 * @hw: pointer to the HW structure
393 * @offset: register offset to be read
394 * @data: pointer to the read data
396 * Acquires semaphore, if necessary, then reads the PHY register at offset
397 * and storing the retrieved information in data. Release any acquired
398 * semaphores before exiting.
400 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
404 if (!(hw->phy.ops.acquire))
407 ret_val = hw->phy.ops.acquire(hw);
411 if (offset > MAX_PHY_MULTI_PAGE_REG) {
412 ret_val = igb_write_phy_reg_mdic(hw,
413 IGP01E1000_PHY_PAGE_SELECT,
416 hw->phy.ops.release(hw);
421 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
424 hw->phy.ops.release(hw);
431 * igb_write_phy_reg_igp - Write igp PHY register
432 * @hw: pointer to the HW structure
433 * @offset: register offset to write to
434 * @data: data to write at register offset
436 * Acquires semaphore, if necessary, then writes the data to PHY register
437 * at the offset. Release any acquired semaphores before exiting.
439 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
443 if (!(hw->phy.ops.acquire))
446 ret_val = hw->phy.ops.acquire(hw);
450 if (offset > MAX_PHY_MULTI_PAGE_REG) {
451 ret_val = igb_write_phy_reg_mdic(hw,
452 IGP01E1000_PHY_PAGE_SELECT,
455 hw->phy.ops.release(hw);
460 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
463 hw->phy.ops.release(hw);
470 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
471 * @hw: pointer to the HW structure
473 * Sets up Carrier-sense on Transmit and downshift values.
475 s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
477 struct e1000_phy_info *phy = &hw->phy;
481 if (phy->reset_disable) {
486 if (phy->type == e1000_phy_82580) {
487 ret_val = hw->phy.ops.reset(hw);
489 hw_dbg("Error resetting the PHY.\n");
494 /* Enable CRS on TX. This must be set for half-duplex operation. */
495 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
499 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
501 /* Enable downshift */
502 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
504 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
508 /* Set MDI/MDIX mode */
509 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
512 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
518 switch (hw->phy.mdix) {
522 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
526 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
529 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
536 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
537 * @hw: pointer to the HW structure
539 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
540 * and downshift values are set also.
542 s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
544 struct e1000_phy_info *phy = &hw->phy;
548 if (phy->reset_disable) {
553 /* Enable CRS on TX. This must be set for half-duplex operation. */
554 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
558 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
561 * MDI/MDI-X = 0 (default)
562 * 0 - Auto for all speeds
565 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
567 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
571 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
574 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
577 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
581 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
586 * disable_polarity_correction = 0 (default)
587 * Automatic Correction for Reversed Cable Polarity
591 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
592 if (phy->disable_polarity_correction == 1)
593 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
595 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
599 if (phy->revision < E1000_REVISION_4) {
600 /* Force TX_CLK in the Extended PHY Specific Control Register
603 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
608 phy_data |= M88E1000_EPSCR_TX_CLK_25;
610 if ((phy->revision == E1000_REVISION_2) &&
611 (phy->id == M88E1111_I_PHY_ID)) {
612 /* 82573L PHY - set the downshift counter to 5x. */
613 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
614 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
616 /* Configure Master and Slave downshift values */
617 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
618 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
619 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
620 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
622 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
628 /* Commit the changes. */
629 ret_val = igb_phy_sw_reset(hw);
631 hw_dbg("Error committing the PHY changes\n");
640 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
641 * @hw: pointer to the HW structure
643 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
644 * Also enables and sets the downshift parameters.
646 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
648 struct e1000_phy_info *phy = &hw->phy;
652 if (phy->reset_disable)
655 /* Enable CRS on Tx. This must be set for half-duplex operation. */
656 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
661 * MDI/MDI-X = 0 (default)
662 * 0 - Auto for all speeds
665 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
667 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
671 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
674 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
677 /* M88E1112 does not support this mode) */
678 if (phy->id != M88E1112_E_PHY_ID) {
679 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
684 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
689 * disable_polarity_correction = 0 (default)
690 * Automatic Correction for Reversed Cable Polarity
694 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
695 if (phy->disable_polarity_correction == 1)
696 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
698 /* Enable downshift and setting it to X6 */
699 if (phy->id == M88E1543_E_PHY_ID) {
700 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
702 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
706 ret_val = igb_phy_sw_reset(hw);
708 hw_dbg("Error committing the PHY changes\n");
713 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
714 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
715 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
717 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
721 /* Commit the changes. */
722 ret_val = igb_phy_sw_reset(hw);
724 hw_dbg("Error committing the PHY changes\n");
727 ret_val = igb_set_master_slave_mode(hw);
735 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
736 * @hw: pointer to the HW structure
738 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
741 s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
743 struct e1000_phy_info *phy = &hw->phy;
747 if (phy->reset_disable) {
752 ret_val = phy->ops.reset(hw);
754 hw_dbg("Error resetting the PHY.\n");
758 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
759 * timeout issues when LFS is enabled.
763 /* The NVM settings will configure LPLU in D3 for
766 if (phy->type == e1000_phy_igp) {
767 /* disable lplu d3 during driver init */
768 if (phy->ops.set_d3_lplu_state)
769 ret_val = phy->ops.set_d3_lplu_state(hw, false);
771 hw_dbg("Error Disabling LPLU D3\n");
776 /* disable lplu d0 during driver init */
777 ret_val = phy->ops.set_d0_lplu_state(hw, false);
779 hw_dbg("Error Disabling LPLU D0\n");
782 /* Configure mdi-mdix settings */
783 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
787 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
791 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
794 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
798 data |= IGP01E1000_PSCR_AUTO_MDIX;
801 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
805 /* set auto-master slave resolution settings */
806 if (hw->mac.autoneg) {
807 /* when autonegotiation advertisement is only 1000Mbps then we
808 * should disable SmartSpeed and enable Auto MasterSlave
809 * resolution as hardware default.
811 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
812 /* Disable SmartSpeed */
813 ret_val = phy->ops.read_reg(hw,
814 IGP01E1000_PHY_PORT_CONFIG,
819 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
820 ret_val = phy->ops.write_reg(hw,
821 IGP01E1000_PHY_PORT_CONFIG,
826 /* Set auto Master/Slave resolution process */
827 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
831 data &= ~CR_1000T_MS_ENABLE;
832 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
837 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
841 /* load defaults for future use */
842 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
843 ((data & CR_1000T_MS_VALUE) ?
844 e1000_ms_force_master :
845 e1000_ms_force_slave) :
848 switch (phy->ms_type) {
849 case e1000_ms_force_master:
850 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
852 case e1000_ms_force_slave:
853 data |= CR_1000T_MS_ENABLE;
854 data &= ~(CR_1000T_MS_VALUE);
857 data &= ~CR_1000T_MS_ENABLE;
861 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
871 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
872 * @hw: pointer to the HW structure
874 * Performs initial bounds checking on autoneg advertisement parameter, then
875 * configure to advertise the full capability. Setup the PHY to autoneg
876 * and restart the negotiation process between the link partner. If
877 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
879 static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
881 struct e1000_phy_info *phy = &hw->phy;
885 /* Perform some bounds checking on the autoneg advertisement
888 phy->autoneg_advertised &= phy->autoneg_mask;
890 /* If autoneg_advertised is zero, we assume it was not defaulted
891 * by the calling code so we set to advertise full capability.
893 if (phy->autoneg_advertised == 0)
894 phy->autoneg_advertised = phy->autoneg_mask;
896 hw_dbg("Reconfiguring auto-neg advertisement params\n");
897 ret_val = igb_phy_setup_autoneg(hw);
899 hw_dbg("Error Setting up Auto-Negotiation\n");
902 hw_dbg("Restarting Auto-Neg\n");
904 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
905 * the Auto Neg Restart bit in the PHY control register.
907 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
911 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
912 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
916 /* Does the user want to wait for Auto-Neg to complete here, or
917 * check at a later time (for example, callback routine).
919 if (phy->autoneg_wait_to_complete) {
920 ret_val = igb_wait_autoneg(hw);
922 hw_dbg("Error while waiting for autoneg to complete\n");
927 hw->mac.get_link_status = true;
934 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
935 * @hw: pointer to the HW structure
937 * Reads the MII auto-neg advertisement register and/or the 1000T control
938 * register and if the PHY is already setup for auto-negotiation, then
939 * return successful. Otherwise, setup advertisement and flow control to
940 * the appropriate values for the wanted auto-negotiation.
942 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
944 struct e1000_phy_info *phy = &hw->phy;
946 u16 mii_autoneg_adv_reg;
947 u16 mii_1000t_ctrl_reg = 0;
949 phy->autoneg_advertised &= phy->autoneg_mask;
951 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
952 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
956 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
957 /* Read the MII 1000Base-T Control Register (Address 9). */
958 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
959 &mii_1000t_ctrl_reg);
964 /* Need to parse both autoneg_advertised and fc and set up
965 * the appropriate PHY registers. First we will parse for
966 * autoneg_advertised software override. Since we can advertise
967 * a plethora of combinations, we need to check each bit
971 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
972 * Advertisement Register (Address 4) and the 1000 mb speed bits in
973 * the 1000Base-T Control Register (Address 9).
975 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
976 NWAY_AR_100TX_HD_CAPS |
977 NWAY_AR_10T_FD_CAPS |
978 NWAY_AR_10T_HD_CAPS);
979 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
981 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
983 /* Do we want to advertise 10 Mb Half Duplex? */
984 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
985 hw_dbg("Advertise 10mb Half duplex\n");
986 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
989 /* Do we want to advertise 10 Mb Full Duplex? */
990 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
991 hw_dbg("Advertise 10mb Full duplex\n");
992 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
995 /* Do we want to advertise 100 Mb Half Duplex? */
996 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
997 hw_dbg("Advertise 100mb Half duplex\n");
998 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1001 /* Do we want to advertise 100 Mb Full Duplex? */
1002 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1003 hw_dbg("Advertise 100mb Full duplex\n");
1004 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1007 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1008 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1009 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
1011 /* Do we want to advertise 1000 Mb Full Duplex? */
1012 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1013 hw_dbg("Advertise 1000mb Full duplex\n");
1014 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1017 /* Check for a software override of the flow control settings, and
1018 * setup the PHY advertisement registers accordingly. If
1019 * auto-negotiation is enabled, then software will have to set the
1020 * "PAUSE" bits to the correct value in the Auto-Negotiation
1021 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1024 * The possible values of the "fc" parameter are:
1025 * 0: Flow control is completely disabled
1026 * 1: Rx flow control is enabled (we can receive pause frames
1027 * but not send pause frames).
1028 * 2: Tx flow control is enabled (we can send pause frames
1029 * but we do not support receiving pause frames).
1030 * 3: Both Rx and TX flow control (symmetric) are enabled.
1031 * other: No software override. The flow control configuration
1032 * in the EEPROM is used.
1034 switch (hw->fc.current_mode) {
1036 /* Flow control (RX & TX) is completely disabled by a
1037 * software over-ride.
1039 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1041 case e1000_fc_rx_pause:
1042 /* RX Flow control is enabled, and TX Flow control is
1043 * disabled, by a software over-ride.
1045 * Since there really isn't a way to advertise that we are
1046 * capable of RX Pause ONLY, we will advertise that we
1047 * support both symmetric and asymmetric RX PAUSE. Later
1048 * (in e1000_config_fc_after_link_up) we will disable the
1049 * hw's ability to send PAUSE frames.
1051 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1053 case e1000_fc_tx_pause:
1054 /* TX Flow control is enabled, and RX Flow control is
1055 * disabled, by a software over-ride.
1057 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1058 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1061 /* Flow control (both RX and TX) is enabled by a software
1064 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1067 hw_dbg("Flow control param set incorrectly\n");
1068 ret_val = -E1000_ERR_CONFIG;
1072 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1076 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1078 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1079 ret_val = phy->ops.write_reg(hw,
1081 mii_1000t_ctrl_reg);
1091 * igb_setup_copper_link - Configure copper link settings
1092 * @hw: pointer to the HW structure
1094 * Calls the appropriate function to configure the link for auto-neg or forced
1095 * speed and duplex. Then we check for link, once link is established calls
1096 * to configure collision distance and flow control are called. If link is
1097 * not established, we return -E1000_ERR_PHY (-2).
1099 s32 igb_setup_copper_link(struct e1000_hw *hw)
1104 if (hw->mac.autoneg) {
1105 /* Setup autoneg and flow control advertisement and perform
1108 ret_val = igb_copper_link_autoneg(hw);
1112 /* PHY will be set to 10H, 10F, 100H or 100F
1113 * depending on user settings.
1115 hw_dbg("Forcing Speed and Duplex\n");
1116 ret_val = hw->phy.ops.force_speed_duplex(hw);
1118 hw_dbg("Error Forcing Speed and Duplex\n");
1123 /* Check link status. Wait up to 100 microseconds for link to become
1126 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
1131 hw_dbg("Valid link established!!!\n");
1132 igb_config_collision_dist(hw);
1133 ret_val = igb_config_fc_after_link_up(hw);
1135 hw_dbg("Unable to establish link!!!\n");
1143 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1144 * @hw: pointer to the HW structure
1146 * Calls the PHY setup function to force speed and duplex. Clears the
1147 * auto-crossover to force MDI manually. Waits for link and returns
1148 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1150 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1152 struct e1000_phy_info *phy = &hw->phy;
1157 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1161 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1163 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1167 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1168 * forced whenever speed and duplex are forced.
1170 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1174 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1175 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1177 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1181 hw_dbg("IGP PSCR: %X\n", phy_data);
1185 if (phy->autoneg_wait_to_complete) {
1186 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1188 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1193 hw_dbg("Link taking longer than expected.\n");
1196 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1206 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1207 * @hw: pointer to the HW structure
1209 * Calls the PHY setup function to force speed and duplex. Clears the
1210 * auto-crossover to force MDI manually. Resets the PHY to commit the
1211 * changes. If time expires while waiting for link up, we reset the DSP.
1212 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1213 * successful completion, else return corresponding error code.
1215 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1217 struct e1000_phy_info *phy = &hw->phy;
1222 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1223 if (phy->type != e1000_phy_i210) {
1224 /* Clear Auto-Crossover to force MDI manually. M88E1000
1225 * requires MDI forced whenever speed and duplex are forced.
1227 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1232 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1233 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1238 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
1241 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1245 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1247 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1251 /* Reset the phy to commit changes. */
1252 ret_val = igb_phy_sw_reset(hw);
1256 if (phy->autoneg_wait_to_complete) {
1257 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1259 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1264 bool reset_dsp = true;
1266 switch (hw->phy.id) {
1267 case I347AT4_E_PHY_ID:
1268 case M88E1112_E_PHY_ID:
1269 case M88E1543_E_PHY_ID:
1270 case M88E1512_E_PHY_ID:
1275 if (hw->phy.type != e1000_phy_m88)
1280 hw_dbg("Link taking longer than expected.\n");
1282 /* We didn't get link.
1283 * Reset the DSP and cross our fingers.
1285 ret_val = phy->ops.write_reg(hw,
1286 M88E1000_PHY_PAGE_SELECT,
1290 ret_val = igb_phy_reset_dsp(hw);
1297 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
1303 if (hw->phy.type != e1000_phy_m88 ||
1304 hw->phy.id == I347AT4_E_PHY_ID ||
1305 hw->phy.id == M88E1112_E_PHY_ID ||
1306 hw->phy.id == M88E1543_E_PHY_ID ||
1307 hw->phy.id == M88E1512_E_PHY_ID ||
1308 hw->phy.id == I210_I_PHY_ID)
1311 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1315 /* Resetting the phy means we need to re-force TX_CLK in the
1316 * Extended PHY Specific Control Register to 25MHz clock from
1317 * the reset value of 2.5MHz.
1319 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1320 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1324 /* In addition, we must re-enable CRS on Tx for both half and full
1327 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1331 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1332 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1339 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1340 * @hw: pointer to the HW structure
1341 * @phy_ctrl: pointer to current value of PHY_CONTROL
1343 * Forces speed and duplex on the PHY by doing the following: disable flow
1344 * control, force speed/duplex on the MAC, disable auto speed detection,
1345 * disable auto-negotiation, configure duplex, configure speed, configure
1346 * the collision distance, write configuration to CTRL register. The
1347 * caller must write to the PHY_CONTROL register for these settings to
1350 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1353 struct e1000_mac_info *mac = &hw->mac;
1356 /* Turn off flow control when forcing speed/duplex */
1357 hw->fc.current_mode = e1000_fc_none;
1359 /* Force speed/duplex on the mac */
1360 ctrl = rd32(E1000_CTRL);
1361 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1362 ctrl &= ~E1000_CTRL_SPD_SEL;
1364 /* Disable Auto Speed Detection */
1365 ctrl &= ~E1000_CTRL_ASDE;
1367 /* Disable autoneg on the phy */
1368 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1370 /* Forcing Full or Half Duplex? */
1371 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1372 ctrl &= ~E1000_CTRL_FD;
1373 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1374 hw_dbg("Half Duplex\n");
1376 ctrl |= E1000_CTRL_FD;
1377 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1378 hw_dbg("Full Duplex\n");
1381 /* Forcing 10mb or 100mb? */
1382 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1383 ctrl |= E1000_CTRL_SPD_100;
1384 *phy_ctrl |= MII_CR_SPEED_100;
1385 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1386 hw_dbg("Forcing 100mb\n");
1388 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1389 *phy_ctrl |= MII_CR_SPEED_10;
1390 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1391 hw_dbg("Forcing 10mb\n");
1394 igb_config_collision_dist(hw);
1396 wr32(E1000_CTRL, ctrl);
1400 * igb_set_d3_lplu_state - Sets low power link up state for D3
1401 * @hw: pointer to the HW structure
1402 * @active: boolean used to enable/disable lplu
1404 * Success returns 0, Failure returns 1
1406 * The low power link up (lplu) state is set to the power management level D3
1407 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1408 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1409 * is used during Dx states where the power conservation is most important.
1410 * During driver activity, SmartSpeed should be enabled so performance is
1413 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1415 struct e1000_phy_info *phy = &hw->phy;
1419 if (!(hw->phy.ops.read_reg))
1422 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1427 data &= ~IGP02E1000_PM_D3_LPLU;
1428 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1432 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1433 * during Dx states where the power conservation is most
1434 * important. During driver activity we should enable
1435 * SmartSpeed, so performance is maintained.
1437 if (phy->smart_speed == e1000_smart_speed_on) {
1438 ret_val = phy->ops.read_reg(hw,
1439 IGP01E1000_PHY_PORT_CONFIG,
1444 data |= IGP01E1000_PSCFR_SMART_SPEED;
1445 ret_val = phy->ops.write_reg(hw,
1446 IGP01E1000_PHY_PORT_CONFIG,
1450 } else if (phy->smart_speed == e1000_smart_speed_off) {
1451 ret_val = phy->ops.read_reg(hw,
1452 IGP01E1000_PHY_PORT_CONFIG,
1457 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1458 ret_val = phy->ops.write_reg(hw,
1459 IGP01E1000_PHY_PORT_CONFIG,
1464 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1465 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1466 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1467 data |= IGP02E1000_PM_D3_LPLU;
1468 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1473 /* When LPLU is enabled, we should disable SmartSpeed */
1474 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1479 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1480 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1489 * igb_check_downshift - Checks whether a downshift in speed occurred
1490 * @hw: pointer to the HW structure
1492 * Success returns 0, Failure returns 1
1494 * A downshift is detected by querying the PHY link health.
1496 s32 igb_check_downshift(struct e1000_hw *hw)
1498 struct e1000_phy_info *phy = &hw->phy;
1500 u16 phy_data, offset, mask;
1502 switch (phy->type) {
1503 case e1000_phy_i210:
1505 case e1000_phy_gg82563:
1506 offset = M88E1000_PHY_SPEC_STATUS;
1507 mask = M88E1000_PSSR_DOWNSHIFT;
1509 case e1000_phy_igp_2:
1511 case e1000_phy_igp_3:
1512 offset = IGP01E1000_PHY_LINK_HEALTH;
1513 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1516 /* speed downshift not supported */
1517 phy->speed_downgraded = false;
1522 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1525 phy->speed_downgraded = (phy_data & mask) ? true : false;
1532 * igb_check_polarity_m88 - Checks the polarity.
1533 * @hw: pointer to the HW structure
1535 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1537 * Polarity is determined based on the PHY specific status register.
1539 s32 igb_check_polarity_m88(struct e1000_hw *hw)
1541 struct e1000_phy_info *phy = &hw->phy;
1545 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1548 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1549 ? e1000_rev_polarity_reversed
1550 : e1000_rev_polarity_normal;
1556 * igb_check_polarity_igp - Checks the polarity.
1557 * @hw: pointer to the HW structure
1559 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1561 * Polarity is determined based on the PHY port status register, and the
1562 * current speed (since there is no polarity at 100Mbps).
1564 static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1566 struct e1000_phy_info *phy = &hw->phy;
1568 u16 data, offset, mask;
1570 /* Polarity is determined based on the speed of
1573 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1577 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1578 IGP01E1000_PSSR_SPEED_1000MBPS) {
1579 offset = IGP01E1000_PHY_PCS_INIT_REG;
1580 mask = IGP01E1000_PHY_POLARITY_MASK;
1582 /* This really only applies to 10Mbps since
1583 * there is no polarity for 100Mbps (always 0).
1585 offset = IGP01E1000_PHY_PORT_STATUS;
1586 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1589 ret_val = phy->ops.read_reg(hw, offset, &data);
1592 phy->cable_polarity = (data & mask)
1593 ? e1000_rev_polarity_reversed
1594 : e1000_rev_polarity_normal;
1601 * igb_wait_autoneg - Wait for auto-neg completion
1602 * @hw: pointer to the HW structure
1604 * Waits for auto-negotiation to complete or for the auto-negotiation time
1605 * limit to expire, which ever happens first.
1607 static s32 igb_wait_autoneg(struct e1000_hw *hw)
1612 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1613 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1614 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1617 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1620 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1625 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1632 * igb_phy_has_link - Polls PHY for link
1633 * @hw: pointer to the HW structure
1634 * @iterations: number of times to poll for link
1635 * @usec_interval: delay between polling attempts
1636 * @success: pointer to whether polling was successful or not
1638 * Polls the PHY status register for link, 'iterations' number of times.
1640 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1641 u32 usec_interval, bool *success)
1646 for (i = 0; i < iterations; i++) {
1647 /* Some PHYs require the PHY_STATUS register to be read
1648 * twice due to the link bit being sticky. No harm doing
1649 * it across the board.
1651 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1652 if (ret_val && usec_interval > 0) {
1653 /* If the first read fails, another entity may have
1654 * ownership of the resources, wait and try again to
1655 * see if they have relinquished the resources yet.
1657 if (usec_interval >= 1000)
1658 mdelay(usec_interval/1000);
1660 udelay(usec_interval);
1662 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1665 if (phy_status & MII_SR_LINK_STATUS)
1667 if (usec_interval >= 1000)
1668 mdelay(usec_interval/1000);
1670 udelay(usec_interval);
1673 *success = (i < iterations) ? true : false;
1679 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1680 * @hw: pointer to the HW structure
1682 * Reads the PHY specific status register to retrieve the cable length
1683 * information. The cable length is determined by averaging the minimum and
1684 * maximum values to get the "average" cable length. The m88 PHY has four
1685 * possible cable length values, which are:
1686 * Register Value Cable Length
1690 * 3 110 - 140 meters
1693 s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1695 struct e1000_phy_info *phy = &hw->phy;
1697 u16 phy_data, index;
1699 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1703 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1704 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1705 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
1706 ret_val = -E1000_ERR_PHY;
1710 phy->min_cable_length = e1000_m88_cable_length_table[index];
1711 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1713 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1719 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1721 struct e1000_phy_info *phy = &hw->phy;
1723 u16 phy_data, phy_data2, index, default_page, is_cm;
1725 switch (hw->phy.id) {
1727 /* Get cable length from PHY Cable Diagnostics Control Reg */
1728 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1729 (I347AT4_PCDL + phy->addr),
1734 /* Check if the unit of cable length is meters or cm */
1735 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1736 I347AT4_PCDC, &phy_data2);
1740 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1742 /* Populate the phy structure with cable length in meters */
1743 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1744 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1745 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1747 case M88E1543_E_PHY_ID:
1748 case M88E1512_E_PHY_ID:
1749 case I347AT4_E_PHY_ID:
1750 /* Remember the original page select and set it to 7 */
1751 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1756 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1760 /* Get cable length from PHY Cable Diagnostics Control Reg */
1761 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
1766 /* Check if the unit of cable length is meters or cm */
1767 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1771 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1773 /* Populate the phy structure with cable length in meters */
1774 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1775 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1776 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1778 /* Reset the page selec to its original value */
1779 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1784 case M88E1112_E_PHY_ID:
1785 /* Remember the original page select and set it to 5 */
1786 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1791 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1795 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1800 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1801 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1802 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
1803 ret_val = -E1000_ERR_PHY;
1807 phy->min_cable_length = e1000_m88_cable_length_table[index];
1808 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1810 phy->cable_length = (phy->min_cable_length +
1811 phy->max_cable_length) / 2;
1813 /* Reset the page select to its original value */
1814 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1821 ret_val = -E1000_ERR_PHY;
1830 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1831 * @hw: pointer to the HW structure
1833 * The automatic gain control (agc) normalizes the amplitude of the
1834 * received signal, adjusting for the attenuation produced by the
1835 * cable. By reading the AGC registers, which represent the
1836 * combination of coarse and fine gain value, the value can be put
1837 * into a lookup table to obtain the approximate cable length
1840 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1842 struct e1000_phy_info *phy = &hw->phy;
1844 u16 phy_data, i, agc_value = 0;
1845 u16 cur_agc_index, max_agc_index = 0;
1846 u16 min_agc_index = ARRAY_SIZE(e1000_igp_2_cable_length_table) - 1;
1847 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1848 IGP02E1000_PHY_AGC_A,
1849 IGP02E1000_PHY_AGC_B,
1850 IGP02E1000_PHY_AGC_C,
1851 IGP02E1000_PHY_AGC_D
1854 /* Read the AGC registers for all channels */
1855 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1856 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1860 /* Getting bits 15:9, which represent the combination of
1861 * coarse and fine gain values. The result is a number
1862 * that can be put into the lookup table to obtain the
1863 * approximate cable length.
1865 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1866 IGP02E1000_AGC_LENGTH_MASK;
1868 /* Array index bound check. */
1869 if ((cur_agc_index >= ARRAY_SIZE(e1000_igp_2_cable_length_table)) ||
1870 (cur_agc_index == 0)) {
1871 ret_val = -E1000_ERR_PHY;
1875 /* Remove min & max AGC values from calculation. */
1876 if (e1000_igp_2_cable_length_table[min_agc_index] >
1877 e1000_igp_2_cable_length_table[cur_agc_index])
1878 min_agc_index = cur_agc_index;
1879 if (e1000_igp_2_cable_length_table[max_agc_index] <
1880 e1000_igp_2_cable_length_table[cur_agc_index])
1881 max_agc_index = cur_agc_index;
1883 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1886 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1887 e1000_igp_2_cable_length_table[max_agc_index]);
1888 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1890 /* Calculate cable length with the error range of +/- 10 meters. */
1891 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1892 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1893 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1895 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1902 * igb_get_phy_info_m88 - Retrieve PHY information
1903 * @hw: pointer to the HW structure
1905 * Valid for only copper links. Read the PHY status register (sticky read)
1906 * to verify that link is up. Read the PHY special control register to
1907 * determine the polarity and 10base-T extended distance. Read the PHY
1908 * special status register to determine MDI/MDIx and current speed. If
1909 * speed is 1000, then determine cable length, local and remote receiver.
1911 s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1913 struct e1000_phy_info *phy = &hw->phy;
1918 if (phy->media_type != e1000_media_type_copper) {
1919 hw_dbg("Phy info is only valid for copper media\n");
1920 ret_val = -E1000_ERR_CONFIG;
1924 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1929 hw_dbg("Phy info is only valid if link is up\n");
1930 ret_val = -E1000_ERR_CONFIG;
1934 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1938 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1941 ret_val = igb_check_polarity_m88(hw);
1945 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1949 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1951 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1952 ret_val = phy->ops.get_cable_length(hw);
1956 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1960 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1961 ? e1000_1000t_rx_status_ok
1962 : e1000_1000t_rx_status_not_ok;
1964 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1965 ? e1000_1000t_rx_status_ok
1966 : e1000_1000t_rx_status_not_ok;
1968 /* Set values to "undefined" */
1969 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1970 phy->local_rx = e1000_1000t_rx_status_undefined;
1971 phy->remote_rx = e1000_1000t_rx_status_undefined;
1979 * igb_get_phy_info_igp - Retrieve igp PHY information
1980 * @hw: pointer to the HW structure
1982 * Read PHY status to determine if link is up. If link is up, then
1983 * set/determine 10base-T extended distance and polarity correction. Read
1984 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1985 * determine on the cable length, local and remote receiver.
1987 s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1989 struct e1000_phy_info *phy = &hw->phy;
1994 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1999 hw_dbg("Phy info is only valid if link is up\n");
2000 ret_val = -E1000_ERR_CONFIG;
2004 phy->polarity_correction = true;
2006 ret_val = igb_check_polarity_igp(hw);
2010 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2014 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2016 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2017 IGP01E1000_PSSR_SPEED_1000MBPS) {
2018 ret_val = phy->ops.get_cable_length(hw);
2022 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2026 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2027 ? e1000_1000t_rx_status_ok
2028 : e1000_1000t_rx_status_not_ok;
2030 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2031 ? e1000_1000t_rx_status_ok
2032 : e1000_1000t_rx_status_not_ok;
2034 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2035 phy->local_rx = e1000_1000t_rx_status_undefined;
2036 phy->remote_rx = e1000_1000t_rx_status_undefined;
2044 * igb_phy_sw_reset - PHY software reset
2045 * @hw: pointer to the HW structure
2047 * Does a software reset of the PHY by reading the PHY control register and
2048 * setting/write the control register reset bit to the PHY.
2050 s32 igb_phy_sw_reset(struct e1000_hw *hw)
2055 if (!(hw->phy.ops.read_reg))
2058 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2062 phy_ctrl |= MII_CR_RESET;
2063 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2074 * igb_phy_hw_reset - PHY hardware reset
2075 * @hw: pointer to the HW structure
2077 * Verify the reset block is not blocking us from resetting. Acquire
2078 * semaphore (if necessary) and read/set/write the device control reset
2079 * bit in the PHY. Wait the appropriate delay time for the device to
2080 * reset and release the semaphore (if necessary).
2082 s32 igb_phy_hw_reset(struct e1000_hw *hw)
2084 struct e1000_phy_info *phy = &hw->phy;
2088 ret_val = igb_check_reset_block(hw);
2094 ret_val = phy->ops.acquire(hw);
2098 ctrl = rd32(E1000_CTRL);
2099 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2102 udelay(phy->reset_delay_us);
2104 wr32(E1000_CTRL, ctrl);
2109 phy->ops.release(hw);
2111 ret_val = phy->ops.get_cfg_done(hw);
2118 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
2119 * @hw: pointer to the HW structure
2121 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2123 s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2125 hw_dbg("Running IGP 3 PHY init script\n");
2127 /* PHY init IGP 3 */
2128 /* Enable rise/fall, 10-mode work in class-A */
2129 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2130 /* Remove all caps from Replica path filter */
2131 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2132 /* Bias trimming for ADC, AFE and Driver (Default) */
2133 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2134 /* Increase Hybrid poly bias */
2135 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2136 /* Add 4% to TX amplitude in Giga mode */
2137 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2138 /* Disable trimming (TTT) */
2139 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2140 /* Poly DC correction to 94.6% + 2% for all channels */
2141 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2142 /* ABS DC correction to 95.9% */
2143 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2144 /* BG temp curve trim */
2145 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2146 /* Increasing ADC OPAMP stage 1 currents to max */
2147 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2148 /* Force 1000 ( required for enabling PHY regs configuration) */
2149 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2150 /* Set upd_freq to 6 */
2151 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2153 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2154 /* Disable adaptive fixed FFE (Default) */
2155 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2156 /* Enable FFE hysteresis */
2157 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2158 /* Fixed FFE for short cable lengths */
2159 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2160 /* Fixed FFE for medium cable lengths */
2161 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2162 /* Fixed FFE for long cable lengths */
2163 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2164 /* Enable Adaptive Clip Threshold */
2165 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2166 /* AHT reset limit to 1 */
2167 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2168 /* Set AHT master delay to 127 msec */
2169 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2170 /* Set scan bits for AHT */
2171 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2172 /* Set AHT Preset bits */
2173 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2174 /* Change integ_factor of channel A to 3 */
2175 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2176 /* Change prop_factor of channels BCD to 8 */
2177 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2178 /* Change cg_icount + enable integbp for channels BCD */
2179 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2180 /* Change cg_icount + enable integbp + change prop_factor_master
2181 * to 8 for channel A
2183 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2184 /* Disable AHT in Slave mode on channel A */
2185 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2186 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2189 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2190 /* Enable restart AN on an1000_dis change */
2191 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2192 /* Enable wh_fifo read clock in 10/100 modes */
2193 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2194 /* Restart AN, Speed selection is 1000 */
2195 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2201 * igb_initialize_M88E1512_phy - Initialize M88E1512 PHY
2202 * @hw: pointer to the HW structure
2204 * Initialize Marvel 1512 to work correctly with Avoton.
2206 s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw)
2208 struct e1000_phy_info *phy = &hw->phy;
2211 /* Switch to PHY page 0xFF. */
2212 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2216 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2220 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2224 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2228 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2232 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2236 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2240 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2244 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2248 /* Switch to PHY page 0xFB. */
2249 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2253 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2257 /* Switch to PHY page 0x12. */
2258 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2262 /* Change mode to SGMII-to-Copper */
2263 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2267 /* Return the PHY to page 0. */
2268 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2272 ret_val = igb_phy_sw_reset(hw);
2274 hw_dbg("Error committing the PHY changes\n");
2278 /* msec_delay(1000); */
2279 usleep_range(1000, 2000);
2285 * igb_power_up_phy_copper - Restore copper link in case of PHY power down
2286 * @hw: pointer to the HW structure
2288 * In the case of a PHY power down to save power, or to turn off link during a
2289 * driver unload, restore the link to previous settings.
2291 void igb_power_up_phy_copper(struct e1000_hw *hw)
2295 /* The PHY will retain its settings across a power down/up cycle */
2296 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2297 mii_reg &= ~MII_CR_POWER_DOWN;
2298 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2302 * igb_power_down_phy_copper - Power down copper PHY
2303 * @hw: pointer to the HW structure
2305 * Power down PHY to save power when interface is down and wake on lan
2308 void igb_power_down_phy_copper(struct e1000_hw *hw)
2312 /* The PHY will retain its settings across a power down/up cycle */
2313 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2314 mii_reg |= MII_CR_POWER_DOWN;
2315 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2316 usleep_range(1000, 2000);
2320 * igb_check_polarity_82580 - Checks the polarity.
2321 * @hw: pointer to the HW structure
2323 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2325 * Polarity is determined based on the PHY specific status register.
2327 static s32 igb_check_polarity_82580(struct e1000_hw *hw)
2329 struct e1000_phy_info *phy = &hw->phy;
2334 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2337 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2338 ? e1000_rev_polarity_reversed
2339 : e1000_rev_polarity_normal;
2345 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
2346 * @hw: pointer to the HW structure
2348 * Calls the PHY setup function to force speed and duplex. Clears the
2349 * auto-crossover to force MDI manually. Waits for link and returns
2350 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2352 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
2354 struct e1000_phy_info *phy = &hw->phy;
2359 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2363 igb_phy_force_speed_duplex_setup(hw, &phy_data);
2365 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2369 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI
2370 * forced whenever speed and duplex are forced.
2372 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2376 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
2378 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2382 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
2386 if (phy->autoneg_wait_to_complete) {
2387 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2389 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2394 hw_dbg("Link taking longer than expected.\n");
2397 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2407 * igb_get_phy_info_82580 - Retrieve I82580 PHY information
2408 * @hw: pointer to the HW structure
2410 * Read PHY status to determine if link is up. If link is up, then
2411 * set/determine 10base-T extended distance and polarity correction. Read
2412 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2413 * determine on the cable length, local and remote receiver.
2415 s32 igb_get_phy_info_82580(struct e1000_hw *hw)
2417 struct e1000_phy_info *phy = &hw->phy;
2422 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2427 hw_dbg("Phy info is only valid if link is up\n");
2428 ret_val = -E1000_ERR_CONFIG;
2432 phy->polarity_correction = true;
2434 ret_val = igb_check_polarity_82580(hw);
2438 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2442 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2444 if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
2445 I82580_PHY_STATUS2_SPEED_1000MBPS) {
2446 ret_val = hw->phy.ops.get_cable_length(hw);
2450 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2454 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2455 ? e1000_1000t_rx_status_ok
2456 : e1000_1000t_rx_status_not_ok;
2458 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2459 ? e1000_1000t_rx_status_ok
2460 : e1000_1000t_rx_status_not_ok;
2462 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2463 phy->local_rx = e1000_1000t_rx_status_undefined;
2464 phy->remote_rx = e1000_1000t_rx_status_undefined;
2472 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY
2473 * @hw: pointer to the HW structure
2475 * Reads the diagnostic status register and verifies result is valid before
2476 * placing it in the phy_cable_length field.
2478 s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2480 struct e1000_phy_info *phy = &hw->phy;
2482 u16 phy_data, length;
2484 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2488 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
2489 I82580_DSTATUS_CABLE_LENGTH_SHIFT;
2491 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2492 ret_val = -E1000_ERR_PHY;
2494 phy->cable_length = length;
2501 * igb_write_phy_reg_gs40g - Write GS40G PHY register
2502 * @hw: pointer to the HW structure
2503 * @offset: lower half is register offset to write to
2504 * upper half is page to use.
2505 * @data: data to write at register offset
2507 * Acquires semaphore, if necessary, then writes the data to PHY register
2508 * at the offset. Release any acquired semaphores before exiting.
2510 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
2513 u16 page = offset >> GS40G_PAGE_SHIFT;
2515 offset = offset & GS40G_OFFSET_MASK;
2516 ret_val = hw->phy.ops.acquire(hw);
2520 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2523 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2526 hw->phy.ops.release(hw);
2531 * igb_read_phy_reg_gs40g - Read GS40G PHY register
2532 * @hw: pointer to the HW structure
2533 * @offset: lower half is register offset to read to
2534 * upper half is page to use.
2535 * @data: data to read at register offset
2537 * Acquires semaphore, if necessary, then reads the data in the PHY register
2538 * at the offset. Release any acquired semaphores before exiting.
2540 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
2543 u16 page = offset >> GS40G_PAGE_SHIFT;
2545 offset = offset & GS40G_OFFSET_MASK;
2546 ret_val = hw->phy.ops.acquire(hw);
2550 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2553 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2556 hw->phy.ops.release(hw);
2561 * igb_set_master_slave_mode - Setup PHY for Master/slave mode
2562 * @hw: pointer to the HW structure
2564 * Sets up Master/slave mode
2566 static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2571 /* Resolve Master/Slave mode */
2572 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2576 /* load defaults for future use */
2577 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2578 ((phy_data & CR_1000T_MS_VALUE) ?
2579 e1000_ms_force_master :
2580 e1000_ms_force_slave) : e1000_ms_auto;
2582 switch (hw->phy.ms_type) {
2583 case e1000_ms_force_master:
2584 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2586 case e1000_ms_force_slave:
2587 phy_data |= CR_1000T_MS_ENABLE;
2588 phy_data &= ~(CR_1000T_MS_VALUE);
2591 phy_data &= ~CR_1000T_MS_ENABLE;
2597 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);