drivers/net/ethernet/intel/igb/e1000_82575.c

   1 /* Intel(R) Gigabit Ethernet Linux driver
   2  * Copyright(c) 2007-2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, see <http://www.gnu.org/licenses/>.
  15  *
  16  * The full GNU General Public License is included in this distribution in
  17  * the file called "COPYING".
  18  *
  19  * Contact Information:
  20  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  */
  23
  24 /* e1000_82575
  25  * e1000_82576
  26  */
  27
  28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29
  30 #include <linux/types.h>
  31 #include <linux/if_ether.h>
  32 #include <linux/i2c.h>
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36 #include "e1000_i210.h"
  37 #include "igb.h"
  38
  39 static s32  igb_get_invariants_82575(struct e1000_hw *);
  40 static s32  igb_acquire_phy_82575(struct e1000_hw *);
  41 static void igb_release_phy_82575(struct e1000_hw *);
  42 static s32  igb_acquire_nvm_82575(struct e1000_hw *);
  43 static void igb_release_nvm_82575(struct e1000_hw *);
  44 static s32  igb_check_for_link_82575(struct e1000_hw *);
  45 static s32  igb_get_cfg_done_82575(struct e1000_hw *);
  46 static s32  igb_init_hw_82575(struct e1000_hw *);
  47 static s32  igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
  48 static s32  igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
  49 static s32  igb_reset_hw_82575(struct e1000_hw *);
  50 static s32  igb_reset_hw_82580(struct e1000_hw *);
  51 static s32  igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
  52 static s32  igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
  53 static s32  igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
  54 static s32  igb_setup_copper_link_82575(struct e1000_hw *);
  55 static s32  igb_setup_serdes_link_82575(struct e1000_hw *);
  56 static s32  igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
  57 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
  58 static s32  igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
  59 static s32  igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
  60                                                  u16 *);
  61 static s32  igb_get_phy_id_82575(struct e1000_hw *);
  62 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
  63 static bool igb_sgmii_active_82575(struct e1000_hw *);
  64 static s32  igb_reset_init_script_82575(struct e1000_hw *);
  65 static s32  igb_read_mac_addr_82575(struct e1000_hw *);
  66 static s32  igb_set_pcie_completion_timeout(struct e1000_hw *hw);
  67 static s32  igb_reset_mdicnfg_82580(struct e1000_hw *hw);
  68 static s32  igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
  69 static s32  igb_update_nvm_checksum_82580(struct e1000_hw *hw);
  70 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
  71 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
  72 static const u16 e1000_82580_rxpbs_table[] = {
  73         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
  74
  75 /* Due to a hw errata, if the host tries to  configure the VFTA register
  76  * while performing queries from the BMC or DMA, then the VFTA in some
  77  * cases won't be written.
  78  */
  79
  80 /**
  81  *  igb_write_vfta_i350 - Write value to VLAN filter table
  82  *  @hw: pointer to the HW structure
  83  *  @offset: register offset in VLAN filter table
  84  *  @value: register value written to VLAN filter table
  85  *
  86  *  Writes value at the given offset in the register array which stores
  87  *  the VLAN filter table.
  88  **/
  89 static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
  90 {
  91         struct igb_adapter *adapter = hw->back;
  92         int i;
  93
  94         for (i = 10; i--;)
  95                 array_wr32(E1000_VFTA, offset, value);
  96
  97         wrfl();
  98         adapter->shadow_vfta[offset] = value;
  99 }
 100
 101 /**
 102  *  igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 103  *  @hw: pointer to the HW structure
 104  *
 105  *  Called to determine if the I2C pins are being used for I2C or as an
 106  *  external MDIO interface since the two options are mutually exclusive.
 107  **/
 108 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 109 {
 110         u32 reg = 0;
 111         bool ext_mdio = false;
 112
 113         switch (hw->mac.type) {
 114         case e1000_82575:
 115         case e1000_82576:
 116                 reg = rd32(E1000_MDIC);
 117                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 118                 break;
 119         case e1000_82580:
 120         case e1000_i350:
 121         case e1000_i354:
 122         case e1000_i210:
 123         case e1000_i211:
 124                 reg = rd32(E1000_MDICNFG);
 125                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 126                 break;
 127         default:
 128                 break;
 129         }
 130         return ext_mdio;
 131 }
 132
 133 /**
 134  *  igb_check_for_link_media_swap - Check which M88E1112 interface linked
 135  *  @hw: pointer to the HW structure
 136  *
 137  *  Poll the M88E1112 interfaces to see which interface achieved link.
 138  */
 139 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
 140 {
 141         struct e1000_phy_info *phy = &hw->phy;
 142         s32 ret_val;
 143         u16 data;
 144         u8 port = 0;
 145
 146         /* Check the copper medium. */
 147         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 148         if (ret_val)
 149                 return ret_val;
 150
 151         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
 152         if (ret_val)
 153                 return ret_val;
 154
 155         if (data & E1000_M88E1112_STATUS_LINK)
 156                 port = E1000_MEDIA_PORT_COPPER;
 157
 158         /* Check the other medium. */
 159         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
 160         if (ret_val)
 161                 return ret_val;
 162
 163         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
 164         if (ret_val)
 165                 return ret_val;
 166
 167
 168         if (data & E1000_M88E1112_STATUS_LINK)
 169                 port = E1000_MEDIA_PORT_OTHER;
 170
 171         /* Determine if a swap needs to happen. */
 172         if (port && (hw->dev_spec._82575.media_port != port)) {
 173                 hw->dev_spec._82575.media_port = port;
 174                 hw->dev_spec._82575.media_changed = true;
 175         }
 176
 177         if (port == E1000_MEDIA_PORT_COPPER) {
 178                 /* reset page to 0 */
 179                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 180                 if (ret_val)
 181                         return ret_val;
 182                 igb_check_for_link_82575(hw);
 183         } else {
 184                 igb_check_for_link_82575(hw);
 185                 /* reset page to 0 */
 186                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 187                 if (ret_val)
 188                         return ret_val;
 189         }
 190
 191         return 0;
 192 }
 193
 194 /**
 195  *  igb_init_phy_params_82575 - Init PHY func ptrs.
 196  *  @hw: pointer to the HW structure
 197  **/
 198 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
 199 {
 200         struct e1000_phy_info *phy = &hw->phy;
 201         s32 ret_val = 0;
 202         u32 ctrl_ext;
 203
 204         if (hw->phy.media_type != e1000_media_type_copper) {
 205                 phy->type = e1000_phy_none;
 206                 goto out;
 207         }
 208
 209         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 210         phy->reset_delay_us     = 100;
 211
 212         ctrl_ext = rd32(E1000_CTRL_EXT);
 213
 214         if (igb_sgmii_active_82575(hw)) {
 215                 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
 216                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 217         } else {
 218                 phy->ops.reset = igb_phy_hw_reset;
 219                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 220         }
 221
 222         wr32(E1000_CTRL_EXT, ctrl_ext);
 223         igb_reset_mdicnfg_82580(hw);
 224
 225         if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
 226                 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
 227                 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
 228         } else {
 229                 switch (hw->mac.type) {
 230                 case e1000_82580:
 231                 case e1000_i350:
 232                 case e1000_i354:
 233                 case e1000_i210:
 234                 case e1000_i211:
 235                         phy->ops.read_reg = igb_read_phy_reg_82580;
 236                         phy->ops.write_reg = igb_write_phy_reg_82580;
 237                         break;
 238                 default:
 239                         phy->ops.read_reg = igb_read_phy_reg_igp;
 240                         phy->ops.write_reg = igb_write_phy_reg_igp;
 241                 }
 242         }
 243
 244         /* set lan id */
 245         hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
 246                         E1000_STATUS_FUNC_SHIFT;
 247
 248         /* Set phy->phy_addr and phy->id. */
 249         ret_val = igb_get_phy_id_82575(hw);
 250         if (ret_val)
 251                 return ret_val;
 252
 253         /* Verify phy id and set remaining function pointers */
 254         switch (phy->id) {
 255         case M88E1543_E_PHY_ID:
 256         case M88E1512_E_PHY_ID:
 257         case I347AT4_E_PHY_ID:
 258         case M88E1112_E_PHY_ID:
 259         case M88E1111_I_PHY_ID:
 260                 phy->type               = e1000_phy_m88;
 261                 phy->ops.check_polarity = igb_check_polarity_m88;
 262                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 263                 if (phy->id != M88E1111_I_PHY_ID)
 264                         phy->ops.get_cable_length =
 265                                          igb_get_cable_length_m88_gen2;
 266                 else
 267                         phy->ops.get_cable_length = igb_get_cable_length_m88;
 268                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 269                 /* Check if this PHY is configured for media swap. */
 270                 if (phy->id == M88E1112_E_PHY_ID) {
 271                         u16 data;
 272
 273                         ret_val = phy->ops.write_reg(hw,
 274                                                      E1000_M88E1112_PAGE_ADDR,
 275                                                      2);
 276                         if (ret_val)
 277                                 goto out;
 278
 279                         ret_val = phy->ops.read_reg(hw,
 280                                                     E1000_M88E1112_MAC_CTRL_1,
 281                                                     &data);
 282                         if (ret_val)
 283                                 goto out;
 284
 285                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 286                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 287                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 288                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 289                                 hw->mac.ops.check_for_link =
 290                                                 igb_check_for_link_media_swap;
 291                 }
 292                 if (phy->id == M88E1512_E_PHY_ID) {
 293                         ret_val = igb_initialize_M88E1512_phy(hw);
 294                         if (ret_val)
 295                                 goto out;
 296                 }
 297                 if (phy->id == M88E1543_E_PHY_ID) {
 298                         ret_val = igb_initialize_M88E1543_phy(hw);
 299                         if (ret_val)
 300                                 goto out;
 301                 }
 302                 break;
 303         case IGP03E1000_E_PHY_ID:
 304                 phy->type = e1000_phy_igp_3;
 305                 phy->ops.get_phy_info = igb_get_phy_info_igp;
 306                 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
 307                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
 308                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
 309                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
 310                 break;
 311         case I82580_I_PHY_ID:
 312         case I350_I_PHY_ID:
 313                 phy->type = e1000_phy_82580;
 314                 phy->ops.force_speed_duplex =
 315                                          igb_phy_force_speed_duplex_82580;
 316                 phy->ops.get_cable_length = igb_get_cable_length_82580;
 317                 phy->ops.get_phy_info = igb_get_phy_info_82580;
 318                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 319                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 320                 break;
 321         case I210_I_PHY_ID:
 322                 phy->type               = e1000_phy_i210;
 323                 phy->ops.check_polarity = igb_check_polarity_m88;
 324                 phy->ops.get_cfg_done   = igb_get_cfg_done_i210;
 325                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 326                 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
 327                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 328                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 329                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 330                 break;
 331         default:
 332                 ret_val = -E1000_ERR_PHY;
 333                 goto out;
 334         }
 335
 336 out:
 337         return ret_val;
 338 }
 339
 340 /**
 341  *  igb_init_nvm_params_82575 - Init NVM func ptrs.
 342  *  @hw: pointer to the HW structure
 343  **/
 344 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
 345 {
 346         struct e1000_nvm_info *nvm = &hw->nvm;
 347         u32 eecd = rd32(E1000_EECD);
 348         u16 size;
 349
 350         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 351                      E1000_EECD_SIZE_EX_SHIFT);
 352
 353         /* Added to a constant, "size" becomes the left-shift value
 354          * for setting word_size.
 355          */
 356         size += NVM_WORD_SIZE_BASE_SHIFT;
 357
 358         /* Just in case size is out of range, cap it to the largest
 359          * EEPROM size supported
 360          */
 361         if (size > 15)
 362                 size = 15;
 363
 364         nvm->word_size = BIT(size);
 365         nvm->opcode_bits = 8;
 366         nvm->delay_usec = 1;
 367
 368         switch (nvm->override) {
 369         case e1000_nvm_override_spi_large:
 370                 nvm->page_size = 32;
 371                 nvm->address_bits = 16;
 372                 break;
 373         case e1000_nvm_override_spi_small:
 374                 nvm->page_size = 8;
 375                 nvm->address_bits = 8;
 376                 break;
 377         default:
 378                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 379                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 380                                     16 : 8;
 381                 break;
 382         }
 383         if (nvm->word_size == BIT(15))
 384                 nvm->page_size = 128;
 385
 386         nvm->type = e1000_nvm_eeprom_spi;
 387
 388         /* NVM Function Pointers */
 389         nvm->ops.acquire = igb_acquire_nvm_82575;
 390         nvm->ops.release = igb_release_nvm_82575;
 391         nvm->ops.write = igb_write_nvm_spi;
 392         nvm->ops.validate = igb_validate_nvm_checksum;
 393         nvm->ops.update = igb_update_nvm_checksum;
 394         if (nvm->word_size < BIT(15))
 395                 nvm->ops.read = igb_read_nvm_eerd;
 396         else
 397                 nvm->ops.read = igb_read_nvm_spi;
 398
 399         /* override generic family function pointers for specific descendants */
 400         switch (hw->mac.type) {
 401         case e1000_82580:
 402                 nvm->ops.validate = igb_validate_nvm_checksum_82580;
 403                 nvm->ops.update = igb_update_nvm_checksum_82580;
 404                 break;
 405         case e1000_i354:
 406         case e1000_i350:
 407                 nvm->ops.validate = igb_validate_nvm_checksum_i350;
 408                 nvm->ops.update = igb_update_nvm_checksum_i350;
 409                 break;
 410         default:
 411                 break;
 412         }
 413
 414         return 0;
 415 }
 416
 417 /**
 418  *  igb_init_mac_params_82575 - Init MAC func ptrs.
 419  *  @hw: pointer to the HW structure
 420  **/
 421 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
 422 {
 423         struct e1000_mac_info *mac = &hw->mac;
 424         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 425
 426         /* Set mta register count */
 427         mac->mta_reg_count = 128;
 428         /* Set uta register count */
 429         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 430         /* Set rar entry count */
 431         switch (mac->type) {
 432         case e1000_82576:
 433                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 434                 break;
 435         case e1000_82580:
 436                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 437                 break;
 438         case e1000_i350:
 439         case e1000_i354:
 440                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 441                 break;
 442         default:
 443                 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 444                 break;
 445         }
 446         /* reset */
 447         if (mac->type >= e1000_82580)
 448                 mac->ops.reset_hw = igb_reset_hw_82580;
 449         else
 450                 mac->ops.reset_hw = igb_reset_hw_82575;
 451
 452         if (mac->type >= e1000_i210) {
 453                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
 454                 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
 455
 456         } else {
 457                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
 458                 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
 459         }
 460
 461         if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
 462                 mac->ops.write_vfta = igb_write_vfta_i350;
 463         else
 464                 mac->ops.write_vfta = igb_write_vfta;
 465
 466         /* Set if part includes ASF firmware */
 467         mac->asf_firmware_present = true;
 468         /* Set if manageability features are enabled. */
 469         mac->arc_subsystem_valid =
 470                 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
 471                         ? true : false;
 472         /* enable EEE on i350 parts and later parts */
 473         if (mac->type >= e1000_i350)
 474                 dev_spec->eee_disable = false;
 475         else
 476                 dev_spec->eee_disable = true;
 477         /* Allow a single clear of the SW semaphore on I210 and newer */
 478         if (mac->type >= e1000_i210)
 479                 dev_spec->clear_semaphore_once = true;
 480         /* physical interface link setup */
 481         mac->ops.setup_physical_interface =
 482                 (hw->phy.media_type == e1000_media_type_copper)
 483                         ? igb_setup_copper_link_82575
 484                         : igb_setup_serdes_link_82575;
 485
 486         if (mac->type == e1000_82580) {
 487                 switch (hw->device_id) {
 488                 /* feature not supported on these id's */
 489                 case E1000_DEV_ID_DH89XXCC_SGMII:
 490                 case E1000_DEV_ID_DH89XXCC_SERDES:
 491                 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
 492                 case E1000_DEV_ID_DH89XXCC_SFP:
 493                         break;
 494                 default:
 495                         hw->dev_spec._82575.mas_capable = true;
 496                         break;
 497                 }
 498         }
 499         return 0;
 500 }
 501
 502 /**
 503  *  igb_set_sfp_media_type_82575 - derives SFP module media type.
 504  *  @hw: pointer to the HW structure
 505  *
 506  *  The media type is chosen based on SFP module.
 507  *  compatibility flags retrieved from SFP ID EEPROM.
 508  **/
 509 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
 510 {
 511         s32 ret_val = E1000_ERR_CONFIG;
 512         u32 ctrl_ext = 0;
 513         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 514         struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
 515         u8 tranceiver_type = 0;
 516         s32 timeout = 3;
 517
 518         /* Turn I2C interface ON and power on sfp cage */
 519         ctrl_ext = rd32(E1000_CTRL_EXT);
 520         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
 521         wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
 522
 523         wrfl();
 524
 525         /* Read SFP module data */
 526         while (timeout) {
 527                 ret_val = igb_read_sfp_data_byte(hw,
 528                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
 529                         &tranceiver_type);
 530                 if (ret_val == 0)
 531                         break;
 532                 msleep(100);
 533                 timeout--;
 534         }
 535         if (ret_val != 0)
 536                 goto out;
 537
 538         ret_val = igb_read_sfp_data_byte(hw,
 539                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
 540                         (u8 *)eth_flags);
 541         if (ret_val != 0)
 542                 goto out;
 543
 544         /* Check if there is some SFP module plugged and powered */
 545         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
 546             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
 547                 dev_spec->module_plugged = true;
 548                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
 549                         hw->phy.media_type = e1000_media_type_internal_serdes;
 550                 } else if (eth_flags->e100_base_fx) {
 551                         dev_spec->sgmii_active = true;
 552                         hw->phy.media_type = e1000_media_type_internal_serdes;
 553                 } else if (eth_flags->e1000_base_t) {
 554                         dev_spec->sgmii_active = true;
 555                         hw->phy.media_type = e1000_media_type_copper;
 556                 } else {
 557                         hw->phy.media_type = e1000_media_type_unknown;
 558                         hw_dbg("PHY module has not been recognized\n");
 559                         goto out;
 560                 }
 561         } else {
 562                 hw->phy.media_type = e1000_media_type_unknown;
 563         }
 564         ret_val = 0;
 565 out:
 566         /* Restore I2C interface setting */
 567         wr32(E1000_CTRL_EXT, ctrl_ext);
 568         return ret_val;
 569 }
 570
 571 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
 572 {
 573         struct e1000_mac_info *mac = &hw->mac;
 574         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 575         s32 ret_val;
 576         u32 ctrl_ext = 0;
 577         u32 link_mode = 0;
 578
 579         switch (hw->device_id) {
 580         case E1000_DEV_ID_82575EB_COPPER:
 581         case E1000_DEV_ID_82575EB_FIBER_SERDES:
 582         case E1000_DEV_ID_82575GB_QUAD_COPPER:
 583                 mac->type = e1000_82575;
 584                 break;
 585         case E1000_DEV_ID_82576:
 586         case E1000_DEV_ID_82576_NS:
 587         case E1000_DEV_ID_82576_NS_SERDES:
 588         case E1000_DEV_ID_82576_FIBER:
 589         case E1000_DEV_ID_82576_SERDES:
 590         case E1000_DEV_ID_82576_QUAD_COPPER:
 591         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
 592         case E1000_DEV_ID_82576_SERDES_QUAD:
 593                 mac->type = e1000_82576;
 594                 break;
 595         case E1000_DEV_ID_82580_COPPER:
 596         case E1000_DEV_ID_82580_FIBER:
 597         case E1000_DEV_ID_82580_QUAD_FIBER:
 598         case E1000_DEV_ID_82580_SERDES:
 599         case E1000_DEV_ID_82580_SGMII:
 600         case E1000_DEV_ID_82580_COPPER_DUAL:
 601         case E1000_DEV_ID_DH89XXCC_SGMII:
 602         case E1000_DEV_ID_DH89XXCC_SERDES:
 603         case E1000_DEV_ID_DH89XXCC_BACKPLANE:
 604         case E1000_DEV_ID_DH89XXCC_SFP:
 605                 mac->type = e1000_82580;
 606                 break;
 607         case E1000_DEV_ID_I350_COPPER:
 608         case E1000_DEV_ID_I350_FIBER:
 609         case E1000_DEV_ID_I350_SERDES:
 610         case E1000_DEV_ID_I350_SGMII:
 611                 mac->type = e1000_i350;
 612                 break;
 613         case E1000_DEV_ID_I210_COPPER:
 614         case E1000_DEV_ID_I210_FIBER:
 615         case E1000_DEV_ID_I210_SERDES:
 616         case E1000_DEV_ID_I210_SGMII:
 617         case E1000_DEV_ID_I210_COPPER_FLASHLESS:
 618         case E1000_DEV_ID_I210_SERDES_FLASHLESS:
 619                 mac->type = e1000_i210;
 620                 break;
 621         case E1000_DEV_ID_I211_COPPER:
 622                 mac->type = e1000_i211;
 623                 break;
 624         case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
 625         case E1000_DEV_ID_I354_SGMII:
 626         case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
 627                 mac->type = e1000_i354;
 628                 break;
 629         default:
 630                 return -E1000_ERR_MAC_INIT;
 631         }
 632
 633         /* Set media type */
 634         /* The 82575 uses bits 22:23 for link mode. The mode can be changed
 635          * based on the EEPROM. We cannot rely upon device ID. There
 636          * is no distinguishable difference between fiber and internal
 637          * SerDes mode on the 82575. There can be an external PHY attached
 638          * on the SGMII interface. For this, we'll set sgmii_active to true.
 639          */
 640         hw->phy.media_type = e1000_media_type_copper;
 641         dev_spec->sgmii_active = false;
 642         dev_spec->module_plugged = false;
 643
 644         ctrl_ext = rd32(E1000_CTRL_EXT);
 645
 646         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
 647         switch (link_mode) {
 648         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
 649                 hw->phy.media_type = e1000_media_type_internal_serdes;
 650                 break;
 651         case E1000_CTRL_EXT_LINK_MODE_SGMII:
 652                 /* Get phy control interface type set (MDIO vs. I2C)*/
 653                 if (igb_sgmii_uses_mdio_82575(hw)) {
 654                         hw->phy.media_type = e1000_media_type_copper;
 655                         dev_spec->sgmii_active = true;
 656                         break;
 657                 }
 658                 /* fall through for I2C based SGMII */
 659         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
 660                 /* read media type from SFP EEPROM */
 661                 ret_val = igb_set_sfp_media_type_82575(hw);
 662                 if ((ret_val != 0) ||
 663                     (hw->phy.media_type == e1000_media_type_unknown)) {
 664                         /* If media type was not identified then return media
 665                          * type defined by the CTRL_EXT settings.
 666                          */
 667                         hw->phy.media_type = e1000_media_type_internal_serdes;
 668
 669                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
 670                                 hw->phy.media_type = e1000_media_type_copper;
 671                                 dev_spec->sgmii_active = true;
 672                         }
 673
 674                         break;
 675                 }
 676
 677                 /* do not change link mode for 100BaseFX */
 678                 if (dev_spec->eth_flags.e100_base_fx)
 679                         break;
 680
 681                 /* change current link mode setting */
 682                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
 683
 684                 if (hw->phy.media_type == e1000_media_type_copper)
 685                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
 686                 else
 687                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
 688
 689                 wr32(E1000_CTRL_EXT, ctrl_ext);
 690
 691                 break;
 692         default:
 693                 break;
 694         }
 695
 696         /* mac initialization and operations */
 697         ret_val = igb_init_mac_params_82575(hw);
 698         if (ret_val)
 699                 goto out;
 700
 701         /* NVM initialization */
 702         ret_val = igb_init_nvm_params_82575(hw);
 703         switch (hw->mac.type) {
 704         case e1000_i210:
 705         case e1000_i211:
 706                 ret_val = igb_init_nvm_params_i210(hw);
 707                 break;
 708         default:
 709                 break;
 710         }
 711
 712         if (ret_val)
 713                 goto out;
 714
 715         /* if part supports SR-IOV then initialize mailbox parameters */
 716         switch (mac->type) {
 717         case e1000_82576:
 718         case e1000_i350:
 719                 igb_init_mbx_params_pf(hw);
 720                 break;
 721         default:
 722                 break;
 723         }
 724
 725         /* setup PHY parameters */
 726         ret_val = igb_init_phy_params_82575(hw);
 727
 728 out:
 729         return ret_val;
 730 }
 731
 732 /**
 733  *  igb_acquire_phy_82575 - Acquire rights to access PHY
 734  *  @hw: pointer to the HW structure
 735  *
 736  *  Acquire access rights to the correct PHY.  This is a
 737  *  function pointer entry point called by the api module.
 738  **/
 739 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
 740 {
 741         u16 mask = E1000_SWFW_PHY0_SM;
 742
 743         if (hw->bus.func == E1000_FUNC_1)
 744                 mask = E1000_SWFW_PHY1_SM;
 745         else if (hw->bus.func == E1000_FUNC_2)
 746                 mask = E1000_SWFW_PHY2_SM;
 747         else if (hw->bus.func == E1000_FUNC_3)
 748                 mask = E1000_SWFW_PHY3_SM;
 749
 750         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 751 }
 752
 753 /**
 754  *  igb_release_phy_82575 - Release rights to access PHY
 755  *  @hw: pointer to the HW structure
 756  *
 757  *  A wrapper to release access rights to the correct PHY.  This is a
 758  *  function pointer entry point called by the api module.
 759  **/
 760 static void igb_release_phy_82575(struct e1000_hw *hw)
 761 {
 762         u16 mask = E1000_SWFW_PHY0_SM;
 763
 764         if (hw->bus.func == E1000_FUNC_1)
 765                 mask = E1000_SWFW_PHY1_SM;
 766         else if (hw->bus.func == E1000_FUNC_2)
 767                 mask = E1000_SWFW_PHY2_SM;
 768         else if (hw->bus.func == E1000_FUNC_3)
 769                 mask = E1000_SWFW_PHY3_SM;
 770
 771         hw->mac.ops.release_swfw_sync(hw, mask);
 772 }
 773
 774 /**
 775  *  igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 776  *  @hw: pointer to the HW structure
 777  *  @offset: register offset to be read
 778  *  @data: pointer to the read data
 779  *
 780  *  Reads the PHY register at offset using the serial gigabit media independent
 781  *  interface and stores the retrieved information in data.
 782  **/
 783 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 784                                           u16 *data)
 785 {
 786         s32 ret_val = -E1000_ERR_PARAM;
 787
 788         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 789                 hw_dbg("PHY Address %u is out of range\n", offset);
 790                 goto out;
 791         }
 792
 793         ret_val = hw->phy.ops.acquire(hw);
 794         if (ret_val)
 795                 goto out;
 796
 797         ret_val = igb_read_phy_reg_i2c(hw, offset, data);
 798
 799         hw->phy.ops.release(hw);
 800
 801 out:
 802         return ret_val;
 803 }
 804
 805 /**
 806  *  igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 807  *  @hw: pointer to the HW structure
 808  *  @offset: register offset to write to
 809  *  @data: data to write at register offset
 810  *
 811  *  Writes the data to PHY register at the offset using the serial gigabit
 812  *  media independent interface.
 813  **/
 814 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 815                                            u16 data)
 816 {
 817         s32 ret_val = -E1000_ERR_PARAM;
 818
 819
 820         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 821                 hw_dbg("PHY Address %d is out of range\n", offset);
 822                 goto out;
 823         }
 824
 825         ret_val = hw->phy.ops.acquire(hw);
 826         if (ret_val)
 827                 goto out;
 828
 829         ret_val = igb_write_phy_reg_i2c(hw, offset, data);
 830
 831         hw->phy.ops.release(hw);
 832
 833 out:
 834         return ret_val;
 835 }
 836
 837 /**
 838  *  igb_get_phy_id_82575 - Retrieve PHY addr and id
 839  *  @hw: pointer to the HW structure
 840  *
 841  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 842  *  sgmi interface.
 843  **/
 844 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
 845 {
 846         struct e1000_phy_info *phy = &hw->phy;
 847         s32  ret_val = 0;
 848         u16 phy_id;
 849         u32 ctrl_ext;
 850         u32 mdic;
 851
 852         /* Extra read required for some PHY's on i354 */
 853         if (hw->mac.type == e1000_i354)
 854                 igb_get_phy_id(hw);
 855
 856         /* For SGMII PHYs, we try the list of possible addresses until
 857          * we find one that works.  For non-SGMII PHYs
 858          * (e.g. integrated copper PHYs), an address of 1 should
 859          * work.  The result of this function should mean phy->phy_addr
 860          * and phy->id are set correctly.
 861          */
 862         if (!(igb_sgmii_active_82575(hw))) {
 863                 phy->addr = 1;
 864                 ret_val = igb_get_phy_id(hw);
 865                 goto out;
 866         }
 867
 868         if (igb_sgmii_uses_mdio_82575(hw)) {
 869                 switch (hw->mac.type) {
 870                 case e1000_82575:
 871                 case e1000_82576:
 872                         mdic = rd32(E1000_MDIC);
 873                         mdic &= E1000_MDIC_PHY_MASK;
 874                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 875                         break;
 876                 case e1000_82580:
 877                 case e1000_i350:
 878                 case e1000_i354:
 879                 case e1000_i210:
 880                 case e1000_i211:
 881                         mdic = rd32(E1000_MDICNFG);
 882                         mdic &= E1000_MDICNFG_PHY_MASK;
 883                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 884                         break;
 885                 default:
 886                         ret_val = -E1000_ERR_PHY;
 887                         goto out;
 888                 }
 889                 ret_val = igb_get_phy_id(hw);
 890                 goto out;
 891         }
 892
 893         /* Power on sgmii phy if it is disabled */
 894         ctrl_ext = rd32(E1000_CTRL_EXT);
 895         wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 896         wrfl();
 897         msleep(300);
 898
 899         /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
 900          * Therefore, we need to test 1-7
 901          */
 902         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 903                 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 904                 if (ret_val == 0) {
 905                         hw_dbg("Vendor ID 0x%08X read at address %u\n",
 906                                phy_id, phy->addr);
 907                         /* At the time of this writing, The M88 part is
 908                          * the only supported SGMII PHY product.
 909                          */
 910                         if (phy_id == M88_VENDOR)
 911                                 break;
 912                 } else {
 913                         hw_dbg("PHY address %u was unreadable\n", phy->addr);
 914                 }
 915         }
 916
 917         /* A valid PHY type couldn't be found. */
 918         if (phy->addr == 8) {
 919                 phy->addr = 0;
 920                 ret_val = -E1000_ERR_PHY;
 921                 goto out;
 922         } else {
 923                 ret_val = igb_get_phy_id(hw);
 924         }
 925
 926         /* restore previous sfp cage power state */
 927         wr32(E1000_CTRL_EXT, ctrl_ext);
 928
 929 out:
 930         return ret_val;
 931 }
 932
 933 /**
 934  *  igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 935  *  @hw: pointer to the HW structure
 936  *
 937  *  Resets the PHY using the serial gigabit media independent interface.
 938  **/
 939 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 940 {
 941         struct e1000_phy_info *phy = &hw->phy;
 942         s32 ret_val;
 943
 944         /* This isn't a true "hard" reset, but is the only reset
 945          * available to us at this time.
 946          */
 947
 948         hw_dbg("Soft resetting SGMII attached PHY...\n");
 949
 950         /* SFP documentation requires the following to configure the SPF module
 951          * to work on SGMII.  No further documentation is given.
 952          */
 953         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 954         if (ret_val)
 955                 goto out;
 956
 957         ret_val = igb_phy_sw_reset(hw);
 958         if (ret_val)
 959                 goto out;
 960
 961         if (phy->id == M88E1512_E_PHY_ID)
 962                 ret_val = igb_initialize_M88E1512_phy(hw);
 963         if (phy->id == M88E1543_E_PHY_ID)
 964                 ret_val = igb_initialize_M88E1543_phy(hw);
 965 out:
 966         return ret_val;
 967 }
 968
 969 /**
 970  *  igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 971  *  @hw: pointer to the HW structure
 972  *  @active: true to enable LPLU, false to disable
 973  *
 974  *  Sets the LPLU D0 state according to the active flag.  When
 975  *  activating LPLU this function also disables smart speed
 976  *  and vice versa.  LPLU will not be activated unless the
 977  *  device autonegotiation advertisement meets standards of
 978  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 979  *  This is a function pointer entry point only called by
 980  *  PHY setup routines.
 981  **/
 982 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 983 {
 984         struct e1000_phy_info *phy = &hw->phy;
 985         s32 ret_val;
 986         u16 data;
 987
 988         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 989         if (ret_val)
 990                 goto out;
 991
 992         if (active) {
 993                 data |= IGP02E1000_PM_D0_LPLU;
 994                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 995                                                  data);
 996                 if (ret_val)
 997                         goto out;
 998
 999                 /* When LPLU is enabled, we should disable SmartSpeed */
1000                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1001                                                 &data);
1002                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1003                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1004                                                  data);
1005                 if (ret_val)
1006                         goto out;
1007         } else {
1008                 data &= ~IGP02E1000_PM_D0_LPLU;
1009                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1010                                                  data);
1011                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1012                  * during Dx states where the power conservation is most
1013                  * important.  During driver activity we should enable
1014                  * SmartSpeed, so performance is maintained.
1015                  */
1016                 if (phy->smart_speed == e1000_smart_speed_on) {
1017                         ret_val = phy->ops.read_reg(hw,
1018                                         IGP01E1000_PHY_PORT_CONFIG, &data);
1019                         if (ret_val)
1020                                 goto out;
1021
1022                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1023                         ret_val = phy->ops.write_reg(hw,
1024                                         IGP01E1000_PHY_PORT_CONFIG, data);
1025                         if (ret_val)
1026                                 goto out;
1027                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1028                         ret_val = phy->ops.read_reg(hw,
1029                                         IGP01E1000_PHY_PORT_CONFIG, &data);
1030                         if (ret_val)
1031                                 goto out;
1032
1033                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1034                         ret_val = phy->ops.write_reg(hw,
1035                                         IGP01E1000_PHY_PORT_CONFIG, data);
1036                         if (ret_val)
1037                                 goto out;
1038                 }
1039         }
1040
1041 out:
1042         return ret_val;
1043 }
1044
1045 /**
1046  *  igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
1047  *  @hw: pointer to the HW structure
1048  *  @active: true to enable LPLU, false to disable
1049  *
1050  *  Sets the LPLU D0 state according to the active flag.  When
1051  *  activating LPLU this function also disables smart speed
1052  *  and vice versa.  LPLU will not be activated unless the
1053  *  device autonegotiation advertisement meets standards of
1054  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1055  *  This is a function pointer entry point only called by
1056  *  PHY setup routines.
1057  **/
1058 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1059 {
1060         struct e1000_phy_info *phy = &hw->phy;
1061         u16 data;
1062
1063         data = rd32(E1000_82580_PHY_POWER_MGMT);
1064
1065         if (active) {
1066                 data |= E1000_82580_PM_D0_LPLU;
1067
1068                 /* When LPLU is enabled, we should disable SmartSpeed */
1069                 data &= ~E1000_82580_PM_SPD;
1070         } else {
1071                 data &= ~E1000_82580_PM_D0_LPLU;
1072
1073                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1074                  * during Dx states where the power conservation is most
1075                  * important.  During driver activity we should enable
1076                  * SmartSpeed, so performance is maintained.
1077                  */
1078                 if (phy->smart_speed == e1000_smart_speed_on)
1079                         data |= E1000_82580_PM_SPD;
1080                 else if (phy->smart_speed == e1000_smart_speed_off)
1081                         data &= ~E1000_82580_PM_SPD; }
1082
1083         wr32(E1000_82580_PHY_POWER_MGMT, data);
1084         return 0;
1085 }
1086
1087 /**
1088  *  igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1089  *  @hw: pointer to the HW structure
1090  *  @active: boolean used to enable/disable lplu
1091  *
1092  *  Success returns 0, Failure returns 1
1093  *
1094  *  The low power link up (lplu) state is set to the power management level D3
1095  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
1096  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
1097  *  is used during Dx states where the power conservation is most important.
1098  *  During driver activity, SmartSpeed should be enabled so performance is
1099  *  maintained.
1100  **/
1101 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1102 {
1103         struct e1000_phy_info *phy = &hw->phy;
1104         u16 data;
1105
1106         data = rd32(E1000_82580_PHY_POWER_MGMT);
1107
1108         if (!active) {
1109                 data &= ~E1000_82580_PM_D3_LPLU;
1110                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1111                  * during Dx states where the power conservation is most
1112                  * important.  During driver activity we should enable
1113                  * SmartSpeed, so performance is maintained.
1114                  */
1115                 if (phy->smart_speed == e1000_smart_speed_on)
1116                         data |= E1000_82580_PM_SPD;
1117                 else if (phy->smart_speed == e1000_smart_speed_off)
1118                         data &= ~E1000_82580_PM_SPD;
1119         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1120                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1121                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1122                 data |= E1000_82580_PM_D3_LPLU;
1123                 /* When LPLU is enabled, we should disable SmartSpeed */
1124                 data &= ~E1000_82580_PM_SPD;
1125         }
1126
1127         wr32(E1000_82580_PHY_POWER_MGMT, data);
1128         return 0;
1129 }
1130
1131 /**
1132  *  igb_acquire_nvm_82575 - Request for access to EEPROM
1133  *  @hw: pointer to the HW structure
1134  *
1135  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
1136  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
1137  *  Return successful if access grant bit set, else clear the request for
1138  *  EEPROM access and return -E1000_ERR_NVM (-1).
1139  **/
1140 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1141 {
1142         s32 ret_val;
1143
1144         ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1145         if (ret_val)
1146                 goto out;
1147
1148         ret_val = igb_acquire_nvm(hw);
1149
1150         if (ret_val)
1151                 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1152
1153 out:
1154         return ret_val;
1155 }
1156
1157 /**
1158  *  igb_release_nvm_82575 - Release exclusive access to EEPROM
1159  *  @hw: pointer to the HW structure
1160  *
1161  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1162  *  then release the semaphores acquired.
1163  **/
1164 static void igb_release_nvm_82575(struct e1000_hw *hw)
1165 {
1166         igb_release_nvm(hw);
1167         hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1168 }
1169
1170 /**
1171  *  igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1172  *  @hw: pointer to the HW structure
1173  *  @mask: specifies which semaphore to acquire
1174  *
1175  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1176  *  will also specify which port we're acquiring the lock for.
1177  **/
1178 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1179 {
1180         u32 swfw_sync;
1181         u32 swmask = mask;
1182         u32 fwmask = mask << 16;
1183         s32 ret_val = 0;
1184         s32 i = 0, timeout = 200;
1185
1186         while (i < timeout) {
1187                 if (igb_get_hw_semaphore(hw)) {
1188                         ret_val = -E1000_ERR_SWFW_SYNC;
1189                         goto out;
1190                 }
1191
1192                 swfw_sync = rd32(E1000_SW_FW_SYNC);
1193                 if (!(swfw_sync & (fwmask | swmask)))
1194                         break;
1195
1196                 /* Firmware currently using resource (fwmask)
1197                  * or other software thread using resource (swmask)
1198                  */
1199                 igb_put_hw_semaphore(hw);
1200                 mdelay(5);
1201                 i++;
1202         }
1203
1204         if (i == timeout) {
1205                 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1206                 ret_val = -E1000_ERR_SWFW_SYNC;
1207                 goto out;
1208         }
1209
1210         swfw_sync |= swmask;
1211         wr32(E1000_SW_FW_SYNC, swfw_sync);
1212
1213         igb_put_hw_semaphore(hw);
1214
1215 out:
1216         return ret_val;
1217 }
1218
1219 /**
1220  *  igb_release_swfw_sync_82575 - Release SW/FW semaphore
1221  *  @hw: pointer to the HW structure
1222  *  @mask: specifies which semaphore to acquire
1223  *
1224  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1225  *  will also specify which port we're releasing the lock for.
1226  **/
1227 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1228 {
1229         u32 swfw_sync;
1230
1231         while (igb_get_hw_semaphore(hw) != 0)
1232                 ; /* Empty */
1233
1234         swfw_sync = rd32(E1000_SW_FW_SYNC);
1235         swfw_sync &= ~mask;
1236         wr32(E1000_SW_FW_SYNC, swfw_sync);
1237
1238         igb_put_hw_semaphore(hw);
1239 }
1240
1241 /**
1242  *  igb_get_cfg_done_82575 - Read config done bit
1243  *  @hw: pointer to the HW structure
1244  *
1245  *  Read the management control register for the config done bit for
1246  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1247  *  to read the config done bit, so an error is *ONLY* logged and returns
1248  *  0.  If we were to return with error, EEPROM-less silicon
1249  *  would not be able to be reset or change link.
1250  **/
1251 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1252 {
1253         s32 timeout = PHY_CFG_TIMEOUT;
1254         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1255
1256         if (hw->bus.func == 1)
1257                 mask = E1000_NVM_CFG_DONE_PORT_1;
1258         else if (hw->bus.func == E1000_FUNC_2)
1259                 mask = E1000_NVM_CFG_DONE_PORT_2;
1260         else if (hw->bus.func == E1000_FUNC_3)
1261                 mask = E1000_NVM_CFG_DONE_PORT_3;
1262
1263         while (timeout) {
1264                 if (rd32(E1000_EEMNGCTL) & mask)
1265                         break;
1266                 usleep_range(1000, 2000);
1267                 timeout--;
1268         }
1269         if (!timeout)
1270                 hw_dbg("MNG configuration cycle has not completed.\n");
1271
1272         /* If EEPROM is not marked present, init the PHY manually */
1273         if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1274             (hw->phy.type == e1000_phy_igp_3))
1275                 igb_phy_init_script_igp3(hw);
1276
1277         return 0;
1278 }
1279
1280 /**
1281  *  igb_get_link_up_info_82575 - Get link speed/duplex info
1282  *  @hw: pointer to the HW structure
1283  *  @speed: stores the current speed
1284  *  @duplex: stores the current duplex
1285  *
1286  *  This is a wrapper function, if using the serial gigabit media independent
1287  *  interface, use PCS to retrieve the link speed and duplex information.
1288  *  Otherwise, use the generic function to get the link speed and duplex info.
1289  **/
1290 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1291                                         u16 *duplex)
1292 {
1293         s32 ret_val;
1294
1295         if (hw->phy.media_type != e1000_media_type_copper)
1296                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1297                                                                duplex);
1298         else
1299                 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1300                                                                     duplex);
1301
1302         return ret_val;
1303 }
1304
1305 /**
1306  *  igb_check_for_link_82575 - Check for link
1307  *  @hw: pointer to the HW structure
1308  *
1309  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1310  *  use the generic interface for determining link.
1311  **/
1312 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1313 {
1314         s32 ret_val;
1315         u16 speed, duplex;
1316
1317         if (hw->phy.media_type != e1000_media_type_copper) {
1318                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1319                                                              &duplex);
1320                 /* Use this flag to determine if link needs to be checked or
1321                  * not.  If  we have link clear the flag so that we do not
1322                  * continue to check for link.
1323                  */
1324                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1325
1326                 /* Configure Flow Control now that Auto-Neg has completed.
1327                  * First, we need to restore the desired flow control
1328                  * settings because we may have had to re-autoneg with a
1329                  * different link partner.
1330                  */
1331                 ret_val = igb_config_fc_after_link_up(hw);
1332                 if (ret_val)
1333                         hw_dbg("Error configuring flow control\n");
1334         } else {
1335                 ret_val = igb_check_for_copper_link(hw);
1336         }
1337
1338         return ret_val;
1339 }
1340
1341 /**
1342  *  igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1343  *  @hw: pointer to the HW structure
1344  **/
1345 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1346 {
1347         u32 reg;
1348
1349
1350         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1351             !igb_sgmii_active_82575(hw))
1352                 return;
1353
1354         /* Enable PCS to turn on link */
1355         reg = rd32(E1000_PCS_CFG0);
1356         reg |= E1000_PCS_CFG_PCS_EN;
1357         wr32(E1000_PCS_CFG0, reg);
1358
1359         /* Power up the laser */
1360         reg = rd32(E1000_CTRL_EXT);
1361         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1362         wr32(E1000_CTRL_EXT, reg);
1363
1364         /* flush the write to verify completion */
1365         wrfl();
1366         usleep_range(1000, 2000);
1367 }
1368
1369 /**
1370  *  igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1371  *  @hw: pointer to the HW structure
1372  *  @speed: stores the current speed
1373  *  @duplex: stores the current duplex
1374  *
1375  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1376  *  duplex, then store the values in the pointers provided.
1377  **/
1378 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1379                                                 u16 *duplex)
1380 {
1381         struct e1000_mac_info *mac = &hw->mac;
1382         u32 pcs, status;
1383
1384         /* Set up defaults for the return values of this function */
1385         mac->serdes_has_link = false;
1386         *speed = 0;
1387         *duplex = 0;
1388
1389         /* Read the PCS Status register for link state. For non-copper mode,
1390          * the status register is not accurate. The PCS status register is
1391          * used instead.
1392          */
1393         pcs = rd32(E1000_PCS_LSTAT);
1394
1395         /* The link up bit determines when link is up on autoneg. The sync ok
1396          * gets set once both sides sync up and agree upon link. Stable link
1397          * can be determined by checking for both link up and link sync ok
1398          */
1399         if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1400                 mac->serdes_has_link = true;
1401
1402                 /* Detect and store PCS speed */
1403                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1404                         *speed = SPEED_1000;
1405                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1406                         *speed = SPEED_100;
1407                 else
1408                         *speed = SPEED_10;
1409
1410                 /* Detect and store PCS duplex */
1411                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1412                         *duplex = FULL_DUPLEX;
1413                 else
1414                         *duplex = HALF_DUPLEX;
1415
1416         /* Check if it is an I354 2.5Gb backplane connection. */
1417                 if (mac->type == e1000_i354) {
1418                         status = rd32(E1000_STATUS);
1419                         if ((status & E1000_STATUS_2P5_SKU) &&
1420                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1421                                 *speed = SPEED_2500;
1422                                 *duplex = FULL_DUPLEX;
1423                                 hw_dbg("2500 Mbs, ");
1424                                 hw_dbg("Full Duplex\n");
1425                         }
1426                 }
1427
1428         }
1429
1430         return 0;
1431 }
1432
1433 /**
1434  *  igb_shutdown_serdes_link_82575 - Remove link during power down
1435  *  @hw: pointer to the HW structure
1436  *
1437  *  In the case of fiber serdes, shut down optics and PCS on driver unload
1438  *  when management pass thru is not enabled.
1439  **/
1440 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1441 {
1442         u32 reg;
1443
1444         if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1445             igb_sgmii_active_82575(hw))
1446                 return;
1447
1448         if (!igb_enable_mng_pass_thru(hw)) {
1449                 /* Disable PCS to turn off link */
1450                 reg = rd32(E1000_PCS_CFG0);
1451                 reg &= ~E1000_PCS_CFG_PCS_EN;
1452                 wr32(E1000_PCS_CFG0, reg);
1453
1454                 /* shutdown the laser */
1455                 reg = rd32(E1000_CTRL_EXT);
1456                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1457                 wr32(E1000_CTRL_EXT, reg);
1458
1459                 /* flush the write to verify completion */
1460                 wrfl();
1461                 usleep_range(1000, 2000);
1462         }
1463 }
1464
1465 /**
1466  *  igb_reset_hw_82575 - Reset hardware
1467  *  @hw: pointer to the HW structure
1468  *
1469  *  This resets the hardware into a known state.  This is a
1470  *  function pointer entry point called by the api module.
1471  **/
1472 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1473 {
1474         u32 ctrl;
1475         s32 ret_val;
1476
1477         /* Prevent the PCI-E bus from sticking if there is no TLP connection
1478          * on the last TLP read/write transaction when MAC is reset.
1479          */
1480         ret_val = igb_disable_pcie_master(hw);
1481         if (ret_val)
1482                 hw_dbg("PCI-E Master disable polling has failed.\n");
1483
1484         /* set the completion timeout for interface */
1485         ret_val = igb_set_pcie_completion_timeout(hw);
1486         if (ret_val)
1487                 hw_dbg("PCI-E Set completion timeout has failed.\n");
1488
1489         hw_dbg("Masking off all interrupts\n");
1490         wr32(E1000_IMC, 0xffffffff);
1491
1492         wr32(E1000_RCTL, 0);
1493         wr32(E1000_TCTL, E1000_TCTL_PSP);
1494         wrfl();
1495
1496         usleep_range(10000, 20000);
1497
1498         ctrl = rd32(E1000_CTRL);
1499
1500         hw_dbg("Issuing a global reset to MAC\n");
1501         wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1502
1503         ret_val = igb_get_auto_rd_done(hw);
1504         if (ret_val) {
1505                 /* When auto config read does not complete, do not
1506                  * return with an error. This can happen in situations
1507                  * where there is no eeprom and prevents getting link.
1508                  */
1509                 hw_dbg("Auto Read Done did not complete\n");
1510         }
1511
1512         /* If EEPROM is not present, run manual init scripts */
1513         if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1514                 igb_reset_init_script_82575(hw);
1515
1516         /* Clear any pending interrupt events. */
1517         wr32(E1000_IMC, 0xffffffff);
1518         rd32(E1000_ICR);
1519
1520         /* Install any alternate MAC address into RAR0 */
1521         ret_val = igb_check_alt_mac_addr(hw);
1522
1523         return ret_val;
1524 }
1525
1526 /**
1527  *  igb_init_hw_82575 - Initialize hardware
1528  *  @hw: pointer to the HW structure
1529  *
1530  *  This inits the hardware readying it for operation.
1531  **/
1532 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1533 {
1534         struct e1000_mac_info *mac = &hw->mac;
1535         s32 ret_val;
1536         u16 i, rar_count = mac->rar_entry_count;
1537
1538         if ((hw->mac.type >= e1000_i210) &&
1539             !(igb_get_flash_presence_i210(hw))) {
1540                 ret_val = igb_pll_workaround_i210(hw);
1541                 if (ret_val)
1542                         return ret_val;
1543         }
1544
1545         /* Initialize identification LED */
1546         ret_val = igb_id_led_init(hw);
1547         if (ret_val) {
1548                 hw_dbg("Error initializing identification LED\n");
1549                 /* This is not fatal and we should not stop init due to this */
1550         }
1551
1552         /* Disabling VLAN filtering */
1553         hw_dbg("Initializing the IEEE VLAN\n");
1554         igb_clear_vfta(hw);
1555
1556         /* Setup the receive address */
1557         igb_init_rx_addrs(hw, rar_count);
1558
1559         /* Zero out the Multicast HASH table */
1560         hw_dbg("Zeroing the MTA\n");
1561         for (i = 0; i < mac->mta_reg_count; i++)
1562                 array_wr32(E1000_MTA, i, 0);
1563
1564         /* Zero out the Unicast HASH table */
1565         hw_dbg("Zeroing the UTA\n");
1566         for (i = 0; i < mac->uta_reg_count; i++)
1567                 array_wr32(E1000_UTA, i, 0);
1568
1569         /* Setup link and flow control */
1570         ret_val = igb_setup_link(hw);
1571
1572         /* Clear all of the statistics registers (clear on read).  It is
1573          * important that we do this after we have tried to establish link
1574          * because the symbol error count will increment wildly if there
1575          * is no link.
1576          */
1577         igb_clear_hw_cntrs_82575(hw);
1578         return ret_val;
1579 }
1580
1581 /**
1582  *  igb_setup_copper_link_82575 - Configure copper link settings
1583  *  @hw: pointer to the HW structure
1584  *
1585  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1586  *  for link, once link is established calls to configure collision distance
1587  *  and flow control are called.
1588  **/
1589 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1590 {
1591         u32 ctrl;
1592         s32  ret_val;
1593         u32 phpm_reg;
1594
1595         ctrl = rd32(E1000_CTRL);
1596         ctrl |= E1000_CTRL_SLU;
1597         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1598         wr32(E1000_CTRL, ctrl);
1599
1600         /* Clear Go Link Disconnect bit on supported devices */
1601         switch (hw->mac.type) {
1602         case e1000_82580:
1603         case e1000_i350:
1604         case e1000_i210:
1605         case e1000_i211:
1606                 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1607                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1608                 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1609                 break;
1610         default:
1611                 break;
1612         }
1613
1614         ret_val = igb_setup_serdes_link_82575(hw);
1615         if (ret_val)
1616                 goto out;
1617
1618         if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1619                 /* allow time for SFP cage time to power up phy */
1620                 msleep(300);
1621
1622                 ret_val = hw->phy.ops.reset(hw);
1623                 if (ret_val) {
1624                         hw_dbg("Error resetting the PHY.\n");
1625                         goto out;
1626                 }
1627         }
1628         switch (hw->phy.type) {
1629         case e1000_phy_i210:
1630         case e1000_phy_m88:
1631                 switch (hw->phy.id) {
1632                 case I347AT4_E_PHY_ID:
1633                 case M88E1112_E_PHY_ID:
1634                 case M88E1543_E_PHY_ID:
1635                 case M88E1512_E_PHY_ID:
1636                 case I210_I_PHY_ID:
1637                         ret_val = igb_copper_link_setup_m88_gen2(hw);
1638                         break;
1639                 default:
1640                         ret_val = igb_copper_link_setup_m88(hw);
1641                         break;
1642                 }
1643                 break;
1644         case e1000_phy_igp_3:
1645                 ret_val = igb_copper_link_setup_igp(hw);
1646                 break;
1647         case e1000_phy_82580:
1648                 ret_val = igb_copper_link_setup_82580(hw);
1649                 break;
1650         default:
1651                 ret_val = -E1000_ERR_PHY;
1652                 break;
1653         }
1654
1655         if (ret_val)
1656                 goto out;
1657
1658         ret_val = igb_setup_copper_link(hw);
1659 out:
1660         return ret_val;
1661 }
1662
1663 /**
1664  *  igb_setup_serdes_link_82575 - Setup link for serdes
1665  *  @hw: pointer to the HW structure
1666  *
1667  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1668  *  used on copper connections where the serialized gigabit media independent
1669  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1670  *  for auto-negotiation or forces speed/duplex.
1671  **/
1672 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1673 {
1674         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1675         bool pcs_autoneg;
1676         s32 ret_val = 0;
1677         u16 data;
1678
1679         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1680             !igb_sgmii_active_82575(hw))
1681                 return ret_val;
1682
1683
1684         /* On the 82575, SerDes loopback mode persists until it is
1685          * explicitly turned off or a power cycle is performed.  A read to
1686          * the register does not indicate its status.  Therefore, we ensure
1687          * loopback mode is disabled during initialization.
1688          */
1689         wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1690
1691         /* power on the sfp cage if present and turn on I2C */
1692         ctrl_ext = rd32(E1000_CTRL_EXT);
1693         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1694         ctrl_ext |= E1000_CTRL_I2C_ENA;
1695         wr32(E1000_CTRL_EXT, ctrl_ext);
1696
1697         ctrl_reg = rd32(E1000_CTRL);
1698         ctrl_reg |= E1000_CTRL_SLU;
1699
1700         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1701                 /* set both sw defined pins */
1702                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1703
1704                 /* Set switch control to serdes energy detect */
1705                 reg = rd32(E1000_CONNSW);
1706                 reg |= E1000_CONNSW_ENRGSRC;
1707                 wr32(E1000_CONNSW, reg);
1708         }
1709
1710         reg = rd32(E1000_PCS_LCTL);
1711
1712         /* default pcs_autoneg to the same setting as mac autoneg */
1713         pcs_autoneg = hw->mac.autoneg;
1714
1715         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1716         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1717                 /* sgmii mode lets the phy handle forcing speed/duplex */
1718                 pcs_autoneg = true;
1719                 /* autoneg time out should be disabled for SGMII mode */
1720                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1721                 break;
1722         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1723                 /* disable PCS autoneg and support parallel detect only */
1724                 pcs_autoneg = false;
1725         default:
1726                 if (hw->mac.type == e1000_82575 ||
1727                     hw->mac.type == e1000_82576) {
1728                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1729                         if (ret_val) {
1730                                 hw_dbg(KERN_DEBUG "NVM Read Error\n\n");
1731                                 return ret_val;
1732                         }
1733
1734                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1735                                 pcs_autoneg = false;
1736                 }
1737
1738                 /* non-SGMII modes only supports a speed of 1000/Full for the
1739                  * link so it is best to just force the MAC and let the pcs
1740                  * link either autoneg or be forced to 1000/Full
1741                  */
1742                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1743                                 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1744
1745                 /* set speed of 1000/Full if speed/duplex is forced */
1746                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1747                 break;
1748         }
1749
1750         wr32(E1000_CTRL, ctrl_reg);
1751
1752         /* New SerDes mode allows for forcing speed or autonegotiating speed
1753          * at 1gb. Autoneg should be default set by most drivers. This is the
1754          * mode that will be compatible with older link partners and switches.
1755          * However, both are supported by the hardware and some drivers/tools.
1756          */
1757         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1758                 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1759
1760         if (pcs_autoneg) {
1761                 /* Set PCS register for autoneg */
1762                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1763                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1764
1765                 /* Disable force flow control for autoneg */
1766                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1767
1768                 /* Configure flow control advertisement for autoneg */
1769                 anadv_reg = rd32(E1000_PCS_ANADV);
1770                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1771                 switch (hw->fc.requested_mode) {
1772                 case e1000_fc_full:
1773                 case e1000_fc_rx_pause:
1774                         anadv_reg |= E1000_TXCW_ASM_DIR;
1775                         anadv_reg |= E1000_TXCW_PAUSE;
1776                         break;
1777                 case e1000_fc_tx_pause:
1778                         anadv_reg |= E1000_TXCW_ASM_DIR;
1779                         break;
1780                 default:
1781                         break;
1782                 }
1783                 wr32(E1000_PCS_ANADV, anadv_reg);
1784
1785                 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1786         } else {
1787                 /* Set PCS register for forced link */
1788                 reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
1789
1790                 /* Force flow control for forced link */
1791                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1792
1793                 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1794         }
1795
1796         wr32(E1000_PCS_LCTL, reg);
1797
1798         if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1799                 igb_force_mac_fc(hw);
1800
1801         return ret_val;
1802 }
1803
1804 /**
1805  *  igb_sgmii_active_82575 - Return sgmii state
1806  *  @hw: pointer to the HW structure
1807  *
1808  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1809  *  which can be enabled for use in the embedded applications.  Simply
1810  *  return the current state of the sgmii interface.
1811  **/
1812 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1813 {
1814         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1815         return dev_spec->sgmii_active;
1816 }
1817
1818 /**
1819  *  igb_reset_init_script_82575 - Inits HW defaults after reset
1820  *  @hw: pointer to the HW structure
1821  *
1822  *  Inits recommended HW defaults after a reset when there is no EEPROM
1823  *  detected. This is only for the 82575.
1824  **/
1825 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1826 {
1827         if (hw->mac.type == e1000_82575) {
1828                 hw_dbg("Running reset init script for 82575\n");
1829                 /* SerDes configuration via SERDESCTRL */
1830                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1831                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1832                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1833                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1834
1835                 /* CCM configuration via CCMCTL register */
1836                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1837                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1838
1839                 /* PCIe lanes configuration */
1840                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1841                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1842                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1843                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1844
1845                 /* PCIe PLL Configuration */
1846                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1847                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1848                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1849         }
1850
1851         return 0;
1852 }
1853
1854 /**
1855  *  igb_read_mac_addr_82575 - Read device MAC address
1856  *  @hw: pointer to the HW structure
1857  **/
1858 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1859 {
1860         s32 ret_val = 0;
1861
1862         /* If there's an alternate MAC address place it in RAR0
1863          * so that it will override the Si installed default perm
1864          * address.
1865          */
1866         ret_val = igb_check_alt_mac_addr(hw);
1867         if (ret_val)
1868                 goto out;
1869
1870         ret_val = igb_read_mac_addr(hw);
1871
1872 out:
1873         return ret_val;
1874 }
1875
1876 /**
1877  * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1878  * @hw: pointer to the HW structure
1879  *
1880  * In the case of a PHY power down to save power, or to turn off link during a
1881  * driver unload, or wake on lan is not enabled, remove the link.
1882  **/
1883 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1884 {
1885         /* If the management interface is not enabled, then power down */
1886         if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1887                 igb_power_down_phy_copper(hw);
1888 }
1889
1890 /**
1891  *  igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1892  *  @hw: pointer to the HW structure
1893  *
1894  *  Clears the hardware counters by reading the counter registers.
1895  **/
1896 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1897 {
1898         igb_clear_hw_cntrs_base(hw);
1899
1900         rd32(E1000_PRC64);
1901         rd32(E1000_PRC127);
1902         rd32(E1000_PRC255);
1903         rd32(E1000_PRC511);
1904         rd32(E1000_PRC1023);
1905         rd32(E1000_PRC1522);
1906         rd32(E1000_PTC64);
1907         rd32(E1000_PTC127);
1908         rd32(E1000_PTC255);
1909         rd32(E1000_PTC511);
1910         rd32(E1000_PTC1023);
1911         rd32(E1000_PTC1522);
1912
1913         rd32(E1000_ALGNERRC);
1914         rd32(E1000_RXERRC);
1915         rd32(E1000_TNCRS);
1916         rd32(E1000_CEXTERR);
1917         rd32(E1000_TSCTC);
1918         rd32(E1000_TSCTFC);
1919
1920         rd32(E1000_MGTPRC);
1921         rd32(E1000_MGTPDC);
1922         rd32(E1000_MGTPTC);
1923
1924         rd32(E1000_IAC);
1925         rd32(E1000_ICRXOC);
1926
1927         rd32(E1000_ICRXPTC);
1928         rd32(E1000_ICRXATC);
1929         rd32(E1000_ICTXPTC);
1930         rd32(E1000_ICTXATC);
1931         rd32(E1000_ICTXQEC);
1932         rd32(E1000_ICTXQMTC);
1933         rd32(E1000_ICRXDMTC);
1934
1935         rd32(E1000_CBTMPC);
1936         rd32(E1000_HTDPMC);
1937         rd32(E1000_CBRMPC);
1938         rd32(E1000_RPTHC);
1939         rd32(E1000_HGPTC);
1940         rd32(E1000_HTCBDPC);
1941         rd32(E1000_HGORCL);
1942         rd32(E1000_HGORCH);
1943         rd32(E1000_HGOTCL);
1944         rd32(E1000_HGOTCH);
1945         rd32(E1000_LENERRS);
1946
1947         /* This register should not be read in copper configurations */
1948         if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1949             igb_sgmii_active_82575(hw))
1950                 rd32(E1000_SCVPC);
1951 }
1952
1953 /**
1954  *  igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1955  *  @hw: pointer to the HW structure
1956  *
1957  *  After rx enable if manageability is enabled then there is likely some
1958  *  bad data at the start of the fifo and possibly in the DMA fifo. This
1959  *  function clears the fifos and flushes any packets that came in as rx was
1960  *  being enabled.
1961  **/
1962 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1963 {
1964         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1965         int i, ms_wait;
1966
1967         /* disable IPv6 options as per hardware errata */
1968         rfctl = rd32(E1000_RFCTL);
1969         rfctl |= E1000_RFCTL_IPV6_EX_DIS;
1970         wr32(E1000_RFCTL, rfctl);
1971
1972         if (hw->mac.type != e1000_82575 ||
1973             !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1974                 return;
1975
1976         /* Disable all RX queues */
1977         for (i = 0; i < 4; i++) {
1978                 rxdctl[i] = rd32(E1000_RXDCTL(i));
1979                 wr32(E1000_RXDCTL(i),
1980                      rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1981         }
1982         /* Poll all queues to verify they have shut down */
1983         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1984                 usleep_range(1000, 2000);
1985                 rx_enabled = 0;
1986                 for (i = 0; i < 4; i++)
1987                         rx_enabled |= rd32(E1000_RXDCTL(i));
1988                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1989                         break;
1990         }
1991
1992         if (ms_wait == 10)
1993                 hw_dbg("Queue disable timed out after 10ms\n");
1994
1995         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1996          * incoming packets are rejected.  Set enable and wait 2ms so that
1997          * any packet that was coming in as RCTL.EN was set is flushed
1998          */
1999         wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2000
2001         rlpml = rd32(E1000_RLPML);
2002         wr32(E1000_RLPML, 0);
2003
2004         rctl = rd32(E1000_RCTL);
2005         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2006         temp_rctl |= E1000_RCTL_LPE;
2007
2008         wr32(E1000_RCTL, temp_rctl);
2009         wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2010         wrfl();
2011         usleep_range(2000, 3000);
2012
2013         /* Enable RX queues that were previously enabled and restore our
2014          * previous state
2015          */
2016         for (i = 0; i < 4; i++)
2017                 wr32(E1000_RXDCTL(i), rxdctl[i]);
2018         wr32(E1000_RCTL, rctl);
2019         wrfl();
2020
2021         wr32(E1000_RLPML, rlpml);
2022         wr32(E1000_RFCTL, rfctl);
2023
2024         /* Flush receive errors generated by workaround */
2025         rd32(E1000_ROC);
2026         rd32(E1000_RNBC);
2027         rd32(E1000_MPC);
2028 }
2029
2030 /**
2031  *  igb_set_pcie_completion_timeout - set pci-e completion timeout
2032  *  @hw: pointer to the HW structure
2033  *
2034  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2035  *  however the hardware default for these parts is 500us to 1ms which is less
2036  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2037  *  increase the value to either 10ms to 200ms for capability version 1 config,
2038  *  or 16ms to 55ms for version 2.
2039  **/
2040 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
2041 {
2042         u32 gcr = rd32(E1000_GCR);
2043         s32 ret_val = 0;
2044         u16 pcie_devctl2;
2045
2046         /* only take action if timeout value is defaulted to 0 */
2047         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2048                 goto out;
2049
2050         /* if capabilities version is type 1 we can write the
2051          * timeout of 10ms to 200ms through the GCR register
2052          */
2053         if (!(gcr & E1000_GCR_CAP_VER2)) {
2054                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2055                 goto out;
2056         }
2057
2058         /* for version 2 capabilities we need to write the config space
2059          * directly in order to set the completion timeout value for
2060          * 16ms to 55ms
2061          */
2062         ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2063                                         &pcie_devctl2);
2064         if (ret_val)
2065                 goto out;
2066
2067         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2068
2069         ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2070                                          &pcie_devctl2);
2071 out:
2072         /* disable completion timeout resend */
2073         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2074
2075         wr32(E1000_GCR, gcr);
2076         return ret_val;
2077 }
2078
2079 /**
2080  *  igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2081  *  @hw: pointer to the hardware struct
2082  *  @enable: state to enter, either enabled or disabled
2083  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2084  *
2085  *  enables/disables L2 switch anti-spoofing functionality.
2086  **/
2087 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2088 {
2089         u32 reg_val, reg_offset;
2090
2091         switch (hw->mac.type) {
2092         case e1000_82576:
2093                 reg_offset = E1000_DTXSWC;
2094                 break;
2095         case e1000_i350:
2096         case e1000_i354:
2097                 reg_offset = E1000_TXSWC;
2098                 break;
2099         default:
2100                 return;
2101         }
2102
2103         reg_val = rd32(reg_offset);
2104         if (enable) {
2105                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2106                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2107                 /* The PF can spoof - it has to in order to
2108                  * support emulation mode NICs
2109                  */
2110                 reg_val ^= (BIT(pf) | BIT(pf + MAX_NUM_VFS));
2111         } else {
2112                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2113                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2114         }
2115         wr32(reg_offset, reg_val);
2116 }
2117
2118 /**
2119  *  igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2120  *  @hw: pointer to the hardware struct
2121  *  @enable: state to enter, either enabled or disabled
2122  *
2123  *  enables/disables L2 switch loopback functionality.
2124  **/
2125 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2126 {
2127         u32 dtxswc;
2128
2129         switch (hw->mac.type) {
2130         case e1000_82576:
2131                 dtxswc = rd32(E1000_DTXSWC);
2132                 if (enable)
2133                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2134                 else
2135                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2136                 wr32(E1000_DTXSWC, dtxswc);
2137                 break;
2138         case e1000_i354:
2139         case e1000_i350:
2140                 dtxswc = rd32(E1000_TXSWC);
2141                 if (enable)
2142                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2143                 else
2144                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2145                 wr32(E1000_TXSWC, dtxswc);
2146                 break;
2147         default:
2148                 /* Currently no other hardware supports loopback */
2149                 break;
2150         }
2151
2152 }
2153
2154 /**
2155  *  igb_vmdq_set_replication_pf - enable or disable vmdq replication
2156  *  @hw: pointer to the hardware struct
2157  *  @enable: state to enter, either enabled or disabled
2158  *
2159  *  enables/disables replication of packets across multiple pools.
2160  **/
2161 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2162 {
2163         u32 vt_ctl = rd32(E1000_VT_CTL);
2164
2165         if (enable)
2166                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2167         else
2168                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2169
2170         wr32(E1000_VT_CTL, vt_ctl);
2171 }
2172
2173 /**
2174  *  igb_read_phy_reg_82580 - Read 82580 MDI control register
2175  *  @hw: pointer to the HW structure
2176  *  @offset: register offset to be read
2177  *  @data: pointer to the read data
2178  *
2179  *  Reads the MDI control register in the PHY at offset and stores the
2180  *  information read to data.
2181  **/
2182 s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2183 {
2184         s32 ret_val;
2185
2186         ret_val = hw->phy.ops.acquire(hw);
2187         if (ret_val)
2188                 goto out;
2189
2190         ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2191
2192         hw->phy.ops.release(hw);
2193
2194 out:
2195         return ret_val;
2196 }
2197
2198 /**
2199  *  igb_write_phy_reg_82580 - Write 82580 MDI control register
2200  *  @hw: pointer to the HW structure
2201  *  @offset: register offset to write to
2202  *  @data: data to write to register at offset
2203  *
2204  *  Writes data to MDI control register in the PHY at offset.
2205  **/
2206 s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2207 {
2208         s32 ret_val;
2209
2210
2211         ret_val = hw->phy.ops.acquire(hw);
2212         if (ret_val)
2213                 goto out;
2214
2215         ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2216
2217         hw->phy.ops.release(hw);
2218
2219 out:
2220         return ret_val;
2221 }
2222
2223 /**
2224  *  igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2225  *  @hw: pointer to the HW structure
2226  *
2227  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2228  *  the values found in the EEPROM.  This addresses an issue in which these
2229  *  bits are not restored from EEPROM after reset.
2230  **/
2231 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2232 {
2233         s32 ret_val = 0;
2234         u32 mdicnfg;
2235         u16 nvm_data = 0;
2236
2237         if (hw->mac.type != e1000_82580)
2238                 goto out;
2239         if (!igb_sgmii_active_82575(hw))
2240                 goto out;
2241
2242         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2243                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2244                                    &nvm_data);
2245         if (ret_val) {
2246                 hw_dbg("NVM Read Error\n");
2247                 goto out;
2248         }
2249
2250         mdicnfg = rd32(E1000_MDICNFG);
2251         if (nvm_data & NVM_WORD24_EXT_MDIO)
2252                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2253         if (nvm_data & NVM_WORD24_COM_MDIO)
2254                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2255         wr32(E1000_MDICNFG, mdicnfg);
2256 out:
2257         return ret_val;
2258 }
2259
2260 /**
2261  *  igb_reset_hw_82580 - Reset hardware
2262  *  @hw: pointer to the HW structure
2263  *
2264  *  This resets function or entire device (all ports, etc.)
2265  *  to a known state.
2266  **/
2267 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2268 {
2269         s32 ret_val = 0;
2270         /* BH SW mailbox bit in SW_FW_SYNC */
2271         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2272         u32 ctrl;
2273         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2274
2275         hw->dev_spec._82575.global_device_reset = false;
2276
2277         /* due to hw errata, global device reset doesn't always
2278          * work on 82580
2279          */
2280         if (hw->mac.type == e1000_82580)
2281                 global_device_reset = false;
2282
2283         /* Get current control state. */
2284         ctrl = rd32(E1000_CTRL);
2285
2286         /* Prevent the PCI-E bus from sticking if there is no TLP connection
2287          * on the last TLP read/write transaction when MAC is reset.
2288          */
2289         ret_val = igb_disable_pcie_master(hw);
2290         if (ret_val)
2291                 hw_dbg("PCI-E Master disable polling has failed.\n");
2292
2293         hw_dbg("Masking off all interrupts\n");
2294         wr32(E1000_IMC, 0xffffffff);
2295         wr32(E1000_RCTL, 0);
2296         wr32(E1000_TCTL, E1000_TCTL_PSP);
2297         wrfl();
2298
2299         usleep_range(10000, 11000);
2300
2301         /* Determine whether or not a global dev reset is requested */
2302         if (global_device_reset &&
2303                 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2304                         global_device_reset = false;
2305
2306         if (global_device_reset &&
2307                 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2308                 ctrl |= E1000_CTRL_DEV_RST;
2309         else
2310                 ctrl |= E1000_CTRL_RST;
2311
2312         wr32(E1000_CTRL, ctrl);
2313         wrfl();
2314
2315         /* Add delay to insure DEV_RST has time to complete */
2316         if (global_device_reset)
2317                 usleep_range(5000, 6000);
2318
2319         ret_val = igb_get_auto_rd_done(hw);
2320         if (ret_val) {
2321                 /* When auto config read does not complete, do not
2322                  * return with an error. This can happen in situations
2323                  * where there is no eeprom and prevents getting link.
2324                  */
2325                 hw_dbg("Auto Read Done did not complete\n");
2326         }
2327
2328         /* clear global device reset status bit */
2329         wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2330
2331         /* Clear any pending interrupt events. */
2332         wr32(E1000_IMC, 0xffffffff);
2333         rd32(E1000_ICR);
2334
2335         ret_val = igb_reset_mdicnfg_82580(hw);
2336         if (ret_val)
2337                 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2338
2339         /* Install any alternate MAC address into RAR0 */
2340         ret_val = igb_check_alt_mac_addr(hw);
2341
2342         /* Release semaphore */
2343         if (global_device_reset)
2344                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2345
2346         return ret_val;
2347 }
2348
2349 /**
2350  *  igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2351  *  @data: data received by reading RXPBS register
2352  *
2353  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2354  *  This function converts the retrieved value into the correct table value
2355  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2356  *  0x0 36  72 144   1   2   4   8  16
2357  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2358  */
2359 u16 igb_rxpbs_adjust_82580(u32 data)
2360 {
2361         u16 ret_val = 0;
2362
2363         if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
2364                 ret_val = e1000_82580_rxpbs_table[data];
2365
2366         return ret_val;
2367 }
2368
2369 /**
2370  *  igb_validate_nvm_checksum_with_offset - Validate EEPROM
2371  *  checksum
2372  *  @hw: pointer to the HW structure
2373  *  @offset: offset in words of the checksum protected region
2374  *
2375  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2376  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2377  **/
2378 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2379                                                  u16 offset)
2380 {
2381         s32 ret_val = 0;
2382         u16 checksum = 0;
2383         u16 i, nvm_data;
2384
2385         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2386                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2387                 if (ret_val) {
2388                         hw_dbg("NVM Read Error\n");
2389                         goto out;
2390                 }
2391                 checksum += nvm_data;
2392         }
2393
2394         if (checksum != (u16) NVM_SUM) {
2395                 hw_dbg("NVM Checksum Invalid\n");
2396                 ret_val = -E1000_ERR_NVM;
2397                 goto out;
2398         }
2399
2400 out:
2401         return ret_val;
2402 }
2403
2404 /**
2405  *  igb_update_nvm_checksum_with_offset - Update EEPROM
2406  *  checksum
2407  *  @hw: pointer to the HW structure
2408  *  @offset: offset in words of the checksum protected region
2409  *
2410  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2411  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2412  *  value to the EEPROM.
2413  **/
2414 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2415 {
2416         s32 ret_val;
2417         u16 checksum = 0;
2418         u16 i, nvm_data;
2419
2420         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2421                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2422                 if (ret_val) {
2423                         hw_dbg("NVM Read Error while updating checksum.\n");
2424                         goto out;
2425                 }
2426                 checksum += nvm_data;
2427         }
2428         checksum = (u16) NVM_SUM - checksum;
2429         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2430                                 &checksum);
2431         if (ret_val)
2432                 hw_dbg("NVM Write Error while updating checksum.\n");
2433
2434 out:
2435         return ret_val;
2436 }
2437
2438 /**
2439  *  igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2440  *  @hw: pointer to the HW structure
2441  *
2442  *  Calculates the EEPROM section checksum by reading/adding each word of
2443  *  the EEPROM and then verifies that the sum of the EEPROM is
2444  *  equal to 0xBABA.
2445  **/
2446 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2447 {
2448         s32 ret_val = 0;
2449         u16 eeprom_regions_count = 1;
2450         u16 j, nvm_data;
2451         u16 nvm_offset;
2452
2453         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2454         if (ret_val) {
2455                 hw_dbg("NVM Read Error\n");
2456                 goto out;
2457         }
2458
2459         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2460                 /* if checksums compatibility bit is set validate checksums
2461                  * for all 4 ports.
2462                  */
2463                 eeprom_regions_count = 4;
2464         }
2465
2466         for (j = 0; j < eeprom_regions_count; j++) {
2467                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2468                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2469                                                                 nvm_offset);
2470                 if (ret_val != 0)
2471                         goto out;
2472         }
2473
2474 out:
2475         return ret_val;
2476 }
2477
2478 /**
2479  *  igb_update_nvm_checksum_82580 - Update EEPROM checksum
2480  *  @hw: pointer to the HW structure
2481  *
2482  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2483  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2484  *  checksum and writes the value to the EEPROM.
2485  **/
2486 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2487 {
2488         s32 ret_val;
2489         u16 j, nvm_data;
2490         u16 nvm_offset;
2491
2492         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2493         if (ret_val) {
2494                 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");
2495                 goto out;
2496         }
2497
2498         if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2499                 /* set compatibility bit to validate checksums appropriately */
2500                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2501                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2502                                         &nvm_data);
2503                 if (ret_val) {
2504                         hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");
2505                         goto out;
2506                 }
2507         }
2508
2509         for (j = 0; j < 4; j++) {
2510                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2511                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2512                 if (ret_val)
2513                         goto out;
2514         }
2515
2516 out:
2517         return ret_val;
2518 }
2519
2520 /**
2521  *  igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2522  *  @hw: pointer to the HW structure
2523  *
2524  *  Calculates the EEPROM section checksum by reading/adding each word of
2525  *  the EEPROM and then verifies that the sum of the EEPROM is
2526  *  equal to 0xBABA.
2527  **/
2528 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2529 {
2530         s32 ret_val = 0;
2531         u16 j;
2532         u16 nvm_offset;
2533
2534         for (j = 0; j < 4; j++) {
2535                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2536                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2537                                                                 nvm_offset);
2538                 if (ret_val != 0)
2539                         goto out;
2540         }
2541
2542 out:
2543         return ret_val;
2544 }
2545
2546 /**
2547  *  igb_update_nvm_checksum_i350 - Update EEPROM checksum
2548  *  @hw: pointer to the HW structure
2549  *
2550  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2551  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2552  *  checksum and writes the value to the EEPROM.
2553  **/
2554 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2555 {
2556         s32 ret_val = 0;
2557         u16 j;
2558         u16 nvm_offset;
2559
2560         for (j = 0; j < 4; j++) {
2561                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2562                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2563                 if (ret_val != 0)
2564                         goto out;
2565         }
2566
2567 out:
2568         return ret_val;
2569 }
2570
2571 /**
2572  *  __igb_access_emi_reg - Read/write EMI register
2573  *  @hw: pointer to the HW structure
2574  *  @addr: EMI address to program
2575  *  @data: pointer to value to read/write from/to the EMI address
2576  *  @read: boolean flag to indicate read or write
2577  **/
2578 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2579                                   u16 *data, bool read)
2580 {
2581         s32 ret_val = 0;
2582
2583         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2584         if (ret_val)
2585                 return ret_val;
2586
2587         if (read)
2588                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2589         else
2590                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2591
2592         return ret_val;
2593 }
2594
2595 /**
2596  *  igb_read_emi_reg - Read Extended Management Interface register
2597  *  @hw: pointer to the HW structure
2598  *  @addr: EMI address to program
2599  *  @data: value to be read from the EMI address
2600  **/
2601 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2602 {
2603         return __igb_access_emi_reg(hw, addr, data, true);
2604 }
2605
2606 /**
2607  *  igb_set_eee_i350 - Enable/disable EEE support
2608  *  @hw: pointer to the HW structure
2609  *  @adv1G: boolean flag enabling 1G EEE advertisement
2610  *  @adv100m: boolean flag enabling 100M EEE advertisement
2611  *
2612  *  Enable/disable EEE based on setting in dev_spec structure.
2613  *
2614  **/
2615 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2616 {
2617         u32 ipcnfg, eeer;
2618
2619         if ((hw->mac.type < e1000_i350) ||
2620             (hw->phy.media_type != e1000_media_type_copper))
2621                 goto out;
2622         ipcnfg = rd32(E1000_IPCNFG);
2623         eeer = rd32(E1000_EEER);
2624
2625         /* enable or disable per user setting */
2626         if (!(hw->dev_spec._82575.eee_disable)) {
2627                 u32 eee_su = rd32(E1000_EEE_SU);
2628
2629                 if (adv100M)
2630                         ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2631                 else
2632                         ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2633
2634                 if (adv1G)
2635                         ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2636                 else
2637                         ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2638
2639                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2640                         E1000_EEER_LPI_FC);
2641
2642                 /* This bit should not be set in normal operation. */
2643                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2644                         hw_dbg("LPI Clock Stop Bit should not be set!\n");
2645
2646         } else {
2647                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2648                         E1000_IPCNFG_EEE_100M_AN);
2649                 eeer &= ~(E1000_EEER_TX_LPI_EN |
2650                         E1000_EEER_RX_LPI_EN |
2651                         E1000_EEER_LPI_FC);
2652         }
2653         wr32(E1000_IPCNFG, ipcnfg);
2654         wr32(E1000_EEER, eeer);
2655         rd32(E1000_IPCNFG);
2656         rd32(E1000_EEER);
2657 out:
2658
2659         return 0;
2660 }
2661
2662 /**
2663  *  igb_set_eee_i354 - Enable/disable EEE support
2664  *  @hw: pointer to the HW structure
2665  *  @adv1G: boolean flag enabling 1G EEE advertisement
2666  *  @adv100m: boolean flag enabling 100M EEE advertisement
2667  *
2668  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2669  *
2670  **/
2671 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2672 {
2673         struct e1000_phy_info *phy = &hw->phy;
2674         s32 ret_val = 0;
2675         u16 phy_data;
2676
2677         if ((hw->phy.media_type != e1000_media_type_copper) ||
2678             ((phy->id != M88E1543_E_PHY_ID) &&
2679              (phy->id != M88E1512_E_PHY_ID)))
2680                 goto out;
2681
2682         if (!hw->dev_spec._82575.eee_disable) {
2683                 /* Switch to PHY page 18. */
2684                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2685                 if (ret_val)
2686                         goto out;
2687
2688                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2689                                             &phy_data);
2690                 if (ret_val)
2691                         goto out;
2692
2693                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2694                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2695                                              phy_data);
2696                 if (ret_val)
2697                         goto out;
2698
2699                 /* Return the PHY to page 0. */
2700                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2701                 if (ret_val)
2702                         goto out;
2703
2704                 /* Turn on EEE advertisement. */
2705                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2706                                              E1000_EEE_ADV_DEV_I354,
2707                                              &phy_data);
2708                 if (ret_val)
2709                         goto out;
2710
2711                 if (adv100M)
2712                         phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2713                 else
2714                         phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2715
2716                 if (adv1G)
2717                         phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2718                 else
2719                         phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2720
2721                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2722                                                 E1000_EEE_ADV_DEV_I354,
2723                                                 phy_data);
2724         } else {
2725                 /* Turn off EEE advertisement. */
2726                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2727                                              E1000_EEE_ADV_DEV_I354,
2728                                              &phy_data);
2729                 if (ret_val)
2730                         goto out;
2731
2732                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2733                               E1000_EEE_ADV_1000_SUPPORTED);
2734                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2735                                               E1000_EEE_ADV_DEV_I354,
2736                                               phy_data);
2737         }
2738
2739 out:
2740         return ret_val;
2741 }
2742
2743 /**
2744  *  igb_get_eee_status_i354 - Get EEE status
2745  *  @hw: pointer to the HW structure
2746  *  @status: EEE status
2747  *
2748  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
2749  *  been received.
2750  **/
2751 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2752 {
2753         struct e1000_phy_info *phy = &hw->phy;
2754         s32 ret_val = 0;
2755         u16 phy_data;
2756
2757         /* Check if EEE is supported on this device. */
2758         if ((hw->phy.media_type != e1000_media_type_copper) ||
2759             ((phy->id != M88E1543_E_PHY_ID) &&
2760              (phy->id != M88E1512_E_PHY_ID)))
2761                 goto out;
2762
2763         ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2764                                      E1000_PCS_STATUS_DEV_I354,
2765                                      &phy_data);
2766         if (ret_val)
2767                 goto out;
2768
2769         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2770                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2771
2772 out:
2773         return ret_val;
2774 }
2775
2776 static const u8 e1000_emc_temp_data[4] = {
2777         E1000_EMC_INTERNAL_DATA,
2778         E1000_EMC_DIODE1_DATA,
2779         E1000_EMC_DIODE2_DATA,
2780         E1000_EMC_DIODE3_DATA
2781 };
2782 static const u8 e1000_emc_therm_limit[4] = {
2783         E1000_EMC_INTERNAL_THERM_LIMIT,
2784         E1000_EMC_DIODE1_THERM_LIMIT,
2785         E1000_EMC_DIODE2_THERM_LIMIT,
2786         E1000_EMC_DIODE3_THERM_LIMIT
2787 };
2788
2789 #ifdef CONFIG_IGB_HWMON
2790 /**
2791  *  igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2792  *  @hw: pointer to hardware structure
2793  *
2794  *  Updates the temperatures in mac.thermal_sensor_data
2795  **/
2796 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2797 {
2798         u16 ets_offset;
2799         u16 ets_cfg;
2800         u16 ets_sensor;
2801         u8  num_sensors;
2802         u8  sensor_index;
2803         u8  sensor_location;
2804         u8  i;
2805         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2806
2807         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2808                 return E1000_NOT_IMPLEMENTED;
2809
2810         data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2811
2812         /* Return the internal sensor only if ETS is unsupported */
2813         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2814         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2815                 return 0;
2816
2817         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2818         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2819             != NVM_ETS_TYPE_EMC)
2820                 return E1000_NOT_IMPLEMENTED;
2821
2822         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2823         if (num_sensors > E1000_MAX_SENSORS)
2824                 num_sensors = E1000_MAX_SENSORS;
2825
2826         for (i = 1; i < num_sensors; i++) {
2827                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2828                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2829                                 NVM_ETS_DATA_INDEX_SHIFT);
2830                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2831                                    NVM_ETS_DATA_LOC_SHIFT);
2832
2833                 if (sensor_location != 0)
2834                         hw->phy.ops.read_i2c_byte(hw,
2835                                         e1000_emc_temp_data[sensor_index],
2836                                         E1000_I2C_THERMAL_SENSOR_ADDR,
2837                                         &data->sensor[i].temp);
2838         }
2839         return 0;
2840 }
2841
2842 /**
2843  *  igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2844  *  @hw: pointer to hardware structure
2845  *
2846  *  Sets the thermal sensor thresholds according to the NVM map
2847  *  and save off the threshold and location values into mac.thermal_sensor_data
2848  **/
2849 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2850 {
2851         u16 ets_offset;
2852         u16 ets_cfg;
2853         u16 ets_sensor;
2854         u8  low_thresh_delta;
2855         u8  num_sensors;
2856         u8  sensor_index;
2857         u8  sensor_location;
2858         u8  therm_limit;
2859         u8  i;
2860         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2861
2862         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2863                 return E1000_NOT_IMPLEMENTED;
2864
2865         memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2866
2867         data->sensor[0].location = 0x1;
2868         data->sensor[0].caution_thresh =
2869                 (rd32(E1000_THHIGHTC) & 0xFF);
2870         data->sensor[0].max_op_thresh =
2871                 (rd32(E1000_THLOWTC) & 0xFF);
2872
2873         /* Return the internal sensor only if ETS is unsupported */
2874         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2875         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2876                 return 0;
2877
2878         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2879         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2880             != NVM_ETS_TYPE_EMC)
2881                 return E1000_NOT_IMPLEMENTED;
2882
2883         low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2884                             NVM_ETS_LTHRES_DELTA_SHIFT);
2885         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2886
2887         for (i = 1; i <= num_sensors; i++) {
2888                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2889                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2890                                 NVM_ETS_DATA_INDEX_SHIFT);
2891                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2892                                    NVM_ETS_DATA_LOC_SHIFT);
2893                 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2894
2895                 hw->phy.ops.write_i2c_byte(hw,
2896                         e1000_emc_therm_limit[sensor_index],
2897                         E1000_I2C_THERMAL_SENSOR_ADDR,
2898                         therm_limit);
2899
2900                 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2901                         data->sensor[i].location = sensor_location;
2902                         data->sensor[i].caution_thresh = therm_limit;
2903                         data->sensor[i].max_op_thresh = therm_limit -
2904                                                         low_thresh_delta;
2905                 }
2906         }
2907         return 0;
2908 }
2909
2910 #endif
2911 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2912         .init_hw              = igb_init_hw_82575,
2913         .check_for_link       = igb_check_for_link_82575,
2914         .rar_set              = igb_rar_set,
2915         .read_mac_addr        = igb_read_mac_addr_82575,
2916         .get_speed_and_duplex = igb_get_link_up_info_82575,
2917 #ifdef CONFIG_IGB_HWMON
2918         .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2919         .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2920 #endif
2921 };
2922
2923 static const struct e1000_phy_operations e1000_phy_ops_82575 = {
2924         .acquire              = igb_acquire_phy_82575,
2925         .get_cfg_done         = igb_get_cfg_done_82575,
2926         .release              = igb_release_phy_82575,
2927         .write_i2c_byte       = igb_write_i2c_byte,
2928         .read_i2c_byte        = igb_read_i2c_byte,
2929 };
2930
2931 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2932         .acquire              = igb_acquire_nvm_82575,
2933         .read                 = igb_read_nvm_eerd,
2934         .release              = igb_release_nvm_82575,
2935         .write                = igb_write_nvm_spi,
2936 };
2937
2938 const struct e1000_info e1000_82575_info = {
2939         .get_invariants = igb_get_invariants_82575,
2940         .mac_ops = &e1000_mac_ops_82575,
2941         .phy_ops = &e1000_phy_ops_82575,
2942         .nvm_ops = &e1000_nvm_ops_82575,
2943 };
2944