drivers/net/ethernet/intel/igb/e1000_82575.c

   1 /* Intel(R) Gigabit Ethernet Linux driver
   2  * Copyright(c) 2007-2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, see <http://www.gnu.org/licenses/>.
  15  *
  16  * The full GNU General Public License is included in this distribution in
  17  * the file called "COPYING".
  18  *
  19  * Contact Information:
  20  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  */
  23
  24 /* e1000_82575
  25  * e1000_82576
  26  */
  27
  28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29
  30 #include <linux/types.h>
  31 #include <linux/if_ether.h>
  32 #include <linux/i2c.h>
  33
  34 #include "e1000_mac.h"
  35 #include "e1000_82575.h"
  36 #include "e1000_i210.h"
  37 #include "igb.h"
  38
  39 static s32  igb_get_invariants_82575(struct e1000_hw *);
  40 static s32  igb_acquire_phy_82575(struct e1000_hw *);
  41 static void igb_release_phy_82575(struct e1000_hw *);
  42 static s32  igb_acquire_nvm_82575(struct e1000_hw *);
  43 static void igb_release_nvm_82575(struct e1000_hw *);
  44 static s32  igb_check_for_link_82575(struct e1000_hw *);
  45 static s32  igb_get_cfg_done_82575(struct e1000_hw *);
  46 static s32  igb_init_hw_82575(struct e1000_hw *);
  47 static s32  igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
  48 static s32  igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
  49 static s32  igb_reset_hw_82575(struct e1000_hw *);
  50 static s32  igb_reset_hw_82580(struct e1000_hw *);
  51 static s32  igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
  52 static s32  igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
  53 static s32  igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
  54 static s32  igb_setup_copper_link_82575(struct e1000_hw *);
  55 static s32  igb_setup_serdes_link_82575(struct e1000_hw *);
  56 static s32  igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
  57 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
  58 static s32  igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
  59 static s32  igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
  60                                                  u16 *);
  61 static s32  igb_get_phy_id_82575(struct e1000_hw *);
  62 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
  63 static bool igb_sgmii_active_82575(struct e1000_hw *);
  64 static s32  igb_reset_init_script_82575(struct e1000_hw *);
  65 static s32  igb_read_mac_addr_82575(struct e1000_hw *);
  66 static s32  igb_set_pcie_completion_timeout(struct e1000_hw *hw);
  67 static s32  igb_reset_mdicnfg_82580(struct e1000_hw *hw);
  68 static s32  igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
  69 static s32  igb_update_nvm_checksum_82580(struct e1000_hw *hw);
  70 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
  71 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
  72 static const u16 e1000_82580_rxpbs_table[] = {
  73         36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
  74
  75 /* Due to a hw errata, if the host tries to  configure the VFTA register
  76  * while performing queries from the BMC or DMA, then the VFTA in some
  77  * cases won't be written.
  78  */
  79
  80 /**
  81  *  igb_write_vfta_i350 - Write value to VLAN filter table
  82  *  @hw: pointer to the HW structure
  83  *  @offset: register offset in VLAN filter table
  84  *  @value: register value written to VLAN filter table
  85  *
  86  *  Writes value at the given offset in the register array which stores
  87  *  the VLAN filter table.
  88  **/
  89 static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
  90 {
  91         struct igb_adapter *adapter = hw->back;
  92         int i;
  93
  94         for (i = 10; i--;)
  95                 array_wr32(E1000_VFTA, offset, value);
  96
  97         wrfl();
  98         adapter->shadow_vfta[offset] = value;
  99 }
 100
 101 /**
 102  *  igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
 103  *  @hw: pointer to the HW structure
 104  *
 105  *  Called to determine if the I2C pins are being used for I2C or as an
 106  *  external MDIO interface since the two options are mutually exclusive.
 107  **/
 108 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
 109 {
 110         u32 reg = 0;
 111         bool ext_mdio = false;
 112
 113         switch (hw->mac.type) {
 114         case e1000_82575:
 115         case e1000_82576:
 116                 reg = rd32(E1000_MDIC);
 117                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 118                 break;
 119         case e1000_82580:
 120         case e1000_i350:
 121         case e1000_i354:
 122         case e1000_i210:
 123         case e1000_i211:
 124                 reg = rd32(E1000_MDICNFG);
 125                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 126                 break;
 127         default:
 128                 break;
 129         }
 130         return ext_mdio;
 131 }
 132
 133 /**
 134  *  igb_check_for_link_media_swap - Check which M88E1112 interface linked
 135  *  @hw: pointer to the HW structure
 136  *
 137  *  Poll the M88E1112 interfaces to see which interface achieved link.
 138  */
 139 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
 140 {
 141         struct e1000_phy_info *phy = &hw->phy;
 142         s32 ret_val;
 143         u16 data;
 144         u8 port = 0;
 145
 146         /* Check the copper medium. */
 147         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 148         if (ret_val)
 149                 return ret_val;
 150
 151         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
 152         if (ret_val)
 153                 return ret_val;
 154
 155         if (data & E1000_M88E1112_STATUS_LINK)
 156                 port = E1000_MEDIA_PORT_COPPER;
 157
 158         /* Check the other medium. */
 159         ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
 160         if (ret_val)
 161                 return ret_val;
 162
 163         ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
 164         if (ret_val)
 165                 return ret_val;
 166
 167
 168         if (data & E1000_M88E1112_STATUS_LINK)
 169                 port = E1000_MEDIA_PORT_OTHER;
 170
 171         /* Determine if a swap needs to happen. */
 172         if (port && (hw->dev_spec._82575.media_port != port)) {
 173                 hw->dev_spec._82575.media_port = port;
 174                 hw->dev_spec._82575.media_changed = true;
 175         }
 176
 177         if (port == E1000_MEDIA_PORT_COPPER) {
 178                 /* reset page to 0 */
 179                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 180                 if (ret_val)
 181                         return ret_val;
 182                 igb_check_for_link_82575(hw);
 183         } else {
 184                 igb_check_for_link_82575(hw);
 185                 /* reset page to 0 */
 186                 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
 187                 if (ret_val)
 188                         return ret_val;
 189         }
 190
 191         return 0;
 192 }
 193
 194 /**
 195  *  igb_init_phy_params_82575 - Init PHY func ptrs.
 196  *  @hw: pointer to the HW structure
 197  **/
 198 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
 199 {
 200         struct e1000_phy_info *phy = &hw->phy;
 201         s32 ret_val = 0;
 202         u32 ctrl_ext;
 203
 204         if (hw->phy.media_type != e1000_media_type_copper) {
 205                 phy->type = e1000_phy_none;
 206                 goto out;
 207         }
 208
 209         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 210         phy->reset_delay_us     = 100;
 211
 212         ctrl_ext = rd32(E1000_CTRL_EXT);
 213
 214         if (igb_sgmii_active_82575(hw)) {
 215                 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
 216                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 217         } else {
 218                 phy->ops.reset = igb_phy_hw_reset;
 219                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 220         }
 221
 222         wr32(E1000_CTRL_EXT, ctrl_ext);
 223         igb_reset_mdicnfg_82580(hw);
 224
 225         if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
 226                 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
 227                 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
 228         } else {
 229                 switch (hw->mac.type) {
 230                 case e1000_82580:
 231                 case e1000_i350:
 232                 case e1000_i354:
 233                 case e1000_i210:
 234                 case e1000_i211:
 235                         phy->ops.read_reg = igb_read_phy_reg_82580;
 236                         phy->ops.write_reg = igb_write_phy_reg_82580;
 237                         break;
 238                 default:
 239                         phy->ops.read_reg = igb_read_phy_reg_igp;
 240                         phy->ops.write_reg = igb_write_phy_reg_igp;
 241                 }
 242         }
 243
 244         /* set lan id */
 245         hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
 246                         E1000_STATUS_FUNC_SHIFT;
 247
 248         /* Make sure the PHY is in a good state. Several people have reported
 249          * firmware leaving the PHY's page select register set to something
 250          * other than the default of zero, which causes the PHY ID read to
 251          * access something other than the intended register.
 252          */
 253         ret_val = hw->phy.ops.reset(hw);
 254         if (ret_val) {
 255                 hw_dbg("Error resetting the PHY.\n");
 256                 goto out;
 257         }
 258
 259         /* Set phy->phy_addr and phy->id. */
 260         igb_write_phy_reg_82580(hw, I347AT4_PAGE_SELECT, 0);
 261         ret_val = igb_get_phy_id_82575(hw);
 262         if (ret_val)
 263                 return ret_val;
 264
 265         /* Verify phy id and set remaining function pointers */
 266         switch (phy->id) {
 267         case M88E1543_E_PHY_ID:
 268         case M88E1512_E_PHY_ID:
 269         case I347AT4_E_PHY_ID:
 270         case M88E1112_E_PHY_ID:
 271         case M88E1111_I_PHY_ID:
 272                 phy->type               = e1000_phy_m88;
 273                 phy->ops.check_polarity = igb_check_polarity_m88;
 274                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 275                 if (phy->id != M88E1111_I_PHY_ID)
 276                         phy->ops.get_cable_length =
 277                                          igb_get_cable_length_m88_gen2;
 278                 else
 279                         phy->ops.get_cable_length = igb_get_cable_length_m88;
 280                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 281                 /* Check if this PHY is configured for media swap. */
 282                 if (phy->id == M88E1112_E_PHY_ID) {
 283                         u16 data;
 284
 285                         ret_val = phy->ops.write_reg(hw,
 286                                                      E1000_M88E1112_PAGE_ADDR,
 287                                                      2);
 288                         if (ret_val)
 289                                 goto out;
 290
 291                         ret_val = phy->ops.read_reg(hw,
 292                                                     E1000_M88E1112_MAC_CTRL_1,
 293                                                     &data);
 294                         if (ret_val)
 295                                 goto out;
 296
 297                         data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
 298                                E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
 299                         if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
 300                             data == E1000_M88E1112_AUTO_COPPER_BASEX)
 301                                 hw->mac.ops.check_for_link =
 302                                                 igb_check_for_link_media_swap;
 303                 }
 304                 if (phy->id == M88E1512_E_PHY_ID) {
 305                         ret_val = igb_initialize_M88E1512_phy(hw);
 306                         if (ret_val)
 307                                 goto out;
 308                 }
 309                 if (phy->id == M88E1543_E_PHY_ID) {
 310                         ret_val = igb_initialize_M88E1543_phy(hw);
 311                         if (ret_val)
 312                                 goto out;
 313                 }
 314                 break;
 315         case IGP03E1000_E_PHY_ID:
 316                 phy->type = e1000_phy_igp_3;
 317                 phy->ops.get_phy_info = igb_get_phy_info_igp;
 318                 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
 319                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
 320                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
 321                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
 322                 break;
 323         case I82580_I_PHY_ID:
 324         case I350_I_PHY_ID:
 325                 phy->type = e1000_phy_82580;
 326                 phy->ops.force_speed_duplex =
 327                                          igb_phy_force_speed_duplex_82580;
 328                 phy->ops.get_cable_length = igb_get_cable_length_82580;
 329                 phy->ops.get_phy_info = igb_get_phy_info_82580;
 330                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 331                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 332                 break;
 333         case I210_I_PHY_ID:
 334                 phy->type               = e1000_phy_i210;
 335                 phy->ops.check_polarity = igb_check_polarity_m88;
 336                 phy->ops.get_cfg_done   = igb_get_cfg_done_i210;
 337                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 338                 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
 339                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 340                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 341                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 342                 break;
 343         case BCM54616_E_PHY_ID:
 344                 phy->type = e1000_phy_bcm54616;
 345                 break;
 346         default:
 347                 ret_val = -E1000_ERR_PHY;
 348                 goto out;
 349         }
 350
 351 out:
 352         return ret_val;
 353 }
 354
 355 /**
 356  *  igb_init_nvm_params_82575 - Init NVM func ptrs.
 357  *  @hw: pointer to the HW structure
 358  **/
 359 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
 360 {
 361         struct e1000_nvm_info *nvm = &hw->nvm;
 362         u32 eecd = rd32(E1000_EECD);
 363         u16 size;
 364
 365         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 366                      E1000_EECD_SIZE_EX_SHIFT);
 367
 368         /* Added to a constant, "size" becomes the left-shift value
 369          * for setting word_size.
 370          */
 371         size += NVM_WORD_SIZE_BASE_SHIFT;
 372
 373         /* Just in case size is out of range, cap it to the largest
 374          * EEPROM size supported
 375          */
 376         if (size > 15)
 377                 size = 15;
 378
 379         nvm->word_size = BIT(size);
 380         nvm->opcode_bits = 8;
 381         nvm->delay_usec = 1;
 382
 383         switch (nvm->override) {
 384         case e1000_nvm_override_spi_large:
 385                 nvm->page_size = 32;
 386                 nvm->address_bits = 16;
 387                 break;
 388         case e1000_nvm_override_spi_small:
 389                 nvm->page_size = 8;
 390                 nvm->address_bits = 8;
 391                 break;
 392         default:
 393                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 394                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 395                                     16 : 8;
 396                 break;
 397         }
 398         if (nvm->word_size == BIT(15))
 399                 nvm->page_size = 128;
 400
 401         nvm->type = e1000_nvm_eeprom_spi;
 402
 403         /* NVM Function Pointers */
 404         nvm->ops.acquire = igb_acquire_nvm_82575;
 405         nvm->ops.release = igb_release_nvm_82575;
 406         nvm->ops.write = igb_write_nvm_spi;
 407         nvm->ops.validate = igb_validate_nvm_checksum;
 408         nvm->ops.update = igb_update_nvm_checksum;
 409         if (nvm->word_size < BIT(15))
 410                 nvm->ops.read = igb_read_nvm_eerd;
 411         else
 412                 nvm->ops.read = igb_read_nvm_spi;
 413
 414         /* override generic family function pointers for specific descendants */
 415         switch (hw->mac.type) {
 416         case e1000_82580:
 417                 nvm->ops.validate = igb_validate_nvm_checksum_82580;
 418                 nvm->ops.update = igb_update_nvm_checksum_82580;
 419                 break;
 420         case e1000_i354:
 421         case e1000_i350:
 422                 nvm->ops.validate = igb_validate_nvm_checksum_i350;
 423                 nvm->ops.update = igb_update_nvm_checksum_i350;
 424                 break;
 425         default:
 426                 break;
 427         }
 428
 429         return 0;
 430 }
 431
 432 /**
 433  *  igb_init_mac_params_82575 - Init MAC func ptrs.
 434  *  @hw: pointer to the HW structure
 435  **/
 436 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
 437 {
 438         struct e1000_mac_info *mac = &hw->mac;
 439         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 440
 441         /* Set mta register count */
 442         mac->mta_reg_count = 128;
 443         /* Set uta register count */
 444         mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
 445         /* Set rar entry count */
 446         switch (mac->type) {
 447         case e1000_82576:
 448                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 449                 break;
 450         case e1000_82580:
 451                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 452                 break;
 453         case e1000_i350:
 454         case e1000_i354:
 455                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 456                 break;
 457         default:
 458                 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 459                 break;
 460         }
 461         /* reset */
 462         if (mac->type >= e1000_82580)
 463                 mac->ops.reset_hw = igb_reset_hw_82580;
 464         else
 465                 mac->ops.reset_hw = igb_reset_hw_82575;
 466
 467         if (mac->type >= e1000_i210) {
 468                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
 469                 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
 470
 471         } else {
 472                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
 473                 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
 474         }
 475
 476         if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
 477                 mac->ops.write_vfta = igb_write_vfta_i350;
 478         else
 479                 mac->ops.write_vfta = igb_write_vfta;
 480
 481         /* Set if part includes ASF firmware */
 482         mac->asf_firmware_present = true;
 483         /* Set if manageability features are enabled. */
 484         mac->arc_subsystem_valid =
 485                 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
 486                         ? true : false;
 487         /* enable EEE on i350 parts and later parts */
 488         if (mac->type >= e1000_i350)
 489                 dev_spec->eee_disable = false;
 490         else
 491                 dev_spec->eee_disable = true;
 492         /* Allow a single clear of the SW semaphore on I210 and newer */
 493         if (mac->type >= e1000_i210)
 494                 dev_spec->clear_semaphore_once = true;
 495         /* physical interface link setup */
 496         mac->ops.setup_physical_interface =
 497                 (hw->phy.media_type == e1000_media_type_copper)
 498                         ? igb_setup_copper_link_82575
 499                         : igb_setup_serdes_link_82575;
 500
 501         if (mac->type == e1000_82580) {
 502                 switch (hw->device_id) {
 503                 /* feature not supported on these id's */
 504                 case E1000_DEV_ID_DH89XXCC_SGMII:
 505                 case E1000_DEV_ID_DH89XXCC_SERDES:
 506                 case E1000_DEV_ID_DH89XXCC_BACKPLANE:
 507                 case E1000_DEV_ID_DH89XXCC_SFP:
 508                         break;
 509                 default:
 510                         hw->dev_spec._82575.mas_capable = true;
 511                         break;
 512                 }
 513         }
 514         return 0;
 515 }
 516
 517 /**
 518  *  igb_set_sfp_media_type_82575 - derives SFP module media type.
 519  *  @hw: pointer to the HW structure
 520  *
 521  *  The media type is chosen based on SFP module.
 522  *  compatibility flags retrieved from SFP ID EEPROM.
 523  **/
 524 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
 525 {
 526         s32 ret_val = E1000_ERR_CONFIG;
 527         u32 ctrl_ext = 0;
 528         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 529         struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
 530         u8 tranceiver_type = 0;
 531         s32 timeout = 3;
 532
 533         /* Turn I2C interface ON and power on sfp cage */
 534         ctrl_ext = rd32(E1000_CTRL_EXT);
 535         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
 536         wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
 537
 538         wrfl();
 539
 540         /* Read SFP module data */
 541         while (timeout) {
 542                 ret_val = igb_read_sfp_data_byte(hw,
 543                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
 544                         &tranceiver_type);
 545                 if (ret_val == 0)
 546                         break;
 547                 msleep(100);
 548                 timeout--;
 549         }
 550         if (ret_val != 0)
 551                 goto out;
 552
 553         ret_val = igb_read_sfp_data_byte(hw,
 554                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
 555                         (u8 *)eth_flags);
 556         if (ret_val != 0)
 557                 goto out;
 558
 559         /* Check if there is some SFP module plugged and powered */
 560         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
 561             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
 562                 dev_spec->module_plugged = true;
 563                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
 564                         hw->phy.media_type = e1000_media_type_internal_serdes;
 565                 } else if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) {
 566                         dev_spec->sgmii_active = true;
 567                         hw->phy.media_type = e1000_media_type_internal_serdes;
 568                 } else if (eth_flags->e1000_base_t) {
 569                         dev_spec->sgmii_active = true;
 570                         hw->phy.media_type = e1000_media_type_copper;
 571                 } else {
 572                         hw->phy.media_type = e1000_media_type_unknown;
 573                         hw_dbg("PHY module has not been recognized\n");
 574                         goto out;
 575                 }
 576         } else {
 577                 hw->phy.media_type = e1000_media_type_unknown;
 578         }
 579         ret_val = 0;
 580 out:
 581         /* Restore I2C interface setting */
 582         wr32(E1000_CTRL_EXT, ctrl_ext);
 583         return ret_val;
 584 }
 585
 586 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
 587 {
 588         struct e1000_mac_info *mac = &hw->mac;
 589         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 590         s32 ret_val;
 591         u32 ctrl_ext = 0;
 592         u32 link_mode = 0;
 593
 594         switch (hw->device_id) {
 595         case E1000_DEV_ID_82575EB_COPPER:
 596         case E1000_DEV_ID_82575EB_FIBER_SERDES:
 597         case E1000_DEV_ID_82575GB_QUAD_COPPER:
 598                 mac->type = e1000_82575;
 599                 break;
 600         case E1000_DEV_ID_82576:
 601         case E1000_DEV_ID_82576_NS:
 602         case E1000_DEV_ID_82576_NS_SERDES:
 603         case E1000_DEV_ID_82576_FIBER:
 604         case E1000_DEV_ID_82576_SERDES:
 605         case E1000_DEV_ID_82576_QUAD_COPPER:
 606         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
 607         case E1000_DEV_ID_82576_SERDES_QUAD:
 608                 mac->type = e1000_82576;
 609                 break;
 610         case E1000_DEV_ID_82580_COPPER:
 611         case E1000_DEV_ID_82580_FIBER:
 612         case E1000_DEV_ID_82580_QUAD_FIBER:
 613         case E1000_DEV_ID_82580_SERDES:
 614         case E1000_DEV_ID_82580_SGMII:
 615         case E1000_DEV_ID_82580_COPPER_DUAL:
 616         case E1000_DEV_ID_DH89XXCC_SGMII:
 617         case E1000_DEV_ID_DH89XXCC_SERDES:
 618         case E1000_DEV_ID_DH89XXCC_BACKPLANE:
 619         case E1000_DEV_ID_DH89XXCC_SFP:
 620                 mac->type = e1000_82580;
 621                 break;
 622         case E1000_DEV_ID_I350_COPPER:
 623         case E1000_DEV_ID_I350_FIBER:
 624         case E1000_DEV_ID_I350_SERDES:
 625         case E1000_DEV_ID_I350_SGMII:
 626                 mac->type = e1000_i350;
 627                 break;
 628         case E1000_DEV_ID_I210_COPPER:
 629         case E1000_DEV_ID_I210_FIBER:
 630         case E1000_DEV_ID_I210_SERDES:
 631         case E1000_DEV_ID_I210_SGMII:
 632         case E1000_DEV_ID_I210_COPPER_FLASHLESS:
 633         case E1000_DEV_ID_I210_SERDES_FLASHLESS:
 634                 mac->type = e1000_i210;
 635                 break;
 636         case E1000_DEV_ID_I211_COPPER:
 637                 mac->type = e1000_i211;
 638                 break;
 639         case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
 640         case E1000_DEV_ID_I354_SGMII:
 641         case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
 642                 mac->type = e1000_i354;
 643                 break;
 644         default:
 645                 return -E1000_ERR_MAC_INIT;
 646         }
 647
 648         /* Set media type */
 649         /* The 82575 uses bits 22:23 for link mode. The mode can be changed
 650          * based on the EEPROM. We cannot rely upon device ID. There
 651          * is no distinguishable difference between fiber and internal
 652          * SerDes mode on the 82575. There can be an external PHY attached
 653          * on the SGMII interface. For this, we'll set sgmii_active to true.
 654          */
 655         hw->phy.media_type = e1000_media_type_copper;
 656         dev_spec->sgmii_active = false;
 657         dev_spec->module_plugged = false;
 658
 659         ctrl_ext = rd32(E1000_CTRL_EXT);
 660
 661         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
 662         switch (link_mode) {
 663         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
 664                 hw->phy.media_type = e1000_media_type_internal_serdes;
 665                 break;
 666         case E1000_CTRL_EXT_LINK_MODE_SGMII:
 667                 /* Get phy control interface type set (MDIO vs. I2C)*/
 668                 if (igb_sgmii_uses_mdio_82575(hw)) {
 669                         hw->phy.media_type = e1000_media_type_copper;
 670                         dev_spec->sgmii_active = true;
 671                         break;
 672                 }
 673                 /* fall through for I2C based SGMII */
 674         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
 675                 /* read media type from SFP EEPROM */
 676                 ret_val = igb_set_sfp_media_type_82575(hw);
 677                 if ((ret_val != 0) ||
 678                     (hw->phy.media_type == e1000_media_type_unknown)) {
 679                         /* If media type was not identified then return media
 680                          * type defined by the CTRL_EXT settings.
 681                          */
 682                         hw->phy.media_type = e1000_media_type_internal_serdes;
 683
 684                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
 685                                 hw->phy.media_type = e1000_media_type_copper;
 686                                 dev_spec->sgmii_active = true;
 687                         }
 688
 689                         break;
 690                 }
 691
 692                 /* change current link mode setting */
 693                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
 694
 695                 if (dev_spec->sgmii_active)
 696                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
 697                 else
 698                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
 699
 700                 wr32(E1000_CTRL_EXT, ctrl_ext);
 701
 702                 break;
 703         default:
 704                 break;
 705         }
 706
 707         /* mac initialization and operations */
 708         ret_val = igb_init_mac_params_82575(hw);
 709         if (ret_val)
 710                 goto out;
 711
 712         /* NVM initialization */
 713         ret_val = igb_init_nvm_params_82575(hw);
 714         switch (hw->mac.type) {
 715         case e1000_i210:
 716         case e1000_i211:
 717                 ret_val = igb_init_nvm_params_i210(hw);
 718                 break;
 719         default:
 720                 break;
 721         }
 722
 723         if (ret_val)
 724                 goto out;
 725
 726         /* if part supports SR-IOV then initialize mailbox parameters */
 727         switch (mac->type) {
 728         case e1000_82576:
 729         case e1000_i350:
 730                 igb_init_mbx_params_pf(hw);
 731                 break;
 732         default:
 733                 break;
 734         }
 735
 736         /* setup PHY parameters */
 737         ret_val = igb_init_phy_params_82575(hw);
 738
 739 out:
 740         return ret_val;
 741 }
 742
 743 /**
 744  *  igb_acquire_phy_82575 - Acquire rights to access PHY
 745  *  @hw: pointer to the HW structure
 746  *
 747  *  Acquire access rights to the correct PHY.  This is a
 748  *  function pointer entry point called by the api module.
 749  **/
 750 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
 751 {
 752         u16 mask = E1000_SWFW_PHY0_SM;
 753
 754         if (hw->bus.func == E1000_FUNC_1)
 755                 mask = E1000_SWFW_PHY1_SM;
 756         else if (hw->bus.func == E1000_FUNC_2)
 757                 mask = E1000_SWFW_PHY2_SM;
 758         else if (hw->bus.func == E1000_FUNC_3)
 759                 mask = E1000_SWFW_PHY3_SM;
 760
 761         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 762 }
 763
 764 /**
 765  *  igb_release_phy_82575 - Release rights to access PHY
 766  *  @hw: pointer to the HW structure
 767  *
 768  *  A wrapper to release access rights to the correct PHY.  This is a
 769  *  function pointer entry point called by the api module.
 770  **/
 771 static void igb_release_phy_82575(struct e1000_hw *hw)
 772 {
 773         u16 mask = E1000_SWFW_PHY0_SM;
 774
 775         if (hw->bus.func == E1000_FUNC_1)
 776                 mask = E1000_SWFW_PHY1_SM;
 777         else if (hw->bus.func == E1000_FUNC_2)
 778                 mask = E1000_SWFW_PHY2_SM;
 779         else if (hw->bus.func == E1000_FUNC_3)
 780                 mask = E1000_SWFW_PHY3_SM;
 781
 782         hw->mac.ops.release_swfw_sync(hw, mask);
 783 }
 784
 785 /**
 786  *  igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 787  *  @hw: pointer to the HW structure
 788  *  @offset: register offset to be read
 789  *  @data: pointer to the read data
 790  *
 791  *  Reads the PHY register at offset using the serial gigabit media independent
 792  *  interface and stores the retrieved information in data.
 793  **/
 794 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 795                                           u16 *data)
 796 {
 797         s32 ret_val = -E1000_ERR_PARAM;
 798
 799         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 800                 hw_dbg("PHY Address %u is out of range\n", offset);
 801                 goto out;
 802         }
 803
 804         ret_val = hw->phy.ops.acquire(hw);
 805         if (ret_val)
 806                 goto out;
 807
 808         ret_val = igb_read_phy_reg_i2c(hw, offset, data);
 809
 810         hw->phy.ops.release(hw);
 811
 812 out:
 813         return ret_val;
 814 }
 815
 816 /**
 817  *  igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 818  *  @hw: pointer to the HW structure
 819  *  @offset: register offset to write to
 820  *  @data: data to write at register offset
 821  *
 822  *  Writes the data to PHY register at the offset using the serial gigabit
 823  *  media independent interface.
 824  **/
 825 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 826                                            u16 data)
 827 {
 828         s32 ret_val = -E1000_ERR_PARAM;
 829
 830
 831         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 832                 hw_dbg("PHY Address %d is out of range\n", offset);
 833                 goto out;
 834         }
 835
 836         ret_val = hw->phy.ops.acquire(hw);
 837         if (ret_val)
 838                 goto out;
 839
 840         ret_val = igb_write_phy_reg_i2c(hw, offset, data);
 841
 842         hw->phy.ops.release(hw);
 843
 844 out:
 845         return ret_val;
 846 }
 847
 848 /**
 849  *  igb_get_phy_id_82575 - Retrieve PHY addr and id
 850  *  @hw: pointer to the HW structure
 851  *
 852  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 853  *  sgmi interface.
 854  **/
 855 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
 856 {
 857         struct e1000_phy_info *phy = &hw->phy;
 858         s32  ret_val = 0;
 859         u16 phy_id;
 860         u32 ctrl_ext;
 861         u32 mdic;
 862
 863         /* Extra read required for some PHY's on i354 */
 864         if (hw->mac.type == e1000_i354)
 865                 igb_get_phy_id(hw);
 866
 867         /* For SGMII PHYs, we try the list of possible addresses until
 868          * we find one that works.  For non-SGMII PHYs
 869          * (e.g. integrated copper PHYs), an address of 1 should
 870          * work.  The result of this function should mean phy->phy_addr
 871          * and phy->id are set correctly.
 872          */
 873         if (!(igb_sgmii_active_82575(hw))) {
 874                 phy->addr = 1;
 875                 ret_val = igb_get_phy_id(hw);
 876                 goto out;
 877         }
 878
 879         if (igb_sgmii_uses_mdio_82575(hw)) {
 880                 switch (hw->mac.type) {
 881                 case e1000_82575:
 882                 case e1000_82576:
 883                         mdic = rd32(E1000_MDIC);
 884                         mdic &= E1000_MDIC_PHY_MASK;
 885                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 886                         break;
 887                 case e1000_82580:
 888                 case e1000_i350:
 889                 case e1000_i354:
 890                 case e1000_i210:
 891                 case e1000_i211:
 892                         mdic = rd32(E1000_MDICNFG);
 893                         mdic &= E1000_MDICNFG_PHY_MASK;
 894                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 895                         break;
 896                 default:
 897                         ret_val = -E1000_ERR_PHY;
 898                         goto out;
 899                 }
 900                 ret_val = igb_get_phy_id(hw);
 901                 goto out;
 902         }
 903
 904         /* Power on sgmii phy if it is disabled */
 905         ctrl_ext = rd32(E1000_CTRL_EXT);
 906         wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 907         wrfl();
 908         msleep(300);
 909
 910         /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
 911          * Therefore, we need to test 1-7
 912          */
 913         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 914                 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 915                 if (ret_val == 0) {
 916                         hw_dbg("Vendor ID 0x%08X read at address %u\n",
 917                                phy_id, phy->addr);
 918                         /* At the time of this writing, The M88 part is
 919                          * the only supported SGMII PHY product.
 920                          */
 921                         if (phy_id == M88_VENDOR)
 922                                 break;
 923                 } else {
 924                         hw_dbg("PHY address %u was unreadable\n", phy->addr);
 925                 }
 926         }
 927
 928         /* A valid PHY type couldn't be found. */
 929         if (phy->addr == 8) {
 930                 phy->addr = 0;
 931                 ret_val = -E1000_ERR_PHY;
 932                 goto out;
 933         } else {
 934                 ret_val = igb_get_phy_id(hw);
 935         }
 936
 937         /* restore previous sfp cage power state */
 938         wr32(E1000_CTRL_EXT, ctrl_ext);
 939
 940 out:
 941         return ret_val;
 942 }
 943
 944 /**
 945  *  igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 946  *  @hw: pointer to the HW structure
 947  *
 948  *  Resets the PHY using the serial gigabit media independent interface.
 949  **/
 950 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 951 {
 952         struct e1000_phy_info *phy = &hw->phy;
 953         s32 ret_val;
 954
 955         /* This isn't a true "hard" reset, but is the only reset
 956          * available to us at this time.
 957          */
 958
 959         hw_dbg("Soft resetting SGMII attached PHY...\n");
 960
 961         /* SFP documentation requires the following to configure the SPF module
 962          * to work on SGMII.  No further documentation is given.
 963          */
 964         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 965         if (ret_val)
 966                 goto out;
 967
 968         ret_val = igb_phy_sw_reset(hw);
 969         if (ret_val)
 970                 goto out;
 971
 972         if (phy->id == M88E1512_E_PHY_ID)
 973                 ret_val = igb_initialize_M88E1512_phy(hw);
 974         if (phy->id == M88E1543_E_PHY_ID)
 975                 ret_val = igb_initialize_M88E1543_phy(hw);
 976 out:
 977         return ret_val;
 978 }
 979
 980 /**
 981  *  igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 982  *  @hw: pointer to the HW structure
 983  *  @active: true to enable LPLU, false to disable
 984  *
 985  *  Sets the LPLU D0 state according to the active flag.  When
 986  *  activating LPLU this function also disables smart speed
 987  *  and vice versa.  LPLU will not be activated unless the
 988  *  device autonegotiation advertisement meets standards of
 989  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 990  *  This is a function pointer entry point only called by
 991  *  PHY setup routines.
 992  **/
 993 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 994 {
 995         struct e1000_phy_info *phy = &hw->phy;
 996         s32 ret_val;
 997         u16 data;
 998
 999         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1000         if (ret_val)
1001                 goto out;
1002
1003         if (active) {
1004                 data |= IGP02E1000_PM_D0_LPLU;
1005                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1006                                                  data);
1007                 if (ret_val)
1008                         goto out;
1009
1010                 /* When LPLU is enabled, we should disable SmartSpeed */
1011                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1012                                                 &data);
1013                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1014                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1015                                                  data);
1016                 if (ret_val)
1017                         goto out;
1018         } else {
1019                 data &= ~IGP02E1000_PM_D0_LPLU;
1020                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1021                                                  data);
1022                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1023                  * during Dx states where the power conservation is most
1024                  * important.  During driver activity we should enable
1025                  * SmartSpeed, so performance is maintained.
1026                  */
1027                 if (phy->smart_speed == e1000_smart_speed_on) {
1028                         ret_val = phy->ops.read_reg(hw,
1029                                         IGP01E1000_PHY_PORT_CONFIG, &data);
1030                         if (ret_val)
1031                                 goto out;
1032
1033                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1034                         ret_val = phy->ops.write_reg(hw,
1035                                         IGP01E1000_PHY_PORT_CONFIG, data);
1036                         if (ret_val)
1037                                 goto out;
1038                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1039                         ret_val = phy->ops.read_reg(hw,
1040                                         IGP01E1000_PHY_PORT_CONFIG, &data);
1041                         if (ret_val)
1042                                 goto out;
1043
1044                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1045                         ret_val = phy->ops.write_reg(hw,
1046                                         IGP01E1000_PHY_PORT_CONFIG, data);
1047                         if (ret_val)
1048                                 goto out;
1049                 }
1050         }
1051
1052 out:
1053         return ret_val;
1054 }
1055
1056 /**
1057  *  igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
1058  *  @hw: pointer to the HW structure
1059  *  @active: true to enable LPLU, false to disable
1060  *
1061  *  Sets the LPLU D0 state according to the active flag.  When
1062  *  activating LPLU this function also disables smart speed
1063  *  and vice versa.  LPLU will not be activated unless the
1064  *  device autonegotiation advertisement meets standards of
1065  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1066  *  This is a function pointer entry point only called by
1067  *  PHY setup routines.
1068  **/
1069 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1070 {
1071         struct e1000_phy_info *phy = &hw->phy;
1072         u16 data;
1073
1074         data = rd32(E1000_82580_PHY_POWER_MGMT);
1075
1076         if (active) {
1077                 data |= E1000_82580_PM_D0_LPLU;
1078
1079                 /* When LPLU is enabled, we should disable SmartSpeed */
1080                 data &= ~E1000_82580_PM_SPD;
1081         } else {
1082                 data &= ~E1000_82580_PM_D0_LPLU;
1083
1084                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1085                  * during Dx states where the power conservation is most
1086                  * important.  During driver activity we should enable
1087                  * SmartSpeed, so performance is maintained.
1088                  */
1089                 if (phy->smart_speed == e1000_smart_speed_on)
1090                         data |= E1000_82580_PM_SPD;
1091                 else if (phy->smart_speed == e1000_smart_speed_off)
1092                         data &= ~E1000_82580_PM_SPD; }
1093
1094         wr32(E1000_82580_PHY_POWER_MGMT, data);
1095         return 0;
1096 }
1097
1098 /**
1099  *  igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1100  *  @hw: pointer to the HW structure
1101  *  @active: boolean used to enable/disable lplu
1102  *
1103  *  Success returns 0, Failure returns 1
1104  *
1105  *  The low power link up (lplu) state is set to the power management level D3
1106  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
1107  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
1108  *  is used during Dx states where the power conservation is most important.
1109  *  During driver activity, SmartSpeed should be enabled so performance is
1110  *  maintained.
1111  **/
1112 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1113 {
1114         struct e1000_phy_info *phy = &hw->phy;
1115         u16 data;
1116
1117         data = rd32(E1000_82580_PHY_POWER_MGMT);
1118
1119         if (!active) {
1120                 data &= ~E1000_82580_PM_D3_LPLU;
1121                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1122                  * during Dx states where the power conservation is most
1123                  * important.  During driver activity we should enable
1124                  * SmartSpeed, so performance is maintained.
1125                  */
1126                 if (phy->smart_speed == e1000_smart_speed_on)
1127                         data |= E1000_82580_PM_SPD;
1128                 else if (phy->smart_speed == e1000_smart_speed_off)
1129                         data &= ~E1000_82580_PM_SPD;
1130         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1131                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1132                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1133                 data |= E1000_82580_PM_D3_LPLU;
1134                 /* When LPLU is enabled, we should disable SmartSpeed */
1135                 data &= ~E1000_82580_PM_SPD;
1136         }
1137
1138         wr32(E1000_82580_PHY_POWER_MGMT, data);
1139         return 0;
1140 }
1141
1142 /**
1143  *  igb_acquire_nvm_82575 - Request for access to EEPROM
1144  *  @hw: pointer to the HW structure
1145  *
1146  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
1147  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
1148  *  Return successful if access grant bit set, else clear the request for
1149  *  EEPROM access and return -E1000_ERR_NVM (-1).
1150  **/
1151 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1152 {
1153         s32 ret_val;
1154
1155         ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1156         if (ret_val)
1157                 goto out;
1158
1159         ret_val = igb_acquire_nvm(hw);
1160
1161         if (ret_val)
1162                 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1163
1164 out:
1165         return ret_val;
1166 }
1167
1168 /**
1169  *  igb_release_nvm_82575 - Release exclusive access to EEPROM
1170  *  @hw: pointer to the HW structure
1171  *
1172  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1173  *  then release the semaphores acquired.
1174  **/
1175 static void igb_release_nvm_82575(struct e1000_hw *hw)
1176 {
1177         igb_release_nvm(hw);
1178         hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1179 }
1180
1181 /**
1182  *  igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1183  *  @hw: pointer to the HW structure
1184  *  @mask: specifies which semaphore to acquire
1185  *
1186  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1187  *  will also specify which port we're acquiring the lock for.
1188  **/
1189 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1190 {
1191         u32 swfw_sync;
1192         u32 swmask = mask;
1193         u32 fwmask = mask << 16;
1194         s32 ret_val = 0;
1195         s32 i = 0, timeout = 200;
1196
1197         while (i < timeout) {
1198                 if (igb_get_hw_semaphore(hw)) {
1199                         ret_val = -E1000_ERR_SWFW_SYNC;
1200                         goto out;
1201                 }
1202
1203                 swfw_sync = rd32(E1000_SW_FW_SYNC);
1204                 if (!(swfw_sync & (fwmask | swmask)))
1205                         break;
1206
1207                 /* Firmware currently using resource (fwmask)
1208                  * or other software thread using resource (swmask)
1209                  */
1210                 igb_put_hw_semaphore(hw);
1211                 mdelay(5);
1212                 i++;
1213         }
1214
1215         if (i == timeout) {
1216                 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1217                 ret_val = -E1000_ERR_SWFW_SYNC;
1218                 goto out;
1219         }
1220
1221         swfw_sync |= swmask;
1222         wr32(E1000_SW_FW_SYNC, swfw_sync);
1223
1224         igb_put_hw_semaphore(hw);
1225
1226 out:
1227         return ret_val;
1228 }
1229
1230 /**
1231  *  igb_release_swfw_sync_82575 - Release SW/FW semaphore
1232  *  @hw: pointer to the HW structure
1233  *  @mask: specifies which semaphore to acquire
1234  *
1235  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1236  *  will also specify which port we're releasing the lock for.
1237  **/
1238 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1239 {
1240         u32 swfw_sync;
1241
1242         while (igb_get_hw_semaphore(hw) != 0)
1243                 ; /* Empty */
1244
1245         swfw_sync = rd32(E1000_SW_FW_SYNC);
1246         swfw_sync &= ~mask;
1247         wr32(E1000_SW_FW_SYNC, swfw_sync);
1248
1249         igb_put_hw_semaphore(hw);
1250 }
1251
1252 /**
1253  *  igb_get_cfg_done_82575 - Read config done bit
1254  *  @hw: pointer to the HW structure
1255  *
1256  *  Read the management control register for the config done bit for
1257  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1258  *  to read the config done bit, so an error is *ONLY* logged and returns
1259  *  0.  If we were to return with error, EEPROM-less silicon
1260  *  would not be able to be reset or change link.
1261  **/
1262 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1263 {
1264         s32 timeout = PHY_CFG_TIMEOUT;
1265         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1266
1267         if (hw->bus.func == 1)
1268                 mask = E1000_NVM_CFG_DONE_PORT_1;
1269         else if (hw->bus.func == E1000_FUNC_2)
1270                 mask = E1000_NVM_CFG_DONE_PORT_2;
1271         else if (hw->bus.func == E1000_FUNC_3)
1272                 mask = E1000_NVM_CFG_DONE_PORT_3;
1273
1274         while (timeout) {
1275                 if (rd32(E1000_EEMNGCTL) & mask)
1276                         break;
1277                 usleep_range(1000, 2000);
1278                 timeout--;
1279         }
1280         if (!timeout)
1281                 hw_dbg("MNG configuration cycle has not completed.\n");
1282
1283         /* If EEPROM is not marked present, init the PHY manually */
1284         if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1285             (hw->phy.type == e1000_phy_igp_3))
1286                 igb_phy_init_script_igp3(hw);
1287
1288         return 0;
1289 }
1290
1291 /**
1292  *  igb_get_link_up_info_82575 - Get link speed/duplex info
1293  *  @hw: pointer to the HW structure
1294  *  @speed: stores the current speed
1295  *  @duplex: stores the current duplex
1296  *
1297  *  This is a wrapper function, if using the serial gigabit media independent
1298  *  interface, use PCS to retrieve the link speed and duplex information.
1299  *  Otherwise, use the generic function to get the link speed and duplex info.
1300  **/
1301 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1302                                         u16 *duplex)
1303 {
1304         s32 ret_val;
1305
1306         if (hw->phy.media_type != e1000_media_type_copper)
1307                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1308                                                                duplex);
1309         else
1310                 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1311                                                                     duplex);
1312
1313         return ret_val;
1314 }
1315
1316 /**
1317  *  igb_check_for_link_82575 - Check for link
1318  *  @hw: pointer to the HW structure
1319  *
1320  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1321  *  use the generic interface for determining link.
1322  **/
1323 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1324 {
1325         s32 ret_val;
1326         u16 speed, duplex;
1327
1328         if (hw->phy.media_type != e1000_media_type_copper) {
1329                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1330                                                              &duplex);
1331                 /* Use this flag to determine if link needs to be checked or
1332                  * not.  If  we have link clear the flag so that we do not
1333                  * continue to check for link.
1334                  */
1335                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1336
1337                 /* Configure Flow Control now that Auto-Neg has completed.
1338                  * First, we need to restore the desired flow control
1339                  * settings because we may have had to re-autoneg with a
1340                  * different link partner.
1341                  */
1342                 ret_val = igb_config_fc_after_link_up(hw);
1343                 if (ret_val)
1344                         hw_dbg("Error configuring flow control\n");
1345         } else {
1346                 ret_val = igb_check_for_copper_link(hw);
1347         }
1348
1349         return ret_val;
1350 }
1351
1352 /**
1353  *  igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1354  *  @hw: pointer to the HW structure
1355  **/
1356 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1357 {
1358         u32 reg;
1359
1360
1361         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1362             !igb_sgmii_active_82575(hw))
1363                 return;
1364
1365         /* Enable PCS to turn on link */
1366         reg = rd32(E1000_PCS_CFG0);
1367         reg |= E1000_PCS_CFG_PCS_EN;
1368         wr32(E1000_PCS_CFG0, reg);
1369
1370         /* Power up the laser */
1371         reg = rd32(E1000_CTRL_EXT);
1372         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1373         wr32(E1000_CTRL_EXT, reg);
1374
1375         /* flush the write to verify completion */
1376         wrfl();
1377         usleep_range(1000, 2000);
1378 }
1379
1380 /**
1381  *  igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1382  *  @hw: pointer to the HW structure
1383  *  @speed: stores the current speed
1384  *  @duplex: stores the current duplex
1385  *
1386  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1387  *  duplex, then store the values in the pointers provided.
1388  **/
1389 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1390                                                 u16 *duplex)
1391 {
1392         struct e1000_mac_info *mac = &hw->mac;
1393         u32 pcs, status;
1394
1395         /* Set up defaults for the return values of this function */
1396         mac->serdes_has_link = false;
1397         *speed = 0;
1398         *duplex = 0;
1399
1400         /* Read the PCS Status register for link state. For non-copper mode,
1401          * the status register is not accurate. The PCS status register is
1402          * used instead.
1403          */
1404         pcs = rd32(E1000_PCS_LSTAT);
1405
1406         /* The link up bit determines when link is up on autoneg. The sync ok
1407          * gets set once both sides sync up and agree upon link. Stable link
1408          * can be determined by checking for both link up and link sync ok
1409          */
1410         if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1411                 mac->serdes_has_link = true;
1412
1413                 /* Detect and store PCS speed */
1414                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1415                         *speed = SPEED_1000;
1416                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1417                         *speed = SPEED_100;
1418                 else
1419                         *speed = SPEED_10;
1420
1421                 /* Detect and store PCS duplex */
1422                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1423                         *duplex = FULL_DUPLEX;
1424                 else
1425                         *duplex = HALF_DUPLEX;
1426
1427         /* Check if it is an I354 2.5Gb backplane connection. */
1428                 if (mac->type == e1000_i354) {
1429                         status = rd32(E1000_STATUS);
1430                         if ((status & E1000_STATUS_2P5_SKU) &&
1431                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1432                                 *speed = SPEED_2500;
1433                                 *duplex = FULL_DUPLEX;
1434                                 hw_dbg("2500 Mbs, ");
1435                                 hw_dbg("Full Duplex\n");
1436                         }
1437                 }
1438
1439         }
1440
1441         return 0;
1442 }
1443
1444 /**
1445  *  igb_shutdown_serdes_link_82575 - Remove link during power down
1446  *  @hw: pointer to the HW structure
1447  *
1448  *  In the case of fiber serdes, shut down optics and PCS on driver unload
1449  *  when management pass thru is not enabled.
1450  **/
1451 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1452 {
1453         u32 reg;
1454
1455         if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1456             igb_sgmii_active_82575(hw))
1457                 return;
1458
1459         if (!igb_enable_mng_pass_thru(hw)) {
1460                 /* Disable PCS to turn off link */
1461                 reg = rd32(E1000_PCS_CFG0);
1462                 reg &= ~E1000_PCS_CFG_PCS_EN;
1463                 wr32(E1000_PCS_CFG0, reg);
1464
1465                 /* shutdown the laser */
1466                 reg = rd32(E1000_CTRL_EXT);
1467                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1468                 wr32(E1000_CTRL_EXT, reg);
1469
1470                 /* flush the write to verify completion */
1471                 wrfl();
1472                 usleep_range(1000, 2000);
1473         }
1474 }
1475
1476 /**
1477  *  igb_reset_hw_82575 - Reset hardware
1478  *  @hw: pointer to the HW structure
1479  *
1480  *  This resets the hardware into a known state.  This is a
1481  *  function pointer entry point called by the api module.
1482  **/
1483 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1484 {
1485         u32 ctrl;
1486         s32 ret_val;
1487
1488         /* Prevent the PCI-E bus from sticking if there is no TLP connection
1489          * on the last TLP read/write transaction when MAC is reset.
1490          */
1491         ret_val = igb_disable_pcie_master(hw);
1492         if (ret_val)
1493                 hw_dbg("PCI-E Master disable polling has failed.\n");
1494
1495         /* set the completion timeout for interface */
1496         ret_val = igb_set_pcie_completion_timeout(hw);
1497         if (ret_val)
1498                 hw_dbg("PCI-E Set completion timeout has failed.\n");
1499
1500         hw_dbg("Masking off all interrupts\n");
1501         wr32(E1000_IMC, 0xffffffff);
1502
1503         wr32(E1000_RCTL, 0);
1504         wr32(E1000_TCTL, E1000_TCTL_PSP);
1505         wrfl();
1506
1507         usleep_range(10000, 20000);
1508
1509         ctrl = rd32(E1000_CTRL);
1510
1511         hw_dbg("Issuing a global reset to MAC\n");
1512         wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1513
1514         ret_val = igb_get_auto_rd_done(hw);
1515         if (ret_val) {
1516                 /* When auto config read does not complete, do not
1517                  * return with an error. This can happen in situations
1518                  * where there is no eeprom and prevents getting link.
1519                  */
1520                 hw_dbg("Auto Read Done did not complete\n");
1521         }
1522
1523         /* If EEPROM is not present, run manual init scripts */
1524         if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1525                 igb_reset_init_script_82575(hw);
1526
1527         /* Clear any pending interrupt events. */
1528         wr32(E1000_IMC, 0xffffffff);
1529         rd32(E1000_ICR);
1530
1531         /* Install any alternate MAC address into RAR0 */
1532         ret_val = igb_check_alt_mac_addr(hw);
1533
1534         return ret_val;
1535 }
1536
1537 /**
1538  *  igb_init_hw_82575 - Initialize hardware
1539  *  @hw: pointer to the HW structure
1540  *
1541  *  This inits the hardware readying it for operation.
1542  **/
1543 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1544 {
1545         struct e1000_mac_info *mac = &hw->mac;
1546         s32 ret_val;
1547         u16 i, rar_count = mac->rar_entry_count;
1548
1549         if ((hw->mac.type >= e1000_i210) &&
1550             !(igb_get_flash_presence_i210(hw))) {
1551                 ret_val = igb_pll_workaround_i210(hw);
1552                 if (ret_val)
1553                         return ret_val;
1554         }
1555
1556         /* Initialize identification LED */
1557         ret_val = igb_id_led_init(hw);
1558         if (ret_val) {
1559                 hw_dbg("Error initializing identification LED\n");
1560                 /* This is not fatal and we should not stop init due to this */
1561         }
1562
1563         /* Disabling VLAN filtering */
1564         hw_dbg("Initializing the IEEE VLAN\n");
1565         igb_clear_vfta(hw);
1566
1567         /* Setup the receive address */
1568         igb_init_rx_addrs(hw, rar_count);
1569
1570         /* Zero out the Multicast HASH table */
1571         hw_dbg("Zeroing the MTA\n");
1572         for (i = 0; i < mac->mta_reg_count; i++)
1573                 array_wr32(E1000_MTA, i, 0);
1574
1575         /* Zero out the Unicast HASH table */
1576         hw_dbg("Zeroing the UTA\n");
1577         for (i = 0; i < mac->uta_reg_count; i++)
1578                 array_wr32(E1000_UTA, i, 0);
1579
1580         /* Setup link and flow control */
1581         ret_val = igb_setup_link(hw);
1582
1583         /* Clear all of the statistics registers (clear on read).  It is
1584          * important that we do this after we have tried to establish link
1585          * because the symbol error count will increment wildly if there
1586          * is no link.
1587          */
1588         igb_clear_hw_cntrs_82575(hw);
1589         return ret_val;
1590 }
1591
1592 /**
1593  *  igb_setup_copper_link_82575 - Configure copper link settings
1594  *  @hw: pointer to the HW structure
1595  *
1596  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1597  *  for link, once link is established calls to configure collision distance
1598  *  and flow control are called.
1599  **/
1600 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1601 {
1602         u32 ctrl;
1603         s32  ret_val;
1604         u32 phpm_reg;
1605
1606         ctrl = rd32(E1000_CTRL);
1607         ctrl |= E1000_CTRL_SLU;
1608         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1609         wr32(E1000_CTRL, ctrl);
1610
1611         /* Clear Go Link Disconnect bit on supported devices */
1612         switch (hw->mac.type) {
1613         case e1000_82580:
1614         case e1000_i350:
1615         case e1000_i210:
1616         case e1000_i211:
1617                 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1618                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1619                 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1620                 break;
1621         default:
1622                 break;
1623         }
1624
1625         ret_val = igb_setup_serdes_link_82575(hw);
1626         if (ret_val)
1627                 goto out;
1628
1629         if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1630                 /* allow time for SFP cage time to power up phy */
1631                 msleep(300);
1632
1633                 ret_val = hw->phy.ops.reset(hw);
1634                 if (ret_val) {
1635                         hw_dbg("Error resetting the PHY.\n");
1636                         goto out;
1637                 }
1638         }
1639         switch (hw->phy.type) {
1640         case e1000_phy_i210:
1641         case e1000_phy_m88:
1642                 switch (hw->phy.id) {
1643                 case I347AT4_E_PHY_ID:
1644                 case M88E1112_E_PHY_ID:
1645                 case M88E1543_E_PHY_ID:
1646                 case M88E1512_E_PHY_ID:
1647                 case I210_I_PHY_ID:
1648                         ret_val = igb_copper_link_setup_m88_gen2(hw);
1649                         break;
1650                 default:
1651                         ret_val = igb_copper_link_setup_m88(hw);
1652                         break;
1653                 }
1654                 break;
1655         case e1000_phy_igp_3:
1656                 ret_val = igb_copper_link_setup_igp(hw);
1657                 break;
1658         case e1000_phy_82580:
1659                 ret_val = igb_copper_link_setup_82580(hw);
1660                 break;
1661         case e1000_phy_bcm54616:
1662                 ret_val = 0;
1663                 break;
1664         default:
1665                 ret_val = -E1000_ERR_PHY;
1666                 break;
1667         }
1668
1669         if (ret_val)
1670                 goto out;
1671
1672         ret_val = igb_setup_copper_link(hw);
1673 out:
1674         return ret_val;
1675 }
1676
1677 /**
1678  *  igb_setup_serdes_link_82575 - Setup link for serdes
1679  *  @hw: pointer to the HW structure
1680  *
1681  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1682  *  used on copper connections where the serialized gigabit media independent
1683  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1684  *  for auto-negotiation or forces speed/duplex.
1685  **/
1686 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1687 {
1688         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1689         bool pcs_autoneg;
1690         s32 ret_val = 0;
1691         u16 data;
1692
1693         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1694             !igb_sgmii_active_82575(hw))
1695                 return ret_val;
1696
1697
1698         /* On the 82575, SerDes loopback mode persists until it is
1699          * explicitly turned off or a power cycle is performed.  A read to
1700          * the register does not indicate its status.  Therefore, we ensure
1701          * loopback mode is disabled during initialization.
1702          */
1703         wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1704
1705         /* power on the sfp cage if present and turn on I2C */
1706         ctrl_ext = rd32(E1000_CTRL_EXT);
1707         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1708         ctrl_ext |= E1000_CTRL_I2C_ENA;
1709         wr32(E1000_CTRL_EXT, ctrl_ext);
1710
1711         ctrl_reg = rd32(E1000_CTRL);
1712         ctrl_reg |= E1000_CTRL_SLU;
1713
1714         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1715                 /* set both sw defined pins */
1716                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1717
1718                 /* Set switch control to serdes energy detect */
1719                 reg = rd32(E1000_CONNSW);
1720                 reg |= E1000_CONNSW_ENRGSRC;
1721                 wr32(E1000_CONNSW, reg);
1722         }
1723
1724         reg = rd32(E1000_PCS_LCTL);
1725
1726         /* default pcs_autoneg to the same setting as mac autoneg */
1727         pcs_autoneg = hw->mac.autoneg;
1728
1729         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1730         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1731                 /* sgmii mode lets the phy handle forcing speed/duplex */
1732                 pcs_autoneg = true;
1733                 /* autoneg time out should be disabled for SGMII mode */
1734                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1735                 break;
1736         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1737                 /* disable PCS autoneg and support parallel detect only */
1738                 pcs_autoneg = false;
1739         default:
1740                 if (hw->mac.type == e1000_82575 ||
1741                     hw->mac.type == e1000_82576) {
1742                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1743                         if (ret_val) {
1744                                 hw_dbg(KERN_DEBUG "NVM Read Error\n\n");
1745                                 return ret_val;
1746                         }
1747
1748                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1749                                 pcs_autoneg = false;
1750                 }
1751
1752                 /* non-SGMII modes only supports a speed of 1000/Full for the
1753                  * link so it is best to just force the MAC and let the pcs
1754                  * link either autoneg or be forced to 1000/Full
1755                  */
1756                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1757                                 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1758
1759                 /* set speed of 1000/Full if speed/duplex is forced */
1760                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1761                 break;
1762         }
1763
1764         wr32(E1000_CTRL, ctrl_reg);
1765
1766         /* New SerDes mode allows for forcing speed or autonegotiating speed
1767          * at 1gb. Autoneg should be default set by most drivers. This is the
1768          * mode that will be compatible with older link partners and switches.
1769          * However, both are supported by the hardware and some drivers/tools.
1770          */
1771         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1772                 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1773
1774         if (pcs_autoneg) {
1775                 /* Set PCS register for autoneg */
1776                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1777                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1778
1779                 /* Disable force flow control for autoneg */
1780                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1781
1782                 /* Configure flow control advertisement for autoneg */
1783                 anadv_reg = rd32(E1000_PCS_ANADV);
1784                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1785                 switch (hw->fc.requested_mode) {
1786                 case e1000_fc_full:
1787                 case e1000_fc_rx_pause:
1788                         anadv_reg |= E1000_TXCW_ASM_DIR;
1789                         anadv_reg |= E1000_TXCW_PAUSE;
1790                         break;
1791                 case e1000_fc_tx_pause:
1792                         anadv_reg |= E1000_TXCW_ASM_DIR;
1793                         break;
1794                 default:
1795                         break;
1796                 }
1797                 wr32(E1000_PCS_ANADV, anadv_reg);
1798
1799                 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1800         } else {
1801                 /* Set PCS register for forced link */
1802                 reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
1803
1804                 /* Force flow control for forced link */
1805                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1806
1807                 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1808         }
1809
1810         wr32(E1000_PCS_LCTL, reg);
1811
1812         if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1813                 igb_force_mac_fc(hw);
1814
1815         return ret_val;
1816 }
1817
1818 /**
1819  *  igb_sgmii_active_82575 - Return sgmii state
1820  *  @hw: pointer to the HW structure
1821  *
1822  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1823  *  which can be enabled for use in the embedded applications.  Simply
1824  *  return the current state of the sgmii interface.
1825  **/
1826 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1827 {
1828         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1829         return dev_spec->sgmii_active;
1830 }
1831
1832 /**
1833  *  igb_reset_init_script_82575 - Inits HW defaults after reset
1834  *  @hw: pointer to the HW structure
1835  *
1836  *  Inits recommended HW defaults after a reset when there is no EEPROM
1837  *  detected. This is only for the 82575.
1838  **/
1839 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1840 {
1841         if (hw->mac.type == e1000_82575) {
1842                 hw_dbg("Running reset init script for 82575\n");
1843                 /* SerDes configuration via SERDESCTRL */
1844                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1845                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1846                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1847                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1848
1849                 /* CCM configuration via CCMCTL register */
1850                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1851                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1852
1853                 /* PCIe lanes configuration */
1854                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1855                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1856                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1857                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1858
1859                 /* PCIe PLL Configuration */
1860                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1861                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1862                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1863         }
1864
1865         return 0;
1866 }
1867
1868 /**
1869  *  igb_read_mac_addr_82575 - Read device MAC address
1870  *  @hw: pointer to the HW structure
1871  **/
1872 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1873 {
1874         s32 ret_val = 0;
1875
1876         /* If there's an alternate MAC address place it in RAR0
1877          * so that it will override the Si installed default perm
1878          * address.
1879          */
1880         ret_val = igb_check_alt_mac_addr(hw);
1881         if (ret_val)
1882                 goto out;
1883
1884         ret_val = igb_read_mac_addr(hw);
1885
1886 out:
1887         return ret_val;
1888 }
1889
1890 /**
1891  * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1892  * @hw: pointer to the HW structure
1893  *
1894  * In the case of a PHY power down to save power, or to turn off link during a
1895  * driver unload, or wake on lan is not enabled, remove the link.
1896  **/
1897 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1898 {
1899         /* If the management interface is not enabled, then power down */
1900         if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1901                 igb_power_down_phy_copper(hw);
1902 }
1903
1904 /**
1905  *  igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1906  *  @hw: pointer to the HW structure
1907  *
1908  *  Clears the hardware counters by reading the counter registers.
1909  **/
1910 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1911 {
1912         igb_clear_hw_cntrs_base(hw);
1913
1914         rd32(E1000_PRC64);
1915         rd32(E1000_PRC127);
1916         rd32(E1000_PRC255);
1917         rd32(E1000_PRC511);
1918         rd32(E1000_PRC1023);
1919         rd32(E1000_PRC1522);
1920         rd32(E1000_PTC64);
1921         rd32(E1000_PTC127);
1922         rd32(E1000_PTC255);
1923         rd32(E1000_PTC511);
1924         rd32(E1000_PTC1023);
1925         rd32(E1000_PTC1522);
1926
1927         rd32(E1000_ALGNERRC);
1928         rd32(E1000_RXERRC);
1929         rd32(E1000_TNCRS);
1930         rd32(E1000_CEXTERR);
1931         rd32(E1000_TSCTC);
1932         rd32(E1000_TSCTFC);
1933
1934         rd32(E1000_MGTPRC);
1935         rd32(E1000_MGTPDC);
1936         rd32(E1000_MGTPTC);
1937
1938         rd32(E1000_IAC);
1939         rd32(E1000_ICRXOC);
1940
1941         rd32(E1000_ICRXPTC);
1942         rd32(E1000_ICRXATC);
1943         rd32(E1000_ICTXPTC);
1944         rd32(E1000_ICTXATC);
1945         rd32(E1000_ICTXQEC);
1946         rd32(E1000_ICTXQMTC);
1947         rd32(E1000_ICRXDMTC);
1948
1949         rd32(E1000_CBTMPC);
1950         rd32(E1000_HTDPMC);
1951         rd32(E1000_CBRMPC);
1952         rd32(E1000_RPTHC);
1953         rd32(E1000_HGPTC);
1954         rd32(E1000_HTCBDPC);
1955         rd32(E1000_HGORCL);
1956         rd32(E1000_HGORCH);
1957         rd32(E1000_HGOTCL);
1958         rd32(E1000_HGOTCH);
1959         rd32(E1000_LENERRS);
1960
1961         /* This register should not be read in copper configurations */
1962         if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1963             igb_sgmii_active_82575(hw))
1964                 rd32(E1000_SCVPC);
1965 }
1966
1967 /**
1968  *  igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1969  *  @hw: pointer to the HW structure
1970  *
1971  *  After rx enable if manageability is enabled then there is likely some
1972  *  bad data at the start of the fifo and possibly in the DMA fifo. This
1973  *  function clears the fifos and flushes any packets that came in as rx was
1974  *  being enabled.
1975  **/
1976 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1977 {
1978         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1979         int i, ms_wait;
1980
1981         /* disable IPv6 options as per hardware errata */
1982         rfctl = rd32(E1000_RFCTL);
1983         rfctl |= E1000_RFCTL_IPV6_EX_DIS;
1984         wr32(E1000_RFCTL, rfctl);
1985
1986         if (hw->mac.type != e1000_82575 ||
1987             !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1988                 return;
1989
1990         /* Disable all RX queues */
1991         for (i = 0; i < 4; i++) {
1992                 rxdctl[i] = rd32(E1000_RXDCTL(i));
1993                 wr32(E1000_RXDCTL(i),
1994                      rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1995         }
1996         /* Poll all queues to verify they have shut down */
1997         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1998                 usleep_range(1000, 2000);
1999                 rx_enabled = 0;
2000                 for (i = 0; i < 4; i++)
2001                         rx_enabled |= rd32(E1000_RXDCTL(i));
2002                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2003                         break;
2004         }
2005
2006         if (ms_wait == 10)
2007                 hw_dbg("Queue disable timed out after 10ms\n");
2008
2009         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2010          * incoming packets are rejected.  Set enable and wait 2ms so that
2011          * any packet that was coming in as RCTL.EN was set is flushed
2012          */
2013         wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2014
2015         rlpml = rd32(E1000_RLPML);
2016         wr32(E1000_RLPML, 0);
2017
2018         rctl = rd32(E1000_RCTL);
2019         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2020         temp_rctl |= E1000_RCTL_LPE;
2021
2022         wr32(E1000_RCTL, temp_rctl);
2023         wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2024         wrfl();
2025         usleep_range(2000, 3000);
2026
2027         /* Enable RX queues that were previously enabled and restore our
2028          * previous state
2029          */
2030         for (i = 0; i < 4; i++)
2031                 wr32(E1000_RXDCTL(i), rxdctl[i]);
2032         wr32(E1000_RCTL, rctl);
2033         wrfl();
2034
2035         wr32(E1000_RLPML, rlpml);
2036         wr32(E1000_RFCTL, rfctl);
2037
2038         /* Flush receive errors generated by workaround */
2039         rd32(E1000_ROC);
2040         rd32(E1000_RNBC);
2041         rd32(E1000_MPC);
2042 }
2043
2044 /**
2045  *  igb_set_pcie_completion_timeout - set pci-e completion timeout
2046  *  @hw: pointer to the HW structure
2047  *
2048  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2049  *  however the hardware default for these parts is 500us to 1ms which is less
2050  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2051  *  increase the value to either 10ms to 200ms for capability version 1 config,
2052  *  or 16ms to 55ms for version 2.
2053  **/
2054 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
2055 {
2056         u32 gcr = rd32(E1000_GCR);
2057         s32 ret_val = 0;
2058         u16 pcie_devctl2;
2059
2060         /* only take action if timeout value is defaulted to 0 */
2061         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2062                 goto out;
2063
2064         /* if capabilities version is type 1 we can write the
2065          * timeout of 10ms to 200ms through the GCR register
2066          */
2067         if (!(gcr & E1000_GCR_CAP_VER2)) {
2068                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2069                 goto out;
2070         }
2071
2072         /* for version 2 capabilities we need to write the config space
2073          * directly in order to set the completion timeout value for
2074          * 16ms to 55ms
2075          */
2076         ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2077                                         &pcie_devctl2);
2078         if (ret_val)
2079                 goto out;
2080
2081         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2082
2083         ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2084                                          &pcie_devctl2);
2085 out:
2086         /* disable completion timeout resend */
2087         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2088
2089         wr32(E1000_GCR, gcr);
2090         return ret_val;
2091 }
2092
2093 /**
2094  *  igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2095  *  @hw: pointer to the hardware struct
2096  *  @enable: state to enter, either enabled or disabled
2097  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2098  *
2099  *  enables/disables L2 switch anti-spoofing functionality.
2100  **/
2101 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2102 {
2103         u32 reg_val, reg_offset;
2104
2105         switch (hw->mac.type) {
2106         case e1000_82576:
2107                 reg_offset = E1000_DTXSWC;
2108                 break;
2109         case e1000_i350:
2110         case e1000_i354:
2111                 reg_offset = E1000_TXSWC;
2112                 break;
2113         default:
2114                 return;
2115         }
2116
2117         reg_val = rd32(reg_offset);
2118         if (enable) {
2119                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2120                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2121                 /* The PF can spoof - it has to in order to
2122                  * support emulation mode NICs
2123                  */
2124                 reg_val ^= (BIT(pf) | BIT(pf + MAX_NUM_VFS));
2125         } else {
2126                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2127                              E1000_DTXSWC_VLAN_SPOOF_MASK);
2128         }
2129         wr32(reg_offset, reg_val);
2130 }
2131
2132 /**
2133  *  igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2134  *  @hw: pointer to the hardware struct
2135  *  @enable: state to enter, either enabled or disabled
2136  *
2137  *  enables/disables L2 switch loopback functionality.
2138  **/
2139 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2140 {
2141         u32 dtxswc;
2142
2143         switch (hw->mac.type) {
2144         case e1000_82576:
2145                 dtxswc = rd32(E1000_DTXSWC);
2146                 if (enable)
2147                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2148                 else
2149                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2150                 wr32(E1000_DTXSWC, dtxswc);
2151                 break;
2152         case e1000_i354:
2153         case e1000_i350:
2154                 dtxswc = rd32(E1000_TXSWC);
2155                 if (enable)
2156                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2157                 else
2158                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2159                 wr32(E1000_TXSWC, dtxswc);
2160                 break;
2161         default:
2162                 /* Currently no other hardware supports loopback */
2163                 break;
2164         }
2165
2166 }
2167
2168 /**
2169  *  igb_vmdq_set_replication_pf - enable or disable vmdq replication
2170  *  @hw: pointer to the hardware struct
2171  *  @enable: state to enter, either enabled or disabled
2172  *
2173  *  enables/disables replication of packets across multiple pools.
2174  **/
2175 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2176 {
2177         u32 vt_ctl = rd32(E1000_VT_CTL);
2178
2179         if (enable)
2180                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2181         else
2182                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2183
2184         wr32(E1000_VT_CTL, vt_ctl);
2185 }
2186
2187 /**
2188  *  igb_read_phy_reg_82580 - Read 82580 MDI control register
2189  *  @hw: pointer to the HW structure
2190  *  @offset: register offset to be read
2191  *  @data: pointer to the read data
2192  *
2193  *  Reads the MDI control register in the PHY at offset and stores the
2194  *  information read to data.
2195  **/
2196 s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2197 {
2198         s32 ret_val;
2199
2200         ret_val = hw->phy.ops.acquire(hw);
2201         if (ret_val)
2202                 goto out;
2203
2204         ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2205
2206         hw->phy.ops.release(hw);
2207
2208 out:
2209         return ret_val;
2210 }
2211
2212 /**
2213  *  igb_write_phy_reg_82580 - Write 82580 MDI control register
2214  *  @hw: pointer to the HW structure
2215  *  @offset: register offset to write to
2216  *  @data: data to write to register at offset
2217  *
2218  *  Writes data to MDI control register in the PHY at offset.
2219  **/
2220 s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2221 {
2222         s32 ret_val;
2223
2224
2225         ret_val = hw->phy.ops.acquire(hw);
2226         if (ret_val)
2227                 goto out;
2228
2229         ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2230
2231         hw->phy.ops.release(hw);
2232
2233 out:
2234         return ret_val;
2235 }
2236
2237 /**
2238  *  igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2239  *  @hw: pointer to the HW structure
2240  *
2241  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2242  *  the values found in the EEPROM.  This addresses an issue in which these
2243  *  bits are not restored from EEPROM after reset.
2244  **/
2245 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2246 {
2247         s32 ret_val = 0;
2248         u32 mdicnfg;
2249         u16 nvm_data = 0;
2250
2251         if (hw->mac.type != e1000_82580)
2252                 goto out;
2253         if (!igb_sgmii_active_82575(hw))
2254                 goto out;
2255
2256         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2257                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2258                                    &nvm_data);
2259         if (ret_val) {
2260                 hw_dbg("NVM Read Error\n");
2261                 goto out;
2262         }
2263
2264         mdicnfg = rd32(E1000_MDICNFG);
2265         if (nvm_data & NVM_WORD24_EXT_MDIO)
2266                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2267         if (nvm_data & NVM_WORD24_COM_MDIO)
2268                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2269         wr32(E1000_MDICNFG, mdicnfg);
2270 out:
2271         return ret_val;
2272 }
2273
2274 /**
2275  *  igb_reset_hw_82580 - Reset hardware
2276  *  @hw: pointer to the HW structure
2277  *
2278  *  This resets function or entire device (all ports, etc.)
2279  *  to a known state.
2280  **/
2281 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2282 {
2283         s32 ret_val = 0;
2284         /* BH SW mailbox bit in SW_FW_SYNC */
2285         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2286         u32 ctrl;
2287         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2288
2289         hw->dev_spec._82575.global_device_reset = false;
2290
2291         /* due to hw errata, global device reset doesn't always
2292          * work on 82580
2293          */
2294         if (hw->mac.type == e1000_82580)
2295                 global_device_reset = false;
2296
2297         /* Get current control state. */
2298         ctrl = rd32(E1000_CTRL);
2299
2300         /* Prevent the PCI-E bus from sticking if there is no TLP connection
2301          * on the last TLP read/write transaction when MAC is reset.
2302          */
2303         ret_val = igb_disable_pcie_master(hw);
2304         if (ret_val)
2305                 hw_dbg("PCI-E Master disable polling has failed.\n");
2306
2307         hw_dbg("Masking off all interrupts\n");
2308         wr32(E1000_IMC, 0xffffffff);
2309         wr32(E1000_RCTL, 0);
2310         wr32(E1000_TCTL, E1000_TCTL_PSP);
2311         wrfl();
2312
2313         usleep_range(10000, 11000);
2314
2315         /* Determine whether or not a global dev reset is requested */
2316         if (global_device_reset &&
2317                 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2318                         global_device_reset = false;
2319
2320         if (global_device_reset &&
2321                 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2322                 ctrl |= E1000_CTRL_DEV_RST;
2323         else
2324                 ctrl |= E1000_CTRL_RST;
2325
2326         wr32(E1000_CTRL, ctrl);
2327         wrfl();
2328
2329         /* Add delay to insure DEV_RST has time to complete */
2330         if (global_device_reset)
2331                 usleep_range(5000, 6000);
2332
2333         ret_val = igb_get_auto_rd_done(hw);
2334         if (ret_val) {
2335                 /* When auto config read does not complete, do not
2336                  * return with an error. This can happen in situations
2337                  * where there is no eeprom and prevents getting link.
2338                  */
2339                 hw_dbg("Auto Read Done did not complete\n");
2340         }
2341
2342         /* clear global device reset status bit */
2343         wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2344
2345         /* Clear any pending interrupt events. */
2346         wr32(E1000_IMC, 0xffffffff);
2347         rd32(E1000_ICR);
2348
2349         ret_val = igb_reset_mdicnfg_82580(hw);
2350         if (ret_val)
2351                 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2352
2353         /* Install any alternate MAC address into RAR0 */
2354         ret_val = igb_check_alt_mac_addr(hw);
2355
2356         /* Release semaphore */
2357         if (global_device_reset)
2358                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2359
2360         return ret_val;
2361 }
2362
2363 /**
2364  *  igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2365  *  @data: data received by reading RXPBS register
2366  *
2367  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2368  *  This function converts the retrieved value into the correct table value
2369  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2370  *  0x0 36  72 144   1   2   4   8  16
2371  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2372  */
2373 u16 igb_rxpbs_adjust_82580(u32 data)
2374 {
2375         u16 ret_val = 0;
2376
2377         if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
2378                 ret_val = e1000_82580_rxpbs_table[data];
2379
2380         return ret_val;
2381 }
2382
2383 /**
2384  *  igb_validate_nvm_checksum_with_offset - Validate EEPROM
2385  *  checksum
2386  *  @hw: pointer to the HW structure
2387  *  @offset: offset in words of the checksum protected region
2388  *
2389  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2390  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2391  **/
2392 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2393                                                  u16 offset)
2394 {
2395         s32 ret_val = 0;
2396         u16 checksum = 0;
2397         u16 i, nvm_data;
2398
2399         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2400                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2401                 if (ret_val) {
2402                         hw_dbg("NVM Read Error\n");
2403                         goto out;
2404                 }
2405                 checksum += nvm_data;
2406         }
2407
2408         if (checksum != (u16) NVM_SUM) {
2409                 hw_dbg("NVM Checksum Invalid\n");
2410                 ret_val = -E1000_ERR_NVM;
2411                 goto out;
2412         }
2413
2414 out:
2415         return ret_val;
2416 }
2417
2418 /**
2419  *  igb_update_nvm_checksum_with_offset - Update EEPROM
2420  *  checksum
2421  *  @hw: pointer to the HW structure
2422  *  @offset: offset in words of the checksum protected region
2423  *
2424  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2425  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2426  *  value to the EEPROM.
2427  **/
2428 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2429 {
2430         s32 ret_val;
2431         u16 checksum = 0;
2432         u16 i, nvm_data;
2433
2434         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2435                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2436                 if (ret_val) {
2437                         hw_dbg("NVM Read Error while updating checksum.\n");
2438                         goto out;
2439                 }
2440                 checksum += nvm_data;
2441         }
2442         checksum = (u16) NVM_SUM - checksum;
2443         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2444                                 &checksum);
2445         if (ret_val)
2446                 hw_dbg("NVM Write Error while updating checksum.\n");
2447
2448 out:
2449         return ret_val;
2450 }
2451
2452 /**
2453  *  igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2454  *  @hw: pointer to the HW structure
2455  *
2456  *  Calculates the EEPROM section checksum by reading/adding each word of
2457  *  the EEPROM and then verifies that the sum of the EEPROM is
2458  *  equal to 0xBABA.
2459  **/
2460 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2461 {
2462         s32 ret_val = 0;
2463         u16 eeprom_regions_count = 1;
2464         u16 j, nvm_data;
2465         u16 nvm_offset;
2466
2467         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2468         if (ret_val) {
2469                 hw_dbg("NVM Read Error\n");
2470                 goto out;
2471         }
2472
2473         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2474                 /* if checksums compatibility bit is set validate checksums
2475                  * for all 4 ports.
2476                  */
2477                 eeprom_regions_count = 4;
2478         }
2479
2480         for (j = 0; j < eeprom_regions_count; j++) {
2481                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2482                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2483                                                                 nvm_offset);
2484                 if (ret_val != 0)
2485                         goto out;
2486         }
2487
2488 out:
2489         return ret_val;
2490 }
2491
2492 /**
2493  *  igb_update_nvm_checksum_82580 - Update EEPROM checksum
2494  *  @hw: pointer to the HW structure
2495  *
2496  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2497  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2498  *  checksum and writes the value to the EEPROM.
2499  **/
2500 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2501 {
2502         s32 ret_val;
2503         u16 j, nvm_data;
2504         u16 nvm_offset;
2505
2506         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2507         if (ret_val) {
2508                 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");
2509                 goto out;
2510         }
2511
2512         if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2513                 /* set compatibility bit to validate checksums appropriately */
2514                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2515                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2516                                         &nvm_data);
2517                 if (ret_val) {
2518                         hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");
2519                         goto out;
2520                 }
2521         }
2522
2523         for (j = 0; j < 4; j++) {
2524                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2525                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2526                 if (ret_val)
2527                         goto out;
2528         }
2529
2530 out:
2531         return ret_val;
2532 }
2533
2534 /**
2535  *  igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2536  *  @hw: pointer to the HW structure
2537  *
2538  *  Calculates the EEPROM section checksum by reading/adding each word of
2539  *  the EEPROM and then verifies that the sum of the EEPROM is
2540  *  equal to 0xBABA.
2541  **/
2542 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2543 {
2544         s32 ret_val = 0;
2545         u16 j;
2546         u16 nvm_offset;
2547
2548         for (j = 0; j < 4; j++) {
2549                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2550                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2551                                                                 nvm_offset);
2552                 if (ret_val != 0)
2553                         goto out;
2554         }
2555
2556 out:
2557         return ret_val;
2558 }
2559
2560 /**
2561  *  igb_update_nvm_checksum_i350 - Update EEPROM checksum
2562  *  @hw: pointer to the HW structure
2563  *
2564  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2565  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2566  *  checksum and writes the value to the EEPROM.
2567  **/
2568 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2569 {
2570         s32 ret_val = 0;
2571         u16 j;
2572         u16 nvm_offset;
2573
2574         for (j = 0; j < 4; j++) {
2575                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2576                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2577                 if (ret_val != 0)
2578                         goto out;
2579         }
2580
2581 out:
2582         return ret_val;
2583 }
2584
2585 /**
2586  *  __igb_access_emi_reg - Read/write EMI register
2587  *  @hw: pointer to the HW structure
2588  *  @addr: EMI address to program
2589  *  @data: pointer to value to read/write from/to the EMI address
2590  *  @read: boolean flag to indicate read or write
2591  **/
2592 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2593                                   u16 *data, bool read)
2594 {
2595         s32 ret_val = 0;
2596
2597         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2598         if (ret_val)
2599                 return ret_val;
2600
2601         if (read)
2602                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2603         else
2604                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2605
2606         return ret_val;
2607 }
2608
2609 /**
2610  *  igb_read_emi_reg - Read Extended Management Interface register
2611  *  @hw: pointer to the HW structure
2612  *  @addr: EMI address to program
2613  *  @data: value to be read from the EMI address
2614  **/
2615 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2616 {
2617         return __igb_access_emi_reg(hw, addr, data, true);
2618 }
2619
2620 /**
2621  *  igb_set_eee_i350 - Enable/disable EEE support
2622  *  @hw: pointer to the HW structure
2623  *  @adv1G: boolean flag enabling 1G EEE advertisement
2624  *  @adv100m: boolean flag enabling 100M EEE advertisement
2625  *
2626  *  Enable/disable EEE based on setting in dev_spec structure.
2627  *
2628  **/
2629 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2630 {
2631         u32 ipcnfg, eeer;
2632
2633         if ((hw->mac.type < e1000_i350) ||
2634             (hw->phy.media_type != e1000_media_type_copper))
2635                 goto out;
2636         ipcnfg = rd32(E1000_IPCNFG);
2637         eeer = rd32(E1000_EEER);
2638
2639         /* enable or disable per user setting */
2640         if (!(hw->dev_spec._82575.eee_disable)) {
2641                 u32 eee_su = rd32(E1000_EEE_SU);
2642
2643                 if (adv100M)
2644                         ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2645                 else
2646                         ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2647
2648                 if (adv1G)
2649                         ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2650                 else
2651                         ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2652
2653                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2654                         E1000_EEER_LPI_FC);
2655
2656                 /* This bit should not be set in normal operation. */
2657                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2658                         hw_dbg("LPI Clock Stop Bit should not be set!\n");
2659
2660         } else {
2661                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2662                         E1000_IPCNFG_EEE_100M_AN);
2663                 eeer &= ~(E1000_EEER_TX_LPI_EN |
2664                         E1000_EEER_RX_LPI_EN |
2665                         E1000_EEER_LPI_FC);
2666         }
2667         wr32(E1000_IPCNFG, ipcnfg);
2668         wr32(E1000_EEER, eeer);
2669         rd32(E1000_IPCNFG);
2670         rd32(E1000_EEER);
2671 out:
2672
2673         return 0;
2674 }
2675
2676 /**
2677  *  igb_set_eee_i354 - Enable/disable EEE support
2678  *  @hw: pointer to the HW structure
2679  *  @adv1G: boolean flag enabling 1G EEE advertisement
2680  *  @adv100m: boolean flag enabling 100M EEE advertisement
2681  *
2682  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2683  *
2684  **/
2685 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2686 {
2687         struct e1000_phy_info *phy = &hw->phy;
2688         s32 ret_val = 0;
2689         u16 phy_data;
2690
2691         if ((hw->phy.media_type != e1000_media_type_copper) ||
2692             ((phy->id != M88E1543_E_PHY_ID) &&
2693              (phy->id != M88E1512_E_PHY_ID)))
2694                 goto out;
2695
2696         if (!hw->dev_spec._82575.eee_disable) {
2697                 /* Switch to PHY page 18. */
2698                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2699                 if (ret_val)
2700                         goto out;
2701
2702                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2703                                             &phy_data);
2704                 if (ret_val)
2705                         goto out;
2706
2707                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2708                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2709                                              phy_data);
2710                 if (ret_val)
2711                         goto out;
2712
2713                 /* Return the PHY to page 0. */
2714                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2715                 if (ret_val)
2716                         goto out;
2717
2718                 /* Turn on EEE advertisement. */
2719                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2720                                              E1000_EEE_ADV_DEV_I354,
2721                                              &phy_data);
2722                 if (ret_val)
2723                         goto out;
2724
2725                 if (adv100M)
2726                         phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2727                 else
2728                         phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2729
2730                 if (adv1G)
2731                         phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2732                 else
2733                         phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2734
2735                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2736                                                 E1000_EEE_ADV_DEV_I354,
2737                                                 phy_data);
2738         } else {
2739                 /* Turn off EEE advertisement. */
2740                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2741                                              E1000_EEE_ADV_DEV_I354,
2742                                              &phy_data);
2743                 if (ret_val)
2744                         goto out;
2745
2746                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2747                               E1000_EEE_ADV_1000_SUPPORTED);
2748                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2749                                               E1000_EEE_ADV_DEV_I354,
2750                                               phy_data);
2751         }
2752
2753 out:
2754         return ret_val;
2755 }
2756
2757 /**
2758  *  igb_get_eee_status_i354 - Get EEE status
2759  *  @hw: pointer to the HW structure
2760  *  @status: EEE status
2761  *
2762  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
2763  *  been received.
2764  **/
2765 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2766 {
2767         struct e1000_phy_info *phy = &hw->phy;
2768         s32 ret_val = 0;
2769         u16 phy_data;
2770
2771         /* Check if EEE is supported on this device. */
2772         if ((hw->phy.media_type != e1000_media_type_copper) ||
2773             ((phy->id != M88E1543_E_PHY_ID) &&
2774              (phy->id != M88E1512_E_PHY_ID)))
2775                 goto out;
2776
2777         ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2778                                      E1000_PCS_STATUS_DEV_I354,
2779                                      &phy_data);
2780         if (ret_val)
2781                 goto out;
2782
2783         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2784                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2785
2786 out:
2787         return ret_val;
2788 }
2789
2790 static const u8 e1000_emc_temp_data[4] = {
2791         E1000_EMC_INTERNAL_DATA,
2792         E1000_EMC_DIODE1_DATA,
2793         E1000_EMC_DIODE2_DATA,
2794         E1000_EMC_DIODE3_DATA
2795 };
2796 static const u8 e1000_emc_therm_limit[4] = {
2797         E1000_EMC_INTERNAL_THERM_LIMIT,
2798         E1000_EMC_DIODE1_THERM_LIMIT,
2799         E1000_EMC_DIODE2_THERM_LIMIT,
2800         E1000_EMC_DIODE3_THERM_LIMIT
2801 };
2802
2803 #ifdef CONFIG_IGB_HWMON
2804 /**
2805  *  igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2806  *  @hw: pointer to hardware structure
2807  *
2808  *  Updates the temperatures in mac.thermal_sensor_data
2809  **/
2810 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2811 {
2812         u16 ets_offset;
2813         u16 ets_cfg;
2814         u16 ets_sensor;
2815         u8  num_sensors;
2816         u8  sensor_index;
2817         u8  sensor_location;
2818         u8  i;
2819         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2820
2821         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2822                 return E1000_NOT_IMPLEMENTED;
2823
2824         data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2825
2826         /* Return the internal sensor only if ETS is unsupported */
2827         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2828         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2829                 return 0;
2830
2831         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2832         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2833             != NVM_ETS_TYPE_EMC)
2834                 return E1000_NOT_IMPLEMENTED;
2835
2836         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2837         if (num_sensors > E1000_MAX_SENSORS)
2838                 num_sensors = E1000_MAX_SENSORS;
2839
2840         for (i = 1; i < num_sensors; i++) {
2841                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2842                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2843                                 NVM_ETS_DATA_INDEX_SHIFT);
2844                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2845                                    NVM_ETS_DATA_LOC_SHIFT);
2846
2847                 if (sensor_location != 0)
2848                         hw->phy.ops.read_i2c_byte(hw,
2849                                         e1000_emc_temp_data[sensor_index],
2850                                         E1000_I2C_THERMAL_SENSOR_ADDR,
2851                                         &data->sensor[i].temp);
2852         }
2853         return 0;
2854 }
2855
2856 /**
2857  *  igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2858  *  @hw: pointer to hardware structure
2859  *
2860  *  Sets the thermal sensor thresholds according to the NVM map
2861  *  and save off the threshold and location values into mac.thermal_sensor_data
2862  **/
2863 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2864 {
2865         u16 ets_offset;
2866         u16 ets_cfg;
2867         u16 ets_sensor;
2868         u8  low_thresh_delta;
2869         u8  num_sensors;
2870         u8  sensor_index;
2871         u8  sensor_location;
2872         u8  therm_limit;
2873         u8  i;
2874         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2875
2876         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2877                 return E1000_NOT_IMPLEMENTED;
2878
2879         memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2880
2881         data->sensor[0].location = 0x1;
2882         data->sensor[0].caution_thresh =
2883                 (rd32(E1000_THHIGHTC) & 0xFF);
2884         data->sensor[0].max_op_thresh =
2885                 (rd32(E1000_THLOWTC) & 0xFF);
2886
2887         /* Return the internal sensor only if ETS is unsupported */
2888         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2889         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2890                 return 0;
2891
2892         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2893         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2894             != NVM_ETS_TYPE_EMC)
2895                 return E1000_NOT_IMPLEMENTED;
2896
2897         low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2898                             NVM_ETS_LTHRES_DELTA_SHIFT);
2899         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2900
2901         for (i = 1; i <= num_sensors; i++) {
2902                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2903                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2904                                 NVM_ETS_DATA_INDEX_SHIFT);
2905                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2906                                    NVM_ETS_DATA_LOC_SHIFT);
2907                 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2908
2909                 hw->phy.ops.write_i2c_byte(hw,
2910                         e1000_emc_therm_limit[sensor_index],
2911                         E1000_I2C_THERMAL_SENSOR_ADDR,
2912                         therm_limit);
2913
2914                 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2915                         data->sensor[i].location = sensor_location;
2916                         data->sensor[i].caution_thresh = therm_limit;
2917                         data->sensor[i].max_op_thresh = therm_limit -
2918                                                         low_thresh_delta;
2919                 }
2920         }
2921         return 0;
2922 }
2923
2924 #endif
2925 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2926         .init_hw              = igb_init_hw_82575,
2927         .check_for_link       = igb_check_for_link_82575,
2928         .rar_set              = igb_rar_set,
2929         .read_mac_addr        = igb_read_mac_addr_82575,
2930         .get_speed_and_duplex = igb_get_link_up_info_82575,
2931 #ifdef CONFIG_IGB_HWMON
2932         .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2933         .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2934 #endif
2935 };
2936
2937 static const struct e1000_phy_operations e1000_phy_ops_82575 = {
2938         .acquire              = igb_acquire_phy_82575,
2939         .get_cfg_done         = igb_get_cfg_done_82575,
2940         .release              = igb_release_phy_82575,
2941         .write_i2c_byte       = igb_write_i2c_byte,
2942         .read_i2c_byte        = igb_read_i2c_byte,
2943 };
2944
2945 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2946         .acquire              = igb_acquire_nvm_82575,
2947         .read                 = igb_read_nvm_eerd,
2948         .release              = igb_release_nvm_82575,
2949         .write                = igb_write_nvm_spi,
2950 };
2951
2952 const struct e1000_info e1000_82575_info = {
2953         .get_invariants = igb_get_invariants_82575,
2954         .mac_ops = &e1000_mac_ops_82575,
2955         .phy_ops = &e1000_phy_ops_82575,
2956         .nvm_ops = &e1000_nvm_ops_82575,
2957 };
2958