1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Intel Corporation. */
4 #include "ice_common.h"
8 * @hw: pointer to the HW struct
9 * @module_typeid: module pointer location in words from the NVM beginning
10 * @offset: byte offset from the module beginning
11 * @length: length of the section to be read (in bytes from the offset)
12 * @data: command buffer (size [bytes] = length)
13 * @last_command: tells if this is the last command in a series
14 * @read_shadow_ram: tell if this is a shadow RAM read
15 * @cd: pointer to command details structure or NULL
17 * Read the NVM using the admin queue commands (0x0701)
19 static enum ice_status
20 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
21 void *data, bool last_command, bool read_shadow_ram,
24 struct ice_aq_desc desc;
25 struct ice_aqc_nvm *cmd;
27 cmd = &desc.params.nvm;
29 if (offset > ICE_AQC_NVM_MAX_OFFSET)
32 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
34 if (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)
35 cmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;
37 /* If this is the last command in a series, set the proper flag. */
39 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
40 cmd->module_typeid = cpu_to_le16(module_typeid);
41 cmd->offset_low = cpu_to_le16(offset & 0xFFFF);
42 cmd->offset_high = (offset >> 16) & 0xFF;
43 cmd->length = cpu_to_le16(length);
45 return ice_aq_send_cmd(hw, &desc, data, length, cd);
49 * ice_read_flat_nvm - Read portion of NVM by flat offset
50 * @hw: pointer to the HW struct
51 * @offset: offset from beginning of NVM
52 * @length: (in) number of bytes to read; (out) number of bytes actually read
53 * @data: buffer to return data in (sized to fit the specified length)
54 * @read_shadow_ram: if true, read from shadow RAM instead of NVM
56 * Reads a portion of the NVM, as a flat memory space. This function correctly
57 * breaks read requests across Shadow RAM sectors and ensures that no single
58 * read request exceeds the maximum 4Kb read for a single AdminQ command.
60 * Returns a status code on failure. Note that the data pointer may be
61 * partially updated if some reads succeed before a failure.
64 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
67 enum ice_status status;
74 /* Verify the length of the read if this is for the Shadow RAM */
75 if (read_shadow_ram && ((offset + inlen) > (hw->nvm.sr_words * 2u))) {
76 ice_debug(hw, ICE_DBG_NVM,
77 "NVM error: requested offset is beyond Shadow RAM limit\n");
82 u32 read_size, sector_offset;
84 /* ice_aq_read_nvm cannot read more than 4Kb at a time.
85 * Additionally, a read from the Shadow RAM may not cross over
86 * a sector boundary. Conveniently, the sector size is also
89 sector_offset = offset % ICE_AQ_MAX_BUF_LEN;
90 read_size = min_t(u32, ICE_AQ_MAX_BUF_LEN - sector_offset,
93 last_cmd = !(bytes_read + read_size < inlen);
95 status = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,
97 data + bytes_read, last_cmd,
98 read_shadow_ram, NULL);
102 bytes_read += read_size;
106 *length = bytes_read;
112 * @hw: pointer to the HW struct
113 * @module_typeid: module pointer location in words from the NVM beginning
114 * @offset: byte offset from the module beginning
115 * @length: length of the section to be written (in bytes from the offset)
116 * @data: command buffer (size [bytes] = length)
117 * @last_command: tells if this is the last command in a series
118 * @command_flags: command parameters
119 * @cd: pointer to command details structure or NULL
121 * Update the NVM using the admin queue commands (0x0703)
124 ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
125 u16 length, void *data, bool last_command, u8 command_flags,
126 struct ice_sq_cd *cd)
128 struct ice_aq_desc desc;
129 struct ice_aqc_nvm *cmd;
131 cmd = &desc.params.nvm;
133 /* In offset the highest byte must be zeroed. */
134 if (offset & 0xFF000000)
135 return ICE_ERR_PARAM;
137 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write);
139 cmd->cmd_flags |= command_flags;
141 /* If this is the last command in a series, set the proper flag. */
143 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
144 cmd->module_typeid = cpu_to_le16(module_typeid);
145 cmd->offset_low = cpu_to_le16(offset & 0xFFFF);
146 cmd->offset_high = (offset >> 16) & 0xFF;
147 cmd->length = cpu_to_le16(length);
149 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
151 return ice_aq_send_cmd(hw, &desc, data, length, cd);
156 * @hw: pointer to the HW struct
157 * @module_typeid: module pointer location in words from the NVM beginning
158 * @cd: pointer to command details structure or NULL
160 * Erase the NVM sector using the admin queue commands (0x0702)
163 ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd)
165 struct ice_aq_desc desc;
166 struct ice_aqc_nvm *cmd;
168 cmd = &desc.params.nvm;
170 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_erase);
172 cmd->module_typeid = cpu_to_le16(module_typeid);
173 cmd->length = cpu_to_le16(ICE_AQC_NVM_ERASE_LEN);
175 cmd->offset_high = 0;
177 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
181 * ice_read_sr_word_aq - Reads Shadow RAM via AQ
182 * @hw: pointer to the HW structure
183 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
184 * @data: word read from the Shadow RAM
186 * Reads one 16 bit word from the Shadow RAM using ice_read_flat_nvm.
188 static enum ice_status
189 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
191 u32 bytes = sizeof(u16);
192 enum ice_status status;
195 /* Note that ice_read_flat_nvm takes into account the 4Kb AdminQ and
196 * Shadow RAM sector restrictions necessary when reading from the NVM.
198 status = ice_read_flat_nvm(hw, offset * sizeof(u16), &bytes,
199 (u8 *)&data_local, true);
203 *data = le16_to_cpu(data_local);
208 * ice_acquire_nvm - Generic request for acquiring the NVM ownership
209 * @hw: pointer to the HW structure
210 * @access: NVM access type (read or write)
212 * This function will request NVM ownership.
215 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
217 if (hw->nvm.blank_nvm_mode)
220 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
224 * ice_release_nvm - Generic request for releasing the NVM ownership
225 * @hw: pointer to the HW structure
227 * This function will release NVM ownership.
229 void ice_release_nvm(struct ice_hw *hw)
231 if (hw->nvm.blank_nvm_mode)
234 ice_release_res(hw, ICE_NVM_RES_ID);
238 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
239 * @hw: pointer to the HW structure
240 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
241 * @data: word read from the Shadow RAM
243 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
245 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
247 enum ice_status status;
249 status = ice_acquire_nvm(hw, ICE_RES_READ);
251 status = ice_read_sr_word_aq(hw, offset, data);
259 * ice_get_pfa_module_tlv - Reads sub module TLV from NVM PFA
260 * @hw: pointer to hardware structure
261 * @module_tlv: pointer to module TLV to return
262 * @module_tlv_len: pointer to module TLV length to return
263 * @module_type: module type requested
265 * Finds the requested sub module TLV type from the Preserved Field
266 * Area (PFA) and returns the TLV pointer and length. The caller can
267 * use these to read the variable length TLV value.
270 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
273 enum ice_status status;
274 u16 pfa_len, pfa_ptr;
277 status = ice_read_sr_word(hw, ICE_SR_PFA_PTR, &pfa_ptr);
279 ice_debug(hw, ICE_DBG_INIT, "Preserved Field Array pointer.\n");
282 status = ice_read_sr_word(hw, pfa_ptr, &pfa_len);
284 ice_debug(hw, ICE_DBG_INIT, "Failed to read PFA length.\n");
287 /* Starting with first TLV after PFA length, iterate through the list
288 * of TLVs to find the requested one.
290 next_tlv = pfa_ptr + 1;
291 while (next_tlv < pfa_ptr + pfa_len) {
292 u16 tlv_sub_module_type;
296 status = ice_read_sr_word(hw, next_tlv, &tlv_sub_module_type);
298 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV type.\n");
301 /* Read TLV length */
302 status = ice_read_sr_word(hw, next_tlv + 1, &tlv_len);
304 ice_debug(hw, ICE_DBG_INIT, "Failed to read TLV length.\n");
307 if (tlv_sub_module_type == module_type) {
309 *module_tlv = next_tlv;
310 *module_tlv_len = tlv_len;
313 return ICE_ERR_INVAL_SIZE;
315 /* Check next TLV, i.e. current TLV pointer + length + 2 words
316 * (for current TLV's type and length)
318 next_tlv = next_tlv + tlv_len + 2;
320 /* Module does not exist */
321 return ICE_ERR_DOES_NOT_EXIST;
325 * ice_read_pba_string - Reads part number string from NVM
326 * @hw: pointer to hardware structure
327 * @pba_num: stores the part number string from the NVM
328 * @pba_num_size: part number string buffer length
330 * Reads the part number string from the NVM.
333 ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size)
335 u16 pba_tlv, pba_tlv_len;
336 enum ice_status status;
337 u16 pba_word, pba_size;
340 status = ice_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,
341 ICE_SR_PBA_BLOCK_PTR);
343 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block TLV.\n");
347 /* pba_size is the next word */
348 status = ice_read_sr_word(hw, (pba_tlv + 2), &pba_size);
350 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Section size.\n");
354 if (pba_tlv_len < pba_size) {
355 ice_debug(hw, ICE_DBG_INIT, "Invalid PBA Block TLV size.\n");
356 return ICE_ERR_INVAL_SIZE;
359 /* Subtract one to get PBA word count (PBA Size word is included in
363 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
364 ice_debug(hw, ICE_DBG_INIT, "Buffer too small for PBA data.\n");
365 return ICE_ERR_PARAM;
368 for (i = 0; i < pba_size; i++) {
369 status = ice_read_sr_word(hw, (pba_tlv + 2 + 1) + i, &pba_word);
371 ice_debug(hw, ICE_DBG_INIT, "Failed to read PBA Block word %d.\n", i);
375 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
376 pba_num[(i * 2) + 1] = pba_word & 0xFF;
378 pba_num[(pba_size * 2)] = '\0';
384 * ice_get_orom_ver_info - Read Option ROM version information
385 * @hw: pointer to the HW struct
387 * Read the Combo Image version data from the Boot Configuration TLV and fill
388 * in the option ROM version data.
390 static enum ice_status ice_get_orom_ver_info(struct ice_hw *hw)
392 u16 combo_hi, combo_lo, boot_cfg_tlv, boot_cfg_tlv_len;
393 struct ice_orom_info *orom = &hw->nvm.orom;
394 enum ice_status status;
397 status = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len,
398 ICE_SR_BOOT_CFG_PTR);
400 ice_debug(hw, ICE_DBG_INIT,
401 "Failed to read Boot Configuration Block TLV.\n");
405 /* Boot Configuration Block must have length at least 2 words
406 * (Combo Image Version High and Combo Image Version Low)
408 if (boot_cfg_tlv_len < 2) {
409 ice_debug(hw, ICE_DBG_INIT,
410 "Invalid Boot Configuration Block TLV size.\n");
411 return ICE_ERR_INVAL_SIZE;
414 status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OROM_VER_OFF),
417 ice_debug(hw, ICE_DBG_INIT, "Failed to read OROM_VER hi.\n");
421 status = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OROM_VER_OFF + 1),
424 ice_debug(hw, ICE_DBG_INIT, "Failed to read OROM_VER lo.\n");
428 combo_ver = ((u32)combo_hi << 16) | combo_lo;
430 orom->major = (u8)((combo_ver & ICE_OROM_VER_MASK) >>
432 orom->patch = (u8)(combo_ver & ICE_OROM_VER_PATCH_MASK);
433 orom->build = (u16)((combo_ver & ICE_OROM_VER_BUILD_MASK) >>
434 ICE_OROM_VER_BUILD_SHIFT);
440 * ice_get_netlist_ver_info
441 * @hw: pointer to the HW struct
443 * Get the netlist version information
445 static enum ice_status ice_get_netlist_ver_info(struct ice_hw *hw)
447 struct ice_netlist_ver_info *ver = &hw->netlist_ver;
454 ret = ice_acquire_nvm(hw, ICE_RES_READ);
457 buff = kcalloc(ICE_AQC_NVM_NETLIST_ID_BLK_LEN, sizeof(*buff),
460 ret = ICE_ERR_NO_MEMORY;
464 /* read module length */
465 ret = ice_aq_read_nvm(hw, ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID,
466 ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN_OFFSET * 2,
467 ICE_AQC_NVM_LINK_TOPO_NETLIST_LEN, &raw_data,
472 data = le16_to_cpu(raw_data);
473 /* exit if length is = 0 */
477 /* read node count */
478 ret = ice_aq_read_nvm(hw, ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID,
479 ICE_AQC_NVM_NETLIST_NODE_COUNT_OFFSET * 2,
480 ICE_AQC_NVM_NETLIST_NODE_COUNT_LEN, &raw_data,
484 data = le16_to_cpu(raw_data) & ICE_AQC_NVM_NETLIST_NODE_COUNT_M;
486 /* netlist ID block starts from offset 4 + node count * 2 */
487 id_blk_start = ICE_AQC_NVM_NETLIST_ID_BLK_START_OFFSET + data * 2;
489 /* read the entire netlist ID block */
490 ret = ice_aq_read_nvm(hw, ICE_AQC_NVM_LINK_TOPO_NETLIST_MOD_ID,
492 ICE_AQC_NVM_NETLIST_ID_BLK_LEN * 2, buff, false,
497 for (i = 0; i < ICE_AQC_NVM_NETLIST_ID_BLK_LEN; i++)
498 buff[i] = le16_to_cpu(((__force __le16 *)buff)[i]);
500 ver->major = (buff[ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_HIGH] << 16) |
501 buff[ICE_AQC_NVM_NETLIST_ID_BLK_MAJOR_VER_LOW];
502 ver->minor = (buff[ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_HIGH] << 16) |
503 buff[ICE_AQC_NVM_NETLIST_ID_BLK_MINOR_VER_LOW];
504 ver->type = (buff[ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_HIGH] << 16) |
505 buff[ICE_AQC_NVM_NETLIST_ID_BLK_TYPE_LOW];
506 ver->rev = (buff[ICE_AQC_NVM_NETLIST_ID_BLK_REV_HIGH] << 16) |
507 buff[ICE_AQC_NVM_NETLIST_ID_BLK_REV_LOW];
508 ver->cust_ver = buff[ICE_AQC_NVM_NETLIST_ID_BLK_CUST_VER];
509 /* Read the left most 4 bytes of SHA */
510 ver->hash = buff[ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH + 15] << 16 |
511 buff[ICE_AQC_NVM_NETLIST_ID_BLK_SHA_HASH + 14];
521 * ice_discover_flash_size - Discover the available flash size.
522 * @hw: pointer to the HW struct
524 * The device flash could be up to 16MB in size. However, it is possible that
525 * the actual size is smaller. Use bisection to determine the accessible size
528 static enum ice_status ice_discover_flash_size(struct ice_hw *hw)
530 u32 min_size = 0, max_size = ICE_AQC_NVM_MAX_OFFSET + 1;
531 enum ice_status status;
533 status = ice_acquire_nvm(hw, ICE_RES_READ);
537 while ((max_size - min_size) > 1) {
538 u32 offset = (max_size + min_size) / 2;
542 status = ice_read_flat_nvm(hw, offset, &len, &data, false);
543 if (status == ICE_ERR_AQ_ERROR &&
544 hw->adminq.sq_last_status == ICE_AQ_RC_EINVAL) {
545 ice_debug(hw, ICE_DBG_NVM,
546 "%s: New upper bound of %u bytes\n",
550 } else if (!status) {
551 ice_debug(hw, ICE_DBG_NVM,
552 "%s: New lower bound of %u bytes\n",
556 /* an unexpected error occurred */
557 goto err_read_flat_nvm;
561 ice_debug(hw, ICE_DBG_NVM,
562 "Predicted flash size is %u bytes\n", max_size);
564 hw->nvm.flash_size = max_size;
573 * ice_init_nvm - initializes NVM setting
574 * @hw: pointer to the HW struct
576 * This function reads and populates NVM settings such as Shadow RAM size,
577 * max_timeout, and blank_nvm_mode
579 enum ice_status ice_init_nvm(struct ice_hw *hw)
581 struct ice_nvm_info *nvm = &hw->nvm;
582 u16 eetrack_lo, eetrack_hi, ver;
583 enum ice_status status;
587 /* The SR size is stored regardless of the NVM programming mode
588 * as the blank mode may be used in the factory line.
590 gens_stat = rd32(hw, GLNVM_GENS);
591 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
593 /* Switching to words (sr_size contains power of 2) */
594 nvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
596 /* Check if we are in the normal or blank NVM programming mode */
597 fla = rd32(hw, GLNVM_FLA);
598 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
599 nvm->blank_nvm_mode = false;
601 /* Blank programming mode */
602 nvm->blank_nvm_mode = true;
603 ice_debug(hw, ICE_DBG_NVM,
604 "NVM init error: unsupported blank mode.\n");
605 return ICE_ERR_NVM_BLANK_MODE;
608 status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &ver);
610 ice_debug(hw, ICE_DBG_INIT,
611 "Failed to read DEV starter version.\n");
614 nvm->major_ver = (ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
615 nvm->minor_ver = (ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
617 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
619 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK lo.\n");
622 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
624 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK hi.\n");
628 nvm->eetrack = (eetrack_hi << 16) | eetrack_lo;
630 status = ice_discover_flash_size(hw);
632 ice_debug(hw, ICE_DBG_NVM,
633 "NVM init error: failed to discover flash size.\n");
637 switch (hw->device_id) {
638 /* the following devices do not have boot_cfg_tlv yet */
639 case ICE_DEV_ID_E823C_BACKPLANE:
640 case ICE_DEV_ID_E823C_QSFP:
641 case ICE_DEV_ID_E823C_SFP:
642 case ICE_DEV_ID_E823C_10G_BASE_T:
643 case ICE_DEV_ID_E823C_SGMII:
644 case ICE_DEV_ID_E822C_BACKPLANE:
645 case ICE_DEV_ID_E822C_QSFP:
646 case ICE_DEV_ID_E822C_10G_BASE_T:
647 case ICE_DEV_ID_E822C_SGMII:
648 case ICE_DEV_ID_E822C_SFP:
649 case ICE_DEV_ID_E822L_BACKPLANE:
650 case ICE_DEV_ID_E822L_SFP:
651 case ICE_DEV_ID_E822L_10G_BASE_T:
652 case ICE_DEV_ID_E822L_SGMII:
653 case ICE_DEV_ID_E823L_BACKPLANE:
654 case ICE_DEV_ID_E823L_SFP:
655 case ICE_DEV_ID_E823L_10G_BASE_T:
656 case ICE_DEV_ID_E823L_1GBE:
657 case ICE_DEV_ID_E823L_QSFP:
663 status = ice_get_orom_ver_info(hw);
665 ice_debug(hw, ICE_DBG_INIT, "Failed to read Option ROM info.\n");
669 /* read the netlist version information */
670 status = ice_get_netlist_ver_info(hw);
672 ice_debug(hw, ICE_DBG_INIT, "Failed to read netlist info.\n");
678 * ice_nvm_validate_checksum
679 * @hw: pointer to the HW struct
681 * Verify NVM PFA checksum validity (0x0706)
683 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
685 struct ice_aqc_nvm_checksum *cmd;
686 struct ice_aq_desc desc;
687 enum ice_status status;
689 status = ice_acquire_nvm(hw, ICE_RES_READ);
693 cmd = &desc.params.nvm_checksum;
695 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
696 cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
698 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
702 if (le16_to_cpu(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
703 status = ICE_ERR_NVM_CHECKSUM;
709 * ice_nvm_write_activate
710 * @hw: pointer to the HW struct
711 * @cmd_flags: NVM activate admin command bits (banks to be validated)
713 * Update the control word with the required banks' validity bits
714 * and dumps the Shadow RAM to flash (0x0707)
716 enum ice_status ice_nvm_write_activate(struct ice_hw *hw, u8 cmd_flags)
718 struct ice_aqc_nvm *cmd;
719 struct ice_aq_desc desc;
721 cmd = &desc.params.nvm;
722 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_write_activate);
724 cmd->cmd_flags = cmd_flags;
726 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
730 * ice_aq_nvm_update_empr
731 * @hw: pointer to the HW struct
733 * Update empr (0x0709). This command allows SW to
734 * request an EMPR to activate new FW.
736 enum ice_status ice_aq_nvm_update_empr(struct ice_hw *hw)
738 struct ice_aq_desc desc;
740 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_update_empr);
742 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
745 /* ice_nvm_set_pkg_data
746 * @hw: pointer to the HW struct
747 * @del_pkg_data_flag: If is set then the current pkg_data store by FW
749 * If bit is set to 1, then buffer should be size 0.
750 * @data: pointer to buffer
751 * @length: length of the buffer
752 * @cd: pointer to command details structure or NULL
754 * Set package data (0x070A). This command is equivalent to the reception
755 * of a PLDM FW Update GetPackageData cmd. This command should be sent
756 * as part of the NVM update as the first cmd in the flow.
760 ice_nvm_set_pkg_data(struct ice_hw *hw, bool del_pkg_data_flag, u8 *data,
761 u16 length, struct ice_sq_cd *cd)
763 struct ice_aqc_nvm_pkg_data *cmd;
764 struct ice_aq_desc desc;
766 if (length != 0 && !data)
767 return ICE_ERR_PARAM;
769 cmd = &desc.params.pkg_data;
771 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_pkg_data);
772 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
774 if (del_pkg_data_flag)
775 cmd->cmd_flags |= ICE_AQC_NVM_PKG_DELETE;
777 return ice_aq_send_cmd(hw, &desc, data, length, cd);
780 /* ice_nvm_pass_component_tbl
781 * @hw: pointer to the HW struct
782 * @data: pointer to buffer
783 * @length: length of the buffer
784 * @transfer_flag: parameter for determining stage of the update
785 * @comp_response: a pointer to the response from the 0x070B AQC.
786 * @comp_response_code: a pointer to the response code from the 0x070B AQC.
787 * @cd: pointer to command details structure or NULL
789 * Pass component table (0x070B). This command is equivalent to the reception
790 * of a PLDM FW Update PassComponentTable cmd. This command should be sent once
791 * per component. It can be only sent after Set Package Data cmd and before
792 * actual update. FW will assume these commands are going to be sent until
793 * the TransferFlag is set to End or StartAndEnd.
797 ice_nvm_pass_component_tbl(struct ice_hw *hw, u8 *data, u16 length,
798 u8 transfer_flag, u8 *comp_response,
799 u8 *comp_response_code, struct ice_sq_cd *cd)
801 struct ice_aqc_nvm_pass_comp_tbl *cmd;
802 struct ice_aq_desc desc;
803 enum ice_status status;
805 if (!data || !comp_response || !comp_response_code)
806 return ICE_ERR_PARAM;
808 cmd = &desc.params.pass_comp_tbl;
810 ice_fill_dflt_direct_cmd_desc(&desc,
811 ice_aqc_opc_nvm_pass_component_tbl);
812 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
814 cmd->transfer_flag = transfer_flag;
815 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
818 *comp_response = cmd->component_response;
819 *comp_response_code = cmd->component_response_code;