1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
4 #ifndef _ICE_CONTROLQ_H_
5 #define _ICE_CONTROLQ_H_
7 #include "ice_adminq_cmd.h"
9 /* Maximum buffer lengths for all control queue types */
10 #define ICE_AQ_MAX_BUF_LEN 4096
11 #define ICE_MBXQ_MAX_BUF_LEN 4096
13 #define ICE_CTL_Q_DESC(R, i) \
14 (&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
16 #define ICE_CTL_Q_DESC_UNUSED(R) \
17 (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
18 (R)->next_to_clean - (R)->next_to_use - 1)
20 /* Defines that help manage the driver vs FW API checks.
21 * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
23 #define EXP_FW_API_VER_BRANCH 0x00
24 #define EXP_FW_API_VER_MAJOR 0x01
25 #define EXP_FW_API_VER_MINOR 0x05
27 /* Different control queue types: These are mainly for SW consumption. */
29 ICE_CTL_Q_UNKNOWN = 0,
34 /* Control Queue timeout settings - max delay 1s */
35 #define ICE_CTL_Q_SQ_CMD_TIMEOUT 10000 /* Count 10000 times */
36 #define ICE_CTL_Q_SQ_CMD_USEC 100 /* Check every 100usec */
37 #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT 10 /* Count 10 times */
38 #define ICE_CTL_Q_ADMIN_INIT_MSEC 100 /* Check every 100msec */
40 struct ice_ctl_q_ring {
41 void *dma_head; /* Virtual address to DMA head */
42 struct ice_dma_mem desc_buf; /* descriptor ring memory */
43 void *cmd_buf; /* command buffer memory */
46 struct ice_dma_mem *sq_bi;
47 struct ice_dma_mem *rq_bi;
50 u16 count; /* Number of descriptors */
52 /* used for interrupt processing */
56 /* used for queue tracking */
68 /* sq transaction details */
70 struct ice_aq_desc *wb_desc;
73 #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
75 /* rq event information */
76 struct ice_rq_event_info {
77 struct ice_aq_desc desc;
83 /* Control Queue information */
84 struct ice_ctl_q_info {
86 enum ice_aq_err rq_last_status; /* last status on receive queue */
87 struct ice_ctl_q_ring rq; /* receive queue */
88 struct ice_ctl_q_ring sq; /* send queue */
89 u32 sq_cmd_timeout; /* send queue cmd write back timeout */
90 u16 num_rq_entries; /* receive queue depth */
91 u16 num_sq_entries; /* send queue depth */
92 u16 rq_buf_size; /* receive queue buffer size */
93 u16 sq_buf_size; /* send queue buffer size */
94 enum ice_aq_err sq_last_status; /* last status on send queue */
95 struct mutex sq_lock; /* Send queue lock */
96 struct mutex rq_lock; /* Receive queue lock */
99 #endif /* _ICE_CONTROLQ_H_ */