1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Intel Corporation. */
4 #include "ice_common.h"
6 #include "ice_adminq_cmd.h"
8 #define ICE_PF_RESET_WAIT_COUNT 200
10 #define ICE_NIC_FLX_ENTRY(hw, mdid, idx) \
11 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(ICE_RXDID_FLEX_NIC), \
12 ((ICE_RX_OPC_MDID << \
13 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
14 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
15 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
16 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
18 #define ICE_NIC_FLX_FLG_ENTRY(hw, flg_0, flg_1, flg_2, flg_3, idx) \
19 wr32((hw), GLFLXP_RXDID_FLAGS(ICE_RXDID_FLEX_NIC, idx), \
20 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
21 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
22 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
23 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
24 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
26 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
30 * ice_set_mac_type - Sets MAC type
31 * @hw: pointer to the HW structure
33 * This function sets the MAC type of the adapter based on the
34 * vendor ID and device ID stored in the hw structure.
36 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
38 if (hw->vendor_id != PCI_VENDOR_ID_INTEL)
39 return ICE_ERR_DEVICE_NOT_SUPPORTED;
41 hw->mac_type = ICE_MAC_GENERIC;
46 * ice_clear_pf_cfg - Clear PF configuration
47 * @hw: pointer to the hardware structure
49 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
50 * configuration, flow director filters, etc.).
52 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
54 struct ice_aq_desc desc;
56 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
58 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
62 * ice_aq_manage_mac_read - manage MAC address read command
63 * @hw: pointer to the hw struct
64 * @buf: a virtual buffer to hold the manage MAC read response
65 * @buf_size: Size of the virtual buffer
66 * @cd: pointer to command details structure or NULL
68 * This function is used to return per PF station MAC address (0x0107).
69 * NOTE: Upon successful completion of this command, MAC address information
70 * is returned in user specified buffer. Please interpret user specified
71 * buffer as "manage_mac_read" response.
72 * Response such as various MAC addresses are stored in HW struct (port.mac)
73 * ice_aq_discover_caps is expected to be called before this function is called.
75 static enum ice_status
76 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
79 struct ice_aqc_manage_mac_read_resp *resp;
80 struct ice_aqc_manage_mac_read *cmd;
81 struct ice_aq_desc desc;
82 enum ice_status status;
86 cmd = &desc.params.mac_read;
88 if (buf_size < sizeof(*resp))
89 return ICE_ERR_BUF_TOO_SHORT;
91 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
93 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
97 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
98 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
100 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
101 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
105 /* A single port can report up to two (LAN and WoL) addresses */
106 for (i = 0; i < cmd->num_addr; i++)
107 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
108 ether_addr_copy(hw->port_info->mac.lan_addr,
110 ether_addr_copy(hw->port_info->mac.perm_addr,
119 * ice_aq_get_phy_caps - returns PHY capabilities
120 * @pi: port information structure
121 * @qual_mods: report qualified modules
122 * @report_mode: report mode capabilities
123 * @pcaps: structure for PHY capabilities to be filled
124 * @cd: pointer to command details structure or NULL
126 * Returns the various PHY capabilities supported on the Port (0x0600)
128 static enum ice_status
129 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
130 struct ice_aqc_get_phy_caps_data *pcaps,
131 struct ice_sq_cd *cd)
133 struct ice_aqc_get_phy_caps *cmd;
134 u16 pcaps_size = sizeof(*pcaps);
135 struct ice_aq_desc desc;
136 enum ice_status status;
138 cmd = &desc.params.get_phy;
140 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
141 return ICE_ERR_PARAM;
143 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
146 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM);
148 cmd->param0 |= cpu_to_le16(report_mode);
149 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
151 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP)
152 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low);
158 * ice_get_media_type - Gets media type
159 * @pi: port information structure
161 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
163 struct ice_link_status *hw_link_info;
166 return ICE_MEDIA_UNKNOWN;
168 hw_link_info = &pi->phy.link_info;
170 if (hw_link_info->phy_type_low) {
171 switch (hw_link_info->phy_type_low) {
172 case ICE_PHY_TYPE_LOW_1000BASE_SX:
173 case ICE_PHY_TYPE_LOW_1000BASE_LX:
174 case ICE_PHY_TYPE_LOW_10GBASE_SR:
175 case ICE_PHY_TYPE_LOW_10GBASE_LR:
176 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
177 case ICE_PHY_TYPE_LOW_25GBASE_SR:
178 case ICE_PHY_TYPE_LOW_25GBASE_LR:
179 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
180 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
181 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
182 return ICE_MEDIA_FIBER;
183 case ICE_PHY_TYPE_LOW_100BASE_TX:
184 case ICE_PHY_TYPE_LOW_1000BASE_T:
185 case ICE_PHY_TYPE_LOW_2500BASE_T:
186 case ICE_PHY_TYPE_LOW_5GBASE_T:
187 case ICE_PHY_TYPE_LOW_10GBASE_T:
188 case ICE_PHY_TYPE_LOW_25GBASE_T:
189 return ICE_MEDIA_BASET;
190 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
191 case ICE_PHY_TYPE_LOW_25GBASE_CR:
192 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
193 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
194 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
196 case ICE_PHY_TYPE_LOW_1000BASE_KX:
197 case ICE_PHY_TYPE_LOW_2500BASE_KX:
198 case ICE_PHY_TYPE_LOW_2500BASE_X:
199 case ICE_PHY_TYPE_LOW_5GBASE_KR:
200 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
201 case ICE_PHY_TYPE_LOW_25GBASE_KR:
202 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
203 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
204 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
205 return ICE_MEDIA_BACKPLANE;
209 return ICE_MEDIA_UNKNOWN;
213 * ice_aq_get_link_info
214 * @pi: port information structure
215 * @ena_lse: enable/disable LinkStatusEvent reporting
216 * @link: pointer to link status structure - optional
217 * @cd: pointer to command details structure or NULL
219 * Get Link Status (0x607). Returns the link status of the adapter.
222 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
223 struct ice_link_status *link, struct ice_sq_cd *cd)
225 struct ice_link_status *hw_link_info_old, *hw_link_info;
226 struct ice_aqc_get_link_status_data link_data = { 0 };
227 struct ice_aqc_get_link_status *resp;
228 enum ice_media_type *hw_media_type;
229 struct ice_fc_info *hw_fc_info;
230 bool tx_pause, rx_pause;
231 struct ice_aq_desc desc;
232 enum ice_status status;
236 return ICE_ERR_PARAM;
237 hw_link_info_old = &pi->phy.link_info_old;
238 hw_media_type = &pi->phy.media_type;
239 hw_link_info = &pi->phy.link_info;
240 hw_fc_info = &pi->fc;
242 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
243 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
244 resp = &desc.params.get_link_status;
245 resp->cmd_flags = cpu_to_le16(cmd_flags);
246 resp->lport_num = pi->lport;
248 status = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data),
254 /* save off old link status information */
255 *hw_link_info_old = *hw_link_info;
257 /* update current link status information */
258 hw_link_info->link_speed = le16_to_cpu(link_data.link_speed);
259 hw_link_info->phy_type_low = le64_to_cpu(link_data.phy_type_low);
260 *hw_media_type = ice_get_media_type(pi);
261 hw_link_info->link_info = link_data.link_info;
262 hw_link_info->an_info = link_data.an_info;
263 hw_link_info->ext_info = link_data.ext_info;
264 hw_link_info->max_frame_size = le16_to_cpu(link_data.max_frame_size);
265 hw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M;
268 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
269 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
270 if (tx_pause && rx_pause)
271 hw_fc_info->current_mode = ICE_FC_FULL;
273 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
275 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
277 hw_fc_info->current_mode = ICE_FC_NONE;
279 hw_link_info->lse_ena =
280 !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED));
282 /* save link status information */
284 *link = *hw_link_info;
286 /* flag cleared so calling functions don't call AQ again */
287 pi->phy.get_link_info = false;
293 * ice_init_flex_parser - initialize rx flex parser
294 * @hw: pointer to the hardware structure
296 * Function to initialize flex descriptors
298 static void ice_init_flex_parser(struct ice_hw *hw)
302 ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_HASH_LOW, 0);
303 ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_HASH_HIGH, 1);
304 ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_FLOW_ID_LOWER, 2);
305 ICE_NIC_FLX_ENTRY(hw, ICE_RX_MDID_FLOW_ID_HIGH, 3);
306 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_PKT_FRG, ICE_RXFLG_UDP_GRE,
307 ICE_RXFLG_PKT_DSI, ICE_RXFLG_FIN, idx++);
308 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_SYN, ICE_RXFLG_RST,
309 ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx++);
310 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI,
311 ICE_RXFLG_EVLAN_x8100, ICE_RXFLG_EVLAN_x9100,
313 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_VLAN_x8100, ICE_RXFLG_TNL_VLAN,
314 ICE_RXFLG_TNL_MAC, ICE_RXFLG_TNL0, idx++);
315 ICE_NIC_FLX_FLG_ENTRY(hw, ICE_RXFLG_TNL1, ICE_RXFLG_TNL2,
316 ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx);
320 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
321 * @hw: pointer to the hw struct
323 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
325 struct ice_switch_info *sw;
327 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw),
328 sizeof(*hw->switch_info), GFP_KERNEL);
329 sw = hw->switch_info;
332 return ICE_ERR_NO_MEMORY;
334 INIT_LIST_HEAD(&sw->vsi_list_map_head);
336 mutex_init(&sw->mac_list_lock);
337 INIT_LIST_HEAD(&sw->mac_list_head);
339 mutex_init(&sw->vlan_list_lock);
340 INIT_LIST_HEAD(&sw->vlan_list_head);
342 mutex_init(&sw->eth_m_list_lock);
343 INIT_LIST_HEAD(&sw->eth_m_list_head);
345 mutex_init(&sw->promisc_list_lock);
346 INIT_LIST_HEAD(&sw->promisc_list_head);
348 mutex_init(&sw->mac_vlan_list_lock);
349 INIT_LIST_HEAD(&sw->mac_vlan_list_head);
355 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
356 * @hw: pointer to the hw struct
358 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
360 struct ice_switch_info *sw = hw->switch_info;
361 struct ice_vsi_list_map_info *v_pos_map;
362 struct ice_vsi_list_map_info *v_tmp_map;
364 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
366 list_del(&v_pos_map->list_entry);
367 devm_kfree(ice_hw_to_dev(hw), v_pos_map);
370 mutex_destroy(&sw->mac_list_lock);
371 mutex_destroy(&sw->vlan_list_lock);
372 mutex_destroy(&sw->eth_m_list_lock);
373 mutex_destroy(&sw->promisc_list_lock);
374 mutex_destroy(&sw->mac_vlan_list_lock);
376 devm_kfree(ice_hw_to_dev(hw), sw);
380 * ice_init_hw - main hardware initialization routine
381 * @hw: pointer to the hardware structure
383 enum ice_status ice_init_hw(struct ice_hw *hw)
385 struct ice_aqc_get_phy_caps_data *pcaps;
386 enum ice_status status;
390 /* Set MAC type based on DeviceID */
391 status = ice_set_mac_type(hw);
395 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
396 PF_FUNC_RID_FUNC_NUM_M) >>
397 PF_FUNC_RID_FUNC_NUM_S;
399 status = ice_reset(hw, ICE_RESET_PFR);
403 /* set these values to minimum allowed */
404 hw->itr_gran_200 = ICE_ITR_GRAN_MIN_200;
405 hw->itr_gran_100 = ICE_ITR_GRAN_MIN_100;
406 hw->itr_gran_50 = ICE_ITR_GRAN_MIN_50;
407 hw->itr_gran_25 = ICE_ITR_GRAN_MIN_25;
409 status = ice_init_all_ctrlq(hw);
411 goto err_unroll_cqinit;
413 status = ice_clear_pf_cfg(hw);
415 goto err_unroll_cqinit;
417 ice_clear_pxe_mode(hw);
419 status = ice_init_nvm(hw);
421 goto err_unroll_cqinit;
423 status = ice_get_caps(hw);
425 goto err_unroll_cqinit;
427 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw),
428 sizeof(*hw->port_info), GFP_KERNEL);
429 if (!hw->port_info) {
430 status = ICE_ERR_NO_MEMORY;
431 goto err_unroll_cqinit;
434 /* set the back pointer to hw */
435 hw->port_info->hw = hw;
437 /* Initialize port_info struct with switch configuration data */
438 status = ice_get_initial_sw_cfg(hw);
440 goto err_unroll_alloc;
444 /* Query the allocated resources for tx scheduler */
445 status = ice_sched_query_res_alloc(hw);
447 ice_debug(hw, ICE_DBG_SCHED,
448 "Failed to get scheduler allocated resources\n");
449 goto err_unroll_alloc;
452 /* Initialize port_info struct with scheduler data */
453 status = ice_sched_init_port(hw->port_info);
455 goto err_unroll_sched;
457 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
459 status = ICE_ERR_NO_MEMORY;
460 goto err_unroll_sched;
463 /* Initialize port_info struct with PHY capabilities */
464 status = ice_aq_get_phy_caps(hw->port_info, false,
465 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
466 devm_kfree(ice_hw_to_dev(hw), pcaps);
468 goto err_unroll_sched;
470 /* Initialize port_info struct with link information */
471 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
473 goto err_unroll_sched;
475 status = ice_init_fltr_mgmt_struct(hw);
477 goto err_unroll_sched;
479 /* Get MAC information */
480 /* A single port can report up to two (LAN and WoL) addresses */
481 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2,
482 sizeof(struct ice_aqc_manage_mac_read_resp),
484 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
487 status = ICE_ERR_NO_MEMORY;
488 goto err_unroll_fltr_mgmt_struct;
491 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
492 devm_kfree(ice_hw_to_dev(hw), mac_buf);
495 goto err_unroll_fltr_mgmt_struct;
497 ice_init_flex_parser(hw);
501 err_unroll_fltr_mgmt_struct:
502 ice_cleanup_fltr_mgmt_struct(hw);
504 ice_sched_cleanup_all(hw);
506 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
508 ice_shutdown_all_ctrlq(hw);
513 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
514 * @hw: pointer to the hardware structure
516 void ice_deinit_hw(struct ice_hw *hw)
518 ice_sched_cleanup_all(hw);
519 ice_shutdown_all_ctrlq(hw);
522 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
523 hw->port_info = NULL;
526 ice_cleanup_fltr_mgmt_struct(hw);
530 * ice_check_reset - Check to see if a global reset is complete
531 * @hw: pointer to the hardware structure
533 enum ice_status ice_check_reset(struct ice_hw *hw)
535 u32 cnt, reg = 0, grst_delay;
537 /* Poll for Device Active state in case a recent CORER, GLOBR,
538 * or EMPR has occurred. The grst delay value is in 100ms units.
539 * Add 1sec for outstanding AQ commands that can take a long time.
541 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
542 GLGEN_RSTCTL_GRSTDEL_S) + 10;
544 for (cnt = 0; cnt < grst_delay; cnt++) {
546 reg = rd32(hw, GLGEN_RSTAT);
547 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
551 if (cnt == grst_delay) {
552 ice_debug(hw, ICE_DBG_INIT,
553 "Global reset polling failed to complete.\n");
554 return ICE_ERR_RESET_FAILED;
557 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
558 GLNVM_ULD_GLOBR_DONE_M)
560 /* Device is Active; check Global Reset processes are done */
561 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
562 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
563 if (reg == ICE_RESET_DONE_MASK) {
564 ice_debug(hw, ICE_DBG_INIT,
565 "Global reset processes done. %d\n", cnt);
571 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
572 ice_debug(hw, ICE_DBG_INIT,
573 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
575 return ICE_ERR_RESET_FAILED;
582 * ice_pf_reset - Reset the PF
583 * @hw: pointer to the hardware structure
585 * If a global reset has been triggered, this function checks
586 * for its completion and then issues the PF reset
588 static enum ice_status ice_pf_reset(struct ice_hw *hw)
592 /* If at function entry a global reset was already in progress, i.e.
593 * state is not 'device active' or any of the reset done bits are not
594 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
595 * global reset is done.
597 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
598 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
599 /* poll on global reset currently in progress until done */
600 if (ice_check_reset(hw))
601 return ICE_ERR_RESET_FAILED;
607 reg = rd32(hw, PFGEN_CTRL);
609 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
611 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
612 reg = rd32(hw, PFGEN_CTRL);
613 if (!(reg & PFGEN_CTRL_PFSWR_M))
619 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
620 ice_debug(hw, ICE_DBG_INIT,
621 "PF reset polling failed to complete.\n");
622 return ICE_ERR_RESET_FAILED;
629 * ice_reset - Perform different types of reset
630 * @hw: pointer to the hardware structure
631 * @req: reset request
633 * This function triggers a reset as specified by the req parameter.
636 * If anything other than a PF reset is triggered, PXE mode is restored.
637 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
638 * interface has been restored in the rebuild flow.
640 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
646 return ice_pf_reset(hw);
647 case ICE_RESET_CORER:
648 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
649 val = GLGEN_RTRIG_CORER_M;
651 case ICE_RESET_GLOBR:
652 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
653 val = GLGEN_RTRIG_GLOBR_M;
657 val |= rd32(hw, GLGEN_RTRIG);
658 wr32(hw, GLGEN_RTRIG, val);
661 /* wait for the FW to be ready */
662 return ice_check_reset(hw);
666 * ice_copy_rxq_ctx_to_hw
667 * @hw: pointer to the hardware structure
668 * @ice_rxq_ctx: pointer to the rxq context
669 * @rxq_index: the index of the rx queue
671 * Copies rxq context from dense structure to hw register space
673 static enum ice_status
674 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
679 return ICE_ERR_BAD_PTR;
681 if (rxq_index > QRX_CTRL_MAX_INDEX)
682 return ICE_ERR_PARAM;
684 /* Copy each dword separately to hw */
685 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
686 wr32(hw, QRX_CONTEXT(i, rxq_index),
687 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
689 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
690 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
696 /* LAN Rx Queue Context */
697 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
698 /* Field Width LSB */
699 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
700 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
701 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
702 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
703 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
704 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
705 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
706 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
707 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
708 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
709 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
710 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
711 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
712 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
713 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
714 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
715 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
716 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
717 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
723 * @hw: pointer to the hardware structure
724 * @rlan_ctx: pointer to the rxq context
725 * @rxq_index: the index of the rx queue
727 * Converts rxq context from sparse to dense structure and then writes
728 * it to hw register space
731 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
734 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
736 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
737 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
740 /* LAN Tx Queue Context */
741 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
742 /* Field Width LSB */
743 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
744 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
745 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
746 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
747 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
748 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
749 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
750 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
751 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
752 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
753 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
754 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
755 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
756 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
757 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
758 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
759 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
760 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
761 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
762 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
763 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
764 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
765 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
766 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
767 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
768 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
769 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 110, 171),
775 * @hw: pointer to the hardware structure
777 * @desc: pointer to control queue descriptor
778 * @buf: pointer to command buffer
779 * @buf_len: max length of buf
781 * Dumps debug log about control command with descriptor contents.
783 void ice_debug_cq(struct ice_hw *hw, u32 __maybe_unused mask, void *desc,
784 void *buf, u16 buf_len)
786 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;
789 #ifndef CONFIG_DYNAMIC_DEBUG
790 if (!(mask & hw->debug_mask))
797 len = le16_to_cpu(cq_desc->datalen);
800 "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
801 le16_to_cpu(cq_desc->opcode),
802 le16_to_cpu(cq_desc->flags),
803 le16_to_cpu(cq_desc->datalen), le16_to_cpu(cq_desc->retval));
804 ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
805 le32_to_cpu(cq_desc->cookie_high),
806 le32_to_cpu(cq_desc->cookie_low));
807 ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
808 le32_to_cpu(cq_desc->params.generic.param0),
809 le32_to_cpu(cq_desc->params.generic.param1));
810 ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
811 le32_to_cpu(cq_desc->params.generic.addr_high),
812 le32_to_cpu(cq_desc->params.generic.addr_low));
813 if (buf && cq_desc->datalen != 0) {
814 ice_debug(hw, mask, "Buffer:\n");
818 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len);
822 /* FW Admin Queue command wrappers */
825 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
826 * @hw: pointer to the hw struct
827 * @desc: descriptor describing the command
828 * @buf: buffer to use for indirect commands (NULL for direct commands)
829 * @buf_size: size of buffer for indirect commands (0 for direct commands)
830 * @cd: pointer to command details structure
832 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
835 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
836 u16 buf_size, struct ice_sq_cd *cd)
838 return ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
843 * @hw: pointer to the hw struct
844 * @cd: pointer to command details structure or NULL
846 * Get the firmware version (0x0001) from the admin queue commands
848 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
850 struct ice_aqc_get_ver *resp;
851 struct ice_aq_desc desc;
852 enum ice_status status;
854 resp = &desc.params.get_ver;
856 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
858 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
861 hw->fw_branch = resp->fw_branch;
862 hw->fw_maj_ver = resp->fw_major;
863 hw->fw_min_ver = resp->fw_minor;
864 hw->fw_patch = resp->fw_patch;
865 hw->fw_build = le32_to_cpu(resp->fw_build);
866 hw->api_branch = resp->api_branch;
867 hw->api_maj_ver = resp->api_major;
868 hw->api_min_ver = resp->api_minor;
869 hw->api_patch = resp->api_patch;
877 * @hw: pointer to the hw struct
878 * @unloading: is the driver unloading itself
880 * Tell the Firmware that we're shutting down the AdminQ and whether
881 * or not the driver is unloading as well (0x0003).
883 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
885 struct ice_aqc_q_shutdown *cmd;
886 struct ice_aq_desc desc;
888 cmd = &desc.params.q_shutdown;
890 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
893 cmd->driver_unloading = cpu_to_le32(ICE_AQC_DRIVER_UNLOADING);
895 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
900 * @hw: pointer to the hw struct
902 * @access: access type
903 * @sdp_number: resource number
904 * @timeout: the maximum time in ms that the driver may hold the resource
905 * @cd: pointer to command details structure or NULL
907 * Requests common resource using the admin queue commands (0x0008).
908 * When attempting to acquire the Global Config Lock, the driver can
909 * learn of three states:
910 * 1) ICE_SUCCESS - acquired lock, and can perform download package
911 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
912 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
913 * successfully downloaded the package; the driver does
914 * not have to download the package and can continue
917 * Note that if the caller is in an acquire lock, perform action, release lock
918 * phase of operation, it is possible that the FW may detect a timeout and issue
919 * a CORER. In this case, the driver will receive a CORER interrupt and will
920 * have to determine its cause. The calling thread that is handling this flow
921 * will likely get an error propagated back to it indicating the Download
922 * Package, Update Package or the Release Resource AQ commands timed out.
924 static enum ice_status
925 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
926 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
927 struct ice_sq_cd *cd)
929 struct ice_aqc_req_res *cmd_resp;
930 struct ice_aq_desc desc;
931 enum ice_status status;
933 cmd_resp = &desc.params.res_owner;
935 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
937 cmd_resp->res_id = cpu_to_le16(res);
938 cmd_resp->access_type = cpu_to_le16(access);
939 cmd_resp->res_number = cpu_to_le32(sdp_number);
940 cmd_resp->timeout = cpu_to_le32(*timeout);
943 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
945 /* The completion specifies the maximum time in ms that the driver
946 * may hold the resource in the Timeout field.
949 /* Global config lock response utilizes an additional status field.
951 * If the Global config lock resource is held by some other driver, the
952 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
953 * and the timeout field indicates the maximum time the current owner
954 * of the resource has to free it.
956 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
957 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
958 *timeout = le32_to_cpu(cmd_resp->timeout);
960 } else if (le16_to_cpu(cmd_resp->status) ==
961 ICE_AQ_RES_GLBL_IN_PROG) {
962 *timeout = le32_to_cpu(cmd_resp->timeout);
963 return ICE_ERR_AQ_ERROR;
964 } else if (le16_to_cpu(cmd_resp->status) ==
965 ICE_AQ_RES_GLBL_DONE) {
966 return ICE_ERR_AQ_NO_WORK;
969 /* invalid FW response, force a timeout immediately */
971 return ICE_ERR_AQ_ERROR;
974 /* If the resource is held by some other driver, the command completes
975 * with a busy return value and the timeout field indicates the maximum
976 * time the current owner of the resource has to free it.
978 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
979 *timeout = le32_to_cpu(cmd_resp->timeout);
986 * @hw: pointer to the hw struct
988 * @sdp_number: resource number
989 * @cd: pointer to command details structure or NULL
991 * release common resource using the admin queue commands (0x0009)
993 static enum ice_status
994 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
995 struct ice_sq_cd *cd)
997 struct ice_aqc_req_res *cmd;
998 struct ice_aq_desc desc;
1000 cmd = &desc.params.res_owner;
1002 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1004 cmd->res_id = cpu_to_le16(res);
1005 cmd->res_number = cpu_to_le32(sdp_number);
1007 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1012 * @hw: pointer to the HW structure
1014 * @access: access type (read or write)
1015 * @timeout: timeout in milliseconds
1017 * This function will attempt to acquire the ownership of a resource.
1020 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1021 enum ice_aq_res_access_type access, u32 timeout)
1023 #define ICE_RES_POLLING_DELAY_MS 10
1024 u32 delay = ICE_RES_POLLING_DELAY_MS;
1025 u32 time_left = timeout;
1026 enum ice_status status;
1028 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1030 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1031 * previously acquired the resource and performed any necessary updates;
1032 * in this case the caller does not obtain the resource and has no
1033 * further work to do.
1035 if (status == ICE_ERR_AQ_NO_WORK)
1036 goto ice_acquire_res_exit;
1039 ice_debug(hw, ICE_DBG_RES,
1040 "resource %d acquire type %d failed.\n", res, access);
1042 /* If necessary, poll until the current lock owner timeouts */
1043 timeout = time_left;
1044 while (status && timeout && time_left) {
1046 timeout = (timeout > delay) ? timeout - delay : 0;
1047 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1049 if (status == ICE_ERR_AQ_NO_WORK)
1050 /* lock free, but no work to do */
1057 if (status && status != ICE_ERR_AQ_NO_WORK)
1058 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1060 ice_acquire_res_exit:
1061 if (status == ICE_ERR_AQ_NO_WORK) {
1062 if (access == ICE_RES_WRITE)
1063 ice_debug(hw, ICE_DBG_RES,
1064 "resource indicates no work to do.\n");
1066 ice_debug(hw, ICE_DBG_RES,
1067 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1074 * @hw: pointer to the HW structure
1077 * This function will release a resource using the proper Admin Command.
1079 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1081 enum ice_status status;
1082 u32 total_delay = 0;
1084 status = ice_aq_release_res(hw, res, 0, NULL);
1086 /* there are some rare cases when trying to release the resource
1087 * results in an admin Q timeout, so handle them correctly
1089 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1090 (total_delay < hw->adminq.sq_cmd_timeout)) {
1092 status = ice_aq_release_res(hw, res, 0, NULL);
1098 * ice_parse_caps - parse function/device capabilities
1099 * @hw: pointer to the hw struct
1100 * @buf: pointer to a buffer containing function/device capability records
1101 * @cap_count: number of capability records in the list
1102 * @opc: type of capabilities list to parse
1104 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1107 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1108 enum ice_adminq_opc opc)
1110 struct ice_aqc_list_caps_elem *cap_resp;
1111 struct ice_hw_func_caps *func_p = NULL;
1112 struct ice_hw_dev_caps *dev_p = NULL;
1113 struct ice_hw_common_caps *caps;
1119 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1121 if (opc == ice_aqc_opc_list_dev_caps) {
1122 dev_p = &hw->dev_caps;
1123 caps = &dev_p->common_cap;
1124 } else if (opc == ice_aqc_opc_list_func_caps) {
1125 func_p = &hw->func_caps;
1126 caps = &func_p->common_cap;
1128 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1132 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1133 u32 logical_id = le32_to_cpu(cap_resp->logical_id);
1134 u32 phys_id = le32_to_cpu(cap_resp->phys_id);
1135 u32 number = le32_to_cpu(cap_resp->number);
1136 u16 cap = le16_to_cpu(cap_resp->cap);
1139 case ICE_AQC_CAPS_VSI:
1141 dev_p->num_vsi_allocd_to_host = number;
1142 ice_debug(hw, ICE_DBG_INIT,
1143 "HW caps: Dev.VSI cnt = %d\n",
1144 dev_p->num_vsi_allocd_to_host);
1145 } else if (func_p) {
1146 func_p->guaranteed_num_vsi = number;
1147 ice_debug(hw, ICE_DBG_INIT,
1148 "HW caps: Func.VSI cnt = %d\n",
1149 func_p->guaranteed_num_vsi);
1152 case ICE_AQC_CAPS_RSS:
1153 caps->rss_table_size = number;
1154 caps->rss_table_entry_width = logical_id;
1155 ice_debug(hw, ICE_DBG_INIT,
1156 "HW caps: RSS table size = %d\n",
1157 caps->rss_table_size);
1158 ice_debug(hw, ICE_DBG_INIT,
1159 "HW caps: RSS table width = %d\n",
1160 caps->rss_table_entry_width);
1162 case ICE_AQC_CAPS_RXQS:
1163 caps->num_rxq = number;
1164 caps->rxq_first_id = phys_id;
1165 ice_debug(hw, ICE_DBG_INIT,
1166 "HW caps: Num Rx Qs = %d\n", caps->num_rxq);
1167 ice_debug(hw, ICE_DBG_INIT,
1168 "HW caps: Rx first queue ID = %d\n",
1169 caps->rxq_first_id);
1171 case ICE_AQC_CAPS_TXQS:
1172 caps->num_txq = number;
1173 caps->txq_first_id = phys_id;
1174 ice_debug(hw, ICE_DBG_INIT,
1175 "HW caps: Num Tx Qs = %d\n", caps->num_txq);
1176 ice_debug(hw, ICE_DBG_INIT,
1177 "HW caps: Tx first queue ID = %d\n",
1178 caps->txq_first_id);
1180 case ICE_AQC_CAPS_MSIX:
1181 caps->num_msix_vectors = number;
1182 caps->msix_vector_first_id = phys_id;
1183 ice_debug(hw, ICE_DBG_INIT,
1184 "HW caps: MSIX vector count = %d\n",
1185 caps->num_msix_vectors);
1186 ice_debug(hw, ICE_DBG_INIT,
1187 "HW caps: MSIX first vector index = %d\n",
1188 caps->msix_vector_first_id);
1190 case ICE_AQC_CAPS_MAX_MTU:
1191 caps->max_mtu = number;
1193 ice_debug(hw, ICE_DBG_INIT,
1194 "HW caps: Dev.MaxMTU = %d\n",
1197 ice_debug(hw, ICE_DBG_INIT,
1198 "HW caps: func.MaxMTU = %d\n",
1202 ice_debug(hw, ICE_DBG_INIT,
1203 "HW caps: Unknown capability[%d]: 0x%x\n", i,
1211 * ice_aq_discover_caps - query function/device capabilities
1212 * @hw: pointer to the hw struct
1213 * @buf: a virtual buffer to hold the capabilities
1214 * @buf_size: Size of the virtual buffer
1215 * @data_size: Size of the returned data, or buf size needed if AQ err==ENOMEM
1216 * @opc: capabilities type to discover - pass in the command opcode
1217 * @cd: pointer to command details structure or NULL
1219 * Get the function(0x000a)/device(0x000b) capabilities description from
1222 static enum ice_status
1223 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u16 *data_size,
1224 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1226 struct ice_aqc_list_caps *cmd;
1227 struct ice_aq_desc desc;
1228 enum ice_status status;
1230 cmd = &desc.params.get_cap;
1232 if (opc != ice_aqc_opc_list_func_caps &&
1233 opc != ice_aqc_opc_list_dev_caps)
1234 return ICE_ERR_PARAM;
1236 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1238 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1240 ice_parse_caps(hw, buf, le32_to_cpu(cmd->count), opc);
1241 *data_size = le16_to_cpu(desc.datalen);
1247 * ice_get_caps - get info about the HW
1248 * @hw: pointer to the hardware structure
1250 enum ice_status ice_get_caps(struct ice_hw *hw)
1252 enum ice_status status;
1257 /* The driver doesn't know how many capabilities the device will return
1258 * so the buffer size required isn't known ahead of time. The driver
1259 * starts with cbuf_len and if this turns out to be insufficient, the
1260 * device returns ICE_AQ_RC_ENOMEM and also the buffer size it needs.
1261 * The driver then allocates the buffer of this size and retries the
1262 * operation. So it follows that the retry count is 2.
1264 #define ICE_GET_CAP_BUF_COUNT 40
1265 #define ICE_GET_CAP_RETRY_COUNT 2
1267 cbuf_len = ICE_GET_CAP_BUF_COUNT *
1268 sizeof(struct ice_aqc_list_caps_elem);
1270 retries = ICE_GET_CAP_RETRY_COUNT;
1275 cbuf = devm_kzalloc(ice_hw_to_dev(hw), cbuf_len, GFP_KERNEL);
1277 return ICE_ERR_NO_MEMORY;
1279 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &data_size,
1280 ice_aqc_opc_list_func_caps, NULL);
1281 devm_kfree(ice_hw_to_dev(hw), cbuf);
1283 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
1286 /* If ENOMEM is returned, try again with bigger buffer */
1287 cbuf_len = data_size;
1288 } while (--retries);
1294 * ice_aq_manage_mac_write - manage MAC address write command
1295 * @hw: pointer to the hw struct
1296 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
1297 * @flags: flags to control write behavior
1298 * @cd: pointer to command details structure or NULL
1300 * This function is used to write MAC address to the NVM (0x0108).
1303 ice_aq_manage_mac_write(struct ice_hw *hw, u8 *mac_addr, u8 flags,
1304 struct ice_sq_cd *cd)
1306 struct ice_aqc_manage_mac_write *cmd;
1307 struct ice_aq_desc desc;
1309 cmd = &desc.params.mac_write;
1310 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
1314 /* Prep values for flags, sah, sal */
1315 cmd->sah = htons(*((u16 *)mac_addr));
1316 cmd->sal = htonl(*((u32 *)(mac_addr + 2)));
1318 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1322 * ice_aq_clear_pxe_mode
1323 * @hw: pointer to the hw struct
1325 * Tell the firmware that the driver is taking over from PXE (0x0110).
1327 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
1329 struct ice_aq_desc desc;
1331 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
1332 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
1334 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1338 * ice_clear_pxe_mode - clear pxe operations mode
1339 * @hw: pointer to the hw struct
1341 * Make sure all PXE mode settings are cleared, including things
1342 * like descriptor fetch/write-back mode.
1344 void ice_clear_pxe_mode(struct ice_hw *hw)
1346 if (ice_check_sq_alive(hw, &hw->adminq))
1347 ice_aq_clear_pxe_mode(hw);
1351 * ice_aq_set_phy_cfg
1352 * @hw: pointer to the hw struct
1353 * @lport: logical port number
1354 * @cfg: structure with PHY configuration data to be set
1355 * @cd: pointer to command details structure or NULL
1357 * Set the various PHY configuration parameters supported on the Port.
1358 * One or more of the Set PHY config parameters may be ignored in an MFP
1359 * mode as the PF may not have the privilege to set some of the PHY Config
1360 * parameters. This status will be indicated by the command response (0x0601).
1362 static enum ice_status
1363 ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,
1364 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
1366 struct ice_aqc_set_phy_cfg *cmd;
1367 struct ice_aq_desc desc;
1370 return ICE_ERR_PARAM;
1372 cmd = &desc.params.set_phy;
1373 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
1374 cmd->lport_num = lport;
1376 return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
1380 * ice_update_link_info - update status of the HW network link
1381 * @pi: port info structure of the interested logical port
1383 static enum ice_status
1384 ice_update_link_info(struct ice_port_info *pi)
1386 struct ice_aqc_get_phy_caps_data *pcaps;
1387 struct ice_phy_info *phy_info;
1388 enum ice_status status;
1392 return ICE_ERR_PARAM;
1396 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
1398 return ICE_ERR_NO_MEMORY;
1400 phy_info = &pi->phy;
1401 status = ice_aq_get_link_info(pi, true, NULL, NULL);
1405 if (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {
1406 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG,
1411 memcpy(phy_info->link_info.module_type, &pcaps->module_type,
1412 sizeof(phy_info->link_info.module_type));
1415 devm_kfree(ice_hw_to_dev(hw), pcaps);
1421 * @pi: port information structure
1422 * @aq_failures: pointer to status code, specific to ice_set_fc routine
1423 * @atomic_restart: enable automatic link update
1425 * Set the requested flow control mode.
1428 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool atomic_restart)
1430 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
1431 struct ice_aqc_get_phy_caps_data *pcaps;
1432 enum ice_status status;
1433 u8 pause_mask = 0x0;
1437 return ICE_ERR_PARAM;
1439 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
1441 switch (pi->fc.req_mode) {
1443 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
1444 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
1446 case ICE_FC_RX_PAUSE:
1447 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
1449 case ICE_FC_TX_PAUSE:
1450 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
1456 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
1458 return ICE_ERR_NO_MEMORY;
1460 /* Get the current phy config */
1461 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
1464 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
1468 /* clear the old pause settings */
1469 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
1470 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
1471 /* set the new capabilities */
1472 cfg.caps |= pause_mask;
1473 /* If the capabilities have changed, then set the new config */
1474 if (cfg.caps != pcaps->caps) {
1475 int retry_count, retry_max = 10;
1477 /* Auto restart link so settings take effect */
1479 cfg.caps |= ICE_AQ_PHY_ENA_ATOMIC_LINK;
1480 /* Copy over all the old settings */
1481 cfg.phy_type_low = pcaps->phy_type_low;
1482 cfg.low_power_ctrl = pcaps->low_power_ctrl;
1483 cfg.eee_cap = pcaps->eee_cap;
1484 cfg.eeer_value = pcaps->eeer_value;
1485 cfg.link_fec_opt = pcaps->link_fec_options;
1487 status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);
1489 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
1493 /* Update the link info
1494 * It sometimes takes a really long time for link to
1495 * come back from the atomic reset. Thus, we wait a
1498 for (retry_count = 0; retry_count < retry_max; retry_count++) {
1499 status = ice_update_link_info(pi);
1508 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
1512 devm_kfree(ice_hw_to_dev(hw), pcaps);
1517 * ice_get_link_status - get status of the HW network link
1518 * @pi: port information structure
1519 * @link_up: pointer to bool (true/false = linkup/linkdown)
1521 * Variable link_up is true if link is up, false if link is down.
1522 * The variable link_up is invalid if status is non zero. As a
1523 * result of this call, link status reporting becomes enabled
1525 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
1527 struct ice_phy_info *phy_info;
1528 enum ice_status status = 0;
1530 if (!pi || !link_up)
1531 return ICE_ERR_PARAM;
1533 phy_info = &pi->phy;
1535 if (phy_info->get_link_info) {
1536 status = ice_update_link_info(pi);
1539 ice_debug(pi->hw, ICE_DBG_LINK,
1540 "get link status error, status = %d\n",
1544 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
1550 * ice_aq_set_link_restart_an
1551 * @pi: pointer to the port information structure
1552 * @ena_link: if true: enable link, if false: disable link
1553 * @cd: pointer to command details structure or NULL
1555 * Sets up the link and restarts the Auto-Negotiation over the link.
1558 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
1559 struct ice_sq_cd *cd)
1561 struct ice_aqc_restart_an *cmd;
1562 struct ice_aq_desc desc;
1564 cmd = &desc.params.restart_an;
1566 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
1568 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
1569 cmd->lport_num = pi->lport;
1571 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
1573 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
1575 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
1579 * ice_aq_set_event_mask
1580 * @hw: pointer to the hw struct
1581 * @port_num: port number of the physical function
1582 * @mask: event mask to be set
1583 * @cd: pointer to command details structure or NULL
1585 * Set event mask (0x0613)
1588 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
1589 struct ice_sq_cd *cd)
1591 struct ice_aqc_set_event_mask *cmd;
1592 struct ice_aq_desc desc;
1594 cmd = &desc.params.set_event_mask;
1596 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
1598 cmd->lport_num = port_num;
1600 cmd->event_mask = cpu_to_le16(mask);
1602 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1606 * __ice_aq_get_set_rss_lut
1607 * @hw: pointer to the hardware structure
1608 * @vsi_id: VSI FW index
1609 * @lut_type: LUT table type
1610 * @lut: pointer to the LUT buffer provided by the caller
1611 * @lut_size: size of the LUT buffer
1612 * @glob_lut_idx: global LUT index
1613 * @set: set true to set the table, false to get the table
1615 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
1617 static enum ice_status
1618 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
1619 u16 lut_size, u8 glob_lut_idx, bool set)
1621 struct ice_aqc_get_set_rss_lut *cmd_resp;
1622 struct ice_aq_desc desc;
1623 enum ice_status status;
1626 cmd_resp = &desc.params.get_set_rss_lut;
1629 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
1630 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1632 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
1635 cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
1636 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
1637 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
1638 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
1641 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
1642 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
1643 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
1644 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
1645 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
1648 status = ICE_ERR_PARAM;
1649 goto ice_aq_get_set_rss_lut_exit;
1652 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
1653 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
1654 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
1657 goto ice_aq_get_set_rss_lut_send;
1658 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
1660 goto ice_aq_get_set_rss_lut_send;
1662 goto ice_aq_get_set_rss_lut_send;
1665 /* LUT size is only valid for Global and PF table types */
1667 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
1669 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
1670 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
1671 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
1672 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
1674 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
1675 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
1676 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
1677 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
1678 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
1683 status = ICE_ERR_PARAM;
1684 goto ice_aq_get_set_rss_lut_exit;
1687 ice_aq_get_set_rss_lut_send:
1688 cmd_resp->flags = cpu_to_le16(flags);
1689 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
1691 ice_aq_get_set_rss_lut_exit:
1696 * ice_aq_get_rss_lut
1697 * @hw: pointer to the hardware structure
1698 * @vsi_id: VSI FW index
1699 * @lut_type: LUT table type
1700 * @lut: pointer to the LUT buffer provided by the caller
1701 * @lut_size: size of the LUT buffer
1703 * get the RSS lookup table, PF or VSI type
1706 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
1709 return __ice_aq_get_set_rss_lut(hw, vsi_id, lut_type, lut, lut_size, 0,
1714 * ice_aq_set_rss_lut
1715 * @hw: pointer to the hardware structure
1716 * @vsi_id: VSI FW index
1717 * @lut_type: LUT table type
1718 * @lut: pointer to the LUT buffer provided by the caller
1719 * @lut_size: size of the LUT buffer
1721 * set the RSS lookup table, PF or VSI type
1724 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
1727 return __ice_aq_get_set_rss_lut(hw, vsi_id, lut_type, lut, lut_size, 0,
1732 * __ice_aq_get_set_rss_key
1733 * @hw: pointer to the hw struct
1734 * @vsi_id: VSI FW index
1735 * @key: pointer to key info struct
1736 * @set: set true to set the key, false to get the key
1738 * get (0x0B04) or set (0x0B02) the RSS key per VSI
1741 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
1742 struct ice_aqc_get_set_rss_keys *key,
1745 struct ice_aqc_get_set_rss_key *cmd_resp;
1746 u16 key_size = sizeof(*key);
1747 struct ice_aq_desc desc;
1749 cmd_resp = &desc.params.get_set_rss_key;
1752 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
1753 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1755 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
1758 cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
1759 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
1760 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
1761 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
1763 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
1767 * ice_aq_get_rss_key
1768 * @hw: pointer to the hw struct
1769 * @vsi_id: VSI FW index
1770 * @key: pointer to key info struct
1772 * get the RSS key per VSI
1775 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_id,
1776 struct ice_aqc_get_set_rss_keys *key)
1778 return __ice_aq_get_set_rss_key(hw, vsi_id, key, false);
1782 * ice_aq_set_rss_key
1783 * @hw: pointer to the hw struct
1784 * @vsi_id: VSI FW index
1785 * @keys: pointer to key info struct
1787 * set the RSS key per VSI
1790 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_id,
1791 struct ice_aqc_get_set_rss_keys *keys)
1793 return __ice_aq_get_set_rss_key(hw, vsi_id, keys, true);
1797 * ice_aq_add_lan_txq
1798 * @hw: pointer to the hardware structure
1799 * @num_qgrps: Number of added queue groups
1800 * @qg_list: list of queue groups to be added
1801 * @buf_size: size of buffer for indirect command
1802 * @cd: pointer to command details structure or NULL
1804 * Add Tx LAN queue (0x0C30)
1807 * Prior to calling add Tx LAN queue:
1808 * Initialize the following as part of the Tx queue context:
1809 * Completion queue ID if the queue uses Completion queue, Quanta profile,
1810 * Cache profile and Packet shaper profile.
1812 * After add Tx LAN queue AQ command is completed:
1813 * Interrupts should be associated with specific queues,
1814 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
1817 static enum ice_status
1818 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
1819 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
1820 struct ice_sq_cd *cd)
1822 u16 i, sum_header_size, sum_q_size = 0;
1823 struct ice_aqc_add_tx_qgrp *list;
1824 struct ice_aqc_add_txqs *cmd;
1825 struct ice_aq_desc desc;
1827 cmd = &desc.params.add_txqs;
1829 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
1832 return ICE_ERR_PARAM;
1834 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
1835 return ICE_ERR_PARAM;
1837 sum_header_size = num_qgrps *
1838 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
1841 for (i = 0; i < num_qgrps; i++) {
1842 struct ice_aqc_add_txqs_perq *q = list->txqs;
1844 sum_q_size += list->num_txqs * sizeof(*q);
1845 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
1848 if (buf_size != (sum_header_size + sum_q_size))
1849 return ICE_ERR_PARAM;
1851 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1853 cmd->num_qgrps = num_qgrps;
1855 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
1859 * ice_aq_dis_lan_txq
1860 * @hw: pointer to the hardware structure
1861 * @num_qgrps: number of groups in the list
1862 * @qg_list: the list of groups to disable
1863 * @buf_size: the total size of the qg_list buffer in bytes
1864 * @cd: pointer to command details structure or NULL
1866 * Disable LAN Tx queue (0x0C31)
1868 static enum ice_status
1869 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
1870 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
1871 struct ice_sq_cd *cd)
1873 struct ice_aqc_dis_txqs *cmd;
1874 struct ice_aq_desc desc;
1877 cmd = &desc.params.dis_txqs;
1878 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
1881 return ICE_ERR_PARAM;
1883 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
1884 return ICE_ERR_PARAM;
1885 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1886 cmd->num_entries = num_qgrps;
1888 for (i = 0; i < num_qgrps; ++i) {
1889 /* Calculate the size taken up by the queue IDs in this group */
1890 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
1892 /* Add the size of the group header */
1893 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
1895 /* If the num of queues is even, add 2 bytes of padding */
1896 if ((qg_list[i].num_qs % 2) == 0)
1901 return ICE_ERR_PARAM;
1903 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
1906 /* End of FW Admin Queue command wrappers */
1909 * ice_write_byte - write a byte to a packed context structure
1910 * @src_ctx: the context structure to read from
1911 * @dest_ctx: the context to be written to
1912 * @ce_info: a description of the struct to be filled
1914 static void ice_write_byte(u8 *src_ctx, u8 *dest_ctx,
1915 const struct ice_ctx_ele *ce_info)
1917 u8 src_byte, dest_byte, mask;
1921 /* copy from the next struct field */
1922 from = src_ctx + ce_info->offset;
1924 /* prepare the bits and mask */
1925 shift_width = ce_info->lsb % 8;
1926 mask = (u8)(BIT(ce_info->width) - 1);
1931 /* shift to correct alignment */
1932 mask <<= shift_width;
1933 src_byte <<= shift_width;
1935 /* get the current bits from the target bit string */
1936 dest = dest_ctx + (ce_info->lsb / 8);
1938 memcpy(&dest_byte, dest, sizeof(dest_byte));
1940 dest_byte &= ~mask; /* get the bits not changing */
1941 dest_byte |= src_byte; /* add in the new bits */
1943 /* put it all back */
1944 memcpy(dest, &dest_byte, sizeof(dest_byte));
1948 * ice_write_word - write a word to a packed context structure
1949 * @src_ctx: the context structure to read from
1950 * @dest_ctx: the context to be written to
1951 * @ce_info: a description of the struct to be filled
1953 static void ice_write_word(u8 *src_ctx, u8 *dest_ctx,
1954 const struct ice_ctx_ele *ce_info)
1961 /* copy from the next struct field */
1962 from = src_ctx + ce_info->offset;
1964 /* prepare the bits and mask */
1965 shift_width = ce_info->lsb % 8;
1966 mask = BIT(ce_info->width) - 1;
1968 /* don't swizzle the bits until after the mask because the mask bits
1969 * will be in a different bit position on big endian machines
1971 src_word = *(u16 *)from;
1974 /* shift to correct alignment */
1975 mask <<= shift_width;
1976 src_word <<= shift_width;
1978 /* get the current bits from the target bit string */
1979 dest = dest_ctx + (ce_info->lsb / 8);
1981 memcpy(&dest_word, dest, sizeof(dest_word));
1983 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */
1984 dest_word |= cpu_to_le16(src_word); /* add in the new bits */
1986 /* put it all back */
1987 memcpy(dest, &dest_word, sizeof(dest_word));
1991 * ice_write_dword - write a dword to a packed context structure
1992 * @src_ctx: the context structure to read from
1993 * @dest_ctx: the context to be written to
1994 * @ce_info: a description of the struct to be filled
1996 static void ice_write_dword(u8 *src_ctx, u8 *dest_ctx,
1997 const struct ice_ctx_ele *ce_info)
1999 u32 src_dword, mask;
2004 /* copy from the next struct field */
2005 from = src_ctx + ce_info->offset;
2007 /* prepare the bits and mask */
2008 shift_width = ce_info->lsb % 8;
2010 /* if the field width is exactly 32 on an x86 machine, then the shift
2011 * operation will not work because the SHL instructions count is masked
2012 * to 5 bits so the shift will do nothing
2014 if (ce_info->width < 32)
2015 mask = BIT(ce_info->width) - 1;
2019 /* don't swizzle the bits until after the mask because the mask bits
2020 * will be in a different bit position on big endian machines
2022 src_dword = *(u32 *)from;
2025 /* shift to correct alignment */
2026 mask <<= shift_width;
2027 src_dword <<= shift_width;
2029 /* get the current bits from the target bit string */
2030 dest = dest_ctx + (ce_info->lsb / 8);
2032 memcpy(&dest_dword, dest, sizeof(dest_dword));
2034 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */
2035 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */
2037 /* put it all back */
2038 memcpy(dest, &dest_dword, sizeof(dest_dword));
2042 * ice_write_qword - write a qword to a packed context structure
2043 * @src_ctx: the context structure to read from
2044 * @dest_ctx: the context to be written to
2045 * @ce_info: a description of the struct to be filled
2047 static void ice_write_qword(u8 *src_ctx, u8 *dest_ctx,
2048 const struct ice_ctx_ele *ce_info)
2050 u64 src_qword, mask;
2055 /* copy from the next struct field */
2056 from = src_ctx + ce_info->offset;
2058 /* prepare the bits and mask */
2059 shift_width = ce_info->lsb % 8;
2061 /* if the field width is exactly 64 on an x86 machine, then the shift
2062 * operation will not work because the SHL instructions count is masked
2063 * to 6 bits so the shift will do nothing
2065 if (ce_info->width < 64)
2066 mask = BIT_ULL(ce_info->width) - 1;
2070 /* don't swizzle the bits until after the mask because the mask bits
2071 * will be in a different bit position on big endian machines
2073 src_qword = *(u64 *)from;
2076 /* shift to correct alignment */
2077 mask <<= shift_width;
2078 src_qword <<= shift_width;
2080 /* get the current bits from the target bit string */
2081 dest = dest_ctx + (ce_info->lsb / 8);
2083 memcpy(&dest_qword, dest, sizeof(dest_qword));
2085 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */
2086 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */
2088 /* put it all back */
2089 memcpy(dest, &dest_qword, sizeof(dest_qword));
2093 * ice_set_ctx - set context bits in packed structure
2094 * @src_ctx: pointer to a generic non-packed context structure
2095 * @dest_ctx: pointer to memory for the packed structure
2096 * @ce_info: a description of the structure to be transformed
2099 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
2103 for (f = 0; ce_info[f].width; f++) {
2104 /* We have to deal with each element of the FW response
2105 * using the correct size so that we are correct regardless
2106 * of the endianness of the machine.
2108 switch (ce_info[f].size_of) {
2110 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
2113 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
2116 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
2119 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
2122 return ICE_ERR_INVAL_SIZE;
2131 * @pi: port information structure
2134 * @num_qgrps: Number of added queue groups
2135 * @buf: list of queue groups to be added
2136 * @buf_size: size of buffer for indirect command
2137 * @cd: pointer to command details structure or NULL
2139 * This function adds one lan q
2142 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_id, u8 tc, u8 num_qgrps,
2143 struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
2144 struct ice_sq_cd *cd)
2146 struct ice_aqc_txsched_elem_data node = { 0 };
2147 struct ice_sched_node *parent;
2148 enum ice_status status;
2151 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
2154 if (num_qgrps > 1 || buf->num_txqs > 1)
2155 return ICE_ERR_MAX_LIMIT;
2159 mutex_lock(&pi->sched_lock);
2161 /* find a parent node */
2162 parent = ice_sched_get_free_qparent(pi, vsi_id, tc,
2163 ICE_SCHED_NODE_OWNER_LAN);
2165 status = ICE_ERR_PARAM;
2168 buf->parent_teid = parent->info.node_teid;
2169 node.parent_teid = parent->info.node_teid;
2170 /* Mark that the values in the "generic" section as valid. The default
2171 * value in the "generic" section is zero. This means that :
2172 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
2173 * - 0 priority among siblings, indicated by Bit 1-3.
2174 * - WFQ, indicated by Bit 4.
2175 * - 0 Adjustment value is used in PSM credit update flow, indicated by
2177 * - Bit 7 is reserved.
2178 * Without setting the generic section as valid in valid_sections, the
2179 * Admin Q command will fail with error code ICE_AQ_RC_EINVAL.
2181 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
2184 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
2188 node.node_teid = buf->txqs[0].q_teid;
2189 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
2191 /* add a leaf node into schduler tree q layer */
2192 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
2195 mutex_unlock(&pi->sched_lock);
2201 * @pi: port information structure
2202 * @num_queues: number of queues
2203 * @q_ids: pointer to the q_id array
2204 * @q_teids: pointer to queue node teids
2205 * @cd: pointer to command details structure or NULL
2207 * This function removes queues and their corresponding nodes in SW DB
2210 ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids,
2211 u32 *q_teids, struct ice_sq_cd *cd)
2213 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
2214 struct ice_aqc_dis_txq_item qg_list;
2217 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
2220 mutex_lock(&pi->sched_lock);
2222 for (i = 0; i < num_queues; i++) {
2223 struct ice_sched_node *node;
2225 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
2228 qg_list.parent_teid = node->info.parent_teid;
2230 qg_list.q_id[0] = cpu_to_le16(q_ids[i]);
2231 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
2232 sizeof(qg_list), cd);
2236 ice_free_sched_node(pi, node);
2238 mutex_unlock(&pi->sched_lock);
2243 * ice_cfg_vsi_qs - configure the new/exisiting VSI queues
2244 * @pi: port information structure
2246 * @tc_bitmap: TC bitmap
2247 * @maxqs: max queues array per TC
2248 * @owner: lan or rdma
2250 * This function adds/updates the VSI queues per TC.
2252 static enum ice_status
2253 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_id, u8 tc_bitmap,
2254 u16 *maxqs, u8 owner)
2256 enum ice_status status = 0;
2259 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
2262 mutex_lock(&pi->sched_lock);
2264 for (i = 0; i < ICE_MAX_TRAFFIC_CLASS; i++) {
2265 /* configuration is possible only if TC node is present */
2266 if (!ice_sched_get_tc_node(pi, i))
2269 status = ice_sched_cfg_vsi(pi, vsi_id, i, maxqs[i], owner,
2270 ice_is_tc_ena(tc_bitmap, i));
2275 mutex_unlock(&pi->sched_lock);
2280 * ice_cfg_vsi_lan - configure VSI lan queues
2281 * @pi: port information structure
2283 * @tc_bitmap: TC bitmap
2284 * @max_lanqs: max lan queues array per TC
2286 * This function adds/updates the VSI lan queues per TC.
2289 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_id, u8 tc_bitmap,
2292 return ice_cfg_vsi_qs(pi, vsi_id, tc_bitmap, max_lanqs,
2293 ICE_SCHED_NODE_OWNER_LAN);