1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Intel Corporation. */
4 #include "ice_common.h"
6 #include "ice_adminq_cmd.h"
9 #define ICE_PF_RESET_WAIT_COUNT 300
12 * ice_set_mac_type - Sets MAC type
13 * @hw: pointer to the HW structure
15 * This function sets the MAC type of the adapter based on the
16 * vendor ID and device ID stored in the HW structure.
18 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
20 if (hw->vendor_id != PCI_VENDOR_ID_INTEL)
21 return ICE_ERR_DEVICE_NOT_SUPPORTED;
23 switch (hw->device_id) {
24 case ICE_DEV_ID_E810C_BACKPLANE:
25 case ICE_DEV_ID_E810C_QSFP:
26 case ICE_DEV_ID_E810C_SFP:
27 case ICE_DEV_ID_E810_XXV_BACKPLANE:
28 case ICE_DEV_ID_E810_XXV_QSFP:
29 case ICE_DEV_ID_E810_XXV_SFP:
30 hw->mac_type = ICE_MAC_E810;
32 case ICE_DEV_ID_E823C_10G_BASE_T:
33 case ICE_DEV_ID_E823C_BACKPLANE:
34 case ICE_DEV_ID_E823C_QSFP:
35 case ICE_DEV_ID_E823C_SFP:
36 case ICE_DEV_ID_E823C_SGMII:
37 case ICE_DEV_ID_E822C_10G_BASE_T:
38 case ICE_DEV_ID_E822C_BACKPLANE:
39 case ICE_DEV_ID_E822C_QSFP:
40 case ICE_DEV_ID_E822C_SFP:
41 case ICE_DEV_ID_E822C_SGMII:
42 case ICE_DEV_ID_E822L_10G_BASE_T:
43 case ICE_DEV_ID_E822L_BACKPLANE:
44 case ICE_DEV_ID_E822L_SFP:
45 case ICE_DEV_ID_E822L_SGMII:
46 case ICE_DEV_ID_E823L_10G_BASE_T:
47 case ICE_DEV_ID_E823L_1GBE:
48 case ICE_DEV_ID_E823L_BACKPLANE:
49 case ICE_DEV_ID_E823L_QSFP:
50 case ICE_DEV_ID_E823L_SFP:
51 hw->mac_type = ICE_MAC_GENERIC;
54 hw->mac_type = ICE_MAC_UNKNOWN;
58 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type);
63 * ice_clear_pf_cfg - Clear PF configuration
64 * @hw: pointer to the hardware structure
66 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
67 * configuration, flow director filters, etc.).
69 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
71 struct ice_aq_desc desc;
73 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
75 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
79 * ice_aq_manage_mac_read - manage MAC address read command
80 * @hw: pointer to the HW struct
81 * @buf: a virtual buffer to hold the manage MAC read response
82 * @buf_size: Size of the virtual buffer
83 * @cd: pointer to command details structure or NULL
85 * This function is used to return per PF station MAC address (0x0107).
86 * NOTE: Upon successful completion of this command, MAC address information
87 * is returned in user specified buffer. Please interpret user specified
88 * buffer as "manage_mac_read" response.
89 * Response such as various MAC addresses are stored in HW struct (port.mac)
90 * ice_discover_dev_caps is expected to be called before this function is
93 static enum ice_status
94 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
97 struct ice_aqc_manage_mac_read_resp *resp;
98 struct ice_aqc_manage_mac_read *cmd;
99 struct ice_aq_desc desc;
100 enum ice_status status;
104 cmd = &desc.params.mac_read;
106 if (buf_size < sizeof(*resp))
107 return ICE_ERR_BUF_TOO_SHORT;
109 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
111 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
115 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
116 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
118 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
119 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
123 /* A single port can report up to two (LAN and WoL) addresses */
124 for (i = 0; i < cmd->num_addr; i++)
125 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
126 ether_addr_copy(hw->port_info->mac.lan_addr,
128 ether_addr_copy(hw->port_info->mac.perm_addr,
137 * ice_aq_get_phy_caps - returns PHY capabilities
138 * @pi: port information structure
139 * @qual_mods: report qualified modules
140 * @report_mode: report mode capabilities
141 * @pcaps: structure for PHY capabilities to be filled
142 * @cd: pointer to command details structure or NULL
144 * Returns the various PHY capabilities supported on the Port (0x0600)
147 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
148 struct ice_aqc_get_phy_caps_data *pcaps,
149 struct ice_sq_cd *cd)
151 struct ice_aqc_get_phy_caps *cmd;
152 u16 pcaps_size = sizeof(*pcaps);
153 struct ice_aq_desc desc;
154 enum ice_status status;
157 cmd = &desc.params.get_phy;
159 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
160 return ICE_ERR_PARAM;
163 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
166 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM);
168 cmd->param0 |= cpu_to_le16(report_mode);
169 status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
171 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n",
173 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
174 (unsigned long long)le64_to_cpu(pcaps->phy_type_low));
175 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
176 (unsigned long long)le64_to_cpu(pcaps->phy_type_high));
177 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps);
178 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
179 pcaps->low_power_ctrl_an);
180 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap);
181 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n",
183 ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n",
184 pcaps->link_fec_options);
185 ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n",
186 pcaps->module_compliance_enforcement);
187 ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n",
188 pcaps->extended_compliance_code);
189 ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n",
190 pcaps->module_type[0]);
191 ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n",
192 pcaps->module_type[1]);
193 ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n",
194 pcaps->module_type[2]);
196 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {
197 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low);
198 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high);
199 memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
200 sizeof(pi->phy.link_info.module_type));
207 * ice_aq_get_link_topo_handle - get link topology node return status
208 * @pi: port information structure
209 * @node_type: requested node type
210 * @cd: pointer to command details structure or NULL
212 * Get link topology node return status for specified node type (0x06E0)
214 * Node type cage can be used to determine if cage is present. If AQC
215 * returns error (ENOENT), then no cage present. If no cage present, then
216 * connection type is backplane or BASE-T.
218 static enum ice_status
219 ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
220 struct ice_sq_cd *cd)
222 struct ice_aqc_get_link_topo *cmd;
223 struct ice_aq_desc desc;
225 cmd = &desc.params.get_link_topo;
227 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
229 cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
230 ICE_AQC_LINK_TOPO_NODE_CTX_S);
233 cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
235 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
239 * ice_is_media_cage_present
240 * @pi: port information structure
242 * Returns true if media cage is present, else false. If no cage, then
243 * media type is backplane or BASE-T.
245 static bool ice_is_media_cage_present(struct ice_port_info *pi)
247 /* Node type cage can be used to determine if cage is present. If AQC
248 * returns error (ENOENT), then no cage present. If no cage present then
249 * connection type is backplane or BASE-T.
251 return !ice_aq_get_link_topo_handle(pi,
252 ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE,
257 * ice_get_media_type - Gets media type
258 * @pi: port information structure
260 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
262 struct ice_link_status *hw_link_info;
265 return ICE_MEDIA_UNKNOWN;
267 hw_link_info = &pi->phy.link_info;
268 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
269 /* If more than one media type is selected, report unknown */
270 return ICE_MEDIA_UNKNOWN;
272 if (hw_link_info->phy_type_low) {
273 /* 1G SGMII is a special case where some DA cable PHYs
274 * may show this as an option when it really shouldn't
275 * be since SGMII is meant to be between a MAC and a PHY
276 * in a backplane. Try to detect this case and handle it
278 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII &&
279 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
280 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||
281 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] ==
282 ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))
285 switch (hw_link_info->phy_type_low) {
286 case ICE_PHY_TYPE_LOW_1000BASE_SX:
287 case ICE_PHY_TYPE_LOW_1000BASE_LX:
288 case ICE_PHY_TYPE_LOW_10GBASE_SR:
289 case ICE_PHY_TYPE_LOW_10GBASE_LR:
290 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
291 case ICE_PHY_TYPE_LOW_25GBASE_SR:
292 case ICE_PHY_TYPE_LOW_25GBASE_LR:
293 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
294 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
295 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
296 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
297 case ICE_PHY_TYPE_LOW_50GBASE_SR:
298 case ICE_PHY_TYPE_LOW_50GBASE_FR:
299 case ICE_PHY_TYPE_LOW_50GBASE_LR:
300 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
301 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
302 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
303 case ICE_PHY_TYPE_LOW_100GBASE_DR:
304 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
305 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
306 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
307 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
308 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
309 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
310 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
311 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
312 return ICE_MEDIA_FIBER;
313 case ICE_PHY_TYPE_LOW_100BASE_TX:
314 case ICE_PHY_TYPE_LOW_1000BASE_T:
315 case ICE_PHY_TYPE_LOW_2500BASE_T:
316 case ICE_PHY_TYPE_LOW_5GBASE_T:
317 case ICE_PHY_TYPE_LOW_10GBASE_T:
318 case ICE_PHY_TYPE_LOW_25GBASE_T:
319 return ICE_MEDIA_BASET;
320 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
321 case ICE_PHY_TYPE_LOW_25GBASE_CR:
322 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
323 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
324 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
325 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
326 case ICE_PHY_TYPE_LOW_50GBASE_CP:
327 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
328 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
329 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
331 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
332 case ICE_PHY_TYPE_LOW_40G_XLAUI:
333 case ICE_PHY_TYPE_LOW_50G_LAUI2:
334 case ICE_PHY_TYPE_LOW_50G_AUI2:
335 case ICE_PHY_TYPE_LOW_50G_AUI1:
336 case ICE_PHY_TYPE_LOW_100G_AUI4:
337 case ICE_PHY_TYPE_LOW_100G_CAUI4:
338 if (ice_is_media_cage_present(pi))
341 case ICE_PHY_TYPE_LOW_1000BASE_KX:
342 case ICE_PHY_TYPE_LOW_2500BASE_KX:
343 case ICE_PHY_TYPE_LOW_2500BASE_X:
344 case ICE_PHY_TYPE_LOW_5GBASE_KR:
345 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
346 case ICE_PHY_TYPE_LOW_25GBASE_KR:
347 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
348 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
349 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
350 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
351 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
352 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
353 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
354 return ICE_MEDIA_BACKPLANE;
357 switch (hw_link_info->phy_type_high) {
358 case ICE_PHY_TYPE_HIGH_100G_AUI2:
359 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
360 if (ice_is_media_cage_present(pi))
363 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
364 return ICE_MEDIA_BACKPLANE;
365 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
366 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
367 return ICE_MEDIA_FIBER;
370 return ICE_MEDIA_UNKNOWN;
374 * ice_aq_get_link_info
375 * @pi: port information structure
376 * @ena_lse: enable/disable LinkStatusEvent reporting
377 * @link: pointer to link status structure - optional
378 * @cd: pointer to command details structure or NULL
380 * Get Link Status (0x607). Returns the link status of the adapter.
383 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
384 struct ice_link_status *link, struct ice_sq_cd *cd)
386 struct ice_aqc_get_link_status_data link_data = { 0 };
387 struct ice_aqc_get_link_status *resp;
388 struct ice_link_status *li_old, *li;
389 enum ice_media_type *hw_media_type;
390 struct ice_fc_info *hw_fc_info;
391 bool tx_pause, rx_pause;
392 struct ice_aq_desc desc;
393 enum ice_status status;
398 return ICE_ERR_PARAM;
400 li_old = &pi->phy.link_info_old;
401 hw_media_type = &pi->phy.media_type;
402 li = &pi->phy.link_info;
403 hw_fc_info = &pi->fc;
405 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
406 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
407 resp = &desc.params.get_link_status;
408 resp->cmd_flags = cpu_to_le16(cmd_flags);
409 resp->lport_num = pi->lport;
411 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
416 /* save off old link status information */
419 /* update current link status information */
420 li->link_speed = le16_to_cpu(link_data.link_speed);
421 li->phy_type_low = le64_to_cpu(link_data.phy_type_low);
422 li->phy_type_high = le64_to_cpu(link_data.phy_type_high);
423 *hw_media_type = ice_get_media_type(pi);
424 li->link_info = link_data.link_info;
425 li->an_info = link_data.an_info;
426 li->ext_info = link_data.ext_info;
427 li->max_frame_size = le16_to_cpu(link_data.max_frame_size);
428 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
429 li->topo_media_conflict = link_data.topo_media_conflict;
430 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
431 ICE_AQ_CFG_PACING_TYPE_M);
434 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
435 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
436 if (tx_pause && rx_pause)
437 hw_fc_info->current_mode = ICE_FC_FULL;
439 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
441 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
443 hw_fc_info->current_mode = ICE_FC_NONE;
445 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED));
447 ice_debug(hw, ICE_DBG_LINK, "get link info\n");
448 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed);
449 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
450 (unsigned long long)li->phy_type_low);
451 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
452 (unsigned long long)li->phy_type_high);
453 ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type);
454 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info);
455 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info);
456 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info);
457 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info);
458 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena);
459 ice_debug(hw, ICE_DBG_LINK, " max_frame = 0x%x\n",
461 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing);
463 /* save link status information */
467 /* flag cleared so calling functions don't call AQ again */
468 pi->phy.get_link_info = false;
474 * ice_fill_tx_timer_and_fc_thresh
475 * @hw: pointer to the HW struct
476 * @cmd: pointer to MAC cfg structure
478 * Add Tx timer and FC refresh threshold info to Set MAC Config AQ command
482 ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw,
483 struct ice_aqc_set_mac_cfg *cmd)
485 u16 fc_thres_val, tx_timer_val;
488 /* We read back the transmit timer and FC threshold value of
489 * LFC. Thus, we will use index =
490 * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.
492 * Also, because we are operating on transmit timer and FC
493 * threshold of LFC, we don't turn on any bit in tx_tmr_priority
495 #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX
497 /* Retrieve the transmit timer */
498 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
500 PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;
501 cmd->tx_tmr_value = cpu_to_le16(tx_timer_val);
503 /* Retrieve the FC threshold */
504 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
505 fc_thres_val = val & PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M;
507 cmd->fc_refresh_threshold = cpu_to_le16(fc_thres_val);
512 * @hw: pointer to the HW struct
513 * @max_frame_size: Maximum Frame Size to be supported
514 * @cd: pointer to command details structure or NULL
516 * Set MAC configuration (0x0603)
519 ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)
521 struct ice_aqc_set_mac_cfg *cmd;
522 struct ice_aq_desc desc;
524 cmd = &desc.params.set_mac_cfg;
526 if (max_frame_size == 0)
527 return ICE_ERR_PARAM;
529 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);
531 cmd->max_frame_size = cpu_to_le16(max_frame_size);
533 ice_fill_tx_timer_and_fc_thresh(hw, cmd);
535 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
539 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
540 * @hw: pointer to the HW struct
542 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
544 struct ice_switch_info *sw;
545 enum ice_status status;
547 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw),
548 sizeof(*hw->switch_info), GFP_KERNEL);
549 sw = hw->switch_info;
552 return ICE_ERR_NO_MEMORY;
554 INIT_LIST_HEAD(&sw->vsi_list_map_head);
556 status = ice_init_def_sw_recp(hw);
558 devm_kfree(ice_hw_to_dev(hw), hw->switch_info);
565 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
566 * @hw: pointer to the HW struct
568 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
570 struct ice_switch_info *sw = hw->switch_info;
571 struct ice_vsi_list_map_info *v_pos_map;
572 struct ice_vsi_list_map_info *v_tmp_map;
573 struct ice_sw_recipe *recps;
576 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
578 list_del(&v_pos_map->list_entry);
579 devm_kfree(ice_hw_to_dev(hw), v_pos_map);
581 recps = hw->switch_info->recp_list;
582 for (i = 0; i < ICE_SW_LKUP_LAST; i++) {
583 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
585 recps[i].root_rid = i;
586 mutex_destroy(&recps[i].filt_rule_lock);
587 list_for_each_entry_safe(lst_itr, tmp_entry,
588 &recps[i].filt_rules, list_entry) {
589 list_del(&lst_itr->list_entry);
590 devm_kfree(ice_hw_to_dev(hw), lst_itr);
593 ice_rm_all_sw_replay_rule_info(hw);
594 devm_kfree(ice_hw_to_dev(hw), sw->recp_list);
595 devm_kfree(ice_hw_to_dev(hw), sw);
599 * ice_get_fw_log_cfg - get FW logging configuration
600 * @hw: pointer to the HW struct
602 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw)
604 struct ice_aq_desc desc;
605 enum ice_status status;
609 size = sizeof(*config) * ICE_AQC_FW_LOG_ID_MAX;
610 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL);
612 return ICE_ERR_NO_MEMORY;
614 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info);
616 status = ice_aq_send_cmd(hw, &desc, config, size, NULL);
620 /* Save FW logging information into the HW structure */
621 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
624 v = le16_to_cpu(config[i]);
625 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
626 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S;
628 if (m < ICE_AQC_FW_LOG_ID_MAX)
629 hw->fw_log.evnts[m].cur = flgs;
633 devm_kfree(ice_hw_to_dev(hw), config);
639 * ice_cfg_fw_log - configure FW logging
640 * @hw: pointer to the HW struct
641 * @enable: enable certain FW logging events if true, disable all if false
643 * This function enables/disables the FW logging via Rx CQ events and a UART
644 * port based on predetermined configurations. FW logging via the Rx CQ can be
645 * enabled/disabled for individual PF's. However, FW logging via the UART can
646 * only be enabled/disabled for all PFs on the same device.
648 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
649 * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
650 * before initializing the device.
652 * When re/configuring FW logging, callers need to update the "cfg" elements of
653 * the hw->fw_log.evnts array with the desired logging event configurations for
654 * modules of interest. When disabling FW logging completely, the callers can
655 * just pass false in the "enable" parameter. On completion, the function will
656 * update the "cur" element of the hw->fw_log.evnts array with the resulting
657 * logging event configurations of the modules that are being re/configured. FW
658 * logging modules that are not part of a reconfiguration operation retain their
661 * Before resetting the device, it is recommended that the driver disables FW
662 * logging before shutting down the control queue. When disabling FW logging
663 * ("enable" = false), the latest configurations of FW logging events stored in
664 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
667 * When enabling FW logging to emit log messages via the Rx CQ during the
668 * device's initialization phase, a mechanism alternative to interrupt handlers
669 * needs to be used to extract FW log messages from the Rx CQ periodically and
670 * to prevent the Rx CQ from being full and stalling other types of control
671 * messages from FW to SW. Interrupts are typically disabled during the device's
672 * initialization phase.
674 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
676 struct ice_aqc_fw_logging *cmd;
677 enum ice_status status = 0;
678 u16 i, chgs = 0, len = 0;
679 struct ice_aq_desc desc;
684 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
687 /* Disable FW logging only when the control queue is still responsive */
689 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
692 /* Get current FW log settings */
693 status = ice_get_fw_log_cfg(hw);
697 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
698 cmd = &desc.params.fw_logging;
700 /* Indicate which controls are valid */
701 if (hw->fw_log.cq_en)
702 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
704 if (hw->fw_log.uart_en)
705 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
708 /* Fill in an array of entries with FW logging modules and
709 * logging events being reconfigured.
711 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
714 /* Keep track of enabled event types */
715 actv_evnts |= hw->fw_log.evnts[i].cfg;
717 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
721 data = devm_kcalloc(ice_hw_to_dev(hw),
722 ICE_AQC_FW_LOG_ID_MAX,
726 return ICE_ERR_NO_MEMORY;
729 val = i << ICE_AQC_FW_LOG_ID_S;
730 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
731 data[chgs++] = cpu_to_le16(val);
734 /* Only enable FW logging if at least one module is specified.
735 * If FW logging is currently enabled but all modules are not
736 * enabled to emit log messages, disable FW logging altogether.
739 /* Leave if there is effectively no change */
743 if (hw->fw_log.cq_en)
744 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
746 if (hw->fw_log.uart_en)
747 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
750 len = sizeof(*data) * chgs;
751 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
755 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
757 /* Update the current configuration to reflect events enabled.
758 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
759 * logging mode is enabled for the device. They do not reflect
760 * actual modules being enabled to emit log messages. So, their
761 * values remain unchanged even when all modules are disabled.
763 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
765 hw->fw_log.actv_evnts = actv_evnts;
766 for (i = 0; i < cnt; i++) {
770 /* When disabling all FW logging events as part
771 * of device's de-initialization, the original
772 * configurations are retained, and can be used
773 * to reconfigure FW logging later if the device
776 hw->fw_log.evnts[i].cur = 0;
780 v = le16_to_cpu(data[i]);
781 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
782 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
788 devm_kfree(ice_hw_to_dev(hw), data);
795 * @hw: pointer to the HW struct
796 * @desc: pointer to the AQ message descriptor
797 * @buf: pointer to the buffer accompanying the AQ message
799 * Formats a FW Log message and outputs it via the standard driver logs.
801 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
803 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n");
804 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,
805 le16_to_cpu(desc->datalen));
806 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n");
810 * ice_get_itr_intrl_gran
811 * @hw: pointer to the HW struct
813 * Determines the ITR/INTRL granularities based on the maximum aggregate
814 * bandwidth according to the device's configuration during power-on.
816 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
818 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
819 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
820 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
822 switch (max_agg_bw) {
823 case ICE_MAX_AGG_BW_200G:
824 case ICE_MAX_AGG_BW_100G:
825 case ICE_MAX_AGG_BW_50G:
826 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
827 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
829 case ICE_MAX_AGG_BW_25G:
830 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
831 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
837 * ice_init_hw - main hardware initialization routine
838 * @hw: pointer to the hardware structure
840 enum ice_status ice_init_hw(struct ice_hw *hw)
842 struct ice_aqc_get_phy_caps_data *pcaps;
843 enum ice_status status;
847 /* Set MAC type based on DeviceID */
848 status = ice_set_mac_type(hw);
852 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
853 PF_FUNC_RID_FUNC_NUM_M) >>
854 PF_FUNC_RID_FUNC_NUM_S;
856 status = ice_reset(hw, ICE_RESET_PFR);
860 ice_get_itr_intrl_gran(hw);
862 status = ice_create_all_ctrlq(hw);
864 goto err_unroll_cqinit;
866 /* Enable FW logging. Not fatal if this fails. */
867 status = ice_cfg_fw_log(hw, true);
869 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
871 status = ice_clear_pf_cfg(hw);
873 goto err_unroll_cqinit;
875 /* Set bit to enable Flow Director filters */
876 wr32(hw, PFQF_FD_ENA, PFQF_FD_ENA_FD_ENA_M);
877 INIT_LIST_HEAD(&hw->fdir_list_head);
879 ice_clear_pxe_mode(hw);
881 status = ice_init_nvm(hw);
883 goto err_unroll_cqinit;
885 status = ice_get_caps(hw);
887 goto err_unroll_cqinit;
889 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw),
890 sizeof(*hw->port_info), GFP_KERNEL);
891 if (!hw->port_info) {
892 status = ICE_ERR_NO_MEMORY;
893 goto err_unroll_cqinit;
896 /* set the back pointer to HW */
897 hw->port_info->hw = hw;
899 /* Initialize port_info struct with switch configuration data */
900 status = ice_get_initial_sw_cfg(hw);
902 goto err_unroll_alloc;
906 /* Query the allocated resources for Tx scheduler */
907 status = ice_sched_query_res_alloc(hw);
909 ice_debug(hw, ICE_DBG_SCHED,
910 "Failed to get scheduler allocated resources\n");
911 goto err_unroll_alloc;
914 /* Initialize port_info struct with scheduler data */
915 status = ice_sched_init_port(hw->port_info);
917 goto err_unroll_sched;
919 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
921 status = ICE_ERR_NO_MEMORY;
922 goto err_unroll_sched;
925 /* Initialize port_info struct with PHY capabilities */
926 status = ice_aq_get_phy_caps(hw->port_info, false,
927 ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps,
929 devm_kfree(ice_hw_to_dev(hw), pcaps);
931 goto err_unroll_sched;
933 /* Initialize port_info struct with link information */
934 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
936 goto err_unroll_sched;
938 /* need a valid SW entry point to build a Tx tree */
939 if (!hw->sw_entry_point_layer) {
940 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
941 status = ICE_ERR_CFG;
942 goto err_unroll_sched;
944 INIT_LIST_HEAD(&hw->agg_list);
945 /* Initialize max burst size */
946 if (!hw->max_burst_size)
947 ice_cfg_rl_burst_size(hw, ICE_SCHED_DFLT_BURST_SIZE);
949 status = ice_init_fltr_mgmt_struct(hw);
951 goto err_unroll_sched;
953 /* Get MAC information */
954 /* A single port can report up to two (LAN and WoL) addresses */
955 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2,
956 sizeof(struct ice_aqc_manage_mac_read_resp),
958 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
961 status = ICE_ERR_NO_MEMORY;
962 goto err_unroll_fltr_mgmt_struct;
965 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
966 devm_kfree(ice_hw_to_dev(hw), mac_buf);
969 goto err_unroll_fltr_mgmt_struct;
970 /* enable jumbo frame support at MAC level */
971 status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL);
973 goto err_unroll_fltr_mgmt_struct;
974 /* Obtain counter base index which would be used by flow director */
975 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base);
977 goto err_unroll_fltr_mgmt_struct;
978 status = ice_init_hw_tbls(hw);
980 goto err_unroll_fltr_mgmt_struct;
981 mutex_init(&hw->tnl_lock);
984 err_unroll_fltr_mgmt_struct:
985 ice_cleanup_fltr_mgmt_struct(hw);
987 ice_sched_cleanup_all(hw);
989 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
991 ice_destroy_all_ctrlq(hw);
996 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
997 * @hw: pointer to the hardware structure
999 * This should be called only during nominal operation, not as a result of
1000 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
1001 * applicable initializations if it fails for any reason.
1003 void ice_deinit_hw(struct ice_hw *hw)
1005 ice_free_fd_res_cntr(hw, hw->fd_ctr_base);
1006 ice_cleanup_fltr_mgmt_struct(hw);
1008 ice_sched_cleanup_all(hw);
1009 ice_sched_clear_agg(hw);
1011 ice_free_hw_tbls(hw);
1012 mutex_destroy(&hw->tnl_lock);
1014 if (hw->port_info) {
1015 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
1016 hw->port_info = NULL;
1019 /* Attempt to disable FW logging before shutting down control queues */
1020 ice_cfg_fw_log(hw, false);
1021 ice_destroy_all_ctrlq(hw);
1023 /* Clear VSI contexts if not already cleared */
1024 ice_clear_all_vsi_ctx(hw);
1028 * ice_check_reset - Check to see if a global reset is complete
1029 * @hw: pointer to the hardware structure
1031 enum ice_status ice_check_reset(struct ice_hw *hw)
1033 u32 cnt, reg = 0, grst_timeout, uld_mask;
1035 /* Poll for Device Active state in case a recent CORER, GLOBR,
1036 * or EMPR has occurred. The grst delay value is in 100ms units.
1037 * Add 1sec for outstanding AQ commands that can take a long time.
1039 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
1040 GLGEN_RSTCTL_GRSTDEL_S) + 10;
1042 for (cnt = 0; cnt < grst_timeout; cnt++) {
1044 reg = rd32(hw, GLGEN_RSTAT);
1045 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
1049 if (cnt == grst_timeout) {
1050 ice_debug(hw, ICE_DBG_INIT,
1051 "Global reset polling failed to complete.\n");
1052 return ICE_ERR_RESET_FAILED;
1055 #define ICE_RESET_DONE_MASK (GLNVM_ULD_PCIER_DONE_M |\
1056 GLNVM_ULD_PCIER_DONE_1_M |\
1057 GLNVM_ULD_CORER_DONE_M |\
1058 GLNVM_ULD_GLOBR_DONE_M |\
1059 GLNVM_ULD_POR_DONE_M |\
1060 GLNVM_ULD_POR_DONE_1_M |\
1061 GLNVM_ULD_PCIER_DONE_2_M)
1063 uld_mask = ICE_RESET_DONE_MASK;
1065 /* Device is Active; check Global Reset processes are done */
1066 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1067 reg = rd32(hw, GLNVM_ULD) & uld_mask;
1068 if (reg == uld_mask) {
1069 ice_debug(hw, ICE_DBG_INIT,
1070 "Global reset processes done. %d\n", cnt);
1076 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1077 ice_debug(hw, ICE_DBG_INIT,
1078 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
1080 return ICE_ERR_RESET_FAILED;
1087 * ice_pf_reset - Reset the PF
1088 * @hw: pointer to the hardware structure
1090 * If a global reset has been triggered, this function checks
1091 * for its completion and then issues the PF reset
1093 static enum ice_status ice_pf_reset(struct ice_hw *hw)
1097 /* If at function entry a global reset was already in progress, i.e.
1098 * state is not 'device active' or any of the reset done bits are not
1099 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
1100 * global reset is done.
1102 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1103 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1104 /* poll on global reset currently in progress until done */
1105 if (ice_check_reset(hw))
1106 return ICE_ERR_RESET_FAILED;
1112 reg = rd32(hw, PFGEN_CTRL);
1114 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1116 /* Wait for the PFR to complete. The wait time is the global config lock
1117 * timeout plus the PFR timeout which will account for a possible reset
1118 * that is occurring during a download package operation.
1120 for (cnt = 0; cnt < ICE_GLOBAL_CFG_LOCK_TIMEOUT +
1121 ICE_PF_RESET_WAIT_COUNT; cnt++) {
1122 reg = rd32(hw, PFGEN_CTRL);
1123 if (!(reg & PFGEN_CTRL_PFSWR_M))
1129 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1130 ice_debug(hw, ICE_DBG_INIT,
1131 "PF reset polling failed to complete.\n");
1132 return ICE_ERR_RESET_FAILED;
1139 * ice_reset - Perform different types of reset
1140 * @hw: pointer to the hardware structure
1141 * @req: reset request
1143 * This function triggers a reset as specified by the req parameter.
1146 * If anything other than a PF reset is triggered, PXE mode is restored.
1147 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1148 * interface has been restored in the rebuild flow.
1150 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1156 return ice_pf_reset(hw);
1157 case ICE_RESET_CORER:
1158 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1159 val = GLGEN_RTRIG_CORER_M;
1161 case ICE_RESET_GLOBR:
1162 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1163 val = GLGEN_RTRIG_GLOBR_M;
1166 return ICE_ERR_PARAM;
1169 val |= rd32(hw, GLGEN_RTRIG);
1170 wr32(hw, GLGEN_RTRIG, val);
1173 /* wait for the FW to be ready */
1174 return ice_check_reset(hw);
1178 * ice_copy_rxq_ctx_to_hw
1179 * @hw: pointer to the hardware structure
1180 * @ice_rxq_ctx: pointer to the rxq context
1181 * @rxq_index: the index of the Rx queue
1183 * Copies rxq context from dense structure to HW register space
1185 static enum ice_status
1186 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1191 return ICE_ERR_BAD_PTR;
1193 if (rxq_index > QRX_CTRL_MAX_INDEX)
1194 return ICE_ERR_PARAM;
1196 /* Copy each dword separately to HW */
1197 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1198 wr32(hw, QRX_CONTEXT(i, rxq_index),
1199 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1201 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1202 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1208 /* LAN Rx Queue Context */
1209 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1210 /* Field Width LSB */
1211 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1212 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1213 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1214 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1215 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1216 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1217 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1218 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1219 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1220 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1221 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1222 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1223 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1224 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1225 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1226 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1227 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1228 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1229 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1230 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1236 * @hw: pointer to the hardware structure
1237 * @rlan_ctx: pointer to the rxq context
1238 * @rxq_index: the index of the Rx queue
1240 * Converts rxq context from sparse to dense structure and then writes
1241 * it to HW register space and enables the hardware to prefetch descriptors
1242 * instead of only fetching them on demand
1245 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1248 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1251 return ICE_ERR_BAD_PTR;
1253 rlan_ctx->prefena = 1;
1255 ice_set_ctx(hw, (u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1256 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1259 /* LAN Tx Queue Context */
1260 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1261 /* Field Width LSB */
1262 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1263 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1264 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1265 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1266 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1267 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1268 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1269 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1270 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1271 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1272 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1273 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1274 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1275 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1276 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1277 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1278 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1279 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1280 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1281 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1282 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1283 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1284 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1285 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1286 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1287 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1288 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1289 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1293 /* FW Admin Queue command wrappers */
1295 /* Software lock/mutex that is meant to be held while the Global Config Lock
1296 * in firmware is acquired by the software to prevent most (but not all) types
1297 * of AQ commands from being sent to FW
1299 DEFINE_MUTEX(ice_global_cfg_lock_sw);
1302 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1303 * @hw: pointer to the HW struct
1304 * @desc: descriptor describing the command
1305 * @buf: buffer to use for indirect commands (NULL for direct commands)
1306 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1307 * @cd: pointer to command details structure
1309 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1312 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1313 u16 buf_size, struct ice_sq_cd *cd)
1315 struct ice_aqc_req_res *cmd = &desc->params.res_owner;
1316 bool lock_acquired = false;
1317 enum ice_status status;
1319 /* When a package download is in process (i.e. when the firmware's
1320 * Global Configuration Lock resource is held), only the Download
1321 * Package, Get Version, Get Package Info List and Release Resource
1322 * (with resource ID set to Global Config Lock) AdminQ commands are
1323 * allowed; all others must block until the package download completes
1324 * and the Global Config Lock is released. See also
1325 * ice_acquire_global_cfg_lock().
1327 switch (le16_to_cpu(desc->opcode)) {
1328 case ice_aqc_opc_download_pkg:
1329 case ice_aqc_opc_get_pkg_info_list:
1330 case ice_aqc_opc_get_ver:
1332 case ice_aqc_opc_release_res:
1333 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK)
1337 mutex_lock(&ice_global_cfg_lock_sw);
1338 lock_acquired = true;
1342 status = ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1344 mutex_unlock(&ice_global_cfg_lock_sw);
1351 * @hw: pointer to the HW struct
1352 * @cd: pointer to command details structure or NULL
1354 * Get the firmware version (0x0001) from the admin queue commands
1356 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1358 struct ice_aqc_get_ver *resp;
1359 struct ice_aq_desc desc;
1360 enum ice_status status;
1362 resp = &desc.params.get_ver;
1364 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1366 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1369 hw->fw_branch = resp->fw_branch;
1370 hw->fw_maj_ver = resp->fw_major;
1371 hw->fw_min_ver = resp->fw_minor;
1372 hw->fw_patch = resp->fw_patch;
1373 hw->fw_build = le32_to_cpu(resp->fw_build);
1374 hw->api_branch = resp->api_branch;
1375 hw->api_maj_ver = resp->api_major;
1376 hw->api_min_ver = resp->api_minor;
1377 hw->api_patch = resp->api_patch;
1384 * ice_aq_send_driver_ver
1385 * @hw: pointer to the HW struct
1386 * @dv: driver's major, minor version
1387 * @cd: pointer to command details structure or NULL
1389 * Send the driver version (0x0002) to the firmware
1392 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1393 struct ice_sq_cd *cd)
1395 struct ice_aqc_driver_ver *cmd;
1396 struct ice_aq_desc desc;
1399 cmd = &desc.params.driver_ver;
1402 return ICE_ERR_PARAM;
1404 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1406 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1407 cmd->major_ver = dv->major_ver;
1408 cmd->minor_ver = dv->minor_ver;
1409 cmd->build_ver = dv->build_ver;
1410 cmd->subbuild_ver = dv->subbuild_ver;
1413 while (len < sizeof(dv->driver_string) &&
1414 isascii(dv->driver_string[len]) && dv->driver_string[len])
1417 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1422 * @hw: pointer to the HW struct
1423 * @unloading: is the driver unloading itself
1425 * Tell the Firmware that we're shutting down the AdminQ and whether
1426 * or not the driver is unloading as well (0x0003).
1428 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1430 struct ice_aqc_q_shutdown *cmd;
1431 struct ice_aq_desc desc;
1433 cmd = &desc.params.q_shutdown;
1435 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1438 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1440 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1445 * @hw: pointer to the HW struct
1447 * @access: access type
1448 * @sdp_number: resource number
1449 * @timeout: the maximum time in ms that the driver may hold the resource
1450 * @cd: pointer to command details structure or NULL
1452 * Requests common resource using the admin queue commands (0x0008).
1453 * When attempting to acquire the Global Config Lock, the driver can
1454 * learn of three states:
1455 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1456 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1457 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1458 * successfully downloaded the package; the driver does
1459 * not have to download the package and can continue
1462 * Note that if the caller is in an acquire lock, perform action, release lock
1463 * phase of operation, it is possible that the FW may detect a timeout and issue
1464 * a CORER. In this case, the driver will receive a CORER interrupt and will
1465 * have to determine its cause. The calling thread that is handling this flow
1466 * will likely get an error propagated back to it indicating the Download
1467 * Package, Update Package or the Release Resource AQ commands timed out.
1469 static enum ice_status
1470 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1471 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1472 struct ice_sq_cd *cd)
1474 struct ice_aqc_req_res *cmd_resp;
1475 struct ice_aq_desc desc;
1476 enum ice_status status;
1478 cmd_resp = &desc.params.res_owner;
1480 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1482 cmd_resp->res_id = cpu_to_le16(res);
1483 cmd_resp->access_type = cpu_to_le16(access);
1484 cmd_resp->res_number = cpu_to_le32(sdp_number);
1485 cmd_resp->timeout = cpu_to_le32(*timeout);
1488 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1490 /* The completion specifies the maximum time in ms that the driver
1491 * may hold the resource in the Timeout field.
1494 /* Global config lock response utilizes an additional status field.
1496 * If the Global config lock resource is held by some other driver, the
1497 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1498 * and the timeout field indicates the maximum time the current owner
1499 * of the resource has to free it.
1501 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1502 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1503 *timeout = le32_to_cpu(cmd_resp->timeout);
1505 } else if (le16_to_cpu(cmd_resp->status) ==
1506 ICE_AQ_RES_GLBL_IN_PROG) {
1507 *timeout = le32_to_cpu(cmd_resp->timeout);
1508 return ICE_ERR_AQ_ERROR;
1509 } else if (le16_to_cpu(cmd_resp->status) ==
1510 ICE_AQ_RES_GLBL_DONE) {
1511 return ICE_ERR_AQ_NO_WORK;
1514 /* invalid FW response, force a timeout immediately */
1516 return ICE_ERR_AQ_ERROR;
1519 /* If the resource is held by some other driver, the command completes
1520 * with a busy return value and the timeout field indicates the maximum
1521 * time the current owner of the resource has to free it.
1523 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1524 *timeout = le32_to_cpu(cmd_resp->timeout);
1530 * ice_aq_release_res
1531 * @hw: pointer to the HW struct
1533 * @sdp_number: resource number
1534 * @cd: pointer to command details structure or NULL
1536 * release common resource using the admin queue commands (0x0009)
1538 static enum ice_status
1539 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1540 struct ice_sq_cd *cd)
1542 struct ice_aqc_req_res *cmd;
1543 struct ice_aq_desc desc;
1545 cmd = &desc.params.res_owner;
1547 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1549 cmd->res_id = cpu_to_le16(res);
1550 cmd->res_number = cpu_to_le32(sdp_number);
1552 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1557 * @hw: pointer to the HW structure
1559 * @access: access type (read or write)
1560 * @timeout: timeout in milliseconds
1562 * This function will attempt to acquire the ownership of a resource.
1565 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1566 enum ice_aq_res_access_type access, u32 timeout)
1568 #define ICE_RES_POLLING_DELAY_MS 10
1569 u32 delay = ICE_RES_POLLING_DELAY_MS;
1570 u32 time_left = timeout;
1571 enum ice_status status;
1573 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1575 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1576 * previously acquired the resource and performed any necessary updates;
1577 * in this case the caller does not obtain the resource and has no
1578 * further work to do.
1580 if (status == ICE_ERR_AQ_NO_WORK)
1581 goto ice_acquire_res_exit;
1584 ice_debug(hw, ICE_DBG_RES,
1585 "resource %d acquire type %d failed.\n", res, access);
1587 /* If necessary, poll until the current lock owner timeouts */
1588 timeout = time_left;
1589 while (status && timeout && time_left) {
1591 timeout = (timeout > delay) ? timeout - delay : 0;
1592 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1594 if (status == ICE_ERR_AQ_NO_WORK)
1595 /* lock free, but no work to do */
1602 if (status && status != ICE_ERR_AQ_NO_WORK)
1603 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1605 ice_acquire_res_exit:
1606 if (status == ICE_ERR_AQ_NO_WORK) {
1607 if (access == ICE_RES_WRITE)
1608 ice_debug(hw, ICE_DBG_RES,
1609 "resource indicates no work to do.\n");
1611 ice_debug(hw, ICE_DBG_RES,
1612 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1619 * @hw: pointer to the HW structure
1622 * This function will release a resource using the proper Admin Command.
1624 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1626 enum ice_status status;
1627 u32 total_delay = 0;
1629 status = ice_aq_release_res(hw, res, 0, NULL);
1631 /* there are some rare cases when trying to release the resource
1632 * results in an admin queue timeout, so handle them correctly
1634 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1635 (total_delay < hw->adminq.sq_cmd_timeout)) {
1637 status = ice_aq_release_res(hw, res, 0, NULL);
1643 * ice_aq_alloc_free_res - command to allocate/free resources
1644 * @hw: pointer to the HW struct
1645 * @num_entries: number of resource entries in buffer
1646 * @buf: Indirect buffer to hold data parameters and response
1647 * @buf_size: size of buffer for indirect commands
1648 * @opc: pass in the command opcode
1649 * @cd: pointer to command details structure or NULL
1651 * Helper function to allocate/free resources using the admin queue commands
1654 ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,
1655 struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,
1656 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1658 struct ice_aqc_alloc_free_res_cmd *cmd;
1659 struct ice_aq_desc desc;
1661 cmd = &desc.params.sw_res_ctrl;
1664 return ICE_ERR_PARAM;
1666 if (buf_size < (num_entries * sizeof(buf->elem[0])))
1667 return ICE_ERR_PARAM;
1669 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1671 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1673 cmd->num_entries = cpu_to_le16(num_entries);
1675 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1679 * ice_alloc_hw_res - allocate resource
1680 * @hw: pointer to the HW struct
1681 * @type: type of resource
1682 * @num: number of resources to allocate
1683 * @btm: allocate from bottom
1684 * @res: pointer to array that will receive the resources
1687 ice_alloc_hw_res(struct ice_hw *hw, u16 type, u16 num, bool btm, u16 *res)
1689 struct ice_aqc_alloc_free_res_elem *buf;
1690 enum ice_status status;
1693 buf_len = struct_size(buf, elem, num);
1694 buf = kzalloc(buf_len, GFP_KERNEL);
1696 return ICE_ERR_NO_MEMORY;
1698 /* Prepare buffer to allocate resource. */
1699 buf->num_elems = cpu_to_le16(num);
1700 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED |
1701 ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX);
1703 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM);
1705 status = ice_aq_alloc_free_res(hw, 1, buf, buf_len,
1706 ice_aqc_opc_alloc_res, NULL);
1708 goto ice_alloc_res_exit;
1710 memcpy(res, buf->elem, sizeof(*buf->elem) * num);
1718 * ice_free_hw_res - free allocated HW resource
1719 * @hw: pointer to the HW struct
1720 * @type: type of resource to free
1721 * @num: number of resources
1722 * @res: pointer to array that contains the resources to free
1724 enum ice_status ice_free_hw_res(struct ice_hw *hw, u16 type, u16 num, u16 *res)
1726 struct ice_aqc_alloc_free_res_elem *buf;
1727 enum ice_status status;
1730 buf_len = struct_size(buf, elem, num);
1731 buf = kzalloc(buf_len, GFP_KERNEL);
1733 return ICE_ERR_NO_MEMORY;
1735 /* Prepare buffer to free resource. */
1736 buf->num_elems = cpu_to_le16(num);
1737 buf->res_type = cpu_to_le16(type);
1738 memcpy(buf->elem, res, sizeof(*buf->elem) * num);
1740 status = ice_aq_alloc_free_res(hw, num, buf, buf_len,
1741 ice_aqc_opc_free_res, NULL);
1743 ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n");
1750 * ice_get_num_per_func - determine number of resources per PF
1751 * @hw: pointer to the HW structure
1752 * @max: value to be evenly split between each PF
1754 * Determine the number of valid functions by going through the bitmap returned
1755 * from parsing capabilities and use this to calculate the number of resources
1756 * per PF based on the max value passed in.
1758 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1762 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1763 funcs = hweight8(hw->dev_caps.common_cap.valid_functions &
1764 ICE_CAPS_VALID_FUNCS_M);
1773 * ice_parse_common_caps - parse common device/function capabilities
1774 * @hw: pointer to the HW struct
1775 * @caps: pointer to common capabilities structure
1776 * @elem: the capability element to parse
1777 * @prefix: message prefix for tracing capabilities
1779 * Given a capability element, extract relevant details into the common
1780 * capability structure.
1782 * Returns: true if the capability matches one of the common capability ids,
1786 ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
1787 struct ice_aqc_list_caps_elem *elem, const char *prefix)
1789 u32 logical_id = le32_to_cpu(elem->logical_id);
1790 u32 phys_id = le32_to_cpu(elem->phys_id);
1791 u32 number = le32_to_cpu(elem->number);
1792 u16 cap = le16_to_cpu(elem->cap);
1796 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1797 caps->valid_functions = number;
1798 ice_debug(hw, ICE_DBG_INIT,
1799 "%s: valid_functions (bitmap) = %d\n", prefix,
1800 caps->valid_functions);
1802 case ICE_AQC_CAPS_SRIOV:
1803 caps->sr_iov_1_1 = (number == 1);
1804 ice_debug(hw, ICE_DBG_INIT,
1805 "%s: sr_iov_1_1 = %d\n", prefix,
1808 case ICE_AQC_CAPS_DCB:
1809 caps->dcb = (number == 1);
1810 caps->active_tc_bitmap = logical_id;
1811 caps->maxtc = phys_id;
1812 ice_debug(hw, ICE_DBG_INIT,
1813 "%s: dcb = %d\n", prefix, caps->dcb);
1814 ice_debug(hw, ICE_DBG_INIT,
1815 "%s: active_tc_bitmap = %d\n", prefix,
1816 caps->active_tc_bitmap);
1817 ice_debug(hw, ICE_DBG_INIT,
1818 "%s: maxtc = %d\n", prefix, caps->maxtc);
1820 case ICE_AQC_CAPS_RSS:
1821 caps->rss_table_size = number;
1822 caps->rss_table_entry_width = logical_id;
1823 ice_debug(hw, ICE_DBG_INIT,
1824 "%s: rss_table_size = %d\n", prefix,
1825 caps->rss_table_size);
1826 ice_debug(hw, ICE_DBG_INIT,
1827 "%s: rss_table_entry_width = %d\n", prefix,
1828 caps->rss_table_entry_width);
1830 case ICE_AQC_CAPS_RXQS:
1831 caps->num_rxq = number;
1832 caps->rxq_first_id = phys_id;
1833 ice_debug(hw, ICE_DBG_INIT,
1834 "%s: num_rxq = %d\n", prefix,
1836 ice_debug(hw, ICE_DBG_INIT,
1837 "%s: rxq_first_id = %d\n", prefix,
1838 caps->rxq_first_id);
1840 case ICE_AQC_CAPS_TXQS:
1841 caps->num_txq = number;
1842 caps->txq_first_id = phys_id;
1843 ice_debug(hw, ICE_DBG_INIT,
1844 "%s: num_txq = %d\n", prefix,
1846 ice_debug(hw, ICE_DBG_INIT,
1847 "%s: txq_first_id = %d\n", prefix,
1848 caps->txq_first_id);
1850 case ICE_AQC_CAPS_MSIX:
1851 caps->num_msix_vectors = number;
1852 caps->msix_vector_first_id = phys_id;
1853 ice_debug(hw, ICE_DBG_INIT,
1854 "%s: num_msix_vectors = %d\n", prefix,
1855 caps->num_msix_vectors);
1856 ice_debug(hw, ICE_DBG_INIT,
1857 "%s: msix_vector_first_id = %d\n", prefix,
1858 caps->msix_vector_first_id);
1860 case ICE_AQC_CAPS_PENDING_NVM_VER:
1861 caps->nvm_update_pending_nvm = true;
1862 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_nvm\n", prefix);
1864 case ICE_AQC_CAPS_PENDING_OROM_VER:
1865 caps->nvm_update_pending_orom = true;
1866 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_orom\n", prefix);
1868 case ICE_AQC_CAPS_PENDING_NET_VER:
1869 caps->nvm_update_pending_netlist = true;
1870 ice_debug(hw, ICE_DBG_INIT, "%s: update_pending_netlist\n", prefix);
1872 case ICE_AQC_CAPS_NVM_MGMT:
1873 caps->nvm_unified_update =
1874 (number & ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?
1876 ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
1877 caps->nvm_unified_update);
1879 case ICE_AQC_CAPS_MAX_MTU:
1880 caps->max_mtu = number;
1881 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1882 prefix, caps->max_mtu);
1885 /* Not one of the recognized common capabilities */
1893 * ice_recalc_port_limited_caps - Recalculate port limited capabilities
1894 * @hw: pointer to the HW structure
1895 * @caps: pointer to capabilities structure to fix
1897 * Re-calculate the capabilities that are dependent on the number of physical
1898 * ports; i.e. some features are not supported or function differently on
1899 * devices with more than 4 ports.
1902 ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)
1904 /* This assumes device capabilities are always scanned before function
1905 * capabilities during the initialization flow.
1907 if (hw->dev_caps.num_funcs > 4) {
1908 /* Max 4 TCs per port */
1910 ice_debug(hw, ICE_DBG_INIT,
1911 "reducing maxtc to %d (based on #ports)\n",
1917 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps
1918 * @hw: pointer to the HW struct
1919 * @func_p: pointer to function capabilities structure
1920 * @cap: pointer to the capability element to parse
1922 * Extract function capabilities for ICE_AQC_CAPS_VF.
1925 ice_parse_vf_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
1926 struct ice_aqc_list_caps_elem *cap)
1928 u32 logical_id = le32_to_cpu(cap->logical_id);
1929 u32 number = le32_to_cpu(cap->number);
1931 func_p->num_allocd_vfs = number;
1932 func_p->vf_base_id = logical_id;
1933 ice_debug(hw, ICE_DBG_INIT, "func caps: num_allocd_vfs = %d\n",
1934 func_p->num_allocd_vfs);
1935 ice_debug(hw, ICE_DBG_INIT, "func caps: vf_base_id = %d\n",
1936 func_p->vf_base_id);
1940 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
1941 * @hw: pointer to the HW struct
1942 * @func_p: pointer to function capabilities structure
1943 * @cap: pointer to the capability element to parse
1945 * Extract function capabilities for ICE_AQC_CAPS_VSI.
1948 ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
1949 struct ice_aqc_list_caps_elem *cap)
1951 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);
1952 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi (fw) = %d\n",
1953 le32_to_cpu(cap->number));
1954 ice_debug(hw, ICE_DBG_INIT, "func caps: guar_num_vsi = %d\n",
1955 func_p->guar_num_vsi);
1959 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
1960 * @hw: pointer to the HW struct
1961 * @func_p: pointer to function capabilities structure
1963 * Extract function capabilities for ICE_AQC_CAPS_FD.
1966 ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p)
1970 reg_val = rd32(hw, GLQF_FD_SIZE);
1971 val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>
1972 GLQF_FD_SIZE_FD_GSIZE_S;
1973 func_p->fd_fltr_guar =
1974 ice_get_num_per_func(hw, val);
1975 val = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>
1976 GLQF_FD_SIZE_FD_BSIZE_S;
1977 func_p->fd_fltr_best_effort = val;
1979 ice_debug(hw, ICE_DBG_INIT,
1980 "func caps: fd_fltr_guar = %d\n",
1981 func_p->fd_fltr_guar);
1982 ice_debug(hw, ICE_DBG_INIT,
1983 "func caps: fd_fltr_best_effort = %d\n",
1984 func_p->fd_fltr_best_effort);
1988 * ice_parse_func_caps - Parse function capabilities
1989 * @hw: pointer to the HW struct
1990 * @func_p: pointer to function capabilities structure
1991 * @buf: buffer containing the function capability records
1992 * @cap_count: the number of capabilities
1994 * Helper function to parse function (0x000A) capabilities list. For
1995 * capabilities shared between device and function, this relies on
1996 * ice_parse_common_caps.
1998 * Loop through the list of provided capabilities and extract the relevant
1999 * data into the function capabilities structured.
2002 ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
2003 void *buf, u32 cap_count)
2005 struct ice_aqc_list_caps_elem *cap_resp;
2008 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2010 memset(func_p, 0, sizeof(*func_p));
2012 for (i = 0; i < cap_count; i++) {
2013 u16 cap = le16_to_cpu(cap_resp[i].cap);
2016 found = ice_parse_common_caps(hw, &func_p->common_cap,
2017 &cap_resp[i], "func caps");
2020 case ICE_AQC_CAPS_VF:
2021 ice_parse_vf_func_caps(hw, func_p, &cap_resp[i]);
2023 case ICE_AQC_CAPS_VSI:
2024 ice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);
2026 case ICE_AQC_CAPS_FD:
2027 ice_parse_fdir_func_caps(hw, func_p);
2030 /* Don't list common capabilities as unknown */
2032 ice_debug(hw, ICE_DBG_INIT,
2033 "func caps: unknown capability[%d]: 0x%x\n",
2039 ice_recalc_port_limited_caps(hw, &func_p->common_cap);
2043 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2044 * @hw: pointer to the HW struct
2045 * @dev_p: pointer to device capabilities structure
2046 * @cap: capability element to parse
2048 * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.
2051 ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2052 struct ice_aqc_list_caps_elem *cap)
2054 u32 number = le32_to_cpu(cap->number);
2056 dev_p->num_funcs = hweight32(number);
2057 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_funcs = %d\n",
2062 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps
2063 * @hw: pointer to the HW struct
2064 * @dev_p: pointer to device capabilities structure
2065 * @cap: capability element to parse
2067 * Parse ICE_AQC_CAPS_VF for device capabilities.
2070 ice_parse_vf_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2071 struct ice_aqc_list_caps_elem *cap)
2073 u32 number = le32_to_cpu(cap->number);
2075 dev_p->num_vfs_exposed = number;
2076 ice_debug(hw, ICE_DBG_INIT, "dev_caps: num_vfs_exposed = %d\n",
2077 dev_p->num_vfs_exposed);
2081 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2082 * @hw: pointer to the HW struct
2083 * @dev_p: pointer to device capabilities structure
2084 * @cap: capability element to parse
2086 * Parse ICE_AQC_CAPS_VSI for device capabilities.
2089 ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2090 struct ice_aqc_list_caps_elem *cap)
2092 u32 number = le32_to_cpu(cap->number);
2094 dev_p->num_vsi_allocd_to_host = number;
2095 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_vsi_allocd_to_host = %d\n",
2096 dev_p->num_vsi_allocd_to_host);
2100 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2101 * @hw: pointer to the HW struct
2102 * @dev_p: pointer to device capabilities structure
2103 * @cap: capability element to parse
2105 * Parse ICE_AQC_CAPS_FD for device capabilities.
2108 ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2109 struct ice_aqc_list_caps_elem *cap)
2111 u32 number = le32_to_cpu(cap->number);
2113 dev_p->num_flow_director_fltr = number;
2114 ice_debug(hw, ICE_DBG_INIT, "dev caps: num_flow_director_fltr = %d\n",
2115 dev_p->num_flow_director_fltr);
2119 * ice_parse_dev_caps - Parse device capabilities
2120 * @hw: pointer to the HW struct
2121 * @dev_p: pointer to device capabilities structure
2122 * @buf: buffer containing the device capability records
2123 * @cap_count: the number of capabilities
2125 * Helper device to parse device (0x000B) capabilities list. For
2126 * capabilities shared between device and function, this relies on
2127 * ice_parse_common_caps.
2129 * Loop through the list of provided capabilities and extract the relevant
2130 * data into the device capabilities structured.
2133 ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,
2134 void *buf, u32 cap_count)
2136 struct ice_aqc_list_caps_elem *cap_resp;
2139 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
2141 memset(dev_p, 0, sizeof(*dev_p));
2143 for (i = 0; i < cap_count; i++) {
2144 u16 cap = le16_to_cpu(cap_resp[i].cap);
2147 found = ice_parse_common_caps(hw, &dev_p->common_cap,
2148 &cap_resp[i], "dev caps");
2151 case ICE_AQC_CAPS_VALID_FUNCTIONS:
2152 ice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);
2154 case ICE_AQC_CAPS_VF:
2155 ice_parse_vf_dev_caps(hw, dev_p, &cap_resp[i]);
2157 case ICE_AQC_CAPS_VSI:
2158 ice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);
2160 case ICE_AQC_CAPS_FD:
2161 ice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);
2164 /* Don't list common capabilities as unknown */
2166 ice_debug(hw, ICE_DBG_INIT,
2167 "dev caps: unknown capability[%d]: 0x%x\n",
2173 ice_recalc_port_limited_caps(hw, &dev_p->common_cap);
2177 * ice_aq_list_caps - query function/device capabilities
2178 * @hw: pointer to the HW struct
2179 * @buf: a buffer to hold the capabilities
2180 * @buf_size: size of the buffer
2181 * @cap_count: if not NULL, set to the number of capabilities reported
2182 * @opc: capabilities type to discover, device or function
2183 * @cd: pointer to command details structure or NULL
2185 * Get the function (0x000A) or device (0x000B) capabilities description from
2186 * firmware and store it in the buffer.
2188 * If the cap_count pointer is not NULL, then it is set to the number of
2189 * capabilities firmware will report. Note that if the buffer size is too
2190 * small, it is possible the command will return ICE_AQ_ERR_ENOMEM. The
2191 * cap_count will still be updated in this case. It is recommended that the
2192 * buffer size be set to ICE_AQ_MAX_BUF_LEN (the largest possible buffer that
2193 * firmware could return) to avoid this.
2196 ice_aq_list_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
2197 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
2199 struct ice_aqc_list_caps *cmd;
2200 struct ice_aq_desc desc;
2201 enum ice_status status;
2203 cmd = &desc.params.get_cap;
2205 if (opc != ice_aqc_opc_list_func_caps &&
2206 opc != ice_aqc_opc_list_dev_caps)
2207 return ICE_ERR_PARAM;
2209 ice_fill_dflt_direct_cmd_desc(&desc, opc);
2210 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
2213 *cap_count = le32_to_cpu(cmd->count);
2219 * ice_discover_dev_caps - Read and extract device capabilities
2220 * @hw: pointer to the hardware structure
2221 * @dev_caps: pointer to device capabilities structure
2223 * Read the device capabilities and extract them into the dev_caps structure
2227 ice_discover_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_caps)
2229 enum ice_status status;
2233 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
2235 return ICE_ERR_NO_MEMORY;
2237 /* Although the driver doesn't know the number of capabilities the
2238 * device will return, we can simply send a 4KB buffer, the maximum
2239 * possible size that firmware can return.
2241 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2243 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2244 ice_aqc_opc_list_dev_caps, NULL);
2246 ice_parse_dev_caps(hw, dev_caps, cbuf, cap_count);
2253 * ice_discover_func_caps - Read and extract function capabilities
2254 * @hw: pointer to the hardware structure
2255 * @func_caps: pointer to function capabilities structure
2257 * Read the function capabilities and extract them into the func_caps structure
2260 static enum ice_status
2261 ice_discover_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_caps)
2263 enum ice_status status;
2267 cbuf = kzalloc(ICE_AQ_MAX_BUF_LEN, GFP_KERNEL);
2269 return ICE_ERR_NO_MEMORY;
2271 /* Although the driver doesn't know the number of capabilities the
2272 * device will return, we can simply send a 4KB buffer, the maximum
2273 * possible size that firmware can return.
2275 cap_count = ICE_AQ_MAX_BUF_LEN / sizeof(struct ice_aqc_list_caps_elem);
2277 status = ice_aq_list_caps(hw, cbuf, ICE_AQ_MAX_BUF_LEN, &cap_count,
2278 ice_aqc_opc_list_func_caps, NULL);
2280 ice_parse_func_caps(hw, func_caps, cbuf, cap_count);
2287 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2288 * @hw: pointer to the hardware structure
2290 void ice_set_safe_mode_caps(struct ice_hw *hw)
2292 struct ice_hw_func_caps *func_caps = &hw->func_caps;
2293 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
2294 struct ice_hw_common_caps cached_caps;
2297 /* cache some func_caps values that should be restored after memset */
2298 cached_caps = func_caps->common_cap;
2300 /* unset func capabilities */
2301 memset(func_caps, 0, sizeof(*func_caps));
2303 #define ICE_RESTORE_FUNC_CAP(name) \
2304 func_caps->common_cap.name = cached_caps.name
2306 /* restore cached values */
2307 ICE_RESTORE_FUNC_CAP(valid_functions);
2308 ICE_RESTORE_FUNC_CAP(txq_first_id);
2309 ICE_RESTORE_FUNC_CAP(rxq_first_id);
2310 ICE_RESTORE_FUNC_CAP(msix_vector_first_id);
2311 ICE_RESTORE_FUNC_CAP(max_mtu);
2312 ICE_RESTORE_FUNC_CAP(nvm_unified_update);
2313 ICE_RESTORE_FUNC_CAP(nvm_update_pending_nvm);
2314 ICE_RESTORE_FUNC_CAP(nvm_update_pending_orom);
2315 ICE_RESTORE_FUNC_CAP(nvm_update_pending_netlist);
2317 /* one Tx and one Rx queue in safe mode */
2318 func_caps->common_cap.num_rxq = 1;
2319 func_caps->common_cap.num_txq = 1;
2321 /* two MSIX vectors, one for traffic and one for misc causes */
2322 func_caps->common_cap.num_msix_vectors = 2;
2323 func_caps->guar_num_vsi = 1;
2325 /* cache some dev_caps values that should be restored after memset */
2326 cached_caps = dev_caps->common_cap;
2327 num_funcs = dev_caps->num_funcs;
2329 /* unset dev capabilities */
2330 memset(dev_caps, 0, sizeof(*dev_caps));
2332 #define ICE_RESTORE_DEV_CAP(name) \
2333 dev_caps->common_cap.name = cached_caps.name
2335 /* restore cached values */
2336 ICE_RESTORE_DEV_CAP(valid_functions);
2337 ICE_RESTORE_DEV_CAP(txq_first_id);
2338 ICE_RESTORE_DEV_CAP(rxq_first_id);
2339 ICE_RESTORE_DEV_CAP(msix_vector_first_id);
2340 ICE_RESTORE_DEV_CAP(max_mtu);
2341 ICE_RESTORE_DEV_CAP(nvm_unified_update);
2342 ICE_RESTORE_DEV_CAP(nvm_update_pending_nvm);
2343 ICE_RESTORE_DEV_CAP(nvm_update_pending_orom);
2344 ICE_RESTORE_DEV_CAP(nvm_update_pending_netlist);
2345 dev_caps->num_funcs = num_funcs;
2347 /* one Tx and one Rx queue per function in safe mode */
2348 dev_caps->common_cap.num_rxq = num_funcs;
2349 dev_caps->common_cap.num_txq = num_funcs;
2351 /* two MSIX vectors per function */
2352 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs;
2356 * ice_get_caps - get info about the HW
2357 * @hw: pointer to the hardware structure
2359 enum ice_status ice_get_caps(struct ice_hw *hw)
2361 enum ice_status status;
2363 status = ice_discover_dev_caps(hw, &hw->dev_caps);
2367 return ice_discover_func_caps(hw, &hw->func_caps);
2371 * ice_aq_manage_mac_write - manage MAC address write command
2372 * @hw: pointer to the HW struct
2373 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
2374 * @flags: flags to control write behavior
2375 * @cd: pointer to command details structure or NULL
2377 * This function is used to write MAC address to the NVM (0x0108).
2380 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
2381 struct ice_sq_cd *cd)
2383 struct ice_aqc_manage_mac_write *cmd;
2384 struct ice_aq_desc desc;
2386 cmd = &desc.params.mac_write;
2387 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
2390 ether_addr_copy(cmd->mac_addr, mac_addr);
2392 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2396 * ice_aq_clear_pxe_mode
2397 * @hw: pointer to the HW struct
2399 * Tell the firmware that the driver is taking over from PXE (0x0110).
2401 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
2403 struct ice_aq_desc desc;
2405 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
2406 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
2408 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
2412 * ice_clear_pxe_mode - clear pxe operations mode
2413 * @hw: pointer to the HW struct
2415 * Make sure all PXE mode settings are cleared, including things
2416 * like descriptor fetch/write-back mode.
2418 void ice_clear_pxe_mode(struct ice_hw *hw)
2420 if (ice_check_sq_alive(hw, &hw->adminq))
2421 ice_aq_clear_pxe_mode(hw);
2425 * ice_get_link_speed_based_on_phy_type - returns link speed
2426 * @phy_type_low: lower part of phy_type
2427 * @phy_type_high: higher part of phy_type
2429 * This helper function will convert an entry in PHY type structure
2430 * [phy_type_low, phy_type_high] to its corresponding link speed.
2431 * Note: In the structure of [phy_type_low, phy_type_high], there should
2432 * be one bit set, as this function will convert one PHY type to its
2434 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2435 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2438 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2440 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2441 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2443 switch (phy_type_low) {
2444 case ICE_PHY_TYPE_LOW_100BASE_TX:
2445 case ICE_PHY_TYPE_LOW_100M_SGMII:
2446 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2448 case ICE_PHY_TYPE_LOW_1000BASE_T:
2449 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2450 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2451 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2452 case ICE_PHY_TYPE_LOW_1G_SGMII:
2453 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2455 case ICE_PHY_TYPE_LOW_2500BASE_T:
2456 case ICE_PHY_TYPE_LOW_2500BASE_X:
2457 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2458 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2460 case ICE_PHY_TYPE_LOW_5GBASE_T:
2461 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2462 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2464 case ICE_PHY_TYPE_LOW_10GBASE_T:
2465 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2466 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2467 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2468 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2469 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2470 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2471 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2473 case ICE_PHY_TYPE_LOW_25GBASE_T:
2474 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2475 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2476 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2477 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2478 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2479 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2480 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2481 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2482 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2483 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2484 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2486 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2487 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2488 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2489 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2490 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2491 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2492 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2494 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2495 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2496 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2497 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2498 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2499 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2500 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2501 case ICE_PHY_TYPE_LOW_50G_AUI2:
2502 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2503 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2504 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2505 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2506 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2507 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2508 case ICE_PHY_TYPE_LOW_50G_AUI1:
2509 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2511 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2512 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2513 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2514 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2515 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2516 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2517 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2518 case ICE_PHY_TYPE_LOW_100G_AUI4:
2519 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2520 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2521 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2522 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2523 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2524 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2527 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2531 switch (phy_type_high) {
2532 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2533 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2534 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2535 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2536 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2537 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2540 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2544 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2545 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2546 return ICE_AQ_LINK_SPEED_UNKNOWN;
2547 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2548 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2549 return ICE_AQ_LINK_SPEED_UNKNOWN;
2550 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2551 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2552 return speed_phy_type_low;
2554 return speed_phy_type_high;
2558 * ice_update_phy_type
2559 * @phy_type_low: pointer to the lower part of phy_type
2560 * @phy_type_high: pointer to the higher part of phy_type
2561 * @link_speeds_bitmap: targeted link speeds bitmap
2563 * Note: For the link_speeds_bitmap structure, you can check it at
2564 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2565 * link_speeds_bitmap include multiple speeds.
2567 * Each entry in this [phy_type_low, phy_type_high] structure will
2568 * present a certain link speed. This helper function will turn on bits
2569 * in [phy_type_low, phy_type_high] structure based on the value of
2570 * link_speeds_bitmap input parameter.
2573 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2574 u16 link_speeds_bitmap)
2581 /* We first check with low part of phy_type */
2582 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2583 pt_low = BIT_ULL(index);
2584 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2586 if (link_speeds_bitmap & speed)
2587 *phy_type_low |= BIT_ULL(index);
2590 /* We then check with high part of phy_type */
2591 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2592 pt_high = BIT_ULL(index);
2593 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2595 if (link_speeds_bitmap & speed)
2596 *phy_type_high |= BIT_ULL(index);
2601 * ice_aq_set_phy_cfg
2602 * @hw: pointer to the HW struct
2603 * @pi: port info structure of the interested logical port
2604 * @cfg: structure with PHY configuration data to be set
2605 * @cd: pointer to command details structure or NULL
2607 * Set the various PHY configuration parameters supported on the Port.
2608 * One or more of the Set PHY config parameters may be ignored in an MFP
2609 * mode as the PF may not have the privilege to set some of the PHY Config
2610 * parameters. This status will be indicated by the command response (0x0601).
2613 ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
2614 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2616 struct ice_aq_desc desc;
2617 enum ice_status status;
2620 return ICE_ERR_PARAM;
2622 /* Ensure that only valid bits of cfg->caps can be turned on. */
2623 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2624 ice_debug(hw, ICE_DBG_PHY,
2625 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2628 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2631 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2632 desc.params.set_phy.lport_num = pi->lport;
2633 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2635 ice_debug(hw, ICE_DBG_LINK, "set phy cfg\n");
2636 ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n",
2637 (unsigned long long)le64_to_cpu(cfg->phy_type_low));
2638 ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n",
2639 (unsigned long long)le64_to_cpu(cfg->phy_type_high));
2640 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps);
2641 ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n",
2642 cfg->low_power_ctrl_an);
2643 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap);
2644 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value);
2645 ice_debug(hw, ICE_DBG_LINK, " link_fec_opt = 0x%x\n",
2648 status = ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2649 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
2653 pi->phy.curr_user_phy_cfg = *cfg;
2659 * ice_update_link_info - update status of the HW network link
2660 * @pi: port info structure of the interested logical port
2662 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2664 struct ice_link_status *li;
2665 enum ice_status status;
2668 return ICE_ERR_PARAM;
2670 li = &pi->phy.link_info;
2672 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2676 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2677 struct ice_aqc_get_phy_caps_data *pcaps;
2681 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps),
2684 return ICE_ERR_NO_MEMORY;
2686 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
2689 devm_kfree(ice_hw_to_dev(hw), pcaps);
2696 * ice_cache_phy_user_req
2697 * @pi: port information structure
2698 * @cache_data: PHY logging data
2699 * @cache_mode: PHY logging mode
2701 * Log the user request on (FC, FEC, SPEED) for later use.
2704 ice_cache_phy_user_req(struct ice_port_info *pi,
2705 struct ice_phy_cache_mode_data cache_data,
2706 enum ice_phy_cache_mode cache_mode)
2711 switch (cache_mode) {
2713 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req;
2715 case ICE_SPEED_MODE:
2716 pi->phy.curr_user_speed_req =
2717 cache_data.data.curr_user_speed_req;
2720 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req;
2728 * ice_caps_to_fc_mode
2729 * @caps: PHY capabilities
2731 * Convert PHY FC capabilities to ice FC mode
2733 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)
2735 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&
2736 caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2739 if (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)
2740 return ICE_FC_TX_PAUSE;
2742 if (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)
2743 return ICE_FC_RX_PAUSE;
2749 * ice_caps_to_fec_mode
2750 * @caps: PHY capabilities
2751 * @fec_options: Link FEC options
2753 * Convert PHY FEC capabilities to ice FEC mode
2755 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)
2757 if (caps & ICE_AQC_PHY_EN_AUTO_FEC)
2758 return ICE_FEC_AUTO;
2760 if (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2761 ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2762 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |
2763 ICE_AQC_PHY_FEC_25G_KR_REQ))
2764 return ICE_FEC_BASER;
2766 if (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2767 ICE_AQC_PHY_FEC_25G_RS_544_REQ |
2768 ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))
2771 return ICE_FEC_NONE;
2775 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode
2776 * @pi: port information structure
2777 * @cfg: PHY configuration data to set FC mode
2778 * @req_mode: FC mode to configure
2781 ice_cfg_phy_fc(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2782 enum ice_fc_mode req_mode)
2784 struct ice_phy_cache_mode_data cache_data;
2785 u8 pause_mask = 0x0;
2788 return ICE_ERR_BAD_PTR;
2792 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2793 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2795 case ICE_FC_RX_PAUSE:
2796 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2798 case ICE_FC_TX_PAUSE:
2799 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2805 /* clear the old pause settings */
2806 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2807 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2809 /* set the new capabilities */
2810 cfg->caps |= pause_mask;
2812 /* Cache user FC request */
2813 cache_data.data.curr_user_fc_req = req_mode;
2814 ice_cache_phy_user_req(pi, cache_data, ICE_FC_MODE);
2821 * @pi: port information structure
2822 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2823 * @ena_auto_link_update: enable automatic link update
2825 * Set the requested flow control mode.
2828 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2830 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2831 struct ice_aqc_get_phy_caps_data *pcaps;
2832 enum ice_status status;
2835 if (!pi || !aq_failures)
2836 return ICE_ERR_BAD_PTR;
2841 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
2843 return ICE_ERR_NO_MEMORY;
2845 /* Get the current PHY config */
2846 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
2849 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2853 ice_copy_phy_caps_to_cfg(pi, pcaps, &cfg);
2855 /* Configure the set PHY data */
2856 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode);
2860 /* If the capabilities have changed, then set the new config */
2861 if (cfg.caps != pcaps->caps) {
2862 int retry_count, retry_max = 10;
2864 /* Auto restart link so settings take effect */
2865 if (ena_auto_link_update)
2866 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2868 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
2870 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2874 /* Update the link info
2875 * It sometimes takes a really long time for link to
2876 * come back from the atomic reset. Thus, we wait a
2879 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2880 status = ice_update_link_info(pi);
2889 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2893 devm_kfree(ice_hw_to_dev(hw), pcaps);
2898 * ice_phy_caps_equals_cfg
2899 * @phy_caps: PHY capabilities
2900 * @phy_cfg: PHY configuration
2902 * Helper function to determine if PHY capabilities matches PHY
2906 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,
2907 struct ice_aqc_set_phy_cfg_data *phy_cfg)
2909 u8 caps_mask, cfg_mask;
2911 if (!phy_caps || !phy_cfg)
2914 /* These bits are not common between capabilities and configuration.
2915 * Do not use them to determine equality.
2917 caps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |
2918 ICE_AQC_GET_PHY_EN_MOD_QUAL);
2919 cfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2921 if (phy_caps->phy_type_low != phy_cfg->phy_type_low ||
2922 phy_caps->phy_type_high != phy_cfg->phy_type_high ||
2923 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||
2924 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||
2925 phy_caps->eee_cap != phy_cfg->eee_cap ||
2926 phy_caps->eeer_value != phy_cfg->eeer_value ||
2927 phy_caps->link_fec_options != phy_cfg->link_fec_opt)
2934 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2935 * @pi: port information structure
2936 * @caps: PHY ability structure to copy date from
2937 * @cfg: PHY configuration structure to copy data to
2939 * Helper function to copy AQC PHY get ability data to PHY set configuration
2943 ice_copy_phy_caps_to_cfg(struct ice_port_info *pi,
2944 struct ice_aqc_get_phy_caps_data *caps,
2945 struct ice_aqc_set_phy_cfg_data *cfg)
2947 if (!pi || !caps || !cfg)
2950 memset(cfg, 0, sizeof(*cfg));
2951 cfg->phy_type_low = caps->phy_type_low;
2952 cfg->phy_type_high = caps->phy_type_high;
2953 cfg->caps = caps->caps;
2954 cfg->low_power_ctrl_an = caps->low_power_ctrl_an;
2955 cfg->eee_cap = caps->eee_cap;
2956 cfg->eeer_value = caps->eeer_value;
2957 cfg->link_fec_opt = caps->link_fec_options;
2958 cfg->module_compliance_enforcement =
2959 caps->module_compliance_enforcement;
2961 if (ice_fw_supports_link_override(pi->hw)) {
2962 struct ice_link_default_override_tlv tlv;
2964 if (ice_get_link_default_override(&tlv, pi))
2967 if (tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE)
2968 cfg->module_compliance_enforcement |=
2969 ICE_LINK_OVERRIDE_STRICT_MODE;
2974 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2975 * @pi: port information structure
2976 * @cfg: PHY configuration data to set FEC mode
2977 * @fec: FEC mode to configure
2980 ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,
2981 enum ice_fec_mode fec)
2983 struct ice_aqc_get_phy_caps_data *pcaps;
2984 enum ice_status status;
2987 return ICE_ERR_BAD_PTR;
2989 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
2991 return ICE_ERR_NO_MEMORY;
2993 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA, pcaps,
2998 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC;
2999 cfg->link_fec_opt = pcaps->link_fec_options;
3003 /* Clear RS bits, and AND BASE-R ability
3004 * bits and OR request bits.
3006 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
3007 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
3008 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
3009 ICE_AQC_PHY_FEC_25G_KR_REQ;
3012 /* Clear BASE-R bits, and AND RS ability
3013 * bits and OR request bits.
3015 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
3016 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
3017 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
3020 /* Clear all FEC option bits. */
3021 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
3024 /* AND auto FEC bit, and all caps bits. */
3025 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
3026 cfg->link_fec_opt |= pcaps->link_fec_options;
3029 status = ICE_ERR_PARAM;
3033 if (fec == ICE_FEC_AUTO && ice_fw_supports_link_override(pi->hw)) {
3034 struct ice_link_default_override_tlv tlv;
3036 status = ice_get_link_default_override(&tlv, pi);
3040 if (!(tlv.options & ICE_LINK_OVERRIDE_STRICT_MODE) &&
3041 (tlv.options & ICE_LINK_OVERRIDE_EN))
3042 cfg->link_fec_opt = tlv.fec_options;
3052 * ice_get_link_status - get status of the HW network link
3053 * @pi: port information structure
3054 * @link_up: pointer to bool (true/false = linkup/linkdown)
3056 * Variable link_up is true if link is up, false if link is down.
3057 * The variable link_up is invalid if status is non zero. As a
3058 * result of this call, link status reporting becomes enabled
3060 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
3062 struct ice_phy_info *phy_info;
3063 enum ice_status status = 0;
3065 if (!pi || !link_up)
3066 return ICE_ERR_PARAM;
3068 phy_info = &pi->phy;
3070 if (phy_info->get_link_info) {
3071 status = ice_update_link_info(pi);
3074 ice_debug(pi->hw, ICE_DBG_LINK,
3075 "get link status error, status = %d\n",
3079 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
3085 * ice_aq_set_link_restart_an
3086 * @pi: pointer to the port information structure
3087 * @ena_link: if true: enable link, if false: disable link
3088 * @cd: pointer to command details structure or NULL
3090 * Sets up the link and restarts the Auto-Negotiation over the link.
3093 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
3094 struct ice_sq_cd *cd)
3096 struct ice_aqc_restart_an *cmd;
3097 struct ice_aq_desc desc;
3099 cmd = &desc.params.restart_an;
3101 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
3103 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
3104 cmd->lport_num = pi->lport;
3106 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
3108 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
3110 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
3114 * ice_aq_set_event_mask
3115 * @hw: pointer to the HW struct
3116 * @port_num: port number of the physical function
3117 * @mask: event mask to be set
3118 * @cd: pointer to command details structure or NULL
3120 * Set event mask (0x0613)
3123 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
3124 struct ice_sq_cd *cd)
3126 struct ice_aqc_set_event_mask *cmd;
3127 struct ice_aq_desc desc;
3129 cmd = &desc.params.set_event_mask;
3131 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
3133 cmd->lport_num = port_num;
3135 cmd->event_mask = cpu_to_le16(mask);
3136 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3140 * ice_aq_set_mac_loopback
3141 * @hw: pointer to the HW struct
3142 * @ena_lpbk: Enable or Disable loopback
3143 * @cd: pointer to command details structure or NULL
3145 * Enable/disable loopback on a given port
3148 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
3150 struct ice_aqc_set_mac_lb *cmd;
3151 struct ice_aq_desc desc;
3153 cmd = &desc.params.set_mac_lb;
3155 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
3157 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
3159 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3163 * ice_aq_set_port_id_led
3164 * @pi: pointer to the port information
3165 * @is_orig_mode: is this LED set to original mode (by the net-list)
3166 * @cd: pointer to command details structure or NULL
3168 * Set LED value for the given port (0x06e9)
3171 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
3172 struct ice_sq_cd *cd)
3174 struct ice_aqc_set_port_id_led *cmd;
3175 struct ice_hw *hw = pi->hw;
3176 struct ice_aq_desc desc;
3178 cmd = &desc.params.set_port_id_led;
3180 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
3183 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
3185 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
3187 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
3192 * @hw: pointer to the HW struct
3193 * @lport: bits [7:0] = logical port, bit [8] = logical port valid
3194 * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)
3195 * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.
3197 * @set_page: set or ignore the page
3198 * @data: pointer to data buffer to be read/written to the I2C device.
3199 * @length: 1-16 for read, 1 for write.
3200 * @write: 0 read, 1 for write.
3201 * @cd: pointer to command details structure or NULL
3203 * Read/Write SFF EEPROM (0x06EE)
3206 ice_aq_sff_eeprom(struct ice_hw *hw, u16 lport, u8 bus_addr,
3207 u16 mem_addr, u8 page, u8 set_page, u8 *data, u8 length,
3208 bool write, struct ice_sq_cd *cd)
3210 struct ice_aqc_sff_eeprom *cmd;
3211 struct ice_aq_desc desc;
3212 enum ice_status status;
3214 if (!data || (mem_addr & 0xff00))
3215 return ICE_ERR_PARAM;
3217 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_sff_eeprom);
3218 cmd = &desc.params.read_write_sff_param;
3219 desc.flags = cpu_to_le16(ICE_AQ_FLAG_RD | ICE_AQ_FLAG_BUF);
3220 cmd->lport_num = (u8)(lport & 0xff);
3221 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01);
3222 cmd->i2c_bus_addr = cpu_to_le16(((bus_addr >> 1) &
3223 ICE_AQC_SFF_I2CBUS_7BIT_M) |
3225 ICE_AQC_SFF_SET_EEPROM_PAGE_S) &
3226 ICE_AQC_SFF_SET_EEPROM_PAGE_M));
3227 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff);
3228 cmd->eeprom_page = cpu_to_le16((u16)page << ICE_AQC_SFF_EEPROM_PAGE_S);
3230 cmd->i2c_bus_addr |= cpu_to_le16(ICE_AQC_SFF_IS_WRITE);
3232 status = ice_aq_send_cmd(hw, &desc, data, length, cd);
3237 * __ice_aq_get_set_rss_lut
3238 * @hw: pointer to the hardware structure
3239 * @vsi_id: VSI FW index
3240 * @lut_type: LUT table type
3241 * @lut: pointer to the LUT buffer provided by the caller
3242 * @lut_size: size of the LUT buffer
3243 * @glob_lut_idx: global LUT index
3244 * @set: set true to set the table, false to get the table
3246 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
3248 static enum ice_status
3249 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
3250 u16 lut_size, u8 glob_lut_idx, bool set)
3252 struct ice_aqc_get_set_rss_lut *cmd_resp;
3253 struct ice_aq_desc desc;
3254 enum ice_status status;
3257 cmd_resp = &desc.params.get_set_rss_lut;
3260 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
3261 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3263 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
3266 cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
3267 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
3268 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
3269 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
3272 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
3273 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
3274 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
3275 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
3276 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
3279 status = ICE_ERR_PARAM;
3280 goto ice_aq_get_set_rss_lut_exit;
3283 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
3284 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
3285 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
3288 goto ice_aq_get_set_rss_lut_send;
3289 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3291 goto ice_aq_get_set_rss_lut_send;
3293 goto ice_aq_get_set_rss_lut_send;
3296 /* LUT size is only valid for Global and PF table types */
3298 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
3300 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
3301 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
3302 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3303 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3305 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
3306 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
3307 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
3308 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
3309 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
3314 status = ICE_ERR_PARAM;
3315 goto ice_aq_get_set_rss_lut_exit;
3318 ice_aq_get_set_rss_lut_send:
3319 cmd_resp->flags = cpu_to_le16(flags);
3320 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
3322 ice_aq_get_set_rss_lut_exit:
3327 * ice_aq_get_rss_lut
3328 * @hw: pointer to the hardware structure
3329 * @vsi_handle: software VSI handle
3330 * @lut_type: LUT table type
3331 * @lut: pointer to the LUT buffer provided by the caller
3332 * @lut_size: size of the LUT buffer
3334 * get the RSS lookup table, PF or VSI type
3337 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3338 u8 *lut, u16 lut_size)
3340 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3341 return ICE_ERR_PARAM;
3343 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3344 lut_type, lut, lut_size, 0, false);
3348 * ice_aq_set_rss_lut
3349 * @hw: pointer to the hardware structure
3350 * @vsi_handle: software VSI handle
3351 * @lut_type: LUT table type
3352 * @lut: pointer to the LUT buffer provided by the caller
3353 * @lut_size: size of the LUT buffer
3355 * set the RSS lookup table, PF or VSI type
3358 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
3359 u8 *lut, u16 lut_size)
3361 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
3362 return ICE_ERR_PARAM;
3364 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3365 lut_type, lut, lut_size, 0, true);
3369 * __ice_aq_get_set_rss_key
3370 * @hw: pointer to the HW struct
3371 * @vsi_id: VSI FW index
3372 * @key: pointer to key info struct
3373 * @set: set true to set the key, false to get the key
3375 * get (0x0B04) or set (0x0B02) the RSS key per VSI
3378 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
3379 struct ice_aqc_get_set_rss_keys *key,
3382 struct ice_aqc_get_set_rss_key *cmd_resp;
3383 u16 key_size = sizeof(*key);
3384 struct ice_aq_desc desc;
3386 cmd_resp = &desc.params.get_set_rss_key;
3389 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
3390 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3392 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
3395 cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
3396 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
3397 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
3398 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
3400 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
3404 * ice_aq_get_rss_key
3405 * @hw: pointer to the HW struct
3406 * @vsi_handle: software VSI handle
3407 * @key: pointer to key info struct
3409 * get the RSS key per VSI
3412 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
3413 struct ice_aqc_get_set_rss_keys *key)
3415 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
3416 return ICE_ERR_PARAM;
3418 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3423 * ice_aq_set_rss_key
3424 * @hw: pointer to the HW struct
3425 * @vsi_handle: software VSI handle
3426 * @keys: pointer to key info struct
3428 * set the RSS key per VSI
3431 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
3432 struct ice_aqc_get_set_rss_keys *keys)
3434 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
3435 return ICE_ERR_PARAM;
3437 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
3442 * ice_aq_add_lan_txq
3443 * @hw: pointer to the hardware structure
3444 * @num_qgrps: Number of added queue groups
3445 * @qg_list: list of queue groups to be added
3446 * @buf_size: size of buffer for indirect command
3447 * @cd: pointer to command details structure or NULL
3449 * Add Tx LAN queue (0x0C30)
3452 * Prior to calling add Tx LAN queue:
3453 * Initialize the following as part of the Tx queue context:
3454 * Completion queue ID if the queue uses Completion queue, Quanta profile,
3455 * Cache profile and Packet shaper profile.
3457 * After add Tx LAN queue AQ command is completed:
3458 * Interrupts should be associated with specific queues,
3459 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
3462 static enum ice_status
3463 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3464 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
3465 struct ice_sq_cd *cd)
3467 struct ice_aqc_add_tx_qgrp *list;
3468 struct ice_aqc_add_txqs *cmd;
3469 struct ice_aq_desc desc;
3470 u16 i, sum_size = 0;
3472 cmd = &desc.params.add_txqs;
3474 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
3477 return ICE_ERR_PARAM;
3479 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3480 return ICE_ERR_PARAM;
3482 for (i = 0, list = qg_list; i < num_qgrps; i++) {
3483 sum_size += struct_size(list, txqs, list->num_txqs);
3484 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs +
3488 if (buf_size != sum_size)
3489 return ICE_ERR_PARAM;
3491 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3493 cmd->num_qgrps = num_qgrps;
3495 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3499 * ice_aq_dis_lan_txq
3500 * @hw: pointer to the hardware structure
3501 * @num_qgrps: number of groups in the list
3502 * @qg_list: the list of groups to disable
3503 * @buf_size: the total size of the qg_list buffer in bytes
3504 * @rst_src: if called due to reset, specifies the reset source
3505 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3506 * @cd: pointer to command details structure or NULL
3508 * Disable LAN Tx queue (0x0C31)
3510 static enum ice_status
3511 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
3512 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
3513 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3514 struct ice_sq_cd *cd)
3516 struct ice_aqc_dis_txq_item *item;
3517 struct ice_aqc_dis_txqs *cmd;
3518 struct ice_aq_desc desc;
3519 enum ice_status status;
3522 cmd = &desc.params.dis_txqs;
3523 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
3525 /* qg_list can be NULL only in VM/VF reset flow */
3526 if (!qg_list && !rst_src)
3527 return ICE_ERR_PARAM;
3529 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
3530 return ICE_ERR_PARAM;
3532 cmd->num_entries = num_qgrps;
3534 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
3535 ICE_AQC_Q_DIS_TIMEOUT_M);
3539 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
3540 cmd->vmvf_and_timeout |=
3541 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
3544 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;
3545 /* In this case, FW expects vmvf_num to be absolute VF ID */
3546 cmd->vmvf_and_timeout |=
3547 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) &
3548 ICE_AQC_Q_DIS_VMVF_NUM_M);
3555 /* flush pipe on time out */
3556 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
3557 /* If no queue group info, we are in a reset flow. Issue the AQ */
3561 /* set RD bit to indicate that command buffer is provided by the driver
3562 * and it needs to be read by the firmware
3564 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
3566 for (i = 0, item = qg_list; i < num_qgrps; i++) {
3567 u16 item_size = struct_size(item, q_id, item->num_qs);
3569 /* If the num of queues is even, add 2 bytes of padding */
3570 if ((item->num_qs % 2) == 0)
3575 item = (struct ice_aqc_dis_txq_item *)((u8 *)item + item_size);
3579 return ICE_ERR_PARAM;
3582 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
3585 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
3586 vmvf_num, hw->adminq.sq_last_status);
3588 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
3589 le16_to_cpu(qg_list[0].q_id[0]),
3590 hw->adminq.sq_last_status);
3595 /* End of FW Admin Queue command wrappers */
3598 * ice_write_byte - write a byte to a packed context structure
3599 * @src_ctx: the context structure to read from
3600 * @dest_ctx: the context to be written to
3601 * @ce_info: a description of the struct to be filled
3604 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3606 u8 src_byte, dest_byte, mask;
3610 /* copy from the next struct field */
3611 from = src_ctx + ce_info->offset;
3613 /* prepare the bits and mask */
3614 shift_width = ce_info->lsb % 8;
3615 mask = (u8)(BIT(ce_info->width) - 1);
3620 /* shift to correct alignment */
3621 mask <<= shift_width;
3622 src_byte <<= shift_width;
3624 /* get the current bits from the target bit string */
3625 dest = dest_ctx + (ce_info->lsb / 8);
3627 memcpy(&dest_byte, dest, sizeof(dest_byte));
3629 dest_byte &= ~mask; /* get the bits not changing */
3630 dest_byte |= src_byte; /* add in the new bits */
3632 /* put it all back */
3633 memcpy(dest, &dest_byte, sizeof(dest_byte));
3637 * ice_write_word - write a word to a packed context structure
3638 * @src_ctx: the context structure to read from
3639 * @dest_ctx: the context to be written to
3640 * @ce_info: a description of the struct to be filled
3643 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3650 /* copy from the next struct field */
3651 from = src_ctx + ce_info->offset;
3653 /* prepare the bits and mask */
3654 shift_width = ce_info->lsb % 8;
3655 mask = BIT(ce_info->width) - 1;
3657 /* don't swizzle the bits until after the mask because the mask bits
3658 * will be in a different bit position on big endian machines
3660 src_word = *(u16 *)from;
3663 /* shift to correct alignment */
3664 mask <<= shift_width;
3665 src_word <<= shift_width;
3667 /* get the current bits from the target bit string */
3668 dest = dest_ctx + (ce_info->lsb / 8);
3670 memcpy(&dest_word, dest, sizeof(dest_word));
3672 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */
3673 dest_word |= cpu_to_le16(src_word); /* add in the new bits */
3675 /* put it all back */
3676 memcpy(dest, &dest_word, sizeof(dest_word));
3680 * ice_write_dword - write a dword to a packed context structure
3681 * @src_ctx: the context structure to read from
3682 * @dest_ctx: the context to be written to
3683 * @ce_info: a description of the struct to be filled
3686 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3688 u32 src_dword, mask;
3693 /* copy from the next struct field */
3694 from = src_ctx + ce_info->offset;
3696 /* prepare the bits and mask */
3697 shift_width = ce_info->lsb % 8;
3699 /* if the field width is exactly 32 on an x86 machine, then the shift
3700 * operation will not work because the SHL instructions count is masked
3701 * to 5 bits so the shift will do nothing
3703 if (ce_info->width < 32)
3704 mask = BIT(ce_info->width) - 1;
3708 /* don't swizzle the bits until after the mask because the mask bits
3709 * will be in a different bit position on big endian machines
3711 src_dword = *(u32 *)from;
3714 /* shift to correct alignment */
3715 mask <<= shift_width;
3716 src_dword <<= shift_width;
3718 /* get the current bits from the target bit string */
3719 dest = dest_ctx + (ce_info->lsb / 8);
3721 memcpy(&dest_dword, dest, sizeof(dest_dword));
3723 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */
3724 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */
3726 /* put it all back */
3727 memcpy(dest, &dest_dword, sizeof(dest_dword));
3731 * ice_write_qword - write a qword to a packed context structure
3732 * @src_ctx: the context structure to read from
3733 * @dest_ctx: the context to be written to
3734 * @ce_info: a description of the struct to be filled
3737 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3739 u64 src_qword, mask;
3744 /* copy from the next struct field */
3745 from = src_ctx + ce_info->offset;
3747 /* prepare the bits and mask */
3748 shift_width = ce_info->lsb % 8;
3750 /* if the field width is exactly 64 on an x86 machine, then the shift
3751 * operation will not work because the SHL instructions count is masked
3752 * to 6 bits so the shift will do nothing
3754 if (ce_info->width < 64)
3755 mask = BIT_ULL(ce_info->width) - 1;
3759 /* don't swizzle the bits until after the mask because the mask bits
3760 * will be in a different bit position on big endian machines
3762 src_qword = *(u64 *)from;
3765 /* shift to correct alignment */
3766 mask <<= shift_width;
3767 src_qword <<= shift_width;
3769 /* get the current bits from the target bit string */
3770 dest = dest_ctx + (ce_info->lsb / 8);
3772 memcpy(&dest_qword, dest, sizeof(dest_qword));
3774 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */
3775 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */
3777 /* put it all back */
3778 memcpy(dest, &dest_qword, sizeof(dest_qword));
3782 * ice_set_ctx - set context bits in packed structure
3783 * @hw: pointer to the hardware structure
3784 * @src_ctx: pointer to a generic non-packed context structure
3785 * @dest_ctx: pointer to memory for the packed structure
3786 * @ce_info: a description of the structure to be transformed
3789 ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx,
3790 const struct ice_ctx_ele *ce_info)
3794 for (f = 0; ce_info[f].width; f++) {
3795 /* We have to deal with each element of the FW response
3796 * using the correct size so that we are correct regardless
3797 * of the endianness of the machine.
3799 if (ce_info[f].width > (ce_info[f].size_of * BITS_PER_BYTE)) {
3800 ice_debug(hw, ICE_DBG_QCTX,
3801 "Field %d width of %d bits larger than size of %d byte(s) ... skipping write\n",
3802 f, ce_info[f].width, ce_info[f].size_of);
3805 switch (ce_info[f].size_of) {
3807 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3810 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3813 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3816 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3819 return ICE_ERR_INVAL_SIZE;
3827 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3828 * @hw: pointer to the HW struct
3829 * @vsi_handle: software VSI handle
3831 * @q_handle: software queue handle
3834 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3836 struct ice_vsi_ctx *vsi;
3837 struct ice_q_ctx *q_ctx;
3839 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3842 if (q_handle >= vsi->num_lan_q_entries[tc])
3844 if (!vsi->lan_q_ctx[tc])
3846 q_ctx = vsi->lan_q_ctx[tc];
3847 return &q_ctx[q_handle];
3852 * @pi: port information structure
3853 * @vsi_handle: software VSI handle
3855 * @q_handle: software queue handle
3856 * @num_qgrps: Number of added queue groups
3857 * @buf: list of queue groups to be added
3858 * @buf_size: size of buffer for indirect command
3859 * @cd: pointer to command details structure or NULL
3861 * This function adds one LAN queue
3864 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3865 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3866 struct ice_sq_cd *cd)
3868 struct ice_aqc_txsched_elem_data node = { 0 };
3869 struct ice_sched_node *parent;
3870 struct ice_q_ctx *q_ctx;
3871 enum ice_status status;
3874 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3877 if (num_qgrps > 1 || buf->num_txqs > 1)
3878 return ICE_ERR_MAX_LIMIT;
3882 if (!ice_is_vsi_valid(hw, vsi_handle))
3883 return ICE_ERR_PARAM;
3885 mutex_lock(&pi->sched_lock);
3887 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3889 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3891 status = ICE_ERR_PARAM;
3895 /* find a parent node */
3896 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3897 ICE_SCHED_NODE_OWNER_LAN);
3899 status = ICE_ERR_PARAM;
3903 buf->parent_teid = parent->info.node_teid;
3904 node.parent_teid = parent->info.node_teid;
3905 /* Mark that the values in the "generic" section as valid. The default
3906 * value in the "generic" section is zero. This means that :
3907 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3908 * - 0 priority among siblings, indicated by Bit 1-3.
3909 * - WFQ, indicated by Bit 4.
3910 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3912 * - Bit 7 is reserved.
3913 * Without setting the generic section as valid in valid_sections, the
3914 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3916 buf->txqs[0].info.valid_sections =
3917 ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |
3918 ICE_AQC_ELEM_VALID_EIR;
3919 buf->txqs[0].info.generic = 0;
3920 buf->txqs[0].info.cir_bw.bw_profile_idx =
3921 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
3922 buf->txqs[0].info.cir_bw.bw_alloc =
3923 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
3924 buf->txqs[0].info.eir_bw.bw_profile_idx =
3925 cpu_to_le16(ICE_SCHED_DFLT_RL_PROF_ID);
3926 buf->txqs[0].info.eir_bw.bw_alloc =
3927 cpu_to_le16(ICE_SCHED_DFLT_BW_WT);
3929 /* add the LAN queue */
3930 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3932 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3933 le16_to_cpu(buf->txqs[0].txq_id),
3934 hw->adminq.sq_last_status);
3938 node.node_teid = buf->txqs[0].q_teid;
3939 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3940 q_ctx->q_handle = q_handle;
3941 q_ctx->q_teid = le32_to_cpu(node.node_teid);
3943 /* add a leaf node into scheduler tree queue layer */
3944 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3946 status = ice_sched_replay_q_bw(pi, q_ctx);
3949 mutex_unlock(&pi->sched_lock);
3955 * @pi: port information structure
3956 * @vsi_handle: software VSI handle
3958 * @num_queues: number of queues
3959 * @q_handles: pointer to software queue handle array
3960 * @q_ids: pointer to the q_id array
3961 * @q_teids: pointer to queue node teids
3962 * @rst_src: if called due to reset, specifies the reset source
3963 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3964 * @cd: pointer to command details structure or NULL
3966 * This function removes queues and their corresponding nodes in SW DB
3969 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3970 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3971 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3972 struct ice_sq_cd *cd)
3974 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3975 struct ice_aqc_dis_txq_item *qg_list;
3976 struct ice_q_ctx *q_ctx;
3980 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3986 /* if queue is disabled already yet the disable queue command
3987 * has to be sent to complete the VF reset, then call
3988 * ice_aq_dis_lan_txq without any queue information
3991 return ice_aq_dis_lan_txq(hw, 0, NULL, 0, rst_src,
3996 buf_size = struct_size(qg_list, q_id, 1);
3997 qg_list = kzalloc(buf_size, GFP_KERNEL);
3999 return ICE_ERR_NO_MEMORY;
4001 mutex_lock(&pi->sched_lock);
4003 for (i = 0; i < num_queues; i++) {
4004 struct ice_sched_node *node;
4006 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
4009 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handles[i]);
4011 ice_debug(hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
4015 if (q_ctx->q_handle != q_handles[i]) {
4016 ice_debug(hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
4017 q_ctx->q_handle, q_handles[i]);
4020 qg_list->parent_teid = node->info.parent_teid;
4021 qg_list->num_qs = 1;
4022 qg_list->q_id[0] = cpu_to_le16(q_ids[i]);
4023 status = ice_aq_dis_lan_txq(hw, 1, qg_list, buf_size, rst_src,
4028 ice_free_sched_node(pi, node);
4029 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
4031 mutex_unlock(&pi->sched_lock);
4037 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4038 * @pi: port information structure
4039 * @vsi_handle: software VSI handle
4040 * @tc_bitmap: TC bitmap
4041 * @maxqs: max queues array per TC
4042 * @owner: LAN or RDMA
4044 * This function adds/updates the VSI queues per TC.
4046 static enum ice_status
4047 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4048 u16 *maxqs, u8 owner)
4050 enum ice_status status = 0;
4053 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
4056 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
4057 return ICE_ERR_PARAM;
4059 mutex_lock(&pi->sched_lock);
4061 ice_for_each_traffic_class(i) {
4062 /* configuration is possible only if TC node is present */
4063 if (!ice_sched_get_tc_node(pi, i))
4066 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
4067 ice_is_tc_ena(tc_bitmap, i));
4072 mutex_unlock(&pi->sched_lock);
4077 * ice_cfg_vsi_lan - configure VSI LAN queues
4078 * @pi: port information structure
4079 * @vsi_handle: software VSI handle
4080 * @tc_bitmap: TC bitmap
4081 * @max_lanqs: max LAN queues array per TC
4083 * This function adds/updates the VSI LAN queues per TC.
4086 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
4089 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
4090 ICE_SCHED_NODE_OWNER_LAN);
4094 * ice_replay_pre_init - replay pre initialization
4095 * @hw: pointer to the HW struct
4097 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
4099 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
4101 struct ice_switch_info *sw = hw->switch_info;
4104 /* Delete old entries from replay filter list head if there is any */
4105 ice_rm_all_sw_replay_rule_info(hw);
4106 /* In start of replay, move entries into replay_rules list, it
4107 * will allow adding rules entries back to filt_rules list,
4108 * which is operational list.
4110 for (i = 0; i < ICE_SW_LKUP_LAST; i++)
4111 list_replace_init(&sw->recp_list[i].filt_rules,
4112 &sw->recp_list[i].filt_replay_rules);
4118 * ice_replay_vsi - replay VSI configuration
4119 * @hw: pointer to the HW struct
4120 * @vsi_handle: driver VSI handle
4122 * Restore all VSI configuration after reset. It is required to call this
4123 * function with main VSI first.
4125 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
4127 enum ice_status status;
4129 if (!ice_is_vsi_valid(hw, vsi_handle))
4130 return ICE_ERR_PARAM;
4132 /* Replay pre-initialization if there is any */
4133 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
4134 status = ice_replay_pre_init(hw);
4138 /* Replay per VSI all RSS configurations */
4139 status = ice_replay_rss_cfg(hw, vsi_handle);
4142 /* Replay per VSI all filters */
4143 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
4148 * ice_replay_post - post replay configuration cleanup
4149 * @hw: pointer to the HW struct
4151 * Post replay cleanup.
4153 void ice_replay_post(struct ice_hw *hw)
4155 /* Delete old entries from replay filter list head */
4156 ice_rm_all_sw_replay_rule_info(hw);
4160 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
4161 * @hw: ptr to the hardware info
4162 * @reg: offset of 64 bit HW register to read from
4163 * @prev_stat_loaded: bool to specify if previous stats are loaded
4164 * @prev_stat: ptr to previous loaded stat value
4165 * @cur_stat: ptr to current stat value
4168 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4169 u64 *prev_stat, u64 *cur_stat)
4171 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
4173 /* device stats are not reset at PFR, they likely will not be zeroed
4174 * when the driver starts. Thus, save the value from the first read
4175 * without adding to the statistic value so that we report stats which
4176 * count up from zero.
4178 if (!prev_stat_loaded) {
4179 *prev_stat = new_data;
4183 /* Calculate the difference between the new and old values, and then
4184 * add it to the software stat value.
4186 if (new_data >= *prev_stat)
4187 *cur_stat += new_data - *prev_stat;
4189 /* to manage the potential roll-over */
4190 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
4192 /* Update the previously stored value to prepare for next read */
4193 *prev_stat = new_data;
4197 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
4198 * @hw: ptr to the hardware info
4199 * @reg: offset of HW register to read from
4200 * @prev_stat_loaded: bool to specify if previous stats are loaded
4201 * @prev_stat: ptr to previous loaded stat value
4202 * @cur_stat: ptr to current stat value
4205 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
4206 u64 *prev_stat, u64 *cur_stat)
4210 new_data = rd32(hw, reg);
4212 /* device stats are not reset at PFR, they likely will not be zeroed
4213 * when the driver starts. Thus, save the value from the first read
4214 * without adding to the statistic value so that we report stats which
4215 * count up from zero.
4217 if (!prev_stat_loaded) {
4218 *prev_stat = new_data;
4222 /* Calculate the difference between the new and old values, and then
4223 * add it to the software stat value.
4225 if (new_data >= *prev_stat)
4226 *cur_stat += new_data - *prev_stat;
4228 /* to manage the potential roll-over */
4229 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
4231 /* Update the previously stored value to prepare for next read */
4232 *prev_stat = new_data;
4236 * ice_sched_query_elem - query element information from HW
4237 * @hw: pointer to the HW struct
4238 * @node_teid: node TEID to be queried
4239 * @buf: buffer to element information
4241 * This function queries HW element information
4244 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
4245 struct ice_aqc_txsched_elem_data *buf)
4247 u16 buf_size, num_elem_ret = 0;
4248 enum ice_status status;
4250 buf_size = sizeof(*buf);
4251 memset(buf, 0, buf_size);
4252 buf->node_teid = cpu_to_le32(node_teid);
4253 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
4255 if (status || num_elem_ret != 1)
4256 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
4261 * ice_fw_supports_link_override
4262 * @hw: pointer to the hardware structure
4264 * Checks if the firmware supports link override
4266 bool ice_fw_supports_link_override(struct ice_hw *hw)
4268 /* Currently, only supported for E810 devices */
4269 if (hw->mac_type != ICE_MAC_E810)
4272 if (hw->api_maj_ver == ICE_FW_API_LINK_OVERRIDE_MAJ) {
4273 if (hw->api_min_ver > ICE_FW_API_LINK_OVERRIDE_MIN)
4275 if (hw->api_min_ver == ICE_FW_API_LINK_OVERRIDE_MIN &&
4276 hw->api_patch >= ICE_FW_API_LINK_OVERRIDE_PATCH)
4278 } else if (hw->api_maj_ver > ICE_FW_API_LINK_OVERRIDE_MAJ) {
4286 * ice_get_link_default_override
4287 * @ldo: pointer to the link default override struct
4288 * @pi: pointer to the port info struct
4290 * Gets the link default override for a port
4293 ice_get_link_default_override(struct ice_link_default_override_tlv *ldo,
4294 struct ice_port_info *pi)
4296 u16 i, tlv, tlv_len, tlv_start, buf, offset;
4297 struct ice_hw *hw = pi->hw;
4298 enum ice_status status;
4300 status = ice_get_pfa_module_tlv(hw, &tlv, &tlv_len,
4301 ICE_SR_LINK_DEFAULT_OVERRIDE_PTR);
4303 ice_debug(hw, ICE_DBG_INIT,
4304 "Failed to read link override TLV.\n");
4308 /* Each port has its own config; calculate for our port */
4309 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS +
4310 ICE_SR_PFA_LINK_OVERRIDE_OFFSET;
4312 /* link options first */
4313 status = ice_read_sr_word(hw, tlv_start, &buf);
4315 ice_debug(hw, ICE_DBG_INIT,
4316 "Failed to read override link options.\n");
4319 ldo->options = buf & ICE_LINK_OVERRIDE_OPT_M;
4320 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >>
4321 ICE_LINK_OVERRIDE_PHY_CFG_S;
4323 /* link PHY config */
4324 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET;
4325 status = ice_read_sr_word(hw, offset, &buf);
4327 ice_debug(hw, ICE_DBG_INIT,
4328 "Failed to read override phy config.\n");
4331 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M;
4334 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET;
4335 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4336 status = ice_read_sr_word(hw, (offset + i), &buf);
4338 ice_debug(hw, ICE_DBG_INIT,
4339 "Failed to read override link options.\n");
4342 /* shift 16 bits at a time to fill 64 bits */
4343 ldo->phy_type_low |= ((u64)buf << (i * 16));
4346 /* PHY types high */
4347 offset = tlv_start + ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET +
4348 ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS;
4349 for (i = 0; i < ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS; i++) {
4350 status = ice_read_sr_word(hw, (offset + i), &buf);
4352 ice_debug(hw, ICE_DBG_INIT,
4353 "Failed to read override link options.\n");
4356 /* shift 16 bits at a time to fill 64 bits */
4357 ldo->phy_type_high |= ((u64)buf << (i * 16));
4364 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
4365 * @caps: get PHY capability data
4367 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps)
4369 if (caps->caps & ICE_AQC_PHY_AN_MODE ||
4370 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 |
4371 ICE_AQC_PHY_AN_EN_CLAUSE73 |
4372 ICE_AQC_PHY_AN_EN_CLAUSE37))
4379 * ice_aq_set_lldp_mib - Set the LLDP MIB
4380 * @hw: pointer to the HW struct
4381 * @mib_type: Local, Remote or both Local and Remote MIBs
4382 * @buf: pointer to the caller-supplied buffer to store the MIB block
4383 * @buf_size: size of the buffer (in bytes)
4384 * @cd: pointer to command details structure or NULL
4386 * Set the LLDP MIB. (0x0A08)
4389 ice_aq_set_lldp_mib(struct ice_hw *hw, u8 mib_type, void *buf, u16 buf_size,
4390 struct ice_sq_cd *cd)
4392 struct ice_aqc_lldp_set_local_mib *cmd;
4393 struct ice_aq_desc desc;
4395 cmd = &desc.params.lldp_set_mib;
4397 if (buf_size == 0 || !buf)
4398 return ICE_ERR_PARAM;
4400 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_set_local_mib);
4402 desc.flags |= cpu_to_le16((u16)ICE_AQ_FLAG_RD);
4403 desc.datalen = cpu_to_le16(buf_size);
4405 cmd->type = mib_type;
4406 cmd->length = cpu_to_le16(buf_size);
4408 return ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);