1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include <linux/prefetch.h>
28 #include <net/busy_poll.h>
31 #include "i40e_trace.h"
32 #include "i40e_prototype.h"
34 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
37 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
38 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
39 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
40 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
41 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
47 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
48 * @ring: the ring that owns the buffer
49 * @tx_buffer: the buffer to free
51 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
52 struct i40e_tx_buffer *tx_buffer)
55 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
56 kfree(tx_buffer->raw_buf);
58 dev_kfree_skb_any(tx_buffer->skb);
59 if (dma_unmap_len(tx_buffer, len))
60 dma_unmap_single(ring->dev,
61 dma_unmap_addr(tx_buffer, dma),
62 dma_unmap_len(tx_buffer, len),
64 } else if (dma_unmap_len(tx_buffer, len)) {
65 dma_unmap_page(ring->dev,
66 dma_unmap_addr(tx_buffer, dma),
67 dma_unmap_len(tx_buffer, len),
71 tx_buffer->next_to_watch = NULL;
72 tx_buffer->skb = NULL;
73 dma_unmap_len_set(tx_buffer, len, 0);
74 /* tx_buffer must be completely set up in the transmit path */
78 * i40evf_clean_tx_ring - Free any empty Tx buffers
79 * @tx_ring: ring to be cleaned
81 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
83 unsigned long bi_size;
86 /* ring already cleared, nothing to do */
90 /* Free all the Tx ring sk_buffs */
91 for (i = 0; i < tx_ring->count; i++)
92 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
94 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
95 memset(tx_ring->tx_bi, 0, bi_size);
97 /* Zero out the descriptor ring */
98 memset(tx_ring->desc, 0, tx_ring->size);
100 tx_ring->next_to_use = 0;
101 tx_ring->next_to_clean = 0;
103 if (!tx_ring->netdev)
106 /* cleanup Tx queue statistics */
107 netdev_tx_reset_queue(txring_txq(tx_ring));
111 * i40evf_free_tx_resources - Free Tx resources per queue
112 * @tx_ring: Tx descriptor ring for a specific queue
114 * Free all transmit software resources
116 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
118 i40evf_clean_tx_ring(tx_ring);
119 kfree(tx_ring->tx_bi);
120 tx_ring->tx_bi = NULL;
123 dma_free_coherent(tx_ring->dev, tx_ring->size,
124 tx_ring->desc, tx_ring->dma);
125 tx_ring->desc = NULL;
130 * i40evf_get_tx_pending - how many Tx descriptors not processed
131 * @tx_ring: the ring of descriptors
132 * @in_sw: is tx_pending being checked in SW or HW
134 * Since there is no access to the ring head register
135 * in XL710, we need to use our local copies
137 u32 i40evf_get_tx_pending(struct i40e_ring *ring, bool in_sw)
141 /* underlying hardware might not allow access and/or always return
142 * 0 for the head/tail registers so just use the cached values
144 head = ring->next_to_clean;
145 tail = ring->next_to_use;
148 return (head < tail) ?
149 tail - head : (tail + ring->count - head);
157 * i40e_clean_tx_irq - Reclaim resources after transmit completes
158 * @vsi: the VSI we care about
159 * @tx_ring: Tx ring to clean
160 * @napi_budget: Used to determine if we are in netpoll
162 * Returns true if there's any budget left (e.g. the clean is finished)
164 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
165 struct i40e_ring *tx_ring, int napi_budget)
167 u16 i = tx_ring->next_to_clean;
168 struct i40e_tx_buffer *tx_buf;
169 struct i40e_tx_desc *tx_desc;
170 unsigned int total_bytes = 0, total_packets = 0;
171 unsigned int budget = vsi->work_limit;
173 tx_buf = &tx_ring->tx_bi[i];
174 tx_desc = I40E_TX_DESC(tx_ring, i);
178 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
180 /* if next_to_watch is not set then there is no work pending */
184 /* prevent any other reads prior to eop_desc */
187 i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
188 /* if the descriptor isn't done, no work yet to do */
189 if (!(eop_desc->cmd_type_offset_bsz &
190 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
193 /* clear next_to_watch to prevent false hangs */
194 tx_buf->next_to_watch = NULL;
196 /* update the statistics for this packet */
197 total_bytes += tx_buf->bytecount;
198 total_packets += tx_buf->gso_segs;
201 napi_consume_skb(tx_buf->skb, napi_budget);
203 /* unmap skb header data */
204 dma_unmap_single(tx_ring->dev,
205 dma_unmap_addr(tx_buf, dma),
206 dma_unmap_len(tx_buf, len),
209 /* clear tx_buffer data */
211 dma_unmap_len_set(tx_buf, len, 0);
213 /* unmap remaining buffers */
214 while (tx_desc != eop_desc) {
215 i40e_trace(clean_tx_irq_unmap,
216 tx_ring, tx_desc, tx_buf);
223 tx_buf = tx_ring->tx_bi;
224 tx_desc = I40E_TX_DESC(tx_ring, 0);
227 /* unmap any remaining paged data */
228 if (dma_unmap_len(tx_buf, len)) {
229 dma_unmap_page(tx_ring->dev,
230 dma_unmap_addr(tx_buf, dma),
231 dma_unmap_len(tx_buf, len),
233 dma_unmap_len_set(tx_buf, len, 0);
237 /* move us one more past the eop_desc for start of next pkt */
243 tx_buf = tx_ring->tx_bi;
244 tx_desc = I40E_TX_DESC(tx_ring, 0);
249 /* update budget accounting */
251 } while (likely(budget));
254 tx_ring->next_to_clean = i;
255 u64_stats_update_begin(&tx_ring->syncp);
256 tx_ring->stats.bytes += total_bytes;
257 tx_ring->stats.packets += total_packets;
258 u64_stats_update_end(&tx_ring->syncp);
259 tx_ring->q_vector->tx.total_bytes += total_bytes;
260 tx_ring->q_vector->tx.total_packets += total_packets;
262 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
263 /* check to see if there are < 4 descriptors
264 * waiting to be written back, then kick the hardware to force
265 * them to be written back in case we stay in NAPI.
266 * In this mode on X722 we do not enable Interrupt.
268 unsigned int j = i40evf_get_tx_pending(tx_ring, false);
271 ((j / WB_STRIDE) == 0) && (j > 0) &&
272 !test_bit(__I40E_VSI_DOWN, vsi->state) &&
273 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
274 tx_ring->arm_wb = true;
277 /* notify netdev of completed buffers */
278 netdev_tx_completed_queue(txring_txq(tx_ring),
279 total_packets, total_bytes);
281 #define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
282 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
283 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
284 /* Make sure that anybody stopping the queue after this
285 * sees the new next_to_clean.
288 if (__netif_subqueue_stopped(tx_ring->netdev,
289 tx_ring->queue_index) &&
290 !test_bit(__I40E_VSI_DOWN, vsi->state)) {
291 netif_wake_subqueue(tx_ring->netdev,
292 tx_ring->queue_index);
293 ++tx_ring->tx_stats.restart_queue;
301 * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
302 * @vsi: the VSI we care about
303 * @q_vector: the vector on which to enable writeback
306 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
307 struct i40e_q_vector *q_vector)
309 u16 flags = q_vector->tx.ring[0].flags;
312 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
315 if (q_vector->arm_wb_state)
318 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
319 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
322 I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
323 vsi->base_vector - 1), val);
324 q_vector->arm_wb_state = true;
328 * i40evf_force_wb - Issue SW Interrupt so HW does a wb
329 * @vsi: the VSI we care about
330 * @q_vector: the vector on which to force writeback
333 void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
335 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
336 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
337 I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
338 I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
339 /* allow 00 to be written to the index */;
342 I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
347 * i40e_set_new_dynamic_itr - Find new ITR level
348 * @rc: structure containing ring performance data
350 * Returns true if ITR changed, false if not
352 * Stores a new ITR value based on packets and byte counts during
353 * the last interrupt. The advantage of per interrupt computation
354 * is faster updates and more accurate ITR for the current traffic
355 * pattern. Constants in this function were computed based on
356 * theoretical maximum wire speed and thresholds were set based on
357 * testing data as well as attempting to minimize response time
358 * while increasing bulk throughput.
360 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
362 enum i40e_latency_range new_latency_range = rc->latency_range;
363 u32 new_itr = rc->itr;
365 unsigned int usecs, estimated_usecs;
367 if (rc->total_packets == 0 || !rc->itr)
370 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
371 bytes_per_int = rc->total_bytes / usecs;
373 /* The calculations in this algorithm depend on interrupts actually
374 * firing at the ITR rate. This may not happen if the packet rate is
375 * really low, or if we've been napi polling. Check to make sure
376 * that's not the case before we continue.
378 estimated_usecs = jiffies_to_usecs(jiffies - rc->last_itr_update);
379 if (estimated_usecs > usecs) {
380 new_latency_range = I40E_LOW_LATENCY;
384 /* simple throttlerate management
385 * 0-10MB/s lowest (50000 ints/s)
386 * 10-20MB/s low (20000 ints/s)
387 * 20-1249MB/s bulk (18000 ints/s)
389 * The math works out because the divisor is in 10^(-6) which
390 * turns the bytes/us input value into MB/s values, but
391 * make sure to use usecs, as the register values written
392 * are in 2 usec increments in the ITR registers, and make sure
393 * to use the smoothed values that the countdown timer gives us.
395 switch (new_latency_range) {
396 case I40E_LOWEST_LATENCY:
397 if (bytes_per_int > 10)
398 new_latency_range = I40E_LOW_LATENCY;
400 case I40E_LOW_LATENCY:
401 if (bytes_per_int > 20)
402 new_latency_range = I40E_BULK_LATENCY;
403 else if (bytes_per_int <= 10)
404 new_latency_range = I40E_LOWEST_LATENCY;
406 case I40E_BULK_LATENCY:
408 if (bytes_per_int <= 20)
409 new_latency_range = I40E_LOW_LATENCY;
414 rc->latency_range = new_latency_range;
416 switch (new_latency_range) {
417 case I40E_LOWEST_LATENCY:
418 new_itr = I40E_ITR_50K;
420 case I40E_LOW_LATENCY:
421 new_itr = I40E_ITR_20K;
423 case I40E_BULK_LATENCY:
424 new_itr = I40E_ITR_18K;
431 rc->total_packets = 0;
432 rc->last_itr_update = jiffies;
434 if (new_itr != rc->itr) {
442 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
443 * @tx_ring: the tx ring to set up
445 * Return 0 on success, negative on error
447 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
449 struct device *dev = tx_ring->dev;
455 /* warn if we are about to overwrite the pointer */
456 WARN_ON(tx_ring->tx_bi);
457 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
458 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
462 /* round up to nearest 4K */
463 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
464 tx_ring->size = ALIGN(tx_ring->size, 4096);
465 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
466 &tx_ring->dma, GFP_KERNEL);
467 if (!tx_ring->desc) {
468 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
473 tx_ring->next_to_use = 0;
474 tx_ring->next_to_clean = 0;
478 kfree(tx_ring->tx_bi);
479 tx_ring->tx_bi = NULL;
484 * i40evf_clean_rx_ring - Free Rx buffers
485 * @rx_ring: ring to be cleaned
487 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
489 unsigned long bi_size;
492 /* ring already cleared, nothing to do */
497 dev_kfree_skb(rx_ring->skb);
501 /* Free all the Rx ring sk_buffs */
502 for (i = 0; i < rx_ring->count; i++) {
503 struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i];
508 /* Invalidate cache lines that may have been written to by
509 * device so that we avoid corrupting memory.
511 dma_sync_single_range_for_cpu(rx_ring->dev,
517 /* free resources associated with mapping */
518 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma,
519 i40e_rx_pg_size(rx_ring),
523 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias);
526 rx_bi->page_offset = 0;
529 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
530 memset(rx_ring->rx_bi, 0, bi_size);
532 /* Zero out the descriptor ring */
533 memset(rx_ring->desc, 0, rx_ring->size);
535 rx_ring->next_to_alloc = 0;
536 rx_ring->next_to_clean = 0;
537 rx_ring->next_to_use = 0;
541 * i40evf_free_rx_resources - Free Rx resources
542 * @rx_ring: ring to clean the resources from
544 * Free all receive software resources
546 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
548 i40evf_clean_rx_ring(rx_ring);
549 kfree(rx_ring->rx_bi);
550 rx_ring->rx_bi = NULL;
553 dma_free_coherent(rx_ring->dev, rx_ring->size,
554 rx_ring->desc, rx_ring->dma);
555 rx_ring->desc = NULL;
560 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
561 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
563 * Returns 0 on success, negative on failure
565 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
567 struct device *dev = rx_ring->dev;
570 /* warn if we are about to overwrite the pointer */
571 WARN_ON(rx_ring->rx_bi);
572 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
573 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
577 u64_stats_init(&rx_ring->syncp);
579 /* Round up to nearest 4K */
580 rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc);
581 rx_ring->size = ALIGN(rx_ring->size, 4096);
582 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
583 &rx_ring->dma, GFP_KERNEL);
585 if (!rx_ring->desc) {
586 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
591 rx_ring->next_to_alloc = 0;
592 rx_ring->next_to_clean = 0;
593 rx_ring->next_to_use = 0;
597 kfree(rx_ring->rx_bi);
598 rx_ring->rx_bi = NULL;
603 * i40e_release_rx_desc - Store the new tail and head values
604 * @rx_ring: ring to bump
605 * @val: new head index
607 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
609 rx_ring->next_to_use = val;
611 /* update next to alloc since we have filled the ring */
612 rx_ring->next_to_alloc = val;
614 /* Force memory writes to complete before letting h/w
615 * know there are new descriptors to fetch. (Only
616 * applicable for weak-ordered memory model archs,
620 writel(val, rx_ring->tail);
624 * i40e_rx_offset - Return expected offset into page to access data
625 * @rx_ring: Ring we are requesting offset of
627 * Returns the offset value for ring into the data buffer.
629 static inline unsigned int i40e_rx_offset(struct i40e_ring *rx_ring)
631 return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0;
635 * i40e_alloc_mapped_page - recycle or make a new page
636 * @rx_ring: ring to use
637 * @bi: rx_buffer struct to modify
639 * Returns true if the page was successfully allocated or
642 static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
643 struct i40e_rx_buffer *bi)
645 struct page *page = bi->page;
648 /* since we are recycling buffers we should seldom need to alloc */
650 rx_ring->rx_stats.page_reuse_count++;
654 /* alloc new page for storage */
655 page = dev_alloc_pages(i40e_rx_pg_order(rx_ring));
656 if (unlikely(!page)) {
657 rx_ring->rx_stats.alloc_page_failed++;
661 /* map page for use */
662 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
663 i40e_rx_pg_size(rx_ring),
667 /* if mapping failed free memory back to system since
668 * there isn't much point in holding memory we can't use
670 if (dma_mapping_error(rx_ring->dev, dma)) {
671 __free_pages(page, i40e_rx_pg_order(rx_ring));
672 rx_ring->rx_stats.alloc_page_failed++;
678 bi->page_offset = i40e_rx_offset(rx_ring);
680 /* initialize pagecnt_bias to 1 representing we fully own page */
681 bi->pagecnt_bias = 1;
687 * i40e_receive_skb - Send a completed packet up the stack
688 * @rx_ring: rx ring in play
689 * @skb: packet to send up
690 * @vlan_tag: vlan tag for packet
692 static void i40e_receive_skb(struct i40e_ring *rx_ring,
693 struct sk_buff *skb, u16 vlan_tag)
695 struct i40e_q_vector *q_vector = rx_ring->q_vector;
697 if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
698 (vlan_tag & VLAN_VID_MASK))
699 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
701 napi_gro_receive(&q_vector->napi, skb);
705 * i40evf_alloc_rx_buffers - Replace used receive buffers
706 * @rx_ring: ring to place buffers on
707 * @cleaned_count: number of buffers to replace
709 * Returns false if all allocations were successful, true if any fail
711 bool i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
713 u16 ntu = rx_ring->next_to_use;
714 union i40e_rx_desc *rx_desc;
715 struct i40e_rx_buffer *bi;
717 /* do nothing if no valid netdev defined */
718 if (!rx_ring->netdev || !cleaned_count)
721 rx_desc = I40E_RX_DESC(rx_ring, ntu);
722 bi = &rx_ring->rx_bi[ntu];
725 if (!i40e_alloc_mapped_page(rx_ring, bi))
728 /* sync the buffer for use by the device */
729 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
734 /* Refresh the desc even if buffer_addrs didn't change
735 * because each write-back erases this info.
737 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
742 if (unlikely(ntu == rx_ring->count)) {
743 rx_desc = I40E_RX_DESC(rx_ring, 0);
748 /* clear the status bits for the next_to_use descriptor */
749 rx_desc->wb.qword1.status_error_len = 0;
752 } while (cleaned_count);
754 if (rx_ring->next_to_use != ntu)
755 i40e_release_rx_desc(rx_ring, ntu);
760 if (rx_ring->next_to_use != ntu)
761 i40e_release_rx_desc(rx_ring, ntu);
763 /* make sure to come back via polling to try again after
770 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
771 * @vsi: the VSI we care about
772 * @skb: skb currently being received and modified
773 * @rx_desc: the receive descriptor
775 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
777 union i40e_rx_desc *rx_desc)
779 struct i40e_rx_ptype_decoded decoded;
780 u32 rx_error, rx_status;
785 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
786 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT;
787 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
788 I40E_RXD_QW1_ERROR_SHIFT;
789 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
790 I40E_RXD_QW1_STATUS_SHIFT;
791 decoded = decode_rx_desc_ptype(ptype);
793 skb->ip_summed = CHECKSUM_NONE;
795 skb_checksum_none_assert(skb);
797 /* Rx csum enabled and ip headers found? */
798 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
801 /* did the hardware decode the packet and checksum? */
802 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
805 /* both known and outer_ip must be set for the below code to work */
806 if (!(decoded.known && decoded.outer_ip))
809 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
810 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
811 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
812 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
815 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
816 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
819 /* likely incorrect csum if alternate IP extension headers found */
821 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
822 /* don't increment checksum err here, non-fatal err */
825 /* there was some L4 error, count error and punt packet to the stack */
826 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
829 /* handle packets that were not able to be checksummed due
830 * to arrival speed, in this case the stack can compute
833 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
836 /* Only report checksum unnecessary for TCP, UDP, or SCTP */
837 switch (decoded.inner_prot) {
838 case I40E_RX_PTYPE_INNER_PROT_TCP:
839 case I40E_RX_PTYPE_INNER_PROT_UDP:
840 case I40E_RX_PTYPE_INNER_PROT_SCTP:
841 skb->ip_summed = CHECKSUM_UNNECESSARY;
850 vsi->back->hw_csum_rx_error++;
854 * i40e_ptype_to_htype - get a hash type
855 * @ptype: the ptype value from the descriptor
857 * Returns a hash type to be used by skb_set_hash
859 static inline int i40e_ptype_to_htype(u8 ptype)
861 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
864 return PKT_HASH_TYPE_NONE;
866 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
867 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
868 return PKT_HASH_TYPE_L4;
869 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
870 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
871 return PKT_HASH_TYPE_L3;
873 return PKT_HASH_TYPE_L2;
877 * i40e_rx_hash - set the hash value in the skb
878 * @ring: descriptor ring
879 * @rx_desc: specific descriptor
881 static inline void i40e_rx_hash(struct i40e_ring *ring,
882 union i40e_rx_desc *rx_desc,
887 const __le64 rss_mask =
888 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
889 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
891 if (!(ring->netdev->features & NETIF_F_RXHASH))
894 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
895 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
896 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
901 * i40evf_process_skb_fields - Populate skb header fields from Rx descriptor
902 * @rx_ring: rx descriptor ring packet is being transacted on
903 * @rx_desc: pointer to the EOP Rx descriptor
904 * @skb: pointer to current skb being populated
905 * @rx_ptype: the packet type decoded by hardware
907 * This function checks the ring, descriptor, and packet information in
908 * order to populate the hash, checksum, VLAN, protocol, and
909 * other fields within the skb.
912 void i40evf_process_skb_fields(struct i40e_ring *rx_ring,
913 union i40e_rx_desc *rx_desc, struct sk_buff *skb,
916 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
918 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);
920 skb_record_rx_queue(skb, rx_ring->queue_index);
922 /* modifies the skb - consumes the enet header */
923 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
927 * i40e_cleanup_headers - Correct empty headers
928 * @rx_ring: rx descriptor ring packet is being transacted on
929 * @skb: pointer to current skb being fixed
931 * Also address the case where we are pulling data in on pages only
932 * and as such no data is present in the skb header.
934 * In addition if skb is not at least 60 bytes we need to pad it so that
935 * it is large enough to qualify as a valid Ethernet frame.
937 * Returns true if an error was encountered and skb was freed.
939 static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb)
941 /* if eth_skb_pad returns an error the skb was freed */
942 if (eth_skb_pad(skb))
949 * i40e_reuse_rx_page - page flip buffer and store it back on the ring
950 * @rx_ring: rx descriptor ring to store buffers on
951 * @old_buff: donor buffer to have page reused
953 * Synchronizes page for reuse by the adapter
955 static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
956 struct i40e_rx_buffer *old_buff)
958 struct i40e_rx_buffer *new_buff;
959 u16 nta = rx_ring->next_to_alloc;
961 new_buff = &rx_ring->rx_bi[nta];
963 /* update, and store next to alloc */
965 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
967 /* transfer page from old buffer to new buffer */
968 new_buff->dma = old_buff->dma;
969 new_buff->page = old_buff->page;
970 new_buff->page_offset = old_buff->page_offset;
971 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
975 * i40e_page_is_reusable - check if any reuse is possible
976 * @page: page struct to check
978 * A page is not reusable if it was allocated under low memory
979 * conditions, or it's not in the same NUMA node as this CPU.
981 static inline bool i40e_page_is_reusable(struct page *page)
983 return (page_to_nid(page) == numa_mem_id()) &&
984 !page_is_pfmemalloc(page);
988 * i40e_can_reuse_rx_page - Determine if this page can be reused by
989 * the adapter for another receive
991 * @rx_buffer: buffer containing the page
993 * If page is reusable, rx_buffer->page_offset is adjusted to point to
994 * an unused region in the page.
996 * For small pages, @truesize will be a constant value, half the size
997 * of the memory at page. We'll attempt to alternate between high and
998 * low halves of the page, with one half ready for use by the hardware
999 * and the other half being consumed by the stack. We use the page
1000 * ref count to determine whether the stack has finished consuming the
1001 * portion of this page that was passed up with a previous packet. If
1002 * the page ref count is >1, we'll assume the "other" half page is
1003 * still busy, and this page cannot be reused.
1005 * For larger pages, @truesize will be the actual space used by the
1006 * received packet (adjusted upward to an even multiple of the cache
1007 * line size). This will advance through the page by the amount
1008 * actually consumed by the received packets while there is still
1009 * space for a buffer. Each region of larger pages will be used at
1010 * most once, after which the page will not be reused.
1012 * In either case, if the page is reusable its refcount is increased.
1014 static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer)
1016 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1017 struct page *page = rx_buffer->page;
1019 /* Is any reuse possible? */
1020 if (unlikely(!i40e_page_is_reusable(page)))
1023 #if (PAGE_SIZE < 8192)
1024 /* if we are only owner of page we can reuse it */
1025 if (unlikely((page_count(page) - pagecnt_bias) > 1))
1028 #define I40E_LAST_OFFSET \
1029 (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048)
1030 if (rx_buffer->page_offset > I40E_LAST_OFFSET)
1034 /* If we have drained the page fragment pool we need to update
1035 * the pagecnt_bias and page count so that we fully restock the
1036 * number of references the driver holds.
1038 if (unlikely(!pagecnt_bias)) {
1039 page_ref_add(page, USHRT_MAX);
1040 rx_buffer->pagecnt_bias = USHRT_MAX;
1047 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff
1048 * @rx_ring: rx descriptor ring to transact packets on
1049 * @rx_buffer: buffer containing page to add
1050 * @skb: sk_buff to place the data into
1051 * @size: packet length from rx_desc
1053 * This function will add the data contained in rx_buffer->page to the skb.
1054 * It will just attach the page as a frag to the skb.
1056 * The function will then update the page offset.
1058 static void i40e_add_rx_frag(struct i40e_ring *rx_ring,
1059 struct i40e_rx_buffer *rx_buffer,
1060 struct sk_buff *skb,
1063 #if (PAGE_SIZE < 8192)
1064 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1066 unsigned int truesize = SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring));
1069 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1070 rx_buffer->page_offset, size, truesize);
1072 /* page is being used so we must update the page offset */
1073 #if (PAGE_SIZE < 8192)
1074 rx_buffer->page_offset ^= truesize;
1076 rx_buffer->page_offset += truesize;
1081 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use
1082 * @rx_ring: rx descriptor ring to transact packets on
1083 * @size: size of buffer to add to skb
1085 * This function will pull an Rx buffer from the ring and synchronize it
1086 * for use by the CPU.
1088 static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring,
1089 const unsigned int size)
1091 struct i40e_rx_buffer *rx_buffer;
1093 rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean];
1094 prefetchw(rx_buffer->page);
1096 /* we are reusing so sync this buffer for CPU use */
1097 dma_sync_single_range_for_cpu(rx_ring->dev,
1099 rx_buffer->page_offset,
1103 /* We have pulled a buffer for use, so decrement pagecnt_bias */
1104 rx_buffer->pagecnt_bias--;
1110 * i40e_construct_skb - Allocate skb and populate it
1111 * @rx_ring: rx descriptor ring to transact packets on
1112 * @rx_buffer: rx buffer to pull data from
1113 * @size: size of buffer to add to skb
1115 * This function allocates an skb. It then populates it with the page
1116 * data from the current receive descriptor, taking care to set up the
1119 static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring,
1120 struct i40e_rx_buffer *rx_buffer,
1124 #if (PAGE_SIZE < 8192)
1125 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1127 unsigned int truesize = SKB_DATA_ALIGN(size);
1129 unsigned int headlen;
1130 struct sk_buff *skb;
1132 /* prefetch first cache line of first page */
1133 va = page_address(rx_buffer->page) + rx_buffer->page_offset;
1135 #if L1_CACHE_BYTES < 128
1136 prefetch(va + L1_CACHE_BYTES);
1139 /* allocate a skb to store the frags */
1140 skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
1142 GFP_ATOMIC | __GFP_NOWARN);
1146 /* Determine available headroom for copy */
1148 if (headlen > I40E_RX_HDR_SIZE)
1149 headlen = eth_get_headlen(va, I40E_RX_HDR_SIZE);
1151 /* align pull length to size of long to optimize memcpy performance */
1152 memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long)));
1154 /* update all of the pointers */
1157 skb_add_rx_frag(skb, 0, rx_buffer->page,
1158 rx_buffer->page_offset + headlen,
1161 /* buffer is used by skb, update page_offset */
1162 #if (PAGE_SIZE < 8192)
1163 rx_buffer->page_offset ^= truesize;
1165 rx_buffer->page_offset += truesize;
1168 /* buffer is unused, reset bias back to rx_buffer */
1169 rx_buffer->pagecnt_bias++;
1176 * i40e_build_skb - Build skb around an existing buffer
1177 * @rx_ring: Rx descriptor ring to transact packets on
1178 * @rx_buffer: Rx buffer to pull data from
1179 * @size: size of buffer to add to skb
1181 * This function builds an skb around an existing Rx buffer, taking care
1182 * to set up the skb correctly and avoid any memcpy overhead.
1184 static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring,
1185 struct i40e_rx_buffer *rx_buffer,
1189 #if (PAGE_SIZE < 8192)
1190 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1192 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1193 SKB_DATA_ALIGN(I40E_SKB_PAD + size);
1195 struct sk_buff *skb;
1197 /* prefetch first cache line of first page */
1198 va = page_address(rx_buffer->page) + rx_buffer->page_offset;
1200 #if L1_CACHE_BYTES < 128
1201 prefetch(va + L1_CACHE_BYTES);
1203 /* build an skb around the page buffer */
1204 skb = build_skb(va - I40E_SKB_PAD, truesize);
1208 /* update pointers within the skb to store the data */
1209 skb_reserve(skb, I40E_SKB_PAD);
1210 __skb_put(skb, size);
1212 /* buffer is used by skb, update page_offset */
1213 #if (PAGE_SIZE < 8192)
1214 rx_buffer->page_offset ^= truesize;
1216 rx_buffer->page_offset += truesize;
1223 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free
1224 * @rx_ring: rx descriptor ring to transact packets on
1225 * @rx_buffer: rx buffer to pull data from
1227 * This function will clean up the contents of the rx_buffer. It will
1228 * either recycle the bufer or unmap it and free the associated resources.
1230 static void i40e_put_rx_buffer(struct i40e_ring *rx_ring,
1231 struct i40e_rx_buffer *rx_buffer)
1233 if (i40e_can_reuse_rx_page(rx_buffer)) {
1234 /* hand second half of page back to the ring */
1235 i40e_reuse_rx_page(rx_ring, rx_buffer);
1236 rx_ring->rx_stats.page_reuse_count++;
1238 /* we are not reusing the buffer so unmap it */
1239 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
1240 i40e_rx_pg_size(rx_ring),
1241 DMA_FROM_DEVICE, I40E_RX_DMA_ATTR);
1242 __page_frag_cache_drain(rx_buffer->page,
1243 rx_buffer->pagecnt_bias);
1246 /* clear contents of buffer_info */
1247 rx_buffer->page = NULL;
1251 * i40e_is_non_eop - process handling of non-EOP buffers
1252 * @rx_ring: Rx ring being processed
1253 * @rx_desc: Rx descriptor for current buffer
1254 * @skb: Current socket buffer containing buffer in progress
1256 * This function updates next to clean. If the buffer is an EOP buffer
1257 * this function exits returning false, otherwise it will place the
1258 * sk_buff in the next buffer to be chained and return true indicating
1259 * that this is in fact a non-EOP buffer.
1261 static bool i40e_is_non_eop(struct i40e_ring *rx_ring,
1262 union i40e_rx_desc *rx_desc,
1263 struct sk_buff *skb)
1265 u32 ntc = rx_ring->next_to_clean + 1;
1267 /* fetch, update, and store next to clean */
1268 ntc = (ntc < rx_ring->count) ? ntc : 0;
1269 rx_ring->next_to_clean = ntc;
1271 prefetch(I40E_RX_DESC(rx_ring, ntc));
1273 /* if we are the last buffer then there is nothing else to do */
1274 #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
1275 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
1278 rx_ring->rx_stats.non_eop_descs++;
1284 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1285 * @rx_ring: rx descriptor ring to transact packets on
1286 * @budget: Total limit on number of packets to process
1288 * This function provides a "bounce buffer" approach to Rx interrupt
1289 * processing. The advantage to this is that on systems that have
1290 * expensive overhead for IOMMU access this provides a means of avoiding
1291 * it by maintaining the mapping of the page to the system.
1293 * Returns amount of work completed
1295 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
1297 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1298 struct sk_buff *skb = rx_ring->skb;
1299 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1300 bool failure = false;
1302 while (likely(total_rx_packets < (unsigned int)budget)) {
1303 struct i40e_rx_buffer *rx_buffer;
1304 union i40e_rx_desc *rx_desc;
1310 /* return some buffers to hardware, one at a time is too slow */
1311 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1312 failure = failure ||
1313 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
1317 rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);
1319 /* status_error_len will always be zero for unused descriptors
1320 * because it's cleared in cleanup, and overlaps with hdr_addr
1321 * which is always zero because packet split isn't used, if the
1322 * hardware wrote DD then the length will be non-zero
1324 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1326 /* This memory barrier is needed to keep us from reading
1327 * any other fields out of the rx_desc until we have
1328 * verified the descriptor has been written back.
1332 size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1333 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1337 i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb);
1338 rx_buffer = i40e_get_rx_buffer(rx_ring, size);
1340 /* retrieve a buffer from the ring */
1342 i40e_add_rx_frag(rx_ring, rx_buffer, skb, size);
1343 else if (ring_uses_build_skb(rx_ring))
1344 skb = i40e_build_skb(rx_ring, rx_buffer, size);
1346 skb = i40e_construct_skb(rx_ring, rx_buffer, size);
1348 /* exit if we failed to retrieve a buffer */
1350 rx_ring->rx_stats.alloc_buff_failed++;
1351 rx_buffer->pagecnt_bias++;
1355 i40e_put_rx_buffer(rx_ring, rx_buffer);
1358 if (i40e_is_non_eop(rx_ring, rx_desc, skb))
1361 /* ERR_MASK will only have valid bits if EOP set, and
1362 * what we are doing here is actually checking
1363 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1366 if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
1367 dev_kfree_skb_any(skb);
1372 if (i40e_cleanup_headers(rx_ring, skb)) {
1377 /* probably a little skewed due to removing CRC */
1378 total_rx_bytes += skb->len;
1380 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1381 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1382 I40E_RXD_QW1_PTYPE_SHIFT;
1384 /* populate checksum, VLAN, and protocol */
1385 i40evf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);
1388 vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1389 le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0;
1391 i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);
1392 i40e_receive_skb(rx_ring, skb, vlan_tag);
1395 /* update budget accounting */
1401 u64_stats_update_begin(&rx_ring->syncp);
1402 rx_ring->stats.packets += total_rx_packets;
1403 rx_ring->stats.bytes += total_rx_bytes;
1404 u64_stats_update_end(&rx_ring->syncp);
1405 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1406 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1408 /* guarantee a trip back through this routine if there was a failure */
1409 return failure ? budget : (int)total_rx_packets;
1412 static u32 i40e_buildreg_itr(const int type, const u16 itr)
1416 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1417 /* Don't clear PBA because that can cause lost interrupts that
1418 * came in while we were cleaning/polling
1420 (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1421 (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1426 /* a small macro to shorten up some long lines */
1427 #define INTREG I40E_VFINT_DYN_CTLN1
1428 static inline int get_rx_itr(struct i40e_vsi *vsi, int idx)
1430 struct i40evf_adapter *adapter = vsi->back;
1432 return adapter->rx_rings[idx].rx_itr_setting;
1435 static inline int get_tx_itr(struct i40e_vsi *vsi, int idx)
1437 struct i40evf_adapter *adapter = vsi->back;
1439 return adapter->tx_rings[idx].tx_itr_setting;
1443 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1444 * @vsi: the VSI we care about
1445 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1448 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1449 struct i40e_q_vector *q_vector)
1451 struct i40e_hw *hw = &vsi->back->hw;
1452 bool rx = false, tx = false;
1455 int idx = q_vector->v_idx;
1456 int rx_itr_setting, tx_itr_setting;
1458 vector = (q_vector->v_idx + vsi->base_vector);
1460 /* avoid dynamic calculation if in countdown mode OR if
1461 * all dynamic is disabled
1463 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1465 rx_itr_setting = get_rx_itr(vsi, idx);
1466 tx_itr_setting = get_tx_itr(vsi, idx);
1468 if (q_vector->itr_countdown > 0 ||
1469 (!ITR_IS_DYNAMIC(rx_itr_setting) &&
1470 !ITR_IS_DYNAMIC(tx_itr_setting))) {
1474 if (ITR_IS_DYNAMIC(rx_itr_setting)) {
1475 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1476 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1479 if (ITR_IS_DYNAMIC(tx_itr_setting)) {
1480 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1481 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1485 /* get the higher of the two ITR adjustments and
1486 * use the same value for both ITR registers
1487 * when in adaptive mode (Rx and/or Tx)
1489 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1491 q_vector->tx.itr = q_vector->rx.itr = itr;
1492 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1494 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1498 /* only need to enable the interrupt once, but need
1499 * to possibly update both ITR values
1502 /* set the INTENA_MSK_MASK so that this first write
1503 * won't actually enable the interrupt, instead just
1504 * updating the ITR (it's bit 31 PF and VF)
1507 /* don't check _DOWN because interrupt isn't being enabled */
1508 wr32(hw, INTREG(vector - 1), rxval);
1512 if (!test_bit(__I40E_VSI_DOWN, vsi->state))
1513 wr32(hw, INTREG(vector - 1), txval);
1515 if (q_vector->itr_countdown)
1516 q_vector->itr_countdown--;
1518 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1522 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1523 * @napi: napi struct with our devices info in it
1524 * @budget: amount of work driver is allowed to do this pass, in packets
1526 * This function will clean all queues associated with a q_vector.
1528 * Returns the amount of work done
1530 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1532 struct i40e_q_vector *q_vector =
1533 container_of(napi, struct i40e_q_vector, napi);
1534 struct i40e_vsi *vsi = q_vector->vsi;
1535 struct i40e_ring *ring;
1536 bool clean_complete = true;
1537 bool arm_wb = false;
1538 int budget_per_ring;
1541 if (test_bit(__I40E_VSI_DOWN, vsi->state)) {
1542 napi_complete(napi);
1546 /* Since the actual Tx work is minimal, we can give the Tx a larger
1547 * budget and be more aggressive about cleaning up the Tx descriptors.
1549 i40e_for_each_ring(ring, q_vector->tx) {
1550 if (!i40e_clean_tx_irq(vsi, ring, budget)) {
1551 clean_complete = false;
1554 arm_wb |= ring->arm_wb;
1555 ring->arm_wb = false;
1558 /* Handle case where we are called by netpoll with a budget of 0 */
1562 /* We attempt to distribute budget to each Rx queue fairly, but don't
1563 * allow the budget to go below 1 because that would exit polling early.
1565 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1567 i40e_for_each_ring(ring, q_vector->rx) {
1568 int cleaned = i40e_clean_rx_irq(ring, budget_per_ring);
1570 work_done += cleaned;
1571 /* if we clean as many as budgeted, we must not be done */
1572 if (cleaned >= budget_per_ring)
1573 clean_complete = false;
1576 /* If work not completed, return budget and polling will return */
1577 if (!clean_complete) {
1578 int cpu_id = smp_processor_id();
1580 /* It is possible that the interrupt affinity has changed but,
1581 * if the cpu is pegged at 100%, polling will never exit while
1582 * traffic continues and the interrupt will be stuck on this
1583 * cpu. We check to make sure affinity is correct before we
1584 * continue to poll, otherwise we must stop polling so the
1585 * interrupt can move to the correct cpu.
1587 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) {
1588 /* Tell napi that we are done polling */
1589 napi_complete_done(napi, work_done);
1591 /* Force an interrupt */
1592 i40evf_force_wb(vsi, q_vector);
1594 /* Return budget-1 so that polling stops */
1599 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1600 i40e_enable_wb_on_itr(vsi, q_vector);
1605 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1606 q_vector->arm_wb_state = false;
1608 /* Work is done so exit the polling mode and re-enable the interrupt */
1609 napi_complete_done(napi, work_done);
1611 i40e_update_enable_itr(vsi, q_vector);
1613 return min(work_done, budget - 1);
1617 * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1619 * @tx_ring: ring to send buffer on
1620 * @flags: the tx flags to be set
1622 * Checks the skb and set up correspondingly several generic transmit flags
1623 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1625 * Returns error code indicate the frame should be dropped upon error and the
1626 * otherwise returns 0 to indicate the flags has been set properly.
1628 static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1629 struct i40e_ring *tx_ring,
1632 __be16 protocol = skb->protocol;
1635 if (protocol == htons(ETH_P_8021Q) &&
1636 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1637 /* When HW VLAN acceleration is turned off by the user the
1638 * stack sets the protocol to 8021q so that the driver
1639 * can take any steps required to support the SW only
1640 * VLAN handling. In our case the driver doesn't need
1641 * to take any further steps so just set the protocol
1642 * to the encapsulated ethertype.
1644 skb->protocol = vlan_get_protocol(skb);
1648 /* if we have a HW VLAN tag being added, default to the HW one */
1649 if (skb_vlan_tag_present(skb)) {
1650 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1651 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1652 /* else if it is a SW VLAN, check the next protocol and store the tag */
1653 } else if (protocol == htons(ETH_P_8021Q)) {
1654 struct vlan_hdr *vhdr, _vhdr;
1656 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1660 protocol = vhdr->h_vlan_encapsulated_proto;
1661 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1662 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1671 * i40e_tso - set up the tso context descriptor
1672 * @first: pointer to first Tx buffer for xmit
1673 * @hdr_len: ptr to the size of the packet header
1674 * @cd_type_cmd_tso_mss: Quad Word 1
1676 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1678 static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len,
1679 u64 *cd_type_cmd_tso_mss)
1681 struct sk_buff *skb = first->skb;
1682 u64 cd_cmd, cd_tso_len, cd_mss;
1693 u32 paylen, l4_offset;
1694 u16 gso_segs, gso_size;
1697 if (skb->ip_summed != CHECKSUM_PARTIAL)
1700 if (!skb_is_gso(skb))
1703 err = skb_cow_head(skb, 0);
1707 ip.hdr = skb_network_header(skb);
1708 l4.hdr = skb_transport_header(skb);
1710 /* initialize outer IP header fields */
1711 if (ip.v4->version == 4) {
1715 ip.v6->payload_len = 0;
1718 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1722 SKB_GSO_UDP_TUNNEL |
1723 SKB_GSO_UDP_TUNNEL_CSUM)) {
1724 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
1725 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
1728 /* determine offset of outer transport header */
1729 l4_offset = l4.hdr - skb->data;
1731 /* remove payload length from outer checksum */
1732 paylen = skb->len - l4_offset;
1733 csum_replace_by_diff(&l4.udp->check,
1734 (__force __wsum)htonl(paylen));
1737 /* reset pointers to inner headers */
1738 ip.hdr = skb_inner_network_header(skb);
1739 l4.hdr = skb_inner_transport_header(skb);
1741 /* initialize inner IP header fields */
1742 if (ip.v4->version == 4) {
1746 ip.v6->payload_len = 0;
1750 /* determine offset of inner transport header */
1751 l4_offset = l4.hdr - skb->data;
1753 /* remove payload length from inner checksum */
1754 paylen = skb->len - l4_offset;
1755 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
1757 /* compute length of segmentation header */
1758 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
1760 /* pull values out of skb_shinfo */
1761 gso_size = skb_shinfo(skb)->gso_size;
1762 gso_segs = skb_shinfo(skb)->gso_segs;
1764 /* update GSO size and bytecount with header size */
1765 first->gso_segs = gso_segs;
1766 first->bytecount += (first->gso_segs - 1) * *hdr_len;
1768 /* find the field values */
1769 cd_cmd = I40E_TX_CTX_DESC_TSO;
1770 cd_tso_len = skb->len - *hdr_len;
1772 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1773 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1774 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1779 * i40e_tx_enable_csum - Enable Tx checksum offloads
1781 * @tx_flags: pointer to Tx flags currently set
1782 * @td_cmd: Tx descriptor command bits to set
1783 * @td_offset: Tx descriptor header offsets to set
1784 * @tx_ring: Tx descriptor ring
1785 * @cd_tunneling: ptr to context desc bits
1787 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1788 u32 *td_cmd, u32 *td_offset,
1789 struct i40e_ring *tx_ring,
1802 unsigned char *exthdr;
1803 u32 offset, cmd = 0;
1807 if (skb->ip_summed != CHECKSUM_PARTIAL)
1810 ip.hdr = skb_network_header(skb);
1811 l4.hdr = skb_transport_header(skb);
1813 /* compute outer L2 header size */
1814 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1816 if (skb->encapsulation) {
1818 /* define outer network header type */
1819 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1820 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
1821 I40E_TX_CTX_EXT_IP_IPV4 :
1822 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1824 l4_proto = ip.v4->protocol;
1825 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1826 tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
1828 exthdr = ip.hdr + sizeof(*ip.v6);
1829 l4_proto = ip.v6->nexthdr;
1830 if (l4.hdr != exthdr)
1831 ipv6_skip_exthdr(skb, exthdr - skb->data,
1832 &l4_proto, &frag_off);
1835 /* define outer transport */
1838 tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
1839 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1842 tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
1843 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1847 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1848 l4.hdr = skb_inner_network_header(skb);
1851 if (*tx_flags & I40E_TX_FLAGS_TSO)
1854 skb_checksum_help(skb);
1858 /* compute outer L3 header size */
1859 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
1860 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
1862 /* switch IP header pointer from outer to inner header */
1863 ip.hdr = skb_inner_network_header(skb);
1865 /* compute tunnel header size */
1866 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
1867 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1869 /* indicate if we need to offload outer UDP header */
1870 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
1871 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
1872 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
1873 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1875 /* record tunnel offload values */
1876 *cd_tunneling |= tunnel;
1878 /* switch L4 header pointer from outer to inner */
1879 l4.hdr = skb_inner_transport_header(skb);
1882 /* reset type as we transition from outer to inner headers */
1883 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
1884 if (ip.v4->version == 4)
1885 *tx_flags |= I40E_TX_FLAGS_IPV4;
1886 if (ip.v6->version == 6)
1887 *tx_flags |= I40E_TX_FLAGS_IPV6;
1890 /* Enable IP checksum offloads */
1891 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1892 l4_proto = ip.v4->protocol;
1893 /* the stack computes the IP header already, the only time we
1894 * need the hardware to recompute it is in the case of TSO.
1896 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
1897 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
1898 I40E_TX_DESC_CMD_IIPT_IPV4;
1899 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1900 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1902 exthdr = ip.hdr + sizeof(*ip.v6);
1903 l4_proto = ip.v6->nexthdr;
1904 if (l4.hdr != exthdr)
1905 ipv6_skip_exthdr(skb, exthdr - skb->data,
1906 &l4_proto, &frag_off);
1909 /* compute inner L3 header size */
1910 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1912 /* Enable L4 checksum offloads */
1915 /* enable checksum offloads */
1916 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1917 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1920 /* enable SCTP checksum offload */
1921 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1922 offset |= (sizeof(struct sctphdr) >> 2) <<
1923 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1926 /* enable UDP checksum offload */
1927 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1928 offset |= (sizeof(struct udphdr) >> 2) <<
1929 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1932 if (*tx_flags & I40E_TX_FLAGS_TSO)
1934 skb_checksum_help(skb);
1939 *td_offset |= offset;
1945 * i40e_create_tx_ctx Build the Tx context descriptor
1946 * @tx_ring: ring to create the descriptor on
1947 * @cd_type_cmd_tso_mss: Quad Word 1
1948 * @cd_tunneling: Quad Word 0 - bits 0-31
1949 * @cd_l2tag2: Quad Word 0 - bits 32-63
1951 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1952 const u64 cd_type_cmd_tso_mss,
1953 const u32 cd_tunneling, const u32 cd_l2tag2)
1955 struct i40e_tx_context_desc *context_desc;
1956 int i = tx_ring->next_to_use;
1958 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1959 !cd_tunneling && !cd_l2tag2)
1962 /* grab the next descriptor */
1963 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1966 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1968 /* cpu_to_le32 and assign to struct fields */
1969 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1970 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1971 context_desc->rsvd = cpu_to_le16(0);
1972 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1976 * __i40evf_chk_linearize - Check if there are more than 8 buffers per packet
1979 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
1980 * and so we need to figure out the cases where we need to linearize the skb.
1982 * For TSO we need to count the TSO header and segment payload separately.
1983 * As such we need to check cases where we have 7 fragments or more as we
1984 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
1985 * the segment payload in the first descriptor, and another 7 for the
1988 bool __i40evf_chk_linearize(struct sk_buff *skb)
1990 const struct skb_frag_struct *frag, *stale;
1993 /* no need to check if number of frags is less than 7 */
1994 nr_frags = skb_shinfo(skb)->nr_frags;
1995 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
1998 /* We need to walk through the list and validate that each group
1999 * of 6 fragments totals at least gso_size.
2001 nr_frags -= I40E_MAX_BUFFER_TXD - 2;
2002 frag = &skb_shinfo(skb)->frags[0];
2004 /* Initialize size to the negative value of gso_size minus 1. We
2005 * use this as the worst case scenerio in which the frag ahead
2006 * of us only provides one byte which is why we are limited to 6
2007 * descriptors for a single transmit as the header and previous
2008 * fragment are already consuming 2 descriptors.
2010 sum = 1 - skb_shinfo(skb)->gso_size;
2012 /* Add size of frags 0 through 4 to create our initial sum */
2013 sum += skb_frag_size(frag++);
2014 sum += skb_frag_size(frag++);
2015 sum += skb_frag_size(frag++);
2016 sum += skb_frag_size(frag++);
2017 sum += skb_frag_size(frag++);
2019 /* Walk through fragments adding latest fragment, testing it, and
2020 * then removing stale fragments from the sum.
2022 for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
2023 int stale_size = skb_frag_size(stale);
2025 sum += skb_frag_size(frag++);
2027 /* The stale fragment may present us with a smaller
2028 * descriptor than the actual fragment size. To account
2029 * for that we need to remove all the data on the front and
2030 * figure out what the remainder would be in the last
2031 * descriptor associated with the fragment.
2033 if (stale_size > I40E_MAX_DATA_PER_TXD) {
2034 int align_pad = -(stale->page_offset) &
2035 (I40E_MAX_READ_REQ_SIZE - 1);
2038 stale_size -= align_pad;
2041 sum -= I40E_MAX_DATA_PER_TXD_ALIGNED;
2042 stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED;
2043 } while (stale_size > I40E_MAX_DATA_PER_TXD);
2046 /* if sum is negative we failed to make sufficient progress */
2060 * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
2061 * @tx_ring: the ring to be checked
2062 * @size: the size buffer we want to assure is available
2064 * Returns -EBUSY if a stop is needed, else 0
2066 int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2068 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2069 /* Memory barrier before checking head and tail */
2072 /* Check again in a case another CPU has just made room available. */
2073 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
2076 /* A reprieve! - use start_queue because it doesn't call schedule */
2077 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2078 ++tx_ring->tx_stats.restart_queue;
2083 * i40evf_tx_map - Build the Tx descriptor
2084 * @tx_ring: ring to send buffer on
2086 * @first: first buffer info buffer to use
2087 * @tx_flags: collected send information
2088 * @hdr_len: size of the packet header
2089 * @td_cmd: the command field in the descriptor
2090 * @td_offset: offset for checksum or crc
2092 static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2093 struct i40e_tx_buffer *first, u32 tx_flags,
2094 const u8 hdr_len, u32 td_cmd, u32 td_offset)
2096 unsigned int data_len = skb->data_len;
2097 unsigned int size = skb_headlen(skb);
2098 struct skb_frag_struct *frag;
2099 struct i40e_tx_buffer *tx_bi;
2100 struct i40e_tx_desc *tx_desc;
2101 u16 i = tx_ring->next_to_use;
2105 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
2106 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
2107 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
2108 I40E_TX_FLAGS_VLAN_SHIFT;
2111 first->tx_flags = tx_flags;
2113 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2115 tx_desc = I40E_TX_DESC(tx_ring, i);
2118 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2119 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
2121 if (dma_mapping_error(tx_ring->dev, dma))
2124 /* record length, and DMA address */
2125 dma_unmap_len_set(tx_bi, len, size);
2126 dma_unmap_addr_set(tx_bi, dma, dma);
2128 /* align size to end of page */
2129 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
2130 tx_desc->buffer_addr = cpu_to_le64(dma);
2132 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
2133 tx_desc->cmd_type_offset_bsz =
2134 build_ctob(td_cmd, td_offset,
2140 if (i == tx_ring->count) {
2141 tx_desc = I40E_TX_DESC(tx_ring, 0);
2148 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
2149 tx_desc->buffer_addr = cpu_to_le64(dma);
2152 if (likely(!data_len))
2155 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2161 if (i == tx_ring->count) {
2162 tx_desc = I40E_TX_DESC(tx_ring, 0);
2166 size = skb_frag_size(frag);
2169 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2172 tx_bi = &tx_ring->tx_bi[i];
2175 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
2178 if (i == tx_ring->count)
2181 tx_ring->next_to_use = i;
2183 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
2185 /* write last descriptor with RS and EOP bits */
2186 td_cmd |= I40E_TXD_CMD;
2187 tx_desc->cmd_type_offset_bsz =
2188 build_ctob(td_cmd, td_offset, size, td_tag);
2190 /* Force memory writes to complete before letting h/w know there
2191 * are new descriptors to fetch.
2193 * We also use this memory barrier to make certain all of the
2194 * status bits have been updated before next_to_watch is written.
2198 /* set next_to_watch value indicating a packet is present */
2199 first->next_to_watch = tx_desc;
2201 /* notify HW of packet */
2202 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
2203 writel(i, tx_ring->tail);
2205 /* we need this if more than one processor can write to our tail
2206 * at a time, it synchronizes IO on IA64/Altix systems
2214 dev_info(tx_ring->dev, "TX DMA map failed\n");
2216 /* clear dma mappings for failed tx_bi map */
2218 tx_bi = &tx_ring->tx_bi[i];
2219 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2227 tx_ring->next_to_use = i;
2231 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2233 * @tx_ring: ring to send buffer on
2235 * Returns NETDEV_TX_OK if sent, else an error code
2237 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2238 struct i40e_ring *tx_ring)
2240 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2241 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2242 struct i40e_tx_buffer *first;
2250 /* prefetch the data, we'll need it later */
2251 prefetch(skb->data);
2253 i40e_trace(xmit_frame_ring, skb, tx_ring);
2255 count = i40e_xmit_descriptor_count(skb);
2256 if (i40e_chk_linearize(skb, count)) {
2257 if (__skb_linearize(skb)) {
2258 dev_kfree_skb_any(skb);
2259 return NETDEV_TX_OK;
2261 count = i40e_txd_use_count(skb->len);
2262 tx_ring->tx_stats.tx_linearize++;
2265 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2266 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2267 * + 4 desc gap to avoid the cache line where head is,
2268 * + 1 desc for context descriptor,
2269 * otherwise try next time
2271 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2272 tx_ring->tx_stats.tx_busy++;
2273 return NETDEV_TX_BUSY;
2276 /* record the location of the first descriptor for this packet */
2277 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2279 first->bytecount = skb->len;
2280 first->gso_segs = 1;
2282 /* prepare the xmit flags */
2283 if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2286 /* obtain protocol of skb */
2287 protocol = vlan_get_protocol(skb);
2289 /* setup IPv4/IPv6 offloads */
2290 if (protocol == htons(ETH_P_IP))
2291 tx_flags |= I40E_TX_FLAGS_IPV4;
2292 else if (protocol == htons(ETH_P_IPV6))
2293 tx_flags |= I40E_TX_FLAGS_IPV6;
2295 tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
2300 tx_flags |= I40E_TX_FLAGS_TSO;
2302 /* Always offload the checksum, since it's in the data descriptor */
2303 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2304 tx_ring, &cd_tunneling);
2308 skb_tx_timestamp(skb);
2310 /* always enable CRC insertion offload */
2311 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2313 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2314 cd_tunneling, cd_l2tag2);
2316 i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2319 return NETDEV_TX_OK;
2322 i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring);
2323 dev_kfree_skb_any(first->skb);
2325 return NETDEV_TX_OK;
2329 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2331 * @netdev: network interface device structure
2333 * Returns NETDEV_TX_OK if sent, else an error code
2335 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2337 struct i40evf_adapter *adapter = netdev_priv(netdev);
2338 struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
2340 /* hardware can't handle really short frames, hardware padding works
2343 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2344 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2345 return NETDEV_TX_OK;
2346 skb->len = I40E_MIN_TX_LEN;
2347 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2350 return i40e_xmit_frame_ring(skb, tx_ring);