drivers/net/ethernet/intel/i40e/i40e_type.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
   3
   4 #ifndef _I40E_TYPE_H_
   5 #define _I40E_TYPE_H_
   6
   7 #include <uapi/linux/if_ether.h>
   8 #include "i40e_adminq.h"
   9 #include "i40e_hmc.h"
  10
  11 #define I40E_MAX_VSI_QP                 16
  12 #define I40E_MAX_VF_VSI                 4
  13 #define I40E_MAX_CHAINED_RX_BUFFERS     5
  14 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS   16
  15
  16 /* Max default timeout in ms, */
  17 #define I40E_MAX_NVM_TIMEOUT            18000
  18
  19 /* Max timeout in ms for the phy to respond */
  20 #define I40E_MAX_PHY_TIMEOUT            500
  21
  22 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  23 #define I40E_MS_TO_GTIME(time)          ((time) * 1000)
  24
  25 /* forward declaration */
  26 struct i40e_hw;
  27 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
  28
  29 /* Data type manipulation macros. */
  30
  31 #define I40E_DESC_UNUSED(R)     \
  32         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  33         (R)->next_to_clean - (R)->next_to_use - 1)
  34
  35 /* bitfields for Tx queue mapping in QTX_CTL */
  36 #define I40E_QTX_CTL_VF_QUEUE   0x0
  37 #define I40E_QTX_CTL_VM_QUEUE   0x1
  38 #define I40E_QTX_CTL_PF_QUEUE   0x2
  39
  40 #define I40E_MDIO_CLAUSE22_STCODE_MASK          I40E_GLGEN_MSCA_STCODE_MASK(1)
  41 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK    I40E_GLGEN_MSCA_OPCODE_MASK(1)
  42 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK     I40E_GLGEN_MSCA_OPCODE_MASK(2)
  43
  44 #define I40E_MDIO_CLAUSE45_STCODE_MASK          I40E_GLGEN_MSCA_STCODE_MASK(0)
  45 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  I40E_GLGEN_MSCA_OPCODE_MASK(0)
  46 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK    I40E_GLGEN_MSCA_OPCODE_MASK(1)
  47 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK     I40E_GLGEN_MSCA_OPCODE_MASK(3)
  48
  49 #define I40E_PHY_COM_REG_PAGE                   0x1E
  50 #define I40E_PHY_LED_LINK_MODE_MASK             0xF0
  51 #define I40E_PHY_LED_MANUAL_ON                  0x100
  52 #define I40E_PHY_LED_PROV_REG_1                 0xC430
  53 #define I40E_PHY_LED_MODE_MASK                  0xFFFF
  54 #define I40E_PHY_LED_MODE_ORIG                  0x80000000
  55
  56 /* These are structs for managing the hardware information and the operations.
  57  * The structures of function pointers are filled out at init time when we
  58  * know for sure exactly which hardware we're working with.  This gives us the
  59  * flexibility of using the same main driver code but adapting to slightly
  60  * different hardware needs as new parts are developed.  For this architecture,
  61  * the Firmware and AdminQ are intended to insulate the driver from most of the
  62  * future changes, but these structures will also do part of the job.
  63  */
  64 enum i40e_mac_type {
  65         I40E_MAC_UNKNOWN = 0,
  66         I40E_MAC_XL710,
  67         I40E_MAC_X722,
  68         I40E_MAC_GENERIC,
  69 };
  70
  71 enum i40e_media_type {
  72         I40E_MEDIA_TYPE_UNKNOWN = 0,
  73         I40E_MEDIA_TYPE_FIBER,
  74         I40E_MEDIA_TYPE_BASET,
  75         I40E_MEDIA_TYPE_BACKPLANE,
  76         I40E_MEDIA_TYPE_CX4,
  77         I40E_MEDIA_TYPE_DA,
  78         I40E_MEDIA_TYPE_VIRTUAL
  79 };
  80
  81 enum i40e_fc_mode {
  82         I40E_FC_NONE = 0,
  83         I40E_FC_RX_PAUSE,
  84         I40E_FC_TX_PAUSE,
  85         I40E_FC_FULL,
  86         I40E_FC_PFC,
  87         I40E_FC_DEFAULT
  88 };
  89
  90 enum i40e_set_fc_aq_failures {
  91         I40E_SET_FC_AQ_FAIL_NONE = 0,
  92         I40E_SET_FC_AQ_FAIL_GET = 1,
  93         I40E_SET_FC_AQ_FAIL_SET = 2,
  94         I40E_SET_FC_AQ_FAIL_UPDATE = 4,
  95         I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
  96 };
  97
  98 enum i40e_vsi_type {
  99         I40E_VSI_MAIN   = 0,
 100         I40E_VSI_VMDQ1  = 1,
 101         I40E_VSI_VMDQ2  = 2,
 102         I40E_VSI_CTRL   = 3,
 103         I40E_VSI_FCOE   = 4,
 104         I40E_VSI_MIRROR = 5,
 105         I40E_VSI_SRIOV  = 6,
 106         I40E_VSI_FDIR   = 7,
 107         I40E_VSI_IWARP  = 8,
 108         I40E_VSI_TYPE_UNKNOWN
 109 };
 110
 111 enum i40e_queue_type {
 112         I40E_QUEUE_TYPE_RX = 0,
 113         I40E_QUEUE_TYPE_TX,
 114         I40E_QUEUE_TYPE_PE_CEQ,
 115         I40E_QUEUE_TYPE_UNKNOWN
 116 };
 117
 118 struct i40e_link_status {
 119         enum i40e_aq_phy_type phy_type;
 120         enum i40e_aq_link_speed link_speed;
 121         u8 link_info;
 122         u8 an_info;
 123         u8 req_fec_info;
 124         u8 fec_info;
 125         u8 ext_info;
 126         u8 loopback;
 127         /* is Link Status Event notification to SW enabled */
 128         bool lse_enable;
 129         u16 max_frame_size;
 130         bool crc_enable;
 131         u8 pacing;
 132         u8 requested_speeds;
 133         u8 module_type[3];
 134         /* 1st byte: module identifier */
 135 #define I40E_MODULE_TYPE_SFP            0x03
 136         /* 3rd byte: ethernet compliance codes for 1G */
 137 #define I40E_MODULE_TYPE_1000BASE_SX    0x01
 138 #define I40E_MODULE_TYPE_1000BASE_LX    0x02
 139 };
 140
 141 struct i40e_phy_info {
 142         struct i40e_link_status link_info;
 143         struct i40e_link_status link_info_old;
 144         bool get_link_info;
 145         enum i40e_media_type media_type;
 146         /* all the phy types the NVM is capable of */
 147         u64 phy_types;
 148 };
 149
 150 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
 151 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
 152 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
 153 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
 154 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
 155 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
 156 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
 157 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
 158 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
 159 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
 160 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
 161 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
 162 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
 163 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
 164 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
 165 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
 166 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
 167 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
 168 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
 169 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
 170 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
 171 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
 172 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
 173 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
 174 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
 175 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
 176 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 177                                 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
 178 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
 179 /* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
 180  * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
 181  * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
 182  * a shift is needed to adjust for this with values larger than 31. The
 183  * only affected values are I40E_PHY_TYPE_25GBASE_*.
 184  */
 185 #define I40E_PHY_TYPE_OFFSET 1
 186 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
 187                                              I40E_PHY_TYPE_OFFSET)
 188 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
 189                                              I40E_PHY_TYPE_OFFSET)
 190 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
 191                                              I40E_PHY_TYPE_OFFSET)
 192 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
 193                                              I40E_PHY_TYPE_OFFSET)
 194 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
 195                                              I40E_PHY_TYPE_OFFSET)
 196 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
 197                                              I40E_PHY_TYPE_OFFSET)
 198 /* Offset for 2.5G/5G PHY Types value to bit number conversion */
 199 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T)
 200 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T)
 201 #define I40E_HW_CAP_MAX_GPIO                    30
 202 /* Capabilities of a PF or a VF or the whole device */
 203 struct i40e_hw_capabilities {
 204         u32  switch_mode;
 205
 206         /* Cloud filter modes:
 207          * Mode1: Filter on L4 port only
 208          * Mode2: Filter for non-tunneled traffic
 209          * Mode3: Filter for tunnel traffic
 210          */
 211 #define I40E_CLOUD_FILTER_MODE1 0x6
 212 #define I40E_CLOUD_FILTER_MODE2 0x7
 213 #define I40E_SWITCH_MODE_MASK   0xF
 214
 215         u32  management_mode;
 216         u32  mng_protocols_over_mctp;
 217         u32  npar_enable;
 218         u32  os2bmc;
 219         u32  valid_functions;
 220         bool sr_iov_1_1;
 221         bool vmdq;
 222         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 223         bool evb_802_1_qbh; /* Bridge Port Extension */
 224         bool dcb;
 225         bool fcoe;
 226         bool iscsi; /* Indicates iSCSI enabled */
 227         bool flex10_enable;
 228         bool flex10_capable;
 229         u32  flex10_mode;
 230
 231         u32 flex10_status;
 232
 233         bool sec_rev_disabled;
 234         bool update_disabled;
 235 #define I40E_NVM_MGMT_SEC_REV_DISABLED  0x1
 236 #define I40E_NVM_MGMT_UPDATE_DISABLED   0x2
 237
 238         bool mgmt_cem;
 239         bool ieee_1588;
 240         bool iwarp;
 241         bool fd;
 242         u32 fd_filters_guaranteed;
 243         u32 fd_filters_best_effort;
 244         bool rss;
 245         u32 rss_table_size;
 246         u32 rss_table_entry_width;
 247         bool led[I40E_HW_CAP_MAX_GPIO];
 248         bool sdp[I40E_HW_CAP_MAX_GPIO];
 249         u32 nvm_image_type;
 250         u32 num_flow_director_filters;
 251         u32 num_vfs;
 252         u32 vf_base_id;
 253         u32 num_vsis;
 254         u32 num_rx_qp;
 255         u32 num_tx_qp;
 256         u32 base_queue;
 257         u32 num_msix_vectors;
 258         u32 num_msix_vectors_vf;
 259         u32 led_pin_num;
 260         u32 sdp_pin_num;
 261         u32 mdio_port_num;
 262         u32 mdio_port_mode;
 263         u8 rx_buf_chain_len;
 264         u32 enabled_tcmap;
 265         u32 maxtc;
 266         u64 wr_csr_prot;
 267 };
 268
 269 struct i40e_mac_info {
 270         enum i40e_mac_type type;
 271         u8 addr[ETH_ALEN];
 272         u8 perm_addr[ETH_ALEN];
 273         u8 port_addr[ETH_ALEN];
 274 };
 275
 276 enum i40e_aq_resources_ids {
 277         I40E_NVM_RESOURCE_ID = 1
 278 };
 279
 280 enum i40e_aq_resource_access_type {
 281         I40E_RESOURCE_READ = 1,
 282         I40E_RESOURCE_WRITE
 283 };
 284
 285 struct i40e_nvm_info {
 286         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 287         u32 timeout;              /* [ms] */
 288         u16 sr_size;              /* Shadow RAM size in words */
 289         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 290         u16 version;              /* NVM package version */
 291         u32 eetrack;              /* NVM data version */
 292         u32 oem_ver;              /* OEM version info */
 293 };
 294
 295 /* definitions used in NVM update support */
 296
 297 enum i40e_nvmupd_cmd {
 298         I40E_NVMUPD_INVALID,
 299         I40E_NVMUPD_READ_CON,
 300         I40E_NVMUPD_READ_SNT,
 301         I40E_NVMUPD_READ_LCB,
 302         I40E_NVMUPD_READ_SA,
 303         I40E_NVMUPD_WRITE_ERA,
 304         I40E_NVMUPD_WRITE_CON,
 305         I40E_NVMUPD_WRITE_SNT,
 306         I40E_NVMUPD_WRITE_LCB,
 307         I40E_NVMUPD_WRITE_SA,
 308         I40E_NVMUPD_CSUM_CON,
 309         I40E_NVMUPD_CSUM_SA,
 310         I40E_NVMUPD_CSUM_LCB,
 311         I40E_NVMUPD_STATUS,
 312         I40E_NVMUPD_EXEC_AQ,
 313         I40E_NVMUPD_GET_AQ_RESULT,
 314         I40E_NVMUPD_GET_AQ_EVENT,
 315 };
 316
 317 enum i40e_nvmupd_state {
 318         I40E_NVMUPD_STATE_INIT,
 319         I40E_NVMUPD_STATE_READING,
 320         I40E_NVMUPD_STATE_WRITING,
 321         I40E_NVMUPD_STATE_INIT_WAIT,
 322         I40E_NVMUPD_STATE_WRITE_WAIT,
 323         I40E_NVMUPD_STATE_ERROR
 324 };
 325
 326 /* nvm_access definition and its masks/shifts need to be accessible to
 327  * application, core driver, and shared code.  Where is the right file?
 328  */
 329 #define I40E_NVM_READ   0xB
 330 #define I40E_NVM_WRITE  0xC
 331
 332 #define I40E_NVM_MOD_PNT_MASK 0xFF
 333
 334 #define I40E_NVM_TRANS_SHIFT                    8
 335 #define I40E_NVM_TRANS_MASK                     (0xf << I40E_NVM_TRANS_SHIFT)
 336 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT       12
 337 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
 338                                 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
 339 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED    0x01
 340 #define I40E_NVM_PRESERVATION_FLAGS_ALL         0x02
 341 #define I40E_NVM_CON                            0x0
 342 #define I40E_NVM_SNT                            0x1
 343 #define I40E_NVM_LCB                            0x2
 344 #define I40E_NVM_SA                             (I40E_NVM_SNT | I40E_NVM_LCB)
 345 #define I40E_NVM_ERA                            0x4
 346 #define I40E_NVM_CSUM                           0x8
 347 #define I40E_NVM_AQE                            0xe
 348 #define I40E_NVM_EXEC                           0xf
 349
 350
 351 #define I40E_NVMUPD_MAX_DATA    4096
 352
 353 struct i40e_nvm_access {
 354         u32 command;
 355         u32 config;
 356         u32 offset;     /* in bytes */
 357         u32 data_size;  /* in bytes */
 358         u8 data[1];
 359 };
 360
 361 /* (Q)SFP module access definitions */
 362 #define I40E_I2C_EEPROM_DEV_ADDR        0xA0
 363 #define I40E_I2C_EEPROM_DEV_ADDR2       0xA2
 364 #define I40E_MODULE_REVISION_ADDR       0x01
 365 #define I40E_MODULE_SFF_8472_COMP       0x5E
 366 #define I40E_MODULE_SFF_8472_SWAP       0x5C
 367 #define I40E_MODULE_SFF_ADDR_MODE       0x04
 368 #define I40E_MODULE_SFF_DDM_IMPLEMENTED 0x40
 369 #define I40E_MODULE_TYPE_QSFP_PLUS      0x0D
 370 #define I40E_MODULE_TYPE_QSFP28         0x11
 371 #define I40E_MODULE_QSFP_MAX_LEN        640
 372
 373 /* PCI bus types */
 374 enum i40e_bus_type {
 375         i40e_bus_type_unknown = 0,
 376         i40e_bus_type_pci,
 377         i40e_bus_type_pcix,
 378         i40e_bus_type_pci_express,
 379         i40e_bus_type_reserved
 380 };
 381
 382 /* PCI bus speeds */
 383 enum i40e_bus_speed {
 384         i40e_bus_speed_unknown  = 0,
 385         i40e_bus_speed_33       = 33,
 386         i40e_bus_speed_66       = 66,
 387         i40e_bus_speed_100      = 100,
 388         i40e_bus_speed_120      = 120,
 389         i40e_bus_speed_133      = 133,
 390         i40e_bus_speed_2500     = 2500,
 391         i40e_bus_speed_5000     = 5000,
 392         i40e_bus_speed_8000     = 8000,
 393         i40e_bus_speed_reserved
 394 };
 395
 396 /* PCI bus widths */
 397 enum i40e_bus_width {
 398         i40e_bus_width_unknown  = 0,
 399         i40e_bus_width_pcie_x1  = 1,
 400         i40e_bus_width_pcie_x2  = 2,
 401         i40e_bus_width_pcie_x4  = 4,
 402         i40e_bus_width_pcie_x8  = 8,
 403         i40e_bus_width_32       = 32,
 404         i40e_bus_width_64       = 64,
 405         i40e_bus_width_reserved
 406 };
 407
 408 /* Bus parameters */
 409 struct i40e_bus_info {
 410         enum i40e_bus_speed speed;
 411         enum i40e_bus_width width;
 412         enum i40e_bus_type type;
 413
 414         u16 func;
 415         u16 device;
 416         u16 lan_id;
 417         u16 bus_id;
 418 };
 419
 420 /* Flow control (FC) parameters */
 421 struct i40e_fc_info {
 422         enum i40e_fc_mode current_mode; /* FC mode in effect */
 423         enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
 424 };
 425
 426 #define I40E_MAX_TRAFFIC_CLASS          8
 427 #define I40E_MAX_USER_PRIORITY          8
 428 #define I40E_DCBX_MAX_APPS              32
 429 #define I40E_LLDPDU_SIZE                1500
 430 #define I40E_TLV_STATUS_OPER            0x1
 431 #define I40E_TLV_STATUS_SYNC            0x2
 432 #define I40E_TLV_STATUS_ERR             0x4
 433 #define I40E_CEE_OPER_MAX_APPS          3
 434 #define I40E_APP_PROTOID_FCOE           0x8906
 435 #define I40E_APP_PROTOID_ISCSI          0x0cbc
 436 #define I40E_APP_PROTOID_FIP            0x8914
 437 #define I40E_APP_SEL_ETHTYPE            0x1
 438 #define I40E_APP_SEL_TCPIP              0x2
 439 #define I40E_CEE_APP_SEL_ETHTYPE        0x0
 440 #define I40E_CEE_APP_SEL_TCPIP          0x1
 441
 442 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 443 struct i40e_dcb_ets_config {
 444         u8 willing;
 445         u8 cbs;
 446         u8 maxtcs;
 447         u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
 448         u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
 449         u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
 450 };
 451
 452 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 453 struct i40e_dcb_pfc_config {
 454         u8 willing;
 455         u8 mbc;
 456         u8 pfccap;
 457         u8 pfcenable;
 458 };
 459
 460 /* CEE or IEEE 802.1Qaz Application Priority data */
 461 struct i40e_dcb_app_priority_table {
 462         u8  priority;
 463         u8  selector;
 464         u16 protocolid;
 465 };
 466
 467 struct i40e_dcbx_config {
 468         u8  dcbx_mode;
 469 #define I40E_DCBX_MODE_CEE      0x1
 470 #define I40E_DCBX_MODE_IEEE     0x2
 471         u8  app_mode;
 472 #define I40E_DCBX_APPS_NON_WILLING 0x1
 473         u32 numapps;
 474         u32 tlv_status; /* CEE mode TLV status */
 475         struct i40e_dcb_ets_config etscfg;
 476         struct i40e_dcb_ets_config etsrec;
 477         struct i40e_dcb_pfc_config pfc;
 478         struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
 479 };
 480
 481 enum i40e_hw_flags {
 482         I40E_HW_CAP_AQ_SRCTL_ACCESS_ENABLE,
 483         I40E_HW_CAP_802_1AD,
 484         I40E_HW_CAP_AQ_PHY_ACCESS,
 485         I40E_HW_CAP_NVM_READ_REQUIRES_LOCK,
 486         I40E_HW_CAP_FW_LLDP_STOPPABLE,
 487         I40E_HW_CAP_FW_LLDP_PERSISTENT,
 488         I40E_HW_CAP_AQ_PHY_ACCESS_EXTENDED,
 489         I40E_HW_CAP_X722_FEC_REQUEST,
 490         I40E_HW_CAP_RSS_AQ,
 491         I40E_HW_CAP_128_QP_RSS,
 492         I40E_HW_CAP_ATR_EVICT,
 493         I40E_HW_CAP_WB_ON_ITR,
 494         I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE,
 495         I40E_HW_CAP_NO_PCI_LINK_CHECK,
 496         I40E_HW_CAP_100M_SGMII,
 497         I40E_HW_CAP_NO_DCB_SUPPORT,
 498         I40E_HW_CAP_USE_SET_LLDP_MIB,
 499         I40E_HW_CAP_GENEVE_OFFLOAD,
 500         I40E_HW_CAP_PTP_L4,
 501         I40E_HW_CAP_WOL_MC_MAGIC_PKT_WAKE,
 502         I40E_HW_CAP_CRT_RETIMER,
 503         I40E_HW_CAP_OUTER_UDP_CSUM,
 504         I40E_HW_CAP_PHY_CONTROLS_LEDS,
 505         I40E_HW_CAP_STOP_FW_LLDP,
 506         I40E_HW_CAP_PORT_ID_VALID,
 507         I40E_HW_CAP_RESTART_AUTONEG,
 508         I40E_HW_CAPS_NBITS,
 509 };
 510
 511 /* Port hardware description */
 512 struct i40e_hw {
 513         u8 __iomem *hw_addr;
 514
 515         /* subsystem structs */
 516         struct i40e_phy_info phy;
 517         struct i40e_mac_info mac;
 518         struct i40e_bus_info bus;
 519         struct i40e_nvm_info nvm;
 520         struct i40e_fc_info fc;
 521
 522         /* PBA ID */
 523         const char *pba_id;
 524
 525         /* pci info */
 526         u16 device_id;
 527         u16 vendor_id;
 528         u16 subsystem_device_id;
 529         u16 subsystem_vendor_id;
 530         u8 revision_id;
 531         u8 port;
 532         bool adapter_stopped;
 533
 534         /* capabilities for entire device and PCI func */
 535         struct i40e_hw_capabilities dev_caps;
 536         struct i40e_hw_capabilities func_caps;
 537
 538         /* Flow Director shared filter space */
 539         u16 fdir_shared_filter_count;
 540
 541         /* device profile info */
 542         u8  pf_id;
 543         u16 main_vsi_seid;
 544
 545         /* for multi-function MACs */
 546         u16 partition_id;
 547         u16 num_partitions;
 548         u16 num_ports;
 549
 550         /* Closest numa node to the device */
 551         u16 numa_node;
 552
 553         /* Admin Queue info */
 554         struct i40e_adminq_info aq;
 555
 556         /* state of nvm update process */
 557         enum i40e_nvmupd_state nvmupd_state;
 558         struct i40e_aq_desc nvm_wb_desc;
 559         struct i40e_aq_desc nvm_aq_event_desc;
 560         struct i40e_virt_mem nvm_buff;
 561         bool nvm_release_on_done;
 562         u16 nvm_wait_opcode;
 563
 564         /* HMC info */
 565         struct i40e_hmc_info hmc; /* HMC info struct */
 566
 567         /* LLDP/DCBX Status */
 568         u16 dcbx_status;
 569
 570         /* DCBX info */
 571         struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 572         struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
 573         struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 574
 575         DECLARE_BITMAP(caps, I40E_HW_CAPS_NBITS);
 576
 577         /* Used in set switch config AQ command */
 578         u16 switch_tag;
 579         u16 first_tag;
 580         u16 second_tag;
 581
 582         /* debug mask */
 583         u32 debug_mask;
 584         char err_str[16];
 585 };
 586
 587 struct i40e_driver_version {
 588         u8 major_version;
 589         u8 minor_version;
 590         u8 build_version;
 591         u8 subbuild_version;
 592         u8 driver_string[32];
 593 };
 594
 595 /* RX Descriptors */
 596 union i40e_16byte_rx_desc {
 597         struct {
 598                 __le64 pkt_addr; /* Packet buffer address */
 599                 __le64 hdr_addr; /* Header buffer address */
 600         } read;
 601         struct {
 602                 struct i40e_16b_rx_wb_qw0 {
 603                         struct {
 604                                 union {
 605                                         __le16 mirroring_status;
 606                                         __le16 fcoe_ctx_id;
 607                                 } mirr_fcoe;
 608                                 __le16 l2tag1;
 609                         } lo_dword;
 610                         union {
 611                                 __le32 rss; /* RSS Hash */
 612                                 __le32 fd_id; /* Flow director filter id */
 613                                 __le32 fcoe_param; /* FCoE DDP Context id */
 614                         } hi_dword;
 615                 } qword0;
 616                 struct {
 617                         /* ext status/error/pktype/length */
 618                         __le64 status_error_len;
 619                 } qword1;
 620         } wb;  /* writeback */
 621         struct {
 622                 u64 qword[2];
 623         } raw;
 624 };
 625
 626 union i40e_32byte_rx_desc {
 627         struct {
 628                 __le64  pkt_addr; /* Packet buffer address */
 629                 __le64  hdr_addr; /* Header buffer address */
 630                         /* bit 0 of hdr_buffer_addr is DD bit */
 631                 __le64  rsvd1;
 632                 __le64  rsvd2;
 633         } read;
 634         struct {
 635                 struct i40e_32b_rx_wb_qw0 {
 636                         struct {
 637                                 union {
 638                                         __le16 mirroring_status;
 639                                         __le16 fcoe_ctx_id;
 640                                 } mirr_fcoe;
 641                                 __le16 l2tag1;
 642                         } lo_dword;
 643                         union {
 644                                 __le32 rss; /* RSS Hash */
 645                                 __le32 fcoe_param; /* FCoE DDP Context id */
 646                                 /* Flow director filter id in case of
 647                                  * Programming status desc WB
 648                                  */
 649                                 __le32 fd_id;
 650                         } hi_dword;
 651                 } qword0;
 652                 struct {
 653                         /* status/error/pktype/length */
 654                         __le64 status_error_len;
 655                 } qword1;
 656                 struct {
 657                         __le16 ext_status; /* extended status */
 658                         __le16 rsvd;
 659                         __le16 l2tag2_1;
 660                         __le16 l2tag2_2;
 661                 } qword2;
 662                 struct {
 663                         union {
 664                                 __le32 flex_bytes_lo;
 665                                 __le32 pe_status;
 666                         } lo_dword;
 667                         union {
 668                                 __le32 flex_bytes_hi;
 669                                 __le32 fd_id;
 670                         } hi_dword;
 671                 } qword3;
 672         } wb;  /* writeback */
 673         struct {
 674                 u64 qword[4];
 675         } raw;
 676 };
 677
 678 enum i40e_rx_desc_status_bits {
 679         /* Note: These are predefined bit offsets */
 680         I40E_RX_DESC_STATUS_DD_SHIFT            = 0,
 681         I40E_RX_DESC_STATUS_EOF_SHIFT           = 1,
 682         I40E_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 683         I40E_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 684         I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 685         I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 686         I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 687         /* Note: Bit 8 is reserved in X710 and XL710 */
 688         I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 689         I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 690         I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
 691         I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 692         I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 693         I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 694         I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 695         /* Note: For non-tunnel packets INT_UDP_0 is the right status for
 696          * UDP header
 697          */
 698         I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 699         I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 700 };
 701
 702 #define I40E_RXD_QW1_STATUS_SHIFT       0
 703 #define I40E_RXD_QW1_STATUS_MASK        ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
 704                                          << I40E_RXD_QW1_STATUS_SHIFT)
 705
 706 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT   I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
 707 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 708                                              I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 709
 710 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT  I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
 711 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
 712                                     BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 713
 714 enum i40e_rx_desc_fltstat_values {
 715         I40E_RX_DESC_FLTSTAT_NO_DATA    = 0,
 716         I40E_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 717         I40E_RX_DESC_FLTSTAT_RSV        = 2,
 718         I40E_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 719 };
 720
 721 #define I40E_RXD_QW1_ERROR_SHIFT        19
 722 #define I40E_RXD_QW1_ERROR_MASK         (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
 723
 724 enum i40e_rx_desc_error_bits {
 725         /* Note: These are predefined bit offsets */
 726         I40E_RX_DESC_ERROR_RXE_SHIFT            = 0,
 727         I40E_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 728         I40E_RX_DESC_ERROR_HBO_SHIFT            = 2,
 729         I40E_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 730         I40E_RX_DESC_ERROR_IPE_SHIFT            = 3,
 731         I40E_RX_DESC_ERROR_L4E_SHIFT            = 4,
 732         I40E_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 733         I40E_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 734         I40E_RX_DESC_ERROR_PPRS_SHIFT           = 7
 735 };
 736
 737 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
 738         I40E_RX_DESC_ERROR_L3L4E_NONE           = 0,
 739         I40E_RX_DESC_ERROR_L3L4E_PROT           = 1,
 740         I40E_RX_DESC_ERROR_L3L4E_FC             = 2,
 741         I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 742         I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 743 };
 744
 745 #define I40E_RXD_QW1_PTYPE_SHIFT        30
 746 #define I40E_RXD_QW1_PTYPE_MASK         (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
 747
 748 /* Packet type non-ip values */
 749 enum i40e_rx_l2_ptype {
 750         I40E_RX_PTYPE_L2_RESERVED                       = 0,
 751         I40E_RX_PTYPE_L2_MAC_PAY2                       = 1,
 752         I40E_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 753         I40E_RX_PTYPE_L2_FIP_PAY2                       = 3,
 754         I40E_RX_PTYPE_L2_OUI_PAY2                       = 4,
 755         I40E_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 756         I40E_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 757         I40E_RX_PTYPE_L2_ECP_PAY2                       = 7,
 758         I40E_RX_PTYPE_L2_EVB_PAY2                       = 8,
 759         I40E_RX_PTYPE_L2_QCN_PAY2                       = 9,
 760         I40E_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 761         I40E_RX_PTYPE_L2_ARP                            = 11,
 762         I40E_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 763         I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 764         I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 765         I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 766         I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 767         I40E_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 768         I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 769         I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 770         I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 771         I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 772         I40E_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 773         I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 774         I40E_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 775         I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 776 };
 777
 778 struct i40e_rx_ptype_decoded {
 779         u32 known:1;
 780         u32 outer_ip:1;
 781         u32 outer_ip_ver:1;
 782         u32 outer_frag:1;
 783         u32 tunnel_type:3;
 784         u32 tunnel_end_prot:2;
 785         u32 tunnel_end_frag:1;
 786         u32 inner_prot:4;
 787         u32 payload_layer:3;
 788 };
 789
 790 enum i40e_rx_ptype_outer_ip {
 791         I40E_RX_PTYPE_OUTER_L2  = 0,
 792         I40E_RX_PTYPE_OUTER_IP  = 1
 793 };
 794
 795 enum i40e_rx_ptype_outer_ip_ver {
 796         I40E_RX_PTYPE_OUTER_NONE        = 0,
 797         I40E_RX_PTYPE_OUTER_IPV4        = 0,
 798         I40E_RX_PTYPE_OUTER_IPV6        = 1
 799 };
 800
 801 enum i40e_rx_ptype_outer_fragmented {
 802         I40E_RX_PTYPE_NOT_FRAG  = 0,
 803         I40E_RX_PTYPE_FRAG      = 1
 804 };
 805
 806 enum i40e_rx_ptype_tunnel_type {
 807         I40E_RX_PTYPE_TUNNEL_NONE               = 0,
 808         I40E_RX_PTYPE_TUNNEL_IP_IP              = 1,
 809         I40E_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 810         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 811         I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 812 };
 813
 814 enum i40e_rx_ptype_tunnel_end_prot {
 815         I40E_RX_PTYPE_TUNNEL_END_NONE   = 0,
 816         I40E_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 817         I40E_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 818 };
 819
 820 enum i40e_rx_ptype_inner_prot {
 821         I40E_RX_PTYPE_INNER_PROT_NONE           = 0,
 822         I40E_RX_PTYPE_INNER_PROT_UDP            = 1,
 823         I40E_RX_PTYPE_INNER_PROT_TCP            = 2,
 824         I40E_RX_PTYPE_INNER_PROT_SCTP           = 3,
 825         I40E_RX_PTYPE_INNER_PROT_ICMP           = 4,
 826         I40E_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 827 };
 828
 829 enum i40e_rx_ptype_payload_layer {
 830         I40E_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 831         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 832         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 833         I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 834 };
 835
 836 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT  38
 837 #define I40E_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 838                                          I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
 839
 840
 841 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT   63
 842 #define I40E_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
 843
 844 enum i40e_rx_desc_ext_status_bits {
 845         /* Note: These are predefined bit offsets */
 846         I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 847         I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 848         I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 849         I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 850         I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 851         I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 852         I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 853 };
 854
 855 enum i40e_rx_desc_pe_status_bits {
 856         /* Note: These are predefined bit offsets */
 857         I40E_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 858         I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 859         I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 860         I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 861         I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 862         I40E_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 863         I40E_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 864         I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 865         I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 866 };
 867
 868 #define I40E_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 869
 870 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 871 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 872                                 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 873
 874 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 875 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 876                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 877
 878 enum i40e_rx_prog_status_desc_status_bits {
 879         /* Note: These are predefined bit offsets */
 880         I40E_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 881         I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 882 };
 883
 884 enum i40e_rx_prog_status_desc_prog_id_masks {
 885         I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 886         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 887         I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 888 };
 889
 890 enum i40e_rx_prog_status_desc_error_bits {
 891         /* Note: These are predefined bit offsets */
 892         I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 893         I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 894         I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 895         I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 896 };
 897
 898 /* TX Descriptor */
 899 struct i40e_tx_desc {
 900         __le64 buffer_addr; /* Address of descriptor's data buf */
 901         __le64 cmd_type_offset_bsz;
 902 };
 903
 904
 905 enum i40e_tx_desc_dtype_value {
 906         I40E_TX_DESC_DTYPE_DATA         = 0x0,
 907         I40E_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 908         I40E_TX_DESC_DTYPE_CONTEXT      = 0x1,
 909         I40E_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 910         I40E_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 911         I40E_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 912         I40E_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 913         I40E_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 914         I40E_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 915         I40E_TX_DESC_DTYPE_DESC_DONE    = 0xF
 916 };
 917
 918 #define I40E_TXD_QW1_CMD_SHIFT  4
 919
 920 enum i40e_tx_desc_cmd_bits {
 921         I40E_TX_DESC_CMD_EOP                    = 0x0001,
 922         I40E_TX_DESC_CMD_RS                     = 0x0002,
 923         I40E_TX_DESC_CMD_ICRC                   = 0x0004,
 924         I40E_TX_DESC_CMD_IL2TAG1                = 0x0008,
 925         I40E_TX_DESC_CMD_DUMMY                  = 0x0010,
 926         I40E_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 927         I40E_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 928         I40E_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 929         I40E_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 930         I40E_TX_DESC_CMD_FCOET                  = 0x0080,
 931         I40E_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 932         I40E_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 933         I40E_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 934         I40E_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 935         I40E_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 936         I40E_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 937         I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 938         I40E_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 939 };
 940
 941 #define I40E_TXD_QW1_OFFSET_SHIFT       16
 942
 943 enum i40e_tx_desc_length_fields {
 944         /* Note: These are predefined bit offsets */
 945         I40E_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 946         I40E_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 947         I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 948 };
 949
 950 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT    34
 951
 952 #define I40E_TXD_QW1_L2TAG1_SHIFT       48
 953
 954 /* Context descriptors */
 955 struct i40e_tx_context_desc {
 956         __le32 tunneling_params;
 957         __le16 l2tag2;
 958         __le16 rsvd;
 959         __le64 type_cmd_tso_mss;
 960 };
 961
 962
 963 #define I40E_TXD_CTX_QW1_CMD_SHIFT      4
 964
 965 enum i40e_tx_ctx_desc_cmd_bits {
 966         I40E_TX_CTX_DESC_TSO            = 0x01,
 967         I40E_TX_CTX_DESC_TSYN           = 0x02,
 968         I40E_TX_CTX_DESC_IL2TAG2        = 0x04,
 969         I40E_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 970         I40E_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 971         I40E_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 972         I40E_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 973         I40E_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 974         I40E_TX_CTX_DESC_SWPE           = 0x40
 975 };
 976
 977 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 978
 979 #define I40E_TXD_CTX_QW1_MSS_SHIFT      50
 980
 981
 982
 983 enum i40e_tx_ctx_desc_eipt_offload {
 984         I40E_TX_CTX_EXT_IP_NONE         = 0x0,
 985         I40E_TX_CTX_EXT_IP_IPV6         = 0x1,
 986         I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 987         I40E_TX_CTX_EXT_IP_IPV4         = 0x3
 988 };
 989
 990 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 991
 992 #define I40E_TXD_CTX_QW0_NATT_SHIFT     9
 993
 994 #define I40E_TXD_CTX_UDP_TUNNELING      BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
 995 #define I40E_TXD_CTX_GRE_TUNNELING      (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
 996
 997
 998
 999 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT   12
1000
1001
1002 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT   23
1003 #define I40E_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1004 struct i40e_filter_program_desc {
1005         __le32 qindex_flex_ptype_vsi;
1006         __le32 rsvd;
1007         __le32 dtype_cmd_cntindex;
1008         __le32 fd_id;
1009 };
1010 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT  0
1011 #define I40E_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1012                                          I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1013 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1014 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1015                                          I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1016 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1017 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1018                                          I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1019
1020 /* Packet Classifier Types for filters */
1021 enum i40e_filter_pctype {
1022         /* Note: Values 0-28 are reserved for future use.
1023          * Value 29, 30, 32 are not supported on XL710 and X710.
1024          */
1025         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1026         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1027         I40E_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1028         I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1029         I40E_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1030         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1031         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1032         I40E_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1033         /* Note: Values 37-38 are reserved for future use.
1034          * Value 39, 40, 42 are not supported on XL710 and X710.
1035          */
1036         I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1037         I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1038         I40E_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1039         I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1040         I40E_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1041         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1042         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1043         I40E_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1044         /* Note: Value 47 is reserved for future use */
1045         I40E_FILTER_PCTYPE_FCOE_OX                      = 48,
1046         I40E_FILTER_PCTYPE_FCOE_RX                      = 49,
1047         I40E_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1048         /* Note: Values 51-62 are reserved for future use */
1049         I40E_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1050 };
1051
1052 enum i40e_filter_program_desc_dest {
1053         I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1054         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1055         I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1056 };
1057
1058 enum i40e_filter_program_desc_fd_status {
1059         I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1060         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1061         I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1062         I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1063 };
1064
1065 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1066 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1067                                          I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1068
1069 #define I40E_TXD_FLTR_QW1_CMD_SHIFT     4
1070
1071 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1072
1073 enum i40e_filter_program_desc_pcmd {
1074         I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1075         I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1076 };
1077
1078 #define I40E_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1079 #define I40E_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1080
1081 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1082 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1083
1084 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1085                                                  I40E_TXD_FLTR_QW1_CMD_SHIFT)
1086 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1087                                           I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1088
1089 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1090                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1091 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1092
1093 #define I40E_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1094                                          I40E_TXD_FLTR_QW1_CMD_SHIFT)
1095 #define I40E_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1096
1097 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1098 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1099                                          I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1100
1101 enum i40e_filter_type {
1102         I40E_FLOW_DIRECTOR_FLTR = 0,
1103         I40E_PE_QUAD_HASH_FLTR = 1,
1104         I40E_ETHERTYPE_FLTR,
1105         I40E_FCOE_CTX_FLTR,
1106         I40E_MAC_VLAN_FLTR,
1107         I40E_HASH_FLTR
1108 };
1109
1110 struct i40e_vsi_context {
1111         u16 seid;
1112         u16 uplink_seid;
1113         u16 vsi_number;
1114         u16 vsis_allocated;
1115         u16 vsis_unallocated;
1116         u16 flags;
1117         u8 pf_num;
1118         u8 vf_num;
1119         u8 connection_type;
1120         struct i40e_aqc_vsi_properties_data info;
1121 };
1122
1123 struct i40e_veb_context {
1124         u16 seid;
1125         u16 uplink_seid;
1126         u16 veb_number;
1127         u16 vebs_allocated;
1128         u16 vebs_unallocated;
1129         u16 flags;
1130         struct i40e_aqc_get_veb_parameters_completion info;
1131 };
1132
1133 /* Statistics collected by each port, VSI, VEB, and S-channel */
1134 struct i40e_eth_stats {
1135         u64 rx_bytes;                   /* gorc */
1136         u64 rx_unicast;                 /* uprc */
1137         u64 rx_multicast;               /* mprc */
1138         u64 rx_broadcast;               /* bprc */
1139         u64 rx_discards;                /* rdpc */
1140         u64 rx_unknown_protocol;        /* rupp */
1141         u64 tx_bytes;                   /* gotc */
1142         u64 tx_unicast;                 /* uptc */
1143         u64 tx_multicast;               /* mptc */
1144         u64 tx_broadcast;               /* bptc */
1145         u64 tx_discards;                /* tdpc */
1146         u64 tx_errors;                  /* tepc */
1147         u64 rx_discards_other;          /* rxerr1 */
1148 };
1149
1150 /* Statistics collected per VEB per TC */
1151 struct i40e_veb_tc_stats {
1152         u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1153         u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1154         u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1155         u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1156 };
1157
1158 /* Statistics collected by the MAC */
1159 struct i40e_hw_port_stats {
1160         /* eth stats collected by the port */
1161         struct i40e_eth_stats eth;
1162
1163         /* additional port specific stats */
1164         u64 tx_dropped_link_down;       /* tdold */
1165         u64 crc_errors;                 /* crcerrs */
1166         u64 illegal_bytes;              /* illerrc */
1167         u64 error_bytes;                /* errbc */
1168         u64 mac_local_faults;           /* mlfc */
1169         u64 mac_remote_faults;          /* mrfc */
1170         u64 rx_length_errors;           /* rlec */
1171         u64 link_xon_rx;                /* lxonrxc */
1172         u64 link_xoff_rx;               /* lxoffrxc */
1173         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1174         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1175         u64 link_xon_tx;                /* lxontxc */
1176         u64 link_xoff_tx;               /* lxofftxc */
1177         u64 priority_xon_tx[8];         /* pxontxc[8] */
1178         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1179         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1180         u64 rx_size_64;                 /* prc64 */
1181         u64 rx_size_127;                /* prc127 */
1182         u64 rx_size_255;                /* prc255 */
1183         u64 rx_size_511;                /* prc511 */
1184         u64 rx_size_1023;               /* prc1023 */
1185         u64 rx_size_1522;               /* prc1522 */
1186         u64 rx_size_big;                /* prc9522 */
1187         u64 rx_undersize;               /* ruc */
1188         u64 rx_fragments;               /* rfc */
1189         u64 rx_oversize;                /* roc */
1190         u64 rx_jabber;                  /* rjc */
1191         u64 tx_size_64;                 /* ptc64 */
1192         u64 tx_size_127;                /* ptc127 */
1193         u64 tx_size_255;                /* ptc255 */
1194         u64 tx_size_511;                /* ptc511 */
1195         u64 tx_size_1023;               /* ptc1023 */
1196         u64 tx_size_1522;               /* ptc1522 */
1197         u64 tx_size_big;                /* ptc9522 */
1198         u64 mac_short_packet_dropped;   /* mspdc */
1199         u64 checksum_error;             /* xec */
1200         /* flow director stats */
1201         u64 fd_atr_match;
1202         u64 fd_sb_match;
1203         u64 fd_atr_tunnel_match;
1204         u32 fd_atr_status;
1205         u32 fd_sb_status;
1206         /* EEE LPI */
1207         u32 tx_lpi_status;
1208         u32 rx_lpi_status;
1209         u64 tx_lpi_count;               /* etlpic */
1210         u64 rx_lpi_count;               /* erlpic */
1211 };
1212
1213 /* Checksum and Shadow RAM pointers */
1214 #define I40E_SR_NVM_CONTROL_WORD                0x00
1215 #define I40E_EMP_MODULE_PTR                     0x0F
1216 #define I40E_SR_EMP_MODULE_PTR                  0x48
1217 #define I40E_SR_PBA_FLAGS                       0x15
1218 #define I40E_SR_PBA_BLOCK_PTR                   0x16
1219 #define I40E_SR_BOOT_CONFIG_PTR                 0x17
1220 #define I40E_NVM_OEM_VER_OFF                    0x83
1221 #define I40E_SR_NVM_DEV_STARTER_VERSION         0x18
1222 #define I40E_SR_NVM_WAKE_ON_LAN                 0x19
1223 #define I40E_SR_NVM_EETRACK_LO                  0x2D
1224 #define I40E_SR_NVM_EETRACK_HI                  0x2E
1225 #define I40E_SR_VPD_PTR                         0x2F
1226 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1227 #define I40E_SR_SW_CHECKSUM_WORD                0x3F
1228 #define I40E_SR_EMP_SR_SETTINGS_PTR             0x48
1229
1230 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1231 #define I40E_SR_VPD_MODULE_MAX_SIZE             1024
1232 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1233 #define I40E_SR_CONTROL_WORD_1_SHIFT            0x06
1234 #define I40E_SR_CONTROL_WORD_1_MASK     (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1235 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE          BIT(12)
1236 #define I40E_PTR_TYPE                           BIT(15)
1237 #define I40E_SR_OCP_CFG_WORD0                   0x2B
1238 #define I40E_SR_OCP_ENABLED                     BIT(15)
1239
1240 /* Shadow RAM related */
1241 #define I40E_SR_SECTOR_SIZE_IN_WORDS    0x800
1242 #define I40E_SR_WORDS_IN_1KB            512
1243 /* Checksum should be calculated such that after adding all the words,
1244  * including the checksum word itself, the sum should be 0xBABA.
1245  */
1246 #define I40E_SR_SW_CHECKSUM_BASE        0xBABA
1247
1248 #define I40E_SRRD_SRCTL_ATTEMPTS        100000
1249
1250 enum i40e_switch_element_types {
1251         I40E_SWITCH_ELEMENT_TYPE_MAC    = 1,
1252         I40E_SWITCH_ELEMENT_TYPE_PF     = 2,
1253         I40E_SWITCH_ELEMENT_TYPE_VF     = 3,
1254         I40E_SWITCH_ELEMENT_TYPE_EMP    = 4,
1255         I40E_SWITCH_ELEMENT_TYPE_BMC    = 6,
1256         I40E_SWITCH_ELEMENT_TYPE_PE     = 16,
1257         I40E_SWITCH_ELEMENT_TYPE_VEB    = 17,
1258         I40E_SWITCH_ELEMENT_TYPE_PA     = 18,
1259         I40E_SWITCH_ELEMENT_TYPE_VSI    = 19,
1260 };
1261
1262 /* Supported EtherType filters */
1263 enum i40e_ether_type_index {
1264         I40E_ETHER_TYPE_1588            = 0,
1265         I40E_ETHER_TYPE_FIP             = 1,
1266         I40E_ETHER_TYPE_OUI_EXTENDED    = 2,
1267         I40E_ETHER_TYPE_MAC_CONTROL     = 3,
1268         I40E_ETHER_TYPE_LLDP            = 4,
1269         I40E_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1270         I40E_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1271         I40E_ETHER_TYPE_QCN_CNM         = 7,
1272         I40E_ETHER_TYPE_8021X           = 8,
1273         I40E_ETHER_TYPE_ARP             = 9,
1274         I40E_ETHER_TYPE_RSV1            = 10,
1275         I40E_ETHER_TYPE_RSV2            = 11,
1276 };
1277
1278 /* Filter context base size is 1K */
1279 #define I40E_HASH_FILTER_BASE_SIZE      1024
1280 /* Supported Hash filter values */
1281 enum i40e_hash_filter_size {
1282         I40E_HASH_FILTER_SIZE_1K        = 0,
1283         I40E_HASH_FILTER_SIZE_2K        = 1,
1284         I40E_HASH_FILTER_SIZE_4K        = 2,
1285         I40E_HASH_FILTER_SIZE_8K        = 3,
1286         I40E_HASH_FILTER_SIZE_16K       = 4,
1287         I40E_HASH_FILTER_SIZE_32K       = 5,
1288         I40E_HASH_FILTER_SIZE_64K       = 6,
1289         I40E_HASH_FILTER_SIZE_128K      = 7,
1290         I40E_HASH_FILTER_SIZE_256K      = 8,
1291         I40E_HASH_FILTER_SIZE_512K      = 9,
1292         I40E_HASH_FILTER_SIZE_1M        = 10,
1293 };
1294
1295 /* DMA context base size is 0.5K */
1296 #define I40E_DMA_CNTX_BASE_SIZE         512
1297 /* Supported DMA context values */
1298 enum i40e_dma_cntx_size {
1299         I40E_DMA_CNTX_SIZE_512          = 0,
1300         I40E_DMA_CNTX_SIZE_1K           = 1,
1301         I40E_DMA_CNTX_SIZE_2K           = 2,
1302         I40E_DMA_CNTX_SIZE_4K           = 3,
1303         I40E_DMA_CNTX_SIZE_8K           = 4,
1304         I40E_DMA_CNTX_SIZE_16K          = 5,
1305         I40E_DMA_CNTX_SIZE_32K          = 6,
1306         I40E_DMA_CNTX_SIZE_64K          = 7,
1307         I40E_DMA_CNTX_SIZE_128K         = 8,
1308         I40E_DMA_CNTX_SIZE_256K         = 9,
1309 };
1310
1311 /* Supported Hash look up table (LUT) sizes */
1312 enum i40e_hash_lut_size {
1313         I40E_HASH_LUT_SIZE_128          = 0,
1314         I40E_HASH_LUT_SIZE_512          = 1,
1315 };
1316
1317 /* Structure to hold a per PF filter control settings */
1318 struct i40e_filter_control_settings {
1319         /* number of PE Quad Hash filter buckets */
1320         enum i40e_hash_filter_size pe_filt_num;
1321         /* number of PE Quad Hash contexts */
1322         enum i40e_dma_cntx_size pe_cntx_num;
1323         /* number of FCoE filter buckets */
1324         enum i40e_hash_filter_size fcoe_filt_num;
1325         /* number of FCoE DDP contexts */
1326         enum i40e_dma_cntx_size fcoe_cntx_num;
1327         /* size of the Hash LUT */
1328         enum i40e_hash_lut_size hash_lut_size;
1329         /* enable FDIR filters for PF and its VFs */
1330         bool enable_fdir;
1331         /* enable Ethertype filters for PF and its VFs */
1332         bool enable_ethtype;
1333         /* enable MAC/VLAN filters for PF and its VFs */
1334         bool enable_macvlan;
1335 };
1336
1337 /* Structure to hold device level control filter counts */
1338 struct i40e_control_filter_stats {
1339         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1340         u16 etype_used;       /* Used perfect EtherType filters */
1341         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1342         u16 etype_free;       /* Un-used perfect EtherType filters */
1343 };
1344
1345 enum i40e_reset_type {
1346         I40E_RESET_POR          = 0,
1347         I40E_RESET_CORER        = 1,
1348         I40E_RESET_GLOBR        = 2,
1349         I40E_RESET_EMPR         = 3,
1350 };
1351
1352 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1353 #define I40E_NVM_LLDP_CFG_PTR   0x06
1354 #define I40E_SR_LLDP_CFG_PTR    0x31
1355 struct i40e_lldp_variables {
1356         u16 length;
1357         u16 adminstatus;
1358         u16 msgfasttx;
1359         u16 msgtxinterval;
1360         u16 txparams;
1361         u16 timers;
1362         u16 crc8;
1363 };
1364
1365 /* Offsets into Alternate Ram */
1366 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1367 #define I40E_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1368 #define I40E_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1369 #define I40E_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1370
1371 /* Alternate Ram Bandwidth Masks */
1372 #define I40E_ALT_BW_VALUE_MASK          0xFF
1373 #define I40E_ALT_BW_VALID_MASK          0x80000000
1374
1375 /* RSS Hash Table Size */
1376 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1377
1378 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1379 #define I40E_X722_L3_SRC_SHIFT          49
1380 #define I40E_X722_L3_SRC_MASK           (0x3ULL << I40E_X722_L3_SRC_SHIFT)
1381 #define I40E_X722_L3_DST_SHIFT          41
1382 #define I40E_X722_L3_DST_MASK           (0x3ULL << I40E_X722_L3_DST_SHIFT)
1383 #define I40E_L3_SRC_SHIFT               47
1384 #define I40E_L3_SRC_MASK                (0x3ULL << I40E_L3_SRC_SHIFT)
1385 #define I40E_L3_V6_SRC_SHIFT            43
1386 #define I40E_L3_V6_SRC_MASK             (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1387 #define I40E_L3_DST_SHIFT               35
1388 #define I40E_L3_DST_MASK                (0x3ULL << I40E_L3_DST_SHIFT)
1389 #define I40E_L3_V6_DST_SHIFT            35
1390 #define I40E_L3_V6_DST_MASK             (0xFFULL << I40E_L3_V6_DST_SHIFT)
1391 #define I40E_L4_SRC_SHIFT               34
1392 #define I40E_L4_SRC_MASK                (0x1ULL << I40E_L4_SRC_SHIFT)
1393 #define I40E_L4_DST_SHIFT               33
1394 #define I40E_L4_DST_MASK                (0x1ULL << I40E_L4_DST_SHIFT)
1395 #define I40E_VERIFY_TAG_SHIFT           31
1396 #define I40E_VERIFY_TAG_MASK            (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1397 #define I40E_VLAN_SRC_SHIFT             55
1398 #define I40E_VLAN_SRC_MASK              (0x1ULL << I40E_VLAN_SRC_SHIFT)
1399
1400 #define I40E_FLEX_50_SHIFT              13
1401 #define I40E_FLEX_50_MASK               (0x1ULL << I40E_FLEX_50_SHIFT)
1402 #define I40E_FLEX_51_SHIFT              12
1403 #define I40E_FLEX_51_MASK               (0x1ULL << I40E_FLEX_51_SHIFT)
1404 #define I40E_FLEX_52_SHIFT              11
1405 #define I40E_FLEX_52_MASK               (0x1ULL << I40E_FLEX_52_SHIFT)
1406 #define I40E_FLEX_53_SHIFT              10
1407 #define I40E_FLEX_53_MASK               (0x1ULL << I40E_FLEX_53_SHIFT)
1408 #define I40E_FLEX_54_SHIFT              9
1409 #define I40E_FLEX_54_MASK               (0x1ULL << I40E_FLEX_54_SHIFT)
1410 #define I40E_FLEX_55_SHIFT              8
1411 #define I40E_FLEX_55_MASK               (0x1ULL << I40E_FLEX_55_SHIFT)
1412 #define I40E_FLEX_56_SHIFT              7
1413 #define I40E_FLEX_56_MASK               (0x1ULL << I40E_FLEX_56_SHIFT)
1414 #define I40E_FLEX_57_SHIFT              6
1415 #define I40E_FLEX_57_MASK               (0x1ULL << I40E_FLEX_57_SHIFT)
1416
1417 /* Version format for Dynamic Device Personalization(DDP) */
1418 struct i40e_ddp_version {
1419         u8 major;
1420         u8 minor;
1421         u8 update;
1422         u8 draft;
1423 };
1424
1425 #define I40E_DDP_NAME_SIZE      32
1426
1427 /* Package header */
1428 struct i40e_package_header {
1429         struct i40e_ddp_version version;
1430         u32 segment_count;
1431         u32 segment_offset[];
1432 };
1433
1434 /* Generic segment header */
1435 struct i40e_generic_seg_header {
1436 #define SEGMENT_TYPE_METADATA   0x00000001
1437 #define SEGMENT_TYPE_I40E       0x00000011
1438         u32 type;
1439         struct i40e_ddp_version version;
1440         u32 size;
1441         char name[I40E_DDP_NAME_SIZE];
1442 };
1443
1444 struct i40e_metadata_segment {
1445         struct i40e_generic_seg_header header;
1446         struct i40e_ddp_version version;
1447 #define I40E_DDP_TRACKID_INVALID        0xFFFFFFFF
1448         u32 track_id;
1449         char name[I40E_DDP_NAME_SIZE];
1450 };
1451
1452 struct i40e_device_id_entry {
1453         u32 vendor_dev_id;
1454         u32 sub_vendor_dev_id;
1455 };
1456
1457 struct i40e_profile_segment {
1458         struct i40e_generic_seg_header header;
1459         struct i40e_ddp_version version;
1460         char name[I40E_DDP_NAME_SIZE];
1461         u32 device_table_count;
1462         struct i40e_device_id_entry device_table[];
1463 };
1464
1465 struct i40e_section_table {
1466         u32 section_count;
1467         u32 section_offset[];
1468 };
1469
1470 struct i40e_profile_section_header {
1471         u16 tbl_size;
1472         u16 data_end;
1473         struct {
1474 #define SECTION_TYPE_INFO       0x00000010
1475 #define SECTION_TYPE_MMIO       0x00000800
1476 #define SECTION_TYPE_RB_MMIO    0x00001800
1477 #define SECTION_TYPE_AQ         0x00000801
1478 #define SECTION_TYPE_RB_AQ      0x00001801
1479 #define SECTION_TYPE_NOTE       0x80000000
1480                 u32 type;
1481                 u32 offset;
1482                 u32 size;
1483         } section;
1484 };
1485
1486 struct i40e_profile_tlv_section_record {
1487         u8 rtype;
1488         u8 type;
1489         u16 len;
1490         u8 data[12];
1491 };
1492
1493 /* Generic AQ section in proflie */
1494 struct i40e_profile_aq_section {
1495         u16 opcode;
1496         u16 flags;
1497         u8  param[16];
1498         u16 datalen;
1499         u8  data[];
1500 };
1501
1502 struct i40e_profile_info {
1503         u32 track_id;
1504         struct i40e_ddp_version version;
1505         u8 op;
1506 #define I40E_DDP_ADD_TRACKID            0x01
1507 #define I40E_DDP_REMOVE_TRACKID 0x02
1508         u8 reserved[7];
1509         u8 name[I40E_DDP_NAME_SIZE];
1510 };
1511 #endif /* _I40E_TYPE_H_ */