1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2015 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
35 #include "i40e_lan_hmc.h"
36 #include "i40e_devids.h"
38 /* I40E_MASK is a macro used on 32 bit registers */
39 #define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
41 #define I40E_MAX_VSI_QP 16
42 #define I40E_MAX_VF_VSI 3
43 #define I40E_MAX_CHAINED_RX_BUFFERS 5
44 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
46 /* Max default timeout in ms, */
47 #define I40E_MAX_NVM_TIMEOUT 18000
49 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
50 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
52 /* forward declaration */
54 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
56 /* Data type manipulation macros. */
58 #define I40E_DESC_UNUSED(R) \
59 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
60 (R)->next_to_clean - (R)->next_to_use - 1)
62 /* bitfields for Tx queue mapping in QTX_CTL */
63 #define I40E_QTX_CTL_VF_QUEUE 0x0
64 #define I40E_QTX_CTL_VM_QUEUE 0x1
65 #define I40E_QTX_CTL_PF_QUEUE 0x2
67 /* debug masks - set these bits in hw->debug_mask to control output */
68 enum i40e_debug_mask {
69 I40E_DEBUG_INIT = 0x00000001,
70 I40E_DEBUG_RELEASE = 0x00000002,
72 I40E_DEBUG_LINK = 0x00000010,
73 I40E_DEBUG_PHY = 0x00000020,
74 I40E_DEBUG_HMC = 0x00000040,
75 I40E_DEBUG_NVM = 0x00000080,
76 I40E_DEBUG_LAN = 0x00000100,
77 I40E_DEBUG_FLOW = 0x00000200,
78 I40E_DEBUG_DCB = 0x00000400,
79 I40E_DEBUG_DIAG = 0x00000800,
80 I40E_DEBUG_FD = 0x00001000,
81 I40E_DEBUG_PACKAGE = 0x00002000,
82 I40E_DEBUG_IWARP = 0x00F00000,
83 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
84 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
85 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
86 I40E_DEBUG_AQ_COMMAND = 0x06000000,
87 I40E_DEBUG_AQ = 0x0F000000,
89 I40E_DEBUG_USER = 0xF0000000,
91 I40E_DEBUG_ALL = 0xFFFFFFFF
94 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
95 I40E_GLGEN_MSCA_STCODE_SHIFT)
96 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
97 I40E_GLGEN_MSCA_OPCODE_SHIFT)
98 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
99 I40E_GLGEN_MSCA_OPCODE_SHIFT)
101 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
102 I40E_GLGEN_MSCA_STCODE_SHIFT)
103 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
104 I40E_GLGEN_MSCA_OPCODE_SHIFT)
105 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
106 I40E_GLGEN_MSCA_OPCODE_SHIFT)
107 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
108 I40E_GLGEN_MSCA_OPCODE_SHIFT)
109 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
110 I40E_GLGEN_MSCA_OPCODE_SHIFT)
112 #define I40E_PHY_COM_REG_PAGE 0x1E
113 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
114 #define I40E_PHY_LED_MANUAL_ON 0x100
115 #define I40E_PHY_LED_PROV_REG_1 0xC430
116 #define I40E_PHY_LED_MODE_MASK 0xFFFF
117 #define I40E_PHY_LED_MODE_ORIG 0x80000000
119 /* These are structs for managing the hardware information and the operations.
120 * The structures of function pointers are filled out at init time when we
121 * know for sure exactly which hardware we're working with. This gives us the
122 * flexibility of using the same main driver code but adapting to slightly
123 * different hardware needs as new parts are developed. For this architecture,
124 * the Firmware and AdminQ are intended to insulate the driver from most of the
125 * future changes, but these structures will also do part of the job.
128 I40E_MAC_UNKNOWN = 0,
136 enum i40e_media_type {
137 I40E_MEDIA_TYPE_UNKNOWN = 0,
138 I40E_MEDIA_TYPE_FIBER,
139 I40E_MEDIA_TYPE_BASET,
140 I40E_MEDIA_TYPE_BACKPLANE,
143 I40E_MEDIA_TYPE_VIRTUAL
155 enum i40e_set_fc_aq_failures {
156 I40E_SET_FC_AQ_FAIL_NONE = 0,
157 I40E_SET_FC_AQ_FAIL_GET = 1,
158 I40E_SET_FC_AQ_FAIL_SET = 2,
159 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
160 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
173 I40E_VSI_TYPE_UNKNOWN
176 enum i40e_queue_type {
177 I40E_QUEUE_TYPE_RX = 0,
179 I40E_QUEUE_TYPE_PE_CEQ,
180 I40E_QUEUE_TYPE_UNKNOWN
183 struct i40e_link_status {
184 enum i40e_aq_phy_type phy_type;
185 enum i40e_aq_link_speed link_speed;
192 /* is Link Status Event notification to SW enabled */
199 /* 1st byte: module identifier */
200 #define I40E_MODULE_TYPE_SFP 0x03
201 #define I40E_MODULE_TYPE_QSFP 0x0D
202 /* 2nd byte: ethernet compliance codes for 10/40G */
203 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
204 #define I40E_MODULE_TYPE_40G_LR4 0x02
205 #define I40E_MODULE_TYPE_40G_SR4 0x04
206 #define I40E_MODULE_TYPE_40G_CR4 0x08
207 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
208 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
209 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
210 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
211 /* 3rd byte: ethernet compliance codes for 1G */
212 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
213 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
214 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
215 #define I40E_MODULE_TYPE_1000BASE_T 0x08
218 struct i40e_phy_info {
219 struct i40e_link_status link_info;
220 struct i40e_link_status link_info_old;
222 enum i40e_media_type media_type;
223 /* all the phy types the NVM is capable of */
227 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
228 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
229 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
230 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
231 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
232 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
233 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
234 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
235 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
236 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
237 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
238 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
239 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
240 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
241 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
242 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
243 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
244 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
245 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
246 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
247 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
248 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
249 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
250 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
251 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
252 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
253 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
254 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
255 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
256 /* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
257 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
258 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
259 * a shift is needed to adjust for this with values larger than 31. The
260 * only affected values are I40E_PHY_TYPE_25GBASE_*.
262 #define I40E_PHY_TYPE_OFFSET 1
263 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
264 I40E_PHY_TYPE_OFFSET)
265 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
266 I40E_PHY_TYPE_OFFSET)
267 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
268 I40E_PHY_TYPE_OFFSET)
269 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
270 I40E_PHY_TYPE_OFFSET)
271 #define I40E_HW_CAP_MAX_GPIO 30
272 /* Capabilities of a PF or a VF or the whole device */
273 struct i40e_hw_capabilities {
275 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
276 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
277 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
280 u32 mng_protocols_over_mctp;
281 #define I40E_MNG_PROTOCOL_PLDM 0x2
282 #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
283 #define I40E_MNG_PROTOCOL_NCSI 0x8
289 bool evb_802_1_qbg; /* Edge Virtual Bridging */
290 bool evb_802_1_qbh; /* Bridge Port Extension */
293 bool iscsi; /* Indicates iSCSI enabled */
297 #define I40E_FLEX10_MODE_UNKNOWN 0x0
298 #define I40E_FLEX10_MODE_DCC 0x1
299 #define I40E_FLEX10_MODE_DCI 0x2
302 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
303 #define I40E_FLEX10_STATUS_VC_MODE 0x2
305 bool sec_rev_disabled;
306 bool update_disabled;
307 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
308 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
314 u32 fd_filters_guaranteed;
315 u32 fd_filters_best_effort;
318 u32 rss_table_entry_width;
319 bool led[I40E_HW_CAP_MAX_GPIO];
320 bool sdp[I40E_HW_CAP_MAX_GPIO];
322 u32 num_flow_director_filters;
329 u32 num_msix_vectors;
330 u32 num_msix_vectors_vf;
341 struct i40e_mac_info {
342 enum i40e_mac_type type;
344 u8 perm_addr[ETH_ALEN];
345 u8 san_addr[ETH_ALEN];
346 u8 port_addr[ETH_ALEN];
350 enum i40e_aq_resources_ids {
351 I40E_NVM_RESOURCE_ID = 1
354 enum i40e_aq_resource_access_type {
355 I40E_RESOURCE_READ = 1,
359 struct i40e_nvm_info {
360 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
361 u32 timeout; /* [ms] */
362 u16 sr_size; /* Shadow RAM size in words */
363 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
364 u16 version; /* NVM package version */
365 u32 eetrack; /* NVM data version */
366 u32 oem_ver; /* OEM version info */
369 /* definitions used in NVM update support */
371 enum i40e_nvmupd_cmd {
373 I40E_NVMUPD_READ_CON,
374 I40E_NVMUPD_READ_SNT,
375 I40E_NVMUPD_READ_LCB,
377 I40E_NVMUPD_WRITE_ERA,
378 I40E_NVMUPD_WRITE_CON,
379 I40E_NVMUPD_WRITE_SNT,
380 I40E_NVMUPD_WRITE_LCB,
381 I40E_NVMUPD_WRITE_SA,
382 I40E_NVMUPD_CSUM_CON,
384 I40E_NVMUPD_CSUM_LCB,
387 I40E_NVMUPD_GET_AQ_RESULT,
390 enum i40e_nvmupd_state {
391 I40E_NVMUPD_STATE_INIT,
392 I40E_NVMUPD_STATE_READING,
393 I40E_NVMUPD_STATE_WRITING,
394 I40E_NVMUPD_STATE_INIT_WAIT,
395 I40E_NVMUPD_STATE_WRITE_WAIT,
396 I40E_NVMUPD_STATE_ERROR
399 /* nvm_access definition and its masks/shifts need to be accessible to
400 * application, core driver, and shared code. Where is the right file?
402 #define I40E_NVM_READ 0xB
403 #define I40E_NVM_WRITE 0xC
405 #define I40E_NVM_MOD_PNT_MASK 0xFF
407 #define I40E_NVM_TRANS_SHIFT 8
408 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
409 #define I40E_NVM_CON 0x0
410 #define I40E_NVM_SNT 0x1
411 #define I40E_NVM_LCB 0x2
412 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
413 #define I40E_NVM_ERA 0x4
414 #define I40E_NVM_CSUM 0x8
415 #define I40E_NVM_EXEC 0xf
417 #define I40E_NVM_ADAPT_SHIFT 16
418 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
420 #define I40E_NVMUPD_MAX_DATA 4096
421 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
423 struct i40e_nvm_access {
426 u32 offset; /* in bytes */
427 u32 data_size; /* in bytes */
433 i40e_bus_type_unknown = 0,
436 i40e_bus_type_pci_express,
437 i40e_bus_type_reserved
441 enum i40e_bus_speed {
442 i40e_bus_speed_unknown = 0,
443 i40e_bus_speed_33 = 33,
444 i40e_bus_speed_66 = 66,
445 i40e_bus_speed_100 = 100,
446 i40e_bus_speed_120 = 120,
447 i40e_bus_speed_133 = 133,
448 i40e_bus_speed_2500 = 2500,
449 i40e_bus_speed_5000 = 5000,
450 i40e_bus_speed_8000 = 8000,
451 i40e_bus_speed_reserved
455 enum i40e_bus_width {
456 i40e_bus_width_unknown = 0,
457 i40e_bus_width_pcie_x1 = 1,
458 i40e_bus_width_pcie_x2 = 2,
459 i40e_bus_width_pcie_x4 = 4,
460 i40e_bus_width_pcie_x8 = 8,
461 i40e_bus_width_32 = 32,
462 i40e_bus_width_64 = 64,
463 i40e_bus_width_reserved
467 struct i40e_bus_info {
468 enum i40e_bus_speed speed;
469 enum i40e_bus_width width;
470 enum i40e_bus_type type;
478 /* Flow control (FC) parameters */
479 struct i40e_fc_info {
480 enum i40e_fc_mode current_mode; /* FC mode in effect */
481 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
484 #define I40E_MAX_TRAFFIC_CLASS 8
485 #define I40E_MAX_USER_PRIORITY 8
486 #define I40E_DCBX_MAX_APPS 32
487 #define I40E_LLDPDU_SIZE 1500
488 #define I40E_TLV_STATUS_OPER 0x1
489 #define I40E_TLV_STATUS_SYNC 0x2
490 #define I40E_TLV_STATUS_ERR 0x4
491 #define I40E_CEE_OPER_MAX_APPS 3
492 #define I40E_APP_PROTOID_FCOE 0x8906
493 #define I40E_APP_PROTOID_ISCSI 0x0cbc
494 #define I40E_APP_PROTOID_FIP 0x8914
495 #define I40E_APP_SEL_ETHTYPE 0x1
496 #define I40E_APP_SEL_TCPIP 0x2
497 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
498 #define I40E_CEE_APP_SEL_TCPIP 0x1
500 /* CEE or IEEE 802.1Qaz ETS Configuration data */
501 struct i40e_dcb_ets_config {
505 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
506 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
507 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
510 /* CEE or IEEE 802.1Qaz PFC Configuration data */
511 struct i40e_dcb_pfc_config {
518 /* CEE or IEEE 802.1Qaz Application Priority data */
519 struct i40e_dcb_app_priority_table {
525 struct i40e_dcbx_config {
527 #define I40E_DCBX_MODE_CEE 0x1
528 #define I40E_DCBX_MODE_IEEE 0x2
530 #define I40E_DCBX_APPS_NON_WILLING 0x1
532 u32 tlv_status; /* CEE mode TLV status */
533 struct i40e_dcb_ets_config etscfg;
534 struct i40e_dcb_ets_config etsrec;
535 struct i40e_dcb_pfc_config pfc;
536 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
539 /* Port hardware description */
544 /* subsystem structs */
545 struct i40e_phy_info phy;
546 struct i40e_mac_info mac;
547 struct i40e_bus_info bus;
548 struct i40e_nvm_info nvm;
549 struct i40e_fc_info fc;
554 u16 subsystem_device_id;
555 u16 subsystem_vendor_id;
558 bool adapter_stopped;
560 /* capabilities for entire device and PCI func */
561 struct i40e_hw_capabilities dev_caps;
562 struct i40e_hw_capabilities func_caps;
564 /* Flow Director shared filter space */
565 u16 fdir_shared_filter_count;
567 /* device profile info */
571 /* for multi-function MACs */
576 /* Closest numa node to the device */
579 /* Admin Queue info */
580 struct i40e_adminq_info aq;
582 /* state of nvm update process */
583 enum i40e_nvmupd_state nvmupd_state;
584 struct i40e_aq_desc nvm_wb_desc;
585 struct i40e_virt_mem nvm_buff;
586 bool nvm_release_on_done;
590 struct i40e_hmc_info hmc; /* HMC info struct */
592 /* LLDP/DCBX Status */
596 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
597 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
598 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
600 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
608 static inline bool i40e_is_vf(struct i40e_hw *hw)
610 return (hw->mac.type == I40E_MAC_VF ||
611 hw->mac.type == I40E_MAC_X722_VF);
614 struct i40e_driver_version {
619 u8 driver_string[32];
623 union i40e_16byte_rx_desc {
625 __le64 pkt_addr; /* Packet buffer address */
626 __le64 hdr_addr; /* Header buffer address */
632 __le16 mirroring_status;
638 __le32 rss; /* RSS Hash */
639 __le32 fd_id; /* Flow director filter id */
640 __le32 fcoe_param; /* FCoE DDP Context id */
644 /* ext status/error/pktype/length */
645 __le64 status_error_len;
647 } wb; /* writeback */
650 union i40e_32byte_rx_desc {
652 __le64 pkt_addr; /* Packet buffer address */
653 __le64 hdr_addr; /* Header buffer address */
654 /* bit 0 of hdr_buffer_addr is DD bit */
662 __le16 mirroring_status;
668 __le32 rss; /* RSS Hash */
669 __le32 fcoe_param; /* FCoE DDP Context id */
670 /* Flow director filter id in case of
671 * Programming status desc WB
677 /* status/error/pktype/length */
678 __le64 status_error_len;
681 __le16 ext_status; /* extended status */
688 __le32 flex_bytes_lo;
692 __le32 flex_bytes_hi;
696 } wb; /* writeback */
699 enum i40e_rx_desc_status_bits {
700 /* Note: These are predefined bit offsets */
701 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
702 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
703 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
704 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
705 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
706 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
707 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
708 /* Note: Bit 8 is reserved in X710 and XL710 */
709 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
710 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
711 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
712 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
713 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
714 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
715 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
716 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
719 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
720 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
723 #define I40E_RXD_QW1_STATUS_SHIFT 0
724 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
725 << I40E_RXD_QW1_STATUS_SHIFT)
727 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
728 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
729 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
731 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
732 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
733 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
735 enum i40e_rx_desc_fltstat_values {
736 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
737 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
738 I40E_RX_DESC_FLTSTAT_RSV = 2,
739 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
742 #define I40E_RXD_QW1_ERROR_SHIFT 19
743 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
745 enum i40e_rx_desc_error_bits {
746 /* Note: These are predefined bit offsets */
747 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
748 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
749 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
750 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
751 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
752 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
753 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
754 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
755 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
758 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
759 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
760 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
761 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
762 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
763 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
766 #define I40E_RXD_QW1_PTYPE_SHIFT 30
767 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
769 /* Packet type non-ip values */
770 enum i40e_rx_l2_ptype {
771 I40E_RX_PTYPE_L2_RESERVED = 0,
772 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
773 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
774 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
775 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
776 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
777 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
778 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
779 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
780 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
781 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
782 I40E_RX_PTYPE_L2_ARP = 11,
783 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
784 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
785 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
786 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
787 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
788 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
789 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
790 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
791 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
792 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
793 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
794 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
795 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
796 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
799 struct i40e_rx_ptype_decoded {
806 u32 tunnel_end_prot:2;
807 u32 tunnel_end_frag:1;
812 enum i40e_rx_ptype_outer_ip {
813 I40E_RX_PTYPE_OUTER_L2 = 0,
814 I40E_RX_PTYPE_OUTER_IP = 1
817 enum i40e_rx_ptype_outer_ip_ver {
818 I40E_RX_PTYPE_OUTER_NONE = 0,
819 I40E_RX_PTYPE_OUTER_IPV4 = 0,
820 I40E_RX_PTYPE_OUTER_IPV6 = 1
823 enum i40e_rx_ptype_outer_fragmented {
824 I40E_RX_PTYPE_NOT_FRAG = 0,
825 I40E_RX_PTYPE_FRAG = 1
828 enum i40e_rx_ptype_tunnel_type {
829 I40E_RX_PTYPE_TUNNEL_NONE = 0,
830 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
831 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
832 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
833 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
836 enum i40e_rx_ptype_tunnel_end_prot {
837 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
838 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
839 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
842 enum i40e_rx_ptype_inner_prot {
843 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
844 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
845 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
846 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
847 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
848 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
851 enum i40e_rx_ptype_payload_layer {
852 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
853 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
854 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
855 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
858 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
859 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
860 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
862 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
863 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
864 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
866 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
867 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
869 enum i40e_rx_desc_ext_status_bits {
870 /* Note: These are predefined bit offsets */
871 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
872 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
873 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
874 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
875 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
876 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
877 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
880 enum i40e_rx_desc_pe_status_bits {
881 /* Note: These are predefined bit offsets */
882 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
883 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
884 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
885 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
886 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
887 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
888 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
889 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
890 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
893 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
894 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
896 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
897 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
898 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
900 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
901 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
902 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
904 enum i40e_rx_prog_status_desc_status_bits {
905 /* Note: These are predefined bit offsets */
906 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
907 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
910 enum i40e_rx_prog_status_desc_prog_id_masks {
911 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
912 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
913 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
916 enum i40e_rx_prog_status_desc_error_bits {
917 /* Note: These are predefined bit offsets */
918 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
919 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
920 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
921 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
925 struct i40e_tx_desc {
926 __le64 buffer_addr; /* Address of descriptor's data buf */
927 __le64 cmd_type_offset_bsz;
930 #define I40E_TXD_QW1_DTYPE_SHIFT 0
931 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
933 enum i40e_tx_desc_dtype_value {
934 I40E_TX_DESC_DTYPE_DATA = 0x0,
935 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
936 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
937 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
938 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
939 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
940 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
941 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
942 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
943 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
946 #define I40E_TXD_QW1_CMD_SHIFT 4
947 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
949 enum i40e_tx_desc_cmd_bits {
950 I40E_TX_DESC_CMD_EOP = 0x0001,
951 I40E_TX_DESC_CMD_RS = 0x0002,
952 I40E_TX_DESC_CMD_ICRC = 0x0004,
953 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
954 I40E_TX_DESC_CMD_DUMMY = 0x0010,
955 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
956 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
957 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
958 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
959 I40E_TX_DESC_CMD_FCOET = 0x0080,
960 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
961 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
962 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
963 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
964 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
965 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
966 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
967 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
970 #define I40E_TXD_QW1_OFFSET_SHIFT 16
971 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
972 I40E_TXD_QW1_OFFSET_SHIFT)
974 enum i40e_tx_desc_length_fields {
975 /* Note: These are predefined bit offsets */
976 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
977 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
978 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
981 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
982 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
983 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
985 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
986 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
988 /* Context descriptors */
989 struct i40e_tx_context_desc {
990 __le32 tunneling_params;
993 __le64 type_cmd_tso_mss;
996 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
997 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
999 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1000 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1002 enum i40e_tx_ctx_desc_cmd_bits {
1003 I40E_TX_CTX_DESC_TSO = 0x01,
1004 I40E_TX_CTX_DESC_TSYN = 0x02,
1005 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1006 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1007 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1008 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1009 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1010 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1011 I40E_TX_CTX_DESC_SWPE = 0x40
1014 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1015 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1016 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1018 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1019 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1020 I40E_TXD_CTX_QW1_MSS_SHIFT)
1022 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1023 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1025 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1026 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1027 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1029 enum i40e_tx_ctx_desc_eipt_offload {
1030 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1031 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1032 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1033 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1036 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1037 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1038 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1040 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1041 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1043 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1044 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1046 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1047 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
1048 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1050 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1052 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1053 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1054 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1056 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1057 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1058 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1060 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1061 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1062 struct i40e_filter_program_desc {
1063 __le32 qindex_flex_ptype_vsi;
1065 __le32 dtype_cmd_cntindex;
1068 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1069 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1070 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1071 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1072 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1073 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1074 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1075 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1076 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1078 /* Packet Classifier Types for filters */
1079 enum i40e_filter_pctype {
1080 /* Note: Values 0-28 are reserved for future use.
1081 * Value 29, 30, 32 are not supported on XL710 and X710.
1083 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1084 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1085 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1086 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1087 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1088 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1089 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1090 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1091 /* Note: Values 37-38 are reserved for future use.
1092 * Value 39, 40, 42 are not supported on XL710 and X710.
1094 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1095 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1096 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1097 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1098 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1099 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1100 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1101 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1102 /* Note: Value 47 is reserved for future use */
1103 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1104 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1105 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1106 /* Note: Values 51-62 are reserved for future use */
1107 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1110 enum i40e_filter_program_desc_dest {
1111 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1112 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1113 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1116 enum i40e_filter_program_desc_fd_status {
1117 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1118 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1119 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1120 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1123 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1124 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1125 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1127 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1128 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1129 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1131 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1132 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1134 enum i40e_filter_program_desc_pcmd {
1135 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1136 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1139 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1140 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1142 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1143 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1145 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1146 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1147 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1148 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1150 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1151 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1152 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1154 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1155 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1156 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1158 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1159 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1160 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1162 enum i40e_filter_type {
1163 I40E_FLOW_DIRECTOR_FLTR = 0,
1164 I40E_PE_QUAD_HASH_FLTR = 1,
1165 I40E_ETHERTYPE_FLTR,
1171 struct i40e_vsi_context {
1176 u16 vsis_unallocated;
1181 struct i40e_aqc_vsi_properties_data info;
1184 struct i40e_veb_context {
1189 u16 vebs_unallocated;
1191 struct i40e_aqc_get_veb_parameters_completion info;
1194 /* Statistics collected by each port, VSI, VEB, and S-channel */
1195 struct i40e_eth_stats {
1196 u64 rx_bytes; /* gorc */
1197 u64 rx_unicast; /* uprc */
1198 u64 rx_multicast; /* mprc */
1199 u64 rx_broadcast; /* bprc */
1200 u64 rx_discards; /* rdpc */
1201 u64 rx_unknown_protocol; /* rupp */
1202 u64 tx_bytes; /* gotc */
1203 u64 tx_unicast; /* uptc */
1204 u64 tx_multicast; /* mptc */
1205 u64 tx_broadcast; /* bptc */
1206 u64 tx_discards; /* tdpc */
1207 u64 tx_errors; /* tepc */
1210 /* Statistics collected per VEB per TC */
1211 struct i40e_veb_tc_stats {
1212 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1213 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1214 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1215 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1218 /* Statistics collected by the MAC */
1219 struct i40e_hw_port_stats {
1220 /* eth stats collected by the port */
1221 struct i40e_eth_stats eth;
1223 /* additional port specific stats */
1224 u64 tx_dropped_link_down; /* tdold */
1225 u64 crc_errors; /* crcerrs */
1226 u64 illegal_bytes; /* illerrc */
1227 u64 error_bytes; /* errbc */
1228 u64 mac_local_faults; /* mlfc */
1229 u64 mac_remote_faults; /* mrfc */
1230 u64 rx_length_errors; /* rlec */
1231 u64 link_xon_rx; /* lxonrxc */
1232 u64 link_xoff_rx; /* lxoffrxc */
1233 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1234 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1235 u64 link_xon_tx; /* lxontxc */
1236 u64 link_xoff_tx; /* lxofftxc */
1237 u64 priority_xon_tx[8]; /* pxontxc[8] */
1238 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1239 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1240 u64 rx_size_64; /* prc64 */
1241 u64 rx_size_127; /* prc127 */
1242 u64 rx_size_255; /* prc255 */
1243 u64 rx_size_511; /* prc511 */
1244 u64 rx_size_1023; /* prc1023 */
1245 u64 rx_size_1522; /* prc1522 */
1246 u64 rx_size_big; /* prc9522 */
1247 u64 rx_undersize; /* ruc */
1248 u64 rx_fragments; /* rfc */
1249 u64 rx_oversize; /* roc */
1250 u64 rx_jabber; /* rjc */
1251 u64 tx_size_64; /* ptc64 */
1252 u64 tx_size_127; /* ptc127 */
1253 u64 tx_size_255; /* ptc255 */
1254 u64 tx_size_511; /* ptc511 */
1255 u64 tx_size_1023; /* ptc1023 */
1256 u64 tx_size_1522; /* ptc1522 */
1257 u64 tx_size_big; /* ptc9522 */
1258 u64 mac_short_packet_dropped; /* mspdc */
1259 u64 checksum_error; /* xec */
1260 /* flow director stats */
1263 u64 fd_atr_tunnel_match;
1269 u64 tx_lpi_count; /* etlpic */
1270 u64 rx_lpi_count; /* erlpic */
1273 /* Checksum and Shadow RAM pointers */
1274 #define I40E_SR_NVM_CONTROL_WORD 0x00
1275 #define I40E_SR_EMP_MODULE_PTR 0x0F
1276 #define I40E_SR_PBA_FLAGS 0x15
1277 #define I40E_SR_PBA_BLOCK_PTR 0x16
1278 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1279 #define I40E_NVM_OEM_VER_OFF 0x83
1280 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1281 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1282 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1283 #define I40E_SR_NVM_EETRACK_LO 0x2D
1284 #define I40E_SR_NVM_EETRACK_HI 0x2E
1285 #define I40E_SR_VPD_PTR 0x2F
1286 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1287 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1289 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1290 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1291 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1292 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1293 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1295 /* Shadow RAM related */
1296 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1297 #define I40E_SR_WORDS_IN_1KB 512
1298 /* Checksum should be calculated such that after adding all the words,
1299 * including the checksum word itself, the sum should be 0xBABA.
1301 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1303 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1305 enum i40e_switch_element_types {
1306 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1307 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1308 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1309 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1310 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1311 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1312 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1313 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1314 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1317 /* Supported EtherType filters */
1318 enum i40e_ether_type_index {
1319 I40E_ETHER_TYPE_1588 = 0,
1320 I40E_ETHER_TYPE_FIP = 1,
1321 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1322 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1323 I40E_ETHER_TYPE_LLDP = 4,
1324 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1325 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1326 I40E_ETHER_TYPE_QCN_CNM = 7,
1327 I40E_ETHER_TYPE_8021X = 8,
1328 I40E_ETHER_TYPE_ARP = 9,
1329 I40E_ETHER_TYPE_RSV1 = 10,
1330 I40E_ETHER_TYPE_RSV2 = 11,
1333 /* Filter context base size is 1K */
1334 #define I40E_HASH_FILTER_BASE_SIZE 1024
1335 /* Supported Hash filter values */
1336 enum i40e_hash_filter_size {
1337 I40E_HASH_FILTER_SIZE_1K = 0,
1338 I40E_HASH_FILTER_SIZE_2K = 1,
1339 I40E_HASH_FILTER_SIZE_4K = 2,
1340 I40E_HASH_FILTER_SIZE_8K = 3,
1341 I40E_HASH_FILTER_SIZE_16K = 4,
1342 I40E_HASH_FILTER_SIZE_32K = 5,
1343 I40E_HASH_FILTER_SIZE_64K = 6,
1344 I40E_HASH_FILTER_SIZE_128K = 7,
1345 I40E_HASH_FILTER_SIZE_256K = 8,
1346 I40E_HASH_FILTER_SIZE_512K = 9,
1347 I40E_HASH_FILTER_SIZE_1M = 10,
1350 /* DMA context base size is 0.5K */
1351 #define I40E_DMA_CNTX_BASE_SIZE 512
1352 /* Supported DMA context values */
1353 enum i40e_dma_cntx_size {
1354 I40E_DMA_CNTX_SIZE_512 = 0,
1355 I40E_DMA_CNTX_SIZE_1K = 1,
1356 I40E_DMA_CNTX_SIZE_2K = 2,
1357 I40E_DMA_CNTX_SIZE_4K = 3,
1358 I40E_DMA_CNTX_SIZE_8K = 4,
1359 I40E_DMA_CNTX_SIZE_16K = 5,
1360 I40E_DMA_CNTX_SIZE_32K = 6,
1361 I40E_DMA_CNTX_SIZE_64K = 7,
1362 I40E_DMA_CNTX_SIZE_128K = 8,
1363 I40E_DMA_CNTX_SIZE_256K = 9,
1366 /* Supported Hash look up table (LUT) sizes */
1367 enum i40e_hash_lut_size {
1368 I40E_HASH_LUT_SIZE_128 = 0,
1369 I40E_HASH_LUT_SIZE_512 = 1,
1372 /* Structure to hold a per PF filter control settings */
1373 struct i40e_filter_control_settings {
1374 /* number of PE Quad Hash filter buckets */
1375 enum i40e_hash_filter_size pe_filt_num;
1376 /* number of PE Quad Hash contexts */
1377 enum i40e_dma_cntx_size pe_cntx_num;
1378 /* number of FCoE filter buckets */
1379 enum i40e_hash_filter_size fcoe_filt_num;
1380 /* number of FCoE DDP contexts */
1381 enum i40e_dma_cntx_size fcoe_cntx_num;
1382 /* size of the Hash LUT */
1383 enum i40e_hash_lut_size hash_lut_size;
1384 /* enable FDIR filters for PF and its VFs */
1386 /* enable Ethertype filters for PF and its VFs */
1387 bool enable_ethtype;
1388 /* enable MAC/VLAN filters for PF and its VFs */
1389 bool enable_macvlan;
1392 /* Structure to hold device level control filter counts */
1393 struct i40e_control_filter_stats {
1394 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1395 u16 etype_used; /* Used perfect EtherType filters */
1396 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1397 u16 etype_free; /* Un-used perfect EtherType filters */
1400 enum i40e_reset_type {
1402 I40E_RESET_CORER = 1,
1403 I40E_RESET_GLOBR = 2,
1404 I40E_RESET_EMPR = 3,
1407 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1408 #define I40E_NVM_LLDP_CFG_PTR 0xD
1409 struct i40e_lldp_variables {
1419 /* Offsets into Alternate Ram */
1420 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1421 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1422 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1423 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1424 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1425 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1427 /* Alternate Ram Bandwidth Masks */
1428 #define I40E_ALT_BW_VALUE_MASK 0xFF
1429 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1430 #define I40E_ALT_BW_VALID_MASK 0x80000000
1432 /* RSS Hash Table Size */
1433 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1435 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1436 #define I40E_X722_L3_SRC_SHIFT 49
1437 #define I40E_X722_L3_SRC_MASK (0x3ULL << I40E_X722_L3_SRC_SHIFT)
1438 #define I40E_X722_L3_DST_SHIFT 41
1439 #define I40E_X722_L3_DST_MASK (0x3ULL << I40E_X722_L3_DST_SHIFT)
1440 #define I40E_L3_SRC_SHIFT 47
1441 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1442 #define I40E_L3_V6_SRC_SHIFT 43
1443 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1444 #define I40E_L3_DST_SHIFT 35
1445 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1446 #define I40E_L3_V6_DST_SHIFT 35
1447 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1448 #define I40E_L4_SRC_SHIFT 34
1449 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1450 #define I40E_L4_DST_SHIFT 33
1451 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1452 #define I40E_VERIFY_TAG_SHIFT 31
1453 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1455 #define I40E_FLEX_50_SHIFT 13
1456 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1457 #define I40E_FLEX_51_SHIFT 12
1458 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1459 #define I40E_FLEX_52_SHIFT 11
1460 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1461 #define I40E_FLEX_53_SHIFT 10
1462 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1463 #define I40E_FLEX_54_SHIFT 9
1464 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1465 #define I40E_FLEX_55_SHIFT 8
1466 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1467 #define I40E_FLEX_56_SHIFT 7
1468 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1469 #define I40E_FLEX_57_SHIFT 6
1470 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1472 /* Version format for PPP */
1473 struct i40e_ppp_version {
1480 #define I40E_PPP_NAME_SIZE 32
1482 /* Package header */
1483 struct i40e_package_header {
1484 struct i40e_ppp_version version;
1486 u32 segment_offset[1];
1489 /* Generic segment header */
1490 struct i40e_generic_seg_header {
1491 #define SEGMENT_TYPE_METADATA 0x00000001
1492 #define SEGMENT_TYPE_NOTES 0x00000002
1493 #define SEGMENT_TYPE_I40E 0x00000011
1494 #define SEGMENT_TYPE_X722 0x00000012
1496 struct i40e_ppp_version version;
1498 char name[I40E_PPP_NAME_SIZE];
1501 struct i40e_metadata_segment {
1502 struct i40e_generic_seg_header header;
1503 struct i40e_ppp_version version;
1505 char name[I40E_PPP_NAME_SIZE];
1508 struct i40e_device_id_entry {
1510 u32 sub_vendor_dev_id;
1513 struct i40e_profile_segment {
1514 struct i40e_generic_seg_header header;
1515 struct i40e_ppp_version version;
1516 char name[I40E_PPP_NAME_SIZE];
1517 u32 device_table_count;
1518 struct i40e_device_id_entry device_table[1];
1521 struct i40e_section_table {
1523 u32 section_offset[1];
1526 struct i40e_profile_section_header {
1530 #define SECTION_TYPE_INFO 0x00000010
1531 #define SECTION_TYPE_MMIO 0x00000800
1532 #define SECTION_TYPE_AQ 0x00000801
1533 #define SECTION_TYPE_NOTE 0x80000000
1534 #define SECTION_TYPE_NAME 0x80000001
1541 struct i40e_profile_info {
1543 struct i40e_ppp_version version;
1545 #define I40E_PPP_ADD_TRACKID 0x01
1546 #define I40E_PPP_REMOVE_TRACKID 0x02
1548 u8 name[I40E_PPP_NAME_SIZE];
1550 #endif /* _I40E_TYPE_H_ */