1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
7 #include "i40e_status.h"
8 #include "i40e_osdep.h"
9 #include "i40e_register.h"
10 #include "i40e_adminq.h"
12 #include "i40e_lan_hmc.h"
13 #include "i40e_devids.h"
15 /* I40E_MASK is a macro used on 32 bit registers */
16 #define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
18 #define I40E_MAX_VSI_QP 16
19 #define I40E_MAX_VF_VSI 4
20 #define I40E_MAX_CHAINED_RX_BUFFERS 5
21 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
23 /* Max default timeout in ms, */
24 #define I40E_MAX_NVM_TIMEOUT 18000
26 /* Max timeout in ms for the phy to respond */
27 #define I40E_MAX_PHY_TIMEOUT 500
29 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
30 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
32 /* forward declaration */
34 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
36 /* Data type manipulation macros. */
38 #define I40E_DESC_UNUSED(R) \
39 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
40 (R)->next_to_clean - (R)->next_to_use - 1)
42 /* bitfields for Tx queue mapping in QTX_CTL */
43 #define I40E_QTX_CTL_VF_QUEUE 0x0
44 #define I40E_QTX_CTL_VM_QUEUE 0x1
45 #define I40E_QTX_CTL_PF_QUEUE 0x2
47 /* debug masks - set these bits in hw->debug_mask to control output */
48 enum i40e_debug_mask {
49 I40E_DEBUG_INIT = 0x00000001,
50 I40E_DEBUG_RELEASE = 0x00000002,
52 I40E_DEBUG_LINK = 0x00000010,
53 I40E_DEBUG_PHY = 0x00000020,
54 I40E_DEBUG_HMC = 0x00000040,
55 I40E_DEBUG_NVM = 0x00000080,
56 I40E_DEBUG_LAN = 0x00000100,
57 I40E_DEBUG_FLOW = 0x00000200,
58 I40E_DEBUG_DCB = 0x00000400,
59 I40E_DEBUG_DIAG = 0x00000800,
60 I40E_DEBUG_FD = 0x00001000,
61 I40E_DEBUG_PACKAGE = 0x00002000,
62 I40E_DEBUG_IWARP = 0x00F00000,
63 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
64 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
65 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
66 I40E_DEBUG_AQ_COMMAND = 0x06000000,
67 I40E_DEBUG_AQ = 0x0F000000,
69 I40E_DEBUG_USER = 0xF0000000,
71 I40E_DEBUG_ALL = 0xFFFFFFFF
74 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
75 I40E_GLGEN_MSCA_STCODE_SHIFT)
76 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
77 I40E_GLGEN_MSCA_OPCODE_SHIFT)
78 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
79 I40E_GLGEN_MSCA_OPCODE_SHIFT)
81 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
82 I40E_GLGEN_MSCA_STCODE_SHIFT)
83 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
84 I40E_GLGEN_MSCA_OPCODE_SHIFT)
85 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
86 I40E_GLGEN_MSCA_OPCODE_SHIFT)
87 #define I40E_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK I40E_MASK(2, \
88 I40E_GLGEN_MSCA_OPCODE_SHIFT)
89 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
90 I40E_GLGEN_MSCA_OPCODE_SHIFT)
92 #define I40E_PHY_COM_REG_PAGE 0x1E
93 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
94 #define I40E_PHY_LED_MANUAL_ON 0x100
95 #define I40E_PHY_LED_PROV_REG_1 0xC430
96 #define I40E_PHY_LED_MODE_MASK 0xFFFF
97 #define I40E_PHY_LED_MODE_ORIG 0x80000000
99 /* These are structs for managing the hardware information and the operations.
100 * The structures of function pointers are filled out at init time when we
101 * know for sure exactly which hardware we're working with. This gives us the
102 * flexibility of using the same main driver code but adapting to slightly
103 * different hardware needs as new parts are developed. For this architecture,
104 * the Firmware and AdminQ are intended to insulate the driver from most of the
105 * future changes, but these structures will also do part of the job.
108 I40E_MAC_UNKNOWN = 0,
116 enum i40e_media_type {
117 I40E_MEDIA_TYPE_UNKNOWN = 0,
118 I40E_MEDIA_TYPE_FIBER,
119 I40E_MEDIA_TYPE_BASET,
120 I40E_MEDIA_TYPE_BACKPLANE,
123 I40E_MEDIA_TYPE_VIRTUAL
135 enum i40e_set_fc_aq_failures {
136 I40E_SET_FC_AQ_FAIL_NONE = 0,
137 I40E_SET_FC_AQ_FAIL_GET = 1,
138 I40E_SET_FC_AQ_FAIL_SET = 2,
139 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
140 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
153 I40E_VSI_TYPE_UNKNOWN
156 enum i40e_queue_type {
157 I40E_QUEUE_TYPE_RX = 0,
159 I40E_QUEUE_TYPE_PE_CEQ,
160 I40E_QUEUE_TYPE_UNKNOWN
163 struct i40e_link_status {
164 enum i40e_aq_phy_type phy_type;
165 enum i40e_aq_link_speed link_speed;
172 /* is Link Status Event notification to SW enabled */
179 /* 1st byte: module identifier */
180 #define I40E_MODULE_TYPE_SFP 0x03
181 #define I40E_MODULE_TYPE_QSFP 0x0D
182 /* 2nd byte: ethernet compliance codes for 10/40G */
183 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01
184 #define I40E_MODULE_TYPE_40G_LR4 0x02
185 #define I40E_MODULE_TYPE_40G_SR4 0x04
186 #define I40E_MODULE_TYPE_40G_CR4 0x08
187 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10
188 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20
189 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
190 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80
191 /* 3rd byte: ethernet compliance codes for 1G */
192 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
193 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
194 #define I40E_MODULE_TYPE_1000BASE_CX 0x04
195 #define I40E_MODULE_TYPE_1000BASE_T 0x08
198 struct i40e_phy_info {
199 struct i40e_link_status link_info;
200 struct i40e_link_status link_info_old;
202 enum i40e_media_type media_type;
203 /* all the phy types the NVM is capable of */
207 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
208 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
209 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
210 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
211 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
212 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
213 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
214 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
215 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
216 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
217 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
218 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
219 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
220 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
221 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
222 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
223 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
224 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
225 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
226 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
227 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
228 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
229 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
230 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
231 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
232 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
233 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
234 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
235 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
236 /* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
237 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
238 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
239 * a shift is needed to adjust for this with values larger than 31. The
240 * only affected values are I40E_PHY_TYPE_25GBASE_*.
242 #define I40E_PHY_TYPE_OFFSET 1
243 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
244 I40E_PHY_TYPE_OFFSET)
245 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
246 I40E_PHY_TYPE_OFFSET)
247 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
248 I40E_PHY_TYPE_OFFSET)
249 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
250 I40E_PHY_TYPE_OFFSET)
251 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
252 I40E_PHY_TYPE_OFFSET)
253 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
254 I40E_PHY_TYPE_OFFSET)
255 #define I40E_HW_CAP_MAX_GPIO 30
256 /* Capabilities of a PF or a VF or the whole device */
257 struct i40e_hw_capabilities {
259 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
260 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
261 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
263 /* Cloud filter modes:
264 * Mode1: Filter on L4 port only
265 * Mode2: Filter for non-tunneled traffic
266 * Mode3: Filter for tunnel traffic
268 #define I40E_CLOUD_FILTER_MODE1 0x6
269 #define I40E_CLOUD_FILTER_MODE2 0x7
270 #define I40E_CLOUD_FILTER_MODE3 0x8
271 #define I40E_SWITCH_MODE_MASK 0xF
274 u32 mng_protocols_over_mctp;
275 #define I40E_MNG_PROTOCOL_PLDM 0x2
276 #define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
277 #define I40E_MNG_PROTOCOL_NCSI 0x8
283 bool evb_802_1_qbg; /* Edge Virtual Bridging */
284 bool evb_802_1_qbh; /* Bridge Port Extension */
287 bool iscsi; /* Indicates iSCSI enabled */
291 #define I40E_FLEX10_MODE_UNKNOWN 0x0
292 #define I40E_FLEX10_MODE_DCC 0x1
293 #define I40E_FLEX10_MODE_DCI 0x2
296 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1
297 #define I40E_FLEX10_STATUS_VC_MODE 0x2
299 bool sec_rev_disabled;
300 bool update_disabled;
301 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
302 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
308 u32 fd_filters_guaranteed;
309 u32 fd_filters_best_effort;
312 u32 rss_table_entry_width;
313 bool led[I40E_HW_CAP_MAX_GPIO];
314 bool sdp[I40E_HW_CAP_MAX_GPIO];
316 u32 num_flow_director_filters;
323 u32 num_msix_vectors;
324 u32 num_msix_vectors_vf;
335 struct i40e_mac_info {
336 enum i40e_mac_type type;
338 u8 perm_addr[ETH_ALEN];
339 u8 san_addr[ETH_ALEN];
340 u8 port_addr[ETH_ALEN];
344 enum i40e_aq_resources_ids {
345 I40E_NVM_RESOURCE_ID = 1
348 enum i40e_aq_resource_access_type {
349 I40E_RESOURCE_READ = 1,
353 struct i40e_nvm_info {
354 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
355 u32 timeout; /* [ms] */
356 u16 sr_size; /* Shadow RAM size in words */
357 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
358 u16 version; /* NVM package version */
359 u32 eetrack; /* NVM data version */
360 u32 oem_ver; /* OEM version info */
363 /* definitions used in NVM update support */
365 enum i40e_nvmupd_cmd {
367 I40E_NVMUPD_READ_CON,
368 I40E_NVMUPD_READ_SNT,
369 I40E_NVMUPD_READ_LCB,
371 I40E_NVMUPD_WRITE_ERA,
372 I40E_NVMUPD_WRITE_CON,
373 I40E_NVMUPD_WRITE_SNT,
374 I40E_NVMUPD_WRITE_LCB,
375 I40E_NVMUPD_WRITE_SA,
376 I40E_NVMUPD_CSUM_CON,
378 I40E_NVMUPD_CSUM_LCB,
381 I40E_NVMUPD_GET_AQ_RESULT,
382 I40E_NVMUPD_GET_AQ_EVENT,
385 enum i40e_nvmupd_state {
386 I40E_NVMUPD_STATE_INIT,
387 I40E_NVMUPD_STATE_READING,
388 I40E_NVMUPD_STATE_WRITING,
389 I40E_NVMUPD_STATE_INIT_WAIT,
390 I40E_NVMUPD_STATE_WRITE_WAIT,
391 I40E_NVMUPD_STATE_ERROR
394 /* nvm_access definition and its masks/shifts need to be accessible to
395 * application, core driver, and shared code. Where is the right file?
397 #define I40E_NVM_READ 0xB
398 #define I40E_NVM_WRITE 0xC
400 #define I40E_NVM_MOD_PNT_MASK 0xFF
402 #define I40E_NVM_TRANS_SHIFT 8
403 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
404 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12
405 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
406 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
407 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01
408 #define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02
409 #define I40E_NVM_CON 0x0
410 #define I40E_NVM_SNT 0x1
411 #define I40E_NVM_LCB 0x2
412 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
413 #define I40E_NVM_ERA 0x4
414 #define I40E_NVM_CSUM 0x8
415 #define I40E_NVM_AQE 0xe
416 #define I40E_NVM_EXEC 0xf
418 #define I40E_NVM_ADAPT_SHIFT 16
419 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
421 #define I40E_NVMUPD_MAX_DATA 4096
422 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
424 struct i40e_nvm_access {
427 u32 offset; /* in bytes */
428 u32 data_size; /* in bytes */
432 /* (Q)SFP module access definitions */
433 #define I40E_I2C_EEPROM_DEV_ADDR 0xA0
434 #define I40E_I2C_EEPROM_DEV_ADDR2 0xA2
435 #define I40E_MODULE_TYPE_ADDR 0x00
436 #define I40E_MODULE_REVISION_ADDR 0x01
437 #define I40E_MODULE_SFF_8472_COMP 0x5E
438 #define I40E_MODULE_SFF_8472_SWAP 0x5C
439 #define I40E_MODULE_SFF_ADDR_MODE 0x04
440 #define I40E_MODULE_TYPE_QSFP_PLUS 0x0D
441 #define I40E_MODULE_TYPE_QSFP28 0x11
442 #define I40E_MODULE_QSFP_MAX_LEN 640
446 i40e_bus_type_unknown = 0,
449 i40e_bus_type_pci_express,
450 i40e_bus_type_reserved
454 enum i40e_bus_speed {
455 i40e_bus_speed_unknown = 0,
456 i40e_bus_speed_33 = 33,
457 i40e_bus_speed_66 = 66,
458 i40e_bus_speed_100 = 100,
459 i40e_bus_speed_120 = 120,
460 i40e_bus_speed_133 = 133,
461 i40e_bus_speed_2500 = 2500,
462 i40e_bus_speed_5000 = 5000,
463 i40e_bus_speed_8000 = 8000,
464 i40e_bus_speed_reserved
468 enum i40e_bus_width {
469 i40e_bus_width_unknown = 0,
470 i40e_bus_width_pcie_x1 = 1,
471 i40e_bus_width_pcie_x2 = 2,
472 i40e_bus_width_pcie_x4 = 4,
473 i40e_bus_width_pcie_x8 = 8,
474 i40e_bus_width_32 = 32,
475 i40e_bus_width_64 = 64,
476 i40e_bus_width_reserved
480 struct i40e_bus_info {
481 enum i40e_bus_speed speed;
482 enum i40e_bus_width width;
483 enum i40e_bus_type type;
491 /* Flow control (FC) parameters */
492 struct i40e_fc_info {
493 enum i40e_fc_mode current_mode; /* FC mode in effect */
494 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
497 #define I40E_MAX_TRAFFIC_CLASS 8
498 #define I40E_MAX_USER_PRIORITY 8
499 #define I40E_DCBX_MAX_APPS 32
500 #define I40E_LLDPDU_SIZE 1500
501 #define I40E_TLV_STATUS_OPER 0x1
502 #define I40E_TLV_STATUS_SYNC 0x2
503 #define I40E_TLV_STATUS_ERR 0x4
504 #define I40E_CEE_OPER_MAX_APPS 3
505 #define I40E_APP_PROTOID_FCOE 0x8906
506 #define I40E_APP_PROTOID_ISCSI 0x0cbc
507 #define I40E_APP_PROTOID_FIP 0x8914
508 #define I40E_APP_SEL_ETHTYPE 0x1
509 #define I40E_APP_SEL_TCPIP 0x2
510 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
511 #define I40E_CEE_APP_SEL_TCPIP 0x1
513 /* CEE or IEEE 802.1Qaz ETS Configuration data */
514 struct i40e_dcb_ets_config {
518 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
519 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
520 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
523 /* CEE or IEEE 802.1Qaz PFC Configuration data */
524 struct i40e_dcb_pfc_config {
531 /* CEE or IEEE 802.1Qaz Application Priority data */
532 struct i40e_dcb_app_priority_table {
538 struct i40e_dcbx_config {
540 #define I40E_DCBX_MODE_CEE 0x1
541 #define I40E_DCBX_MODE_IEEE 0x2
543 #define I40E_DCBX_APPS_NON_WILLING 0x1
545 u32 tlv_status; /* CEE mode TLV status */
546 struct i40e_dcb_ets_config etscfg;
547 struct i40e_dcb_ets_config etsrec;
548 struct i40e_dcb_pfc_config pfc;
549 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
552 /* Port hardware description */
557 /* subsystem structs */
558 struct i40e_phy_info phy;
559 struct i40e_mac_info mac;
560 struct i40e_bus_info bus;
561 struct i40e_nvm_info nvm;
562 struct i40e_fc_info fc;
567 u16 subsystem_device_id;
568 u16 subsystem_vendor_id;
571 bool adapter_stopped;
573 /* capabilities for entire device and PCI func */
574 struct i40e_hw_capabilities dev_caps;
575 struct i40e_hw_capabilities func_caps;
577 /* Flow Director shared filter space */
578 u16 fdir_shared_filter_count;
580 /* device profile info */
584 /* for multi-function MACs */
589 /* Closest numa node to the device */
592 /* Admin Queue info */
593 struct i40e_adminq_info aq;
595 /* state of nvm update process */
596 enum i40e_nvmupd_state nvmupd_state;
597 struct i40e_aq_desc nvm_wb_desc;
598 struct i40e_aq_desc nvm_aq_event_desc;
599 struct i40e_virt_mem nvm_buff;
600 bool nvm_release_on_done;
604 struct i40e_hmc_info hmc; /* HMC info struct */
606 /* LLDP/DCBX Status */
610 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
611 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
612 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
614 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
615 #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
616 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
617 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
620 /* Used in set switch config AQ command */
630 static inline bool i40e_is_vf(struct i40e_hw *hw)
632 return (hw->mac.type == I40E_MAC_VF ||
633 hw->mac.type == I40E_MAC_X722_VF);
636 struct i40e_driver_version {
641 u8 driver_string[32];
645 union i40e_16byte_rx_desc {
647 __le64 pkt_addr; /* Packet buffer address */
648 __le64 hdr_addr; /* Header buffer address */
654 __le16 mirroring_status;
660 __le32 rss; /* RSS Hash */
661 __le32 fd_id; /* Flow director filter id */
662 __le32 fcoe_param; /* FCoE DDP Context id */
666 /* ext status/error/pktype/length */
667 __le64 status_error_len;
669 } wb; /* writeback */
672 union i40e_32byte_rx_desc {
674 __le64 pkt_addr; /* Packet buffer address */
675 __le64 hdr_addr; /* Header buffer address */
676 /* bit 0 of hdr_buffer_addr is DD bit */
684 __le16 mirroring_status;
690 __le32 rss; /* RSS Hash */
691 __le32 fcoe_param; /* FCoE DDP Context id */
692 /* Flow director filter id in case of
693 * Programming status desc WB
699 /* status/error/pktype/length */
700 __le64 status_error_len;
703 __le16 ext_status; /* extended status */
710 __le32 flex_bytes_lo;
714 __le32 flex_bytes_hi;
718 } wb; /* writeback */
721 enum i40e_rx_desc_status_bits {
722 /* Note: These are predefined bit offsets */
723 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
724 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
725 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
726 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
727 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
728 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
729 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
730 /* Note: Bit 8 is reserved in X710 and XL710 */
731 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
732 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
733 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
734 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
735 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
736 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
737 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
738 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
741 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
742 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
745 #define I40E_RXD_QW1_STATUS_SHIFT 0
746 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
747 << I40E_RXD_QW1_STATUS_SHIFT)
749 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
750 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
751 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
753 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
754 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
755 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
757 enum i40e_rx_desc_fltstat_values {
758 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
759 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
760 I40E_RX_DESC_FLTSTAT_RSV = 2,
761 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
764 #define I40E_RXD_QW1_ERROR_SHIFT 19
765 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
767 enum i40e_rx_desc_error_bits {
768 /* Note: These are predefined bit offsets */
769 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
770 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
771 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
772 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
773 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
774 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
775 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
776 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
777 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
780 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
781 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
782 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
783 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
784 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
785 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
788 #define I40E_RXD_QW1_PTYPE_SHIFT 30
789 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
791 /* Packet type non-ip values */
792 enum i40e_rx_l2_ptype {
793 I40E_RX_PTYPE_L2_RESERVED = 0,
794 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
795 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
796 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
797 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
798 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
799 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
800 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
801 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
802 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
803 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
804 I40E_RX_PTYPE_L2_ARP = 11,
805 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
806 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
807 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
808 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
809 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
810 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
811 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
812 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
813 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
814 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
815 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
816 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
817 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
818 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
821 struct i40e_rx_ptype_decoded {
828 u32 tunnel_end_prot:2;
829 u32 tunnel_end_frag:1;
834 enum i40e_rx_ptype_outer_ip {
835 I40E_RX_PTYPE_OUTER_L2 = 0,
836 I40E_RX_PTYPE_OUTER_IP = 1
839 enum i40e_rx_ptype_outer_ip_ver {
840 I40E_RX_PTYPE_OUTER_NONE = 0,
841 I40E_RX_PTYPE_OUTER_IPV4 = 0,
842 I40E_RX_PTYPE_OUTER_IPV6 = 1
845 enum i40e_rx_ptype_outer_fragmented {
846 I40E_RX_PTYPE_NOT_FRAG = 0,
847 I40E_RX_PTYPE_FRAG = 1
850 enum i40e_rx_ptype_tunnel_type {
851 I40E_RX_PTYPE_TUNNEL_NONE = 0,
852 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
853 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
854 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
855 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
858 enum i40e_rx_ptype_tunnel_end_prot {
859 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
860 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
861 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
864 enum i40e_rx_ptype_inner_prot {
865 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
866 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
867 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
868 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
869 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
870 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
873 enum i40e_rx_ptype_payload_layer {
874 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
875 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
876 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
877 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
880 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
881 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
882 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
884 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
885 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
886 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
888 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
889 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
891 enum i40e_rx_desc_ext_status_bits {
892 /* Note: These are predefined bit offsets */
893 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
894 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
895 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
896 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
897 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
898 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
899 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
902 enum i40e_rx_desc_pe_status_bits {
903 /* Note: These are predefined bit offsets */
904 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
905 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
906 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
907 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
908 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
909 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
910 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
911 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
912 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
915 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
916 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
918 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
919 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
920 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
922 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
923 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
924 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
926 enum i40e_rx_prog_status_desc_status_bits {
927 /* Note: These are predefined bit offsets */
928 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
929 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
932 enum i40e_rx_prog_status_desc_prog_id_masks {
933 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
934 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
935 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
938 enum i40e_rx_prog_status_desc_error_bits {
939 /* Note: These are predefined bit offsets */
940 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
941 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
942 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
943 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
947 struct i40e_tx_desc {
948 __le64 buffer_addr; /* Address of descriptor's data buf */
949 __le64 cmd_type_offset_bsz;
952 #define I40E_TXD_QW1_DTYPE_SHIFT 0
953 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
955 enum i40e_tx_desc_dtype_value {
956 I40E_TX_DESC_DTYPE_DATA = 0x0,
957 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
958 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
959 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
960 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
961 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
962 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
963 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
964 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
965 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
968 #define I40E_TXD_QW1_CMD_SHIFT 4
969 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
971 enum i40e_tx_desc_cmd_bits {
972 I40E_TX_DESC_CMD_EOP = 0x0001,
973 I40E_TX_DESC_CMD_RS = 0x0002,
974 I40E_TX_DESC_CMD_ICRC = 0x0004,
975 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
976 I40E_TX_DESC_CMD_DUMMY = 0x0010,
977 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
978 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
979 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
980 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
981 I40E_TX_DESC_CMD_FCOET = 0x0080,
982 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
983 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
984 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
985 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
986 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
987 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
988 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
989 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
992 #define I40E_TXD_QW1_OFFSET_SHIFT 16
993 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
994 I40E_TXD_QW1_OFFSET_SHIFT)
996 enum i40e_tx_desc_length_fields {
997 /* Note: These are predefined bit offsets */
998 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
999 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
1000 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
1003 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
1004 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
1005 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
1007 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
1008 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
1010 /* Context descriptors */
1011 struct i40e_tx_context_desc {
1012 __le32 tunneling_params;
1015 __le64 type_cmd_tso_mss;
1018 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
1019 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
1021 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
1022 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
1024 enum i40e_tx_ctx_desc_cmd_bits {
1025 I40E_TX_CTX_DESC_TSO = 0x01,
1026 I40E_TX_CTX_DESC_TSYN = 0x02,
1027 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
1028 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
1029 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
1030 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1031 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1032 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1033 I40E_TX_CTX_DESC_SWPE = 0x40
1036 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1037 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
1038 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
1040 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1041 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
1042 I40E_TXD_CTX_QW1_MSS_SHIFT)
1044 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
1045 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
1047 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
1048 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
1049 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
1051 enum i40e_tx_ctx_desc_eipt_offload {
1052 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1053 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1054 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1055 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1058 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1059 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1060 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1062 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1063 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1065 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1066 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1068 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1069 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
1070 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1072 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1074 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1075 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1076 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1078 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1079 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1080 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1082 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1083 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1084 struct i40e_filter_program_desc {
1085 __le32 qindex_flex_ptype_vsi;
1087 __le32 dtype_cmd_cntindex;
1090 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1091 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1092 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1093 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1094 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1095 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1096 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1097 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1098 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1100 /* Packet Classifier Types for filters */
1101 enum i40e_filter_pctype {
1102 /* Note: Values 0-28 are reserved for future use.
1103 * Value 29, 30, 32 are not supported on XL710 and X710.
1105 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1106 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1107 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1108 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1109 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1110 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1111 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1112 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1113 /* Note: Values 37-38 are reserved for future use.
1114 * Value 39, 40, 42 are not supported on XL710 and X710.
1116 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1117 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1118 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1119 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1120 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1121 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1122 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1123 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1124 /* Note: Value 47 is reserved for future use */
1125 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1126 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1127 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1128 /* Note: Values 51-62 are reserved for future use */
1129 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1132 enum i40e_filter_program_desc_dest {
1133 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1134 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1135 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1138 enum i40e_filter_program_desc_fd_status {
1139 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1140 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1141 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1142 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1145 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1146 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1147 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1149 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1150 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1151 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1153 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1154 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1156 enum i40e_filter_program_desc_pcmd {
1157 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1158 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1161 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1162 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1164 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1165 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1167 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1168 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1169 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1170 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1172 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1173 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1174 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1176 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1177 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1178 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1180 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1181 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1182 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1184 enum i40e_filter_type {
1185 I40E_FLOW_DIRECTOR_FLTR = 0,
1186 I40E_PE_QUAD_HASH_FLTR = 1,
1187 I40E_ETHERTYPE_FLTR,
1193 struct i40e_vsi_context {
1198 u16 vsis_unallocated;
1203 struct i40e_aqc_vsi_properties_data info;
1206 struct i40e_veb_context {
1211 u16 vebs_unallocated;
1213 struct i40e_aqc_get_veb_parameters_completion info;
1216 /* Statistics collected by each port, VSI, VEB, and S-channel */
1217 struct i40e_eth_stats {
1218 u64 rx_bytes; /* gorc */
1219 u64 rx_unicast; /* uprc */
1220 u64 rx_multicast; /* mprc */
1221 u64 rx_broadcast; /* bprc */
1222 u64 rx_discards; /* rdpc */
1223 u64 rx_unknown_protocol; /* rupp */
1224 u64 tx_bytes; /* gotc */
1225 u64 tx_unicast; /* uptc */
1226 u64 tx_multicast; /* mptc */
1227 u64 tx_broadcast; /* bptc */
1228 u64 tx_discards; /* tdpc */
1229 u64 tx_errors; /* tepc */
1232 /* Statistics collected per VEB per TC */
1233 struct i40e_veb_tc_stats {
1234 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1235 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1236 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1237 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1240 /* Statistics collected by the MAC */
1241 struct i40e_hw_port_stats {
1242 /* eth stats collected by the port */
1243 struct i40e_eth_stats eth;
1245 /* additional port specific stats */
1246 u64 tx_dropped_link_down; /* tdold */
1247 u64 crc_errors; /* crcerrs */
1248 u64 illegal_bytes; /* illerrc */
1249 u64 error_bytes; /* errbc */
1250 u64 mac_local_faults; /* mlfc */
1251 u64 mac_remote_faults; /* mrfc */
1252 u64 rx_length_errors; /* rlec */
1253 u64 link_xon_rx; /* lxonrxc */
1254 u64 link_xoff_rx; /* lxoffrxc */
1255 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1256 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1257 u64 link_xon_tx; /* lxontxc */
1258 u64 link_xoff_tx; /* lxofftxc */
1259 u64 priority_xon_tx[8]; /* pxontxc[8] */
1260 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1261 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1262 u64 rx_size_64; /* prc64 */
1263 u64 rx_size_127; /* prc127 */
1264 u64 rx_size_255; /* prc255 */
1265 u64 rx_size_511; /* prc511 */
1266 u64 rx_size_1023; /* prc1023 */
1267 u64 rx_size_1522; /* prc1522 */
1268 u64 rx_size_big; /* prc9522 */
1269 u64 rx_undersize; /* ruc */
1270 u64 rx_fragments; /* rfc */
1271 u64 rx_oversize; /* roc */
1272 u64 rx_jabber; /* rjc */
1273 u64 tx_size_64; /* ptc64 */
1274 u64 tx_size_127; /* ptc127 */
1275 u64 tx_size_255; /* ptc255 */
1276 u64 tx_size_511; /* ptc511 */
1277 u64 tx_size_1023; /* ptc1023 */
1278 u64 tx_size_1522; /* ptc1522 */
1279 u64 tx_size_big; /* ptc9522 */
1280 u64 mac_short_packet_dropped; /* mspdc */
1281 u64 checksum_error; /* xec */
1282 /* flow director stats */
1285 u64 fd_atr_tunnel_match;
1291 u64 tx_lpi_count; /* etlpic */
1292 u64 rx_lpi_count; /* erlpic */
1295 /* Checksum and Shadow RAM pointers */
1296 #define I40E_SR_NVM_CONTROL_WORD 0x00
1297 #define I40E_EMP_MODULE_PTR 0x0F
1298 #define I40E_SR_EMP_MODULE_PTR 0x48
1299 #define I40E_SR_PBA_FLAGS 0x15
1300 #define I40E_SR_PBA_BLOCK_PTR 0x16
1301 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1302 #define I40E_NVM_OEM_VER_OFF 0x83
1303 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1304 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1305 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1306 #define I40E_SR_NVM_EETRACK_LO 0x2D
1307 #define I40E_SR_NVM_EETRACK_HI 0x2E
1308 #define I40E_SR_VPD_PTR 0x2F
1309 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1310 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1312 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1313 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1314 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1315 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1316 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1317 #define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5)
1318 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12)
1319 #define I40E_PTR_TYPE BIT(15)
1320 #define I40E_SR_OCP_CFG_WORD0 0x2B
1321 #define I40E_SR_OCP_ENABLED BIT(15)
1323 /* Shadow RAM related */
1324 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1325 #define I40E_SR_WORDS_IN_1KB 512
1326 /* Checksum should be calculated such that after adding all the words,
1327 * including the checksum word itself, the sum should be 0xBABA.
1329 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1331 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1333 enum i40e_switch_element_types {
1334 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1335 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1336 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1337 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1338 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1339 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1340 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1341 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1342 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1345 /* Supported EtherType filters */
1346 enum i40e_ether_type_index {
1347 I40E_ETHER_TYPE_1588 = 0,
1348 I40E_ETHER_TYPE_FIP = 1,
1349 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1350 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1351 I40E_ETHER_TYPE_LLDP = 4,
1352 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1353 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1354 I40E_ETHER_TYPE_QCN_CNM = 7,
1355 I40E_ETHER_TYPE_8021X = 8,
1356 I40E_ETHER_TYPE_ARP = 9,
1357 I40E_ETHER_TYPE_RSV1 = 10,
1358 I40E_ETHER_TYPE_RSV2 = 11,
1361 /* Filter context base size is 1K */
1362 #define I40E_HASH_FILTER_BASE_SIZE 1024
1363 /* Supported Hash filter values */
1364 enum i40e_hash_filter_size {
1365 I40E_HASH_FILTER_SIZE_1K = 0,
1366 I40E_HASH_FILTER_SIZE_2K = 1,
1367 I40E_HASH_FILTER_SIZE_4K = 2,
1368 I40E_HASH_FILTER_SIZE_8K = 3,
1369 I40E_HASH_FILTER_SIZE_16K = 4,
1370 I40E_HASH_FILTER_SIZE_32K = 5,
1371 I40E_HASH_FILTER_SIZE_64K = 6,
1372 I40E_HASH_FILTER_SIZE_128K = 7,
1373 I40E_HASH_FILTER_SIZE_256K = 8,
1374 I40E_HASH_FILTER_SIZE_512K = 9,
1375 I40E_HASH_FILTER_SIZE_1M = 10,
1378 /* DMA context base size is 0.5K */
1379 #define I40E_DMA_CNTX_BASE_SIZE 512
1380 /* Supported DMA context values */
1381 enum i40e_dma_cntx_size {
1382 I40E_DMA_CNTX_SIZE_512 = 0,
1383 I40E_DMA_CNTX_SIZE_1K = 1,
1384 I40E_DMA_CNTX_SIZE_2K = 2,
1385 I40E_DMA_CNTX_SIZE_4K = 3,
1386 I40E_DMA_CNTX_SIZE_8K = 4,
1387 I40E_DMA_CNTX_SIZE_16K = 5,
1388 I40E_DMA_CNTX_SIZE_32K = 6,
1389 I40E_DMA_CNTX_SIZE_64K = 7,
1390 I40E_DMA_CNTX_SIZE_128K = 8,
1391 I40E_DMA_CNTX_SIZE_256K = 9,
1394 /* Supported Hash look up table (LUT) sizes */
1395 enum i40e_hash_lut_size {
1396 I40E_HASH_LUT_SIZE_128 = 0,
1397 I40E_HASH_LUT_SIZE_512 = 1,
1400 /* Structure to hold a per PF filter control settings */
1401 struct i40e_filter_control_settings {
1402 /* number of PE Quad Hash filter buckets */
1403 enum i40e_hash_filter_size pe_filt_num;
1404 /* number of PE Quad Hash contexts */
1405 enum i40e_dma_cntx_size pe_cntx_num;
1406 /* number of FCoE filter buckets */
1407 enum i40e_hash_filter_size fcoe_filt_num;
1408 /* number of FCoE DDP contexts */
1409 enum i40e_dma_cntx_size fcoe_cntx_num;
1410 /* size of the Hash LUT */
1411 enum i40e_hash_lut_size hash_lut_size;
1412 /* enable FDIR filters for PF and its VFs */
1414 /* enable Ethertype filters for PF and its VFs */
1415 bool enable_ethtype;
1416 /* enable MAC/VLAN filters for PF and its VFs */
1417 bool enable_macvlan;
1420 /* Structure to hold device level control filter counts */
1421 struct i40e_control_filter_stats {
1422 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1423 u16 etype_used; /* Used perfect EtherType filters */
1424 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1425 u16 etype_free; /* Un-used perfect EtherType filters */
1428 enum i40e_reset_type {
1430 I40E_RESET_CORER = 1,
1431 I40E_RESET_GLOBR = 2,
1432 I40E_RESET_EMPR = 3,
1435 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1436 #define I40E_NVM_LLDP_CFG_PTR 0x06
1437 #define I40E_SR_LLDP_CFG_PTR 0x31
1438 struct i40e_lldp_variables {
1448 /* Offsets into Alternate Ram */
1449 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1450 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1451 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */
1452 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */
1453 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1454 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1456 /* Alternate Ram Bandwidth Masks */
1457 #define I40E_ALT_BW_VALUE_MASK 0xFF
1458 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1459 #define I40E_ALT_BW_VALID_MASK 0x80000000
1461 /* RSS Hash Table Size */
1462 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1464 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1465 #define I40E_L3_SRC_SHIFT 47
1466 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1467 #define I40E_L3_V6_SRC_SHIFT 43
1468 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1469 #define I40E_L3_DST_SHIFT 35
1470 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1471 #define I40E_L3_V6_DST_SHIFT 35
1472 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1473 #define I40E_L4_SRC_SHIFT 34
1474 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1475 #define I40E_L4_DST_SHIFT 33
1476 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1477 #define I40E_VERIFY_TAG_SHIFT 31
1478 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1480 #define I40E_FLEX_50_SHIFT 13
1481 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1482 #define I40E_FLEX_51_SHIFT 12
1483 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1484 #define I40E_FLEX_52_SHIFT 11
1485 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1486 #define I40E_FLEX_53_SHIFT 10
1487 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1488 #define I40E_FLEX_54_SHIFT 9
1489 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1490 #define I40E_FLEX_55_SHIFT 8
1491 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1492 #define I40E_FLEX_56_SHIFT 7
1493 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1494 #define I40E_FLEX_57_SHIFT 6
1495 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1497 /* Version format for Dynamic Device Personalization(DDP) */
1498 struct i40e_ddp_version {
1505 #define I40E_DDP_NAME_SIZE 32
1507 /* Package header */
1508 struct i40e_package_header {
1509 struct i40e_ddp_version version;
1511 u32 segment_offset[1];
1514 /* Generic segment header */
1515 struct i40e_generic_seg_header {
1516 #define SEGMENT_TYPE_METADATA 0x00000001
1517 #define SEGMENT_TYPE_NOTES 0x00000002
1518 #define SEGMENT_TYPE_I40E 0x00000011
1519 #define SEGMENT_TYPE_X722 0x00000012
1521 struct i40e_ddp_version version;
1523 char name[I40E_DDP_NAME_SIZE];
1526 struct i40e_metadata_segment {
1527 struct i40e_generic_seg_header header;
1528 struct i40e_ddp_version version;
1530 char name[I40E_DDP_NAME_SIZE];
1533 struct i40e_device_id_entry {
1535 u32 sub_vendor_dev_id;
1538 struct i40e_profile_segment {
1539 struct i40e_generic_seg_header header;
1540 struct i40e_ddp_version version;
1541 char name[I40E_DDP_NAME_SIZE];
1542 u32 device_table_count;
1543 struct i40e_device_id_entry device_table[1];
1546 struct i40e_section_table {
1548 u32 section_offset[1];
1551 struct i40e_profile_section_header {
1555 #define SECTION_TYPE_INFO 0x00000010
1556 #define SECTION_TYPE_MMIO 0x00000800
1557 #define SECTION_TYPE_AQ 0x00000801
1558 #define SECTION_TYPE_NOTE 0x80000000
1559 #define SECTION_TYPE_NAME 0x80000001
1566 struct i40e_profile_info {
1568 struct i40e_ddp_version version;
1570 #define I40E_DDP_ADD_TRACKID 0x01
1571 #define I40E_DDP_REMOVE_TRACKID 0x02
1573 u8 name[I40E_DDP_NAME_SIZE];
1575 #endif /* _I40E_TYPE_H_ */