1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include <linux/prefetch.h>
28 #include <net/busy_poll.h>
29 #include <linux/bpf_trace.h>
31 #include "i40e_trace.h"
32 #include "i40e_prototype.h"
34 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
37 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
38 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
39 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
40 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
41 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
44 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
46 * i40e_fdir - Generate a Flow Director descriptor based on fdata
47 * @tx_ring: Tx ring to send buffer on
48 * @fdata: Flow director filter data
49 * @add: Indicate if we are adding a rule or deleting one
52 static void i40e_fdir(struct i40e_ring *tx_ring,
53 struct i40e_fdir_filter *fdata, bool add)
55 struct i40e_filter_program_desc *fdir_desc;
56 struct i40e_pf *pf = tx_ring->vsi->back;
57 u32 flex_ptype, dtype_cmd;
60 /* grab the next descriptor */
61 i = tx_ring->next_to_use;
62 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
65 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
67 flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK &
68 (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT);
70 flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK &
71 (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);
73 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
74 (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
76 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
77 (fdata->flex_offset << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);
79 /* Use LAN VSI Id if not programmed by user */
80 flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK &
81 ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) <<
82 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT);
84 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
87 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
88 I40E_TXD_FLTR_QW1_PCMD_SHIFT :
89 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
90 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
92 dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK &
93 (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT);
95 dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK &
96 (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT);
98 if (fdata->cnt_index) {
99 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
100 dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK &
101 ((u32)fdata->cnt_index <<
102 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT);
105 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
106 fdir_desc->rsvd = cpu_to_le32(0);
107 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
108 fdir_desc->fd_id = cpu_to_le32(fdata->fd_id);
111 #define I40E_FD_CLEAN_DELAY 10
113 * i40e_program_fdir_filter - Program a Flow Director filter
114 * @fdir_data: Packet data that will be filter parameters
115 * @raw_packet: the pre-allocated packet buffer for FDir
116 * @pf: The PF pointer
117 * @add: True for add/update, False for remove
119 static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data,
120 u8 *raw_packet, struct i40e_pf *pf,
123 struct i40e_tx_buffer *tx_buf, *first;
124 struct i40e_tx_desc *tx_desc;
125 struct i40e_ring *tx_ring;
126 struct i40e_vsi *vsi;
132 /* find existing FDIR VSI */
133 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
137 tx_ring = vsi->tx_rings[0];
140 /* we need two descriptors to add/del a filter and we can wait */
141 for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) {
144 msleep_interruptible(1);
147 dma = dma_map_single(dev, raw_packet,
148 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
149 if (dma_mapping_error(dev, dma))
152 /* grab the next descriptor */
153 i = tx_ring->next_to_use;
154 first = &tx_ring->tx_bi[i];
155 i40e_fdir(tx_ring, fdir_data, add);
157 /* Now program a dummy descriptor */
158 i = tx_ring->next_to_use;
159 tx_desc = I40E_TX_DESC(tx_ring, i);
160 tx_buf = &tx_ring->tx_bi[i];
162 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
164 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
166 /* record length, and DMA address */
167 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
168 dma_unmap_addr_set(tx_buf, dma, dma);
170 tx_desc->buffer_addr = cpu_to_le64(dma);
171 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
173 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
174 tx_buf->raw_buf = (void *)raw_packet;
176 tx_desc->cmd_type_offset_bsz =
177 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
179 /* Force memory writes to complete before letting h/w
180 * know there are new descriptors to fetch.
184 /* Mark the data descriptor to be watched */
185 first->next_to_watch = tx_desc;
187 writel(tx_ring->next_to_use, tx_ring->tail);
194 #define IP_HEADER_OFFSET 14
195 #define I40E_UDPIP_DUMMY_PACKET_LEN 42
197 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
198 * @vsi: pointer to the targeted VSI
199 * @fd_data: the flow director data required for the FDir descriptor
200 * @add: true adds a filter, false removes it
202 * Returns 0 if the filters were successfully added or removed
204 static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
205 struct i40e_fdir_filter *fd_data,
208 struct i40e_pf *pf = vsi->back;
213 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
214 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
217 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
220 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
222 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
223 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
224 + sizeof(struct iphdr));
226 ip->daddr = fd_data->dst_ip;
227 udp->dest = fd_data->dst_port;
228 ip->saddr = fd_data->src_ip;
229 udp->source = fd_data->src_port;
231 if (fd_data->flex_filter) {
232 u8 *payload = raw_packet + I40E_UDPIP_DUMMY_PACKET_LEN;
233 __be16 pattern = fd_data->flex_word;
234 u16 off = fd_data->flex_offset;
236 *((__force __be16 *)(payload + off)) = pattern;
239 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
240 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
242 dev_info(&pf->pdev->dev,
243 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
244 fd_data->pctype, fd_data->fd_id, ret);
245 /* Free the packet buffer since it wasn't added to the ring */
248 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
250 dev_info(&pf->pdev->dev,
251 "Filter OK for PCTYPE %d loc = %d\n",
252 fd_data->pctype, fd_data->fd_id);
254 dev_info(&pf->pdev->dev,
255 "Filter deleted for PCTYPE %d loc = %d\n",
256 fd_data->pctype, fd_data->fd_id);
260 pf->fd_udp4_filter_cnt++;
262 pf->fd_udp4_filter_cnt--;
267 #define I40E_TCPIP_DUMMY_PACKET_LEN 54
269 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
270 * @vsi: pointer to the targeted VSI
271 * @fd_data: the flow director data required for the FDir descriptor
272 * @add: true adds a filter, false removes it
274 * Returns 0 if the filters were successfully added or removed
276 static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
277 struct i40e_fdir_filter *fd_data,
280 struct i40e_pf *pf = vsi->back;
286 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
287 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
288 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
289 0x0, 0x72, 0, 0, 0, 0};
291 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
294 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
296 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
297 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
298 + sizeof(struct iphdr));
300 ip->daddr = fd_data->dst_ip;
301 tcp->dest = fd_data->dst_port;
302 ip->saddr = fd_data->src_ip;
303 tcp->source = fd_data->src_port;
305 if (fd_data->flex_filter) {
306 u8 *payload = raw_packet + I40E_TCPIP_DUMMY_PACKET_LEN;
307 __be16 pattern = fd_data->flex_word;
308 u16 off = fd_data->flex_offset;
310 *((__force __be16 *)(payload + off)) = pattern;
313 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
314 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
316 dev_info(&pf->pdev->dev,
317 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
318 fd_data->pctype, fd_data->fd_id, ret);
319 /* Free the packet buffer since it wasn't added to the ring */
322 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
324 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
325 fd_data->pctype, fd_data->fd_id);
327 dev_info(&pf->pdev->dev,
328 "Filter deleted for PCTYPE %d loc = %d\n",
329 fd_data->pctype, fd_data->fd_id);
333 pf->fd_tcp4_filter_cnt++;
334 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
335 I40E_DEBUG_FD & pf->hw.debug_mask)
336 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
337 pf->flags |= I40E_FLAG_FD_ATR_AUTO_DISABLED;
339 pf->fd_tcp4_filter_cnt--;
345 #define I40E_SCTPIP_DUMMY_PACKET_LEN 46
347 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
348 * a specific flow spec
349 * @vsi: pointer to the targeted VSI
350 * @fd_data: the flow director data required for the FDir descriptor
351 * @add: true adds a filter, false removes it
353 * Returns 0 if the filters were successfully added or removed
355 static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
356 struct i40e_fdir_filter *fd_data,
359 struct i40e_pf *pf = vsi->back;
360 struct sctphdr *sctp;
365 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
366 0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, 0,
367 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
369 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
372 memcpy(raw_packet, packet, I40E_SCTPIP_DUMMY_PACKET_LEN);
374 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
375 sctp = (struct sctphdr *)(raw_packet + IP_HEADER_OFFSET
376 + sizeof(struct iphdr));
378 ip->daddr = fd_data->dst_ip;
379 sctp->dest = fd_data->dst_port;
380 ip->saddr = fd_data->src_ip;
381 sctp->source = fd_data->src_port;
383 if (fd_data->flex_filter) {
384 u8 *payload = raw_packet + I40E_SCTPIP_DUMMY_PACKET_LEN;
385 __be16 pattern = fd_data->flex_word;
386 u16 off = fd_data->flex_offset;
388 *((__force __be16 *)(payload + off)) = pattern;
391 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
392 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
394 dev_info(&pf->pdev->dev,
395 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
396 fd_data->pctype, fd_data->fd_id, ret);
397 /* Free the packet buffer since it wasn't added to the ring */
400 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
402 dev_info(&pf->pdev->dev,
403 "Filter OK for PCTYPE %d loc = %d\n",
404 fd_data->pctype, fd_data->fd_id);
406 dev_info(&pf->pdev->dev,
407 "Filter deleted for PCTYPE %d loc = %d\n",
408 fd_data->pctype, fd_data->fd_id);
412 pf->fd_sctp4_filter_cnt++;
414 pf->fd_sctp4_filter_cnt--;
419 #define I40E_IP_DUMMY_PACKET_LEN 34
421 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
422 * a specific flow spec
423 * @vsi: pointer to the targeted VSI
424 * @fd_data: the flow director data required for the FDir descriptor
425 * @add: true adds a filter, false removes it
427 * Returns 0 if the filters were successfully added or removed
429 static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
430 struct i40e_fdir_filter *fd_data,
433 struct i40e_pf *pf = vsi->back;
438 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
439 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
442 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
443 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
444 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
447 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
448 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
450 ip->saddr = fd_data->src_ip;
451 ip->daddr = fd_data->dst_ip;
454 if (fd_data->flex_filter) {
455 u8 *payload = raw_packet + I40E_IP_DUMMY_PACKET_LEN;
456 __be16 pattern = fd_data->flex_word;
457 u16 off = fd_data->flex_offset;
459 *((__force __be16 *)(payload + off)) = pattern;
463 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
465 dev_info(&pf->pdev->dev,
466 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
467 fd_data->pctype, fd_data->fd_id, ret);
468 /* The packet buffer wasn't added to the ring so we
469 * need to free it now.
473 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
475 dev_info(&pf->pdev->dev,
476 "Filter OK for PCTYPE %d loc = %d\n",
477 fd_data->pctype, fd_data->fd_id);
479 dev_info(&pf->pdev->dev,
480 "Filter deleted for PCTYPE %d loc = %d\n",
481 fd_data->pctype, fd_data->fd_id);
486 pf->fd_ip4_filter_cnt++;
488 pf->fd_ip4_filter_cnt--;
494 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
495 * @vsi: pointer to the targeted VSI
496 * @cmd: command to get or set RX flow classification rules
497 * @add: true adds a filter, false removes it
500 int i40e_add_del_fdir(struct i40e_vsi *vsi,
501 struct i40e_fdir_filter *input, bool add)
503 struct i40e_pf *pf = vsi->back;
506 switch (input->flow_type & ~FLOW_EXT) {
508 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
511 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
514 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
517 switch (input->ip4_proto) {
519 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
522 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
525 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
528 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
531 /* We cannot support masking based on protocol */
532 dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n",
538 dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n",
543 /* The buffer allocated here will be normally be freed by
544 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit
545 * completion. In the event of an error adding the buffer to the FDIR
546 * ring, it will immediately be freed. It may also be freed by
547 * i40e_clean_tx_ring() when closing the VSI.
553 * i40e_fd_handle_status - check the Programming Status for FD
554 * @rx_ring: the Rx ring for this descriptor
555 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
556 * @prog_id: the id originally used for programming
558 * This is used to verify if the FD programming or invalidation
559 * requested by SW to the HW is successful or not and take actions accordingly.
561 static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
562 union i40e_rx_desc *rx_desc, u8 prog_id)
564 struct i40e_pf *pf = rx_ring->vsi->back;
565 struct pci_dev *pdev = pf->pdev;
566 u32 fcnt_prog, fcnt_avail;
570 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
571 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
572 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
574 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
575 pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id);
576 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
577 (I40E_DEBUG_FD & pf->hw.debug_mask))
578 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
581 /* Check if the programming error is for ATR.
582 * If so, auto disable ATR and set a state for
583 * flush in progress. Next time we come here if flush is in
584 * progress do nothing, once flush is complete the state will
587 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
591 /* store the current atr filter count */
592 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
594 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) &&
595 pf->flags & I40E_FLAG_FD_SB_AUTO_DISABLED) {
596 pf->flags |= I40E_FLAG_FD_ATR_AUTO_DISABLED;
597 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
600 /* filter programming failed most likely due to table full */
601 fcnt_prog = i40e_get_global_fd_count(pf);
602 fcnt_avail = pf->fdir_pf_filter_count;
603 /* If ATR is running fcnt_prog can quickly change,
604 * if we are very close to full, it makes sense to disable
605 * FD ATR/SB and then re-enable it when there is room.
607 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
608 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
609 !(pf->flags & I40E_FLAG_FD_SB_AUTO_DISABLED)) {
610 pf->flags |= I40E_FLAG_FD_SB_AUTO_DISABLED;
611 if (I40E_DEBUG_FD & pf->hw.debug_mask)
612 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
615 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
616 if (I40E_DEBUG_FD & pf->hw.debug_mask)
617 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
618 rx_desc->wb.qword0.hi_dword.fd_id);
623 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
624 * @ring: the ring that owns the buffer
625 * @tx_buffer: the buffer to free
627 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
628 struct i40e_tx_buffer *tx_buffer)
630 if (tx_buffer->skb) {
631 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
632 kfree(tx_buffer->raw_buf);
633 else if (ring_is_xdp(ring))
634 page_frag_free(tx_buffer->raw_buf);
636 dev_kfree_skb_any(tx_buffer->skb);
637 if (dma_unmap_len(tx_buffer, len))
638 dma_unmap_single(ring->dev,
639 dma_unmap_addr(tx_buffer, dma),
640 dma_unmap_len(tx_buffer, len),
642 } else if (dma_unmap_len(tx_buffer, len)) {
643 dma_unmap_page(ring->dev,
644 dma_unmap_addr(tx_buffer, dma),
645 dma_unmap_len(tx_buffer, len),
649 tx_buffer->next_to_watch = NULL;
650 tx_buffer->skb = NULL;
651 dma_unmap_len_set(tx_buffer, len, 0);
652 /* tx_buffer must be completely set up in the transmit path */
656 * i40e_clean_tx_ring - Free any empty Tx buffers
657 * @tx_ring: ring to be cleaned
659 void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
661 unsigned long bi_size;
664 /* ring already cleared, nothing to do */
668 /* Free all the Tx ring sk_buffs */
669 for (i = 0; i < tx_ring->count; i++)
670 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
672 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
673 memset(tx_ring->tx_bi, 0, bi_size);
675 /* Zero out the descriptor ring */
676 memset(tx_ring->desc, 0, tx_ring->size);
678 tx_ring->next_to_use = 0;
679 tx_ring->next_to_clean = 0;
681 if (!tx_ring->netdev)
684 /* cleanup Tx queue statistics */
685 netdev_tx_reset_queue(txring_txq(tx_ring));
689 * i40e_free_tx_resources - Free Tx resources per queue
690 * @tx_ring: Tx descriptor ring for a specific queue
692 * Free all transmit software resources
694 void i40e_free_tx_resources(struct i40e_ring *tx_ring)
696 i40e_clean_tx_ring(tx_ring);
697 kfree(tx_ring->tx_bi);
698 tx_ring->tx_bi = NULL;
701 dma_free_coherent(tx_ring->dev, tx_ring->size,
702 tx_ring->desc, tx_ring->dma);
703 tx_ring->desc = NULL;
708 * i40e_get_tx_pending - how many tx descriptors not processed
709 * @tx_ring: the ring of descriptors
711 * Since there is no access to the ring head register
712 * in XL710, we need to use our local copies
714 u32 i40e_get_tx_pending(struct i40e_ring *ring)
718 head = i40e_get_head(ring);
719 tail = readl(ring->tail);
722 return (head < tail) ?
723 tail - head : (tail + ring->count - head);
731 * i40e_clean_tx_irq - Reclaim resources after transmit completes
732 * @vsi: the VSI we care about
733 * @tx_ring: Tx ring to clean
734 * @napi_budget: Used to determine if we are in netpoll
736 * Returns true if there's any budget left (e.g. the clean is finished)
738 static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
739 struct i40e_ring *tx_ring, int napi_budget)
741 u16 i = tx_ring->next_to_clean;
742 struct i40e_tx_buffer *tx_buf;
743 struct i40e_tx_desc *tx_head;
744 struct i40e_tx_desc *tx_desc;
745 unsigned int total_bytes = 0, total_packets = 0;
746 unsigned int budget = vsi->work_limit;
748 tx_buf = &tx_ring->tx_bi[i];
749 tx_desc = I40E_TX_DESC(tx_ring, i);
752 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
755 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
757 /* if next_to_watch is not set then there is no work pending */
761 /* prevent any other reads prior to eop_desc */
764 i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
765 /* we have caught up to head, no work left to do */
766 if (tx_head == tx_desc)
769 /* clear next_to_watch to prevent false hangs */
770 tx_buf->next_to_watch = NULL;
772 /* update the statistics for this packet */
773 total_bytes += tx_buf->bytecount;
774 total_packets += tx_buf->gso_segs;
776 /* free the skb/XDP data */
777 if (ring_is_xdp(tx_ring))
778 page_frag_free(tx_buf->raw_buf);
780 napi_consume_skb(tx_buf->skb, napi_budget);
782 /* unmap skb header data */
783 dma_unmap_single(tx_ring->dev,
784 dma_unmap_addr(tx_buf, dma),
785 dma_unmap_len(tx_buf, len),
788 /* clear tx_buffer data */
790 dma_unmap_len_set(tx_buf, len, 0);
792 /* unmap remaining buffers */
793 while (tx_desc != eop_desc) {
794 i40e_trace(clean_tx_irq_unmap,
795 tx_ring, tx_desc, tx_buf);
802 tx_buf = tx_ring->tx_bi;
803 tx_desc = I40E_TX_DESC(tx_ring, 0);
806 /* unmap any remaining paged data */
807 if (dma_unmap_len(tx_buf, len)) {
808 dma_unmap_page(tx_ring->dev,
809 dma_unmap_addr(tx_buf, dma),
810 dma_unmap_len(tx_buf, len),
812 dma_unmap_len_set(tx_buf, len, 0);
816 /* move us one more past the eop_desc for start of next pkt */
822 tx_buf = tx_ring->tx_bi;
823 tx_desc = I40E_TX_DESC(tx_ring, 0);
828 /* update budget accounting */
830 } while (likely(budget));
833 tx_ring->next_to_clean = i;
834 u64_stats_update_begin(&tx_ring->syncp);
835 tx_ring->stats.bytes += total_bytes;
836 tx_ring->stats.packets += total_packets;
837 u64_stats_update_end(&tx_ring->syncp);
838 tx_ring->q_vector->tx.total_bytes += total_bytes;
839 tx_ring->q_vector->tx.total_packets += total_packets;
841 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
842 /* check to see if there are < 4 descriptors
843 * waiting to be written back, then kick the hardware to force
844 * them to be written back in case we stay in NAPI.
845 * In this mode on X722 we do not enable Interrupt.
847 unsigned int j = i40e_get_tx_pending(tx_ring);
850 ((j / WB_STRIDE) == 0) && (j > 0) &&
851 !test_bit(__I40E_VSI_DOWN, vsi->state) &&
852 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
853 tx_ring->arm_wb = true;
856 if (ring_is_xdp(tx_ring))
859 /* notify netdev of completed buffers */
860 netdev_tx_completed_queue(txring_txq(tx_ring),
861 total_packets, total_bytes);
863 #define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
864 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
865 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
866 /* Make sure that anybody stopping the queue after this
867 * sees the new next_to_clean.
870 if (__netif_subqueue_stopped(tx_ring->netdev,
871 tx_ring->queue_index) &&
872 !test_bit(__I40E_VSI_DOWN, vsi->state)) {
873 netif_wake_subqueue(tx_ring->netdev,
874 tx_ring->queue_index);
875 ++tx_ring->tx_stats.restart_queue;
883 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
884 * @vsi: the VSI we care about
885 * @q_vector: the vector on which to enable writeback
888 static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
889 struct i40e_q_vector *q_vector)
891 u16 flags = q_vector->tx.ring[0].flags;
894 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
897 if (q_vector->arm_wb_state)
900 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
901 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
902 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
905 I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1),
908 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
909 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
911 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
913 q_vector->arm_wb_state = true;
917 * i40e_force_wb - Issue SW Interrupt so HW does a wb
918 * @vsi: the VSI we care about
919 * @q_vector: the vector on which to force writeback
922 void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
924 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
925 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
926 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
927 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
928 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
929 /* allow 00 to be written to the index */
932 I40E_PFINT_DYN_CTLN(q_vector->v_idx +
933 vsi->base_vector - 1), val);
935 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
936 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
937 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
938 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
939 /* allow 00 to be written to the index */
941 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
946 * i40e_set_new_dynamic_itr - Find new ITR level
947 * @rc: structure containing ring performance data
949 * Returns true if ITR changed, false if not
951 * Stores a new ITR value based on packets and byte counts during
952 * the last interrupt. The advantage of per interrupt computation
953 * is faster updates and more accurate ITR for the current traffic
954 * pattern. Constants in this function were computed based on
955 * theoretical maximum wire speed and thresholds were set based on
956 * testing data as well as attempting to minimize response time
957 * while increasing bulk throughput.
959 static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
961 enum i40e_latency_range new_latency_range = rc->latency_range;
962 u32 new_itr = rc->itr;
964 unsigned int usecs, estimated_usecs;
966 if (rc->total_packets == 0 || !rc->itr)
969 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
970 bytes_per_int = rc->total_bytes / usecs;
972 /* The calculations in this algorithm depend on interrupts actually
973 * firing at the ITR rate. This may not happen if the packet rate is
974 * really low, or if we've been napi polling. Check to make sure
975 * that's not the case before we continue.
977 estimated_usecs = jiffies_to_usecs(jiffies - rc->last_itr_update);
978 if (estimated_usecs > usecs) {
979 new_latency_range = I40E_LOW_LATENCY;
983 /* simple throttlerate management
984 * 0-10MB/s lowest (50000 ints/s)
985 * 10-20MB/s low (20000 ints/s)
986 * 20-1249MB/s bulk (18000 ints/s)
988 * The math works out because the divisor is in 10^(-6) which
989 * turns the bytes/us input value into MB/s values, but
990 * make sure to use usecs, as the register values written
991 * are in 2 usec increments in the ITR registers, and make sure
992 * to use the smoothed values that the countdown timer gives us.
994 switch (new_latency_range) {
995 case I40E_LOWEST_LATENCY:
996 if (bytes_per_int > 10)
997 new_latency_range = I40E_LOW_LATENCY;
999 case I40E_LOW_LATENCY:
1000 if (bytes_per_int > 20)
1001 new_latency_range = I40E_BULK_LATENCY;
1002 else if (bytes_per_int <= 10)
1003 new_latency_range = I40E_LOWEST_LATENCY;
1005 case I40E_BULK_LATENCY:
1007 if (bytes_per_int <= 20)
1008 new_latency_range = I40E_LOW_LATENCY;
1013 rc->latency_range = new_latency_range;
1015 switch (new_latency_range) {
1016 case I40E_LOWEST_LATENCY:
1017 new_itr = I40E_ITR_50K;
1019 case I40E_LOW_LATENCY:
1020 new_itr = I40E_ITR_20K;
1022 case I40E_BULK_LATENCY:
1023 new_itr = I40E_ITR_18K;
1029 rc->total_bytes = 0;
1030 rc->total_packets = 0;
1031 rc->last_itr_update = jiffies;
1033 if (new_itr != rc->itr) {
1041 * i40e_reuse_rx_page - page flip buffer and store it back on the ring
1042 * @rx_ring: rx descriptor ring to store buffers on
1043 * @old_buff: donor buffer to have page reused
1045 * Synchronizes page for reuse by the adapter
1047 static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
1048 struct i40e_rx_buffer *old_buff)
1050 struct i40e_rx_buffer *new_buff;
1051 u16 nta = rx_ring->next_to_alloc;
1053 new_buff = &rx_ring->rx_bi[nta];
1055 /* update, and store next to alloc */
1057 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1059 /* transfer page from old buffer to new buffer */
1060 new_buff->dma = old_buff->dma;
1061 new_buff->page = old_buff->page;
1062 new_buff->page_offset = old_buff->page_offset;
1063 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1067 * i40e_rx_is_programming_status - check for programming status descriptor
1068 * @qw: qword representing status_error_len in CPU ordering
1070 * The value of in the descriptor length field indicate if this
1071 * is a programming status descriptor for flow director or FCoE
1072 * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise
1073 * it is a packet descriptor.
1075 static inline bool i40e_rx_is_programming_status(u64 qw)
1077 /* The Rx filter programming status and SPH bit occupy the same
1078 * spot in the descriptor. Since we don't support packet split we
1079 * can just reuse the bit as an indication that this is a
1080 * programming status descriptor.
1082 return qw & I40E_RXD_QW1_LENGTH_SPH_MASK;
1086 * i40e_clean_programming_status - clean the programming status descriptor
1087 * @rx_ring: the rx ring that has this descriptor
1088 * @rx_desc: the rx descriptor written back by HW
1089 * @qw: qword representing status_error_len in CPU ordering
1091 * Flow director should handle FD_FILTER_STATUS to check its filter programming
1092 * status being successful or not and take actions accordingly. FCoE should
1093 * handle its context/filter programming/invalidation status and take actions.
1096 static void i40e_clean_programming_status(struct i40e_ring *rx_ring,
1097 union i40e_rx_desc *rx_desc,
1100 struct i40e_rx_buffer *rx_buffer;
1101 u32 ntc = rx_ring->next_to_clean;
1104 /* fetch, update, and store next to clean */
1105 rx_buffer = &rx_ring->rx_bi[ntc++];
1106 ntc = (ntc < rx_ring->count) ? ntc : 0;
1107 rx_ring->next_to_clean = ntc;
1109 prefetch(I40E_RX_DESC(rx_ring, ntc));
1111 /* place unused page back on the ring */
1112 i40e_reuse_rx_page(rx_ring, rx_buffer);
1113 rx_ring->rx_stats.page_reuse_count++;
1115 /* clear contents of buffer_info */
1116 rx_buffer->page = NULL;
1118 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1119 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1121 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
1122 i40e_fd_handle_status(rx_ring, rx_desc, id);
1126 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
1127 * @tx_ring: the tx ring to set up
1129 * Return 0 on success, negative on error
1131 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
1133 struct device *dev = tx_ring->dev;
1139 /* warn if we are about to overwrite the pointer */
1140 WARN_ON(tx_ring->tx_bi);
1141 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
1142 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
1143 if (!tx_ring->tx_bi)
1146 u64_stats_init(&tx_ring->syncp);
1148 /* round up to nearest 4K */
1149 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1150 /* add u32 for head writeback, align after this takes care of
1151 * guaranteeing this is at least one cache line in size
1153 tx_ring->size += sizeof(u32);
1154 tx_ring->size = ALIGN(tx_ring->size, 4096);
1155 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1156 &tx_ring->dma, GFP_KERNEL);
1157 if (!tx_ring->desc) {
1158 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1163 tx_ring->next_to_use = 0;
1164 tx_ring->next_to_clean = 0;
1168 kfree(tx_ring->tx_bi);
1169 tx_ring->tx_bi = NULL;
1174 * i40e_clean_rx_ring - Free Rx buffers
1175 * @rx_ring: ring to be cleaned
1177 void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1179 unsigned long bi_size;
1182 /* ring already cleared, nothing to do */
1183 if (!rx_ring->rx_bi)
1187 dev_kfree_skb(rx_ring->skb);
1188 rx_ring->skb = NULL;
1191 /* Free all the Rx ring sk_buffs */
1192 for (i = 0; i < rx_ring->count; i++) {
1193 struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i];
1198 /* Invalidate cache lines that may have been written to by
1199 * device so that we avoid corrupting memory.
1201 dma_sync_single_range_for_cpu(rx_ring->dev,
1204 rx_ring->rx_buf_len,
1207 /* free resources associated with mapping */
1208 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma,
1209 i40e_rx_pg_size(rx_ring),
1213 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias);
1216 rx_bi->page_offset = 0;
1219 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1220 memset(rx_ring->rx_bi, 0, bi_size);
1222 /* Zero out the descriptor ring */
1223 memset(rx_ring->desc, 0, rx_ring->size);
1225 rx_ring->next_to_alloc = 0;
1226 rx_ring->next_to_clean = 0;
1227 rx_ring->next_to_use = 0;
1231 * i40e_free_rx_resources - Free Rx resources
1232 * @rx_ring: ring to clean the resources from
1234 * Free all receive software resources
1236 void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1238 i40e_clean_rx_ring(rx_ring);
1239 rx_ring->xdp_prog = NULL;
1240 kfree(rx_ring->rx_bi);
1241 rx_ring->rx_bi = NULL;
1243 if (rx_ring->desc) {
1244 dma_free_coherent(rx_ring->dev, rx_ring->size,
1245 rx_ring->desc, rx_ring->dma);
1246 rx_ring->desc = NULL;
1251 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1252 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1254 * Returns 0 on success, negative on failure
1256 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1258 struct device *dev = rx_ring->dev;
1261 /* warn if we are about to overwrite the pointer */
1262 WARN_ON(rx_ring->rx_bi);
1263 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1264 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
1265 if (!rx_ring->rx_bi)
1268 u64_stats_init(&rx_ring->syncp);
1270 /* Round up to nearest 4K */
1271 rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1272 rx_ring->size = ALIGN(rx_ring->size, 4096);
1273 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1274 &rx_ring->dma, GFP_KERNEL);
1276 if (!rx_ring->desc) {
1277 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1282 rx_ring->next_to_alloc = 0;
1283 rx_ring->next_to_clean = 0;
1284 rx_ring->next_to_use = 0;
1286 rx_ring->xdp_prog = rx_ring->vsi->xdp_prog;
1290 kfree(rx_ring->rx_bi);
1291 rx_ring->rx_bi = NULL;
1296 * i40e_release_rx_desc - Store the new tail and head values
1297 * @rx_ring: ring to bump
1298 * @val: new head index
1300 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1302 rx_ring->next_to_use = val;
1304 /* update next to alloc since we have filled the ring */
1305 rx_ring->next_to_alloc = val;
1307 /* Force memory writes to complete before letting h/w
1308 * know there are new descriptors to fetch. (Only
1309 * applicable for weak-ordered memory model archs,
1313 writel(val, rx_ring->tail);
1317 * i40e_rx_offset - Return expected offset into page to access data
1318 * @rx_ring: Ring we are requesting offset of
1320 * Returns the offset value for ring into the data buffer.
1322 static inline unsigned int i40e_rx_offset(struct i40e_ring *rx_ring)
1324 return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0;
1328 * i40e_alloc_mapped_page - recycle or make a new page
1329 * @rx_ring: ring to use
1330 * @bi: rx_buffer struct to modify
1332 * Returns true if the page was successfully allocated or
1335 static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
1336 struct i40e_rx_buffer *bi)
1338 struct page *page = bi->page;
1341 /* since we are recycling buffers we should seldom need to alloc */
1343 rx_ring->rx_stats.page_reuse_count++;
1347 /* alloc new page for storage */
1348 page = dev_alloc_pages(i40e_rx_pg_order(rx_ring));
1349 if (unlikely(!page)) {
1350 rx_ring->rx_stats.alloc_page_failed++;
1354 /* map page for use */
1355 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1356 i40e_rx_pg_size(rx_ring),
1360 /* if mapping failed free memory back to system since
1361 * there isn't much point in holding memory we can't use
1363 if (dma_mapping_error(rx_ring->dev, dma)) {
1364 __free_pages(page, i40e_rx_pg_order(rx_ring));
1365 rx_ring->rx_stats.alloc_page_failed++;
1371 bi->page_offset = i40e_rx_offset(rx_ring);
1373 /* initialize pagecnt_bias to 1 representing we fully own page */
1374 bi->pagecnt_bias = 1;
1380 * i40e_receive_skb - Send a completed packet up the stack
1381 * @rx_ring: rx ring in play
1382 * @skb: packet to send up
1383 * @vlan_tag: vlan tag for packet
1385 static void i40e_receive_skb(struct i40e_ring *rx_ring,
1386 struct sk_buff *skb, u16 vlan_tag)
1388 struct i40e_q_vector *q_vector = rx_ring->q_vector;
1390 if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1391 (vlan_tag & VLAN_VID_MASK))
1392 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
1394 napi_gro_receive(&q_vector->napi, skb);
1398 * i40e_alloc_rx_buffers - Replace used receive buffers
1399 * @rx_ring: ring to place buffers on
1400 * @cleaned_count: number of buffers to replace
1402 * Returns false if all allocations were successful, true if any fail
1404 bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
1406 u16 ntu = rx_ring->next_to_use;
1407 union i40e_rx_desc *rx_desc;
1408 struct i40e_rx_buffer *bi;
1410 /* do nothing if no valid netdev defined */
1411 if (!rx_ring->netdev || !cleaned_count)
1414 rx_desc = I40E_RX_DESC(rx_ring, ntu);
1415 bi = &rx_ring->rx_bi[ntu];
1418 if (!i40e_alloc_mapped_page(rx_ring, bi))
1421 /* sync the buffer for use by the device */
1422 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1424 rx_ring->rx_buf_len,
1427 /* Refresh the desc even if buffer_addrs didn't change
1428 * because each write-back erases this info.
1430 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1435 if (unlikely(ntu == rx_ring->count)) {
1436 rx_desc = I40E_RX_DESC(rx_ring, 0);
1437 bi = rx_ring->rx_bi;
1441 /* clear the status bits for the next_to_use descriptor */
1442 rx_desc->wb.qword1.status_error_len = 0;
1445 } while (cleaned_count);
1447 if (rx_ring->next_to_use != ntu)
1448 i40e_release_rx_desc(rx_ring, ntu);
1453 if (rx_ring->next_to_use != ntu)
1454 i40e_release_rx_desc(rx_ring, ntu);
1456 /* make sure to come back via polling to try again after
1457 * allocation failure
1463 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1464 * @vsi: the VSI we care about
1465 * @skb: skb currently being received and modified
1466 * @rx_desc: the receive descriptor
1468 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1469 struct sk_buff *skb,
1470 union i40e_rx_desc *rx_desc)
1472 struct i40e_rx_ptype_decoded decoded;
1473 u32 rx_error, rx_status;
1478 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1479 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT;
1480 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1481 I40E_RXD_QW1_ERROR_SHIFT;
1482 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1483 I40E_RXD_QW1_STATUS_SHIFT;
1484 decoded = decode_rx_desc_ptype(ptype);
1486 skb->ip_summed = CHECKSUM_NONE;
1488 skb_checksum_none_assert(skb);
1490 /* Rx csum enabled and ip headers found? */
1491 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1494 /* did the hardware decode the packet and checksum? */
1495 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1498 /* both known and outer_ip must be set for the below code to work */
1499 if (!(decoded.known && decoded.outer_ip))
1502 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1503 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
1504 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1505 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
1508 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1509 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1512 /* likely incorrect csum if alternate IP extension headers found */
1514 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1515 /* don't increment checksum err here, non-fatal err */
1518 /* there was some L4 error, count error and punt packet to the stack */
1519 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1522 /* handle packets that were not able to be checksummed due
1523 * to arrival speed, in this case the stack can compute
1526 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1529 /* If there is an outer header present that might contain a checksum
1530 * we need to bump the checksum level by 1 to reflect the fact that
1531 * we are indicating we validated the inner checksum.
1533 if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT)
1534 skb->csum_level = 1;
1536 /* Only report checksum unnecessary for TCP, UDP, or SCTP */
1537 switch (decoded.inner_prot) {
1538 case I40E_RX_PTYPE_INNER_PROT_TCP:
1539 case I40E_RX_PTYPE_INNER_PROT_UDP:
1540 case I40E_RX_PTYPE_INNER_PROT_SCTP:
1541 skb->ip_summed = CHECKSUM_UNNECESSARY;
1550 vsi->back->hw_csum_rx_error++;
1554 * i40e_ptype_to_htype - get a hash type
1555 * @ptype: the ptype value from the descriptor
1557 * Returns a hash type to be used by skb_set_hash
1559 static inline int i40e_ptype_to_htype(u8 ptype)
1561 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1564 return PKT_HASH_TYPE_NONE;
1566 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1567 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1568 return PKT_HASH_TYPE_L4;
1569 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1570 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1571 return PKT_HASH_TYPE_L3;
1573 return PKT_HASH_TYPE_L2;
1577 * i40e_rx_hash - set the hash value in the skb
1578 * @ring: descriptor ring
1579 * @rx_desc: specific descriptor
1581 static inline void i40e_rx_hash(struct i40e_ring *ring,
1582 union i40e_rx_desc *rx_desc,
1583 struct sk_buff *skb,
1587 const __le64 rss_mask =
1588 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1589 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1591 if (!(ring->netdev->features & NETIF_F_RXHASH))
1594 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1595 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1596 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
1601 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor
1602 * @rx_ring: rx descriptor ring packet is being transacted on
1603 * @rx_desc: pointer to the EOP Rx descriptor
1604 * @skb: pointer to current skb being populated
1605 * @rx_ptype: the packet type decoded by hardware
1607 * This function checks the ring, descriptor, and packet information in
1608 * order to populate the hash, checksum, VLAN, protocol, and
1609 * other fields within the skb.
1612 void i40e_process_skb_fields(struct i40e_ring *rx_ring,
1613 union i40e_rx_desc *rx_desc, struct sk_buff *skb,
1616 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1617 u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1618 I40E_RXD_QW1_STATUS_SHIFT;
1619 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK;
1620 u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1621 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT;
1623 if (unlikely(tsynvalid))
1624 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn);
1626 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1628 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);
1630 skb_record_rx_queue(skb, rx_ring->queue_index);
1632 /* modifies the skb - consumes the enet header */
1633 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1637 * i40e_cleanup_headers - Correct empty headers
1638 * @rx_ring: rx descriptor ring packet is being transacted on
1639 * @skb: pointer to current skb being fixed
1640 * @rx_desc: pointer to the EOP Rx descriptor
1642 * Also address the case where we are pulling data in on pages only
1643 * and as such no data is present in the skb header.
1645 * In addition if skb is not at least 60 bytes we need to pad it so that
1646 * it is large enough to qualify as a valid Ethernet frame.
1648 * Returns true if an error was encountered and skb was freed.
1650 static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb,
1651 union i40e_rx_desc *rx_desc)
1654 /* XDP packets use error pointer so abort at this point */
1658 /* ERR_MASK will only have valid bits if EOP set, and
1659 * what we are doing here is actually checking
1660 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1663 if (unlikely(i40e_test_staterr(rx_desc,
1664 BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
1665 dev_kfree_skb_any(skb);
1669 /* if eth_skb_pad returns an error the skb was freed */
1670 if (eth_skb_pad(skb))
1677 * i40e_page_is_reusable - check if any reuse is possible
1678 * @page: page struct to check
1680 * A page is not reusable if it was allocated under low memory
1681 * conditions, or it's not in the same NUMA node as this CPU.
1683 static inline bool i40e_page_is_reusable(struct page *page)
1685 return (page_to_nid(page) == numa_mem_id()) &&
1686 !page_is_pfmemalloc(page);
1690 * i40e_can_reuse_rx_page - Determine if this page can be reused by
1691 * the adapter for another receive
1693 * @rx_buffer: buffer containing the page
1695 * If page is reusable, rx_buffer->page_offset is adjusted to point to
1696 * an unused region in the page.
1698 * For small pages, @truesize will be a constant value, half the size
1699 * of the memory at page. We'll attempt to alternate between high and
1700 * low halves of the page, with one half ready for use by the hardware
1701 * and the other half being consumed by the stack. We use the page
1702 * ref count to determine whether the stack has finished consuming the
1703 * portion of this page that was passed up with a previous packet. If
1704 * the page ref count is >1, we'll assume the "other" half page is
1705 * still busy, and this page cannot be reused.
1707 * For larger pages, @truesize will be the actual space used by the
1708 * received packet (adjusted upward to an even multiple of the cache
1709 * line size). This will advance through the page by the amount
1710 * actually consumed by the received packets while there is still
1711 * space for a buffer. Each region of larger pages will be used at
1712 * most once, after which the page will not be reused.
1714 * In either case, if the page is reusable its refcount is increased.
1716 static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer)
1718 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1719 struct page *page = rx_buffer->page;
1721 /* Is any reuse possible? */
1722 if (unlikely(!i40e_page_is_reusable(page)))
1725 #if (PAGE_SIZE < 8192)
1726 /* if we are only owner of page we can reuse it */
1727 if (unlikely((page_count(page) - pagecnt_bias) > 1))
1730 #define I40E_LAST_OFFSET \
1731 (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048)
1732 if (rx_buffer->page_offset > I40E_LAST_OFFSET)
1736 /* If we have drained the page fragment pool we need to update
1737 * the pagecnt_bias and page count so that we fully restock the
1738 * number of references the driver holds.
1740 if (unlikely(!pagecnt_bias)) {
1741 page_ref_add(page, USHRT_MAX);
1742 rx_buffer->pagecnt_bias = USHRT_MAX;
1749 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff
1750 * @rx_ring: rx descriptor ring to transact packets on
1751 * @rx_buffer: buffer containing page to add
1752 * @skb: sk_buff to place the data into
1753 * @size: packet length from rx_desc
1755 * This function will add the data contained in rx_buffer->page to the skb.
1756 * It will just attach the page as a frag to the skb.
1758 * The function will then update the page offset.
1760 static void i40e_add_rx_frag(struct i40e_ring *rx_ring,
1761 struct i40e_rx_buffer *rx_buffer,
1762 struct sk_buff *skb,
1765 #if (PAGE_SIZE < 8192)
1766 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1768 unsigned int truesize = SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring));
1771 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1772 rx_buffer->page_offset, size, truesize);
1774 /* page is being used so we must update the page offset */
1775 #if (PAGE_SIZE < 8192)
1776 rx_buffer->page_offset ^= truesize;
1778 rx_buffer->page_offset += truesize;
1783 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use
1784 * @rx_ring: rx descriptor ring to transact packets on
1785 * @size: size of buffer to add to skb
1787 * This function will pull an Rx buffer from the ring and synchronize it
1788 * for use by the CPU.
1790 static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring,
1791 const unsigned int size)
1793 struct i40e_rx_buffer *rx_buffer;
1795 rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean];
1796 prefetchw(rx_buffer->page);
1798 /* we are reusing so sync this buffer for CPU use */
1799 dma_sync_single_range_for_cpu(rx_ring->dev,
1801 rx_buffer->page_offset,
1805 /* We have pulled a buffer for use, so decrement pagecnt_bias */
1806 rx_buffer->pagecnt_bias--;
1812 * i40e_construct_skb - Allocate skb and populate it
1813 * @rx_ring: rx descriptor ring to transact packets on
1814 * @rx_buffer: rx buffer to pull data from
1815 * @xdp: xdp_buff pointing to the data
1817 * This function allocates an skb. It then populates it with the page
1818 * data from the current receive descriptor, taking care to set up the
1821 static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring,
1822 struct i40e_rx_buffer *rx_buffer,
1823 struct xdp_buff *xdp)
1825 unsigned int size = xdp->data_end - xdp->data;
1826 #if (PAGE_SIZE < 8192)
1827 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1829 unsigned int truesize = SKB_DATA_ALIGN(size);
1831 unsigned int headlen;
1832 struct sk_buff *skb;
1834 /* prefetch first cache line of first page */
1835 prefetch(xdp->data);
1836 #if L1_CACHE_BYTES < 128
1837 prefetch(xdp->data + L1_CACHE_BYTES);
1840 /* allocate a skb to store the frags */
1841 skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
1843 GFP_ATOMIC | __GFP_NOWARN);
1847 /* Determine available headroom for copy */
1849 if (headlen > I40E_RX_HDR_SIZE)
1850 headlen = eth_get_headlen(xdp->data, I40E_RX_HDR_SIZE);
1852 /* align pull length to size of long to optimize memcpy performance */
1853 memcpy(__skb_put(skb, headlen), xdp->data,
1854 ALIGN(headlen, sizeof(long)));
1856 /* update all of the pointers */
1859 skb_add_rx_frag(skb, 0, rx_buffer->page,
1860 rx_buffer->page_offset + headlen,
1863 /* buffer is used by skb, update page_offset */
1864 #if (PAGE_SIZE < 8192)
1865 rx_buffer->page_offset ^= truesize;
1867 rx_buffer->page_offset += truesize;
1870 /* buffer is unused, reset bias back to rx_buffer */
1871 rx_buffer->pagecnt_bias++;
1878 * i40e_build_skb - Build skb around an existing buffer
1879 * @rx_ring: Rx descriptor ring to transact packets on
1880 * @rx_buffer: Rx buffer to pull data from
1881 * @xdp: xdp_buff pointing to the data
1883 * This function builds an skb around an existing Rx buffer, taking care
1884 * to set up the skb correctly and avoid any memcpy overhead.
1886 static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring,
1887 struct i40e_rx_buffer *rx_buffer,
1888 struct xdp_buff *xdp)
1890 unsigned int size = xdp->data_end - xdp->data;
1891 #if (PAGE_SIZE < 8192)
1892 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1894 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
1895 SKB_DATA_ALIGN(I40E_SKB_PAD + size);
1897 struct sk_buff *skb;
1899 /* prefetch first cache line of first page */
1900 prefetch(xdp->data);
1901 #if L1_CACHE_BYTES < 128
1902 prefetch(xdp->data + L1_CACHE_BYTES);
1904 /* build an skb around the page buffer */
1905 skb = build_skb(xdp->data_hard_start, truesize);
1909 /* update pointers within the skb to store the data */
1910 skb_reserve(skb, I40E_SKB_PAD);
1911 __skb_put(skb, size);
1913 /* buffer is used by skb, update page_offset */
1914 #if (PAGE_SIZE < 8192)
1915 rx_buffer->page_offset ^= truesize;
1917 rx_buffer->page_offset += truesize;
1924 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free
1925 * @rx_ring: rx descriptor ring to transact packets on
1926 * @rx_buffer: rx buffer to pull data from
1928 * This function will clean up the contents of the rx_buffer. It will
1929 * either recycle the bufer or unmap it and free the associated resources.
1931 static void i40e_put_rx_buffer(struct i40e_ring *rx_ring,
1932 struct i40e_rx_buffer *rx_buffer)
1934 if (i40e_can_reuse_rx_page(rx_buffer)) {
1935 /* hand second half of page back to the ring */
1936 i40e_reuse_rx_page(rx_ring, rx_buffer);
1937 rx_ring->rx_stats.page_reuse_count++;
1939 /* we are not reusing the buffer so unmap it */
1940 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
1941 i40e_rx_pg_size(rx_ring),
1942 DMA_FROM_DEVICE, I40E_RX_DMA_ATTR);
1943 __page_frag_cache_drain(rx_buffer->page,
1944 rx_buffer->pagecnt_bias);
1947 /* clear contents of buffer_info */
1948 rx_buffer->page = NULL;
1952 * i40e_is_non_eop - process handling of non-EOP buffers
1953 * @rx_ring: Rx ring being processed
1954 * @rx_desc: Rx descriptor for current buffer
1955 * @skb: Current socket buffer containing buffer in progress
1957 * This function updates next to clean. If the buffer is an EOP buffer
1958 * this function exits returning false, otherwise it will place the
1959 * sk_buff in the next buffer to be chained and return true indicating
1960 * that this is in fact a non-EOP buffer.
1962 static bool i40e_is_non_eop(struct i40e_ring *rx_ring,
1963 union i40e_rx_desc *rx_desc,
1964 struct sk_buff *skb)
1966 u32 ntc = rx_ring->next_to_clean + 1;
1968 /* fetch, update, and store next to clean */
1969 ntc = (ntc < rx_ring->count) ? ntc : 0;
1970 rx_ring->next_to_clean = ntc;
1972 prefetch(I40E_RX_DESC(rx_ring, ntc));
1974 /* if we are the last buffer then there is nothing else to do */
1975 #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
1976 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
1979 rx_ring->rx_stats.non_eop_descs++;
1984 #define I40E_XDP_PASS 0
1985 #define I40E_XDP_CONSUMED 1
1986 #define I40E_XDP_TX 2
1988 static int i40e_xmit_xdp_ring(struct xdp_buff *xdp,
1989 struct i40e_ring *xdp_ring);
1992 * i40e_run_xdp - run an XDP program
1993 * @rx_ring: Rx ring being processed
1994 * @xdp: XDP buffer containing the frame
1996 static struct sk_buff *i40e_run_xdp(struct i40e_ring *rx_ring,
1997 struct xdp_buff *xdp)
1999 int result = I40E_XDP_PASS;
2000 struct i40e_ring *xdp_ring;
2001 struct bpf_prog *xdp_prog;
2005 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2010 act = bpf_prog_run_xdp(xdp_prog, xdp);
2015 xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2016 result = i40e_xmit_xdp_ring(xdp, xdp_ring);
2019 bpf_warn_invalid_xdp_action(act);
2021 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2022 /* fallthrough -- handle aborts by dropping packet */
2024 result = I40E_XDP_CONSUMED;
2029 return ERR_PTR(-result);
2033 * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region
2035 * @rx_buffer: Rx buffer to adjust
2036 * @size: Size of adjustment
2038 static void i40e_rx_buffer_flip(struct i40e_ring *rx_ring,
2039 struct i40e_rx_buffer *rx_buffer,
2042 #if (PAGE_SIZE < 8192)
2043 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2045 rx_buffer->page_offset ^= truesize;
2047 unsigned int truesize = SKB_DATA_ALIGN(i40e_rx_offset(rx_ring) + size);
2049 rx_buffer->page_offset += truesize;
2054 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2055 * @rx_ring: rx descriptor ring to transact packets on
2056 * @budget: Total limit on number of packets to process
2058 * This function provides a "bounce buffer" approach to Rx interrupt
2059 * processing. The advantage to this is that on systems that have
2060 * expensive overhead for IOMMU access this provides a means of avoiding
2061 * it by maintaining the mapping of the page to the system.
2063 * Returns amount of work completed
2065 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
2067 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2068 struct sk_buff *skb = rx_ring->skb;
2069 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
2070 bool failure = false, xdp_xmit = false;
2072 while (likely(total_rx_packets < (unsigned int)budget)) {
2073 struct i40e_rx_buffer *rx_buffer;
2074 union i40e_rx_desc *rx_desc;
2075 struct xdp_buff xdp;
2081 /* return some buffers to hardware, one at a time is too slow */
2082 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
2083 failure = failure ||
2084 i40e_alloc_rx_buffers(rx_ring, cleaned_count);
2088 rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);
2090 /* status_error_len will always be zero for unused descriptors
2091 * because it's cleared in cleanup, and overlaps with hdr_addr
2092 * which is always zero because packet split isn't used, if the
2093 * hardware wrote DD then the length will be non-zero
2095 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
2097 /* This memory barrier is needed to keep us from reading
2098 * any other fields out of the rx_desc until we have
2099 * verified the descriptor has been written back.
2103 if (unlikely(i40e_rx_is_programming_status(qword))) {
2104 i40e_clean_programming_status(rx_ring, rx_desc, qword);
2108 size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
2109 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
2113 i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb);
2114 rx_buffer = i40e_get_rx_buffer(rx_ring, size);
2116 /* retrieve a buffer from the ring */
2118 xdp.data = page_address(rx_buffer->page) +
2119 rx_buffer->page_offset;
2120 xdp.data_hard_start = xdp.data -
2121 i40e_rx_offset(rx_ring);
2122 xdp.data_end = xdp.data + size;
2124 skb = i40e_run_xdp(rx_ring, &xdp);
2128 if (PTR_ERR(skb) == -I40E_XDP_TX) {
2130 i40e_rx_buffer_flip(rx_ring, rx_buffer, size);
2132 rx_buffer->pagecnt_bias++;
2134 total_rx_bytes += size;
2137 i40e_add_rx_frag(rx_ring, rx_buffer, skb, size);
2138 } else if (ring_uses_build_skb(rx_ring)) {
2139 skb = i40e_build_skb(rx_ring, rx_buffer, &xdp);
2141 skb = i40e_construct_skb(rx_ring, rx_buffer, &xdp);
2144 /* exit if we failed to retrieve a buffer */
2146 rx_ring->rx_stats.alloc_buff_failed++;
2147 rx_buffer->pagecnt_bias++;
2151 i40e_put_rx_buffer(rx_ring, rx_buffer);
2154 if (i40e_is_non_eop(rx_ring, rx_desc, skb))
2157 if (i40e_cleanup_headers(rx_ring, skb, rx_desc)) {
2162 /* probably a little skewed due to removing CRC */
2163 total_rx_bytes += skb->len;
2165 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
2166 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
2167 I40E_RXD_QW1_PTYPE_SHIFT;
2169 /* populate checksum, VLAN, and protocol */
2170 i40e_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);
2172 vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
2173 le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0;
2175 i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);
2176 i40e_receive_skb(rx_ring, skb, vlan_tag);
2179 /* update budget accounting */
2184 struct i40e_ring *xdp_ring;
2186 xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2188 /* Force memory writes to complete before letting h/w
2189 * know there are new descriptors to fetch.
2193 writel(xdp_ring->next_to_use, xdp_ring->tail);
2198 u64_stats_update_begin(&rx_ring->syncp);
2199 rx_ring->stats.packets += total_rx_packets;
2200 rx_ring->stats.bytes += total_rx_bytes;
2201 u64_stats_update_end(&rx_ring->syncp);
2202 rx_ring->q_vector->rx.total_packets += total_rx_packets;
2203 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
2205 /* guarantee a trip back through this routine if there was a failure */
2206 return failure ? budget : (int)total_rx_packets;
2209 static u32 i40e_buildreg_itr(const int type, const u16 itr)
2213 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2214 /* Don't clear PBA because that can cause lost interrupts that
2215 * came in while we were cleaning/polling
2217 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
2218 (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
2223 /* a small macro to shorten up some long lines */
2224 #define INTREG I40E_PFINT_DYN_CTLN
2225 static inline int get_rx_itr(struct i40e_vsi *vsi, int idx)
2227 return vsi->rx_rings[idx]->rx_itr_setting;
2230 static inline int get_tx_itr(struct i40e_vsi *vsi, int idx)
2232 return vsi->tx_rings[idx]->tx_itr_setting;
2236 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
2237 * @vsi: the VSI we care about
2238 * @q_vector: q_vector for which itr is being updated and interrupt enabled
2241 static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
2242 struct i40e_q_vector *q_vector)
2244 struct i40e_hw *hw = &vsi->back->hw;
2245 bool rx = false, tx = false;
2248 int idx = q_vector->v_idx;
2249 int rx_itr_setting, tx_itr_setting;
2251 /* If we don't have MSIX, then we only need to re-enable icr0 */
2252 if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) {
2253 i40e_irq_dynamic_enable_icr0(vsi->back, false);
2257 vector = (q_vector->v_idx + vsi->base_vector);
2259 /* avoid dynamic calculation if in countdown mode OR if
2260 * all dynamic is disabled
2262 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
2264 rx_itr_setting = get_rx_itr(vsi, idx);
2265 tx_itr_setting = get_tx_itr(vsi, idx);
2267 if (q_vector->itr_countdown > 0 ||
2268 (!ITR_IS_DYNAMIC(rx_itr_setting) &&
2269 !ITR_IS_DYNAMIC(tx_itr_setting))) {
2273 if (ITR_IS_DYNAMIC(rx_itr_setting)) {
2274 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
2275 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
2278 if (ITR_IS_DYNAMIC(tx_itr_setting)) {
2279 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
2280 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
2284 /* get the higher of the two ITR adjustments and
2285 * use the same value for both ITR registers
2286 * when in adaptive mode (Rx and/or Tx)
2288 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
2290 q_vector->tx.itr = q_vector->rx.itr = itr;
2291 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
2293 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
2297 /* only need to enable the interrupt once, but need
2298 * to possibly update both ITR values
2301 /* set the INTENA_MSK_MASK so that this first write
2302 * won't actually enable the interrupt, instead just
2303 * updating the ITR (it's bit 31 PF and VF)
2306 /* don't check _DOWN because interrupt isn't being enabled */
2307 wr32(hw, INTREG(vector - 1), rxval);
2311 if (!test_bit(__I40E_VSI_DOWN, vsi->state))
2312 wr32(hw, INTREG(vector - 1), txval);
2314 if (q_vector->itr_countdown)
2315 q_vector->itr_countdown--;
2317 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2321 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
2322 * @napi: napi struct with our devices info in it
2323 * @budget: amount of work driver is allowed to do this pass, in packets
2325 * This function will clean all queues associated with a q_vector.
2327 * Returns the amount of work done
2329 int i40e_napi_poll(struct napi_struct *napi, int budget)
2331 struct i40e_q_vector *q_vector =
2332 container_of(napi, struct i40e_q_vector, napi);
2333 struct i40e_vsi *vsi = q_vector->vsi;
2334 struct i40e_ring *ring;
2335 bool clean_complete = true;
2336 bool arm_wb = false;
2337 int budget_per_ring;
2340 if (test_bit(__I40E_VSI_DOWN, vsi->state)) {
2341 napi_complete(napi);
2345 /* Since the actual Tx work is minimal, we can give the Tx a larger
2346 * budget and be more aggressive about cleaning up the Tx descriptors.
2348 i40e_for_each_ring(ring, q_vector->tx) {
2349 if (!i40e_clean_tx_irq(vsi, ring, budget)) {
2350 clean_complete = false;
2353 arm_wb |= ring->arm_wb;
2354 ring->arm_wb = false;
2357 /* Handle case where we are called by netpoll with a budget of 0 */
2361 /* We attempt to distribute budget to each Rx queue fairly, but don't
2362 * allow the budget to go below 1 because that would exit polling early.
2364 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
2366 i40e_for_each_ring(ring, q_vector->rx) {
2367 int cleaned = i40e_clean_rx_irq(ring, budget_per_ring);
2369 work_done += cleaned;
2370 /* if we clean as many as budgeted, we must not be done */
2371 if (cleaned >= budget_per_ring)
2372 clean_complete = false;
2375 /* If work not completed, return budget and polling will return */
2376 if (!clean_complete) {
2377 int cpu_id = smp_processor_id();
2379 /* It is possible that the interrupt affinity has changed but,
2380 * if the cpu is pegged at 100%, polling will never exit while
2381 * traffic continues and the interrupt will be stuck on this
2382 * cpu. We check to make sure affinity is correct before we
2383 * continue to poll, otherwise we must stop polling so the
2384 * interrupt can move to the correct cpu.
2386 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) {
2387 /* Tell napi that we are done polling */
2388 napi_complete_done(napi, work_done);
2390 /* Force an interrupt */
2391 i40e_force_wb(vsi, q_vector);
2393 /* Return budget-1 so that polling stops */
2398 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
2399 i40e_enable_wb_on_itr(vsi, q_vector);
2404 if (q_vector->tx.ring[0].flags & I40E_TXR_FLAGS_WB_ON_ITR)
2405 q_vector->arm_wb_state = false;
2407 /* Work is done so exit the polling mode and re-enable the interrupt */
2408 napi_complete_done(napi, work_done);
2410 i40e_update_enable_itr(vsi, q_vector);
2412 return min(work_done, budget - 1);
2416 * i40e_atr - Add a Flow Director ATR filter
2417 * @tx_ring: ring to add programming descriptor to
2419 * @tx_flags: send tx flags
2421 static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2424 struct i40e_filter_program_desc *fdir_desc;
2425 struct i40e_pf *pf = tx_ring->vsi->back;
2427 unsigned char *network;
2429 struct ipv6hdr *ipv6;
2433 u32 flex_ptype, dtype_cmd;
2437 /* make sure ATR is enabled */
2438 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
2441 if (pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED)
2444 /* if sampling is disabled do nothing */
2445 if (!tx_ring->atr_sample_rate)
2448 /* Currently only IPv4/IPv6 with TCP is supported */
2449 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
2452 /* snag network header to get L4 type and address */
2453 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ?
2454 skb_inner_network_header(skb) : skb_network_header(skb);
2456 /* Note: tx_flags gets modified to reflect inner protocols in
2457 * tx_enable_csum function if encap is enabled.
2459 if (tx_flags & I40E_TX_FLAGS_IPV4) {
2460 /* access ihl as u8 to avoid unaligned access on ia64 */
2461 hlen = (hdr.network[0] & 0x0F) << 2;
2462 l4_proto = hdr.ipv4->protocol;
2464 /* find the start of the innermost ipv6 header */
2465 unsigned int inner_hlen = hdr.network - skb->data;
2466 unsigned int h_offset = inner_hlen;
2468 /* this function updates h_offset to the end of the header */
2470 ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL);
2471 /* hlen will contain our best estimate of the tcp header */
2472 hlen = h_offset - inner_hlen;
2475 if (l4_proto != IPPROTO_TCP)
2478 th = (struct tcphdr *)(hdr.network + hlen);
2480 /* Due to lack of space, no more new filters can be programmed */
2481 if (th->syn && (pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED))
2483 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) {
2484 /* HW ATR eviction will take care of removing filters on FIN
2487 if (th->fin || th->rst)
2491 tx_ring->atr_count++;
2493 /* sample on all syn/fin/rst packets or once every atr sample rate */
2497 (tx_ring->atr_count < tx_ring->atr_sample_rate))
2500 tx_ring->atr_count = 0;
2502 /* grab the next descriptor */
2503 i = tx_ring->next_to_use;
2504 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2507 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2509 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2510 I40E_TXD_FLTR_QW0_QINDEX_MASK;
2511 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ?
2512 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2513 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2514 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2515 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2517 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2519 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2521 dtype_cmd |= (th->fin || th->rst) ?
2522 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2523 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2524 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2525 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2527 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2528 I40E_TXD_FLTR_QW1_DEST_SHIFT;
2530 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2531 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2533 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2534 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2536 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2537 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2538 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2541 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2542 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2543 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2545 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED)
2546 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2548 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2549 fdir_desc->rsvd = cpu_to_le32(0);
2550 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2551 fdir_desc->fd_id = cpu_to_le32(0);
2555 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2557 * @tx_ring: ring to send buffer on
2558 * @flags: the tx flags to be set
2560 * Checks the skb and set up correspondingly several generic transmit flags
2561 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2563 * Returns error code indicate the frame should be dropped upon error and the
2564 * otherwise returns 0 to indicate the flags has been set properly.
2566 static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2567 struct i40e_ring *tx_ring,
2570 __be16 protocol = skb->protocol;
2573 if (protocol == htons(ETH_P_8021Q) &&
2574 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2575 /* When HW VLAN acceleration is turned off by the user the
2576 * stack sets the protocol to 8021q so that the driver
2577 * can take any steps required to support the SW only
2578 * VLAN handling. In our case the driver doesn't need
2579 * to take any further steps so just set the protocol
2580 * to the encapsulated ethertype.
2582 skb->protocol = vlan_get_protocol(skb);
2586 /* if we have a HW VLAN tag being added, default to the HW one */
2587 if (skb_vlan_tag_present(skb)) {
2588 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2589 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2590 /* else if it is a SW VLAN, check the next protocol and store the tag */
2591 } else if (protocol == htons(ETH_P_8021Q)) {
2592 struct vlan_hdr *vhdr, _vhdr;
2594 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2598 protocol = vhdr->h_vlan_encapsulated_proto;
2599 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2600 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2603 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2606 /* Insert 802.1p priority into VLAN header */
2607 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2608 (skb->priority != TC_PRIO_CONTROL)) {
2609 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2610 tx_flags |= (skb->priority & 0x7) <<
2611 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2612 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2613 struct vlan_ethhdr *vhdr;
2616 rc = skb_cow_head(skb, 0);
2619 vhdr = (struct vlan_ethhdr *)skb->data;
2620 vhdr->h_vlan_TCI = htons(tx_flags >>
2621 I40E_TX_FLAGS_VLAN_SHIFT);
2623 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2633 * i40e_tso - set up the tso context descriptor
2634 * @first: pointer to first Tx buffer for xmit
2635 * @hdr_len: ptr to the size of the packet header
2636 * @cd_type_cmd_tso_mss: Quad Word 1
2638 * Returns 0 if no TSO can happen, 1 if tso is going, or error
2640 static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len,
2641 u64 *cd_type_cmd_tso_mss)
2643 struct sk_buff *skb = first->skb;
2644 u64 cd_cmd, cd_tso_len, cd_mss;
2655 u32 paylen, l4_offset;
2656 u16 gso_segs, gso_size;
2659 if (skb->ip_summed != CHECKSUM_PARTIAL)
2662 if (!skb_is_gso(skb))
2665 err = skb_cow_head(skb, 0);
2669 ip.hdr = skb_network_header(skb);
2670 l4.hdr = skb_transport_header(skb);
2672 /* initialize outer IP header fields */
2673 if (ip.v4->version == 4) {
2677 ip.v6->payload_len = 0;
2680 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
2684 SKB_GSO_UDP_TUNNEL |
2685 SKB_GSO_UDP_TUNNEL_CSUM)) {
2686 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
2687 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
2690 /* determine offset of outer transport header */
2691 l4_offset = l4.hdr - skb->data;
2693 /* remove payload length from outer checksum */
2694 paylen = skb->len - l4_offset;
2695 csum_replace_by_diff(&l4.udp->check,
2696 (__force __wsum)htonl(paylen));
2699 /* reset pointers to inner headers */
2700 ip.hdr = skb_inner_network_header(skb);
2701 l4.hdr = skb_inner_transport_header(skb);
2703 /* initialize inner IP header fields */
2704 if (ip.v4->version == 4) {
2708 ip.v6->payload_len = 0;
2712 /* determine offset of inner transport header */
2713 l4_offset = l4.hdr - skb->data;
2715 /* remove payload length from inner checksum */
2716 paylen = skb->len - l4_offset;
2717 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
2719 /* compute length of segmentation header */
2720 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
2722 /* pull values out of skb_shinfo */
2723 gso_size = skb_shinfo(skb)->gso_size;
2724 gso_segs = skb_shinfo(skb)->gso_segs;
2726 /* update GSO size and bytecount with header size */
2727 first->gso_segs = gso_segs;
2728 first->bytecount += (first->gso_segs - 1) * *hdr_len;
2730 /* find the field values */
2731 cd_cmd = I40E_TX_CTX_DESC_TSO;
2732 cd_tso_len = skb->len - *hdr_len;
2734 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2735 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2736 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
2741 * i40e_tsyn - set up the tsyn context descriptor
2742 * @tx_ring: ptr to the ring to send
2743 * @skb: ptr to the skb we're sending
2744 * @tx_flags: the collected send information
2745 * @cd_type_cmd_tso_mss: Quad Word 1
2747 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
2749 static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
2750 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
2754 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
2757 /* Tx timestamps cannot be sampled when doing TSO */
2758 if (tx_flags & I40E_TX_FLAGS_TSO)
2761 /* only timestamp the outbound packet if the user has requested it and
2762 * we are not already transmitting a packet to be timestamped
2764 pf = i40e_netdev_to_pf(tx_ring->netdev);
2765 if (!(pf->flags & I40E_FLAG_PTP))
2769 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) {
2770 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2771 pf->ptp_tx_start = jiffies;
2772 pf->ptp_tx_skb = skb_get(skb);
2774 pf->tx_hwtstamp_skipped++;
2778 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
2779 I40E_TXD_CTX_QW1_CMD_SHIFT;
2785 * i40e_tx_enable_csum - Enable Tx checksum offloads
2787 * @tx_flags: pointer to Tx flags currently set
2788 * @td_cmd: Tx descriptor command bits to set
2789 * @td_offset: Tx descriptor header offsets to set
2790 * @tx_ring: Tx descriptor ring
2791 * @cd_tunneling: ptr to context desc bits
2793 static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
2794 u32 *td_cmd, u32 *td_offset,
2795 struct i40e_ring *tx_ring,
2808 unsigned char *exthdr;
2809 u32 offset, cmd = 0;
2813 if (skb->ip_summed != CHECKSUM_PARTIAL)
2816 ip.hdr = skb_network_header(skb);
2817 l4.hdr = skb_transport_header(skb);
2819 /* compute outer L2 header size */
2820 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
2822 if (skb->encapsulation) {
2824 /* define outer network header type */
2825 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2826 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
2827 I40E_TX_CTX_EXT_IP_IPV4 :
2828 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
2830 l4_proto = ip.v4->protocol;
2831 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
2834 tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
2836 exthdr = ip.hdr + sizeof(*ip.v6);
2837 l4_proto = ip.v6->nexthdr;
2838 ret = ipv6_skip_exthdr(skb, exthdr - skb->data,
2839 &l4_proto, &frag_off);
2844 /* define outer transport */
2847 tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
2848 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
2851 tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
2852 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
2856 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
2857 l4.hdr = skb_inner_network_header(skb);
2860 if (*tx_flags & I40E_TX_FLAGS_TSO)
2863 skb_checksum_help(skb);
2867 /* compute outer L3 header size */
2868 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
2869 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
2871 /* switch IP header pointer from outer to inner header */
2872 ip.hdr = skb_inner_network_header(skb);
2874 /* compute tunnel header size */
2875 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
2876 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
2878 /* indicate if we need to offload outer UDP header */
2879 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
2880 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
2881 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
2882 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
2884 /* record tunnel offload values */
2885 *cd_tunneling |= tunnel;
2887 /* switch L4 header pointer from outer to inner */
2888 l4.hdr = skb_inner_transport_header(skb);
2891 /* reset type as we transition from outer to inner headers */
2892 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
2893 if (ip.v4->version == 4)
2894 *tx_flags |= I40E_TX_FLAGS_IPV4;
2895 if (ip.v6->version == 6)
2896 *tx_flags |= I40E_TX_FLAGS_IPV6;
2899 /* Enable IP checksum offloads */
2900 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2901 l4_proto = ip.v4->protocol;
2902 /* the stack computes the IP header already, the only time we
2903 * need the hardware to recompute it is in the case of TSO.
2905 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
2906 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
2907 I40E_TX_DESC_CMD_IIPT_IPV4;
2908 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
2909 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
2911 exthdr = ip.hdr + sizeof(*ip.v6);
2912 l4_proto = ip.v6->nexthdr;
2913 if (l4.hdr != exthdr)
2914 ipv6_skip_exthdr(skb, exthdr - skb->data,
2915 &l4_proto, &frag_off);
2918 /* compute inner L3 header size */
2919 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2921 /* Enable L4 checksum offloads */
2924 /* enable checksum offloads */
2925 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
2926 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2929 /* enable SCTP checksum offload */
2930 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
2931 offset |= (sizeof(struct sctphdr) >> 2) <<
2932 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2935 /* enable UDP checksum offload */
2936 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
2937 offset |= (sizeof(struct udphdr) >> 2) <<
2938 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2941 if (*tx_flags & I40E_TX_FLAGS_TSO)
2943 skb_checksum_help(skb);
2948 *td_offset |= offset;
2954 * i40e_create_tx_ctx Build the Tx context descriptor
2955 * @tx_ring: ring to create the descriptor on
2956 * @cd_type_cmd_tso_mss: Quad Word 1
2957 * @cd_tunneling: Quad Word 0 - bits 0-31
2958 * @cd_l2tag2: Quad Word 0 - bits 32-63
2960 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
2961 const u64 cd_type_cmd_tso_mss,
2962 const u32 cd_tunneling, const u32 cd_l2tag2)
2964 struct i40e_tx_context_desc *context_desc;
2965 int i = tx_ring->next_to_use;
2967 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
2968 !cd_tunneling && !cd_l2tag2)
2971 /* grab the next descriptor */
2972 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
2975 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2977 /* cpu_to_le32 and assign to struct fields */
2978 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
2979 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
2980 context_desc->rsvd = cpu_to_le16(0);
2981 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
2985 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
2986 * @tx_ring: the ring to be checked
2987 * @size: the size buffer we want to assure is available
2989 * Returns -EBUSY if a stop is needed, else 0
2991 int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2993 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2994 /* Memory barrier before checking head and tail */
2997 /* Check again in a case another CPU has just made room available. */
2998 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
3001 /* A reprieve! - use start_queue because it doesn't call schedule */
3002 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
3003 ++tx_ring->tx_stats.restart_queue;
3008 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet
3011 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
3012 * and so we need to figure out the cases where we need to linearize the skb.
3014 * For TSO we need to count the TSO header and segment payload separately.
3015 * As such we need to check cases where we have 7 fragments or more as we
3016 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
3017 * the segment payload in the first descriptor, and another 7 for the
3020 bool __i40e_chk_linearize(struct sk_buff *skb)
3022 const struct skb_frag_struct *frag, *stale;
3025 /* no need to check if number of frags is less than 7 */
3026 nr_frags = skb_shinfo(skb)->nr_frags;
3027 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
3030 /* We need to walk through the list and validate that each group
3031 * of 6 fragments totals at least gso_size.
3033 nr_frags -= I40E_MAX_BUFFER_TXD - 2;
3034 frag = &skb_shinfo(skb)->frags[0];
3036 /* Initialize size to the negative value of gso_size minus 1. We
3037 * use this as the worst case scenerio in which the frag ahead
3038 * of us only provides one byte which is why we are limited to 6
3039 * descriptors for a single transmit as the header and previous
3040 * fragment are already consuming 2 descriptors.
3042 sum = 1 - skb_shinfo(skb)->gso_size;
3044 /* Add size of frags 0 through 4 to create our initial sum */
3045 sum += skb_frag_size(frag++);
3046 sum += skb_frag_size(frag++);
3047 sum += skb_frag_size(frag++);
3048 sum += skb_frag_size(frag++);
3049 sum += skb_frag_size(frag++);
3051 /* Walk through fragments adding latest fragment, testing it, and
3052 * then removing stale fragments from the sum.
3054 for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
3055 int stale_size = skb_frag_size(stale);
3057 sum += skb_frag_size(frag++);
3059 /* The stale fragment may present us with a smaller
3060 * descriptor than the actual fragment size. To account
3061 * for that we need to remove all the data on the front and
3062 * figure out what the remainder would be in the last
3063 * descriptor associated with the fragment.
3065 if (stale_size > I40E_MAX_DATA_PER_TXD) {
3066 int align_pad = -(stale->page_offset) &
3067 (I40E_MAX_READ_REQ_SIZE - 1);
3070 stale_size -= align_pad;
3073 sum -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3074 stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3075 } while (stale_size > I40E_MAX_DATA_PER_TXD);
3078 /* if sum is negative we failed to make sufficient progress */
3092 * i40e_tx_map - Build the Tx descriptor
3093 * @tx_ring: ring to send buffer on
3095 * @first: first buffer info buffer to use
3096 * @tx_flags: collected send information
3097 * @hdr_len: size of the packet header
3098 * @td_cmd: the command field in the descriptor
3099 * @td_offset: offset for checksum or crc
3101 * Returns 0 on success, -1 on failure to DMA
3103 static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
3104 struct i40e_tx_buffer *first, u32 tx_flags,
3105 const u8 hdr_len, u32 td_cmd, u32 td_offset)
3107 unsigned int data_len = skb->data_len;
3108 unsigned int size = skb_headlen(skb);
3109 struct skb_frag_struct *frag;
3110 struct i40e_tx_buffer *tx_bi;
3111 struct i40e_tx_desc *tx_desc;
3112 u16 i = tx_ring->next_to_use;
3117 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
3118 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
3119 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
3120 I40E_TX_FLAGS_VLAN_SHIFT;
3123 first->tx_flags = tx_flags;
3125 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
3127 tx_desc = I40E_TX_DESC(tx_ring, i);
3130 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
3131 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3133 if (dma_mapping_error(tx_ring->dev, dma))
3136 /* record length, and DMA address */
3137 dma_unmap_len_set(tx_bi, len, size);
3138 dma_unmap_addr_set(tx_bi, dma, dma);
3140 /* align size to end of page */
3141 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
3142 tx_desc->buffer_addr = cpu_to_le64(dma);
3144 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
3145 tx_desc->cmd_type_offset_bsz =
3146 build_ctob(td_cmd, td_offset,
3153 if (i == tx_ring->count) {
3154 tx_desc = I40E_TX_DESC(tx_ring, 0);
3161 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3162 tx_desc->buffer_addr = cpu_to_le64(dma);
3165 if (likely(!data_len))
3168 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
3175 if (i == tx_ring->count) {
3176 tx_desc = I40E_TX_DESC(tx_ring, 0);
3180 size = skb_frag_size(frag);
3183 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
3186 tx_bi = &tx_ring->tx_bi[i];
3189 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
3192 if (i == tx_ring->count)
3195 tx_ring->next_to_use = i;
3197 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
3199 /* write last descriptor with EOP bit */
3200 td_cmd |= I40E_TX_DESC_CMD_EOP;
3202 /* We can OR these values together as they both are checked against
3203 * 4 below and at this point desc_count will be used as a boolean value
3204 * after this if/else block.
3206 desc_count |= ++tx_ring->packet_stride;
3208 /* Algorithm to optimize tail and RS bit setting:
3209 * if queue is stopped
3211 * reset packet counter
3212 * else if xmit_more is supported and is true
3213 * advance packet counter to 4
3214 * reset desc_count to 0
3216 * if desc_count >= 4
3218 * reset packet counter
3222 * Note: If there are less than 4 descriptors
3223 * pending and interrupts were disabled the service task will
3224 * trigger a force WB.
3226 if (netif_xmit_stopped(txring_txq(tx_ring))) {
3228 } else if (skb->xmit_more) {
3229 /* set stride to arm on next packet and reset desc_count */
3230 tx_ring->packet_stride = WB_STRIDE;
3232 } else if (desc_count >= WB_STRIDE) {
3234 /* write last descriptor with RS bit set */
3235 td_cmd |= I40E_TX_DESC_CMD_RS;
3236 tx_ring->packet_stride = 0;
3239 tx_desc->cmd_type_offset_bsz =
3240 build_ctob(td_cmd, td_offset, size, td_tag);
3242 /* Force memory writes to complete before letting h/w know there
3243 * are new descriptors to fetch.
3245 * We also use this memory barrier to make certain all of the
3246 * status bits have been updated before next_to_watch is written.
3250 /* set next_to_watch value indicating a packet is present */
3251 first->next_to_watch = tx_desc;
3253 /* notify HW of packet */
3255 writel(i, tx_ring->tail);
3257 /* we need this if more than one processor can write to our tail
3258 * at a time, it synchronizes IO on IA64/Altix systems
3266 dev_info(tx_ring->dev, "TX DMA map failed\n");
3268 /* clear dma mappings for failed tx_bi map */
3270 tx_bi = &tx_ring->tx_bi[i];
3271 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
3279 tx_ring->next_to_use = i;
3285 * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring
3286 * @xdp: data to transmit
3287 * @xdp_ring: XDP Tx ring
3289 static int i40e_xmit_xdp_ring(struct xdp_buff *xdp,
3290 struct i40e_ring *xdp_ring)
3292 u32 size = xdp->data_end - xdp->data;
3293 u16 i = xdp_ring->next_to_use;
3294 struct i40e_tx_buffer *tx_bi;
3295 struct i40e_tx_desc *tx_desc;
3298 if (!unlikely(I40E_DESC_UNUSED(xdp_ring))) {
3299 xdp_ring->tx_stats.tx_busy++;
3300 return I40E_XDP_CONSUMED;
3303 dma = dma_map_single(xdp_ring->dev, xdp->data, size, DMA_TO_DEVICE);
3304 if (dma_mapping_error(xdp_ring->dev, dma))
3305 return I40E_XDP_CONSUMED;
3307 tx_bi = &xdp_ring->tx_bi[i];
3308 tx_bi->bytecount = size;
3309 tx_bi->gso_segs = 1;
3310 tx_bi->raw_buf = xdp->data;
3312 /* record length, and DMA address */
3313 dma_unmap_len_set(tx_bi, len, size);
3314 dma_unmap_addr_set(tx_bi, dma, dma);
3316 tx_desc = I40E_TX_DESC(xdp_ring, i);
3317 tx_desc->buffer_addr = cpu_to_le64(dma);
3318 tx_desc->cmd_type_offset_bsz = build_ctob(I40E_TX_DESC_CMD_ICRC
3322 /* Make certain all of the status bits have been updated
3323 * before next_to_watch is written.
3328 if (i == xdp_ring->count)
3331 tx_bi->next_to_watch = tx_desc;
3332 xdp_ring->next_to_use = i;
3338 * i40e_xmit_frame_ring - Sends buffer on Tx ring
3340 * @tx_ring: ring to send buffer on
3342 * Returns NETDEV_TX_OK if sent, else an error code
3344 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
3345 struct i40e_ring *tx_ring)
3347 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
3348 u32 cd_tunneling = 0, cd_l2tag2 = 0;
3349 struct i40e_tx_buffer *first;
3358 /* prefetch the data, we'll need it later */
3359 prefetch(skb->data);
3361 i40e_trace(xmit_frame_ring, skb, tx_ring);
3363 count = i40e_xmit_descriptor_count(skb);
3364 if (i40e_chk_linearize(skb, count)) {
3365 if (__skb_linearize(skb)) {
3366 dev_kfree_skb_any(skb);
3367 return NETDEV_TX_OK;
3369 count = i40e_txd_use_count(skb->len);
3370 tx_ring->tx_stats.tx_linearize++;
3373 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
3374 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
3375 * + 4 desc gap to avoid the cache line where head is,
3376 * + 1 desc for context descriptor,
3377 * otherwise try next time
3379 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
3380 tx_ring->tx_stats.tx_busy++;
3381 return NETDEV_TX_BUSY;
3384 /* record the location of the first descriptor for this packet */
3385 first = &tx_ring->tx_bi[tx_ring->next_to_use];
3387 first->bytecount = skb->len;
3388 first->gso_segs = 1;
3390 /* prepare the xmit flags */
3391 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
3394 /* obtain protocol of skb */
3395 protocol = vlan_get_protocol(skb);
3397 /* setup IPv4/IPv6 offloads */
3398 if (protocol == htons(ETH_P_IP))
3399 tx_flags |= I40E_TX_FLAGS_IPV4;
3400 else if (protocol == htons(ETH_P_IPV6))
3401 tx_flags |= I40E_TX_FLAGS_IPV6;
3403 tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
3408 tx_flags |= I40E_TX_FLAGS_TSO;
3410 /* Always offload the checksum, since it's in the data descriptor */
3411 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
3412 tx_ring, &cd_tunneling);
3416 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
3419 tx_flags |= I40E_TX_FLAGS_TSYN;
3421 skb_tx_timestamp(skb);
3423 /* always enable CRC insertion offload */
3424 td_cmd |= I40E_TX_DESC_CMD_ICRC;
3426 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
3427 cd_tunneling, cd_l2tag2);
3429 /* Add Flow Director ATR if it's enabled.
3431 * NOTE: this must always be directly before the data descriptor.
3433 i40e_atr(tx_ring, skb, tx_flags);
3435 if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
3437 goto cleanup_tx_tstamp;
3439 return NETDEV_TX_OK;
3442 i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring);
3443 dev_kfree_skb_any(first->skb);
3446 if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) {
3447 struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev);
3449 dev_kfree_skb_any(pf->ptp_tx_skb);
3450 pf->ptp_tx_skb = NULL;
3451 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
3454 return NETDEV_TX_OK;
3458 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
3460 * @netdev: network interface device structure
3462 * Returns NETDEV_TX_OK if sent, else an error code
3464 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3466 struct i40e_netdev_priv *np = netdev_priv(netdev);
3467 struct i40e_vsi *vsi = np->vsi;
3468 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
3470 /* hardware can't handle really short frames, hardware padding works
3473 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
3474 return NETDEV_TX_OK;
3476 return i40e_xmit_frame_ring(skb, tx_ring);