1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #include "i40e_prototype.h"
30 * i40e_init_nvm_ops - Initialize NVM function pointers
31 * @hw: pointer to the HW structure
33 * Setup the function pointers and the NVM info structure. Should be called
34 * once per NVM initialization, e.g. inside the i40e_init_shared_code().
35 * Please notice that the NVM term is used here (& in all methods covered
36 * in this file) as an equivalent of the FLASH part mapped into the SR.
37 * We are accessing FLASH always thru the Shadow RAM.
39 i40e_status i40e_init_nvm(struct i40e_hw *hw)
41 struct i40e_nvm_info *nvm = &hw->nvm;
42 i40e_status ret_code = 0;
46 /* The SR size is stored regardless of the nvm programming mode
47 * as the blank mode may be used in the factory line.
49 gens = rd32(hw, I40E_GLNVM_GENS);
50 sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
51 I40E_GLNVM_GENS_SR_SIZE_SHIFT);
52 /* Switching to words (sr_size contains power of 2KB) */
53 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB;
55 /* Check if we are in the normal or blank NVM programming mode */
56 fla = rd32(hw, I40E_GLNVM_FLA);
57 if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
59 nvm->timeout = I40E_MAX_NVM_TIMEOUT;
60 nvm->blank_nvm_mode = false;
61 } else { /* Blank programming mode */
62 nvm->blank_nvm_mode = true;
63 ret_code = I40E_ERR_NVM_BLANK_MODE;
64 i40e_debug(hw, I40E_DEBUG_NVM, "NVM init error: unsupported blank mode.\n");
71 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
72 * @hw: pointer to the HW structure
73 * @access: NVM access type (read or write)
75 * This function will request NVM ownership for reading
76 * via the proper Admin Command.
78 i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
79 enum i40e_aq_resource_access_type access)
81 i40e_status ret_code = 0;
85 if (hw->nvm.blank_nvm_mode)
86 goto i40e_i40e_acquire_nvm_exit;
88 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
90 /* Reading the Global Device Timer */
91 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
93 /* Store the timeout */
94 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime;
97 i40e_debug(hw, I40E_DEBUG_NVM,
98 "NVM acquire type %d failed time_left=%llu ret=%d aq_err=%d\n",
99 access, time_left, ret_code, hw->aq.asq_last_status);
101 if (ret_code && time_left) {
102 /* Poll until the current NVM owner timeouts */
103 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT) + gtime;
104 while ((gtime < timeout) && time_left) {
105 usleep_range(10000, 20000);
106 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
107 ret_code = i40e_aq_request_resource(hw,
108 I40E_NVM_RESOURCE_ID,
109 access, 0, &time_left,
112 hw->nvm.hw_semaphore_timeout =
113 I40E_MS_TO_GTIME(time_left) + gtime;
118 hw->nvm.hw_semaphore_timeout = 0;
119 i40e_debug(hw, I40E_DEBUG_NVM,
120 "NVM acquire timed out, wait %llu ms before trying again. status=%d aq_err=%d\n",
121 time_left, ret_code, hw->aq.asq_last_status);
125 i40e_i40e_acquire_nvm_exit:
130 * i40e_release_nvm - Generic request for releasing the NVM ownership
131 * @hw: pointer to the HW structure
133 * This function will release NVM resource via the proper Admin Command.
135 void i40e_release_nvm(struct i40e_hw *hw)
137 if (!hw->nvm.blank_nvm_mode)
138 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
142 * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
143 * @hw: pointer to the HW structure
145 * Polls the SRCTL Shadow RAM register done bit.
147 static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
149 i40e_status ret_code = I40E_ERR_TIMEOUT;
152 /* Poll the I40E_GLNVM_SRCTL until the done bit is set */
153 for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
154 srctl = rd32(hw, I40E_GLNVM_SRCTL);
155 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
161 if (ret_code == I40E_ERR_TIMEOUT)
162 i40e_debug(hw, I40E_DEBUG_NVM, "Done bit in GLNVM_SRCTL not set");
167 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
168 * @hw: pointer to the HW structure
169 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
170 * @data: word read from the Shadow RAM
172 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
174 static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,
177 i40e_status ret_code = I40E_ERR_TIMEOUT;
180 if (offset >= hw->nvm.sr_size) {
181 i40e_debug(hw, I40E_DEBUG_NVM,
182 "NVM read error: offset %d beyond Shadow RAM limit %d\n",
183 offset, hw->nvm.sr_size);
184 ret_code = I40E_ERR_PARAM;
188 /* Poll the done bit first */
189 ret_code = i40e_poll_sr_srctl_done_bit(hw);
191 /* Write the address and start reading */
192 sr_reg = ((u32)offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
193 BIT(I40E_GLNVM_SRCTL_START_SHIFT);
194 wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
196 /* Poll I40E_GLNVM_SRCTL until the done bit is set */
197 ret_code = i40e_poll_sr_srctl_done_bit(hw);
199 sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
200 *data = (u16)((sr_reg &
201 I40E_GLNVM_SRDATA_RDDATA_MASK)
202 >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
206 i40e_debug(hw, I40E_DEBUG_NVM,
207 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
215 * i40e_read_nvm_aq - Read Shadow RAM.
216 * @hw: pointer to the HW structure.
217 * @module_pointer: module pointer location in words from the NVM beginning
218 * @offset: offset in words from module start
219 * @words: number of words to write
220 * @data: buffer with words to write to the Shadow RAM
221 * @last_command: tells the AdminQ that this is the last command
223 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
225 static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
226 u32 offset, u16 words, void *data,
229 i40e_status ret_code = I40E_ERR_NVM;
230 struct i40e_asq_cmd_details cmd_details;
232 memset(&cmd_details, 0, sizeof(cmd_details));
234 /* Here we are checking the SR limit only for the flat memory model.
235 * We cannot do it for the module-based model, as we did not acquire
236 * the NVM resource yet (we cannot get the module pointer value).
237 * Firmware will check the module-based model.
239 if ((offset + words) > hw->nvm.sr_size)
240 i40e_debug(hw, I40E_DEBUG_NVM,
241 "NVM write error: offset %d beyond Shadow RAM limit %d\n",
242 (offset + words), hw->nvm.sr_size);
243 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
244 /* We can write only up to 4KB (one sector), in one AQ write */
245 i40e_debug(hw, I40E_DEBUG_NVM,
246 "NVM write fail error: tried to write %d words, limit is %d.\n",
247 words, I40E_SR_SECTOR_SIZE_IN_WORDS);
248 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
249 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
250 /* A single write cannot spread over two sectors */
251 i40e_debug(hw, I40E_DEBUG_NVM,
252 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
255 ret_code = i40e_aq_read_nvm(hw, module_pointer,
256 2 * offset, /*bytes*/
258 data, last_command, &cmd_details);
264 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
265 * @hw: pointer to the HW structure
266 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
267 * @data: word read from the Shadow RAM
269 * Reads one 16 bit word from the Shadow RAM using the AdminQ
271 static i40e_status i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,
274 i40e_status ret_code = I40E_ERR_TIMEOUT;
276 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);
277 *data = le16_to_cpu(*(__le16 *)data);
283 * __i40e_read_nvm_word - Reads nvm word, assumes called does the locking
284 * @hw: pointer to the HW structure
285 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
286 * @data: word read from the Shadow RAM
288 * Reads one 16 bit word from the Shadow RAM.
290 * Do not use this function except in cases where the nvm lock is already
291 * taken via i40e_acquire_nvm().
293 static i40e_status __i40e_read_nvm_word(struct i40e_hw *hw,
294 u16 offset, u16 *data)
296 i40e_status ret_code = 0;
298 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
299 ret_code = i40e_read_nvm_word_aq(hw, offset, data);
301 ret_code = i40e_read_nvm_word_srctl(hw, offset, data);
306 * i40e_read_nvm_word - Reads nvm word and acquire lock if necessary
307 * @hw: pointer to the HW structure
308 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
309 * @data: word read from the Shadow RAM
311 * Reads one 16 bit word from the Shadow RAM.
313 i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
316 i40e_status ret_code = 0;
318 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
322 ret_code = __i40e_read_nvm_word(hw, offset, data);
324 i40e_release_nvm(hw);
330 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
331 * @hw: pointer to the HW structure
332 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
333 * @words: (in) number of words to read; (out) number of words actually read
334 * @data: words read from the Shadow RAM
336 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
337 * method. The buffer read is preceded by the NVM ownership take
338 * and followed by the release.
340 static i40e_status i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,
341 u16 *words, u16 *data)
343 i40e_status ret_code = 0;
346 /* Loop thru the selected region */
347 for (word = 0; word < *words; word++) {
348 index = offset + word;
349 ret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);
354 /* Update the number of words read from the Shadow RAM */
361 * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
362 * @hw: pointer to the HW structure
363 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
364 * @words: (in) number of words to read; (out) number of words actually read
365 * @data: words read from the Shadow RAM
367 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()
368 * method. The buffer read is preceded by the NVM ownership take
369 * and followed by the release.
371 static i40e_status i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,
372 u16 *words, u16 *data)
374 i40e_status ret_code;
375 u16 read_size = *words;
376 bool last_cmd = false;
381 /* Calculate number of bytes we should read in this step.
382 * FVL AQ do not allow to read more than one page at a time or
383 * to cross page boundaries.
385 if (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)
386 read_size = min(*words,
387 (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -
388 (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));
390 read_size = min((*words - words_read),
391 I40E_SR_SECTOR_SIZE_IN_WORDS);
393 /* Check if this is last command, if so set proper flag */
394 if ((words_read + read_size) >= *words)
397 ret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,
398 data + words_read, last_cmd);
400 goto read_nvm_buffer_aq_exit;
402 /* Increment counter for words already read and move offset to
405 words_read += read_size;
407 } while (words_read < *words);
409 for (i = 0; i < *words; i++)
410 data[i] = le16_to_cpu(((__le16 *)data)[i]);
412 read_nvm_buffer_aq_exit:
418 * __i40e_read_nvm_buffer - Reads nvm buffer, caller must acquire lock
419 * @hw: pointer to the HW structure
420 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
421 * @words: (in) number of words to read; (out) number of words actually read
422 * @data: words read from the Shadow RAM
424 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
427 static i40e_status __i40e_read_nvm_buffer(struct i40e_hw *hw,
428 u16 offset, u16 *words,
431 i40e_status ret_code = 0;
433 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE)
434 ret_code = i40e_read_nvm_buffer_aq(hw, offset, words, data);
436 ret_code = i40e_read_nvm_buffer_srctl(hw, offset, words, data);
441 * i40e_write_nvm_aq - Writes Shadow RAM.
442 * @hw: pointer to the HW structure.
443 * @module_pointer: module pointer location in words from the NVM beginning
444 * @offset: offset in words from module start
445 * @words: number of words to write
446 * @data: buffer with words to write to the Shadow RAM
447 * @last_command: tells the AdminQ that this is the last command
449 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
451 static i40e_status i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
452 u32 offset, u16 words, void *data,
455 i40e_status ret_code = I40E_ERR_NVM;
456 struct i40e_asq_cmd_details cmd_details;
458 memset(&cmd_details, 0, sizeof(cmd_details));
459 cmd_details.wb_desc = &hw->nvm_wb_desc;
461 /* Here we are checking the SR limit only for the flat memory model.
462 * We cannot do it for the module-based model, as we did not acquire
463 * the NVM resource yet (we cannot get the module pointer value).
464 * Firmware will check the module-based model.
466 if ((offset + words) > hw->nvm.sr_size)
467 i40e_debug(hw, I40E_DEBUG_NVM,
468 "NVM write error: offset %d beyond Shadow RAM limit %d\n",
469 (offset + words), hw->nvm.sr_size);
470 else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
471 /* We can write only up to 4KB (one sector), in one AQ write */
472 i40e_debug(hw, I40E_DEBUG_NVM,
473 "NVM write fail error: tried to write %d words, limit is %d.\n",
474 words, I40E_SR_SECTOR_SIZE_IN_WORDS);
475 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
476 != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
477 /* A single write cannot spread over two sectors */
478 i40e_debug(hw, I40E_DEBUG_NVM,
479 "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n",
482 ret_code = i40e_aq_update_nvm(hw, module_pointer,
483 2 * offset, /*bytes*/
485 data, last_command, &cmd_details);
491 * i40e_calc_nvm_checksum - Calculates and returns the checksum
492 * @hw: pointer to hardware structure
493 * @checksum: pointer to the checksum
495 * This function calculates SW Checksum that covers the whole 64kB shadow RAM
496 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
497 * is customer specific and unknown. Therefore, this function skips all maximum
498 * possible size of VPD (1kB).
500 static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw,
503 i40e_status ret_code;
504 struct i40e_virt_mem vmem;
505 u16 pcie_alt_module = 0;
506 u16 checksum_local = 0;
511 ret_code = i40e_allocate_virt_mem(hw, &vmem,
512 I40E_SR_SECTOR_SIZE_IN_WORDS * sizeof(u16));
514 goto i40e_calc_nvm_checksum_exit;
515 data = (u16 *)vmem.va;
517 /* read pointer to VPD area */
518 ret_code = __i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
520 ret_code = I40E_ERR_NVM_CHECKSUM;
521 goto i40e_calc_nvm_checksum_exit;
524 /* read pointer to PCIe Alt Auto-load module */
525 ret_code = __i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
528 ret_code = I40E_ERR_NVM_CHECKSUM;
529 goto i40e_calc_nvm_checksum_exit;
532 /* Calculate SW checksum that covers the whole 64kB shadow RAM
533 * except the VPD and PCIe ALT Auto-load modules
535 for (i = 0; i < hw->nvm.sr_size; i++) {
537 if ((i % I40E_SR_SECTOR_SIZE_IN_WORDS) == 0) {
538 u16 words = I40E_SR_SECTOR_SIZE_IN_WORDS;
540 ret_code = __i40e_read_nvm_buffer(hw, i, &words, data);
542 ret_code = I40E_ERR_NVM_CHECKSUM;
543 goto i40e_calc_nvm_checksum_exit;
547 /* Skip Checksum word */
548 if (i == I40E_SR_SW_CHECKSUM_WORD)
550 /* Skip VPD module (convert byte size to word count) */
551 if ((i >= (u32)vpd_module) &&
552 (i < ((u32)vpd_module +
553 (I40E_SR_VPD_MODULE_MAX_SIZE / 2)))) {
556 /* Skip PCIe ALT module (convert byte size to word count) */
557 if ((i >= (u32)pcie_alt_module) &&
558 (i < ((u32)pcie_alt_module +
559 (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2)))) {
563 checksum_local += data[i % I40E_SR_SECTOR_SIZE_IN_WORDS];
566 *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
568 i40e_calc_nvm_checksum_exit:
569 i40e_free_virt_mem(hw, &vmem);
574 * i40e_update_nvm_checksum - Updates the NVM checksum
575 * @hw: pointer to hardware structure
577 * NVM ownership must be acquired before calling this function and released
578 * on ARQ completion event reception by caller.
579 * This function will commit SR to NVM.
581 i40e_status i40e_update_nvm_checksum(struct i40e_hw *hw)
583 i40e_status ret_code;
587 ret_code = i40e_calc_nvm_checksum(hw, &checksum);
589 le_sum = cpu_to_le16(checksum);
590 ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
598 * i40e_validate_nvm_checksum - Validate EEPROM checksum
599 * @hw: pointer to hardware structure
600 * @checksum: calculated checksum
602 * Performs checksum calculation and validates the NVM SW checksum. If the
603 * caller does not need checksum, the value can be NULL.
605 i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
608 i40e_status ret_code = 0;
610 u16 checksum_local = 0;
612 /* We must acquire the NVM lock in order to correctly synchronize the
613 * NVM accesses across multiple PFs. Without doing so it is possible
614 * for one of the PFs to read invalid data potentially indicating that
615 * the checksum is invalid.
617 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
620 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
621 __i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
622 i40e_release_nvm(hw);
626 /* Verify read checksum from EEPROM is the same as
627 * calculated checksum
629 if (checksum_local != checksum_sr)
630 ret_code = I40E_ERR_NVM_CHECKSUM;
632 /* If the user cares, return the calculated checksum */
634 *checksum = checksum_local;
639 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
640 struct i40e_nvm_access *cmd,
641 u8 *bytes, int *perrno);
642 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
643 struct i40e_nvm_access *cmd,
644 u8 *bytes, int *perrno);
645 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
646 struct i40e_nvm_access *cmd,
647 u8 *bytes, int *errno);
648 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
649 struct i40e_nvm_access *cmd,
651 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
652 struct i40e_nvm_access *cmd,
654 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
655 struct i40e_nvm_access *cmd,
656 u8 *bytes, int *perrno);
657 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
658 struct i40e_nvm_access *cmd,
659 u8 *bytes, int *perrno);
660 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
661 struct i40e_nvm_access *cmd,
662 u8 *bytes, int *perrno);
663 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
664 struct i40e_nvm_access *cmd,
665 u8 *bytes, int *perrno);
666 static inline u8 i40e_nvmupd_get_module(u32 val)
668 return (u8)(val & I40E_NVM_MOD_PNT_MASK);
670 static inline u8 i40e_nvmupd_get_transaction(u32 val)
672 return (u8)((val & I40E_NVM_TRANS_MASK) >> I40E_NVM_TRANS_SHIFT);
675 static const char * const i40e_nvm_update_state_str[] = {
676 "I40E_NVMUPD_INVALID",
677 "I40E_NVMUPD_READ_CON",
678 "I40E_NVMUPD_READ_SNT",
679 "I40E_NVMUPD_READ_LCB",
680 "I40E_NVMUPD_READ_SA",
681 "I40E_NVMUPD_WRITE_ERA",
682 "I40E_NVMUPD_WRITE_CON",
683 "I40E_NVMUPD_WRITE_SNT",
684 "I40E_NVMUPD_WRITE_LCB",
685 "I40E_NVMUPD_WRITE_SA",
686 "I40E_NVMUPD_CSUM_CON",
687 "I40E_NVMUPD_CSUM_SA",
688 "I40E_NVMUPD_CSUM_LCB",
689 "I40E_NVMUPD_STATUS",
690 "I40E_NVMUPD_EXEC_AQ",
691 "I40E_NVMUPD_GET_AQ_RESULT",
695 * i40e_nvmupd_command - Process an NVM update command
696 * @hw: pointer to hardware structure
697 * @cmd: pointer to nvm update command
698 * @bytes: pointer to the data buffer
699 * @perrno: pointer to return error code
701 * Dispatches command depending on what update state is current
703 i40e_status i40e_nvmupd_command(struct i40e_hw *hw,
704 struct i40e_nvm_access *cmd,
705 u8 *bytes, int *perrno)
708 enum i40e_nvmupd_cmd upd_cmd;
713 /* early check for status command and debug msgs */
714 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
716 i40e_debug(hw, I40E_DEBUG_NVM, "%s state %d nvm_release_on_hold %d opc 0x%04x cmd 0x%08x config 0x%08x offset 0x%08x data_size 0x%08x\n",
717 i40e_nvm_update_state_str[upd_cmd],
719 hw->nvm_release_on_done, hw->nvm_wait_opcode,
720 cmd->command, cmd->config, cmd->offset, cmd->data_size);
722 if (upd_cmd == I40E_NVMUPD_INVALID) {
724 i40e_debug(hw, I40E_DEBUG_NVM,
725 "i40e_nvmupd_validate_command returns %d errno %d\n",
729 /* a status request returns immediately rather than
730 * going into the state machine
732 if (upd_cmd == I40E_NVMUPD_STATUS) {
733 if (!cmd->data_size) {
735 return I40E_ERR_BUF_TOO_SHORT;
738 bytes[0] = hw->nvmupd_state;
740 if (cmd->data_size >= 4) {
742 *((u16 *)&bytes[2]) = hw->nvm_wait_opcode;
748 switch (hw->nvmupd_state) {
749 case I40E_NVMUPD_STATE_INIT:
750 status = i40e_nvmupd_state_init(hw, cmd, bytes, perrno);
753 case I40E_NVMUPD_STATE_READING:
754 status = i40e_nvmupd_state_reading(hw, cmd, bytes, perrno);
757 case I40E_NVMUPD_STATE_WRITING:
758 status = i40e_nvmupd_state_writing(hw, cmd, bytes, perrno);
761 case I40E_NVMUPD_STATE_INIT_WAIT:
762 case I40E_NVMUPD_STATE_WRITE_WAIT:
763 /* if we need to stop waiting for an event, clear
764 * the wait info and return before doing anything else
766 if (cmd->offset == 0xffff) {
767 i40e_nvmupd_check_wait_event(hw, hw->nvm_wait_opcode);
771 status = I40E_ERR_NOT_READY;
776 /* invalid state, should never happen */
777 i40e_debug(hw, I40E_DEBUG_NVM,
778 "NVMUPD: no such state %d\n", hw->nvmupd_state);
779 status = I40E_NOT_SUPPORTED;
787 * i40e_nvmupd_state_init - Handle NVM update state Init
788 * @hw: pointer to hardware structure
789 * @cmd: pointer to nvm update command buffer
790 * @bytes: pointer to the data buffer
791 * @perrno: pointer to return error code
793 * Process legitimate commands of the Init state and conditionally set next
794 * state. Reject all other commands.
796 static i40e_status i40e_nvmupd_state_init(struct i40e_hw *hw,
797 struct i40e_nvm_access *cmd,
798 u8 *bytes, int *perrno)
800 i40e_status status = 0;
801 enum i40e_nvmupd_cmd upd_cmd;
803 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
806 case I40E_NVMUPD_READ_SA:
807 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
809 *perrno = i40e_aq_rc_to_posix(status,
810 hw->aq.asq_last_status);
812 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
813 i40e_release_nvm(hw);
817 case I40E_NVMUPD_READ_SNT:
818 status = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
820 *perrno = i40e_aq_rc_to_posix(status,
821 hw->aq.asq_last_status);
823 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
825 i40e_release_nvm(hw);
827 hw->nvmupd_state = I40E_NVMUPD_STATE_READING;
831 case I40E_NVMUPD_WRITE_ERA:
832 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
834 *perrno = i40e_aq_rc_to_posix(status,
835 hw->aq.asq_last_status);
837 status = i40e_nvmupd_nvm_erase(hw, cmd, perrno);
839 i40e_release_nvm(hw);
841 hw->nvm_release_on_done = true;
842 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_erase;
843 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
848 case I40E_NVMUPD_WRITE_SA:
849 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
851 *perrno = i40e_aq_rc_to_posix(status,
852 hw->aq.asq_last_status);
854 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
856 i40e_release_nvm(hw);
858 hw->nvm_release_on_done = true;
859 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
860 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
865 case I40E_NVMUPD_WRITE_SNT:
866 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
868 *perrno = i40e_aq_rc_to_posix(status,
869 hw->aq.asq_last_status);
871 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
873 i40e_release_nvm(hw);
875 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
876 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
881 case I40E_NVMUPD_CSUM_SA:
882 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
884 *perrno = i40e_aq_rc_to_posix(status,
885 hw->aq.asq_last_status);
887 status = i40e_update_nvm_checksum(hw);
889 *perrno = hw->aq.asq_last_status ?
890 i40e_aq_rc_to_posix(status,
891 hw->aq.asq_last_status) :
893 i40e_release_nvm(hw);
895 hw->nvm_release_on_done = true;
896 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
897 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
902 case I40E_NVMUPD_EXEC_AQ:
903 status = i40e_nvmupd_exec_aq(hw, cmd, bytes, perrno);
906 case I40E_NVMUPD_GET_AQ_RESULT:
907 status = i40e_nvmupd_get_aq_result(hw, cmd, bytes, perrno);
911 i40e_debug(hw, I40E_DEBUG_NVM,
912 "NVMUPD: bad cmd %s in init state\n",
913 i40e_nvm_update_state_str[upd_cmd]);
914 status = I40E_ERR_NVM;
922 * i40e_nvmupd_state_reading - Handle NVM update state Reading
923 * @hw: pointer to hardware structure
924 * @cmd: pointer to nvm update command buffer
925 * @bytes: pointer to the data buffer
926 * @perrno: pointer to return error code
928 * NVM ownership is already held. Process legitimate commands and set any
929 * change in state; reject all other commands.
931 static i40e_status i40e_nvmupd_state_reading(struct i40e_hw *hw,
932 struct i40e_nvm_access *cmd,
933 u8 *bytes, int *perrno)
935 i40e_status status = 0;
936 enum i40e_nvmupd_cmd upd_cmd;
938 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
941 case I40E_NVMUPD_READ_SA:
942 case I40E_NVMUPD_READ_CON:
943 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
946 case I40E_NVMUPD_READ_LCB:
947 status = i40e_nvmupd_nvm_read(hw, cmd, bytes, perrno);
948 i40e_release_nvm(hw);
949 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
953 i40e_debug(hw, I40E_DEBUG_NVM,
954 "NVMUPD: bad cmd %s in reading state.\n",
955 i40e_nvm_update_state_str[upd_cmd]);
956 status = I40E_NOT_SUPPORTED;
964 * i40e_nvmupd_state_writing - Handle NVM update state Writing
965 * @hw: pointer to hardware structure
966 * @cmd: pointer to nvm update command buffer
967 * @bytes: pointer to the data buffer
968 * @perrno: pointer to return error code
970 * NVM ownership is already held. Process legitimate commands and set any
971 * change in state; reject all other commands
973 static i40e_status i40e_nvmupd_state_writing(struct i40e_hw *hw,
974 struct i40e_nvm_access *cmd,
975 u8 *bytes, int *perrno)
977 i40e_status status = 0;
978 enum i40e_nvmupd_cmd upd_cmd;
979 bool retry_attempt = false;
981 upd_cmd = i40e_nvmupd_validate_command(hw, cmd, perrno);
985 case I40E_NVMUPD_WRITE_CON:
986 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
988 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
989 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
993 case I40E_NVMUPD_WRITE_LCB:
994 status = i40e_nvmupd_nvm_write(hw, cmd, bytes, perrno);
996 *perrno = hw->aq.asq_last_status ?
997 i40e_aq_rc_to_posix(status,
998 hw->aq.asq_last_status) :
1000 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1002 hw->nvm_release_on_done = true;
1003 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1004 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1008 case I40E_NVMUPD_CSUM_CON:
1009 /* Assumes the caller has acquired the nvm */
1010 status = i40e_update_nvm_checksum(hw);
1012 *perrno = hw->aq.asq_last_status ?
1013 i40e_aq_rc_to_posix(status,
1014 hw->aq.asq_last_status) :
1016 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1018 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1019 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT;
1023 case I40E_NVMUPD_CSUM_LCB:
1024 /* Assumes the caller has acquired the nvm */
1025 status = i40e_update_nvm_checksum(hw);
1027 *perrno = hw->aq.asq_last_status ?
1028 i40e_aq_rc_to_posix(status,
1029 hw->aq.asq_last_status) :
1031 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1033 hw->nvm_release_on_done = true;
1034 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update;
1035 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1040 i40e_debug(hw, I40E_DEBUG_NVM,
1041 "NVMUPD: bad cmd %s in writing state.\n",
1042 i40e_nvm_update_state_str[upd_cmd]);
1043 status = I40E_NOT_SUPPORTED;
1048 /* In some circumstances, a multi-write transaction takes longer
1049 * than the default 3 minute timeout on the write semaphore. If
1050 * the write failed with an EBUSY status, this is likely the problem,
1051 * so here we try to reacquire the semaphore then retry the write.
1052 * We only do one retry, then give up.
1054 if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) &&
1056 i40e_status old_status = status;
1057 u32 old_asq_status = hw->aq.asq_last_status;
1060 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
1061 if (gtime >= hw->nvm.hw_semaphore_timeout) {
1062 i40e_debug(hw, I40E_DEBUG_ALL,
1063 "NVMUPD: write semaphore expired (%d >= %lld), retrying\n",
1064 gtime, hw->nvm.hw_semaphore_timeout);
1065 i40e_release_nvm(hw);
1066 status = i40e_acquire_nvm(hw, I40E_RESOURCE_WRITE);
1068 i40e_debug(hw, I40E_DEBUG_ALL,
1069 "NVMUPD: write semaphore reacquire failed aq_err = %d\n",
1070 hw->aq.asq_last_status);
1071 status = old_status;
1072 hw->aq.asq_last_status = old_asq_status;
1074 retry_attempt = true;
1084 * i40e_nvmupd_check_wait_event - handle NVM update operation events
1085 * @hw: pointer to the hardware structure
1086 * @opcode: the event that just happened
1088 void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode)
1090 if (opcode == hw->nvm_wait_opcode) {
1091 i40e_debug(hw, I40E_DEBUG_NVM,
1092 "NVMUPD: clearing wait on opcode 0x%04x\n", opcode);
1093 if (hw->nvm_release_on_done) {
1094 i40e_release_nvm(hw);
1095 hw->nvm_release_on_done = false;
1097 hw->nvm_wait_opcode = 0;
1099 switch (hw->nvmupd_state) {
1100 case I40E_NVMUPD_STATE_INIT_WAIT:
1101 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT;
1104 case I40E_NVMUPD_STATE_WRITE_WAIT:
1105 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING;
1115 * i40e_nvmupd_validate_command - Validate given command
1116 * @hw: pointer to hardware structure
1117 * @cmd: pointer to nvm update command buffer
1118 * @perrno: pointer to return error code
1120 * Return one of the valid command types or I40E_NVMUPD_INVALID
1122 static enum i40e_nvmupd_cmd i40e_nvmupd_validate_command(struct i40e_hw *hw,
1123 struct i40e_nvm_access *cmd,
1126 enum i40e_nvmupd_cmd upd_cmd;
1127 u8 module, transaction;
1129 /* anything that doesn't match a recognized case is an error */
1130 upd_cmd = I40E_NVMUPD_INVALID;
1132 transaction = i40e_nvmupd_get_transaction(cmd->config);
1133 module = i40e_nvmupd_get_module(cmd->config);
1135 /* limits on data size */
1136 if ((cmd->data_size < 1) ||
1137 (cmd->data_size > I40E_NVMUPD_MAX_DATA)) {
1138 i40e_debug(hw, I40E_DEBUG_NVM,
1139 "i40e_nvmupd_validate_command data_size %d\n",
1142 return I40E_NVMUPD_INVALID;
1145 switch (cmd->command) {
1147 switch (transaction) {
1149 upd_cmd = I40E_NVMUPD_READ_CON;
1152 upd_cmd = I40E_NVMUPD_READ_SNT;
1155 upd_cmd = I40E_NVMUPD_READ_LCB;
1158 upd_cmd = I40E_NVMUPD_READ_SA;
1162 upd_cmd = I40E_NVMUPD_STATUS;
1163 else if (module == 0)
1164 upd_cmd = I40E_NVMUPD_GET_AQ_RESULT;
1169 case I40E_NVM_WRITE:
1170 switch (transaction) {
1172 upd_cmd = I40E_NVMUPD_WRITE_CON;
1175 upd_cmd = I40E_NVMUPD_WRITE_SNT;
1178 upd_cmd = I40E_NVMUPD_WRITE_LCB;
1181 upd_cmd = I40E_NVMUPD_WRITE_SA;
1184 upd_cmd = I40E_NVMUPD_WRITE_ERA;
1187 upd_cmd = I40E_NVMUPD_CSUM_CON;
1189 case (I40E_NVM_CSUM|I40E_NVM_SA):
1190 upd_cmd = I40E_NVMUPD_CSUM_SA;
1192 case (I40E_NVM_CSUM|I40E_NVM_LCB):
1193 upd_cmd = I40E_NVMUPD_CSUM_LCB;
1197 upd_cmd = I40E_NVMUPD_EXEC_AQ;
1207 * i40e_nvmupd_exec_aq - Run an AQ command
1208 * @hw: pointer to hardware structure
1209 * @cmd: pointer to nvm update command buffer
1210 * @bytes: pointer to the data buffer
1211 * @perrno: pointer to return error code
1213 * cmd structure contains identifiers and data buffer
1215 static i40e_status i40e_nvmupd_exec_aq(struct i40e_hw *hw,
1216 struct i40e_nvm_access *cmd,
1217 u8 *bytes, int *perrno)
1219 struct i40e_asq_cmd_details cmd_details;
1221 struct i40e_aq_desc *aq_desc;
1227 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1228 memset(&cmd_details, 0, sizeof(cmd_details));
1229 cmd_details.wb_desc = &hw->nvm_wb_desc;
1231 aq_desc_len = sizeof(struct i40e_aq_desc);
1232 memset(&hw->nvm_wb_desc, 0, aq_desc_len);
1234 /* get the aq descriptor */
1235 if (cmd->data_size < aq_desc_len) {
1236 i40e_debug(hw, I40E_DEBUG_NVM,
1237 "NVMUPD: not enough aq desc bytes for exec, size %d < %d\n",
1238 cmd->data_size, aq_desc_len);
1240 return I40E_ERR_PARAM;
1242 aq_desc = (struct i40e_aq_desc *)bytes;
1244 /* if data buffer needed, make sure it's ready */
1245 aq_data_len = cmd->data_size - aq_desc_len;
1246 buff_size = max_t(u32, aq_data_len, le16_to_cpu(aq_desc->datalen));
1248 if (!hw->nvm_buff.va) {
1249 status = i40e_allocate_virt_mem(hw, &hw->nvm_buff,
1250 hw->aq.asq_buf_size);
1252 i40e_debug(hw, I40E_DEBUG_NVM,
1253 "NVMUPD: i40e_allocate_virt_mem for exec buff failed, %d\n",
1257 if (hw->nvm_buff.va) {
1258 buff = hw->nvm_buff.va;
1259 memcpy(buff, &bytes[aq_desc_len], aq_data_len);
1263 /* and away we go! */
1264 status = i40e_asq_send_command(hw, aq_desc, buff,
1265 buff_size, &cmd_details);
1267 i40e_debug(hw, I40E_DEBUG_NVM,
1268 "i40e_nvmupd_exec_aq err %s aq_err %s\n",
1269 i40e_stat_str(hw, status),
1270 i40e_aq_str(hw, hw->aq.asq_last_status));
1271 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1274 /* should we wait for a followup event? */
1276 hw->nvm_wait_opcode = cmd->offset;
1277 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT;
1284 * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq
1285 * @hw: pointer to hardware structure
1286 * @cmd: pointer to nvm update command buffer
1287 * @bytes: pointer to the data buffer
1288 * @perrno: pointer to return error code
1290 * cmd structure contains identifiers and data buffer
1292 static i40e_status i40e_nvmupd_get_aq_result(struct i40e_hw *hw,
1293 struct i40e_nvm_access *cmd,
1294 u8 *bytes, int *perrno)
1301 i40e_debug(hw, I40E_DEBUG_NVM, "NVMUPD: %s\n", __func__);
1303 aq_desc_len = sizeof(struct i40e_aq_desc);
1304 aq_total_len = aq_desc_len + le16_to_cpu(hw->nvm_wb_desc.datalen);
1306 /* check offset range */
1307 if (cmd->offset > aq_total_len) {
1308 i40e_debug(hw, I40E_DEBUG_NVM, "%s: offset too big %d > %d\n",
1309 __func__, cmd->offset, aq_total_len);
1311 return I40E_ERR_PARAM;
1314 /* check copylength range */
1315 if (cmd->data_size > (aq_total_len - cmd->offset)) {
1316 int new_len = aq_total_len - cmd->offset;
1318 i40e_debug(hw, I40E_DEBUG_NVM, "%s: copy length %d too big, trimming to %d\n",
1319 __func__, cmd->data_size, new_len);
1320 cmd->data_size = new_len;
1323 remainder = cmd->data_size;
1324 if (cmd->offset < aq_desc_len) {
1325 u32 len = aq_desc_len - cmd->offset;
1327 len = min(len, cmd->data_size);
1328 i40e_debug(hw, I40E_DEBUG_NVM, "%s: aq_desc bytes %d to %d\n",
1329 __func__, cmd->offset, cmd->offset + len);
1331 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset;
1332 memcpy(bytes, buff, len);
1336 buff = hw->nvm_buff.va;
1338 buff = hw->nvm_buff.va + (cmd->offset - aq_desc_len);
1341 if (remainder > 0) {
1342 int start_byte = buff - (u8 *)hw->nvm_buff.va;
1344 i40e_debug(hw, I40E_DEBUG_NVM, "%s: databuf bytes %d to %d\n",
1345 __func__, start_byte, start_byte + remainder);
1346 memcpy(bytes, buff, remainder);
1353 * i40e_nvmupd_nvm_read - Read NVM
1354 * @hw: pointer to hardware structure
1355 * @cmd: pointer to nvm update command buffer
1356 * @bytes: pointer to the data buffer
1357 * @perrno: pointer to return error code
1359 * cmd structure contains identifiers and data buffer
1361 static i40e_status i40e_nvmupd_nvm_read(struct i40e_hw *hw,
1362 struct i40e_nvm_access *cmd,
1363 u8 *bytes, int *perrno)
1365 struct i40e_asq_cmd_details cmd_details;
1367 u8 module, transaction;
1370 transaction = i40e_nvmupd_get_transaction(cmd->config);
1371 module = i40e_nvmupd_get_module(cmd->config);
1372 last = (transaction == I40E_NVM_LCB) || (transaction == I40E_NVM_SA);
1374 memset(&cmd_details, 0, sizeof(cmd_details));
1375 cmd_details.wb_desc = &hw->nvm_wb_desc;
1377 status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1378 bytes, last, &cmd_details);
1380 i40e_debug(hw, I40E_DEBUG_NVM,
1381 "i40e_nvmupd_nvm_read mod 0x%x off 0x%x len 0x%x\n",
1382 module, cmd->offset, cmd->data_size);
1383 i40e_debug(hw, I40E_DEBUG_NVM,
1384 "i40e_nvmupd_nvm_read status %d aq %d\n",
1385 status, hw->aq.asq_last_status);
1386 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1393 * i40e_nvmupd_nvm_erase - Erase an NVM module
1394 * @hw: pointer to hardware structure
1395 * @cmd: pointer to nvm update command buffer
1396 * @perrno: pointer to return error code
1398 * module, offset, data_size and data are in cmd structure
1400 static i40e_status i40e_nvmupd_nvm_erase(struct i40e_hw *hw,
1401 struct i40e_nvm_access *cmd,
1404 i40e_status status = 0;
1405 struct i40e_asq_cmd_details cmd_details;
1406 u8 module, transaction;
1409 transaction = i40e_nvmupd_get_transaction(cmd->config);
1410 module = i40e_nvmupd_get_module(cmd->config);
1411 last = (transaction & I40E_NVM_LCB);
1413 memset(&cmd_details, 0, sizeof(cmd_details));
1414 cmd_details.wb_desc = &hw->nvm_wb_desc;
1416 status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size,
1417 last, &cmd_details);
1419 i40e_debug(hw, I40E_DEBUG_NVM,
1420 "i40e_nvmupd_nvm_erase mod 0x%x off 0x%x len 0x%x\n",
1421 module, cmd->offset, cmd->data_size);
1422 i40e_debug(hw, I40E_DEBUG_NVM,
1423 "i40e_nvmupd_nvm_erase status %d aq %d\n",
1424 status, hw->aq.asq_last_status);
1425 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);
1432 * i40e_nvmupd_nvm_write - Write NVM
1433 * @hw: pointer to hardware structure
1434 * @cmd: pointer to nvm update command buffer
1435 * @bytes: pointer to the data buffer
1436 * @perrno: pointer to return error code
1438 * module, offset, data_size and data are in cmd structure
1440 static i40e_status i40e_nvmupd_nvm_write(struct i40e_hw *hw,
1441 struct i40e_nvm_access *cmd,
1442 u8 *bytes, int *perrno)
1444 i40e_status status = 0;
1445 struct i40e_asq_cmd_details cmd_details;
1446 u8 module, transaction;
1449 transaction = i40e_nvmupd_get_transaction(cmd->config);
1450 module = i40e_nvmupd_get_module(cmd->config);
1451 last = (transaction & I40E_NVM_LCB);
1453 memset(&cmd_details, 0, sizeof(cmd_details));
1454 cmd_details.wb_desc = &hw->nvm_wb_desc;
1456 status = i40e_aq_update_nvm(hw, module, cmd->offset,
1457 (u16)cmd->data_size, bytes, last,
1460 i40e_debug(hw, I40E_DEBUG_NVM,
1461 "i40e_nvmupd_nvm_write mod 0x%x off 0x%x len 0x%x\n",
1462 module, cmd->offset, cmd->data_size);
1463 i40e_debug(hw, I40E_DEBUG_NVM,
1464 "i40e_nvmupd_nvm_write status %d aq %d\n",
1465 status, hw->aq.asq_last_status);
1466 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status);