1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
9 #define I40E_DCBX_STATUS_NOT_STARTED 0
10 #define I40E_DCBX_STATUS_IN_PROGRESS 1
11 #define I40E_DCBX_STATUS_DONE 2
12 #define I40E_DCBX_STATUS_MULTIPLE_PEERS 3
13 #define I40E_DCBX_STATUS_DISABLED 7
15 #define I40E_TLV_TYPE_END 0
16 #define I40E_TLV_TYPE_ORG 127
18 #define I40E_IEEE_8021QAZ_OUI 0x0080C2
19 #define I40E_IEEE_SUBTYPE_ETS_CFG 9
20 #define I40E_IEEE_SUBTYPE_ETS_REC 10
21 #define I40E_IEEE_SUBTYPE_PFC_CFG 11
22 #define I40E_IEEE_SUBTYPE_APP_PRI 12
24 #define I40E_CEE_DCBX_OUI 0x001b21
25 #define I40E_CEE_DCBX_TYPE 2
27 #define I40E_CEE_SUBTYPE_CTRL 1
28 #define I40E_CEE_SUBTYPE_PG_CFG 2
29 #define I40E_CEE_SUBTYPE_PFC_CFG 3
30 #define I40E_CEE_SUBTYPE_APP_PRI 4
32 #define I40E_CEE_MAX_FEAT_TYPE 3
33 /* Defines for LLDP TLV header */
34 #define I40E_LLDP_TLV_LEN_SHIFT 0
35 #define I40E_LLDP_TLV_LEN_MASK (0x01FF << I40E_LLDP_TLV_LEN_SHIFT)
36 #define I40E_LLDP_TLV_TYPE_SHIFT 9
37 #define I40E_LLDP_TLV_TYPE_MASK (0x7F << I40E_LLDP_TLV_TYPE_SHIFT)
38 #define I40E_LLDP_TLV_SUBTYPE_SHIFT 0
39 #define I40E_LLDP_TLV_SUBTYPE_MASK (0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT)
40 #define I40E_LLDP_TLV_OUI_SHIFT 8
41 #define I40E_LLDP_TLV_OUI_MASK (0xFFFFFF << I40E_LLDP_TLV_OUI_SHIFT)
43 /* Defines for IEEE ETS TLV */
44 #define I40E_IEEE_ETS_MAXTC_SHIFT 0
45 #define I40E_IEEE_ETS_MAXTC_MASK (0x7 << I40E_IEEE_ETS_MAXTC_SHIFT)
46 #define I40E_IEEE_ETS_CBS_SHIFT 6
47 #define I40E_IEEE_ETS_CBS_MASK BIT(I40E_IEEE_ETS_CBS_SHIFT)
48 #define I40E_IEEE_ETS_WILLING_SHIFT 7
49 #define I40E_IEEE_ETS_WILLING_MASK BIT(I40E_IEEE_ETS_WILLING_SHIFT)
50 #define I40E_IEEE_ETS_PRIO_0_SHIFT 0
51 #define I40E_IEEE_ETS_PRIO_0_MASK (0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT)
52 #define I40E_IEEE_ETS_PRIO_1_SHIFT 4
53 #define I40E_IEEE_ETS_PRIO_1_MASK (0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT)
54 #define I40E_CEE_PGID_PRIO_0_SHIFT 0
55 #define I40E_CEE_PGID_PRIO_0_MASK (0xF << I40E_CEE_PGID_PRIO_0_SHIFT)
56 #define I40E_CEE_PGID_PRIO_1_SHIFT 4
57 #define I40E_CEE_PGID_PRIO_1_MASK (0xF << I40E_CEE_PGID_PRIO_1_SHIFT)
58 #define I40E_CEE_PGID_STRICT 15
60 /* Defines for IEEE TSA types */
61 #define I40E_IEEE_TSA_STRICT 0
62 #define I40E_IEEE_TSA_ETS 2
64 /* Defines for IEEE PFC TLV */
65 #define I40E_IEEE_PFC_CAP_SHIFT 0
66 #define I40E_IEEE_PFC_CAP_MASK (0xF << I40E_IEEE_PFC_CAP_SHIFT)
67 #define I40E_IEEE_PFC_MBC_SHIFT 6
68 #define I40E_IEEE_PFC_MBC_MASK BIT(I40E_IEEE_PFC_MBC_SHIFT)
69 #define I40E_IEEE_PFC_WILLING_SHIFT 7
70 #define I40E_IEEE_PFC_WILLING_MASK BIT(I40E_IEEE_PFC_WILLING_SHIFT)
72 /* Defines for IEEE APP TLV */
73 #define I40E_IEEE_APP_SEL_SHIFT 0
74 #define I40E_IEEE_APP_SEL_MASK (0x7 << I40E_IEEE_APP_SEL_SHIFT)
75 #define I40E_IEEE_APP_PRIO_SHIFT 5
76 #define I40E_IEEE_APP_PRIO_MASK (0x7 << I40E_IEEE_APP_PRIO_SHIFT)
81 /* IEEE 802.1AB LLDP Organization specific TLV */
82 struct i40e_lldp_org_tlv {
88 struct i40e_cee_tlv_hdr {
94 struct i40e_cee_ctrl_tlv {
95 struct i40e_cee_tlv_hdr hdr;
100 struct i40e_cee_feat_tlv {
101 struct i40e_cee_tlv_hdr hdr;
102 u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */
103 #define I40E_CEE_FEAT_TLV_ENABLE_MASK 0x80
104 #define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40
105 #define I40E_CEE_FEAT_TLV_ERR_MASK 0x20
110 struct i40e_cee_app_prio {
112 u8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */
113 #define I40E_CEE_APP_SELECTOR_MASK 0x03
119 i40e_status i40e_get_dcbx_status(struct i40e_hw *hw,
121 i40e_status i40e_lldp_to_dcb_config(u8 *lldpmib,
122 struct i40e_dcbx_config *dcbcfg);
123 i40e_status i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
125 struct i40e_dcbx_config *dcbcfg);
126 i40e_status i40e_get_dcb_config(struct i40e_hw *hw);
127 i40e_status i40e_init_dcb(struct i40e_hw *hw);
128 #endif /* _I40E_DCB_H_ */