drivers/net/ethernet/intel/i40e/i40e_common.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
   3
   4 #include "i40e_type.h"
   5 #include "i40e_adminq.h"
   6 #include "i40e_prototype.h"
   7 #include <linux/avf/virtchnl.h>
   8
   9 /**
  10  * i40e_set_mac_type - Sets MAC type
  11  * @hw: pointer to the HW structure
  12  *
  13  * This function sets the mac type of the adapter based on the
  14  * vendor ID and device ID stored in the hw structure.
  15  **/
  16 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
  17 {
  18         i40e_status status = 0;
  19
  20         if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
  21                 switch (hw->device_id) {
  22                 case I40E_DEV_ID_SFP_XL710:
  23                 case I40E_DEV_ID_QEMU:
  24                 case I40E_DEV_ID_KX_B:
  25                 case I40E_DEV_ID_KX_C:
  26                 case I40E_DEV_ID_QSFP_A:
  27                 case I40E_DEV_ID_QSFP_B:
  28                 case I40E_DEV_ID_QSFP_C:
  29                 case I40E_DEV_ID_10G_BASE_T:
  30                 case I40E_DEV_ID_10G_BASE_T4:
  31                 case I40E_DEV_ID_20G_KR2:
  32                 case I40E_DEV_ID_20G_KR2_A:
  33                 case I40E_DEV_ID_25G_B:
  34                 case I40E_DEV_ID_25G_SFP28:
  35                         hw->mac.type = I40E_MAC_XL710;
  36                         break;
  37                 case I40E_DEV_ID_KX_X722:
  38                 case I40E_DEV_ID_QSFP_X722:
  39                 case I40E_DEV_ID_SFP_X722:
  40                 case I40E_DEV_ID_1G_BASE_T_X722:
  41                 case I40E_DEV_ID_10G_BASE_T_X722:
  42                 case I40E_DEV_ID_SFP_I_X722:
  43                         hw->mac.type = I40E_MAC_X722;
  44                         break;
  45                 default:
  46                         hw->mac.type = I40E_MAC_GENERIC;
  47                         break;
  48                 }
  49         } else {
  50                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  51         }
  52
  53         hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
  54                   hw->mac.type, status);
  55         return status;
  56 }
  57
  58 /**
  59  * i40e_aq_str - convert AQ err code to a string
  60  * @hw: pointer to the HW structure
  61  * @aq_err: the AQ error code to convert
  62  **/
  63 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  64 {
  65         switch (aq_err) {
  66         case I40E_AQ_RC_OK:
  67                 return "OK";
  68         case I40E_AQ_RC_EPERM:
  69                 return "I40E_AQ_RC_EPERM";
  70         case I40E_AQ_RC_ENOENT:
  71                 return "I40E_AQ_RC_ENOENT";
  72         case I40E_AQ_RC_ESRCH:
  73                 return "I40E_AQ_RC_ESRCH";
  74         case I40E_AQ_RC_EINTR:
  75                 return "I40E_AQ_RC_EINTR";
  76         case I40E_AQ_RC_EIO:
  77                 return "I40E_AQ_RC_EIO";
  78         case I40E_AQ_RC_ENXIO:
  79                 return "I40E_AQ_RC_ENXIO";
  80         case I40E_AQ_RC_E2BIG:
  81                 return "I40E_AQ_RC_E2BIG";
  82         case I40E_AQ_RC_EAGAIN:
  83                 return "I40E_AQ_RC_EAGAIN";
  84         case I40E_AQ_RC_ENOMEM:
  85                 return "I40E_AQ_RC_ENOMEM";
  86         case I40E_AQ_RC_EACCES:
  87                 return "I40E_AQ_RC_EACCES";
  88         case I40E_AQ_RC_EFAULT:
  89                 return "I40E_AQ_RC_EFAULT";
  90         case I40E_AQ_RC_EBUSY:
  91                 return "I40E_AQ_RC_EBUSY";
  92         case I40E_AQ_RC_EEXIST:
  93                 return "I40E_AQ_RC_EEXIST";
  94         case I40E_AQ_RC_EINVAL:
  95                 return "I40E_AQ_RC_EINVAL";
  96         case I40E_AQ_RC_ENOTTY:
  97                 return "I40E_AQ_RC_ENOTTY";
  98         case I40E_AQ_RC_ENOSPC:
  99                 return "I40E_AQ_RC_ENOSPC";
 100         case I40E_AQ_RC_ENOSYS:
 101                 return "I40E_AQ_RC_ENOSYS";
 102         case I40E_AQ_RC_ERANGE:
 103                 return "I40E_AQ_RC_ERANGE";
 104         case I40E_AQ_RC_EFLUSHED:
 105                 return "I40E_AQ_RC_EFLUSHED";
 106         case I40E_AQ_RC_BAD_ADDR:
 107                 return "I40E_AQ_RC_BAD_ADDR";
 108         case I40E_AQ_RC_EMODE:
 109                 return "I40E_AQ_RC_EMODE";
 110         case I40E_AQ_RC_EFBIG:
 111                 return "I40E_AQ_RC_EFBIG";
 112         }
 113
 114         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 115         return hw->err_str;
 116 }
 117
 118 /**
 119  * i40e_stat_str - convert status err code to a string
 120  * @hw: pointer to the HW structure
 121  * @stat_err: the status error code to convert
 122  **/
 123 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
 124 {
 125         switch (stat_err) {
 126         case 0:
 127                 return "OK";
 128         case I40E_ERR_NVM:
 129                 return "I40E_ERR_NVM";
 130         case I40E_ERR_NVM_CHECKSUM:
 131                 return "I40E_ERR_NVM_CHECKSUM";
 132         case I40E_ERR_PHY:
 133                 return "I40E_ERR_PHY";
 134         case I40E_ERR_CONFIG:
 135                 return "I40E_ERR_CONFIG";
 136         case I40E_ERR_PARAM:
 137                 return "I40E_ERR_PARAM";
 138         case I40E_ERR_MAC_TYPE:
 139                 return "I40E_ERR_MAC_TYPE";
 140         case I40E_ERR_UNKNOWN_PHY:
 141                 return "I40E_ERR_UNKNOWN_PHY";
 142         case I40E_ERR_LINK_SETUP:
 143                 return "I40E_ERR_LINK_SETUP";
 144         case I40E_ERR_ADAPTER_STOPPED:
 145                 return "I40E_ERR_ADAPTER_STOPPED";
 146         case I40E_ERR_INVALID_MAC_ADDR:
 147                 return "I40E_ERR_INVALID_MAC_ADDR";
 148         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 149                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 150         case I40E_ERR_MASTER_REQUESTS_PENDING:
 151                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 152         case I40E_ERR_INVALID_LINK_SETTINGS:
 153                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 154         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 155                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 156         case I40E_ERR_RESET_FAILED:
 157                 return "I40E_ERR_RESET_FAILED";
 158         case I40E_ERR_SWFW_SYNC:
 159                 return "I40E_ERR_SWFW_SYNC";
 160         case I40E_ERR_NO_AVAILABLE_VSI:
 161                 return "I40E_ERR_NO_AVAILABLE_VSI";
 162         case I40E_ERR_NO_MEMORY:
 163                 return "I40E_ERR_NO_MEMORY";
 164         case I40E_ERR_BAD_PTR:
 165                 return "I40E_ERR_BAD_PTR";
 166         case I40E_ERR_RING_FULL:
 167                 return "I40E_ERR_RING_FULL";
 168         case I40E_ERR_INVALID_PD_ID:
 169                 return "I40E_ERR_INVALID_PD_ID";
 170         case I40E_ERR_INVALID_QP_ID:
 171                 return "I40E_ERR_INVALID_QP_ID";
 172         case I40E_ERR_INVALID_CQ_ID:
 173                 return "I40E_ERR_INVALID_CQ_ID";
 174         case I40E_ERR_INVALID_CEQ_ID:
 175                 return "I40E_ERR_INVALID_CEQ_ID";
 176         case I40E_ERR_INVALID_AEQ_ID:
 177                 return "I40E_ERR_INVALID_AEQ_ID";
 178         case I40E_ERR_INVALID_SIZE:
 179                 return "I40E_ERR_INVALID_SIZE";
 180         case I40E_ERR_INVALID_ARP_INDEX:
 181                 return "I40E_ERR_INVALID_ARP_INDEX";
 182         case I40E_ERR_INVALID_FPM_FUNC_ID:
 183                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 184         case I40E_ERR_QP_INVALID_MSG_SIZE:
 185                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 186         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 187                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 188         case I40E_ERR_INVALID_FRAG_COUNT:
 189                 return "I40E_ERR_INVALID_FRAG_COUNT";
 190         case I40E_ERR_QUEUE_EMPTY:
 191                 return "I40E_ERR_QUEUE_EMPTY";
 192         case I40E_ERR_INVALID_ALIGNMENT:
 193                 return "I40E_ERR_INVALID_ALIGNMENT";
 194         case I40E_ERR_FLUSHED_QUEUE:
 195                 return "I40E_ERR_FLUSHED_QUEUE";
 196         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 197                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 198         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 199                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 200         case I40E_ERR_TIMEOUT:
 201                 return "I40E_ERR_TIMEOUT";
 202         case I40E_ERR_OPCODE_MISMATCH:
 203                 return "I40E_ERR_OPCODE_MISMATCH";
 204         case I40E_ERR_CQP_COMPL_ERROR:
 205                 return "I40E_ERR_CQP_COMPL_ERROR";
 206         case I40E_ERR_INVALID_VF_ID:
 207                 return "I40E_ERR_INVALID_VF_ID";
 208         case I40E_ERR_INVALID_HMCFN_ID:
 209                 return "I40E_ERR_INVALID_HMCFN_ID";
 210         case I40E_ERR_BACKING_PAGE_ERROR:
 211                 return "I40E_ERR_BACKING_PAGE_ERROR";
 212         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 213                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 214         case I40E_ERR_INVALID_PBLE_INDEX:
 215                 return "I40E_ERR_INVALID_PBLE_INDEX";
 216         case I40E_ERR_INVALID_SD_INDEX:
 217                 return "I40E_ERR_INVALID_SD_INDEX";
 218         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 219                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 220         case I40E_ERR_INVALID_SD_TYPE:
 221                 return "I40E_ERR_INVALID_SD_TYPE";
 222         case I40E_ERR_MEMCPY_FAILED:
 223                 return "I40E_ERR_MEMCPY_FAILED";
 224         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 225                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 226         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 227                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 228         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 229                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 230         case I40E_ERR_SRQ_ENABLED:
 231                 return "I40E_ERR_SRQ_ENABLED";
 232         case I40E_ERR_ADMIN_QUEUE_ERROR:
 233                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 234         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 235                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 236         case I40E_ERR_BUF_TOO_SHORT:
 237                 return "I40E_ERR_BUF_TOO_SHORT";
 238         case I40E_ERR_ADMIN_QUEUE_FULL:
 239                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 240         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 241                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 242         case I40E_ERR_BAD_IWARP_CQE:
 243                 return "I40E_ERR_BAD_IWARP_CQE";
 244         case I40E_ERR_NVM_BLANK_MODE:
 245                 return "I40E_ERR_NVM_BLANK_MODE";
 246         case I40E_ERR_NOT_IMPLEMENTED:
 247                 return "I40E_ERR_NOT_IMPLEMENTED";
 248         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 249                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 250         case I40E_ERR_DIAG_TEST_FAILED:
 251                 return "I40E_ERR_DIAG_TEST_FAILED";
 252         case I40E_ERR_NOT_READY:
 253                 return "I40E_ERR_NOT_READY";
 254         case I40E_NOT_SUPPORTED:
 255                 return "I40E_NOT_SUPPORTED";
 256         case I40E_ERR_FIRMWARE_API_VERSION:
 257                 return "I40E_ERR_FIRMWARE_API_VERSION";
 258         case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
 259                 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
 260         }
 261
 262         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 263         return hw->err_str;
 264 }
 265
 266 /**
 267  * i40e_debug_aq
 268  * @hw: debug mask related to admin queue
 269  * @mask: debug mask
 270  * @desc: pointer to admin queue descriptor
 271  * @buffer: pointer to command buffer
 272  * @buf_len: max length of buffer
 273  *
 274  * Dumps debug log about adminq command with descriptor contents.
 275  **/
 276 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 277                    void *buffer, u16 buf_len)
 278 {
 279         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 280         u16 len;
 281         u8 *buf = (u8 *)buffer;
 282
 283         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 284                 return;
 285
 286         len = le16_to_cpu(aq_desc->datalen);
 287
 288         i40e_debug(hw, mask,
 289                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 290                    le16_to_cpu(aq_desc->opcode),
 291                    le16_to_cpu(aq_desc->flags),
 292                    le16_to_cpu(aq_desc->datalen),
 293                    le16_to_cpu(aq_desc->retval));
 294         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 295                    le32_to_cpu(aq_desc->cookie_high),
 296                    le32_to_cpu(aq_desc->cookie_low));
 297         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 298                    le32_to_cpu(aq_desc->params.internal.param0),
 299                    le32_to_cpu(aq_desc->params.internal.param1));
 300         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 301                    le32_to_cpu(aq_desc->params.external.addr_high),
 302                    le32_to_cpu(aq_desc->params.external.addr_low));
 303
 304         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 305                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 306                 if (buf_len < len)
 307                         len = buf_len;
 308                 /* write the full 16-byte chunks */
 309                 if (hw->debug_mask & mask) {
 310                         char prefix[27];
 311
 312                         snprintf(prefix, sizeof(prefix),
 313                                  "i40e %02x:%02x.%x: \t0x",
 314                                  hw->bus.bus_id,
 315                                  hw->bus.device,
 316                                  hw->bus.func);
 317
 318                         print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
 319                                        16, 1, buf, len, false);
 320                 }
 321         }
 322 }
 323
 324 /**
 325  * i40e_check_asq_alive
 326  * @hw: pointer to the hw struct
 327  *
 328  * Returns true if Queue is enabled else false.
 329  **/
 330 bool i40e_check_asq_alive(struct i40e_hw *hw)
 331 {
 332         if (hw->aq.asq.len)
 333                 return !!(rd32(hw, hw->aq.asq.len) &
 334                           I40E_PF_ATQLEN_ATQENABLE_MASK);
 335         else
 336                 return false;
 337 }
 338
 339 /**
 340  * i40e_aq_queue_shutdown
 341  * @hw: pointer to the hw struct
 342  * @unloading: is the driver unloading itself
 343  *
 344  * Tell the Firmware that we're shutting down the AdminQ and whether
 345  * or not the driver is unloading as well.
 346  **/
 347 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
 348                                              bool unloading)
 349 {
 350         struct i40e_aq_desc desc;
 351         struct i40e_aqc_queue_shutdown *cmd =
 352                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 353         i40e_status status;
 354
 355         i40e_fill_default_direct_cmd_desc(&desc,
 356                                           i40e_aqc_opc_queue_shutdown);
 357
 358         if (unloading)
 359                 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
 360         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 361
 362         return status;
 363 }
 364
 365 /**
 366  * i40e_aq_get_set_rss_lut
 367  * @hw: pointer to the hardware structure
 368  * @vsi_id: vsi fw index
 369  * @pf_lut: for PF table set true, for VSI table set false
 370  * @lut: pointer to the lut buffer provided by the caller
 371  * @lut_size: size of the lut buffer
 372  * @set: set true to set the table, false to get the table
 373  *
 374  * Internal function to get or set RSS look up table
 375  **/
 376 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 377                                            u16 vsi_id, bool pf_lut,
 378                                            u8 *lut, u16 lut_size,
 379                                            bool set)
 380 {
 381         i40e_status status;
 382         struct i40e_aq_desc desc;
 383         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 384                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 385
 386         if (set)
 387                 i40e_fill_default_direct_cmd_desc(&desc,
 388                                                   i40e_aqc_opc_set_rss_lut);
 389         else
 390                 i40e_fill_default_direct_cmd_desc(&desc,
 391                                                   i40e_aqc_opc_get_rss_lut);
 392
 393         /* Indirect command */
 394         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
 395         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
 396
 397         cmd_resp->vsi_id =
 398                         cpu_to_le16((u16)((vsi_id <<
 399                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 400                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 401         cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 402
 403         if (pf_lut)
 404                 cmd_resp->flags |= cpu_to_le16((u16)
 405                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 406                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 407                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 408         else
 409                 cmd_resp->flags |= cpu_to_le16((u16)
 410                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 411                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 412                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 413
 414         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 415
 416         return status;
 417 }
 418
 419 /**
 420  * i40e_aq_get_rss_lut
 421  * @hw: pointer to the hardware structure
 422  * @vsi_id: vsi fw index
 423  * @pf_lut: for PF table set true, for VSI table set false
 424  * @lut: pointer to the lut buffer provided by the caller
 425  * @lut_size: size of the lut buffer
 426  *
 427  * get the RSS lookup table, PF or VSI type
 428  **/
 429 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 430                                 bool pf_lut, u8 *lut, u16 lut_size)
 431 {
 432         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 433                                        false);
 434 }
 435
 436 /**
 437  * i40e_aq_set_rss_lut
 438  * @hw: pointer to the hardware structure
 439  * @vsi_id: vsi fw index
 440  * @pf_lut: for PF table set true, for VSI table set false
 441  * @lut: pointer to the lut buffer provided by the caller
 442  * @lut_size: size of the lut buffer
 443  *
 444  * set the RSS lookup table, PF or VSI type
 445  **/
 446 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 447                                 bool pf_lut, u8 *lut, u16 lut_size)
 448 {
 449         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 450 }
 451
 452 /**
 453  * i40e_aq_get_set_rss_key
 454  * @hw: pointer to the hw struct
 455  * @vsi_id: vsi fw index
 456  * @key: pointer to key info struct
 457  * @set: set true to set the key, false to get the key
 458  *
 459  * get the RSS key per VSI
 460  **/
 461 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 462                                       u16 vsi_id,
 463                                       struct i40e_aqc_get_set_rss_key_data *key,
 464                                       bool set)
 465 {
 466         i40e_status status;
 467         struct i40e_aq_desc desc;
 468         struct i40e_aqc_get_set_rss_key *cmd_resp =
 469                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 470         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 471
 472         if (set)
 473                 i40e_fill_default_direct_cmd_desc(&desc,
 474                                                   i40e_aqc_opc_set_rss_key);
 475         else
 476                 i40e_fill_default_direct_cmd_desc(&desc,
 477                                                   i40e_aqc_opc_get_rss_key);
 478
 479         /* Indirect command */
 480         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
 481         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
 482
 483         cmd_resp->vsi_id =
 484                         cpu_to_le16((u16)((vsi_id <<
 485                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 486                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 487         cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 488
 489         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 490
 491         return status;
 492 }
 493
 494 /**
 495  * i40e_aq_get_rss_key
 496  * @hw: pointer to the hw struct
 497  * @vsi_id: vsi fw index
 498  * @key: pointer to key info struct
 499  *
 500  **/
 501 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
 502                                 u16 vsi_id,
 503                                 struct i40e_aqc_get_set_rss_key_data *key)
 504 {
 505         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 506 }
 507
 508 /**
 509  * i40e_aq_set_rss_key
 510  * @hw: pointer to the hw struct
 511  * @vsi_id: vsi fw index
 512  * @key: pointer to key info struct
 513  *
 514  * set the RSS key per VSI
 515  **/
 516 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
 517                                 u16 vsi_id,
 518                                 struct i40e_aqc_get_set_rss_key_data *key)
 519 {
 520         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 521 }
 522
 523 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 524  * hardware to a bit-field that can be used by SW to more easily determine the
 525  * packet type.
 526  *
 527  * Macros are used to shorten the table lines and make this table human
 528  * readable.
 529  *
 530  * We store the PTYPE in the top byte of the bit field - this is just so that
 531  * we can check that the table doesn't have a row missing, as the index into
 532  * the table should be the PTYPE.
 533  *
 534  * Typical work flow:
 535  *
 536  * IF NOT i40e_ptype_lookup[ptype].known
 537  * THEN
 538  *      Packet is unknown
 539  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 540  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 541  * ELSE
 542  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 543  * ENDIF
 544  */
 545
 546 /* macro to make the table lines short */
 547 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 548         {       PTYPE, \
 549                 1, \
 550                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 551                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 552                 I40E_RX_PTYPE_##OUTER_FRAG, \
 553                 I40E_RX_PTYPE_TUNNEL_##T, \
 554                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 555                 I40E_RX_PTYPE_##TEF, \
 556                 I40E_RX_PTYPE_INNER_PROT_##I, \
 557                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 558
 559 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 560                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 561
 562 /* shorter macros makes the table fit but are terse */
 563 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 564 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 565 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 566
 567 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 568 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 569         /* L2 Packet types */
 570         I40E_PTT_UNUSED_ENTRY(0),
 571         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 572         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 573         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 574         I40E_PTT_UNUSED_ENTRY(4),
 575         I40E_PTT_UNUSED_ENTRY(5),
 576         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 577         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 578         I40E_PTT_UNUSED_ENTRY(8),
 579         I40E_PTT_UNUSED_ENTRY(9),
 580         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 581         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 582         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 583         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 584         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 585         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 586         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 587         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 588         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 589         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 590         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 591         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 592
 593         /* Non Tunneled IPv4 */
 594         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 595         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 596         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 597         I40E_PTT_UNUSED_ENTRY(25),
 598         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 599         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 600         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 601
 602         /* IPv4 --> IPv4 */
 603         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 604         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 605         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 606         I40E_PTT_UNUSED_ENTRY(32),
 607         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 608         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 609         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 610
 611         /* IPv4 --> IPv6 */
 612         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 613         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 614         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 615         I40E_PTT_UNUSED_ENTRY(39),
 616         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 617         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 618         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 619
 620         /* IPv4 --> GRE/NAT */
 621         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 622
 623         /* IPv4 --> GRE/NAT --> IPv4 */
 624         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 625         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 626         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 627         I40E_PTT_UNUSED_ENTRY(47),
 628         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 629         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 630         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 631
 632         /* IPv4 --> GRE/NAT --> IPv6 */
 633         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 634         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 635         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 636         I40E_PTT_UNUSED_ENTRY(54),
 637         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 638         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 639         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 640
 641         /* IPv4 --> GRE/NAT --> MAC */
 642         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 643
 644         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 645         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 646         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 647         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 648         I40E_PTT_UNUSED_ENTRY(62),
 649         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 650         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 651         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 652
 653         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 654         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 655         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 656         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 657         I40E_PTT_UNUSED_ENTRY(69),
 658         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 659         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 660         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 661
 662         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 663         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 664
 665         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 666         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 667         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 668         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 669         I40E_PTT_UNUSED_ENTRY(77),
 670         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 671         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 672         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 673
 674         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 675         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 676         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 677         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 678         I40E_PTT_UNUSED_ENTRY(84),
 679         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 680         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 681         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 682
 683         /* Non Tunneled IPv6 */
 684         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 685         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 686         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 687         I40E_PTT_UNUSED_ENTRY(91),
 688         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 689         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 690         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 691
 692         /* IPv6 --> IPv4 */
 693         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 694         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 695         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 696         I40E_PTT_UNUSED_ENTRY(98),
 697         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 698         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 699         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 700
 701         /* IPv6 --> IPv6 */
 702         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 703         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 704         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 705         I40E_PTT_UNUSED_ENTRY(105),
 706         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 707         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 708         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 709
 710         /* IPv6 --> GRE/NAT */
 711         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 712
 713         /* IPv6 --> GRE/NAT -> IPv4 */
 714         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 715         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 716         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 717         I40E_PTT_UNUSED_ENTRY(113),
 718         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 719         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 720         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 721
 722         /* IPv6 --> GRE/NAT -> IPv6 */
 723         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 724         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 725         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 726         I40E_PTT_UNUSED_ENTRY(120),
 727         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 728         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 729         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 730
 731         /* IPv6 --> GRE/NAT -> MAC */
 732         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 733
 734         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 735         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 736         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 737         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 738         I40E_PTT_UNUSED_ENTRY(128),
 739         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 740         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 741         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 742
 743         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 744         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 745         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 746         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 747         I40E_PTT_UNUSED_ENTRY(135),
 748         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 749         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 750         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 751
 752         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 753         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 754
 755         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 756         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 757         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 758         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 759         I40E_PTT_UNUSED_ENTRY(143),
 760         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 761         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 762         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 763
 764         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 765         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 766         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 767         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 768         I40E_PTT_UNUSED_ENTRY(150),
 769         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 770         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 771         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 772
 773         /* unused entries */
 774         I40E_PTT_UNUSED_ENTRY(154),
 775         I40E_PTT_UNUSED_ENTRY(155),
 776         I40E_PTT_UNUSED_ENTRY(156),
 777         I40E_PTT_UNUSED_ENTRY(157),
 778         I40E_PTT_UNUSED_ENTRY(158),
 779         I40E_PTT_UNUSED_ENTRY(159),
 780
 781         I40E_PTT_UNUSED_ENTRY(160),
 782         I40E_PTT_UNUSED_ENTRY(161),
 783         I40E_PTT_UNUSED_ENTRY(162),
 784         I40E_PTT_UNUSED_ENTRY(163),
 785         I40E_PTT_UNUSED_ENTRY(164),
 786         I40E_PTT_UNUSED_ENTRY(165),
 787         I40E_PTT_UNUSED_ENTRY(166),
 788         I40E_PTT_UNUSED_ENTRY(167),
 789         I40E_PTT_UNUSED_ENTRY(168),
 790         I40E_PTT_UNUSED_ENTRY(169),
 791
 792         I40E_PTT_UNUSED_ENTRY(170),
 793         I40E_PTT_UNUSED_ENTRY(171),
 794         I40E_PTT_UNUSED_ENTRY(172),
 795         I40E_PTT_UNUSED_ENTRY(173),
 796         I40E_PTT_UNUSED_ENTRY(174),
 797         I40E_PTT_UNUSED_ENTRY(175),
 798         I40E_PTT_UNUSED_ENTRY(176),
 799         I40E_PTT_UNUSED_ENTRY(177),
 800         I40E_PTT_UNUSED_ENTRY(178),
 801         I40E_PTT_UNUSED_ENTRY(179),
 802
 803         I40E_PTT_UNUSED_ENTRY(180),
 804         I40E_PTT_UNUSED_ENTRY(181),
 805         I40E_PTT_UNUSED_ENTRY(182),
 806         I40E_PTT_UNUSED_ENTRY(183),
 807         I40E_PTT_UNUSED_ENTRY(184),
 808         I40E_PTT_UNUSED_ENTRY(185),
 809         I40E_PTT_UNUSED_ENTRY(186),
 810         I40E_PTT_UNUSED_ENTRY(187),
 811         I40E_PTT_UNUSED_ENTRY(188),
 812         I40E_PTT_UNUSED_ENTRY(189),
 813
 814         I40E_PTT_UNUSED_ENTRY(190),
 815         I40E_PTT_UNUSED_ENTRY(191),
 816         I40E_PTT_UNUSED_ENTRY(192),
 817         I40E_PTT_UNUSED_ENTRY(193),
 818         I40E_PTT_UNUSED_ENTRY(194),
 819         I40E_PTT_UNUSED_ENTRY(195),
 820         I40E_PTT_UNUSED_ENTRY(196),
 821         I40E_PTT_UNUSED_ENTRY(197),
 822         I40E_PTT_UNUSED_ENTRY(198),
 823         I40E_PTT_UNUSED_ENTRY(199),
 824
 825         I40E_PTT_UNUSED_ENTRY(200),
 826         I40E_PTT_UNUSED_ENTRY(201),
 827         I40E_PTT_UNUSED_ENTRY(202),
 828         I40E_PTT_UNUSED_ENTRY(203),
 829         I40E_PTT_UNUSED_ENTRY(204),
 830         I40E_PTT_UNUSED_ENTRY(205),
 831         I40E_PTT_UNUSED_ENTRY(206),
 832         I40E_PTT_UNUSED_ENTRY(207),
 833         I40E_PTT_UNUSED_ENTRY(208),
 834         I40E_PTT_UNUSED_ENTRY(209),
 835
 836         I40E_PTT_UNUSED_ENTRY(210),
 837         I40E_PTT_UNUSED_ENTRY(211),
 838         I40E_PTT_UNUSED_ENTRY(212),
 839         I40E_PTT_UNUSED_ENTRY(213),
 840         I40E_PTT_UNUSED_ENTRY(214),
 841         I40E_PTT_UNUSED_ENTRY(215),
 842         I40E_PTT_UNUSED_ENTRY(216),
 843         I40E_PTT_UNUSED_ENTRY(217),
 844         I40E_PTT_UNUSED_ENTRY(218),
 845         I40E_PTT_UNUSED_ENTRY(219),
 846
 847         I40E_PTT_UNUSED_ENTRY(220),
 848         I40E_PTT_UNUSED_ENTRY(221),
 849         I40E_PTT_UNUSED_ENTRY(222),
 850         I40E_PTT_UNUSED_ENTRY(223),
 851         I40E_PTT_UNUSED_ENTRY(224),
 852         I40E_PTT_UNUSED_ENTRY(225),
 853         I40E_PTT_UNUSED_ENTRY(226),
 854         I40E_PTT_UNUSED_ENTRY(227),
 855         I40E_PTT_UNUSED_ENTRY(228),
 856         I40E_PTT_UNUSED_ENTRY(229),
 857
 858         I40E_PTT_UNUSED_ENTRY(230),
 859         I40E_PTT_UNUSED_ENTRY(231),
 860         I40E_PTT_UNUSED_ENTRY(232),
 861         I40E_PTT_UNUSED_ENTRY(233),
 862         I40E_PTT_UNUSED_ENTRY(234),
 863         I40E_PTT_UNUSED_ENTRY(235),
 864         I40E_PTT_UNUSED_ENTRY(236),
 865         I40E_PTT_UNUSED_ENTRY(237),
 866         I40E_PTT_UNUSED_ENTRY(238),
 867         I40E_PTT_UNUSED_ENTRY(239),
 868
 869         I40E_PTT_UNUSED_ENTRY(240),
 870         I40E_PTT_UNUSED_ENTRY(241),
 871         I40E_PTT_UNUSED_ENTRY(242),
 872         I40E_PTT_UNUSED_ENTRY(243),
 873         I40E_PTT_UNUSED_ENTRY(244),
 874         I40E_PTT_UNUSED_ENTRY(245),
 875         I40E_PTT_UNUSED_ENTRY(246),
 876         I40E_PTT_UNUSED_ENTRY(247),
 877         I40E_PTT_UNUSED_ENTRY(248),
 878         I40E_PTT_UNUSED_ENTRY(249),
 879
 880         I40E_PTT_UNUSED_ENTRY(250),
 881         I40E_PTT_UNUSED_ENTRY(251),
 882         I40E_PTT_UNUSED_ENTRY(252),
 883         I40E_PTT_UNUSED_ENTRY(253),
 884         I40E_PTT_UNUSED_ENTRY(254),
 885         I40E_PTT_UNUSED_ENTRY(255)
 886 };
 887
 888 /**
 889  * i40e_init_shared_code - Initialize the shared code
 890  * @hw: pointer to hardware structure
 891  *
 892  * This assigns the MAC type and PHY code and inits the NVM.
 893  * Does not touch the hardware. This function must be called prior to any
 894  * other function in the shared code. The i40e_hw structure should be
 895  * memset to 0 prior to calling this function.  The following fields in
 896  * hw structure should be filled in prior to calling this function:
 897  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 898  * subsystem_vendor_id, and revision_id
 899  **/
 900 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
 901 {
 902         i40e_status status = 0;
 903         u32 port, ari, func_rid;
 904
 905         i40e_set_mac_type(hw);
 906
 907         switch (hw->mac.type) {
 908         case I40E_MAC_XL710:
 909         case I40E_MAC_X722:
 910                 break;
 911         default:
 912                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 913         }
 914
 915         hw->phy.get_link_info = true;
 916
 917         /* Determine port number and PF number*/
 918         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
 919                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
 920         hw->port = (u8)port;
 921         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
 922                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
 923         func_rid = rd32(hw, I40E_PF_FUNC_RID);
 924         if (ari)
 925                 hw->pf_id = (u8)(func_rid & 0xff);
 926         else
 927                 hw->pf_id = (u8)(func_rid & 0x7);
 928
 929         if (hw->mac.type == I40E_MAC_X722)
 930                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
 931                              I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
 932
 933         status = i40e_init_nvm(hw);
 934         return status;
 935 }
 936
 937 /**
 938  * i40e_aq_mac_address_read - Retrieve the MAC addresses
 939  * @hw: pointer to the hw struct
 940  * @flags: a return indicator of what addresses were added to the addr store
 941  * @addrs: the requestor's mac addr store
 942  * @cmd_details: pointer to command details structure or NULL
 943  **/
 944 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
 945                                    u16 *flags,
 946                                    struct i40e_aqc_mac_address_read_data *addrs,
 947                                    struct i40e_asq_cmd_details *cmd_details)
 948 {
 949         struct i40e_aq_desc desc;
 950         struct i40e_aqc_mac_address_read *cmd_data =
 951                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
 952         i40e_status status;
 953
 954         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
 955         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
 956
 957         status = i40e_asq_send_command(hw, &desc, addrs,
 958                                        sizeof(*addrs), cmd_details);
 959         *flags = le16_to_cpu(cmd_data->command_flags);
 960
 961         return status;
 962 }
 963
 964 /**
 965  * i40e_aq_mac_address_write - Change the MAC addresses
 966  * @hw: pointer to the hw struct
 967  * @flags: indicates which MAC to be written
 968  * @mac_addr: address to write
 969  * @cmd_details: pointer to command details structure or NULL
 970  **/
 971 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
 972                                     u16 flags, u8 *mac_addr,
 973                                     struct i40e_asq_cmd_details *cmd_details)
 974 {
 975         struct i40e_aq_desc desc;
 976         struct i40e_aqc_mac_address_write *cmd_data =
 977                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
 978         i40e_status status;
 979
 980         i40e_fill_default_direct_cmd_desc(&desc,
 981                                           i40e_aqc_opc_mac_address_write);
 982         cmd_data->command_flags = cpu_to_le16(flags);
 983         cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
 984         cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
 985                                         ((u32)mac_addr[3] << 16) |
 986                                         ((u32)mac_addr[4] << 8) |
 987                                         mac_addr[5]);
 988
 989         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
 990
 991         return status;
 992 }
 993
 994 /**
 995  * i40e_get_mac_addr - get MAC address
 996  * @hw: pointer to the HW structure
 997  * @mac_addr: pointer to MAC address
 998  *
 999  * Reads the adapter's MAC address from register
1000  **/
1001 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1002 {
1003         struct i40e_aqc_mac_address_read_data addrs;
1004         i40e_status status;
1005         u16 flags = 0;
1006
1007         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1008
1009         if (flags & I40E_AQC_LAN_ADDR_VALID)
1010                 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1011
1012         return status;
1013 }
1014
1015 /**
1016  * i40e_get_port_mac_addr - get Port MAC address
1017  * @hw: pointer to the HW structure
1018  * @mac_addr: pointer to Port MAC address
1019  *
1020  * Reads the adapter's Port MAC address
1021  **/
1022 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1023 {
1024         struct i40e_aqc_mac_address_read_data addrs;
1025         i40e_status status;
1026         u16 flags = 0;
1027
1028         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1029         if (status)
1030                 return status;
1031
1032         if (flags & I40E_AQC_PORT_ADDR_VALID)
1033                 ether_addr_copy(mac_addr, addrs.port_mac);
1034         else
1035                 status = I40E_ERR_INVALID_MAC_ADDR;
1036
1037         return status;
1038 }
1039
1040 /**
1041  * i40e_pre_tx_queue_cfg - pre tx queue configure
1042  * @hw: pointer to the HW structure
1043  * @queue: target PF queue index
1044  * @enable: state change request
1045  *
1046  * Handles hw requirement to indicate intention to enable
1047  * or disable target queue.
1048  **/
1049 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1050 {
1051         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1052         u32 reg_block = 0;
1053         u32 reg_val;
1054
1055         if (abs_queue_idx >= 128) {
1056                 reg_block = abs_queue_idx / 128;
1057                 abs_queue_idx %= 128;
1058         }
1059
1060         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1061         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1062         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1063
1064         if (enable)
1065                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1066         else
1067                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1068
1069         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1070 }
1071
1072 /**
1073  *  i40e_read_pba_string - Reads part number string from EEPROM
1074  *  @hw: pointer to hardware structure
1075  *  @pba_num: stores the part number string from the EEPROM
1076  *  @pba_num_size: part number string buffer length
1077  *
1078  *  Reads the part number string from the EEPROM.
1079  **/
1080 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1081                                  u32 pba_num_size)
1082 {
1083         i40e_status status = 0;
1084         u16 pba_word = 0;
1085         u16 pba_size = 0;
1086         u16 pba_ptr = 0;
1087         u16 i = 0;
1088
1089         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1090         if (status || (pba_word != 0xFAFA)) {
1091                 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1092                 return status;
1093         }
1094
1095         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1096         if (status) {
1097                 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1098                 return status;
1099         }
1100
1101         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1102         if (status) {
1103                 hw_dbg(hw, "Failed to read PBA Block size.\n");
1104                 return status;
1105         }
1106
1107         /* Subtract one to get PBA word count (PBA Size word is included in
1108          * total size)
1109          */
1110         pba_size--;
1111         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1112                 hw_dbg(hw, "Buffer to small for PBA data.\n");
1113                 return I40E_ERR_PARAM;
1114         }
1115
1116         for (i = 0; i < pba_size; i++) {
1117                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1118                 if (status) {
1119                         hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1120                         return status;
1121                 }
1122
1123                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1124                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1125         }
1126         pba_num[(pba_size * 2)] = '\0';
1127
1128         return status;
1129 }
1130
1131 /**
1132  * i40e_get_media_type - Gets media type
1133  * @hw: pointer to the hardware structure
1134  **/
1135 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1136 {
1137         enum i40e_media_type media;
1138
1139         switch (hw->phy.link_info.phy_type) {
1140         case I40E_PHY_TYPE_10GBASE_SR:
1141         case I40E_PHY_TYPE_10GBASE_LR:
1142         case I40E_PHY_TYPE_1000BASE_SX:
1143         case I40E_PHY_TYPE_1000BASE_LX:
1144         case I40E_PHY_TYPE_40GBASE_SR4:
1145         case I40E_PHY_TYPE_40GBASE_LR4:
1146         case I40E_PHY_TYPE_25GBASE_LR:
1147         case I40E_PHY_TYPE_25GBASE_SR:
1148                 media = I40E_MEDIA_TYPE_FIBER;
1149                 break;
1150         case I40E_PHY_TYPE_100BASE_TX:
1151         case I40E_PHY_TYPE_1000BASE_T:
1152         case I40E_PHY_TYPE_10GBASE_T:
1153                 media = I40E_MEDIA_TYPE_BASET;
1154                 break;
1155         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1156         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1157         case I40E_PHY_TYPE_10GBASE_CR1:
1158         case I40E_PHY_TYPE_40GBASE_CR4:
1159         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1160         case I40E_PHY_TYPE_40GBASE_AOC:
1161         case I40E_PHY_TYPE_10GBASE_AOC:
1162         case I40E_PHY_TYPE_25GBASE_CR:
1163         case I40E_PHY_TYPE_25GBASE_AOC:
1164         case I40E_PHY_TYPE_25GBASE_ACC:
1165                 media = I40E_MEDIA_TYPE_DA;
1166                 break;
1167         case I40E_PHY_TYPE_1000BASE_KX:
1168         case I40E_PHY_TYPE_10GBASE_KX4:
1169         case I40E_PHY_TYPE_10GBASE_KR:
1170         case I40E_PHY_TYPE_40GBASE_KR4:
1171         case I40E_PHY_TYPE_20GBASE_KR2:
1172         case I40E_PHY_TYPE_25GBASE_KR:
1173                 media = I40E_MEDIA_TYPE_BACKPLANE;
1174                 break;
1175         case I40E_PHY_TYPE_SGMII:
1176         case I40E_PHY_TYPE_XAUI:
1177         case I40E_PHY_TYPE_XFI:
1178         case I40E_PHY_TYPE_XLAUI:
1179         case I40E_PHY_TYPE_XLPPI:
1180         default:
1181                 media = I40E_MEDIA_TYPE_UNKNOWN;
1182                 break;
1183         }
1184
1185         return media;
1186 }
1187
1188 /**
1189  * i40e_poll_globr - Poll for Global Reset completion
1190  * @hw: pointer to the hardware structure
1191  * @retry_limit: how many times to retry before failure
1192  **/
1193 static i40e_status i40e_poll_globr(struct i40e_hw *hw,
1194                                    u32 retry_limit)
1195 {
1196         u32 cnt, reg = 0;
1197
1198         for (cnt = 0; cnt < retry_limit; cnt++) {
1199                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1200                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1201                         return 0;
1202                 msleep(100);
1203         }
1204
1205         hw_dbg(hw, "Global reset failed.\n");
1206         hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
1207
1208         return I40E_ERR_RESET_FAILED;
1209 }
1210
1211 #define I40E_PF_RESET_WAIT_COUNT_A0     200
1212 #define I40E_PF_RESET_WAIT_COUNT        200
1213 /**
1214  * i40e_pf_reset - Reset the PF
1215  * @hw: pointer to the hardware structure
1216  *
1217  * Assuming someone else has triggered a global reset,
1218  * assure the global reset is complete and then reset the PF
1219  **/
1220 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1221 {
1222         u32 cnt = 0;
1223         u32 cnt1 = 0;
1224         u32 reg = 0;
1225         u32 grst_del;
1226
1227         /* Poll for Global Reset steady state in case of recent GRST.
1228          * The grst delay value is in 100ms units, and we'll wait a
1229          * couple counts longer to be sure we don't just miss the end.
1230          */
1231         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1232                     I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1233                     I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1234
1235         /* It can take upto 15 secs for GRST steady state.
1236          * Bump it to 16 secs max to be safe.
1237          */
1238         grst_del = grst_del * 20;
1239
1240         for (cnt = 0; cnt < grst_del; cnt++) {
1241                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1242                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1243                         break;
1244                 msleep(100);
1245         }
1246         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1247                 hw_dbg(hw, "Global reset polling failed to complete.\n");
1248                 return I40E_ERR_RESET_FAILED;
1249         }
1250
1251         /* Now Wait for the FW to be ready */
1252         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1253                 reg = rd32(hw, I40E_GLNVM_ULD);
1254                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1255                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1256                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1257                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1258                         hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1259                         break;
1260                 }
1261                 usleep_range(10000, 20000);
1262         }
1263         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1264                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1265                 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1266                 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1267                 return I40E_ERR_RESET_FAILED;
1268         }
1269
1270         /* If there was a Global Reset in progress when we got here,
1271          * we don't need to do the PF Reset
1272          */
1273         if (!cnt) {
1274                 u32 reg2 = 0;
1275                 if (hw->revision_id == 0)
1276                         cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1277                 else
1278                         cnt = I40E_PF_RESET_WAIT_COUNT;
1279                 reg = rd32(hw, I40E_PFGEN_CTRL);
1280                 wr32(hw, I40E_PFGEN_CTRL,
1281                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1282                 for (; cnt; cnt--) {
1283                         reg = rd32(hw, I40E_PFGEN_CTRL);
1284                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1285                                 break;
1286                         reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1287                         if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1288                                 break;
1289                         usleep_range(1000, 2000);
1290                 }
1291                 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1292                         if (i40e_poll_globr(hw, grst_del))
1293                                 return I40E_ERR_RESET_FAILED;
1294                 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1295                         hw_dbg(hw, "PF reset polling failed to complete.\n");
1296                         return I40E_ERR_RESET_FAILED;
1297                 }
1298         }
1299
1300         i40e_clear_pxe_mode(hw);
1301
1302         return 0;
1303 }
1304
1305 /**
1306  * i40e_clear_hw - clear out any left over hw state
1307  * @hw: pointer to the hw struct
1308  *
1309  * Clear queues and interrupts, typically called at init time,
1310  * but after the capabilities have been found so we know how many
1311  * queues and msix vectors have been allocated.
1312  **/
1313 void i40e_clear_hw(struct i40e_hw *hw)
1314 {
1315         u32 num_queues, base_queue;
1316         u32 num_pf_int;
1317         u32 num_vf_int;
1318         u32 num_vfs;
1319         u32 i, j;
1320         u32 val;
1321         u32 eol = 0x7ff;
1322
1323         /* get number of interrupts, queues, and VFs */
1324         val = rd32(hw, I40E_GLPCI_CNF2);
1325         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1326                      I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1327         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1328                      I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1329
1330         val = rd32(hw, I40E_PFLAN_QALLOC);
1331         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1332                      I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1333         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1334             I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1335         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1336                 num_queues = (j - base_queue) + 1;
1337         else
1338                 num_queues = 0;
1339
1340         val = rd32(hw, I40E_PF_VT_PFALLOC);
1341         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1342             I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1343         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1344             I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1345         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1346                 num_vfs = (j - i) + 1;
1347         else
1348                 num_vfs = 0;
1349
1350         /* stop all the interrupts */
1351         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1352         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1353         for (i = 0; i < num_pf_int - 2; i++)
1354                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1355
1356         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1357         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1358         wr32(hw, I40E_PFINT_LNKLST0, val);
1359         for (i = 0; i < num_pf_int - 2; i++)
1360                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1361         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1362         for (i = 0; i < num_vfs; i++)
1363                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1364         for (i = 0; i < num_vf_int - 2; i++)
1365                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1366
1367         /* warn the HW of the coming Tx disables */
1368         for (i = 0; i < num_queues; i++) {
1369                 u32 abs_queue_idx = base_queue + i;
1370                 u32 reg_block = 0;
1371
1372                 if (abs_queue_idx >= 128) {
1373                         reg_block = abs_queue_idx / 128;
1374                         abs_queue_idx %= 128;
1375                 }
1376
1377                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1378                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1379                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1380                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1381
1382                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1383         }
1384         udelay(400);
1385
1386         /* stop all the queues */
1387         for (i = 0; i < num_queues; i++) {
1388                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1389                 wr32(hw, I40E_QTX_ENA(i), 0);
1390                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1391                 wr32(hw, I40E_QRX_ENA(i), 0);
1392         }
1393
1394         /* short wait for all queue disables to settle */
1395         udelay(50);
1396 }
1397
1398 /**
1399  * i40e_clear_pxe_mode - clear pxe operations mode
1400  * @hw: pointer to the hw struct
1401  *
1402  * Make sure all PXE mode settings are cleared, including things
1403  * like descriptor fetch/write-back mode.
1404  **/
1405 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1406 {
1407         u32 reg;
1408
1409         if (i40e_check_asq_alive(hw))
1410                 i40e_aq_clear_pxe_mode(hw, NULL);
1411
1412         /* Clear single descriptor fetch/write-back mode */
1413         reg = rd32(hw, I40E_GLLAN_RCTL_0);
1414
1415         if (hw->revision_id == 0) {
1416                 /* As a work around clear PXE_MODE instead of setting it */
1417                 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1418         } else {
1419                 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1420         }
1421 }
1422
1423 /**
1424  * i40e_led_is_mine - helper to find matching led
1425  * @hw: pointer to the hw struct
1426  * @idx: index into GPIO registers
1427  *
1428  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1429  */
1430 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1431 {
1432         u32 gpio_val = 0;
1433         u32 port;
1434
1435         if (!hw->func_caps.led[idx])
1436                 return 0;
1437
1438         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1439         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1440                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1441
1442         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1443          * if it is not our port then ignore
1444          */
1445         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1446             (port != hw->port))
1447                 return 0;
1448
1449         return gpio_val;
1450 }
1451
1452 #define I40E_COMBINED_ACTIVITY 0xA
1453 #define I40E_FILTER_ACTIVITY 0xE
1454 #define I40E_LINK_ACTIVITY 0xC
1455 #define I40E_MAC_ACTIVITY 0xD
1456 #define I40E_LED0 22
1457
1458 /**
1459  * i40e_led_get - return current on/off mode
1460  * @hw: pointer to the hw struct
1461  *
1462  * The value returned is the 'mode' field as defined in the
1463  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1464  * values are variations of possible behaviors relating to
1465  * blink, link, and wire.
1466  **/
1467 u32 i40e_led_get(struct i40e_hw *hw)
1468 {
1469         u32 current_mode = 0;
1470         u32 mode = 0;
1471         int i;
1472
1473         /* as per the documentation GPIO 22-29 are the LED
1474          * GPIO pins named LED0..LED7
1475          */
1476         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1477                 u32 gpio_val = i40e_led_is_mine(hw, i);
1478
1479                 if (!gpio_val)
1480                         continue;
1481
1482                 /* ignore gpio LED src mode entries related to the activity
1483                  * LEDs
1484                  */
1485                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1486                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1487                 switch (current_mode) {
1488                 case I40E_COMBINED_ACTIVITY:
1489                 case I40E_FILTER_ACTIVITY:
1490                 case I40E_MAC_ACTIVITY:
1491                 case I40E_LINK_ACTIVITY:
1492                         continue;
1493                 default:
1494                         break;
1495                 }
1496
1497                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1498                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1499                 break;
1500         }
1501
1502         return mode;
1503 }
1504
1505 /**
1506  * i40e_led_set - set new on/off mode
1507  * @hw: pointer to the hw struct
1508  * @mode: 0=off, 0xf=on (else see manual for mode details)
1509  * @blink: true if the LED should blink when on, false if steady
1510  *
1511  * if this function is used to turn on the blink it should
1512  * be used to disable the blink when restoring the original state.
1513  **/
1514 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1515 {
1516         u32 current_mode = 0;
1517         int i;
1518
1519         if (mode & 0xfffffff0)
1520                 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1521
1522         /* as per the documentation GPIO 22-29 are the LED
1523          * GPIO pins named LED0..LED7
1524          */
1525         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1526                 u32 gpio_val = i40e_led_is_mine(hw, i);
1527
1528                 if (!gpio_val)
1529                         continue;
1530
1531                 /* ignore gpio LED src mode entries related to the activity
1532                  * LEDs
1533                  */
1534                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1535                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1536                 switch (current_mode) {
1537                 case I40E_COMBINED_ACTIVITY:
1538                 case I40E_FILTER_ACTIVITY:
1539                 case I40E_MAC_ACTIVITY:
1540                 case I40E_LINK_ACTIVITY:
1541                         continue;
1542                 default:
1543                         break;
1544                 }
1545
1546                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1547                 /* this & is a bit of paranoia, but serves as a range check */
1548                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1549                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1550
1551                 if (blink)
1552                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1553                 else
1554                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1555
1556                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1557                 break;
1558         }
1559 }
1560
1561 /* Admin command wrappers */
1562
1563 /**
1564  * i40e_aq_get_phy_capabilities
1565  * @hw: pointer to the hw struct
1566  * @abilities: structure for PHY capabilities to be filled
1567  * @qualified_modules: report Qualified Modules
1568  * @report_init: report init capabilities (active are default)
1569  * @cmd_details: pointer to command details structure or NULL
1570  *
1571  * Returns the various PHY abilities supported on the Port.
1572  **/
1573 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1574                         bool qualified_modules, bool report_init,
1575                         struct i40e_aq_get_phy_abilities_resp *abilities,
1576                         struct i40e_asq_cmd_details *cmd_details)
1577 {
1578         struct i40e_aq_desc desc;
1579         i40e_status status;
1580         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1581         u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1582
1583         if (!abilities)
1584                 return I40E_ERR_PARAM;
1585
1586         do {
1587                 i40e_fill_default_direct_cmd_desc(&desc,
1588                                                i40e_aqc_opc_get_phy_abilities);
1589
1590                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1591                 if (abilities_size > I40E_AQ_LARGE_BUF)
1592                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1593
1594                 if (qualified_modules)
1595                         desc.params.external.param0 |=
1596                         cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1597
1598                 if (report_init)
1599                         desc.params.external.param0 |=
1600                         cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1601
1602                 status = i40e_asq_send_command(hw, &desc, abilities,
1603                                                abilities_size, cmd_details);
1604
1605                 if (status)
1606                         break;
1607
1608                 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1609                         status = I40E_ERR_UNKNOWN_PHY;
1610                         break;
1611                 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1612                         usleep_range(1000, 2000);
1613                         total_delay++;
1614                         status = I40E_ERR_TIMEOUT;
1615                 }
1616         } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1617                  (total_delay < max_delay));
1618
1619         if (status)
1620                 return status;
1621
1622         if (report_init) {
1623                 if (hw->mac.type ==  I40E_MAC_XL710 &&
1624                     hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1625                     hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1626                         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1627                 } else {
1628                         hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1629                         hw->phy.phy_types |=
1630                                         ((u64)abilities->phy_type_ext << 32);
1631                 }
1632         }
1633
1634         return status;
1635 }
1636
1637 /**
1638  * i40e_aq_set_phy_config
1639  * @hw: pointer to the hw struct
1640  * @config: structure with PHY configuration to be set
1641  * @cmd_details: pointer to command details structure or NULL
1642  *
1643  * Set the various PHY configuration parameters
1644  * supported on the Port.One or more of the Set PHY config parameters may be
1645  * ignored in an MFP mode as the PF may not have the privilege to set some
1646  * of the PHY Config parameters. This status will be indicated by the
1647  * command response.
1648  **/
1649 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1650                                 struct i40e_aq_set_phy_config *config,
1651                                 struct i40e_asq_cmd_details *cmd_details)
1652 {
1653         struct i40e_aq_desc desc;
1654         struct i40e_aq_set_phy_config *cmd =
1655                         (struct i40e_aq_set_phy_config *)&desc.params.raw;
1656         enum i40e_status_code status;
1657
1658         if (!config)
1659                 return I40E_ERR_PARAM;
1660
1661         i40e_fill_default_direct_cmd_desc(&desc,
1662                                           i40e_aqc_opc_set_phy_config);
1663
1664         *cmd = *config;
1665
1666         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1667
1668         return status;
1669 }
1670
1671 static noinline_for_stack enum i40e_status_code
1672 i40e_set_fc_status(struct i40e_hw *hw,
1673                    struct i40e_aq_get_phy_abilities_resp *abilities,
1674                    bool atomic_restart)
1675 {
1676         struct i40e_aq_set_phy_config config;
1677         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1678         u8 pause_mask = 0x0;
1679
1680         switch (fc_mode) {
1681         case I40E_FC_FULL:
1682                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1683                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1684                 break;
1685         case I40E_FC_RX_PAUSE:
1686                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1687                 break;
1688         case I40E_FC_TX_PAUSE:
1689                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1690                 break;
1691         default:
1692                 break;
1693         }
1694
1695         memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1696         /* clear the old pause settings */
1697         config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1698                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1699         /* set the new abilities */
1700         config.abilities |= pause_mask;
1701         /* If the abilities have changed, then set the new config */
1702         if (config.abilities == abilities->abilities)
1703                 return 0;
1704
1705         /* Auto restart link so settings take effect */
1706         if (atomic_restart)
1707                 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1708         /* Copy over all the old settings */
1709         config.phy_type = abilities->phy_type;
1710         config.phy_type_ext = abilities->phy_type_ext;
1711         config.link_speed = abilities->link_speed;
1712         config.eee_capability = abilities->eee_capability;
1713         config.eeer = abilities->eeer_val;
1714         config.low_power_ctrl = abilities->d3_lpan;
1715         config.fec_config = abilities->fec_cfg_curr_mod_ext_info &
1716                             I40E_AQ_PHY_FEC_CONFIG_MASK;
1717
1718         return i40e_aq_set_phy_config(hw, &config, NULL);
1719 }
1720
1721 /**
1722  * i40e_set_fc
1723  * @hw: pointer to the hw struct
1724  * @aq_failures: buffer to return AdminQ failure information
1725  * @atomic_restart: whether to enable atomic link restart
1726  *
1727  * Set the requested flow control mode using set_phy_config.
1728  **/
1729 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1730                                   bool atomic_restart)
1731 {
1732         struct i40e_aq_get_phy_abilities_resp abilities;
1733         enum i40e_status_code status;
1734
1735         *aq_failures = 0x0;
1736
1737         /* Get the current phy config */
1738         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1739                                               NULL);
1740         if (status) {
1741                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1742                 return status;
1743         }
1744
1745         status = i40e_set_fc_status(hw, &abilities, atomic_restart);
1746         if (status)
1747                 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1748
1749         /* Update the link info */
1750         status = i40e_update_link_info(hw);
1751         if (status) {
1752                 /* Wait a little bit (on 40G cards it sometimes takes a really
1753                  * long time for link to come back from the atomic reset)
1754                  * and try once more
1755                  */
1756                 msleep(1000);
1757                 status = i40e_update_link_info(hw);
1758         }
1759         if (status)
1760                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1761
1762         return status;
1763 }
1764
1765 /**
1766  * i40e_aq_clear_pxe_mode
1767  * @hw: pointer to the hw struct
1768  * @cmd_details: pointer to command details structure or NULL
1769  *
1770  * Tell the firmware that the driver is taking over from PXE
1771  **/
1772 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1773                                 struct i40e_asq_cmd_details *cmd_details)
1774 {
1775         i40e_status status;
1776         struct i40e_aq_desc desc;
1777         struct i40e_aqc_clear_pxe *cmd =
1778                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1779
1780         i40e_fill_default_direct_cmd_desc(&desc,
1781                                           i40e_aqc_opc_clear_pxe_mode);
1782
1783         cmd->rx_cnt = 0x2;
1784
1785         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1786
1787         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1788
1789         return status;
1790 }
1791
1792 /**
1793  * i40e_aq_set_link_restart_an
1794  * @hw: pointer to the hw struct
1795  * @enable_link: if true: enable link, if false: disable link
1796  * @cmd_details: pointer to command details structure or NULL
1797  *
1798  * Sets up the link and restarts the Auto-Negotiation over the link.
1799  **/
1800 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1801                                         bool enable_link,
1802                                         struct i40e_asq_cmd_details *cmd_details)
1803 {
1804         struct i40e_aq_desc desc;
1805         struct i40e_aqc_set_link_restart_an *cmd =
1806                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1807         i40e_status status;
1808
1809         i40e_fill_default_direct_cmd_desc(&desc,
1810                                           i40e_aqc_opc_set_link_restart_an);
1811
1812         cmd->command = I40E_AQ_PHY_RESTART_AN;
1813         if (enable_link)
1814                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1815         else
1816                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1817
1818         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1819
1820         return status;
1821 }
1822
1823 /**
1824  * i40e_aq_get_link_info
1825  * @hw: pointer to the hw struct
1826  * @enable_lse: enable/disable LinkStatusEvent reporting
1827  * @link: pointer to link status structure - optional
1828  * @cmd_details: pointer to command details structure or NULL
1829  *
1830  * Returns the link status of the adapter.
1831  **/
1832 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1833                                 bool enable_lse, struct i40e_link_status *link,
1834                                 struct i40e_asq_cmd_details *cmd_details)
1835 {
1836         struct i40e_aq_desc desc;
1837         struct i40e_aqc_get_link_status *resp =
1838                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1839         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1840         i40e_status status;
1841         bool tx_pause, rx_pause;
1842         u16 command_flags;
1843
1844         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1845
1846         if (enable_lse)
1847                 command_flags = I40E_AQ_LSE_ENABLE;
1848         else
1849                 command_flags = I40E_AQ_LSE_DISABLE;
1850         resp->command_flags = cpu_to_le16(command_flags);
1851
1852         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1853
1854         if (status)
1855                 goto aq_get_link_info_exit;
1856
1857         /* save off old link status information */
1858         hw->phy.link_info_old = *hw_link_info;
1859
1860         /* update link status */
1861         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1862         hw->phy.media_type = i40e_get_media_type(hw);
1863         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1864         hw_link_info->link_info = resp->link_info;
1865         hw_link_info->an_info = resp->an_info;
1866         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1867                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1868         hw_link_info->ext_info = resp->ext_info;
1869         hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1870         hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1871         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1872
1873         /* update fc info */
1874         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1875         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1876         if (tx_pause & rx_pause)
1877                 hw->fc.current_mode = I40E_FC_FULL;
1878         else if (tx_pause)
1879                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1880         else if (rx_pause)
1881                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1882         else
1883                 hw->fc.current_mode = I40E_FC_NONE;
1884
1885         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1886                 hw_link_info->crc_enable = true;
1887         else
1888                 hw_link_info->crc_enable = false;
1889
1890         if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1891                 hw_link_info->lse_enable = true;
1892         else
1893                 hw_link_info->lse_enable = false;
1894
1895         if ((hw->mac.type == I40E_MAC_XL710) &&
1896             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1897              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1898                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1899
1900         if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1901             hw->aq.api_min_ver >= 7) {
1902                 __le32 tmp;
1903
1904                 memcpy(&tmp, resp->link_type, sizeof(tmp));
1905                 hw->phy.phy_types = le32_to_cpu(tmp);
1906                 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1907         }
1908
1909         /* save link status information */
1910         if (link)
1911                 *link = *hw_link_info;
1912
1913         /* flag cleared so helper functions don't call AQ again */
1914         hw->phy.get_link_info = false;
1915
1916 aq_get_link_info_exit:
1917         return status;
1918 }
1919
1920 /**
1921  * i40e_aq_set_phy_int_mask
1922  * @hw: pointer to the hw struct
1923  * @mask: interrupt mask to be set
1924  * @cmd_details: pointer to command details structure or NULL
1925  *
1926  * Set link interrupt mask.
1927  **/
1928 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1929                                      u16 mask,
1930                                      struct i40e_asq_cmd_details *cmd_details)
1931 {
1932         struct i40e_aq_desc desc;
1933         struct i40e_aqc_set_phy_int_mask *cmd =
1934                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1935         i40e_status status;
1936
1937         i40e_fill_default_direct_cmd_desc(&desc,
1938                                           i40e_aqc_opc_set_phy_int_mask);
1939
1940         cmd->event_mask = cpu_to_le16(mask);
1941
1942         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1943
1944         return status;
1945 }
1946
1947 /**
1948  * i40e_aq_set_phy_debug
1949  * @hw: pointer to the hw struct
1950  * @cmd_flags: debug command flags
1951  * @cmd_details: pointer to command details structure or NULL
1952  *
1953  * Reset the external PHY.
1954  **/
1955 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1956                                   struct i40e_asq_cmd_details *cmd_details)
1957 {
1958         struct i40e_aq_desc desc;
1959         struct i40e_aqc_set_phy_debug *cmd =
1960                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1961         i40e_status status;
1962
1963         i40e_fill_default_direct_cmd_desc(&desc,
1964                                           i40e_aqc_opc_set_phy_debug);
1965
1966         cmd->command_flags = cmd_flags;
1967
1968         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1969
1970         return status;
1971 }
1972
1973 /**
1974  * i40e_is_aq_api_ver_ge
1975  * @aq: pointer to AdminQ info containing HW API version to compare
1976  * @maj: API major value
1977  * @min: API minor value
1978  *
1979  * Assert whether current HW API version is greater/equal than provided.
1980  **/
1981 static bool i40e_is_aq_api_ver_ge(struct i40e_adminq_info *aq, u16 maj,
1982                                   u16 min)
1983 {
1984         return (aq->api_maj_ver > maj ||
1985                 (aq->api_maj_ver == maj && aq->api_min_ver >= min));
1986 }
1987
1988 /**
1989  * i40e_aq_add_vsi
1990  * @hw: pointer to the hw struct
1991  * @vsi_ctx: pointer to a vsi context struct
1992  * @cmd_details: pointer to command details structure or NULL
1993  *
1994  * Add a VSI context to the hardware.
1995 **/
1996 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1997                                 struct i40e_vsi_context *vsi_ctx,
1998                                 struct i40e_asq_cmd_details *cmd_details)
1999 {
2000         struct i40e_aq_desc desc;
2001         struct i40e_aqc_add_get_update_vsi *cmd =
2002                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2003         struct i40e_aqc_add_get_update_vsi_completion *resp =
2004                 (struct i40e_aqc_add_get_update_vsi_completion *)
2005                 &desc.params.raw;
2006         i40e_status status;
2007
2008         i40e_fill_default_direct_cmd_desc(&desc,
2009                                           i40e_aqc_opc_add_vsi);
2010
2011         cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
2012         cmd->connection_type = vsi_ctx->connection_type;
2013         cmd->vf_id = vsi_ctx->vf_num;
2014         cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
2015
2016         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2017
2018         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2019                                     sizeof(vsi_ctx->info), cmd_details);
2020
2021         if (status)
2022                 goto aq_add_vsi_exit;
2023
2024         vsi_ctx->seid = le16_to_cpu(resp->seid);
2025         vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2026         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2027         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2028
2029 aq_add_vsi_exit:
2030         return status;
2031 }
2032
2033 /**
2034  * i40e_aq_set_default_vsi
2035  * @hw: pointer to the hw struct
2036  * @seid: vsi number
2037  * @cmd_details: pointer to command details structure or NULL
2038  **/
2039 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw,
2040                                     u16 seid,
2041                                     struct i40e_asq_cmd_details *cmd_details)
2042 {
2043         struct i40e_aq_desc desc;
2044         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2045                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2046                 &desc.params.raw;
2047         i40e_status status;
2048
2049         i40e_fill_default_direct_cmd_desc(&desc,
2050                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2051
2052         cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2053         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2054         cmd->seid = cpu_to_le16(seid);
2055
2056         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2057
2058         return status;
2059 }
2060
2061 /**
2062  * i40e_aq_clear_default_vsi
2063  * @hw: pointer to the hw struct
2064  * @seid: vsi number
2065  * @cmd_details: pointer to command details structure or NULL
2066  **/
2067 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2068                                       u16 seid,
2069                                       struct i40e_asq_cmd_details *cmd_details)
2070 {
2071         struct i40e_aq_desc desc;
2072         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2073                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2074                 &desc.params.raw;
2075         i40e_status status;
2076
2077         i40e_fill_default_direct_cmd_desc(&desc,
2078                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2079
2080         cmd->promiscuous_flags = cpu_to_le16(0);
2081         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2082         cmd->seid = cpu_to_le16(seid);
2083
2084         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2085
2086         return status;
2087 }
2088
2089 /**
2090  * i40e_aq_set_vsi_unicast_promiscuous
2091  * @hw: pointer to the hw struct
2092  * @seid: vsi number
2093  * @set: set unicast promiscuous enable/disable
2094  * @cmd_details: pointer to command details structure or NULL
2095  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2096  **/
2097 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2098                                 u16 seid, bool set,
2099                                 struct i40e_asq_cmd_details *cmd_details,
2100                                 bool rx_only_promisc)
2101 {
2102         struct i40e_aq_desc desc;
2103         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2104                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2105         i40e_status status;
2106         u16 flags = 0;
2107
2108         i40e_fill_default_direct_cmd_desc(&desc,
2109                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2110
2111         if (set) {
2112                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2113                 if (rx_only_promisc && i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2114                         flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2115         }
2116
2117         cmd->promiscuous_flags = cpu_to_le16(flags);
2118
2119         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2120         if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2121                 cmd->valid_flags |=
2122                         cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2123
2124         cmd->seid = cpu_to_le16(seid);
2125         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2126
2127         return status;
2128 }
2129
2130 /**
2131  * i40e_aq_set_vsi_multicast_promiscuous
2132  * @hw: pointer to the hw struct
2133  * @seid: vsi number
2134  * @set: set multicast promiscuous enable/disable
2135  * @cmd_details: pointer to command details structure or NULL
2136  **/
2137 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2138                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2139 {
2140         struct i40e_aq_desc desc;
2141         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2142                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2143         i40e_status status;
2144         u16 flags = 0;
2145
2146         i40e_fill_default_direct_cmd_desc(&desc,
2147                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2148
2149         if (set)
2150                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2151
2152         cmd->promiscuous_flags = cpu_to_le16(flags);
2153
2154         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2155
2156         cmd->seid = cpu_to_le16(seid);
2157         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2158
2159         return status;
2160 }
2161
2162 /**
2163  * i40e_aq_set_vsi_mc_promisc_on_vlan
2164  * @hw: pointer to the hw struct
2165  * @seid: vsi number
2166  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2167  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2168  * @cmd_details: pointer to command details structure or NULL
2169  **/
2170 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2171                                                          u16 seid, bool enable,
2172                                                          u16 vid,
2173                                 struct i40e_asq_cmd_details *cmd_details)
2174 {
2175         struct i40e_aq_desc desc;
2176         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2177                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2178         enum i40e_status_code status;
2179         u16 flags = 0;
2180
2181         i40e_fill_default_direct_cmd_desc(&desc,
2182                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2183
2184         if (enable)
2185                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2186
2187         cmd->promiscuous_flags = cpu_to_le16(flags);
2188         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2189         cmd->seid = cpu_to_le16(seid);
2190         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2191
2192         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2193
2194         return status;
2195 }
2196
2197 /**
2198  * i40e_aq_set_vsi_uc_promisc_on_vlan
2199  * @hw: pointer to the hw struct
2200  * @seid: vsi number
2201  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2202  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2203  * @cmd_details: pointer to command details structure or NULL
2204  **/
2205 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2206                                                          u16 seid, bool enable,
2207                                                          u16 vid,
2208                                 struct i40e_asq_cmd_details *cmd_details)
2209 {
2210         struct i40e_aq_desc desc;
2211         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2212                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2213         enum i40e_status_code status;
2214         u16 flags = 0;
2215
2216         i40e_fill_default_direct_cmd_desc(&desc,
2217                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2218
2219         if (enable) {
2220                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2221                 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2222                         flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2223         }
2224
2225         cmd->promiscuous_flags = cpu_to_le16(flags);
2226         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2227         if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2228                 cmd->valid_flags |=
2229                         cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2230         cmd->seid = cpu_to_le16(seid);
2231         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2232
2233         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2234
2235         return status;
2236 }
2237
2238 /**
2239  * i40e_aq_set_vsi_bc_promisc_on_vlan
2240  * @hw: pointer to the hw struct
2241  * @seid: vsi number
2242  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2243  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2244  * @cmd_details: pointer to command details structure or NULL
2245  **/
2246 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2247                                 u16 seid, bool enable, u16 vid,
2248                                 struct i40e_asq_cmd_details *cmd_details)
2249 {
2250         struct i40e_aq_desc desc;
2251         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2252                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2253         i40e_status status;
2254         u16 flags = 0;
2255
2256         i40e_fill_default_direct_cmd_desc(&desc,
2257                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2258
2259         if (enable)
2260                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2261
2262         cmd->promiscuous_flags = cpu_to_le16(flags);
2263         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2264         cmd->seid = cpu_to_le16(seid);
2265         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2266
2267         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2268
2269         return status;
2270 }
2271
2272 /**
2273  * i40e_aq_set_vsi_broadcast
2274  * @hw: pointer to the hw struct
2275  * @seid: vsi number
2276  * @set_filter: true to set filter, false to clear filter
2277  * @cmd_details: pointer to command details structure or NULL
2278  *
2279  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2280  **/
2281 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2282                                 u16 seid, bool set_filter,
2283                                 struct i40e_asq_cmd_details *cmd_details)
2284 {
2285         struct i40e_aq_desc desc;
2286         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2287                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2288         i40e_status status;
2289
2290         i40e_fill_default_direct_cmd_desc(&desc,
2291                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2292
2293         if (set_filter)
2294                 cmd->promiscuous_flags
2295                             |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2296         else
2297                 cmd->promiscuous_flags
2298                             &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2299
2300         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2301         cmd->seid = cpu_to_le16(seid);
2302         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2303
2304         return status;
2305 }
2306
2307 /**
2308  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2309  * @hw: pointer to the hw struct
2310  * @seid: vsi number
2311  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2312  * @cmd_details: pointer to command details structure or NULL
2313  **/
2314 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2315                                        u16 seid, bool enable,
2316                                        struct i40e_asq_cmd_details *cmd_details)
2317 {
2318         struct i40e_aq_desc desc;
2319         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2320                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2321         i40e_status status;
2322         u16 flags = 0;
2323
2324         i40e_fill_default_direct_cmd_desc(&desc,
2325                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2326         if (enable)
2327                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2328
2329         cmd->promiscuous_flags = cpu_to_le16(flags);
2330         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2331         cmd->seid = cpu_to_le16(seid);
2332
2333         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2334
2335         return status;
2336 }
2337
2338 /**
2339  * i40e_get_vsi_params - get VSI configuration info
2340  * @hw: pointer to the hw struct
2341  * @vsi_ctx: pointer to a vsi context struct
2342  * @cmd_details: pointer to command details structure or NULL
2343  **/
2344 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2345                                 struct i40e_vsi_context *vsi_ctx,
2346                                 struct i40e_asq_cmd_details *cmd_details)
2347 {
2348         struct i40e_aq_desc desc;
2349         struct i40e_aqc_add_get_update_vsi *cmd =
2350                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2351         struct i40e_aqc_add_get_update_vsi_completion *resp =
2352                 (struct i40e_aqc_add_get_update_vsi_completion *)
2353                 &desc.params.raw;
2354         i40e_status status;
2355
2356         i40e_fill_default_direct_cmd_desc(&desc,
2357                                           i40e_aqc_opc_get_vsi_parameters);
2358
2359         cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2360
2361         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2362
2363         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2364                                     sizeof(vsi_ctx->info), NULL);
2365
2366         if (status)
2367                 goto aq_get_vsi_params_exit;
2368
2369         vsi_ctx->seid = le16_to_cpu(resp->seid);
2370         vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2371         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2372         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2373
2374 aq_get_vsi_params_exit:
2375         return status;
2376 }
2377
2378 /**
2379  * i40e_aq_update_vsi_params
2380  * @hw: pointer to the hw struct
2381  * @vsi_ctx: pointer to a vsi context struct
2382  * @cmd_details: pointer to command details structure or NULL
2383  *
2384  * Update a VSI context.
2385  **/
2386 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2387                                 struct i40e_vsi_context *vsi_ctx,
2388                                 struct i40e_asq_cmd_details *cmd_details)
2389 {
2390         struct i40e_aq_desc desc;
2391         struct i40e_aqc_add_get_update_vsi *cmd =
2392                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2393         struct i40e_aqc_add_get_update_vsi_completion *resp =
2394                 (struct i40e_aqc_add_get_update_vsi_completion *)
2395                 &desc.params.raw;
2396         i40e_status status;
2397
2398         i40e_fill_default_direct_cmd_desc(&desc,
2399                                           i40e_aqc_opc_update_vsi_parameters);
2400         cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2401
2402         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2403
2404         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2405                                     sizeof(vsi_ctx->info), cmd_details);
2406
2407         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2408         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2409
2410         return status;
2411 }
2412
2413 /**
2414  * i40e_aq_get_switch_config
2415  * @hw: pointer to the hardware structure
2416  * @buf: pointer to the result buffer
2417  * @buf_size: length of input buffer
2418  * @start_seid: seid to start for the report, 0 == beginning
2419  * @cmd_details: pointer to command details structure or NULL
2420  *
2421  * Fill the buf with switch configuration returned from AdminQ command
2422  **/
2423 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2424                                 struct i40e_aqc_get_switch_config_resp *buf,
2425                                 u16 buf_size, u16 *start_seid,
2426                                 struct i40e_asq_cmd_details *cmd_details)
2427 {
2428         struct i40e_aq_desc desc;
2429         struct i40e_aqc_switch_seid *scfg =
2430                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2431         i40e_status status;
2432
2433         i40e_fill_default_direct_cmd_desc(&desc,
2434                                           i40e_aqc_opc_get_switch_config);
2435         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2436         if (buf_size > I40E_AQ_LARGE_BUF)
2437                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2438         scfg->seid = cpu_to_le16(*start_seid);
2439
2440         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2441         *start_seid = le16_to_cpu(scfg->seid);
2442
2443         return status;
2444 }
2445
2446 /**
2447  * i40e_aq_set_switch_config
2448  * @hw: pointer to the hardware structure
2449  * @flags: bit flag values to set
2450  * @mode: cloud filter mode
2451  * @valid_flags: which bit flags to set
2452  * @mode: cloud filter mode
2453  * @cmd_details: pointer to command details structure or NULL
2454  *
2455  * Set switch configuration bits
2456  **/
2457 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2458                                                 u16 flags,
2459                                                 u16 valid_flags, u8 mode,
2460                                 struct i40e_asq_cmd_details *cmd_details)
2461 {
2462         struct i40e_aq_desc desc;
2463         struct i40e_aqc_set_switch_config *scfg =
2464                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2465         enum i40e_status_code status;
2466
2467         i40e_fill_default_direct_cmd_desc(&desc,
2468                                           i40e_aqc_opc_set_switch_config);
2469         scfg->flags = cpu_to_le16(flags);
2470         scfg->valid_flags = cpu_to_le16(valid_flags);
2471         scfg->mode = mode;
2472         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2473                 scfg->switch_tag = cpu_to_le16(hw->switch_tag);
2474                 scfg->first_tag = cpu_to_le16(hw->first_tag);
2475                 scfg->second_tag = cpu_to_le16(hw->second_tag);
2476         }
2477         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2478
2479         return status;
2480 }
2481
2482 /**
2483  * i40e_aq_get_firmware_version
2484  * @hw: pointer to the hw struct
2485  * @fw_major_version: firmware major version
2486  * @fw_minor_version: firmware minor version
2487  * @fw_build: firmware build number
2488  * @api_major_version: major queue version
2489  * @api_minor_version: minor queue version
2490  * @cmd_details: pointer to command details structure or NULL
2491  *
2492  * Get the firmware version from the admin queue commands
2493  **/
2494 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2495                                 u16 *fw_major_version, u16 *fw_minor_version,
2496                                 u32 *fw_build,
2497                                 u16 *api_major_version, u16 *api_minor_version,
2498                                 struct i40e_asq_cmd_details *cmd_details)
2499 {
2500         struct i40e_aq_desc desc;
2501         struct i40e_aqc_get_version *resp =
2502                 (struct i40e_aqc_get_version *)&desc.params.raw;
2503         i40e_status status;
2504
2505         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2506
2507         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2508
2509         if (!status) {
2510                 if (fw_major_version)
2511                         *fw_major_version = le16_to_cpu(resp->fw_major);
2512                 if (fw_minor_version)
2513                         *fw_minor_version = le16_to_cpu(resp->fw_minor);
2514                 if (fw_build)
2515                         *fw_build = le32_to_cpu(resp->fw_build);
2516                 if (api_major_version)
2517                         *api_major_version = le16_to_cpu(resp->api_major);
2518                 if (api_minor_version)
2519                         *api_minor_version = le16_to_cpu(resp->api_minor);
2520         }
2521
2522         return status;
2523 }
2524
2525 /**
2526  * i40e_aq_send_driver_version
2527  * @hw: pointer to the hw struct
2528  * @dv: driver's major, minor version
2529  * @cmd_details: pointer to command details structure or NULL
2530  *
2531  * Send the driver version to the firmware
2532  **/
2533 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2534                                 struct i40e_driver_version *dv,
2535                                 struct i40e_asq_cmd_details *cmd_details)
2536 {
2537         struct i40e_aq_desc desc;
2538         struct i40e_aqc_driver_version *cmd =
2539                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2540         i40e_status status;
2541         u16 len;
2542
2543         if (dv == NULL)
2544                 return I40E_ERR_PARAM;
2545
2546         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2547
2548         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2549         cmd->driver_major_ver = dv->major_version;
2550         cmd->driver_minor_ver = dv->minor_version;
2551         cmd->driver_build_ver = dv->build_version;
2552         cmd->driver_subbuild_ver = dv->subbuild_version;
2553
2554         len = 0;
2555         while (len < sizeof(dv->driver_string) &&
2556                (dv->driver_string[len] < 0x80) &&
2557                dv->driver_string[len])
2558                 len++;
2559         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2560                                        len, cmd_details);
2561
2562         return status;
2563 }
2564
2565 /**
2566  * i40e_get_link_status - get status of the HW network link
2567  * @hw: pointer to the hw struct
2568  * @link_up: pointer to bool (true/false = linkup/linkdown)
2569  *
2570  * Variable link_up true if link is up, false if link is down.
2571  * The variable link_up is invalid if returned value of status != 0
2572  *
2573  * Side effect: LinkStatusEvent reporting becomes enabled
2574  **/
2575 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2576 {
2577         i40e_status status = 0;
2578
2579         if (hw->phy.get_link_info) {
2580                 status = i40e_update_link_info(hw);
2581
2582                 if (status)
2583                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2584                                    status);
2585         }
2586
2587         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2588
2589         return status;
2590 }
2591
2592 /**
2593  * i40e_updatelink_status - update status of the HW network link
2594  * @hw: pointer to the hw struct
2595  **/
2596 noinline_for_stack i40e_status i40e_update_link_info(struct i40e_hw *hw)
2597 {
2598         struct i40e_aq_get_phy_abilities_resp abilities;
2599         i40e_status status = 0;
2600
2601         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2602         if (status)
2603                 return status;
2604
2605         /* extra checking needed to ensure link info to user is timely */
2606         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2607             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2608              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2609                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2610                                                       &abilities, NULL);
2611                 if (status)
2612                         return status;
2613
2614                 hw->phy.link_info.req_fec_info =
2615                         abilities.fec_cfg_curr_mod_ext_info &
2616                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2617
2618                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2619                        sizeof(hw->phy.link_info.module_type));
2620         }
2621
2622         return status;
2623 }
2624
2625 /**
2626  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2627  * @hw: pointer to the hw struct
2628  * @uplink_seid: the MAC or other gizmo SEID
2629  * @downlink_seid: the VSI SEID
2630  * @enabled_tc: bitmap of TCs to be enabled
2631  * @default_port: true for default port VSI, false for control port
2632  * @veb_seid: pointer to where to put the resulting VEB SEID
2633  * @enable_stats: true to turn on VEB stats
2634  * @cmd_details: pointer to command details structure or NULL
2635  *
2636  * This asks the FW to add a VEB between the uplink and downlink
2637  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2638  **/
2639 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2640                                 u16 downlink_seid, u8 enabled_tc,
2641                                 bool default_port, u16 *veb_seid,
2642                                 bool enable_stats,
2643                                 struct i40e_asq_cmd_details *cmd_details)
2644 {
2645         struct i40e_aq_desc desc;
2646         struct i40e_aqc_add_veb *cmd =
2647                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2648         struct i40e_aqc_add_veb_completion *resp =
2649                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2650         i40e_status status;
2651         u16 veb_flags = 0;
2652
2653         /* SEIDs need to either both be set or both be 0 for floating VEB */
2654         if (!!uplink_seid != !!downlink_seid)
2655                 return I40E_ERR_PARAM;
2656
2657         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2658
2659         cmd->uplink_seid = cpu_to_le16(uplink_seid);
2660         cmd->downlink_seid = cpu_to_le16(downlink_seid);
2661         cmd->enable_tcs = enabled_tc;
2662         if (!uplink_seid)
2663                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2664         if (default_port)
2665                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2666         else
2667                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2668
2669         /* reverse logic here: set the bitflag to disable the stats */
2670         if (!enable_stats)
2671                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2672
2673         cmd->veb_flags = cpu_to_le16(veb_flags);
2674
2675         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2676
2677         if (!status && veb_seid)
2678                 *veb_seid = le16_to_cpu(resp->veb_seid);
2679
2680         return status;
2681 }
2682
2683 /**
2684  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2685  * @hw: pointer to the hw struct
2686  * @veb_seid: the SEID of the VEB to query
2687  * @switch_id: the uplink switch id
2688  * @floating: set to true if the VEB is floating
2689  * @statistic_index: index of the stats counter block for this VEB
2690  * @vebs_used: number of VEB's used by function
2691  * @vebs_free: total VEB's not reserved by any function
2692  * @cmd_details: pointer to command details structure or NULL
2693  *
2694  * This retrieves the parameters for a particular VEB, specified by
2695  * uplink_seid, and returns them to the caller.
2696  **/
2697 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2698                                 u16 veb_seid, u16 *switch_id,
2699                                 bool *floating, u16 *statistic_index,
2700                                 u16 *vebs_used, u16 *vebs_free,
2701                                 struct i40e_asq_cmd_details *cmd_details)
2702 {
2703         struct i40e_aq_desc desc;
2704         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2705                 (struct i40e_aqc_get_veb_parameters_completion *)
2706                 &desc.params.raw;
2707         i40e_status status;
2708
2709         if (veb_seid == 0)
2710                 return I40E_ERR_PARAM;
2711
2712         i40e_fill_default_direct_cmd_desc(&desc,
2713                                           i40e_aqc_opc_get_veb_parameters);
2714         cmd_resp->seid = cpu_to_le16(veb_seid);
2715
2716         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2717         if (status)
2718                 goto get_veb_exit;
2719
2720         if (switch_id)
2721                 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2722         if (statistic_index)
2723                 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2724         if (vebs_used)
2725                 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2726         if (vebs_free)
2727                 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2728         if (floating) {
2729                 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2730
2731                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2732                         *floating = true;
2733                 else
2734                         *floating = false;
2735         }
2736
2737 get_veb_exit:
2738         return status;
2739 }
2740
2741 /**
2742  * i40e_aq_add_macvlan
2743  * @hw: pointer to the hw struct
2744  * @seid: VSI for the mac address
2745  * @mv_list: list of macvlans to be added
2746  * @count: length of the list
2747  * @cmd_details: pointer to command details structure or NULL
2748  *
2749  * Add MAC/VLAN addresses to the HW filtering
2750  **/
2751 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2752                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2753                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2754 {
2755         struct i40e_aq_desc desc;
2756         struct i40e_aqc_macvlan *cmd =
2757                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2758         i40e_status status;
2759         u16 buf_size;
2760         int i;
2761
2762         if (count == 0 || !mv_list || !hw)
2763                 return I40E_ERR_PARAM;
2764
2765         buf_size = count * sizeof(*mv_list);
2766
2767         /* prep the rest of the request */
2768         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2769         cmd->num_addresses = cpu_to_le16(count);
2770         cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2771         cmd->seid[1] = 0;
2772         cmd->seid[2] = 0;
2773
2774         for (i = 0; i < count; i++)
2775                 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2776                         mv_list[i].flags |=
2777                                cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2778
2779         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2780         if (buf_size > I40E_AQ_LARGE_BUF)
2781                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2782
2783         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2784                                        cmd_details);
2785
2786         return status;
2787 }
2788
2789 /**
2790  * i40e_aq_remove_macvlan
2791  * @hw: pointer to the hw struct
2792  * @seid: VSI for the mac address
2793  * @mv_list: list of macvlans to be removed
2794  * @count: length of the list
2795  * @cmd_details: pointer to command details structure or NULL
2796  *
2797  * Remove MAC/VLAN addresses from the HW filtering
2798  **/
2799 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2800                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2801                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2802 {
2803         struct i40e_aq_desc desc;
2804         struct i40e_aqc_macvlan *cmd =
2805                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2806         i40e_status status;
2807         u16 buf_size;
2808
2809         if (count == 0 || !mv_list || !hw)
2810                 return I40E_ERR_PARAM;
2811
2812         buf_size = count * sizeof(*mv_list);
2813
2814         /* prep the rest of the request */
2815         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2816         cmd->num_addresses = cpu_to_le16(count);
2817         cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2818         cmd->seid[1] = 0;
2819         cmd->seid[2] = 0;
2820
2821         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2822         if (buf_size > I40E_AQ_LARGE_BUF)
2823                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2824
2825         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2826                                        cmd_details);
2827
2828         return status;
2829 }
2830
2831 /**
2832  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2833  * @hw: pointer to the hw struct
2834  * @opcode: AQ opcode for add or delete mirror rule
2835  * @sw_seid: Switch SEID (to which rule refers)
2836  * @rule_type: Rule Type (ingress/egress/VLAN)
2837  * @id: Destination VSI SEID or Rule ID
2838  * @count: length of the list
2839  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2840  * @cmd_details: pointer to command details structure or NULL
2841  * @rule_id: Rule ID returned from FW
2842  * @rules_used: Number of rules used in internal switch
2843  * @rules_free: Number of rules free in internal switch
2844  *
2845  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2846  * VEBs/VEPA elements only
2847  **/
2848 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2849                                 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2850                                 u16 count, __le16 *mr_list,
2851                                 struct i40e_asq_cmd_details *cmd_details,
2852                                 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2853 {
2854         struct i40e_aq_desc desc;
2855         struct i40e_aqc_add_delete_mirror_rule *cmd =
2856                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2857         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2858         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2859         i40e_status status;
2860         u16 buf_size;
2861
2862         buf_size = count * sizeof(*mr_list);
2863
2864         /* prep the rest of the request */
2865         i40e_fill_default_direct_cmd_desc(&desc, opcode);
2866         cmd->seid = cpu_to_le16(sw_seid);
2867         cmd->rule_type = cpu_to_le16(rule_type &
2868                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
2869         cmd->num_entries = cpu_to_le16(count);
2870         /* Dest VSI for add, rule_id for delete */
2871         cmd->destination = cpu_to_le16(id);
2872         if (mr_list) {
2873                 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2874                                                 I40E_AQ_FLAG_RD));
2875                 if (buf_size > I40E_AQ_LARGE_BUF)
2876                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2877         }
2878
2879         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2880                                        cmd_details);
2881         if (!status ||
2882             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2883                 if (rule_id)
2884                         *rule_id = le16_to_cpu(resp->rule_id);
2885                 if (rules_used)
2886                         *rules_used = le16_to_cpu(resp->mirror_rules_used);
2887                 if (rules_free)
2888                         *rules_free = le16_to_cpu(resp->mirror_rules_free);
2889         }
2890         return status;
2891 }
2892
2893 /**
2894  * i40e_aq_add_mirrorrule - add a mirror rule
2895  * @hw: pointer to the hw struct
2896  * @sw_seid: Switch SEID (to which rule refers)
2897  * @rule_type: Rule Type (ingress/egress/VLAN)
2898  * @dest_vsi: SEID of VSI to which packets will be mirrored
2899  * @count: length of the list
2900  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2901  * @cmd_details: pointer to command details structure or NULL
2902  * @rule_id: Rule ID returned from FW
2903  * @rules_used: Number of rules used in internal switch
2904  * @rules_free: Number of rules free in internal switch
2905  *
2906  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2907  **/
2908 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2909                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2910                         struct i40e_asq_cmd_details *cmd_details,
2911                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2912 {
2913         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2914             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2915                 if (count == 0 || !mr_list)
2916                         return I40E_ERR_PARAM;
2917         }
2918
2919         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2920                                   rule_type, dest_vsi, count, mr_list,
2921                                   cmd_details, rule_id, rules_used, rules_free);
2922 }
2923
2924 /**
2925  * i40e_aq_delete_mirrorrule - delete a mirror rule
2926  * @hw: pointer to the hw struct
2927  * @sw_seid: Switch SEID (to which rule refers)
2928  * @rule_type: Rule Type (ingress/egress/VLAN)
2929  * @count: length of the list
2930  * @rule_id: Rule ID that is returned in the receive desc as part of
2931  *              add_mirrorrule.
2932  * @mr_list: list of mirrored VLAN IDs to be removed
2933  * @cmd_details: pointer to command details structure or NULL
2934  * @rules_used: Number of rules used in internal switch
2935  * @rules_free: Number of rules free in internal switch
2936  *
2937  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2938  **/
2939 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2940                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2941                         struct i40e_asq_cmd_details *cmd_details,
2942                         u16 *rules_used, u16 *rules_free)
2943 {
2944         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2945         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2946                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2947                  * mirroring. For other rule_type, count and rule_type should
2948                  * not matter.
2949                  */
2950                 if (count == 0 || !mr_list)
2951                         return I40E_ERR_PARAM;
2952         }
2953
2954         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2955                                   rule_type, rule_id, count, mr_list,
2956                                   cmd_details, NULL, rules_used, rules_free);
2957 }
2958
2959 /**
2960  * i40e_aq_send_msg_to_vf
2961  * @hw: pointer to the hardware structure
2962  * @vfid: VF id to send msg
2963  * @v_opcode: opcodes for VF-PF communication
2964  * @v_retval: return error code
2965  * @msg: pointer to the msg buffer
2966  * @msglen: msg length
2967  * @cmd_details: pointer to command details
2968  *
2969  * send msg to vf
2970  **/
2971 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2972                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2973                                 struct i40e_asq_cmd_details *cmd_details)
2974 {
2975         struct i40e_aq_desc desc;
2976         struct i40e_aqc_pf_vf_message *cmd =
2977                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2978         i40e_status status;
2979
2980         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2981         cmd->id = cpu_to_le32(vfid);
2982         desc.cookie_high = cpu_to_le32(v_opcode);
2983         desc.cookie_low = cpu_to_le32(v_retval);
2984         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2985         if (msglen) {
2986                 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2987                                                 I40E_AQ_FLAG_RD));
2988                 if (msglen > I40E_AQ_LARGE_BUF)
2989                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2990                 desc.datalen = cpu_to_le16(msglen);
2991         }
2992         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2993
2994         return status;
2995 }
2996
2997 /**
2998  * i40e_aq_debug_read_register
2999  * @hw: pointer to the hw struct
3000  * @reg_addr: register address
3001  * @reg_val: register value
3002  * @cmd_details: pointer to command details structure or NULL
3003  *
3004  * Read the register using the admin queue commands
3005  **/
3006 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
3007                                 u32 reg_addr, u64 *reg_val,
3008                                 struct i40e_asq_cmd_details *cmd_details)
3009 {
3010         struct i40e_aq_desc desc;
3011         struct i40e_aqc_debug_reg_read_write *cmd_resp =
3012                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3013         i40e_status status;
3014
3015         if (reg_val == NULL)
3016                 return I40E_ERR_PARAM;
3017
3018         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
3019
3020         cmd_resp->address = cpu_to_le32(reg_addr);
3021
3022         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3023
3024         if (!status) {
3025                 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
3026                            (u64)le32_to_cpu(cmd_resp->value_low);
3027         }
3028
3029         return status;
3030 }
3031
3032 /**
3033  * i40e_aq_debug_write_register
3034  * @hw: pointer to the hw struct
3035  * @reg_addr: register address
3036  * @reg_val: register value
3037  * @cmd_details: pointer to command details structure or NULL
3038  *
3039  * Write to a register using the admin queue commands
3040  **/
3041 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
3042                                         u32 reg_addr, u64 reg_val,
3043                                         struct i40e_asq_cmd_details *cmd_details)
3044 {
3045         struct i40e_aq_desc desc;
3046         struct i40e_aqc_debug_reg_read_write *cmd =
3047                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
3048         i40e_status status;
3049
3050         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
3051
3052         cmd->address = cpu_to_le32(reg_addr);
3053         cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
3054         cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
3055
3056         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3057
3058         return status;
3059 }
3060
3061 /**
3062  * i40e_aq_request_resource
3063  * @hw: pointer to the hw struct
3064  * @resource: resource id
3065  * @access: access type
3066  * @sdp_number: resource number
3067  * @timeout: the maximum time in ms that the driver may hold the resource
3068  * @cmd_details: pointer to command details structure or NULL
3069  *
3070  * requests common resource using the admin queue commands
3071  **/
3072 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
3073                                 enum i40e_aq_resources_ids resource,
3074                                 enum i40e_aq_resource_access_type access,
3075                                 u8 sdp_number, u64 *timeout,
3076                                 struct i40e_asq_cmd_details *cmd_details)
3077 {
3078         struct i40e_aq_desc desc;
3079         struct i40e_aqc_request_resource *cmd_resp =
3080                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3081         i40e_status status;
3082
3083         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3084
3085         cmd_resp->resource_id = cpu_to_le16(resource);
3086         cmd_resp->access_type = cpu_to_le16(access);
3087         cmd_resp->resource_number = cpu_to_le32(sdp_number);
3088
3089         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3090         /* The completion specifies the maximum time in ms that the driver
3091          * may hold the resource in the Timeout field.
3092          * If the resource is held by someone else, the command completes with
3093          * busy return value and the timeout field indicates the maximum time
3094          * the current owner of the resource has to free it.
3095          */
3096         if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3097                 *timeout = le32_to_cpu(cmd_resp->timeout);
3098
3099         return status;
3100 }
3101
3102 /**
3103  * i40e_aq_release_resource
3104  * @hw: pointer to the hw struct
3105  * @resource: resource id
3106  * @sdp_number: resource number
3107  * @cmd_details: pointer to command details structure or NULL
3108  *
3109  * release common resource using the admin queue commands
3110  **/
3111 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
3112                                 enum i40e_aq_resources_ids resource,
3113                                 u8 sdp_number,
3114                                 struct i40e_asq_cmd_details *cmd_details)
3115 {
3116         struct i40e_aq_desc desc;
3117         struct i40e_aqc_request_resource *cmd =
3118                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3119         i40e_status status;
3120
3121         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3122
3123         cmd->resource_id = cpu_to_le16(resource);
3124         cmd->resource_number = cpu_to_le32(sdp_number);
3125
3126         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3127
3128         return status;
3129 }
3130
3131 /**
3132  * i40e_aq_read_nvm
3133  * @hw: pointer to the hw struct
3134  * @module_pointer: module pointer location in words from the NVM beginning
3135  * @offset: byte offset from the module beginning
3136  * @length: length of the section to be read (in bytes from the offset)
3137  * @data: command buffer (size [bytes] = length)
3138  * @last_command: tells if this is the last command in a series
3139  * @cmd_details: pointer to command details structure or NULL
3140  *
3141  * Read the NVM using the admin queue commands
3142  **/
3143 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3144                                 u32 offset, u16 length, void *data,
3145                                 bool last_command,
3146                                 struct i40e_asq_cmd_details *cmd_details)
3147 {
3148         struct i40e_aq_desc desc;
3149         struct i40e_aqc_nvm_update *cmd =
3150                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3151         i40e_status status;
3152
3153         /* In offset the highest byte must be zeroed. */
3154         if (offset & 0xFF000000) {
3155                 status = I40E_ERR_PARAM;
3156                 goto i40e_aq_read_nvm_exit;
3157         }
3158
3159         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3160
3161         /* If this is the last command in a series, set the proper flag. */
3162         if (last_command)
3163                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3164         cmd->module_pointer = module_pointer;
3165         cmd->offset = cpu_to_le32(offset);
3166         cmd->length = cpu_to_le16(length);
3167
3168         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3169         if (length > I40E_AQ_LARGE_BUF)
3170                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3171
3172         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3173
3174 i40e_aq_read_nvm_exit:
3175         return status;
3176 }
3177
3178 /**
3179  * i40e_aq_erase_nvm
3180  * @hw: pointer to the hw struct
3181  * @module_pointer: module pointer location in words from the NVM beginning
3182  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3183  * @length: length of the section to be erased (expressed in 4 KB)
3184  * @last_command: tells if this is the last command in a series
3185  * @cmd_details: pointer to command details structure or NULL
3186  *
3187  * Erase the NVM sector using the admin queue commands
3188  **/
3189 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3190                               u32 offset, u16 length, bool last_command,
3191                               struct i40e_asq_cmd_details *cmd_details)
3192 {
3193         struct i40e_aq_desc desc;
3194         struct i40e_aqc_nvm_update *cmd =
3195                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3196         i40e_status status;
3197
3198         /* In offset the highest byte must be zeroed. */
3199         if (offset & 0xFF000000) {
3200                 status = I40E_ERR_PARAM;
3201                 goto i40e_aq_erase_nvm_exit;
3202         }
3203
3204         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3205
3206         /* If this is the last command in a series, set the proper flag. */
3207         if (last_command)
3208                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3209         cmd->module_pointer = module_pointer;
3210         cmd->offset = cpu_to_le32(offset);
3211         cmd->length = cpu_to_le16(length);
3212
3213         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3214
3215 i40e_aq_erase_nvm_exit:
3216         return status;
3217 }
3218
3219 /**
3220  * i40e_parse_discover_capabilities
3221  * @hw: pointer to the hw struct
3222  * @buff: pointer to a buffer containing device/function capability records
3223  * @cap_count: number of capability records in the list
3224  * @list_type_opc: type of capabilities list to parse
3225  *
3226  * Parse the device/function capabilities list.
3227  **/
3228 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3229                                      u32 cap_count,
3230                                      enum i40e_admin_queue_opc list_type_opc)
3231 {
3232         struct i40e_aqc_list_capabilities_element_resp *cap;
3233         u32 valid_functions, num_functions;
3234         u32 number, logical_id, phys_id;
3235         struct i40e_hw_capabilities *p;
3236         u16 id, ocp_cfg_word0;
3237         i40e_status status;
3238         u8 major_rev;
3239         u32 i = 0;
3240
3241         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3242
3243         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3244                 p = &hw->dev_caps;
3245         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3246                 p = &hw->func_caps;
3247         else
3248                 return;
3249
3250         for (i = 0; i < cap_count; i++, cap++) {
3251                 id = le16_to_cpu(cap->id);
3252                 number = le32_to_cpu(cap->number);
3253                 logical_id = le32_to_cpu(cap->logical_id);
3254                 phys_id = le32_to_cpu(cap->phys_id);
3255                 major_rev = cap->major_rev;
3256
3257                 switch (id) {
3258                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3259                         p->switch_mode = number;
3260                         break;
3261                 case I40E_AQ_CAP_ID_MNG_MODE:
3262                         p->management_mode = number;
3263                         if (major_rev > 1) {
3264                                 p->mng_protocols_over_mctp = logical_id;
3265                                 i40e_debug(hw, I40E_DEBUG_INIT,
3266                                            "HW Capability: Protocols over MCTP = %d\n",
3267                                            p->mng_protocols_over_mctp);
3268                         } else {
3269                                 p->mng_protocols_over_mctp = 0;
3270                         }
3271                         break;
3272                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3273                         p->npar_enable = number;
3274                         break;
3275                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3276                         p->os2bmc = number;
3277                         break;
3278                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3279                         p->valid_functions = number;
3280                         break;
3281                 case I40E_AQ_CAP_ID_SRIOV:
3282                         if (number == 1)
3283                                 p->sr_iov_1_1 = true;
3284                         break;
3285                 case I40E_AQ_CAP_ID_VF:
3286                         p->num_vfs = number;
3287                         p->vf_base_id = logical_id;
3288                         break;
3289                 case I40E_AQ_CAP_ID_VMDQ:
3290                         if (number == 1)
3291                                 p->vmdq = true;
3292                         break;
3293                 case I40E_AQ_CAP_ID_8021QBG:
3294                         if (number == 1)
3295                                 p->evb_802_1_qbg = true;
3296                         break;
3297                 case I40E_AQ_CAP_ID_8021QBR:
3298                         if (number == 1)
3299                                 p->evb_802_1_qbh = true;
3300                         break;
3301                 case I40E_AQ_CAP_ID_VSI:
3302                         p->num_vsis = number;
3303                         break;
3304                 case I40E_AQ_CAP_ID_DCB:
3305                         if (number == 1) {
3306                                 p->dcb = true;
3307                                 p->enabled_tcmap = logical_id;
3308                                 p->maxtc = phys_id;
3309                         }
3310                         break;
3311                 case I40E_AQ_CAP_ID_FCOE:
3312                         if (number == 1)
3313                                 p->fcoe = true;
3314                         break;
3315                 case I40E_AQ_CAP_ID_ISCSI:
3316                         if (number == 1)
3317                                 p->iscsi = true;
3318                         break;
3319                 case I40E_AQ_CAP_ID_RSS:
3320                         p->rss = true;
3321                         p->rss_table_size = number;
3322                         p->rss_table_entry_width = logical_id;
3323                         break;
3324                 case I40E_AQ_CAP_ID_RXQ:
3325                         p->num_rx_qp = number;
3326                         p->base_queue = phys_id;
3327                         break;
3328                 case I40E_AQ_CAP_ID_TXQ:
3329                         p->num_tx_qp = number;
3330                         p->base_queue = phys_id;
3331                         break;
3332                 case I40E_AQ_CAP_ID_MSIX:
3333                         p->num_msix_vectors = number;
3334                         i40e_debug(hw, I40E_DEBUG_INIT,
3335                                    "HW Capability: MSIX vector count = %d\n",
3336                                    p->num_msix_vectors);
3337                         break;
3338                 case I40E_AQ_CAP_ID_VF_MSIX:
3339                         p->num_msix_vectors_vf = number;
3340                         break;
3341                 case I40E_AQ_CAP_ID_FLEX10:
3342                         if (major_rev == 1) {
3343                                 if (number == 1) {
3344                                         p->flex10_enable = true;
3345                                         p->flex10_capable = true;
3346                                 }
3347                         } else {
3348                                 /* Capability revision >= 2 */
3349                                 if (number & 1)
3350                                         p->flex10_enable = true;
3351                                 if (number & 2)
3352                                         p->flex10_capable = true;
3353                         }
3354                         p->flex10_mode = logical_id;
3355                         p->flex10_status = phys_id;
3356                         break;
3357                 case I40E_AQ_CAP_ID_CEM:
3358                         if (number == 1)
3359                                 p->mgmt_cem = true;
3360                         break;
3361                 case I40E_AQ_CAP_ID_IWARP:
3362                         if (number == 1)
3363                                 p->iwarp = true;
3364                         break;
3365                 case I40E_AQ_CAP_ID_LED:
3366                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3367                                 p->led[phys_id] = true;
3368                         break;
3369                 case I40E_AQ_CAP_ID_SDP:
3370                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3371                                 p->sdp[phys_id] = true;
3372                         break;
3373                 case I40E_AQ_CAP_ID_MDIO:
3374                         if (number == 1) {
3375                                 p->mdio_port_num = phys_id;
3376                                 p->mdio_port_mode = logical_id;
3377                         }
3378                         break;
3379                 case I40E_AQ_CAP_ID_1588:
3380                         if (number == 1)
3381                                 p->ieee_1588 = true;
3382                         break;
3383                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3384                         p->fd = true;
3385                         p->fd_filters_guaranteed = number;
3386                         p->fd_filters_best_effort = logical_id;
3387                         break;
3388                 case I40E_AQ_CAP_ID_WSR_PROT:
3389                         p->wr_csr_prot = (u64)number;
3390                         p->wr_csr_prot |= (u64)logical_id << 32;
3391                         break;
3392                 case I40E_AQ_CAP_ID_NVM_MGMT:
3393                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3394                                 p->sec_rev_disabled = true;
3395                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3396                                 p->update_disabled = true;
3397                         break;
3398                 default:
3399                         break;
3400                 }
3401         }
3402
3403         if (p->fcoe)
3404                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3405
3406         /* Software override ensuring FCoE is disabled if npar or mfp
3407          * mode because it is not supported in these modes.
3408          */
3409         if (p->npar_enable || p->flex10_enable)
3410                 p->fcoe = false;
3411
3412         /* count the enabled ports (aka the "not disabled" ports) */
3413         hw->num_ports = 0;
3414         for (i = 0; i < 4; i++) {
3415                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3416                 u64 port_cfg = 0;
3417
3418                 /* use AQ read to get the physical register offset instead
3419                  * of the port relative offset
3420                  */
3421                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3422                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3423                         hw->num_ports++;
3424         }
3425
3426         /* OCP cards case: if a mezz is removed the Ethernet port is at
3427          * disabled state in PRTGEN_CNF register. Additional NVM read is
3428          * needed in order to check if we are dealing with OCP card.
3429          * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting
3430          * physical ports results in wrong partition id calculation and thus
3431          * not supporting WoL.
3432          */
3433         if (hw->mac.type == I40E_MAC_X722) {
3434                 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) {
3435                         status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3436                                                   2 * I40E_SR_OCP_CFG_WORD0,
3437                                                   sizeof(ocp_cfg_word0),
3438                                                   &ocp_cfg_word0, true, NULL);
3439                         if (!status &&
3440                             (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3441                                 hw->num_ports = 4;
3442                         i40e_release_nvm(hw);
3443                 }
3444         }
3445
3446         valid_functions = p->valid_functions;
3447         num_functions = 0;
3448         while (valid_functions) {
3449                 if (valid_functions & 1)
3450                         num_functions++;
3451                 valid_functions >>= 1;
3452         }
3453
3454         /* partition id is 1-based, and functions are evenly spread
3455          * across the ports as partitions
3456          */
3457         if (hw->num_ports != 0) {
3458                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3459                 hw->num_partitions = num_functions / hw->num_ports;
3460         }
3461
3462         /* additional HW specific goodies that might
3463          * someday be HW version specific
3464          */
3465         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3466 }
3467
3468 /**
3469  * i40e_aq_discover_capabilities
3470  * @hw: pointer to the hw struct
3471  * @buff: a virtual buffer to hold the capabilities
3472  * @buff_size: Size of the virtual buffer
3473  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3474  * @list_type_opc: capabilities type to discover - pass in the command opcode
3475  * @cmd_details: pointer to command details structure or NULL
3476  *
3477  * Get the device capabilities descriptions from the firmware
3478  **/
3479 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3480                                 void *buff, u16 buff_size, u16 *data_size,
3481                                 enum i40e_admin_queue_opc list_type_opc,
3482                                 struct i40e_asq_cmd_details *cmd_details)
3483 {
3484         struct i40e_aqc_list_capabilites *cmd;
3485         struct i40e_aq_desc desc;
3486         i40e_status status = 0;
3487
3488         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3489
3490         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3491                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3492                 status = I40E_ERR_PARAM;
3493                 goto exit;
3494         }
3495
3496         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3497
3498         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3499         if (buff_size > I40E_AQ_LARGE_BUF)
3500                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3501
3502         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3503         *data_size = le16_to_cpu(desc.datalen);
3504
3505         if (status)
3506                 goto exit;
3507
3508         i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3509                                          list_type_opc);
3510
3511 exit:
3512         return status;
3513 }
3514
3515 /**
3516  * i40e_aq_update_nvm
3517  * @hw: pointer to the hw struct
3518  * @module_pointer: module pointer location in words from the NVM beginning
3519  * @offset: byte offset from the module beginning
3520  * @length: length of the section to be written (in bytes from the offset)
3521  * @data: command buffer (size [bytes] = length)
3522  * @last_command: tells if this is the last command in a series
3523  * @preservation_flags: Preservation mode flags
3524  * @cmd_details: pointer to command details structure or NULL
3525  *
3526  * Update the NVM using the admin queue commands
3527  **/
3528 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3529                                u32 offset, u16 length, void *data,
3530                                 bool last_command, u8 preservation_flags,
3531                                struct i40e_asq_cmd_details *cmd_details)
3532 {
3533         struct i40e_aq_desc desc;
3534         struct i40e_aqc_nvm_update *cmd =
3535                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3536         i40e_status status;
3537
3538         /* In offset the highest byte must be zeroed. */
3539         if (offset & 0xFF000000) {
3540                 status = I40E_ERR_PARAM;
3541                 goto i40e_aq_update_nvm_exit;
3542         }
3543
3544         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3545
3546         /* If this is the last command in a series, set the proper flag. */
3547         if (last_command)
3548                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3549         if (hw->mac.type == I40E_MAC_X722) {
3550                 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
3551                         cmd->command_flags |=
3552                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
3553                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3554                 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
3555                         cmd->command_flags |=
3556                                 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
3557                                  I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3558         }
3559         cmd->module_pointer = module_pointer;
3560         cmd->offset = cpu_to_le32(offset);
3561         cmd->length = cpu_to_le16(length);
3562
3563         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3564         if (length > I40E_AQ_LARGE_BUF)
3565                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3566
3567         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3568
3569 i40e_aq_update_nvm_exit:
3570         return status;
3571 }
3572
3573 /**
3574  * i40e_aq_rearrange_nvm
3575  * @hw: pointer to the hw struct
3576  * @rearrange_nvm: defines direction of rearrangement
3577  * @cmd_details: pointer to command details structure or NULL
3578  *
3579  * Rearrange NVM structure, available only for transition FW
3580  **/
3581 i40e_status i40e_aq_rearrange_nvm(struct i40e_hw *hw,
3582                                   u8 rearrange_nvm,
3583                                   struct i40e_asq_cmd_details *cmd_details)
3584 {
3585         struct i40e_aqc_nvm_update *cmd;
3586         i40e_status status;
3587         struct i40e_aq_desc desc;
3588
3589         cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
3590
3591         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3592
3593         rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
3594                          I40E_AQ_NVM_REARRANGE_TO_STRUCT);
3595
3596         if (!rearrange_nvm) {
3597                 status = I40E_ERR_PARAM;
3598                 goto i40e_aq_rearrange_nvm_exit;
3599         }
3600
3601         cmd->command_flags |= rearrange_nvm;
3602         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3603
3604 i40e_aq_rearrange_nvm_exit:
3605         return status;
3606 }
3607
3608 /**
3609  * i40e_aq_get_lldp_mib
3610  * @hw: pointer to the hw struct
3611  * @bridge_type: type of bridge requested
3612  * @mib_type: Local, Remote or both Local and Remote MIBs
3613  * @buff: pointer to a user supplied buffer to store the MIB block
3614  * @buff_size: size of the buffer (in bytes)
3615  * @local_len : length of the returned Local LLDP MIB
3616  * @remote_len: length of the returned Remote LLDP MIB
3617  * @cmd_details: pointer to command details structure or NULL
3618  *
3619  * Requests the complete LLDP MIB (entire packet).
3620  **/
3621 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3622                                 u8 mib_type, void *buff, u16 buff_size,
3623                                 u16 *local_len, u16 *remote_len,
3624                                 struct i40e_asq_cmd_details *cmd_details)
3625 {
3626         struct i40e_aq_desc desc;
3627         struct i40e_aqc_lldp_get_mib *cmd =
3628                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3629         struct i40e_aqc_lldp_get_mib *resp =
3630                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3631         i40e_status status;
3632
3633         if (buff_size == 0 || !buff)
3634                 return I40E_ERR_PARAM;
3635
3636         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3637         /* Indirect Command */
3638         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3639
3640         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3641         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3642                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3643
3644         desc.datalen = cpu_to_le16(buff_size);
3645
3646         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3647         if (buff_size > I40E_AQ_LARGE_BUF)
3648                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3649
3650         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3651         if (!status) {
3652                 if (local_len != NULL)
3653                         *local_len = le16_to_cpu(resp->local_len);
3654                 if (remote_len != NULL)
3655                         *remote_len = le16_to_cpu(resp->remote_len);
3656         }
3657
3658         return status;
3659 }
3660
3661 /**
3662  * i40e_aq_cfg_lldp_mib_change_event
3663  * @hw: pointer to the hw struct
3664  * @enable_update: Enable or Disable event posting
3665  * @cmd_details: pointer to command details structure or NULL
3666  *
3667  * Enable or Disable posting of an event on ARQ when LLDP MIB
3668  * associated with the interface changes
3669  **/
3670 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3671                                 bool enable_update,
3672                                 struct i40e_asq_cmd_details *cmd_details)
3673 {
3674         struct i40e_aq_desc desc;
3675         struct i40e_aqc_lldp_update_mib *cmd =
3676                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3677         i40e_status status;
3678
3679         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3680
3681         if (!enable_update)
3682                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3683
3684         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3685
3686         return status;
3687 }
3688
3689 /**
3690  * i40e_aq_stop_lldp
3691  * @hw: pointer to the hw struct
3692  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3693  * @cmd_details: pointer to command details structure or NULL
3694  *
3695  * Stop or Shutdown the embedded LLDP Agent
3696  **/
3697 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3698                                 struct i40e_asq_cmd_details *cmd_details)
3699 {
3700         struct i40e_aq_desc desc;
3701         struct i40e_aqc_lldp_stop *cmd =
3702                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3703         i40e_status status;
3704
3705         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3706
3707         if (shutdown_agent)
3708                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3709
3710         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3711
3712         return status;
3713 }
3714
3715 /**
3716  * i40e_aq_start_lldp
3717  * @hw: pointer to the hw struct
3718  * @buff: buffer for result
3719  * @buff_size: buffer size
3720  * @cmd_details: pointer to command details structure or NULL
3721  *
3722  * Start the embedded LLDP Agent on all ports.
3723  **/
3724 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3725                                 struct i40e_asq_cmd_details *cmd_details)
3726 {
3727         struct i40e_aq_desc desc;
3728         struct i40e_aqc_lldp_start *cmd =
3729                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3730         i40e_status status;
3731
3732         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3733
3734         cmd->command = I40E_AQ_LLDP_AGENT_START;
3735         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3736
3737         return status;
3738 }
3739
3740 /**
3741  * i40e_aq_set_dcb_parameters
3742  * @hw: pointer to the hw struct
3743  * @cmd_details: pointer to command details structure or NULL
3744  * @dcb_enable: True if DCB configuration needs to be applied
3745  *
3746  **/
3747 enum i40e_status_code
3748 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
3749                            struct i40e_asq_cmd_details *cmd_details)
3750 {
3751         struct i40e_aq_desc desc;
3752         struct i40e_aqc_set_dcb_parameters *cmd =
3753                 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
3754         i40e_status status;
3755
3756         i40e_fill_default_direct_cmd_desc(&desc,
3757                                           i40e_aqc_opc_set_dcb_parameters);
3758
3759         if (dcb_enable) {
3760                 cmd->valid_flags = I40E_DCB_VALID;
3761                 cmd->command = I40E_AQ_DCB_SET_AGENT;
3762         }
3763         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3764
3765         return status;
3766 }
3767
3768 /**
3769  * i40e_aq_get_cee_dcb_config
3770  * @hw: pointer to the hw struct
3771  * @buff: response buffer that stores CEE operational configuration
3772  * @buff_size: size of the buffer passed
3773  * @cmd_details: pointer to command details structure or NULL
3774  *
3775  * Get CEE DCBX mode operational configuration from firmware
3776  **/
3777 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3778                                        void *buff, u16 buff_size,
3779                                        struct i40e_asq_cmd_details *cmd_details)
3780 {
3781         struct i40e_aq_desc desc;
3782         i40e_status status;
3783
3784         if (buff_size == 0 || !buff)
3785                 return I40E_ERR_PARAM;
3786
3787         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3788
3789         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3790         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3791                                        cmd_details);
3792
3793         return status;
3794 }
3795
3796 /**
3797  * i40e_aq_add_udp_tunnel
3798  * @hw: pointer to the hw struct
3799  * @udp_port: the UDP port to add in Host byte order
3800  * @protocol_index: protocol index type
3801  * @filter_index: pointer to filter index
3802  * @cmd_details: pointer to command details structure or NULL
3803  *
3804  * Note: Firmware expects the udp_port value to be in Little Endian format,
3805  * and this function will call cpu_to_le16 to convert from Host byte order to
3806  * Little Endian order.
3807  **/
3808 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3809                                 u16 udp_port, u8 protocol_index,
3810                                 u8 *filter_index,
3811                                 struct i40e_asq_cmd_details *cmd_details)
3812 {
3813         struct i40e_aq_desc desc;
3814         struct i40e_aqc_add_udp_tunnel *cmd =
3815                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3816         struct i40e_aqc_del_udp_tunnel_completion *resp =
3817                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3818         i40e_status status;
3819
3820         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3821
3822         cmd->udp_port = cpu_to_le16(udp_port);
3823         cmd->protocol_type = protocol_index;
3824
3825         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3826
3827         if (!status && filter_index)
3828                 *filter_index = resp->index;
3829
3830         return status;
3831 }
3832
3833 /**
3834  * i40e_aq_del_udp_tunnel
3835  * @hw: pointer to the hw struct
3836  * @index: filter index
3837  * @cmd_details: pointer to command details structure or NULL
3838  **/
3839 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3840                                 struct i40e_asq_cmd_details *cmd_details)
3841 {
3842         struct i40e_aq_desc desc;
3843         struct i40e_aqc_remove_udp_tunnel *cmd =
3844                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3845         i40e_status status;
3846
3847         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3848
3849         cmd->index = index;
3850
3851         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3852
3853         return status;
3854 }
3855
3856 /**
3857  * i40e_aq_delete_element - Delete switch element
3858  * @hw: pointer to the hw struct
3859  * @seid: the SEID to delete from the switch
3860  * @cmd_details: pointer to command details structure or NULL
3861  *
3862  * This deletes a switch element from the switch.
3863  **/
3864 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3865                                 struct i40e_asq_cmd_details *cmd_details)
3866 {
3867         struct i40e_aq_desc desc;
3868         struct i40e_aqc_switch_seid *cmd =
3869                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3870         i40e_status status;
3871
3872         if (seid == 0)
3873                 return I40E_ERR_PARAM;
3874
3875         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3876
3877         cmd->seid = cpu_to_le16(seid);
3878
3879         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3880
3881         return status;
3882 }
3883
3884 /**
3885  * i40e_aq_dcb_updated - DCB Updated Command
3886  * @hw: pointer to the hw struct
3887  * @cmd_details: pointer to command details structure or NULL
3888  *
3889  * EMP will return when the shared RPB settings have been
3890  * recomputed and modified. The retval field in the descriptor
3891  * will be set to 0 when RPB is modified.
3892  **/
3893 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3894                                 struct i40e_asq_cmd_details *cmd_details)
3895 {
3896         struct i40e_aq_desc desc;
3897         i40e_status status;
3898
3899         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3900
3901         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3902
3903         return status;
3904 }
3905
3906 /**
3907  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3908  * @hw: pointer to the hw struct
3909  * @seid: seid for the physical port/switching component/vsi
3910  * @buff: Indirect buffer to hold data parameters and response
3911  * @buff_size: Indirect buffer size
3912  * @opcode: Tx scheduler AQ command opcode
3913  * @cmd_details: pointer to command details structure or NULL
3914  *
3915  * Generic command handler for Tx scheduler AQ commands
3916  **/
3917 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3918                                 void *buff, u16 buff_size,
3919                                  enum i40e_admin_queue_opc opcode,
3920                                 struct i40e_asq_cmd_details *cmd_details)
3921 {
3922         struct i40e_aq_desc desc;
3923         struct i40e_aqc_tx_sched_ind *cmd =
3924                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3925         i40e_status status;
3926         bool cmd_param_flag = false;
3927
3928         switch (opcode) {
3929         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3930         case i40e_aqc_opc_configure_vsi_tc_bw:
3931         case i40e_aqc_opc_enable_switching_comp_ets:
3932         case i40e_aqc_opc_modify_switching_comp_ets:
3933         case i40e_aqc_opc_disable_switching_comp_ets:
3934         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3935         case i40e_aqc_opc_configure_switching_comp_bw_config:
3936                 cmd_param_flag = true;
3937                 break;
3938         case i40e_aqc_opc_query_vsi_bw_config:
3939         case i40e_aqc_opc_query_vsi_ets_sla_config:
3940         case i40e_aqc_opc_query_switching_comp_ets_config:
3941         case i40e_aqc_opc_query_port_ets_config:
3942         case i40e_aqc_opc_query_switching_comp_bw_config:
3943                 cmd_param_flag = false;
3944                 break;
3945         default:
3946                 return I40E_ERR_PARAM;
3947         }
3948
3949         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3950
3951         /* Indirect command */
3952         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3953         if (cmd_param_flag)
3954                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3955         if (buff_size > I40E_AQ_LARGE_BUF)
3956                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3957
3958         desc.datalen = cpu_to_le16(buff_size);
3959
3960         cmd->vsi_seid = cpu_to_le16(seid);
3961
3962         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3963
3964         return status;
3965 }
3966
3967 /**
3968  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3969  * @hw: pointer to the hw struct
3970  * @seid: VSI seid
3971  * @credit: BW limit credits (0 = disabled)
3972  * @max_credit: Max BW limit credits
3973  * @cmd_details: pointer to command details structure or NULL
3974  **/
3975 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3976                                 u16 seid, u16 credit, u8 max_credit,
3977                                 struct i40e_asq_cmd_details *cmd_details)
3978 {
3979         struct i40e_aq_desc desc;
3980         struct i40e_aqc_configure_vsi_bw_limit *cmd =
3981                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3982         i40e_status status;
3983
3984         i40e_fill_default_direct_cmd_desc(&desc,
3985                                           i40e_aqc_opc_configure_vsi_bw_limit);
3986
3987         cmd->vsi_seid = cpu_to_le16(seid);
3988         cmd->credit = cpu_to_le16(credit);
3989         cmd->max_credit = max_credit;
3990
3991         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3992
3993         return status;
3994 }
3995
3996 /**
3997  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3998  * @hw: pointer to the hw struct
3999  * @seid: VSI seid
4000  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
4001  * @cmd_details: pointer to command details structure or NULL
4002  **/
4003 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
4004                         u16 seid,
4005                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
4006                         struct i40e_asq_cmd_details *cmd_details)
4007 {
4008         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4009                                     i40e_aqc_opc_configure_vsi_tc_bw,
4010                                     cmd_details);
4011 }
4012
4013 /**
4014  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
4015  * @hw: pointer to the hw struct
4016  * @seid: seid of the switching component connected to Physical Port
4017  * @ets_data: Buffer holding ETS parameters
4018  * @opcode: Tx scheduler AQ command opcode
4019  * @cmd_details: pointer to command details structure or NULL
4020  **/
4021 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4022                 u16 seid,
4023                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4024                 enum i40e_admin_queue_opc opcode,
4025                 struct i40e_asq_cmd_details *cmd_details)
4026 {
4027         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4028                                     sizeof(*ets_data), opcode, cmd_details);
4029 }
4030
4031 /**
4032  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
4033  * @hw: pointer to the hw struct
4034  * @seid: seid of the switching component
4035  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
4036  * @cmd_details: pointer to command details structure or NULL
4037  **/
4038 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4039         u16 seid,
4040         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4041         struct i40e_asq_cmd_details *cmd_details)
4042 {
4043         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4044                             i40e_aqc_opc_configure_switching_comp_bw_config,
4045                             cmd_details);
4046 }
4047
4048 /**
4049  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
4050  * @hw: pointer to the hw struct
4051  * @seid: seid of the VSI
4052  * @bw_data: Buffer to hold VSI BW configuration
4053  * @cmd_details: pointer to command details structure or NULL
4054  **/
4055 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4056                         u16 seid,
4057                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4058                         struct i40e_asq_cmd_details *cmd_details)
4059 {
4060         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4061                                     i40e_aqc_opc_query_vsi_bw_config,
4062                                     cmd_details);
4063 }
4064
4065 /**
4066  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
4067  * @hw: pointer to the hw struct
4068  * @seid: seid of the VSI
4069  * @bw_data: Buffer to hold VSI BW configuration per TC
4070  * @cmd_details: pointer to command details structure or NULL
4071  **/
4072 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4073                         u16 seid,
4074                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4075                         struct i40e_asq_cmd_details *cmd_details)
4076 {
4077         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4078                                     i40e_aqc_opc_query_vsi_ets_sla_config,
4079                                     cmd_details);
4080 }
4081
4082 /**
4083  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
4084  * @hw: pointer to the hw struct
4085  * @seid: seid of the switching component
4086  * @bw_data: Buffer to hold switching component's per TC BW config
4087  * @cmd_details: pointer to command details structure or NULL
4088  **/
4089 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4090                 u16 seid,
4091                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4092                 struct i40e_asq_cmd_details *cmd_details)
4093 {
4094         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4095                                    i40e_aqc_opc_query_switching_comp_ets_config,
4096                                    cmd_details);
4097 }
4098
4099 /**
4100  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
4101  * @hw: pointer to the hw struct
4102  * @seid: seid of the VSI or switching component connected to Physical Port
4103  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
4104  * @cmd_details: pointer to command details structure or NULL
4105  **/
4106 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4107                         u16 seid,
4108                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
4109                         struct i40e_asq_cmd_details *cmd_details)
4110 {
4111         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4112                                     i40e_aqc_opc_query_port_ets_config,
4113                                     cmd_details);
4114 }
4115
4116 /**
4117  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
4118  * @hw: pointer to the hw struct
4119  * @seid: seid of the switching component
4120  * @bw_data: Buffer to hold switching component's BW configuration
4121  * @cmd_details: pointer to command details structure or NULL
4122  **/
4123 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4124                 u16 seid,
4125                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4126                 struct i40e_asq_cmd_details *cmd_details)
4127 {
4128         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4129                                     i40e_aqc_opc_query_switching_comp_bw_config,
4130                                     cmd_details);
4131 }
4132
4133 /**
4134  * i40e_validate_filter_settings
4135  * @hw: pointer to the hardware structure
4136  * @settings: Filter control settings
4137  *
4138  * Check and validate the filter control settings passed.
4139  * The function checks for the valid filter/context sizes being
4140  * passed for FCoE and PE.
4141  *
4142  * Returns 0 if the values passed are valid and within
4143  * range else returns an error.
4144  **/
4145 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
4146                                 struct i40e_filter_control_settings *settings)
4147 {
4148         u32 fcoe_cntx_size, fcoe_filt_size;
4149         u32 pe_cntx_size, pe_filt_size;
4150         u32 fcoe_fmax;
4151         u32 val;
4152
4153         /* Validate FCoE settings passed */
4154         switch (settings->fcoe_filt_num) {
4155         case I40E_HASH_FILTER_SIZE_1K:
4156         case I40E_HASH_FILTER_SIZE_2K:
4157         case I40E_HASH_FILTER_SIZE_4K:
4158         case I40E_HASH_FILTER_SIZE_8K:
4159         case I40E_HASH_FILTER_SIZE_16K:
4160         case I40E_HASH_FILTER_SIZE_32K:
4161                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4162                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4163                 break;
4164         default:
4165                 return I40E_ERR_PARAM;
4166         }
4167
4168         switch (settings->fcoe_cntx_num) {
4169         case I40E_DMA_CNTX_SIZE_512:
4170         case I40E_DMA_CNTX_SIZE_1K:
4171         case I40E_DMA_CNTX_SIZE_2K:
4172         case I40E_DMA_CNTX_SIZE_4K:
4173                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4174                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4175                 break;
4176         default:
4177                 return I40E_ERR_PARAM;
4178         }
4179
4180         /* Validate PE settings passed */
4181         switch (settings->pe_filt_num) {
4182         case I40E_HASH_FILTER_SIZE_1K:
4183         case I40E_HASH_FILTER_SIZE_2K:
4184         case I40E_HASH_FILTER_SIZE_4K:
4185         case I40E_HASH_FILTER_SIZE_8K:
4186         case I40E_HASH_FILTER_SIZE_16K:
4187         case I40E_HASH_FILTER_SIZE_32K:
4188         case I40E_HASH_FILTER_SIZE_64K:
4189         case I40E_HASH_FILTER_SIZE_128K:
4190         case I40E_HASH_FILTER_SIZE_256K:
4191         case I40E_HASH_FILTER_SIZE_512K:
4192         case I40E_HASH_FILTER_SIZE_1M:
4193                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4194                 pe_filt_size <<= (u32)settings->pe_filt_num;
4195                 break;
4196         default:
4197                 return I40E_ERR_PARAM;
4198         }
4199
4200         switch (settings->pe_cntx_num) {
4201         case I40E_DMA_CNTX_SIZE_512:
4202         case I40E_DMA_CNTX_SIZE_1K:
4203         case I40E_DMA_CNTX_SIZE_2K:
4204         case I40E_DMA_CNTX_SIZE_4K:
4205         case I40E_DMA_CNTX_SIZE_8K:
4206         case I40E_DMA_CNTX_SIZE_16K:
4207         case I40E_DMA_CNTX_SIZE_32K:
4208         case I40E_DMA_CNTX_SIZE_64K:
4209         case I40E_DMA_CNTX_SIZE_128K:
4210         case I40E_DMA_CNTX_SIZE_256K:
4211                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4212                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4213                 break;
4214         default:
4215                 return I40E_ERR_PARAM;
4216         }
4217
4218         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4219         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4220         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4221                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4222         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
4223                 return I40E_ERR_INVALID_SIZE;
4224
4225         return 0;
4226 }
4227
4228 /**
4229  * i40e_set_filter_control
4230  * @hw: pointer to the hardware structure
4231  * @settings: Filter control settings
4232  *
4233  * Set the Queue Filters for PE/FCoE and enable filters required
4234  * for a single PF. It is expected that these settings are programmed
4235  * at the driver initialization time.
4236  **/
4237 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
4238                                 struct i40e_filter_control_settings *settings)
4239 {
4240         i40e_status ret = 0;
4241         u32 hash_lut_size = 0;
4242         u32 val;
4243
4244         if (!settings)
4245                 return I40E_ERR_PARAM;
4246
4247         /* Validate the input settings */
4248         ret = i40e_validate_filter_settings(hw, settings);
4249         if (ret)
4250                 return ret;
4251
4252         /* Read the PF Queue Filter control register */
4253         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
4254
4255         /* Program required PE hash buckets for the PF */
4256         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4257         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4258                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4259         /* Program required PE contexts for the PF */
4260         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4261         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4262                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4263
4264         /* Program required FCoE hash buckets for the PF */
4265         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4266         val |= ((u32)settings->fcoe_filt_num <<
4267                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4268                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4269         /* Program required FCoE DDP contexts for the PF */
4270         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4271         val |= ((u32)settings->fcoe_cntx_num <<
4272                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4273                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4274
4275         /* Program Hash LUT size for the PF */
4276         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4277         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4278                 hash_lut_size = 1;
4279         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4280                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4281
4282         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4283         if (settings->enable_fdir)
4284                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4285         if (settings->enable_ethtype)
4286                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4287         if (settings->enable_macvlan)
4288                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4289
4290         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
4291
4292         return 0;
4293 }
4294
4295 /**
4296  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4297  * @hw: pointer to the hw struct
4298  * @mac_addr: MAC address to use in the filter
4299  * @ethtype: Ethertype to use in the filter
4300  * @flags: Flags that needs to be applied to the filter
4301  * @vsi_seid: seid of the control VSI
4302  * @queue: VSI queue number to send the packet to
4303  * @is_add: Add control packet filter if True else remove
4304  * @stats: Structure to hold information on control filter counts
4305  * @cmd_details: pointer to command details structure or NULL
4306  *
4307  * This command will Add or Remove control packet filter for a control VSI.
4308  * In return it will update the total number of perfect filter count in
4309  * the stats member.
4310  **/
4311 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4312                                 u8 *mac_addr, u16 ethtype, u16 flags,
4313                                 u16 vsi_seid, u16 queue, bool is_add,
4314                                 struct i40e_control_filter_stats *stats,
4315                                 struct i40e_asq_cmd_details *cmd_details)
4316 {
4317         struct i40e_aq_desc desc;
4318         struct i40e_aqc_add_remove_control_packet_filter *cmd =
4319                 (struct i40e_aqc_add_remove_control_packet_filter *)
4320                 &desc.params.raw;
4321         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4322                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4323                 &desc.params.raw;
4324         i40e_status status;
4325
4326         if (vsi_seid == 0)
4327                 return I40E_ERR_PARAM;
4328
4329         if (is_add) {
4330                 i40e_fill_default_direct_cmd_desc(&desc,
4331                                 i40e_aqc_opc_add_control_packet_filter);
4332                 cmd->queue = cpu_to_le16(queue);
4333         } else {
4334                 i40e_fill_default_direct_cmd_desc(&desc,
4335                                 i40e_aqc_opc_remove_control_packet_filter);
4336         }
4337
4338         if (mac_addr)
4339                 ether_addr_copy(cmd->mac, mac_addr);
4340
4341         cmd->etype = cpu_to_le16(ethtype);
4342         cmd->flags = cpu_to_le16(flags);
4343         cmd->seid = cpu_to_le16(vsi_seid);
4344
4345         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4346
4347         if (!status && stats) {
4348                 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4349                 stats->etype_used = le16_to_cpu(resp->etype_used);
4350                 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4351                 stats->etype_free = le16_to_cpu(resp->etype_free);
4352         }
4353
4354         return status;
4355 }
4356
4357 /**
4358  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4359  * @hw: pointer to the hw struct
4360  * @seid: VSI seid to add ethertype filter from
4361  **/
4362 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4363                                                     u16 seid)
4364 {
4365 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4366         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4367                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4368                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4369         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4370         i40e_status status;
4371
4372         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4373                                                        seid, 0, true, NULL,
4374                                                        NULL);
4375         if (status)
4376                 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4377 }
4378
4379 /**
4380  * i40e_aq_alternate_read
4381  * @hw: pointer to the hardware structure
4382  * @reg_addr0: address of first dword to be read
4383  * @reg_val0: pointer for data read from 'reg_addr0'
4384  * @reg_addr1: address of second dword to be read
4385  * @reg_val1: pointer for data read from 'reg_addr1'
4386  *
4387  * Read one or two dwords from alternate structure. Fields are indicated
4388  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4389  * is not passed then only register at 'reg_addr0' is read.
4390  *
4391  **/
4392 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4393                                           u32 reg_addr0, u32 *reg_val0,
4394                                           u32 reg_addr1, u32 *reg_val1)
4395 {
4396         struct i40e_aq_desc desc;
4397         struct i40e_aqc_alternate_write *cmd_resp =
4398                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4399         i40e_status status;
4400
4401         if (!reg_val0)
4402                 return I40E_ERR_PARAM;
4403
4404         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4405         cmd_resp->address0 = cpu_to_le32(reg_addr0);
4406         cmd_resp->address1 = cpu_to_le32(reg_addr1);
4407
4408         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4409
4410         if (!status) {
4411                 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4412
4413                 if (reg_val1)
4414                         *reg_val1 = le32_to_cpu(cmd_resp->data1);
4415         }
4416
4417         return status;
4418 }
4419
4420 /**
4421  * i40e_aq_resume_port_tx
4422  * @hw: pointer to the hardware structure
4423  * @cmd_details: pointer to command details structure or NULL
4424  *
4425  * Resume port's Tx traffic
4426  **/
4427 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4428                                    struct i40e_asq_cmd_details *cmd_details)
4429 {
4430         struct i40e_aq_desc desc;
4431         i40e_status status;
4432
4433         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4434
4435         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4436
4437         return status;
4438 }
4439
4440 /**
4441  * i40e_set_pci_config_data - store PCI bus info
4442  * @hw: pointer to hardware structure
4443  * @link_status: the link status word from PCI config space
4444  *
4445  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4446  **/
4447 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4448 {
4449         hw->bus.type = i40e_bus_type_pci_express;
4450
4451         switch (link_status & PCI_EXP_LNKSTA_NLW) {
4452         case PCI_EXP_LNKSTA_NLW_X1:
4453                 hw->bus.width = i40e_bus_width_pcie_x1;
4454                 break;
4455         case PCI_EXP_LNKSTA_NLW_X2:
4456                 hw->bus.width = i40e_bus_width_pcie_x2;
4457                 break;
4458         case PCI_EXP_LNKSTA_NLW_X4:
4459                 hw->bus.width = i40e_bus_width_pcie_x4;
4460                 break;
4461         case PCI_EXP_LNKSTA_NLW_X8:
4462                 hw->bus.width = i40e_bus_width_pcie_x8;
4463                 break;
4464         default:
4465                 hw->bus.width = i40e_bus_width_unknown;
4466                 break;
4467         }
4468
4469         switch (link_status & PCI_EXP_LNKSTA_CLS) {
4470         case PCI_EXP_LNKSTA_CLS_2_5GB:
4471                 hw->bus.speed = i40e_bus_speed_2500;
4472                 break;
4473         case PCI_EXP_LNKSTA_CLS_5_0GB:
4474                 hw->bus.speed = i40e_bus_speed_5000;
4475                 break;
4476         case PCI_EXP_LNKSTA_CLS_8_0GB:
4477                 hw->bus.speed = i40e_bus_speed_8000;
4478                 break;
4479         default:
4480                 hw->bus.speed = i40e_bus_speed_unknown;
4481                 break;
4482         }
4483 }
4484
4485 /**
4486  * i40e_aq_debug_dump
4487  * @hw: pointer to the hardware structure
4488  * @cluster_id: specific cluster to dump
4489  * @table_id: table id within cluster
4490  * @start_index: index of line in the block to read
4491  * @buff_size: dump buffer size
4492  * @buff: dump buffer
4493  * @ret_buff_size: actual buffer size returned
4494  * @ret_next_table: next block to read
4495  * @ret_next_index: next index to read
4496  * @cmd_details: pointer to command details structure or NULL
4497  *
4498  * Dump internal FW/HW data for debug purposes.
4499  *
4500  **/
4501 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4502                                u8 table_id, u32 start_index, u16 buff_size,
4503                                void *buff, u16 *ret_buff_size,
4504                                u8 *ret_next_table, u32 *ret_next_index,
4505                                struct i40e_asq_cmd_details *cmd_details)
4506 {
4507         struct i40e_aq_desc desc;
4508         struct i40e_aqc_debug_dump_internals *cmd =
4509                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4510         struct i40e_aqc_debug_dump_internals *resp =
4511                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4512         i40e_status status;
4513
4514         if (buff_size == 0 || !buff)
4515                 return I40E_ERR_PARAM;
4516
4517         i40e_fill_default_direct_cmd_desc(&desc,
4518                                           i40e_aqc_opc_debug_dump_internals);
4519         /* Indirect Command */
4520         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4521         if (buff_size > I40E_AQ_LARGE_BUF)
4522                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4523
4524         cmd->cluster_id = cluster_id;
4525         cmd->table_id = table_id;
4526         cmd->idx = cpu_to_le32(start_index);
4527
4528         desc.datalen = cpu_to_le16(buff_size);
4529
4530         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4531         if (!status) {
4532                 if (ret_buff_size)
4533                         *ret_buff_size = le16_to_cpu(desc.datalen);
4534                 if (ret_next_table)
4535                         *ret_next_table = resp->table_id;
4536                 if (ret_next_index)
4537                         *ret_next_index = le32_to_cpu(resp->idx);
4538         }
4539
4540         return status;
4541 }
4542
4543 /**
4544  * i40e_read_bw_from_alt_ram
4545  * @hw: pointer to the hardware structure
4546  * @max_bw: pointer for max_bw read
4547  * @min_bw: pointer for min_bw read
4548  * @min_valid: pointer for bool that is true if min_bw is a valid value
4549  * @max_valid: pointer for bool that is true if max_bw is a valid value
4550  *
4551  * Read bw from the alternate ram for the given pf
4552  **/
4553 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4554                                       u32 *max_bw, u32 *min_bw,
4555                                       bool *min_valid, bool *max_valid)
4556 {
4557         i40e_status status;
4558         u32 max_bw_addr, min_bw_addr;
4559
4560         /* Calculate the address of the min/max bw registers */
4561         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4562                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
4563                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4564         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4565                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
4566                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4567
4568         /* Read the bandwidths from alt ram */
4569         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4570                                         min_bw_addr, min_bw);
4571
4572         if (*min_bw & I40E_ALT_BW_VALID_MASK)
4573                 *min_valid = true;
4574         else
4575                 *min_valid = false;
4576
4577         if (*max_bw & I40E_ALT_BW_VALID_MASK)
4578                 *max_valid = true;
4579         else
4580                 *max_valid = false;
4581
4582         return status;
4583 }
4584
4585 /**
4586  * i40e_aq_configure_partition_bw
4587  * @hw: pointer to the hardware structure
4588  * @bw_data: Buffer holding valid pfs and bw limits
4589  * @cmd_details: pointer to command details
4590  *
4591  * Configure partitions guaranteed/max bw
4592  **/
4593 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4594                         struct i40e_aqc_configure_partition_bw_data *bw_data,
4595                         struct i40e_asq_cmd_details *cmd_details)
4596 {
4597         i40e_status status;
4598         struct i40e_aq_desc desc;
4599         u16 bwd_size = sizeof(*bw_data);
4600
4601         i40e_fill_default_direct_cmd_desc(&desc,
4602                                           i40e_aqc_opc_configure_partition_bw);
4603
4604         /* Indirect command */
4605         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4606         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4607
4608         if (bwd_size > I40E_AQ_LARGE_BUF)
4609                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4610
4611         desc.datalen = cpu_to_le16(bwd_size);
4612
4613         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4614                                        cmd_details);
4615
4616         return status;
4617 }
4618
4619 /**
4620  * i40e_read_phy_register_clause22
4621  * @hw: pointer to the HW structure
4622  * @reg: register address in the page
4623  * @phy_addr: PHY address on MDIO interface
4624  * @value: PHY register value
4625  *
4626  * Reads specified PHY register value
4627  **/
4628 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
4629                                             u16 reg, u8 phy_addr, u16 *value)
4630 {
4631         i40e_status status = I40E_ERR_TIMEOUT;
4632         u8 port_num = (u8)hw->func_caps.mdio_port_num;
4633         u32 command = 0;
4634         u16 retry = 1000;
4635
4636         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4637                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4638                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4639                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4640                   (I40E_GLGEN_MSCA_MDICMD_MASK);
4641         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4642         do {
4643                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4644                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4645                         status = 0;
4646                         break;
4647                 }
4648                 udelay(10);
4649                 retry--;
4650         } while (retry);
4651
4652         if (status) {
4653                 i40e_debug(hw, I40E_DEBUG_PHY,
4654                            "PHY: Can't write command to external PHY.\n");
4655         } else {
4656                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4657                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4658                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4659         }
4660
4661         return status;
4662 }
4663
4664 /**
4665  * i40e_write_phy_register_clause22
4666  * @hw: pointer to the HW structure
4667  * @reg: register address in the page
4668  * @phy_addr: PHY address on MDIO interface
4669  * @value: PHY register value
4670  *
4671  * Writes specified PHY register value
4672  **/
4673 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
4674                                              u16 reg, u8 phy_addr, u16 value)
4675 {
4676         i40e_status status = I40E_ERR_TIMEOUT;
4677         u8 port_num = (u8)hw->func_caps.mdio_port_num;
4678         u32 command  = 0;
4679         u16 retry = 1000;
4680
4681         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4682         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4683
4684         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4685                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4686                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4687                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4688                   (I40E_GLGEN_MSCA_MDICMD_MASK);
4689
4690         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4691         do {
4692                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4693                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4694                         status = 0;
4695                         break;
4696                 }
4697                 udelay(10);
4698                 retry--;
4699         } while (retry);
4700
4701         return status;
4702 }
4703
4704 /**
4705  * i40e_read_phy_register_clause45
4706  * @hw: pointer to the HW structure
4707  * @page: registers page number
4708  * @reg: register address in the page
4709  * @phy_addr: PHY address on MDIO interface
4710  * @value: PHY register value
4711  *
4712  * Reads specified PHY register value
4713  **/
4714 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
4715                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
4716 {
4717         i40e_status status = I40E_ERR_TIMEOUT;
4718         u32 command = 0;
4719         u16 retry = 1000;
4720         u8 port_num = hw->func_caps.mdio_port_num;
4721
4722         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4723                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4724                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4725                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4726                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4727                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4728                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4729         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4730         do {
4731                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4732                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4733                         status = 0;
4734                         break;
4735                 }
4736                 usleep_range(10, 20);
4737                 retry--;
4738         } while (retry);
4739
4740         if (status) {
4741                 i40e_debug(hw, I40E_DEBUG_PHY,
4742                            "PHY: Can't write command to external PHY.\n");
4743                 goto phy_read_end;
4744         }
4745
4746         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4747                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4748                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4749                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4750                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4751                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4752         status = I40E_ERR_TIMEOUT;
4753         retry = 1000;
4754         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4755         do {
4756                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4757                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4758                         status = 0;
4759                         break;
4760                 }
4761                 usleep_range(10, 20);
4762                 retry--;
4763         } while (retry);
4764
4765         if (!status) {
4766                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4767                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4768                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4769         } else {
4770                 i40e_debug(hw, I40E_DEBUG_PHY,
4771                            "PHY: Can't read register value from external PHY.\n");
4772         }
4773
4774 phy_read_end:
4775         return status;
4776 }
4777
4778 /**
4779  * i40e_write_phy_register_clause45
4780  * @hw: pointer to the HW structure
4781  * @page: registers page number
4782  * @reg: register address in the page
4783  * @phy_addr: PHY address on MDIO interface
4784  * @value: PHY register value
4785  *
4786  * Writes value to specified PHY register
4787  **/
4788 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
4789                                 u8 page, u16 reg, u8 phy_addr, u16 value)
4790 {
4791         i40e_status status = I40E_ERR_TIMEOUT;
4792         u32 command = 0;
4793         u16 retry = 1000;
4794         u8 port_num = hw->func_caps.mdio_port_num;
4795
4796         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4797                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4798                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4799                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4800                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4801                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4802                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4803         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4804         do {
4805                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4806                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4807                         status = 0;
4808                         break;
4809                 }
4810                 usleep_range(10, 20);
4811                 retry--;
4812         } while (retry);
4813         if (status) {
4814                 i40e_debug(hw, I40E_DEBUG_PHY,
4815                            "PHY: Can't write command to external PHY.\n");
4816                 goto phy_write_end;
4817         }
4818
4819         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4820         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4821
4822         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4823                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4824                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4825                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4826                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4827                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4828         status = I40E_ERR_TIMEOUT;
4829         retry = 1000;
4830         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4831         do {
4832                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4833                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4834                         status = 0;
4835                         break;
4836                 }
4837                 usleep_range(10, 20);
4838                 retry--;
4839         } while (retry);
4840
4841 phy_write_end:
4842         return status;
4843 }
4844
4845 /**
4846  * i40e_write_phy_register
4847  * @hw: pointer to the HW structure
4848  * @page: registers page number
4849  * @reg: register address in the page
4850  * @phy_addr: PHY address on MDIO interface
4851  * @value: PHY register value
4852  *
4853  * Writes value to specified PHY register
4854  **/
4855 i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4856                                     u8 page, u16 reg, u8 phy_addr, u16 value)
4857 {
4858         i40e_status status;
4859
4860         switch (hw->device_id) {
4861         case I40E_DEV_ID_1G_BASE_T_X722:
4862                 status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4863                                                           value);
4864                 break;
4865         case I40E_DEV_ID_10G_BASE_T:
4866         case I40E_DEV_ID_10G_BASE_T4:
4867         case I40E_DEV_ID_10G_BASE_T_X722:
4868         case I40E_DEV_ID_25G_B:
4869         case I40E_DEV_ID_25G_SFP28:
4870                 status = i40e_write_phy_register_clause45(hw, page, reg,
4871                                                           phy_addr, value);
4872                 break;
4873         default:
4874                 status = I40E_ERR_UNKNOWN_PHY;
4875                 break;
4876         }
4877
4878         return status;
4879 }
4880
4881 /**
4882  * i40e_read_phy_register
4883  * @hw: pointer to the HW structure
4884  * @page: registers page number
4885  * @reg: register address in the page
4886  * @phy_addr: PHY address on MDIO interface
4887  * @value: PHY register value
4888  *
4889  * Reads specified PHY register value
4890  **/
4891 i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4892                                    u8 page, u16 reg, u8 phy_addr, u16 *value)
4893 {
4894         i40e_status status;
4895
4896         switch (hw->device_id) {
4897         case I40E_DEV_ID_1G_BASE_T_X722:
4898                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4899                                                          value);
4900                 break;
4901         case I40E_DEV_ID_10G_BASE_T:
4902         case I40E_DEV_ID_10G_BASE_T4:
4903         case I40E_DEV_ID_10G_BASE_T_X722:
4904         case I40E_DEV_ID_25G_B:
4905         case I40E_DEV_ID_25G_SFP28:
4906                 status = i40e_read_phy_register_clause45(hw, page, reg,
4907                                                          phy_addr, value);
4908                 break;
4909         default:
4910                 status = I40E_ERR_UNKNOWN_PHY;
4911                 break;
4912         }
4913
4914         return status;
4915 }
4916
4917 /**
4918  * i40e_get_phy_address
4919  * @hw: pointer to the HW structure
4920  * @dev_num: PHY port num that address we want
4921  *
4922  * Gets PHY address for current port
4923  **/
4924 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4925 {
4926         u8 port_num = hw->func_caps.mdio_port_num;
4927         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4928
4929         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4930 }
4931
4932 /**
4933  * i40e_blink_phy_led
4934  * @hw: pointer to the HW structure
4935  * @time: time how long led will blinks in secs
4936  * @interval: gap between LED on and off in msecs
4937  *
4938  * Blinks PHY link LED
4939  **/
4940 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4941                                     u32 time, u32 interval)
4942 {
4943         i40e_status status = 0;
4944         u32 i;
4945         u16 led_ctl;
4946         u16 gpio_led_port;
4947         u16 led_reg;
4948         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4949         u8 phy_addr = 0;
4950         u8 port_num;
4951
4952         i = rd32(hw, I40E_PFGEN_PORTNUM);
4953         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4954         phy_addr = i40e_get_phy_address(hw, port_num);
4955
4956         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4957              led_addr++) {
4958                 status = i40e_read_phy_register_clause45(hw,
4959                                                          I40E_PHY_COM_REG_PAGE,
4960                                                          led_addr, phy_addr,
4961                                                          &led_reg);
4962                 if (status)
4963                         goto phy_blinking_end;
4964                 led_ctl = led_reg;
4965                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4966                         led_reg = 0;
4967                         status = i40e_write_phy_register_clause45(hw,
4968                                                          I40E_PHY_COM_REG_PAGE,
4969                                                          led_addr, phy_addr,
4970                                                          led_reg);
4971                         if (status)
4972                                 goto phy_blinking_end;
4973                         break;
4974                 }
4975         }
4976
4977         if (time > 0 && interval > 0) {
4978                 for (i = 0; i < time * 1000; i += interval) {
4979                         status = i40e_read_phy_register_clause45(hw,
4980                                                 I40E_PHY_COM_REG_PAGE,
4981                                                 led_addr, phy_addr, &led_reg);
4982                         if (status)
4983                                 goto restore_config;
4984                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
4985                                 led_reg = 0;
4986                         else
4987                                 led_reg = I40E_PHY_LED_MANUAL_ON;
4988                         status = i40e_write_phy_register_clause45(hw,
4989                                                 I40E_PHY_COM_REG_PAGE,
4990                                                 led_addr, phy_addr, led_reg);
4991                         if (status)
4992                                 goto restore_config;
4993                         msleep(interval);
4994                 }
4995         }
4996
4997 restore_config:
4998         status = i40e_write_phy_register_clause45(hw,
4999                                                   I40E_PHY_COM_REG_PAGE,
5000                                                   led_addr, phy_addr, led_ctl);
5001
5002 phy_blinking_end:
5003         return status;
5004 }
5005
5006 /**
5007  * i40e_led_get_reg - read LED register
5008  * @hw: pointer to the HW structure
5009  * @led_addr: LED register address
5010  * @reg_val: read register value
5011  **/
5012 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
5013                                               u32 *reg_val)
5014 {
5015         enum i40e_status_code status;
5016         u8 phy_addr = 0;
5017         u8 port_num;
5018         u32 i;
5019
5020         *reg_val = 0;
5021         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5022                 status =
5023                        i40e_aq_get_phy_register(hw,
5024                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5025                                                 I40E_PHY_COM_REG_PAGE,
5026                                                 I40E_PHY_LED_PROV_REG_1,
5027                                                 reg_val, NULL);
5028         } else {
5029                 i = rd32(hw, I40E_PFGEN_PORTNUM);
5030                 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5031                 phy_addr = i40e_get_phy_address(hw, port_num);
5032                 status = i40e_read_phy_register_clause45(hw,
5033                                                          I40E_PHY_COM_REG_PAGE,
5034                                                          led_addr, phy_addr,
5035                                                          (u16 *)reg_val);
5036         }
5037         return status;
5038 }
5039
5040 /**
5041  * i40e_led_set_reg - write LED register
5042  * @hw: pointer to the HW structure
5043  * @led_addr: LED register address
5044  * @reg_val: register value to write
5045  **/
5046 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
5047                                               u32 reg_val)
5048 {
5049         enum i40e_status_code status;
5050         u8 phy_addr = 0;
5051         u8 port_num;
5052         u32 i;
5053
5054         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5055                 status =
5056                        i40e_aq_set_phy_register(hw,
5057                                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5058                                                 I40E_PHY_COM_REG_PAGE,
5059                                                 I40E_PHY_LED_PROV_REG_1,
5060                                                 reg_val, NULL);
5061         } else {
5062                 i = rd32(hw, I40E_PFGEN_PORTNUM);
5063                 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5064                 phy_addr = i40e_get_phy_address(hw, port_num);
5065                 status = i40e_write_phy_register_clause45(hw,
5066                                                           I40E_PHY_COM_REG_PAGE,
5067                                                           led_addr, phy_addr,
5068                                                           (u16)reg_val);
5069         }
5070
5071         return status;
5072 }
5073
5074 /**
5075  * i40e_led_get_phy - return current on/off mode
5076  * @hw: pointer to the hw struct
5077  * @led_addr: address of led register to use
5078  * @val: original value of register to use
5079  *
5080  **/
5081 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
5082                              u16 *val)
5083 {
5084         i40e_status status = 0;
5085         u16 gpio_led_port;
5086         u8 phy_addr = 0;
5087         u16 reg_val;
5088         u16 temp_addr;
5089         u8 port_num;
5090         u32 i;
5091         u32 reg_val_aq;
5092
5093         if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5094                 status =
5095                       i40e_aq_get_phy_register(hw,
5096                                                I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5097                                                I40E_PHY_COM_REG_PAGE,
5098                                                I40E_PHY_LED_PROV_REG_1,
5099                                                &reg_val_aq, NULL);
5100                 if (status == I40E_SUCCESS)
5101                         *val = (u16)reg_val_aq;
5102                 return status;
5103         }
5104         temp_addr = I40E_PHY_LED_PROV_REG_1;
5105         i = rd32(hw, I40E_PFGEN_PORTNUM);
5106         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5107         phy_addr = i40e_get_phy_address(hw, port_num);
5108
5109         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
5110              temp_addr++) {
5111                 status = i40e_read_phy_register_clause45(hw,
5112                                                          I40E_PHY_COM_REG_PAGE,
5113                                                          temp_addr, phy_addr,
5114                                                          &reg_val);
5115                 if (status)
5116                         return status;
5117                 *val = reg_val;
5118                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
5119                         *led_addr = temp_addr;
5120                         break;
5121                 }
5122         }
5123         return status;
5124 }
5125
5126 /**
5127  * i40e_led_set_phy
5128  * @hw: pointer to the HW structure
5129  * @on: true or false
5130  * @led_addr: address of led register to use
5131  * @mode: original val plus bit for set or ignore
5132  *
5133  * Set led's on or off when controlled by the PHY
5134  *
5135  **/
5136 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
5137                              u16 led_addr, u32 mode)
5138 {
5139         i40e_status status = 0;
5140         u32 led_ctl = 0;
5141         u32 led_reg = 0;
5142
5143         status = i40e_led_get_reg(hw, led_addr, &led_reg);
5144         if (status)
5145                 return status;
5146         led_ctl = led_reg;
5147         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
5148                 led_reg = 0;
5149                 status = i40e_led_set_reg(hw, led_addr, led_reg);
5150                 if (status)
5151                         return status;
5152         }
5153         status = i40e_led_get_reg(hw, led_addr, &led_reg);
5154         if (status)
5155                 goto restore_config;
5156         if (on)
5157                 led_reg = I40E_PHY_LED_MANUAL_ON;
5158         else
5159                 led_reg = 0;
5160
5161         status = i40e_led_set_reg(hw, led_addr, led_reg);
5162         if (status)
5163                 goto restore_config;
5164         if (mode & I40E_PHY_LED_MODE_ORIG) {
5165                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
5166                 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5167         }
5168         return status;
5169
5170 restore_config:
5171         status = i40e_led_set_reg(hw, led_addr, led_ctl);
5172         return status;
5173 }
5174
5175 /**
5176  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
5177  * @hw: pointer to the hw struct
5178  * @reg_addr: register address
5179  * @reg_val: ptr to register value
5180  * @cmd_details: pointer to command details structure or NULL
5181  *
5182  * Use the firmware to read the Rx control register,
5183  * especially useful if the Rx unit is under heavy pressure
5184  **/
5185 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
5186                                 u32 reg_addr, u32 *reg_val,
5187                                 struct i40e_asq_cmd_details *cmd_details)
5188 {
5189         struct i40e_aq_desc desc;
5190         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
5191                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5192         i40e_status status;
5193
5194         if (!reg_val)
5195                 return I40E_ERR_PARAM;
5196
5197         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
5198
5199         cmd_resp->address = cpu_to_le32(reg_addr);
5200
5201         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5202
5203         if (status == 0)
5204                 *reg_val = le32_to_cpu(cmd_resp->value);
5205
5206         return status;
5207 }
5208
5209 /**
5210  * i40e_read_rx_ctl - read from an Rx control register
5211  * @hw: pointer to the hw struct
5212  * @reg_addr: register address
5213  **/
5214 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
5215 {
5216         i40e_status status = 0;
5217         bool use_register;
5218         int retry = 5;
5219         u32 val = 0;
5220
5221         use_register = (((hw->aq.api_maj_ver == 1) &&
5222                         (hw->aq.api_min_ver < 5)) ||
5223                         (hw->mac.type == I40E_MAC_X722));
5224         if (!use_register) {
5225 do_retry:
5226                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
5227                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5228                         usleep_range(1000, 2000);
5229                         retry--;
5230                         goto do_retry;
5231                 }
5232         }
5233
5234         /* if the AQ access failed, try the old-fashioned way */
5235         if (status || use_register)
5236                 val = rd32(hw, reg_addr);
5237
5238         return val;
5239 }
5240
5241 /**
5242  * i40e_aq_rx_ctl_write_register
5243  * @hw: pointer to the hw struct
5244  * @reg_addr: register address
5245  * @reg_val: register value
5246  * @cmd_details: pointer to command details structure or NULL
5247  *
5248  * Use the firmware to write to an Rx control register,
5249  * especially useful if the Rx unit is under heavy pressure
5250  **/
5251 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
5252                                 u32 reg_addr, u32 reg_val,
5253                                 struct i40e_asq_cmd_details *cmd_details)
5254 {
5255         struct i40e_aq_desc desc;
5256         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
5257                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5258         i40e_status status;
5259
5260         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
5261
5262         cmd->address = cpu_to_le32(reg_addr);
5263         cmd->value = cpu_to_le32(reg_val);
5264
5265         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5266
5267         return status;
5268 }
5269
5270 /**
5271  * i40e_write_rx_ctl - write to an Rx control register
5272  * @hw: pointer to the hw struct
5273  * @reg_addr: register address
5274  * @reg_val: register value
5275  **/
5276 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5277 {
5278         i40e_status status = 0;
5279         bool use_register;
5280         int retry = 5;
5281
5282         use_register = (((hw->aq.api_maj_ver == 1) &&
5283                         (hw->aq.api_min_ver < 5)) ||
5284                         (hw->mac.type == I40E_MAC_X722));
5285         if (!use_register) {
5286 do_retry:
5287                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5288                                                        reg_val, NULL);
5289                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5290                         usleep_range(1000, 2000);
5291                         retry--;
5292                         goto do_retry;
5293                 }
5294         }
5295
5296         /* if the AQ access failed, try the old-fashioned way */
5297         if (status || use_register)
5298                 wr32(hw, reg_addr, reg_val);
5299 }
5300
5301 /**
5302  * i40e_aq_set_phy_register
5303  * @hw: pointer to the hw struct
5304  * @phy_select: select which phy should be accessed
5305  * @dev_addr: PHY device address
5306  * @reg_addr: PHY register address
5307  * @reg_val: new register value
5308  * @cmd_details: pointer to command details structure or NULL
5309  *
5310  * Write the external PHY register.
5311  **/
5312 i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw,
5313                                      u8 phy_select, u8 dev_addr,
5314                                      u32 reg_addr, u32 reg_val,
5315                                      struct i40e_asq_cmd_details *cmd_details)
5316 {
5317         struct i40e_aq_desc desc;
5318         struct i40e_aqc_phy_register_access *cmd =
5319                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5320         i40e_status status;
5321
5322         i40e_fill_default_direct_cmd_desc(&desc,
5323                                           i40e_aqc_opc_set_phy_register);
5324
5325         cmd->phy_interface = phy_select;
5326         cmd->dev_address = dev_addr;
5327         cmd->reg_address = cpu_to_le32(reg_addr);
5328         cmd->reg_value = cpu_to_le32(reg_val);
5329
5330         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5331
5332         return status;
5333 }
5334
5335 /**
5336  * i40e_aq_get_phy_register
5337  * @hw: pointer to the hw struct
5338  * @phy_select: select which phy should be accessed
5339  * @dev_addr: PHY device address
5340  * @reg_addr: PHY register address
5341  * @reg_val: read register value
5342  * @cmd_details: pointer to command details structure or NULL
5343  *
5344  * Read the external PHY register.
5345  **/
5346 i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw,
5347                                      u8 phy_select, u8 dev_addr,
5348                                      u32 reg_addr, u32 *reg_val,
5349                                      struct i40e_asq_cmd_details *cmd_details)
5350 {
5351         struct i40e_aq_desc desc;
5352         struct i40e_aqc_phy_register_access *cmd =
5353                 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5354         i40e_status status;
5355
5356         i40e_fill_default_direct_cmd_desc(&desc,
5357                                           i40e_aqc_opc_get_phy_register);
5358
5359         cmd->phy_interface = phy_select;
5360         cmd->dev_address = dev_addr;
5361         cmd->reg_address = cpu_to_le32(reg_addr);
5362
5363         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5364         if (!status)
5365                 *reg_val = le32_to_cpu(cmd->reg_value);
5366
5367         return status;
5368 }
5369
5370 /**
5371  * i40e_aq_write_ddp - Write dynamic device personalization (ddp)
5372  * @hw: pointer to the hw struct
5373  * @buff: command buffer (size in bytes = buff_size)
5374  * @buff_size: buffer size in bytes
5375  * @track_id: package tracking id
5376  * @error_offset: returns error offset
5377  * @error_info: returns error information
5378  * @cmd_details: pointer to command details structure or NULL
5379  **/
5380 enum
5381 i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
5382                                    u16 buff_size, u32 track_id,
5383                                    u32 *error_offset, u32 *error_info,
5384                                    struct i40e_asq_cmd_details *cmd_details)
5385 {
5386         struct i40e_aq_desc desc;
5387         struct i40e_aqc_write_personalization_profile *cmd =
5388                 (struct i40e_aqc_write_personalization_profile *)
5389                 &desc.params.raw;
5390         struct i40e_aqc_write_ddp_resp *resp;
5391         i40e_status status;
5392
5393         i40e_fill_default_direct_cmd_desc(&desc,
5394                                           i40e_aqc_opc_write_personalization_profile);
5395
5396         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5397         if (buff_size > I40E_AQ_LARGE_BUF)
5398                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5399
5400         desc.datalen = cpu_to_le16(buff_size);
5401
5402         cmd->profile_track_id = cpu_to_le32(track_id);
5403
5404         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5405         if (!status) {
5406                 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
5407                 if (error_offset)
5408                         *error_offset = le32_to_cpu(resp->error_offset);
5409                 if (error_info)
5410                         *error_info = le32_to_cpu(resp->error_info);
5411         }
5412
5413         return status;
5414 }
5415
5416 /**
5417  * i40e_aq_get_ddp_list - Read dynamic device personalization (ddp)
5418  * @hw: pointer to the hw struct
5419  * @buff: command buffer (size in bytes = buff_size)
5420  * @buff_size: buffer size in bytes
5421  * @flags: AdminQ command flags
5422  * @cmd_details: pointer to command details structure or NULL
5423  **/
5424 enum
5425 i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
5426                                       u16 buff_size, u8 flags,
5427                                       struct i40e_asq_cmd_details *cmd_details)
5428 {
5429         struct i40e_aq_desc desc;
5430         struct i40e_aqc_get_applied_profiles *cmd =
5431                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5432         i40e_status status;
5433
5434         i40e_fill_default_direct_cmd_desc(&desc,
5435                                           i40e_aqc_opc_get_personalization_profile_list);
5436
5437         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5438         if (buff_size > I40E_AQ_LARGE_BUF)
5439                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5440         desc.datalen = cpu_to_le16(buff_size);
5441
5442         cmd->flags = flags;
5443
5444         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5445
5446         return status;
5447 }
5448
5449 /**
5450  * i40e_find_segment_in_package
5451  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
5452  * @pkg_hdr: pointer to the package header to be searched
5453  *
5454  * This function searches a package file for a particular segment type. On
5455  * success it returns a pointer to the segment header, otherwise it will
5456  * return NULL.
5457  **/
5458 struct i40e_generic_seg_header *
5459 i40e_find_segment_in_package(u32 segment_type,
5460                              struct i40e_package_header *pkg_hdr)
5461 {
5462         struct i40e_generic_seg_header *segment;
5463         u32 i;
5464
5465         /* Search all package segments for the requested segment type */
5466         for (i = 0; i < pkg_hdr->segment_count; i++) {
5467                 segment =
5468                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5469                          pkg_hdr->segment_offset[i]);
5470
5471                 if (segment->type == segment_type)
5472                         return segment;
5473         }
5474
5475         return NULL;
5476 }
5477
5478 /**
5479  * i40e_write_profile
5480  * @hw: pointer to the hardware structure
5481  * @profile: pointer to the profile segment of the package to be downloaded
5482  * @track_id: package tracking id
5483  *
5484  * Handles the download of a complete package.
5485  */
5486 enum i40e_status_code
5487 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5488                    u32 track_id)
5489 {
5490         i40e_status status = 0;
5491         struct i40e_section_table *sec_tbl;
5492         struct i40e_profile_section_header *sec = NULL;
5493         u32 dev_cnt;
5494         u32 vendor_dev_id;
5495         u32 *nvm;
5496         u32 section_size = 0;
5497         u32 offset = 0, info = 0;
5498         u32 i;
5499
5500         dev_cnt = profile->device_table_count;
5501
5502         for (i = 0; i < dev_cnt; i++) {
5503                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
5504                 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL)
5505                         if (hw->device_id == (vendor_dev_id & 0xFFFF))
5506                                 break;
5507         }
5508         if (i == dev_cnt) {
5509                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
5510                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5511         }
5512
5513         nvm = (u32 *)&profile->device_table[dev_cnt];
5514         sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
5515
5516         for (i = 0; i < sec_tbl->section_count; i++) {
5517                 sec = (struct i40e_profile_section_header *)((u8 *)profile +
5518                                              sec_tbl->section_offset[i]);
5519
5520                 /* Skip 'AQ', 'note' and 'name' sections */
5521                 if (sec->section.type != SECTION_TYPE_MMIO)
5522                         continue;
5523
5524                 section_size = sec->section.size +
5525                         sizeof(struct i40e_profile_section_header);
5526
5527                 /* Write profile */
5528                 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5529                                            track_id, &offset, &info, NULL);
5530                 if (status) {
5531                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
5532                                    "Failed to write profile: offset %d, info %d",
5533                                    offset, info);
5534                         break;
5535                 }
5536         }
5537         return status;
5538 }
5539
5540 /**
5541  * i40e_add_pinfo_to_list
5542  * @hw: pointer to the hardware structure
5543  * @profile: pointer to the profile segment of the package
5544  * @profile_info_sec: buffer for information section
5545  * @track_id: package tracking id
5546  *
5547  * Register a profile to the list of loaded profiles.
5548  */
5549 enum i40e_status_code
5550 i40e_add_pinfo_to_list(struct i40e_hw *hw,
5551                        struct i40e_profile_segment *profile,
5552                        u8 *profile_info_sec, u32 track_id)
5553 {
5554         i40e_status status = 0;
5555         struct i40e_profile_section_header *sec = NULL;
5556         struct i40e_profile_info *pinfo;
5557         u32 offset = 0, info = 0;
5558
5559         sec = (struct i40e_profile_section_header *)profile_info_sec;
5560         sec->tbl_size = 1;
5561         sec->data_end = sizeof(struct i40e_profile_section_header) +
5562                         sizeof(struct i40e_profile_info);
5563         sec->section.type = SECTION_TYPE_INFO;
5564         sec->section.offset = sizeof(struct i40e_profile_section_header);
5565         sec->section.size = sizeof(struct i40e_profile_info);
5566         pinfo = (struct i40e_profile_info *)(profile_info_sec +
5567                                              sec->section.offset);
5568         pinfo->track_id = track_id;
5569         pinfo->version = profile->version;
5570         pinfo->op = I40E_DDP_ADD_TRACKID;
5571         memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
5572
5573         status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
5574                                    track_id, &offset, &info, NULL);
5575
5576         return status;
5577 }
5578
5579 /**
5580  * i40e_aq_add_cloud_filters
5581  * @hw: pointer to the hardware structure
5582  * @seid: VSI seid to add cloud filters from
5583  * @filters: Buffer which contains the filters to be added
5584  * @filter_count: number of filters contained in the buffer
5585  *
5586  * Set the cloud filters for a given VSI.  The contents of the
5587  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5588  * of the function.
5589  *
5590  **/
5591 enum i40e_status_code
5592 i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,
5593                           struct i40e_aqc_cloud_filters_element_data *filters,
5594                           u8 filter_count)
5595 {
5596         struct i40e_aq_desc desc;
5597         struct i40e_aqc_add_remove_cloud_filters *cmd =
5598         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5599         enum i40e_status_code status;
5600         u16 buff_len;
5601
5602         i40e_fill_default_direct_cmd_desc(&desc,
5603                                           i40e_aqc_opc_add_cloud_filters);
5604
5605         buff_len = filter_count * sizeof(*filters);
5606         desc.datalen = cpu_to_le16(buff_len);
5607         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5608         cmd->num_filters = filter_count;
5609         cmd->seid = cpu_to_le16(seid);
5610
5611         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5612
5613         return status;
5614 }
5615
5616 /**
5617  * i40e_aq_add_cloud_filters_bb
5618  * @hw: pointer to the hardware structure
5619  * @seid: VSI seid to add cloud filters from
5620  * @filters: Buffer which contains the filters in big buffer to be added
5621  * @filter_count: number of filters contained in the buffer
5622  *
5623  * Set the big buffer cloud filters for a given VSI.  The contents of the
5624  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5625  * function.
5626  *
5627  **/
5628 enum i40e_status_code
5629 i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5630                              struct i40e_aqc_cloud_filters_element_bb *filters,
5631                              u8 filter_count)
5632 {
5633         struct i40e_aq_desc desc;
5634         struct i40e_aqc_add_remove_cloud_filters *cmd =
5635         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5636         i40e_status status;
5637         u16 buff_len;
5638         int i;
5639
5640         i40e_fill_default_direct_cmd_desc(&desc,
5641                                           i40e_aqc_opc_add_cloud_filters);
5642
5643         buff_len = filter_count * sizeof(*filters);
5644         desc.datalen = cpu_to_le16(buff_len);
5645         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5646         cmd->num_filters = filter_count;
5647         cmd->seid = cpu_to_le16(seid);
5648         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5649
5650         for (i = 0; i < filter_count; i++) {
5651                 u16 tnl_type;
5652                 u32 ti;
5653
5654                 tnl_type = (le16_to_cpu(filters[i].element.flags) &
5655                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5656                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5657
5658                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5659                  * one more byte further than normally used for Tenant ID in
5660                  * other tunnel types.
5661                  */
5662                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5663                         ti = le32_to_cpu(filters[i].element.tenant_id);
5664                         filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5665                 }
5666         }
5667
5668         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5669
5670         return status;
5671 }
5672
5673 /**
5674  * i40e_aq_rem_cloud_filters
5675  * @hw: pointer to the hardware structure
5676  * @seid: VSI seid to remove cloud filters from
5677  * @filters: Buffer which contains the filters to be removed
5678  * @filter_count: number of filters contained in the buffer
5679  *
5680  * Remove the cloud filters for a given VSI.  The contents of the
5681  * i40e_aqc_cloud_filters_element_data are filled in by the caller
5682  * of the function.
5683  *
5684  **/
5685 enum i40e_status_code
5686 i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5687                           struct i40e_aqc_cloud_filters_element_data *filters,
5688                           u8 filter_count)
5689 {
5690         struct i40e_aq_desc desc;
5691         struct i40e_aqc_add_remove_cloud_filters *cmd =
5692         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5693         enum i40e_status_code status;
5694         u16 buff_len;
5695
5696         i40e_fill_default_direct_cmd_desc(&desc,
5697                                           i40e_aqc_opc_remove_cloud_filters);
5698
5699         buff_len = filter_count * sizeof(*filters);
5700         desc.datalen = cpu_to_le16(buff_len);
5701         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5702         cmd->num_filters = filter_count;
5703         cmd->seid = cpu_to_le16(seid);
5704
5705         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5706
5707         return status;
5708 }
5709
5710 /**
5711  * i40e_aq_rem_cloud_filters_bb
5712  * @hw: pointer to the hardware structure
5713  * @seid: VSI seid to remove cloud filters from
5714  * @filters: Buffer which contains the filters in big buffer to be removed
5715  * @filter_count: number of filters contained in the buffer
5716  *
5717  * Remove the big buffer cloud filters for a given VSI.  The contents of the
5718  * i40e_aqc_cloud_filters_element_bb are filled in by the caller of the
5719  * function.
5720  *
5721  **/
5722 enum i40e_status_code
5723 i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5724                              struct i40e_aqc_cloud_filters_element_bb *filters,
5725                              u8 filter_count)
5726 {
5727         struct i40e_aq_desc desc;
5728         struct i40e_aqc_add_remove_cloud_filters *cmd =
5729         (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5730         i40e_status status;
5731         u16 buff_len;
5732         int i;
5733
5734         i40e_fill_default_direct_cmd_desc(&desc,
5735                                           i40e_aqc_opc_remove_cloud_filters);
5736
5737         buff_len = filter_count * sizeof(*filters);
5738         desc.datalen = cpu_to_le16(buff_len);
5739         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5740         cmd->num_filters = filter_count;
5741         cmd->seid = cpu_to_le16(seid);
5742         cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5743
5744         for (i = 0; i < filter_count; i++) {
5745                 u16 tnl_type;
5746                 u32 ti;
5747
5748                 tnl_type = (le16_to_cpu(filters[i].element.flags) &
5749                            I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5750                            I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5751
5752                 /* Due to hardware eccentricities, the VNI for Geneve is shifted
5753                  * one more byte further than normally used for Tenant ID in
5754                  * other tunnel types.
5755                  */
5756                 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5757                         ti = le32_to_cpu(filters[i].element.tenant_id);
5758                         filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5759                 }
5760         }
5761
5762         status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5763
5764         return status;
5765 }