drivers/net/ethernet/intel/i40e/i40e_common.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2016 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include "i40e_type.h"
  28 #include "i40e_adminq.h"
  29 #include "i40e_prototype.h"
  30 #include <linux/avf/virtchnl.h>
  31
  32 /**
  33  * i40e_set_mac_type - Sets MAC type
  34  * @hw: pointer to the HW structure
  35  *
  36  * This function sets the mac type of the adapter based on the
  37  * vendor ID and device ID stored in the hw structure.
  38  **/
  39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
  40 {
  41         i40e_status status = 0;
  42
  43         if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
  44                 switch (hw->device_id) {
  45                 case I40E_DEV_ID_SFP_XL710:
  46                 case I40E_DEV_ID_QEMU:
  47                 case I40E_DEV_ID_KX_B:
  48                 case I40E_DEV_ID_KX_C:
  49                 case I40E_DEV_ID_QSFP_A:
  50                 case I40E_DEV_ID_QSFP_B:
  51                 case I40E_DEV_ID_QSFP_C:
  52                 case I40E_DEV_ID_10G_BASE_T:
  53                 case I40E_DEV_ID_10G_BASE_T4:
  54                 case I40E_DEV_ID_20G_KR2:
  55                 case I40E_DEV_ID_20G_KR2_A:
  56                 case I40E_DEV_ID_25G_B:
  57                 case I40E_DEV_ID_25G_SFP28:
  58                         hw->mac.type = I40E_MAC_XL710;
  59                         break;
  60                 case I40E_DEV_ID_KX_X722:
  61                 case I40E_DEV_ID_QSFP_X722:
  62                 case I40E_DEV_ID_SFP_X722:
  63                 case I40E_DEV_ID_1G_BASE_T_X722:
  64                 case I40E_DEV_ID_10G_BASE_T_X722:
  65                 case I40E_DEV_ID_SFP_I_X722:
  66                         hw->mac.type = I40E_MAC_X722;
  67                         break;
  68                 default:
  69                         hw->mac.type = I40E_MAC_GENERIC;
  70                         break;
  71                 }
  72         } else {
  73                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  74         }
  75
  76         hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
  77                   hw->mac.type, status);
  78         return status;
  79 }
  80
  81 /**
  82  * i40e_aq_str - convert AQ err code to a string
  83  * @hw: pointer to the HW structure
  84  * @aq_err: the AQ error code to convert
  85  **/
  86 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  87 {
  88         switch (aq_err) {
  89         case I40E_AQ_RC_OK:
  90                 return "OK";
  91         case I40E_AQ_RC_EPERM:
  92                 return "I40E_AQ_RC_EPERM";
  93         case I40E_AQ_RC_ENOENT:
  94                 return "I40E_AQ_RC_ENOENT";
  95         case I40E_AQ_RC_ESRCH:
  96                 return "I40E_AQ_RC_ESRCH";
  97         case I40E_AQ_RC_EINTR:
  98                 return "I40E_AQ_RC_EINTR";
  99         case I40E_AQ_RC_EIO:
 100                 return "I40E_AQ_RC_EIO";
 101         case I40E_AQ_RC_ENXIO:
 102                 return "I40E_AQ_RC_ENXIO";
 103         case I40E_AQ_RC_E2BIG:
 104                 return "I40E_AQ_RC_E2BIG";
 105         case I40E_AQ_RC_EAGAIN:
 106                 return "I40E_AQ_RC_EAGAIN";
 107         case I40E_AQ_RC_ENOMEM:
 108                 return "I40E_AQ_RC_ENOMEM";
 109         case I40E_AQ_RC_EACCES:
 110                 return "I40E_AQ_RC_EACCES";
 111         case I40E_AQ_RC_EFAULT:
 112                 return "I40E_AQ_RC_EFAULT";
 113         case I40E_AQ_RC_EBUSY:
 114                 return "I40E_AQ_RC_EBUSY";
 115         case I40E_AQ_RC_EEXIST:
 116                 return "I40E_AQ_RC_EEXIST";
 117         case I40E_AQ_RC_EINVAL:
 118                 return "I40E_AQ_RC_EINVAL";
 119         case I40E_AQ_RC_ENOTTY:
 120                 return "I40E_AQ_RC_ENOTTY";
 121         case I40E_AQ_RC_ENOSPC:
 122                 return "I40E_AQ_RC_ENOSPC";
 123         case I40E_AQ_RC_ENOSYS:
 124                 return "I40E_AQ_RC_ENOSYS";
 125         case I40E_AQ_RC_ERANGE:
 126                 return "I40E_AQ_RC_ERANGE";
 127         case I40E_AQ_RC_EFLUSHED:
 128                 return "I40E_AQ_RC_EFLUSHED";
 129         case I40E_AQ_RC_BAD_ADDR:
 130                 return "I40E_AQ_RC_BAD_ADDR";
 131         case I40E_AQ_RC_EMODE:
 132                 return "I40E_AQ_RC_EMODE";
 133         case I40E_AQ_RC_EFBIG:
 134                 return "I40E_AQ_RC_EFBIG";
 135         }
 136
 137         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 138         return hw->err_str;
 139 }
 140
 141 /**
 142  * i40e_stat_str - convert status err code to a string
 143  * @hw: pointer to the HW structure
 144  * @stat_err: the status error code to convert
 145  **/
 146 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
 147 {
 148         switch (stat_err) {
 149         case 0:
 150                 return "OK";
 151         case I40E_ERR_NVM:
 152                 return "I40E_ERR_NVM";
 153         case I40E_ERR_NVM_CHECKSUM:
 154                 return "I40E_ERR_NVM_CHECKSUM";
 155         case I40E_ERR_PHY:
 156                 return "I40E_ERR_PHY";
 157         case I40E_ERR_CONFIG:
 158                 return "I40E_ERR_CONFIG";
 159         case I40E_ERR_PARAM:
 160                 return "I40E_ERR_PARAM";
 161         case I40E_ERR_MAC_TYPE:
 162                 return "I40E_ERR_MAC_TYPE";
 163         case I40E_ERR_UNKNOWN_PHY:
 164                 return "I40E_ERR_UNKNOWN_PHY";
 165         case I40E_ERR_LINK_SETUP:
 166                 return "I40E_ERR_LINK_SETUP";
 167         case I40E_ERR_ADAPTER_STOPPED:
 168                 return "I40E_ERR_ADAPTER_STOPPED";
 169         case I40E_ERR_INVALID_MAC_ADDR:
 170                 return "I40E_ERR_INVALID_MAC_ADDR";
 171         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 172                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 173         case I40E_ERR_MASTER_REQUESTS_PENDING:
 174                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 175         case I40E_ERR_INVALID_LINK_SETTINGS:
 176                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 177         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 178                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 179         case I40E_ERR_RESET_FAILED:
 180                 return "I40E_ERR_RESET_FAILED";
 181         case I40E_ERR_SWFW_SYNC:
 182                 return "I40E_ERR_SWFW_SYNC";
 183         case I40E_ERR_NO_AVAILABLE_VSI:
 184                 return "I40E_ERR_NO_AVAILABLE_VSI";
 185         case I40E_ERR_NO_MEMORY:
 186                 return "I40E_ERR_NO_MEMORY";
 187         case I40E_ERR_BAD_PTR:
 188                 return "I40E_ERR_BAD_PTR";
 189         case I40E_ERR_RING_FULL:
 190                 return "I40E_ERR_RING_FULL";
 191         case I40E_ERR_INVALID_PD_ID:
 192                 return "I40E_ERR_INVALID_PD_ID";
 193         case I40E_ERR_INVALID_QP_ID:
 194                 return "I40E_ERR_INVALID_QP_ID";
 195         case I40E_ERR_INVALID_CQ_ID:
 196                 return "I40E_ERR_INVALID_CQ_ID";
 197         case I40E_ERR_INVALID_CEQ_ID:
 198                 return "I40E_ERR_INVALID_CEQ_ID";
 199         case I40E_ERR_INVALID_AEQ_ID:
 200                 return "I40E_ERR_INVALID_AEQ_ID";
 201         case I40E_ERR_INVALID_SIZE:
 202                 return "I40E_ERR_INVALID_SIZE";
 203         case I40E_ERR_INVALID_ARP_INDEX:
 204                 return "I40E_ERR_INVALID_ARP_INDEX";
 205         case I40E_ERR_INVALID_FPM_FUNC_ID:
 206                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 207         case I40E_ERR_QP_INVALID_MSG_SIZE:
 208                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 209         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 210                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 211         case I40E_ERR_INVALID_FRAG_COUNT:
 212                 return "I40E_ERR_INVALID_FRAG_COUNT";
 213         case I40E_ERR_QUEUE_EMPTY:
 214                 return "I40E_ERR_QUEUE_EMPTY";
 215         case I40E_ERR_INVALID_ALIGNMENT:
 216                 return "I40E_ERR_INVALID_ALIGNMENT";
 217         case I40E_ERR_FLUSHED_QUEUE:
 218                 return "I40E_ERR_FLUSHED_QUEUE";
 219         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 220                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 221         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 222                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 223         case I40E_ERR_TIMEOUT:
 224                 return "I40E_ERR_TIMEOUT";
 225         case I40E_ERR_OPCODE_MISMATCH:
 226                 return "I40E_ERR_OPCODE_MISMATCH";
 227         case I40E_ERR_CQP_COMPL_ERROR:
 228                 return "I40E_ERR_CQP_COMPL_ERROR";
 229         case I40E_ERR_INVALID_VF_ID:
 230                 return "I40E_ERR_INVALID_VF_ID";
 231         case I40E_ERR_INVALID_HMCFN_ID:
 232                 return "I40E_ERR_INVALID_HMCFN_ID";
 233         case I40E_ERR_BACKING_PAGE_ERROR:
 234                 return "I40E_ERR_BACKING_PAGE_ERROR";
 235         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 236                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 237         case I40E_ERR_INVALID_PBLE_INDEX:
 238                 return "I40E_ERR_INVALID_PBLE_INDEX";
 239         case I40E_ERR_INVALID_SD_INDEX:
 240                 return "I40E_ERR_INVALID_SD_INDEX";
 241         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 242                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 243         case I40E_ERR_INVALID_SD_TYPE:
 244                 return "I40E_ERR_INVALID_SD_TYPE";
 245         case I40E_ERR_MEMCPY_FAILED:
 246                 return "I40E_ERR_MEMCPY_FAILED";
 247         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 248                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 249         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 250                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 251         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 252                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 253         case I40E_ERR_SRQ_ENABLED:
 254                 return "I40E_ERR_SRQ_ENABLED";
 255         case I40E_ERR_ADMIN_QUEUE_ERROR:
 256                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 257         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 258                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 259         case I40E_ERR_BUF_TOO_SHORT:
 260                 return "I40E_ERR_BUF_TOO_SHORT";
 261         case I40E_ERR_ADMIN_QUEUE_FULL:
 262                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 263         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 264                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 265         case I40E_ERR_BAD_IWARP_CQE:
 266                 return "I40E_ERR_BAD_IWARP_CQE";
 267         case I40E_ERR_NVM_BLANK_MODE:
 268                 return "I40E_ERR_NVM_BLANK_MODE";
 269         case I40E_ERR_NOT_IMPLEMENTED:
 270                 return "I40E_ERR_NOT_IMPLEMENTED";
 271         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 272                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 273         case I40E_ERR_DIAG_TEST_FAILED:
 274                 return "I40E_ERR_DIAG_TEST_FAILED";
 275         case I40E_ERR_NOT_READY:
 276                 return "I40E_ERR_NOT_READY";
 277         case I40E_NOT_SUPPORTED:
 278                 return "I40E_NOT_SUPPORTED";
 279         case I40E_ERR_FIRMWARE_API_VERSION:
 280                 return "I40E_ERR_FIRMWARE_API_VERSION";
 281         }
 282
 283         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 284         return hw->err_str;
 285 }
 286
 287 /**
 288  * i40e_debug_aq
 289  * @hw: debug mask related to admin queue
 290  * @mask: debug mask
 291  * @desc: pointer to admin queue descriptor
 292  * @buffer: pointer to command buffer
 293  * @buf_len: max length of buffer
 294  *
 295  * Dumps debug log about adminq command with descriptor contents.
 296  **/
 297 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 298                    void *buffer, u16 buf_len)
 299 {
 300         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 301         u16 len;
 302         u8 *buf = (u8 *)buffer;
 303
 304         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 305                 return;
 306
 307         len = le16_to_cpu(aq_desc->datalen);
 308
 309         i40e_debug(hw, mask,
 310                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 311                    le16_to_cpu(aq_desc->opcode),
 312                    le16_to_cpu(aq_desc->flags),
 313                    le16_to_cpu(aq_desc->datalen),
 314                    le16_to_cpu(aq_desc->retval));
 315         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 316                    le32_to_cpu(aq_desc->cookie_high),
 317                    le32_to_cpu(aq_desc->cookie_low));
 318         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 319                    le32_to_cpu(aq_desc->params.internal.param0),
 320                    le32_to_cpu(aq_desc->params.internal.param1));
 321         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 322                    le32_to_cpu(aq_desc->params.external.addr_high),
 323                    le32_to_cpu(aq_desc->params.external.addr_low));
 324
 325         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 326                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 327                 if (buf_len < len)
 328                         len = buf_len;
 329                 /* write the full 16-byte chunks */
 330                 if (hw->debug_mask & mask) {
 331                         char prefix[27];
 332
 333                         snprintf(prefix, sizeof(prefix),
 334                                  "i40e %02x:%02x.%x: \t0x",
 335                                  hw->bus.bus_id,
 336                                  hw->bus.device,
 337                                  hw->bus.func);
 338
 339                         print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
 340                                        16, 1, buf, len, false);
 341                 }
 342         }
 343 }
 344
 345 /**
 346  * i40e_check_asq_alive
 347  * @hw: pointer to the hw struct
 348  *
 349  * Returns true if Queue is enabled else false.
 350  **/
 351 bool i40e_check_asq_alive(struct i40e_hw *hw)
 352 {
 353         if (hw->aq.asq.len)
 354                 return !!(rd32(hw, hw->aq.asq.len) &
 355                           I40E_PF_ATQLEN_ATQENABLE_MASK);
 356         else
 357                 return false;
 358 }
 359
 360 /**
 361  * i40e_aq_queue_shutdown
 362  * @hw: pointer to the hw struct
 363  * @unloading: is the driver unloading itself
 364  *
 365  * Tell the Firmware that we're shutting down the AdminQ and whether
 366  * or not the driver is unloading as well.
 367  **/
 368 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
 369                                              bool unloading)
 370 {
 371         struct i40e_aq_desc desc;
 372         struct i40e_aqc_queue_shutdown *cmd =
 373                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 374         i40e_status status;
 375
 376         i40e_fill_default_direct_cmd_desc(&desc,
 377                                           i40e_aqc_opc_queue_shutdown);
 378
 379         if (unloading)
 380                 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
 381         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 382
 383         return status;
 384 }
 385
 386 /**
 387  * i40e_aq_get_set_rss_lut
 388  * @hw: pointer to the hardware structure
 389  * @vsi_id: vsi fw index
 390  * @pf_lut: for PF table set true, for VSI table set false
 391  * @lut: pointer to the lut buffer provided by the caller
 392  * @lut_size: size of the lut buffer
 393  * @set: set true to set the table, false to get the table
 394  *
 395  * Internal function to get or set RSS look up table
 396  **/
 397 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 398                                            u16 vsi_id, bool pf_lut,
 399                                            u8 *lut, u16 lut_size,
 400                                            bool set)
 401 {
 402         i40e_status status;
 403         struct i40e_aq_desc desc;
 404         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 405                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 406
 407         if (set)
 408                 i40e_fill_default_direct_cmd_desc(&desc,
 409                                                   i40e_aqc_opc_set_rss_lut);
 410         else
 411                 i40e_fill_default_direct_cmd_desc(&desc,
 412                                                   i40e_aqc_opc_get_rss_lut);
 413
 414         /* Indirect command */
 415         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
 416         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
 417
 418         cmd_resp->vsi_id =
 419                         cpu_to_le16((u16)((vsi_id <<
 420                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 421                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 422         cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 423
 424         if (pf_lut)
 425                 cmd_resp->flags |= cpu_to_le16((u16)
 426                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 427                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 428                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 429         else
 430                 cmd_resp->flags |= cpu_to_le16((u16)
 431                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 432                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 433                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 434
 435         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 436
 437         return status;
 438 }
 439
 440 /**
 441  * i40e_aq_get_rss_lut
 442  * @hw: pointer to the hardware structure
 443  * @vsi_id: vsi fw index
 444  * @pf_lut: for PF table set true, for VSI table set false
 445  * @lut: pointer to the lut buffer provided by the caller
 446  * @lut_size: size of the lut buffer
 447  *
 448  * get the RSS lookup table, PF or VSI type
 449  **/
 450 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 451                                 bool pf_lut, u8 *lut, u16 lut_size)
 452 {
 453         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 454                                        false);
 455 }
 456
 457 /**
 458  * i40e_aq_set_rss_lut
 459  * @hw: pointer to the hardware structure
 460  * @vsi_id: vsi fw index
 461  * @pf_lut: for PF table set true, for VSI table set false
 462  * @lut: pointer to the lut buffer provided by the caller
 463  * @lut_size: size of the lut buffer
 464  *
 465  * set the RSS lookup table, PF or VSI type
 466  **/
 467 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 468                                 bool pf_lut, u8 *lut, u16 lut_size)
 469 {
 470         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 471 }
 472
 473 /**
 474  * i40e_aq_get_set_rss_key
 475  * @hw: pointer to the hw struct
 476  * @vsi_id: vsi fw index
 477  * @key: pointer to key info struct
 478  * @set: set true to set the key, false to get the key
 479  *
 480  * get the RSS key per VSI
 481  **/
 482 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 483                                       u16 vsi_id,
 484                                       struct i40e_aqc_get_set_rss_key_data *key,
 485                                       bool set)
 486 {
 487         i40e_status status;
 488         struct i40e_aq_desc desc;
 489         struct i40e_aqc_get_set_rss_key *cmd_resp =
 490                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 491         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 492
 493         if (set)
 494                 i40e_fill_default_direct_cmd_desc(&desc,
 495                                                   i40e_aqc_opc_set_rss_key);
 496         else
 497                 i40e_fill_default_direct_cmd_desc(&desc,
 498                                                   i40e_aqc_opc_get_rss_key);
 499
 500         /* Indirect command */
 501         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
 502         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
 503
 504         cmd_resp->vsi_id =
 505                         cpu_to_le16((u16)((vsi_id <<
 506                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 507                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 508         cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 509
 510         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 511
 512         return status;
 513 }
 514
 515 /**
 516  * i40e_aq_get_rss_key
 517  * @hw: pointer to the hw struct
 518  * @vsi_id: vsi fw index
 519  * @key: pointer to key info struct
 520  *
 521  **/
 522 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
 523                                 u16 vsi_id,
 524                                 struct i40e_aqc_get_set_rss_key_data *key)
 525 {
 526         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 527 }
 528
 529 /**
 530  * i40e_aq_set_rss_key
 531  * @hw: pointer to the hw struct
 532  * @vsi_id: vsi fw index
 533  * @key: pointer to key info struct
 534  *
 535  * set the RSS key per VSI
 536  **/
 537 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
 538                                 u16 vsi_id,
 539                                 struct i40e_aqc_get_set_rss_key_data *key)
 540 {
 541         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 542 }
 543
 544 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 545  * hardware to a bit-field that can be used by SW to more easily determine the
 546  * packet type.
 547  *
 548  * Macros are used to shorten the table lines and make this table human
 549  * readable.
 550  *
 551  * We store the PTYPE in the top byte of the bit field - this is just so that
 552  * we can check that the table doesn't have a row missing, as the index into
 553  * the table should be the PTYPE.
 554  *
 555  * Typical work flow:
 556  *
 557  * IF NOT i40e_ptype_lookup[ptype].known
 558  * THEN
 559  *      Packet is unknown
 560  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 561  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 562  * ELSE
 563  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 564  * ENDIF
 565  */
 566
 567 /* macro to make the table lines short */
 568 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 569         {       PTYPE, \
 570                 1, \
 571                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 572                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 573                 I40E_RX_PTYPE_##OUTER_FRAG, \
 574                 I40E_RX_PTYPE_TUNNEL_##T, \
 575                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 576                 I40E_RX_PTYPE_##TEF, \
 577                 I40E_RX_PTYPE_INNER_PROT_##I, \
 578                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 579
 580 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 581                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 582
 583 /* shorter macros makes the table fit but are terse */
 584 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 585 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 586 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 587
 588 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 589 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 590         /* L2 Packet types */
 591         I40E_PTT_UNUSED_ENTRY(0),
 592         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 593         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 594         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 595         I40E_PTT_UNUSED_ENTRY(4),
 596         I40E_PTT_UNUSED_ENTRY(5),
 597         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 598         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 599         I40E_PTT_UNUSED_ENTRY(8),
 600         I40E_PTT_UNUSED_ENTRY(9),
 601         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 602         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 603         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 604         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 605         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 606         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 607         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 608         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 609         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 610         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 611         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 612         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 613
 614         /* Non Tunneled IPv4 */
 615         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 616         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 617         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 618         I40E_PTT_UNUSED_ENTRY(25),
 619         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 620         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 621         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 622
 623         /* IPv4 --> IPv4 */
 624         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 625         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 626         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 627         I40E_PTT_UNUSED_ENTRY(32),
 628         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 629         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 630         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 631
 632         /* IPv4 --> IPv6 */
 633         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 634         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 635         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 636         I40E_PTT_UNUSED_ENTRY(39),
 637         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 638         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 639         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 640
 641         /* IPv4 --> GRE/NAT */
 642         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 643
 644         /* IPv4 --> GRE/NAT --> IPv4 */
 645         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 646         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 647         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 648         I40E_PTT_UNUSED_ENTRY(47),
 649         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 650         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 651         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 652
 653         /* IPv4 --> GRE/NAT --> IPv6 */
 654         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 655         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 656         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 657         I40E_PTT_UNUSED_ENTRY(54),
 658         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 659         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 660         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 661
 662         /* IPv4 --> GRE/NAT --> MAC */
 663         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 664
 665         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 666         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 667         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 668         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 669         I40E_PTT_UNUSED_ENTRY(62),
 670         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 671         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 672         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 673
 674         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 675         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 676         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 677         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 678         I40E_PTT_UNUSED_ENTRY(69),
 679         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 680         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 681         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 682
 683         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 684         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 685
 686         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 687         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 688         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 689         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 690         I40E_PTT_UNUSED_ENTRY(77),
 691         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 692         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 693         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 694
 695         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 696         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 697         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 698         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 699         I40E_PTT_UNUSED_ENTRY(84),
 700         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 701         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 702         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 703
 704         /* Non Tunneled IPv6 */
 705         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 706         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 707         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 708         I40E_PTT_UNUSED_ENTRY(91),
 709         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 710         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 711         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 712
 713         /* IPv6 --> IPv4 */
 714         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 715         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 716         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 717         I40E_PTT_UNUSED_ENTRY(98),
 718         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 719         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 720         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 721
 722         /* IPv6 --> IPv6 */
 723         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 724         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 725         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 726         I40E_PTT_UNUSED_ENTRY(105),
 727         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 728         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 729         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 730
 731         /* IPv6 --> GRE/NAT */
 732         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 733
 734         /* IPv6 --> GRE/NAT -> IPv4 */
 735         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 736         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 737         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 738         I40E_PTT_UNUSED_ENTRY(113),
 739         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 740         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 741         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 742
 743         /* IPv6 --> GRE/NAT -> IPv6 */
 744         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 745         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 746         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 747         I40E_PTT_UNUSED_ENTRY(120),
 748         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 749         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 750         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 751
 752         /* IPv6 --> GRE/NAT -> MAC */
 753         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 754
 755         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 756         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 757         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 758         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 759         I40E_PTT_UNUSED_ENTRY(128),
 760         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 761         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 762         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 763
 764         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 765         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 766         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 767         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 768         I40E_PTT_UNUSED_ENTRY(135),
 769         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 770         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 771         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 772
 773         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 774         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 775
 776         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 777         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 778         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 779         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 780         I40E_PTT_UNUSED_ENTRY(143),
 781         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 782         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 783         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 784
 785         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 786         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 787         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 788         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 789         I40E_PTT_UNUSED_ENTRY(150),
 790         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 791         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 792         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 793
 794         /* unused entries */
 795         I40E_PTT_UNUSED_ENTRY(154),
 796         I40E_PTT_UNUSED_ENTRY(155),
 797         I40E_PTT_UNUSED_ENTRY(156),
 798         I40E_PTT_UNUSED_ENTRY(157),
 799         I40E_PTT_UNUSED_ENTRY(158),
 800         I40E_PTT_UNUSED_ENTRY(159),
 801
 802         I40E_PTT_UNUSED_ENTRY(160),
 803         I40E_PTT_UNUSED_ENTRY(161),
 804         I40E_PTT_UNUSED_ENTRY(162),
 805         I40E_PTT_UNUSED_ENTRY(163),
 806         I40E_PTT_UNUSED_ENTRY(164),
 807         I40E_PTT_UNUSED_ENTRY(165),
 808         I40E_PTT_UNUSED_ENTRY(166),
 809         I40E_PTT_UNUSED_ENTRY(167),
 810         I40E_PTT_UNUSED_ENTRY(168),
 811         I40E_PTT_UNUSED_ENTRY(169),
 812
 813         I40E_PTT_UNUSED_ENTRY(170),
 814         I40E_PTT_UNUSED_ENTRY(171),
 815         I40E_PTT_UNUSED_ENTRY(172),
 816         I40E_PTT_UNUSED_ENTRY(173),
 817         I40E_PTT_UNUSED_ENTRY(174),
 818         I40E_PTT_UNUSED_ENTRY(175),
 819         I40E_PTT_UNUSED_ENTRY(176),
 820         I40E_PTT_UNUSED_ENTRY(177),
 821         I40E_PTT_UNUSED_ENTRY(178),
 822         I40E_PTT_UNUSED_ENTRY(179),
 823
 824         I40E_PTT_UNUSED_ENTRY(180),
 825         I40E_PTT_UNUSED_ENTRY(181),
 826         I40E_PTT_UNUSED_ENTRY(182),
 827         I40E_PTT_UNUSED_ENTRY(183),
 828         I40E_PTT_UNUSED_ENTRY(184),
 829         I40E_PTT_UNUSED_ENTRY(185),
 830         I40E_PTT_UNUSED_ENTRY(186),
 831         I40E_PTT_UNUSED_ENTRY(187),
 832         I40E_PTT_UNUSED_ENTRY(188),
 833         I40E_PTT_UNUSED_ENTRY(189),
 834
 835         I40E_PTT_UNUSED_ENTRY(190),
 836         I40E_PTT_UNUSED_ENTRY(191),
 837         I40E_PTT_UNUSED_ENTRY(192),
 838         I40E_PTT_UNUSED_ENTRY(193),
 839         I40E_PTT_UNUSED_ENTRY(194),
 840         I40E_PTT_UNUSED_ENTRY(195),
 841         I40E_PTT_UNUSED_ENTRY(196),
 842         I40E_PTT_UNUSED_ENTRY(197),
 843         I40E_PTT_UNUSED_ENTRY(198),
 844         I40E_PTT_UNUSED_ENTRY(199),
 845
 846         I40E_PTT_UNUSED_ENTRY(200),
 847         I40E_PTT_UNUSED_ENTRY(201),
 848         I40E_PTT_UNUSED_ENTRY(202),
 849         I40E_PTT_UNUSED_ENTRY(203),
 850         I40E_PTT_UNUSED_ENTRY(204),
 851         I40E_PTT_UNUSED_ENTRY(205),
 852         I40E_PTT_UNUSED_ENTRY(206),
 853         I40E_PTT_UNUSED_ENTRY(207),
 854         I40E_PTT_UNUSED_ENTRY(208),
 855         I40E_PTT_UNUSED_ENTRY(209),
 856
 857         I40E_PTT_UNUSED_ENTRY(210),
 858         I40E_PTT_UNUSED_ENTRY(211),
 859         I40E_PTT_UNUSED_ENTRY(212),
 860         I40E_PTT_UNUSED_ENTRY(213),
 861         I40E_PTT_UNUSED_ENTRY(214),
 862         I40E_PTT_UNUSED_ENTRY(215),
 863         I40E_PTT_UNUSED_ENTRY(216),
 864         I40E_PTT_UNUSED_ENTRY(217),
 865         I40E_PTT_UNUSED_ENTRY(218),
 866         I40E_PTT_UNUSED_ENTRY(219),
 867
 868         I40E_PTT_UNUSED_ENTRY(220),
 869         I40E_PTT_UNUSED_ENTRY(221),
 870         I40E_PTT_UNUSED_ENTRY(222),
 871         I40E_PTT_UNUSED_ENTRY(223),
 872         I40E_PTT_UNUSED_ENTRY(224),
 873         I40E_PTT_UNUSED_ENTRY(225),
 874         I40E_PTT_UNUSED_ENTRY(226),
 875         I40E_PTT_UNUSED_ENTRY(227),
 876         I40E_PTT_UNUSED_ENTRY(228),
 877         I40E_PTT_UNUSED_ENTRY(229),
 878
 879         I40E_PTT_UNUSED_ENTRY(230),
 880         I40E_PTT_UNUSED_ENTRY(231),
 881         I40E_PTT_UNUSED_ENTRY(232),
 882         I40E_PTT_UNUSED_ENTRY(233),
 883         I40E_PTT_UNUSED_ENTRY(234),
 884         I40E_PTT_UNUSED_ENTRY(235),
 885         I40E_PTT_UNUSED_ENTRY(236),
 886         I40E_PTT_UNUSED_ENTRY(237),
 887         I40E_PTT_UNUSED_ENTRY(238),
 888         I40E_PTT_UNUSED_ENTRY(239),
 889
 890         I40E_PTT_UNUSED_ENTRY(240),
 891         I40E_PTT_UNUSED_ENTRY(241),
 892         I40E_PTT_UNUSED_ENTRY(242),
 893         I40E_PTT_UNUSED_ENTRY(243),
 894         I40E_PTT_UNUSED_ENTRY(244),
 895         I40E_PTT_UNUSED_ENTRY(245),
 896         I40E_PTT_UNUSED_ENTRY(246),
 897         I40E_PTT_UNUSED_ENTRY(247),
 898         I40E_PTT_UNUSED_ENTRY(248),
 899         I40E_PTT_UNUSED_ENTRY(249),
 900
 901         I40E_PTT_UNUSED_ENTRY(250),
 902         I40E_PTT_UNUSED_ENTRY(251),
 903         I40E_PTT_UNUSED_ENTRY(252),
 904         I40E_PTT_UNUSED_ENTRY(253),
 905         I40E_PTT_UNUSED_ENTRY(254),
 906         I40E_PTT_UNUSED_ENTRY(255)
 907 };
 908
 909 /**
 910  * i40e_init_shared_code - Initialize the shared code
 911  * @hw: pointer to hardware structure
 912  *
 913  * This assigns the MAC type and PHY code and inits the NVM.
 914  * Does not touch the hardware. This function must be called prior to any
 915  * other function in the shared code. The i40e_hw structure should be
 916  * memset to 0 prior to calling this function.  The following fields in
 917  * hw structure should be filled in prior to calling this function:
 918  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 919  * subsystem_vendor_id, and revision_id
 920  **/
 921 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
 922 {
 923         i40e_status status = 0;
 924         u32 port, ari, func_rid;
 925
 926         i40e_set_mac_type(hw);
 927
 928         switch (hw->mac.type) {
 929         case I40E_MAC_XL710:
 930         case I40E_MAC_X722:
 931                 break;
 932         default:
 933                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 934         }
 935
 936         hw->phy.get_link_info = true;
 937
 938         /* Determine port number and PF number*/
 939         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
 940                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
 941         hw->port = (u8)port;
 942         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
 943                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
 944         func_rid = rd32(hw, I40E_PF_FUNC_RID);
 945         if (ari)
 946                 hw->pf_id = (u8)(func_rid & 0xff);
 947         else
 948                 hw->pf_id = (u8)(func_rid & 0x7);
 949
 950         if (hw->mac.type == I40E_MAC_X722)
 951                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
 952
 953         status = i40e_init_nvm(hw);
 954         return status;
 955 }
 956
 957 /**
 958  * i40e_aq_mac_address_read - Retrieve the MAC addresses
 959  * @hw: pointer to the hw struct
 960  * @flags: a return indicator of what addresses were added to the addr store
 961  * @addrs: the requestor's mac addr store
 962  * @cmd_details: pointer to command details structure or NULL
 963  **/
 964 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
 965                                    u16 *flags,
 966                                    struct i40e_aqc_mac_address_read_data *addrs,
 967                                    struct i40e_asq_cmd_details *cmd_details)
 968 {
 969         struct i40e_aq_desc desc;
 970         struct i40e_aqc_mac_address_read *cmd_data =
 971                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
 972         i40e_status status;
 973
 974         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
 975         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
 976
 977         status = i40e_asq_send_command(hw, &desc, addrs,
 978                                        sizeof(*addrs), cmd_details);
 979         *flags = le16_to_cpu(cmd_data->command_flags);
 980
 981         return status;
 982 }
 983
 984 /**
 985  * i40e_aq_mac_address_write - Change the MAC addresses
 986  * @hw: pointer to the hw struct
 987  * @flags: indicates which MAC to be written
 988  * @mac_addr: address to write
 989  * @cmd_details: pointer to command details structure or NULL
 990  **/
 991 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
 992                                     u16 flags, u8 *mac_addr,
 993                                     struct i40e_asq_cmd_details *cmd_details)
 994 {
 995         struct i40e_aq_desc desc;
 996         struct i40e_aqc_mac_address_write *cmd_data =
 997                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
 998         i40e_status status;
 999
1000         i40e_fill_default_direct_cmd_desc(&desc,
1001                                           i40e_aqc_opc_mac_address_write);
1002         cmd_data->command_flags = cpu_to_le16(flags);
1003         cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
1004         cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
1005                                         ((u32)mac_addr[3] << 16) |
1006                                         ((u32)mac_addr[4] << 8) |
1007                                         mac_addr[5]);
1008
1009         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1010
1011         return status;
1012 }
1013
1014 /**
1015  * i40e_get_mac_addr - get MAC address
1016  * @hw: pointer to the HW structure
1017  * @mac_addr: pointer to MAC address
1018  *
1019  * Reads the adapter's MAC address from register
1020  **/
1021 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1022 {
1023         struct i40e_aqc_mac_address_read_data addrs;
1024         i40e_status status;
1025         u16 flags = 0;
1026
1027         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1028
1029         if (flags & I40E_AQC_LAN_ADDR_VALID)
1030                 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1031
1032         return status;
1033 }
1034
1035 /**
1036  * i40e_get_port_mac_addr - get Port MAC address
1037  * @hw: pointer to the HW structure
1038  * @mac_addr: pointer to Port MAC address
1039  *
1040  * Reads the adapter's Port MAC address
1041  **/
1042 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1043 {
1044         struct i40e_aqc_mac_address_read_data addrs;
1045         i40e_status status;
1046         u16 flags = 0;
1047
1048         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1049         if (status)
1050                 return status;
1051
1052         if (flags & I40E_AQC_PORT_ADDR_VALID)
1053                 ether_addr_copy(mac_addr, addrs.port_mac);
1054         else
1055                 status = I40E_ERR_INVALID_MAC_ADDR;
1056
1057         return status;
1058 }
1059
1060 /**
1061  * i40e_pre_tx_queue_cfg - pre tx queue configure
1062  * @hw: pointer to the HW structure
1063  * @queue: target PF queue index
1064  * @enable: state change request
1065  *
1066  * Handles hw requirement to indicate intention to enable
1067  * or disable target queue.
1068  **/
1069 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1070 {
1071         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1072         u32 reg_block = 0;
1073         u32 reg_val;
1074
1075         if (abs_queue_idx >= 128) {
1076                 reg_block = abs_queue_idx / 128;
1077                 abs_queue_idx %= 128;
1078         }
1079
1080         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1081         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1082         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1083
1084         if (enable)
1085                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1086         else
1087                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1088
1089         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1090 }
1091
1092 /**
1093  *  i40e_read_pba_string - Reads part number string from EEPROM
1094  *  @hw: pointer to hardware structure
1095  *  @pba_num: stores the part number string from the EEPROM
1096  *  @pba_num_size: part number string buffer length
1097  *
1098  *  Reads the part number string from the EEPROM.
1099  **/
1100 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1101                                  u32 pba_num_size)
1102 {
1103         i40e_status status = 0;
1104         u16 pba_word = 0;
1105         u16 pba_size = 0;
1106         u16 pba_ptr = 0;
1107         u16 i = 0;
1108
1109         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1110         if (status || (pba_word != 0xFAFA)) {
1111                 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1112                 return status;
1113         }
1114
1115         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1116         if (status) {
1117                 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1118                 return status;
1119         }
1120
1121         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1122         if (status) {
1123                 hw_dbg(hw, "Failed to read PBA Block size.\n");
1124                 return status;
1125         }
1126
1127         /* Subtract one to get PBA word count (PBA Size word is included in
1128          * total size)
1129          */
1130         pba_size--;
1131         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1132                 hw_dbg(hw, "Buffer to small for PBA data.\n");
1133                 return I40E_ERR_PARAM;
1134         }
1135
1136         for (i = 0; i < pba_size; i++) {
1137                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1138                 if (status) {
1139                         hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1140                         return status;
1141                 }
1142
1143                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1144                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1145         }
1146         pba_num[(pba_size * 2)] = '\0';
1147
1148         return status;
1149 }
1150
1151 /**
1152  * i40e_get_media_type - Gets media type
1153  * @hw: pointer to the hardware structure
1154  **/
1155 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1156 {
1157         enum i40e_media_type media;
1158
1159         switch (hw->phy.link_info.phy_type) {
1160         case I40E_PHY_TYPE_10GBASE_SR:
1161         case I40E_PHY_TYPE_10GBASE_LR:
1162         case I40E_PHY_TYPE_1000BASE_SX:
1163         case I40E_PHY_TYPE_1000BASE_LX:
1164         case I40E_PHY_TYPE_40GBASE_SR4:
1165         case I40E_PHY_TYPE_40GBASE_LR4:
1166         case I40E_PHY_TYPE_25GBASE_LR:
1167         case I40E_PHY_TYPE_25GBASE_SR:
1168                 media = I40E_MEDIA_TYPE_FIBER;
1169                 break;
1170         case I40E_PHY_TYPE_100BASE_TX:
1171         case I40E_PHY_TYPE_1000BASE_T:
1172         case I40E_PHY_TYPE_10GBASE_T:
1173                 media = I40E_MEDIA_TYPE_BASET;
1174                 break;
1175         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1176         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1177         case I40E_PHY_TYPE_10GBASE_CR1:
1178         case I40E_PHY_TYPE_40GBASE_CR4:
1179         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1180         case I40E_PHY_TYPE_40GBASE_AOC:
1181         case I40E_PHY_TYPE_10GBASE_AOC:
1182         case I40E_PHY_TYPE_25GBASE_CR:
1183                 media = I40E_MEDIA_TYPE_DA;
1184                 break;
1185         case I40E_PHY_TYPE_1000BASE_KX:
1186         case I40E_PHY_TYPE_10GBASE_KX4:
1187         case I40E_PHY_TYPE_10GBASE_KR:
1188         case I40E_PHY_TYPE_40GBASE_KR4:
1189         case I40E_PHY_TYPE_20GBASE_KR2:
1190         case I40E_PHY_TYPE_25GBASE_KR:
1191                 media = I40E_MEDIA_TYPE_BACKPLANE;
1192                 break;
1193         case I40E_PHY_TYPE_SGMII:
1194         case I40E_PHY_TYPE_XAUI:
1195         case I40E_PHY_TYPE_XFI:
1196         case I40E_PHY_TYPE_XLAUI:
1197         case I40E_PHY_TYPE_XLPPI:
1198         default:
1199                 media = I40E_MEDIA_TYPE_UNKNOWN;
1200                 break;
1201         }
1202
1203         return media;
1204 }
1205
1206 #define I40E_PF_RESET_WAIT_COUNT_A0     200
1207 #define I40E_PF_RESET_WAIT_COUNT        200
1208 /**
1209  * i40e_pf_reset - Reset the PF
1210  * @hw: pointer to the hardware structure
1211  *
1212  * Assuming someone else has triggered a global reset,
1213  * assure the global reset is complete and then reset the PF
1214  **/
1215 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1216 {
1217         u32 cnt = 0;
1218         u32 cnt1 = 0;
1219         u32 reg = 0;
1220         u32 grst_del;
1221
1222         /* Poll for Global Reset steady state in case of recent GRST.
1223          * The grst delay value is in 100ms units, and we'll wait a
1224          * couple counts longer to be sure we don't just miss the end.
1225          */
1226         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1227                     I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1228                     I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1229
1230         /* It can take upto 15 secs for GRST steady state.
1231          * Bump it to 16 secs max to be safe.
1232          */
1233         grst_del = grst_del * 20;
1234
1235         for (cnt = 0; cnt < grst_del; cnt++) {
1236                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1237                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1238                         break;
1239                 msleep(100);
1240         }
1241         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1242                 hw_dbg(hw, "Global reset polling failed to complete.\n");
1243                 return I40E_ERR_RESET_FAILED;
1244         }
1245
1246         /* Now Wait for the FW to be ready */
1247         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1248                 reg = rd32(hw, I40E_GLNVM_ULD);
1249                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1250                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1251                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1252                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1253                         hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1254                         break;
1255                 }
1256                 usleep_range(10000, 20000);
1257         }
1258         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1259                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1260                 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1261                 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1262                 return I40E_ERR_RESET_FAILED;
1263         }
1264
1265         /* If there was a Global Reset in progress when we got here,
1266          * we don't need to do the PF Reset
1267          */
1268         if (!cnt) {
1269                 if (hw->revision_id == 0)
1270                         cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1271                 else
1272                         cnt = I40E_PF_RESET_WAIT_COUNT;
1273                 reg = rd32(hw, I40E_PFGEN_CTRL);
1274                 wr32(hw, I40E_PFGEN_CTRL,
1275                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1276                 for (; cnt; cnt--) {
1277                         reg = rd32(hw, I40E_PFGEN_CTRL);
1278                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1279                                 break;
1280                         usleep_range(1000, 2000);
1281                 }
1282                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1283                         hw_dbg(hw, "PF reset polling failed to complete.\n");
1284                         return I40E_ERR_RESET_FAILED;
1285                 }
1286         }
1287
1288         i40e_clear_pxe_mode(hw);
1289
1290         return 0;
1291 }
1292
1293 /**
1294  * i40e_clear_hw - clear out any left over hw state
1295  * @hw: pointer to the hw struct
1296  *
1297  * Clear queues and interrupts, typically called at init time,
1298  * but after the capabilities have been found so we know how many
1299  * queues and msix vectors have been allocated.
1300  **/
1301 void i40e_clear_hw(struct i40e_hw *hw)
1302 {
1303         u32 num_queues, base_queue;
1304         u32 num_pf_int;
1305         u32 num_vf_int;
1306         u32 num_vfs;
1307         u32 i, j;
1308         u32 val;
1309         u32 eol = 0x7ff;
1310
1311         /* get number of interrupts, queues, and VFs */
1312         val = rd32(hw, I40E_GLPCI_CNF2);
1313         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1314                      I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1315         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1316                      I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1317
1318         val = rd32(hw, I40E_PFLAN_QALLOC);
1319         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1320                      I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1321         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1322             I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1323         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1324                 num_queues = (j - base_queue) + 1;
1325         else
1326                 num_queues = 0;
1327
1328         val = rd32(hw, I40E_PF_VT_PFALLOC);
1329         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1330             I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1331         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1332             I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1333         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1334                 num_vfs = (j - i) + 1;
1335         else
1336                 num_vfs = 0;
1337
1338         /* stop all the interrupts */
1339         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1340         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1341         for (i = 0; i < num_pf_int - 2; i++)
1342                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1343
1344         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1345         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1346         wr32(hw, I40E_PFINT_LNKLST0, val);
1347         for (i = 0; i < num_pf_int - 2; i++)
1348                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1349         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1350         for (i = 0; i < num_vfs; i++)
1351                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1352         for (i = 0; i < num_vf_int - 2; i++)
1353                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1354
1355         /* warn the HW of the coming Tx disables */
1356         for (i = 0; i < num_queues; i++) {
1357                 u32 abs_queue_idx = base_queue + i;
1358                 u32 reg_block = 0;
1359
1360                 if (abs_queue_idx >= 128) {
1361                         reg_block = abs_queue_idx / 128;
1362                         abs_queue_idx %= 128;
1363                 }
1364
1365                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1366                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1367                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1368                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1369
1370                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1371         }
1372         udelay(400);
1373
1374         /* stop all the queues */
1375         for (i = 0; i < num_queues; i++) {
1376                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1377                 wr32(hw, I40E_QTX_ENA(i), 0);
1378                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1379                 wr32(hw, I40E_QRX_ENA(i), 0);
1380         }
1381
1382         /* short wait for all queue disables to settle */
1383         udelay(50);
1384 }
1385
1386 /**
1387  * i40e_clear_pxe_mode - clear pxe operations mode
1388  * @hw: pointer to the hw struct
1389  *
1390  * Make sure all PXE mode settings are cleared, including things
1391  * like descriptor fetch/write-back mode.
1392  **/
1393 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1394 {
1395         u32 reg;
1396
1397         if (i40e_check_asq_alive(hw))
1398                 i40e_aq_clear_pxe_mode(hw, NULL);
1399
1400         /* Clear single descriptor fetch/write-back mode */
1401         reg = rd32(hw, I40E_GLLAN_RCTL_0);
1402
1403         if (hw->revision_id == 0) {
1404                 /* As a work around clear PXE_MODE instead of setting it */
1405                 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1406         } else {
1407                 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1408         }
1409 }
1410
1411 /**
1412  * i40e_led_is_mine - helper to find matching led
1413  * @hw: pointer to the hw struct
1414  * @idx: index into GPIO registers
1415  *
1416  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1417  */
1418 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1419 {
1420         u32 gpio_val = 0;
1421         u32 port;
1422
1423         if (!hw->func_caps.led[idx])
1424                 return 0;
1425
1426         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1427         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1428                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1429
1430         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1431          * if it is not our port then ignore
1432          */
1433         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1434             (port != hw->port))
1435                 return 0;
1436
1437         return gpio_val;
1438 }
1439
1440 #define I40E_COMBINED_ACTIVITY 0xA
1441 #define I40E_FILTER_ACTIVITY 0xE
1442 #define I40E_LINK_ACTIVITY 0xC
1443 #define I40E_MAC_ACTIVITY 0xD
1444 #define I40E_LED0 22
1445
1446 /**
1447  * i40e_led_get - return current on/off mode
1448  * @hw: pointer to the hw struct
1449  *
1450  * The value returned is the 'mode' field as defined in the
1451  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1452  * values are variations of possible behaviors relating to
1453  * blink, link, and wire.
1454  **/
1455 u32 i40e_led_get(struct i40e_hw *hw)
1456 {
1457         u32 current_mode = 0;
1458         u32 mode = 0;
1459         int i;
1460
1461         /* as per the documentation GPIO 22-29 are the LED
1462          * GPIO pins named LED0..LED7
1463          */
1464         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1465                 u32 gpio_val = i40e_led_is_mine(hw, i);
1466
1467                 if (!gpio_val)
1468                         continue;
1469
1470                 /* ignore gpio LED src mode entries related to the activity
1471                  * LEDs
1472                  */
1473                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1474                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1475                 switch (current_mode) {
1476                 case I40E_COMBINED_ACTIVITY:
1477                 case I40E_FILTER_ACTIVITY:
1478                 case I40E_MAC_ACTIVITY:
1479                         continue;
1480                 default:
1481                         break;
1482                 }
1483
1484                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1485                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1486                 break;
1487         }
1488
1489         return mode;
1490 }
1491
1492 /**
1493  * i40e_led_set - set new on/off mode
1494  * @hw: pointer to the hw struct
1495  * @mode: 0=off, 0xf=on (else see manual for mode details)
1496  * @blink: true if the LED should blink when on, false if steady
1497  *
1498  * if this function is used to turn on the blink it should
1499  * be used to disable the blink when restoring the original state.
1500  **/
1501 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1502 {
1503         u32 current_mode = 0;
1504         int i;
1505
1506         if (mode & 0xfffffff0)
1507                 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1508
1509         /* as per the documentation GPIO 22-29 are the LED
1510          * GPIO pins named LED0..LED7
1511          */
1512         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1513                 u32 gpio_val = i40e_led_is_mine(hw, i);
1514
1515                 if (!gpio_val)
1516                         continue;
1517
1518                 /* ignore gpio LED src mode entries related to the activity
1519                  * LEDs
1520                  */
1521                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1522                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1523                 switch (current_mode) {
1524                 case I40E_COMBINED_ACTIVITY:
1525                 case I40E_FILTER_ACTIVITY:
1526                 case I40E_MAC_ACTIVITY:
1527                         continue;
1528                 default:
1529                         break;
1530                 }
1531
1532                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1533                 /* this & is a bit of paranoia, but serves as a range check */
1534                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1535                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1536
1537                 if (mode == I40E_LINK_ACTIVITY)
1538                         blink = false;
1539
1540                 if (blink)
1541                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1542                 else
1543                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1544
1545                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1546                 break;
1547         }
1548 }
1549
1550 /* Admin command wrappers */
1551
1552 /**
1553  * i40e_aq_get_phy_capabilities
1554  * @hw: pointer to the hw struct
1555  * @abilities: structure for PHY capabilities to be filled
1556  * @qualified_modules: report Qualified Modules
1557  * @report_init: report init capabilities (active are default)
1558  * @cmd_details: pointer to command details structure or NULL
1559  *
1560  * Returns the various PHY abilities supported on the Port.
1561  **/
1562 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1563                         bool qualified_modules, bool report_init,
1564                         struct i40e_aq_get_phy_abilities_resp *abilities,
1565                         struct i40e_asq_cmd_details *cmd_details)
1566 {
1567         struct i40e_aq_desc desc;
1568         i40e_status status;
1569         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1570
1571         if (!abilities)
1572                 return I40E_ERR_PARAM;
1573
1574         i40e_fill_default_direct_cmd_desc(&desc,
1575                                           i40e_aqc_opc_get_phy_abilities);
1576
1577         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1578         if (abilities_size > I40E_AQ_LARGE_BUF)
1579                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1580
1581         if (qualified_modules)
1582                 desc.params.external.param0 |=
1583                         cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1584
1585         if (report_init)
1586                 desc.params.external.param0 |=
1587                         cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1588
1589         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1590                                        cmd_details);
1591
1592         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1593                 status = I40E_ERR_UNKNOWN_PHY;
1594
1595         if (report_init) {
1596                 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1597                 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32);
1598         }
1599
1600         return status;
1601 }
1602
1603 /**
1604  * i40e_aq_set_phy_config
1605  * @hw: pointer to the hw struct
1606  * @config: structure with PHY configuration to be set
1607  * @cmd_details: pointer to command details structure or NULL
1608  *
1609  * Set the various PHY configuration parameters
1610  * supported on the Port.One or more of the Set PHY config parameters may be
1611  * ignored in an MFP mode as the PF may not have the privilege to set some
1612  * of the PHY Config parameters. This status will be indicated by the
1613  * command response.
1614  **/
1615 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1616                                 struct i40e_aq_set_phy_config *config,
1617                                 struct i40e_asq_cmd_details *cmd_details)
1618 {
1619         struct i40e_aq_desc desc;
1620         struct i40e_aq_set_phy_config *cmd =
1621                         (struct i40e_aq_set_phy_config *)&desc.params.raw;
1622         enum i40e_status_code status;
1623
1624         if (!config)
1625                 return I40E_ERR_PARAM;
1626
1627         i40e_fill_default_direct_cmd_desc(&desc,
1628                                           i40e_aqc_opc_set_phy_config);
1629
1630         *cmd = *config;
1631
1632         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1633
1634         return status;
1635 }
1636
1637 /**
1638  * i40e_set_fc
1639  * @hw: pointer to the hw struct
1640  *
1641  * Set the requested flow control mode using set_phy_config.
1642  **/
1643 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1644                                   bool atomic_restart)
1645 {
1646         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1647         struct i40e_aq_get_phy_abilities_resp abilities;
1648         struct i40e_aq_set_phy_config config;
1649         enum i40e_status_code status;
1650         u8 pause_mask = 0x0;
1651
1652         *aq_failures = 0x0;
1653
1654         switch (fc_mode) {
1655         case I40E_FC_FULL:
1656                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1657                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1658                 break;
1659         case I40E_FC_RX_PAUSE:
1660                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1661                 break;
1662         case I40E_FC_TX_PAUSE:
1663                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1664                 break;
1665         default:
1666                 break;
1667         }
1668
1669         /* Get the current phy config */
1670         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1671                                               NULL);
1672         if (status) {
1673                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1674                 return status;
1675         }
1676
1677         memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1678         /* clear the old pause settings */
1679         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1680                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1681         /* set the new abilities */
1682         config.abilities |= pause_mask;
1683         /* If the abilities have changed, then set the new config */
1684         if (config.abilities != abilities.abilities) {
1685                 /* Auto restart link so settings take effect */
1686                 if (atomic_restart)
1687                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1688                 /* Copy over all the old settings */
1689                 config.phy_type = abilities.phy_type;
1690                 config.phy_type_ext = abilities.phy_type_ext;
1691                 config.link_speed = abilities.link_speed;
1692                 config.eee_capability = abilities.eee_capability;
1693                 config.eeer = abilities.eeer_val;
1694                 config.low_power_ctrl = abilities.d3_lpan;
1695                 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1696                                     I40E_AQ_PHY_FEC_CONFIG_MASK;
1697                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1698
1699                 if (status)
1700                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1701         }
1702         /* Update the link info */
1703         status = i40e_update_link_info(hw);
1704         if (status) {
1705                 /* Wait a little bit (on 40G cards it sometimes takes a really
1706                  * long time for link to come back from the atomic reset)
1707                  * and try once more
1708                  */
1709                 msleep(1000);
1710                 status = i40e_update_link_info(hw);
1711         }
1712         if (status)
1713                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1714
1715         return status;
1716 }
1717
1718 /**
1719  * i40e_aq_clear_pxe_mode
1720  * @hw: pointer to the hw struct
1721  * @cmd_details: pointer to command details structure or NULL
1722  *
1723  * Tell the firmware that the driver is taking over from PXE
1724  **/
1725 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1726                                 struct i40e_asq_cmd_details *cmd_details)
1727 {
1728         i40e_status status;
1729         struct i40e_aq_desc desc;
1730         struct i40e_aqc_clear_pxe *cmd =
1731                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1732
1733         i40e_fill_default_direct_cmd_desc(&desc,
1734                                           i40e_aqc_opc_clear_pxe_mode);
1735
1736         cmd->rx_cnt = 0x2;
1737
1738         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1739
1740         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1741
1742         return status;
1743 }
1744
1745 /**
1746  * i40e_aq_set_link_restart_an
1747  * @hw: pointer to the hw struct
1748  * @enable_link: if true: enable link, if false: disable link
1749  * @cmd_details: pointer to command details structure or NULL
1750  *
1751  * Sets up the link and restarts the Auto-Negotiation over the link.
1752  **/
1753 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1754                                         bool enable_link,
1755                                         struct i40e_asq_cmd_details *cmd_details)
1756 {
1757         struct i40e_aq_desc desc;
1758         struct i40e_aqc_set_link_restart_an *cmd =
1759                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1760         i40e_status status;
1761
1762         i40e_fill_default_direct_cmd_desc(&desc,
1763                                           i40e_aqc_opc_set_link_restart_an);
1764
1765         cmd->command = I40E_AQ_PHY_RESTART_AN;
1766         if (enable_link)
1767                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1768         else
1769                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1770
1771         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1772
1773         return status;
1774 }
1775
1776 /**
1777  * i40e_aq_get_link_info
1778  * @hw: pointer to the hw struct
1779  * @enable_lse: enable/disable LinkStatusEvent reporting
1780  * @link: pointer to link status structure - optional
1781  * @cmd_details: pointer to command details structure or NULL
1782  *
1783  * Returns the link status of the adapter.
1784  **/
1785 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1786                                 bool enable_lse, struct i40e_link_status *link,
1787                                 struct i40e_asq_cmd_details *cmd_details)
1788 {
1789         struct i40e_aq_desc desc;
1790         struct i40e_aqc_get_link_status *resp =
1791                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1792         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1793         i40e_status status;
1794         bool tx_pause, rx_pause;
1795         u16 command_flags;
1796
1797         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1798
1799         if (enable_lse)
1800                 command_flags = I40E_AQ_LSE_ENABLE;
1801         else
1802                 command_flags = I40E_AQ_LSE_DISABLE;
1803         resp->command_flags = cpu_to_le16(command_flags);
1804
1805         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1806
1807         if (status)
1808                 goto aq_get_link_info_exit;
1809
1810         /* save off old link status information */
1811         hw->phy.link_info_old = *hw_link_info;
1812
1813         /* update link status */
1814         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1815         hw->phy.media_type = i40e_get_media_type(hw);
1816         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1817         hw_link_info->link_info = resp->link_info;
1818         hw_link_info->an_info = resp->an_info;
1819         hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1820                                                  I40E_AQ_CONFIG_FEC_RS_ENA);
1821         hw_link_info->ext_info = resp->ext_info;
1822         hw_link_info->loopback = resp->loopback;
1823         hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1824         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1825
1826         /* update fc info */
1827         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1828         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1829         if (tx_pause & rx_pause)
1830                 hw->fc.current_mode = I40E_FC_FULL;
1831         else if (tx_pause)
1832                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1833         else if (rx_pause)
1834                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1835         else
1836                 hw->fc.current_mode = I40E_FC_NONE;
1837
1838         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1839                 hw_link_info->crc_enable = true;
1840         else
1841                 hw_link_info->crc_enable = false;
1842
1843         if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1844                 hw_link_info->lse_enable = true;
1845         else
1846                 hw_link_info->lse_enable = false;
1847
1848         if ((hw->mac.type == I40E_MAC_XL710) &&
1849             (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1850              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1851                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1852
1853         /* save link status information */
1854         if (link)
1855                 *link = *hw_link_info;
1856
1857         /* flag cleared so helper functions don't call AQ again */
1858         hw->phy.get_link_info = false;
1859
1860 aq_get_link_info_exit:
1861         return status;
1862 }
1863
1864 /**
1865  * i40e_aq_set_phy_int_mask
1866  * @hw: pointer to the hw struct
1867  * @mask: interrupt mask to be set
1868  * @cmd_details: pointer to command details structure or NULL
1869  *
1870  * Set link interrupt mask.
1871  **/
1872 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1873                                      u16 mask,
1874                                      struct i40e_asq_cmd_details *cmd_details)
1875 {
1876         struct i40e_aq_desc desc;
1877         struct i40e_aqc_set_phy_int_mask *cmd =
1878                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1879         i40e_status status;
1880
1881         i40e_fill_default_direct_cmd_desc(&desc,
1882                                           i40e_aqc_opc_set_phy_int_mask);
1883
1884         cmd->event_mask = cpu_to_le16(mask);
1885
1886         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1887
1888         return status;
1889 }
1890
1891 /**
1892  * i40e_aq_set_phy_debug
1893  * @hw: pointer to the hw struct
1894  * @cmd_flags: debug command flags
1895  * @cmd_details: pointer to command details structure or NULL
1896  *
1897  * Reset the external PHY.
1898  **/
1899 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1900                                   struct i40e_asq_cmd_details *cmd_details)
1901 {
1902         struct i40e_aq_desc desc;
1903         struct i40e_aqc_set_phy_debug *cmd =
1904                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1905         i40e_status status;
1906
1907         i40e_fill_default_direct_cmd_desc(&desc,
1908                                           i40e_aqc_opc_set_phy_debug);
1909
1910         cmd->command_flags = cmd_flags;
1911
1912         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1913
1914         return status;
1915 }
1916
1917 /**
1918  * i40e_is_aq_api_ver_ge
1919  * @aq: pointer to AdminQ info containing HW API version to compare
1920  * @maj: API major value
1921  * @min: API minor value
1922  *
1923  * Assert whether current HW API version is greater/equal than provided.
1924  **/
1925 static bool i40e_is_aq_api_ver_ge(struct i40e_adminq_info *aq, u16 maj,
1926                                   u16 min)
1927 {
1928         return (aq->api_maj_ver > maj ||
1929                 (aq->api_maj_ver == maj && aq->api_min_ver >= min));
1930 }
1931
1932 /**
1933  * i40e_aq_add_vsi
1934  * @hw: pointer to the hw struct
1935  * @vsi_ctx: pointer to a vsi context struct
1936  * @cmd_details: pointer to command details structure or NULL
1937  *
1938  * Add a VSI context to the hardware.
1939 **/
1940 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1941                                 struct i40e_vsi_context *vsi_ctx,
1942                                 struct i40e_asq_cmd_details *cmd_details)
1943 {
1944         struct i40e_aq_desc desc;
1945         struct i40e_aqc_add_get_update_vsi *cmd =
1946                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1947         struct i40e_aqc_add_get_update_vsi_completion *resp =
1948                 (struct i40e_aqc_add_get_update_vsi_completion *)
1949                 &desc.params.raw;
1950         i40e_status status;
1951
1952         i40e_fill_default_direct_cmd_desc(&desc,
1953                                           i40e_aqc_opc_add_vsi);
1954
1955         cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1956         cmd->connection_type = vsi_ctx->connection_type;
1957         cmd->vf_id = vsi_ctx->vf_num;
1958         cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1959
1960         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1961
1962         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1963                                     sizeof(vsi_ctx->info), cmd_details);
1964
1965         if (status)
1966                 goto aq_add_vsi_exit;
1967
1968         vsi_ctx->seid = le16_to_cpu(resp->seid);
1969         vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1970         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1971         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1972
1973 aq_add_vsi_exit:
1974         return status;
1975 }
1976
1977 /**
1978  * i40e_aq_set_default_vsi
1979  * @hw: pointer to the hw struct
1980  * @seid: vsi number
1981  * @cmd_details: pointer to command details structure or NULL
1982  **/
1983 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw,
1984                                     u16 seid,
1985                                     struct i40e_asq_cmd_details *cmd_details)
1986 {
1987         struct i40e_aq_desc desc;
1988         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1989                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1990                 &desc.params.raw;
1991         i40e_status status;
1992
1993         i40e_fill_default_direct_cmd_desc(&desc,
1994                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
1995
1996         cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1997         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1998         cmd->seid = cpu_to_le16(seid);
1999
2000         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2001
2002         return status;
2003 }
2004
2005 /**
2006  * i40e_aq_clear_default_vsi
2007  * @hw: pointer to the hw struct
2008  * @seid: vsi number
2009  * @cmd_details: pointer to command details structure or NULL
2010  **/
2011 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2012                                       u16 seid,
2013                                       struct i40e_asq_cmd_details *cmd_details)
2014 {
2015         struct i40e_aq_desc desc;
2016         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2017                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2018                 &desc.params.raw;
2019         i40e_status status;
2020
2021         i40e_fill_default_direct_cmd_desc(&desc,
2022                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2023
2024         cmd->promiscuous_flags = cpu_to_le16(0);
2025         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2026         cmd->seid = cpu_to_le16(seid);
2027
2028         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2029
2030         return status;
2031 }
2032
2033 /**
2034  * i40e_aq_set_vsi_unicast_promiscuous
2035  * @hw: pointer to the hw struct
2036  * @seid: vsi number
2037  * @set: set unicast promiscuous enable/disable
2038  * @cmd_details: pointer to command details structure or NULL
2039  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2040  **/
2041 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2042                                 u16 seid, bool set,
2043                                 struct i40e_asq_cmd_details *cmd_details,
2044                                 bool rx_only_promisc)
2045 {
2046         struct i40e_aq_desc desc;
2047         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2048                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2049         i40e_status status;
2050         u16 flags = 0;
2051
2052         i40e_fill_default_direct_cmd_desc(&desc,
2053                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2054
2055         if (set) {
2056                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2057                 if (rx_only_promisc && i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2058                         flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2059         }
2060
2061         cmd->promiscuous_flags = cpu_to_le16(flags);
2062
2063         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2064         if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2065                 cmd->valid_flags |=
2066                         cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2067
2068         cmd->seid = cpu_to_le16(seid);
2069         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2070
2071         return status;
2072 }
2073
2074 /**
2075  * i40e_aq_set_vsi_multicast_promiscuous
2076  * @hw: pointer to the hw struct
2077  * @seid: vsi number
2078  * @set: set multicast promiscuous enable/disable
2079  * @cmd_details: pointer to command details structure or NULL
2080  **/
2081 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2082                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2083 {
2084         struct i40e_aq_desc desc;
2085         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2086                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2087         i40e_status status;
2088         u16 flags = 0;
2089
2090         i40e_fill_default_direct_cmd_desc(&desc,
2091                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2092
2093         if (set)
2094                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2095
2096         cmd->promiscuous_flags = cpu_to_le16(flags);
2097
2098         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2099
2100         cmd->seid = cpu_to_le16(seid);
2101         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2102
2103         return status;
2104 }
2105
2106 /**
2107  * i40e_aq_set_vsi_mc_promisc_on_vlan
2108  * @hw: pointer to the hw struct
2109  * @seid: vsi number
2110  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2111  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2112  * @cmd_details: pointer to command details structure or NULL
2113  **/
2114 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2115                                                          u16 seid, bool enable,
2116                                                          u16 vid,
2117                                 struct i40e_asq_cmd_details *cmd_details)
2118 {
2119         struct i40e_aq_desc desc;
2120         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2121                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2122         enum i40e_status_code status;
2123         u16 flags = 0;
2124
2125         i40e_fill_default_direct_cmd_desc(&desc,
2126                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2127
2128         if (enable)
2129                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2130
2131         cmd->promiscuous_flags = cpu_to_le16(flags);
2132         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2133         cmd->seid = cpu_to_le16(seid);
2134         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2135
2136         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2137
2138         return status;
2139 }
2140
2141 /**
2142  * i40e_aq_set_vsi_uc_promisc_on_vlan
2143  * @hw: pointer to the hw struct
2144  * @seid: vsi number
2145  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2146  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2147  * @cmd_details: pointer to command details structure or NULL
2148  **/
2149 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2150                                                          u16 seid, bool enable,
2151                                                          u16 vid,
2152                                 struct i40e_asq_cmd_details *cmd_details)
2153 {
2154         struct i40e_aq_desc desc;
2155         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2156                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2157         enum i40e_status_code status;
2158         u16 flags = 0;
2159
2160         i40e_fill_default_direct_cmd_desc(&desc,
2161                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2162
2163         if (enable) {
2164                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2165                 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2166                         flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2167         }
2168
2169         cmd->promiscuous_flags = cpu_to_le16(flags);
2170         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2171         if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2172                 cmd->valid_flags |=
2173                         cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2174         cmd->seid = cpu_to_le16(seid);
2175         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2176
2177         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2178
2179         return status;
2180 }
2181
2182 /**
2183  * i40e_aq_set_vsi_bc_promisc_on_vlan
2184  * @hw: pointer to the hw struct
2185  * @seid: vsi number
2186  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2187  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2188  * @cmd_details: pointer to command details structure or NULL
2189  **/
2190 i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2191                                 u16 seid, bool enable, u16 vid,
2192                                 struct i40e_asq_cmd_details *cmd_details)
2193 {
2194         struct i40e_aq_desc desc;
2195         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2196                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2197         i40e_status status;
2198         u16 flags = 0;
2199
2200         i40e_fill_default_direct_cmd_desc(&desc,
2201                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2202
2203         if (enable)
2204                 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2205
2206         cmd->promiscuous_flags = cpu_to_le16(flags);
2207         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2208         cmd->seid = cpu_to_le16(seid);
2209         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2210
2211         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2212
2213         return status;
2214 }
2215
2216 /**
2217  * i40e_aq_set_vsi_broadcast
2218  * @hw: pointer to the hw struct
2219  * @seid: vsi number
2220  * @set_filter: true to set filter, false to clear filter
2221  * @cmd_details: pointer to command details structure or NULL
2222  *
2223  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2224  **/
2225 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2226                                 u16 seid, bool set_filter,
2227                                 struct i40e_asq_cmd_details *cmd_details)
2228 {
2229         struct i40e_aq_desc desc;
2230         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2231                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2232         i40e_status status;
2233
2234         i40e_fill_default_direct_cmd_desc(&desc,
2235                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2236
2237         if (set_filter)
2238                 cmd->promiscuous_flags
2239                             |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2240         else
2241                 cmd->promiscuous_flags
2242                             &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2243
2244         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2245         cmd->seid = cpu_to_le16(seid);
2246         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2247
2248         return status;
2249 }
2250
2251 /**
2252  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2253  * @hw: pointer to the hw struct
2254  * @seid: vsi number
2255  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2256  * @cmd_details: pointer to command details structure or NULL
2257  **/
2258 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2259                                        u16 seid, bool enable,
2260                                        struct i40e_asq_cmd_details *cmd_details)
2261 {
2262         struct i40e_aq_desc desc;
2263         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2264                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2265         i40e_status status;
2266         u16 flags = 0;
2267
2268         i40e_fill_default_direct_cmd_desc(&desc,
2269                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2270         if (enable)
2271                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2272
2273         cmd->promiscuous_flags = cpu_to_le16(flags);
2274         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2275         cmd->seid = cpu_to_le16(seid);
2276
2277         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2278
2279         return status;
2280 }
2281
2282 /**
2283  * i40e_get_vsi_params - get VSI configuration info
2284  * @hw: pointer to the hw struct
2285  * @vsi_ctx: pointer to a vsi context struct
2286  * @cmd_details: pointer to command details structure or NULL
2287  **/
2288 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2289                                 struct i40e_vsi_context *vsi_ctx,
2290                                 struct i40e_asq_cmd_details *cmd_details)
2291 {
2292         struct i40e_aq_desc desc;
2293         struct i40e_aqc_add_get_update_vsi *cmd =
2294                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2295         struct i40e_aqc_add_get_update_vsi_completion *resp =
2296                 (struct i40e_aqc_add_get_update_vsi_completion *)
2297                 &desc.params.raw;
2298         i40e_status status;
2299
2300         i40e_fill_default_direct_cmd_desc(&desc,
2301                                           i40e_aqc_opc_get_vsi_parameters);
2302
2303         cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2304
2305         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2306
2307         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2308                                     sizeof(vsi_ctx->info), NULL);
2309
2310         if (status)
2311                 goto aq_get_vsi_params_exit;
2312
2313         vsi_ctx->seid = le16_to_cpu(resp->seid);
2314         vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2315         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2316         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2317
2318 aq_get_vsi_params_exit:
2319         return status;
2320 }
2321
2322 /**
2323  * i40e_aq_update_vsi_params
2324  * @hw: pointer to the hw struct
2325  * @vsi_ctx: pointer to a vsi context struct
2326  * @cmd_details: pointer to command details structure or NULL
2327  *
2328  * Update a VSI context.
2329  **/
2330 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2331                                 struct i40e_vsi_context *vsi_ctx,
2332                                 struct i40e_asq_cmd_details *cmd_details)
2333 {
2334         struct i40e_aq_desc desc;
2335         struct i40e_aqc_add_get_update_vsi *cmd =
2336                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2337         struct i40e_aqc_add_get_update_vsi_completion *resp =
2338                 (struct i40e_aqc_add_get_update_vsi_completion *)
2339                 &desc.params.raw;
2340         i40e_status status;
2341
2342         i40e_fill_default_direct_cmd_desc(&desc,
2343                                           i40e_aqc_opc_update_vsi_parameters);
2344         cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2345
2346         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2347
2348         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2349                                     sizeof(vsi_ctx->info), cmd_details);
2350
2351         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2352         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2353
2354         return status;
2355 }
2356
2357 /**
2358  * i40e_aq_get_switch_config
2359  * @hw: pointer to the hardware structure
2360  * @buf: pointer to the result buffer
2361  * @buf_size: length of input buffer
2362  * @start_seid: seid to start for the report, 0 == beginning
2363  * @cmd_details: pointer to command details structure or NULL
2364  *
2365  * Fill the buf with switch configuration returned from AdminQ command
2366  **/
2367 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2368                                 struct i40e_aqc_get_switch_config_resp *buf,
2369                                 u16 buf_size, u16 *start_seid,
2370                                 struct i40e_asq_cmd_details *cmd_details)
2371 {
2372         struct i40e_aq_desc desc;
2373         struct i40e_aqc_switch_seid *scfg =
2374                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2375         i40e_status status;
2376
2377         i40e_fill_default_direct_cmd_desc(&desc,
2378                                           i40e_aqc_opc_get_switch_config);
2379         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2380         if (buf_size > I40E_AQ_LARGE_BUF)
2381                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2382         scfg->seid = cpu_to_le16(*start_seid);
2383
2384         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2385         *start_seid = le16_to_cpu(scfg->seid);
2386
2387         return status;
2388 }
2389
2390 /**
2391  * i40e_aq_set_switch_config
2392  * @hw: pointer to the hardware structure
2393  * @flags: bit flag values to set
2394  * @valid_flags: which bit flags to set
2395  * @cmd_details: pointer to command details structure or NULL
2396  *
2397  * Set switch configuration bits
2398  **/
2399 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2400                                                 u16 flags,
2401                                                 u16 valid_flags,
2402                                 struct i40e_asq_cmd_details *cmd_details)
2403 {
2404         struct i40e_aq_desc desc;
2405         struct i40e_aqc_set_switch_config *scfg =
2406                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2407         enum i40e_status_code status;
2408
2409         i40e_fill_default_direct_cmd_desc(&desc,
2410                                           i40e_aqc_opc_set_switch_config);
2411         scfg->flags = cpu_to_le16(flags);
2412         scfg->valid_flags = cpu_to_le16(valid_flags);
2413
2414         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2415
2416         return status;
2417 }
2418
2419 /**
2420  * i40e_aq_get_firmware_version
2421  * @hw: pointer to the hw struct
2422  * @fw_major_version: firmware major version
2423  * @fw_minor_version: firmware minor version
2424  * @fw_build: firmware build number
2425  * @api_major_version: major queue version
2426  * @api_minor_version: minor queue version
2427  * @cmd_details: pointer to command details structure or NULL
2428  *
2429  * Get the firmware version from the admin queue commands
2430  **/
2431 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2432                                 u16 *fw_major_version, u16 *fw_minor_version,
2433                                 u32 *fw_build,
2434                                 u16 *api_major_version, u16 *api_minor_version,
2435                                 struct i40e_asq_cmd_details *cmd_details)
2436 {
2437         struct i40e_aq_desc desc;
2438         struct i40e_aqc_get_version *resp =
2439                 (struct i40e_aqc_get_version *)&desc.params.raw;
2440         i40e_status status;
2441
2442         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2443
2444         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2445
2446         if (!status) {
2447                 if (fw_major_version)
2448                         *fw_major_version = le16_to_cpu(resp->fw_major);
2449                 if (fw_minor_version)
2450                         *fw_minor_version = le16_to_cpu(resp->fw_minor);
2451                 if (fw_build)
2452                         *fw_build = le32_to_cpu(resp->fw_build);
2453                 if (api_major_version)
2454                         *api_major_version = le16_to_cpu(resp->api_major);
2455                 if (api_minor_version)
2456                         *api_minor_version = le16_to_cpu(resp->api_minor);
2457         }
2458
2459         return status;
2460 }
2461
2462 /**
2463  * i40e_aq_send_driver_version
2464  * @hw: pointer to the hw struct
2465  * @dv: driver's major, minor version
2466  * @cmd_details: pointer to command details structure or NULL
2467  *
2468  * Send the driver version to the firmware
2469  **/
2470 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2471                                 struct i40e_driver_version *dv,
2472                                 struct i40e_asq_cmd_details *cmd_details)
2473 {
2474         struct i40e_aq_desc desc;
2475         struct i40e_aqc_driver_version *cmd =
2476                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2477         i40e_status status;
2478         u16 len;
2479
2480         if (dv == NULL)
2481                 return I40E_ERR_PARAM;
2482
2483         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2484
2485         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2486         cmd->driver_major_ver = dv->major_version;
2487         cmd->driver_minor_ver = dv->minor_version;
2488         cmd->driver_build_ver = dv->build_version;
2489         cmd->driver_subbuild_ver = dv->subbuild_version;
2490
2491         len = 0;
2492         while (len < sizeof(dv->driver_string) &&
2493                (dv->driver_string[len] < 0x80) &&
2494                dv->driver_string[len])
2495                 len++;
2496         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2497                                        len, cmd_details);
2498
2499         return status;
2500 }
2501
2502 /**
2503  * i40e_get_link_status - get status of the HW network link
2504  * @hw: pointer to the hw struct
2505  * @link_up: pointer to bool (true/false = linkup/linkdown)
2506  *
2507  * Variable link_up true if link is up, false if link is down.
2508  * The variable link_up is invalid if returned value of status != 0
2509  *
2510  * Side effect: LinkStatusEvent reporting becomes enabled
2511  **/
2512 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2513 {
2514         i40e_status status = 0;
2515
2516         if (hw->phy.get_link_info) {
2517                 status = i40e_update_link_info(hw);
2518
2519                 if (status)
2520                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2521                                    status);
2522         }
2523
2524         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2525
2526         return status;
2527 }
2528
2529 /**
2530  * i40e_updatelink_status - update status of the HW network link
2531  * @hw: pointer to the hw struct
2532  **/
2533 i40e_status i40e_update_link_info(struct i40e_hw *hw)
2534 {
2535         struct i40e_aq_get_phy_abilities_resp abilities;
2536         i40e_status status = 0;
2537
2538         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2539         if (status)
2540                 return status;
2541
2542         /* extra checking needed to ensure link info to user is timely */
2543         if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2544             ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2545              !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2546                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2547                                                       &abilities, NULL);
2548                 if (status)
2549                         return status;
2550
2551                 hw->phy.link_info.req_fec_info =
2552                         abilities.fec_cfg_curr_mod_ext_info &
2553                         (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2554
2555                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2556                        sizeof(hw->phy.link_info.module_type));
2557         }
2558
2559         return status;
2560 }
2561
2562 /**
2563  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2564  * @hw: pointer to the hw struct
2565  * @uplink_seid: the MAC or other gizmo SEID
2566  * @downlink_seid: the VSI SEID
2567  * @enabled_tc: bitmap of TCs to be enabled
2568  * @default_port: true for default port VSI, false for control port
2569  * @veb_seid: pointer to where to put the resulting VEB SEID
2570  * @enable_stats: true to turn on VEB stats
2571  * @cmd_details: pointer to command details structure or NULL
2572  *
2573  * This asks the FW to add a VEB between the uplink and downlink
2574  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2575  **/
2576 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2577                                 u16 downlink_seid, u8 enabled_tc,
2578                                 bool default_port, u16 *veb_seid,
2579                                 bool enable_stats,
2580                                 struct i40e_asq_cmd_details *cmd_details)
2581 {
2582         struct i40e_aq_desc desc;
2583         struct i40e_aqc_add_veb *cmd =
2584                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2585         struct i40e_aqc_add_veb_completion *resp =
2586                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2587         i40e_status status;
2588         u16 veb_flags = 0;
2589
2590         /* SEIDs need to either both be set or both be 0 for floating VEB */
2591         if (!!uplink_seid != !!downlink_seid)
2592                 return I40E_ERR_PARAM;
2593
2594         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2595
2596         cmd->uplink_seid = cpu_to_le16(uplink_seid);
2597         cmd->downlink_seid = cpu_to_le16(downlink_seid);
2598         cmd->enable_tcs = enabled_tc;
2599         if (!uplink_seid)
2600                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2601         if (default_port)
2602                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2603         else
2604                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2605
2606         /* reverse logic here: set the bitflag to disable the stats */
2607         if (!enable_stats)
2608                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2609
2610         cmd->veb_flags = cpu_to_le16(veb_flags);
2611
2612         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2613
2614         if (!status && veb_seid)
2615                 *veb_seid = le16_to_cpu(resp->veb_seid);
2616
2617         return status;
2618 }
2619
2620 /**
2621  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2622  * @hw: pointer to the hw struct
2623  * @veb_seid: the SEID of the VEB to query
2624  * @switch_id: the uplink switch id
2625  * @floating: set to true if the VEB is floating
2626  * @statistic_index: index of the stats counter block for this VEB
2627  * @vebs_used: number of VEB's used by function
2628  * @vebs_free: total VEB's not reserved by any function
2629  * @cmd_details: pointer to command details structure or NULL
2630  *
2631  * This retrieves the parameters for a particular VEB, specified by
2632  * uplink_seid, and returns them to the caller.
2633  **/
2634 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2635                                 u16 veb_seid, u16 *switch_id,
2636                                 bool *floating, u16 *statistic_index,
2637                                 u16 *vebs_used, u16 *vebs_free,
2638                                 struct i40e_asq_cmd_details *cmd_details)
2639 {
2640         struct i40e_aq_desc desc;
2641         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2642                 (struct i40e_aqc_get_veb_parameters_completion *)
2643                 &desc.params.raw;
2644         i40e_status status;
2645
2646         if (veb_seid == 0)
2647                 return I40E_ERR_PARAM;
2648
2649         i40e_fill_default_direct_cmd_desc(&desc,
2650                                           i40e_aqc_opc_get_veb_parameters);
2651         cmd_resp->seid = cpu_to_le16(veb_seid);
2652
2653         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2654         if (status)
2655                 goto get_veb_exit;
2656
2657         if (switch_id)
2658                 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2659         if (statistic_index)
2660                 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2661         if (vebs_used)
2662                 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2663         if (vebs_free)
2664                 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2665         if (floating) {
2666                 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2667
2668                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2669                         *floating = true;
2670                 else
2671                         *floating = false;
2672         }
2673
2674 get_veb_exit:
2675         return status;
2676 }
2677
2678 /**
2679  * i40e_aq_add_macvlan
2680  * @hw: pointer to the hw struct
2681  * @seid: VSI for the mac address
2682  * @mv_list: list of macvlans to be added
2683  * @count: length of the list
2684  * @cmd_details: pointer to command details structure or NULL
2685  *
2686  * Add MAC/VLAN addresses to the HW filtering
2687  **/
2688 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2689                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2690                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2691 {
2692         struct i40e_aq_desc desc;
2693         struct i40e_aqc_macvlan *cmd =
2694                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2695         i40e_status status;
2696         u16 buf_size;
2697         int i;
2698
2699         if (count == 0 || !mv_list || !hw)
2700                 return I40E_ERR_PARAM;
2701
2702         buf_size = count * sizeof(*mv_list);
2703
2704         /* prep the rest of the request */
2705         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2706         cmd->num_addresses = cpu_to_le16(count);
2707         cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2708         cmd->seid[1] = 0;
2709         cmd->seid[2] = 0;
2710
2711         for (i = 0; i < count; i++)
2712                 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2713                         mv_list[i].flags |=
2714                                cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2715
2716         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2717         if (buf_size > I40E_AQ_LARGE_BUF)
2718                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2719
2720         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2721                                        cmd_details);
2722
2723         return status;
2724 }
2725
2726 /**
2727  * i40e_aq_remove_macvlan
2728  * @hw: pointer to the hw struct
2729  * @seid: VSI for the mac address
2730  * @mv_list: list of macvlans to be removed
2731  * @count: length of the list
2732  * @cmd_details: pointer to command details structure or NULL
2733  *
2734  * Remove MAC/VLAN addresses from the HW filtering
2735  **/
2736 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2737                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2738                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2739 {
2740         struct i40e_aq_desc desc;
2741         struct i40e_aqc_macvlan *cmd =
2742                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2743         i40e_status status;
2744         u16 buf_size;
2745
2746         if (count == 0 || !mv_list || !hw)
2747                 return I40E_ERR_PARAM;
2748
2749         buf_size = count * sizeof(*mv_list);
2750
2751         /* prep the rest of the request */
2752         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2753         cmd->num_addresses = cpu_to_le16(count);
2754         cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2755         cmd->seid[1] = 0;
2756         cmd->seid[2] = 0;
2757
2758         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2759         if (buf_size > I40E_AQ_LARGE_BUF)
2760                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2761
2762         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2763                                        cmd_details);
2764
2765         return status;
2766 }
2767
2768 /**
2769  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2770  * @hw: pointer to the hw struct
2771  * @opcode: AQ opcode for add or delete mirror rule
2772  * @sw_seid: Switch SEID (to which rule refers)
2773  * @rule_type: Rule Type (ingress/egress/VLAN)
2774  * @id: Destination VSI SEID or Rule ID
2775  * @count: length of the list
2776  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2777  * @cmd_details: pointer to command details structure or NULL
2778  * @rule_id: Rule ID returned from FW
2779  * @rule_used: Number of rules used in internal switch
2780  * @rule_free: Number of rules free in internal switch
2781  *
2782  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2783  * VEBs/VEPA elements only
2784  **/
2785 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2786                                 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2787                                 u16 count, __le16 *mr_list,
2788                                 struct i40e_asq_cmd_details *cmd_details,
2789                                 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2790 {
2791         struct i40e_aq_desc desc;
2792         struct i40e_aqc_add_delete_mirror_rule *cmd =
2793                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2794         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2795         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2796         i40e_status status;
2797         u16 buf_size;
2798
2799         buf_size = count * sizeof(*mr_list);
2800
2801         /* prep the rest of the request */
2802         i40e_fill_default_direct_cmd_desc(&desc, opcode);
2803         cmd->seid = cpu_to_le16(sw_seid);
2804         cmd->rule_type = cpu_to_le16(rule_type &
2805                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
2806         cmd->num_entries = cpu_to_le16(count);
2807         /* Dest VSI for add, rule_id for delete */
2808         cmd->destination = cpu_to_le16(id);
2809         if (mr_list) {
2810                 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2811                                                 I40E_AQ_FLAG_RD));
2812                 if (buf_size > I40E_AQ_LARGE_BUF)
2813                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2814         }
2815
2816         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2817                                        cmd_details);
2818         if (!status ||
2819             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2820                 if (rule_id)
2821                         *rule_id = le16_to_cpu(resp->rule_id);
2822                 if (rules_used)
2823                         *rules_used = le16_to_cpu(resp->mirror_rules_used);
2824                 if (rules_free)
2825                         *rules_free = le16_to_cpu(resp->mirror_rules_free);
2826         }
2827         return status;
2828 }
2829
2830 /**
2831  * i40e_aq_add_mirrorrule - add a mirror rule
2832  * @hw: pointer to the hw struct
2833  * @sw_seid: Switch SEID (to which rule refers)
2834  * @rule_type: Rule Type (ingress/egress/VLAN)
2835  * @dest_vsi: SEID of VSI to which packets will be mirrored
2836  * @count: length of the list
2837  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2838  * @cmd_details: pointer to command details structure or NULL
2839  * @rule_id: Rule ID returned from FW
2840  * @rule_used: Number of rules used in internal switch
2841  * @rule_free: Number of rules free in internal switch
2842  *
2843  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2844  **/
2845 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2846                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2847                         struct i40e_asq_cmd_details *cmd_details,
2848                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2849 {
2850         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2851             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2852                 if (count == 0 || !mr_list)
2853                         return I40E_ERR_PARAM;
2854         }
2855
2856         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2857                                   rule_type, dest_vsi, count, mr_list,
2858                                   cmd_details, rule_id, rules_used, rules_free);
2859 }
2860
2861 /**
2862  * i40e_aq_delete_mirrorrule - delete a mirror rule
2863  * @hw: pointer to the hw struct
2864  * @sw_seid: Switch SEID (to which rule refers)
2865  * @rule_type: Rule Type (ingress/egress/VLAN)
2866  * @count: length of the list
2867  * @rule_id: Rule ID that is returned in the receive desc as part of
2868  *              add_mirrorrule.
2869  * @mr_list: list of mirrored VLAN IDs to be removed
2870  * @cmd_details: pointer to command details structure or NULL
2871  * @rule_used: Number of rules used in internal switch
2872  * @rule_free: Number of rules free in internal switch
2873  *
2874  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2875  **/
2876 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2877                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2878                         struct i40e_asq_cmd_details *cmd_details,
2879                         u16 *rules_used, u16 *rules_free)
2880 {
2881         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2882         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2883                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2884                  * mirroring. For other rule_type, count and rule_type should
2885                  * not matter.
2886                  */
2887                 if (count == 0 || !mr_list)
2888                         return I40E_ERR_PARAM;
2889         }
2890
2891         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2892                                   rule_type, rule_id, count, mr_list,
2893                                   cmd_details, NULL, rules_used, rules_free);
2894 }
2895
2896 /**
2897  * i40e_aq_send_msg_to_vf
2898  * @hw: pointer to the hardware structure
2899  * @vfid: VF id to send msg
2900  * @v_opcode: opcodes for VF-PF communication
2901  * @v_retval: return error code
2902  * @msg: pointer to the msg buffer
2903  * @msglen: msg length
2904  * @cmd_details: pointer to command details
2905  *
2906  * send msg to vf
2907  **/
2908 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2909                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2910                                 struct i40e_asq_cmd_details *cmd_details)
2911 {
2912         struct i40e_aq_desc desc;
2913         struct i40e_aqc_pf_vf_message *cmd =
2914                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2915         i40e_status status;
2916
2917         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2918         cmd->id = cpu_to_le32(vfid);
2919         desc.cookie_high = cpu_to_le32(v_opcode);
2920         desc.cookie_low = cpu_to_le32(v_retval);
2921         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2922         if (msglen) {
2923                 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2924                                                 I40E_AQ_FLAG_RD));
2925                 if (msglen > I40E_AQ_LARGE_BUF)
2926                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2927                 desc.datalen = cpu_to_le16(msglen);
2928         }
2929         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2930
2931         return status;
2932 }
2933
2934 /**
2935  * i40e_aq_debug_read_register
2936  * @hw: pointer to the hw struct
2937  * @reg_addr: register address
2938  * @reg_val: register value
2939  * @cmd_details: pointer to command details structure or NULL
2940  *
2941  * Read the register using the admin queue commands
2942  **/
2943 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2944                                 u32 reg_addr, u64 *reg_val,
2945                                 struct i40e_asq_cmd_details *cmd_details)
2946 {
2947         struct i40e_aq_desc desc;
2948         struct i40e_aqc_debug_reg_read_write *cmd_resp =
2949                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2950         i40e_status status;
2951
2952         if (reg_val == NULL)
2953                 return I40E_ERR_PARAM;
2954
2955         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2956
2957         cmd_resp->address = cpu_to_le32(reg_addr);
2958
2959         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2960
2961         if (!status) {
2962                 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2963                            (u64)le32_to_cpu(cmd_resp->value_low);
2964         }
2965
2966         return status;
2967 }
2968
2969 /**
2970  * i40e_aq_debug_write_register
2971  * @hw: pointer to the hw struct
2972  * @reg_addr: register address
2973  * @reg_val: register value
2974  * @cmd_details: pointer to command details structure or NULL
2975  *
2976  * Write to a register using the admin queue commands
2977  **/
2978 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2979                                         u32 reg_addr, u64 reg_val,
2980                                         struct i40e_asq_cmd_details *cmd_details)
2981 {
2982         struct i40e_aq_desc desc;
2983         struct i40e_aqc_debug_reg_read_write *cmd =
2984                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2985         i40e_status status;
2986
2987         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2988
2989         cmd->address = cpu_to_le32(reg_addr);
2990         cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2991         cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2992
2993         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2994
2995         return status;
2996 }
2997
2998 /**
2999  * i40e_aq_request_resource
3000  * @hw: pointer to the hw struct
3001  * @resource: resource id
3002  * @access: access type
3003  * @sdp_number: resource number
3004  * @timeout: the maximum time in ms that the driver may hold the resource
3005  * @cmd_details: pointer to command details structure or NULL
3006  *
3007  * requests common resource using the admin queue commands
3008  **/
3009 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
3010                                 enum i40e_aq_resources_ids resource,
3011                                 enum i40e_aq_resource_access_type access,
3012                                 u8 sdp_number, u64 *timeout,
3013                                 struct i40e_asq_cmd_details *cmd_details)
3014 {
3015         struct i40e_aq_desc desc;
3016         struct i40e_aqc_request_resource *cmd_resp =
3017                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3018         i40e_status status;
3019
3020         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
3021
3022         cmd_resp->resource_id = cpu_to_le16(resource);
3023         cmd_resp->access_type = cpu_to_le16(access);
3024         cmd_resp->resource_number = cpu_to_le32(sdp_number);
3025
3026         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3027         /* The completion specifies the maximum time in ms that the driver
3028          * may hold the resource in the Timeout field.
3029          * If the resource is held by someone else, the command completes with
3030          * busy return value and the timeout field indicates the maximum time
3031          * the current owner of the resource has to free it.
3032          */
3033         if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3034                 *timeout = le32_to_cpu(cmd_resp->timeout);
3035
3036         return status;
3037 }
3038
3039 /**
3040  * i40e_aq_release_resource
3041  * @hw: pointer to the hw struct
3042  * @resource: resource id
3043  * @sdp_number: resource number
3044  * @cmd_details: pointer to command details structure or NULL
3045  *
3046  * release common resource using the admin queue commands
3047  **/
3048 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
3049                                 enum i40e_aq_resources_ids resource,
3050                                 u8 sdp_number,
3051                                 struct i40e_asq_cmd_details *cmd_details)
3052 {
3053         struct i40e_aq_desc desc;
3054         struct i40e_aqc_request_resource *cmd =
3055                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3056         i40e_status status;
3057
3058         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3059
3060         cmd->resource_id = cpu_to_le16(resource);
3061         cmd->resource_number = cpu_to_le32(sdp_number);
3062
3063         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3064
3065         return status;
3066 }
3067
3068 /**
3069  * i40e_aq_read_nvm
3070  * @hw: pointer to the hw struct
3071  * @module_pointer: module pointer location in words from the NVM beginning
3072  * @offset: byte offset from the module beginning
3073  * @length: length of the section to be read (in bytes from the offset)
3074  * @data: command buffer (size [bytes] = length)
3075  * @last_command: tells if this is the last command in a series
3076  * @cmd_details: pointer to command details structure or NULL
3077  *
3078  * Read the NVM using the admin queue commands
3079  **/
3080 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3081                                 u32 offset, u16 length, void *data,
3082                                 bool last_command,
3083                                 struct i40e_asq_cmd_details *cmd_details)
3084 {
3085         struct i40e_aq_desc desc;
3086         struct i40e_aqc_nvm_update *cmd =
3087                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3088         i40e_status status;
3089
3090         /* In offset the highest byte must be zeroed. */
3091         if (offset & 0xFF000000) {
3092                 status = I40E_ERR_PARAM;
3093                 goto i40e_aq_read_nvm_exit;
3094         }
3095
3096         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3097
3098         /* If this is the last command in a series, set the proper flag. */
3099         if (last_command)
3100                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3101         cmd->module_pointer = module_pointer;
3102         cmd->offset = cpu_to_le32(offset);
3103         cmd->length = cpu_to_le16(length);
3104
3105         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3106         if (length > I40E_AQ_LARGE_BUF)
3107                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3108
3109         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3110
3111 i40e_aq_read_nvm_exit:
3112         return status;
3113 }
3114
3115 /**
3116  * i40e_aq_erase_nvm
3117  * @hw: pointer to the hw struct
3118  * @module_pointer: module pointer location in words from the NVM beginning
3119  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3120  * @length: length of the section to be erased (expressed in 4 KB)
3121  * @last_command: tells if this is the last command in a series
3122  * @cmd_details: pointer to command details structure or NULL
3123  *
3124  * Erase the NVM sector using the admin queue commands
3125  **/
3126 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3127                               u32 offset, u16 length, bool last_command,
3128                               struct i40e_asq_cmd_details *cmd_details)
3129 {
3130         struct i40e_aq_desc desc;
3131         struct i40e_aqc_nvm_update *cmd =
3132                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3133         i40e_status status;
3134
3135         /* In offset the highest byte must be zeroed. */
3136         if (offset & 0xFF000000) {
3137                 status = I40E_ERR_PARAM;
3138                 goto i40e_aq_erase_nvm_exit;
3139         }
3140
3141         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3142
3143         /* If this is the last command in a series, set the proper flag. */
3144         if (last_command)
3145                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3146         cmd->module_pointer = module_pointer;
3147         cmd->offset = cpu_to_le32(offset);
3148         cmd->length = cpu_to_le16(length);
3149
3150         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3151
3152 i40e_aq_erase_nvm_exit:
3153         return status;
3154 }
3155
3156 /**
3157  * i40e_parse_discover_capabilities
3158  * @hw: pointer to the hw struct
3159  * @buff: pointer to a buffer containing device/function capability records
3160  * @cap_count: number of capability records in the list
3161  * @list_type_opc: type of capabilities list to parse
3162  *
3163  * Parse the device/function capabilities list.
3164  **/
3165 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3166                                      u32 cap_count,
3167                                      enum i40e_admin_queue_opc list_type_opc)
3168 {
3169         struct i40e_aqc_list_capabilities_element_resp *cap;
3170         u32 valid_functions, num_functions;
3171         u32 number, logical_id, phys_id;
3172         struct i40e_hw_capabilities *p;
3173         u8 major_rev;
3174         u32 i = 0;
3175         u16 id;
3176
3177         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3178
3179         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3180                 p = &hw->dev_caps;
3181         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3182                 p = &hw->func_caps;
3183         else
3184                 return;
3185
3186         for (i = 0; i < cap_count; i++, cap++) {
3187                 id = le16_to_cpu(cap->id);
3188                 number = le32_to_cpu(cap->number);
3189                 logical_id = le32_to_cpu(cap->logical_id);
3190                 phys_id = le32_to_cpu(cap->phys_id);
3191                 major_rev = cap->major_rev;
3192
3193                 switch (id) {
3194                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3195                         p->switch_mode = number;
3196                         break;
3197                 case I40E_AQ_CAP_ID_MNG_MODE:
3198                         p->management_mode = number;
3199                         if (major_rev > 1) {
3200                                 p->mng_protocols_over_mctp = logical_id;
3201                                 i40e_debug(hw, I40E_DEBUG_INIT,
3202                                            "HW Capability: Protocols over MCTP = %d\n",
3203                                            p->mng_protocols_over_mctp);
3204                         } else {
3205                                 p->mng_protocols_over_mctp = 0;
3206                         }
3207                         break;
3208                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3209                         p->npar_enable = number;
3210                         break;
3211                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3212                         p->os2bmc = number;
3213                         break;
3214                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3215                         p->valid_functions = number;
3216                         break;
3217                 case I40E_AQ_CAP_ID_SRIOV:
3218                         if (number == 1)
3219                                 p->sr_iov_1_1 = true;
3220                         break;
3221                 case I40E_AQ_CAP_ID_VF:
3222                         p->num_vfs = number;
3223                         p->vf_base_id = logical_id;
3224                         break;
3225                 case I40E_AQ_CAP_ID_VMDQ:
3226                         if (number == 1)
3227                                 p->vmdq = true;
3228                         break;
3229                 case I40E_AQ_CAP_ID_8021QBG:
3230                         if (number == 1)
3231                                 p->evb_802_1_qbg = true;
3232                         break;
3233                 case I40E_AQ_CAP_ID_8021QBR:
3234                         if (number == 1)
3235                                 p->evb_802_1_qbh = true;
3236                         break;
3237                 case I40E_AQ_CAP_ID_VSI:
3238                         p->num_vsis = number;
3239                         break;
3240                 case I40E_AQ_CAP_ID_DCB:
3241                         if (number == 1) {
3242                                 p->dcb = true;
3243                                 p->enabled_tcmap = logical_id;
3244                                 p->maxtc = phys_id;
3245                         }
3246                         break;
3247                 case I40E_AQ_CAP_ID_FCOE:
3248                         if (number == 1)
3249                                 p->fcoe = true;
3250                         break;
3251                 case I40E_AQ_CAP_ID_ISCSI:
3252                         if (number == 1)
3253                                 p->iscsi = true;
3254                         break;
3255                 case I40E_AQ_CAP_ID_RSS:
3256                         p->rss = true;
3257                         p->rss_table_size = number;
3258                         p->rss_table_entry_width = logical_id;
3259                         break;
3260                 case I40E_AQ_CAP_ID_RXQ:
3261                         p->num_rx_qp = number;
3262                         p->base_queue = phys_id;
3263                         break;
3264                 case I40E_AQ_CAP_ID_TXQ:
3265                         p->num_tx_qp = number;
3266                         p->base_queue = phys_id;
3267                         break;
3268                 case I40E_AQ_CAP_ID_MSIX:
3269                         p->num_msix_vectors = number;
3270                         i40e_debug(hw, I40E_DEBUG_INIT,
3271                                    "HW Capability: MSIX vector count = %d\n",
3272                                    p->num_msix_vectors);
3273                         break;
3274                 case I40E_AQ_CAP_ID_VF_MSIX:
3275                         p->num_msix_vectors_vf = number;
3276                         break;
3277                 case I40E_AQ_CAP_ID_FLEX10:
3278                         if (major_rev == 1) {
3279                                 if (number == 1) {
3280                                         p->flex10_enable = true;
3281                                         p->flex10_capable = true;
3282                                 }
3283                         } else {
3284                                 /* Capability revision >= 2 */
3285                                 if (number & 1)
3286                                         p->flex10_enable = true;
3287                                 if (number & 2)
3288                                         p->flex10_capable = true;
3289                         }
3290                         p->flex10_mode = logical_id;
3291                         p->flex10_status = phys_id;
3292                         break;
3293                 case I40E_AQ_CAP_ID_CEM:
3294                         if (number == 1)
3295                                 p->mgmt_cem = true;
3296                         break;
3297                 case I40E_AQ_CAP_ID_IWARP:
3298                         if (number == 1)
3299                                 p->iwarp = true;
3300                         break;
3301                 case I40E_AQ_CAP_ID_LED:
3302                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3303                                 p->led[phys_id] = true;
3304                         break;
3305                 case I40E_AQ_CAP_ID_SDP:
3306                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3307                                 p->sdp[phys_id] = true;
3308                         break;
3309                 case I40E_AQ_CAP_ID_MDIO:
3310                         if (number == 1) {
3311                                 p->mdio_port_num = phys_id;
3312                                 p->mdio_port_mode = logical_id;
3313                         }
3314                         break;
3315                 case I40E_AQ_CAP_ID_1588:
3316                         if (number == 1)
3317                                 p->ieee_1588 = true;
3318                         break;
3319                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3320                         p->fd = true;
3321                         p->fd_filters_guaranteed = number;
3322                         p->fd_filters_best_effort = logical_id;
3323                         break;
3324                 case I40E_AQ_CAP_ID_WSR_PROT:
3325                         p->wr_csr_prot = (u64)number;
3326                         p->wr_csr_prot |= (u64)logical_id << 32;
3327                         break;
3328                 case I40E_AQ_CAP_ID_NVM_MGMT:
3329                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3330                                 p->sec_rev_disabled = true;
3331                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3332                                 p->update_disabled = true;
3333                         break;
3334                 default:
3335                         break;
3336                 }
3337         }
3338
3339         if (p->fcoe)
3340                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3341
3342         /* Software override ensuring FCoE is disabled if npar or mfp
3343          * mode because it is not supported in these modes.
3344          */
3345         if (p->npar_enable || p->flex10_enable)
3346                 p->fcoe = false;
3347
3348         /* count the enabled ports (aka the "not disabled" ports) */
3349         hw->num_ports = 0;
3350         for (i = 0; i < 4; i++) {
3351                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3352                 u64 port_cfg = 0;
3353
3354                 /* use AQ read to get the physical register offset instead
3355                  * of the port relative offset
3356                  */
3357                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3358                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3359                         hw->num_ports++;
3360         }
3361
3362         valid_functions = p->valid_functions;
3363         num_functions = 0;
3364         while (valid_functions) {
3365                 if (valid_functions & 1)
3366                         num_functions++;
3367                 valid_functions >>= 1;
3368         }
3369
3370         /* partition id is 1-based, and functions are evenly spread
3371          * across the ports as partitions
3372          */
3373         if (hw->num_ports != 0) {
3374                 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3375                 hw->num_partitions = num_functions / hw->num_ports;
3376         }
3377
3378         /* additional HW specific goodies that might
3379          * someday be HW version specific
3380          */
3381         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3382 }
3383
3384 /**
3385  * i40e_aq_discover_capabilities
3386  * @hw: pointer to the hw struct
3387  * @buff: a virtual buffer to hold the capabilities
3388  * @buff_size: Size of the virtual buffer
3389  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3390  * @list_type_opc: capabilities type to discover - pass in the command opcode
3391  * @cmd_details: pointer to command details structure or NULL
3392  *
3393  * Get the device capabilities descriptions from the firmware
3394  **/
3395 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3396                                 void *buff, u16 buff_size, u16 *data_size,
3397                                 enum i40e_admin_queue_opc list_type_opc,
3398                                 struct i40e_asq_cmd_details *cmd_details)
3399 {
3400         struct i40e_aqc_list_capabilites *cmd;
3401         struct i40e_aq_desc desc;
3402         i40e_status status = 0;
3403
3404         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3405
3406         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3407                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3408                 status = I40E_ERR_PARAM;
3409                 goto exit;
3410         }
3411
3412         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3413
3414         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3415         if (buff_size > I40E_AQ_LARGE_BUF)
3416                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3417
3418         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3419         *data_size = le16_to_cpu(desc.datalen);
3420
3421         if (status)
3422                 goto exit;
3423
3424         i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3425                                          list_type_opc);
3426
3427 exit:
3428         return status;
3429 }
3430
3431 /**
3432  * i40e_aq_update_nvm
3433  * @hw: pointer to the hw struct
3434  * @module_pointer: module pointer location in words from the NVM beginning
3435  * @offset: byte offset from the module beginning
3436  * @length: length of the section to be written (in bytes from the offset)
3437  * @data: command buffer (size [bytes] = length)
3438  * @last_command: tells if this is the last command in a series
3439  * @cmd_details: pointer to command details structure or NULL
3440  *
3441  * Update the NVM using the admin queue commands
3442  **/
3443 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3444                                u32 offset, u16 length, void *data,
3445                                bool last_command,
3446                                struct i40e_asq_cmd_details *cmd_details)
3447 {
3448         struct i40e_aq_desc desc;
3449         struct i40e_aqc_nvm_update *cmd =
3450                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3451         i40e_status status;
3452
3453         /* In offset the highest byte must be zeroed. */
3454         if (offset & 0xFF000000) {
3455                 status = I40E_ERR_PARAM;
3456                 goto i40e_aq_update_nvm_exit;
3457         }
3458
3459         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3460
3461         /* If this is the last command in a series, set the proper flag. */
3462         if (last_command)
3463                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3464         cmd->module_pointer = module_pointer;
3465         cmd->offset = cpu_to_le32(offset);
3466         cmd->length = cpu_to_le16(length);
3467
3468         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3469         if (length > I40E_AQ_LARGE_BUF)
3470                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3471
3472         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3473
3474 i40e_aq_update_nvm_exit:
3475         return status;
3476 }
3477
3478 /**
3479  * i40e_aq_get_lldp_mib
3480  * @hw: pointer to the hw struct
3481  * @bridge_type: type of bridge requested
3482  * @mib_type: Local, Remote or both Local and Remote MIBs
3483  * @buff: pointer to a user supplied buffer to store the MIB block
3484  * @buff_size: size of the buffer (in bytes)
3485  * @local_len : length of the returned Local LLDP MIB
3486  * @remote_len: length of the returned Remote LLDP MIB
3487  * @cmd_details: pointer to command details structure or NULL
3488  *
3489  * Requests the complete LLDP MIB (entire packet).
3490  **/
3491 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3492                                 u8 mib_type, void *buff, u16 buff_size,
3493                                 u16 *local_len, u16 *remote_len,
3494                                 struct i40e_asq_cmd_details *cmd_details)
3495 {
3496         struct i40e_aq_desc desc;
3497         struct i40e_aqc_lldp_get_mib *cmd =
3498                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3499         struct i40e_aqc_lldp_get_mib *resp =
3500                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3501         i40e_status status;
3502
3503         if (buff_size == 0 || !buff)
3504                 return I40E_ERR_PARAM;
3505
3506         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3507         /* Indirect Command */
3508         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3509
3510         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3511         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3512                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3513
3514         desc.datalen = cpu_to_le16(buff_size);
3515
3516         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3517         if (buff_size > I40E_AQ_LARGE_BUF)
3518                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3519
3520         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3521         if (!status) {
3522                 if (local_len != NULL)
3523                         *local_len = le16_to_cpu(resp->local_len);
3524                 if (remote_len != NULL)
3525                         *remote_len = le16_to_cpu(resp->remote_len);
3526         }
3527
3528         return status;
3529 }
3530
3531 /**
3532  * i40e_aq_cfg_lldp_mib_change_event
3533  * @hw: pointer to the hw struct
3534  * @enable_update: Enable or Disable event posting
3535  * @cmd_details: pointer to command details structure or NULL
3536  *
3537  * Enable or Disable posting of an event on ARQ when LLDP MIB
3538  * associated with the interface changes
3539  **/
3540 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3541                                 bool enable_update,
3542                                 struct i40e_asq_cmd_details *cmd_details)
3543 {
3544         struct i40e_aq_desc desc;
3545         struct i40e_aqc_lldp_update_mib *cmd =
3546                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3547         i40e_status status;
3548
3549         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3550
3551         if (!enable_update)
3552                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3553
3554         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3555
3556         return status;
3557 }
3558
3559 /**
3560  * i40e_aq_stop_lldp
3561  * @hw: pointer to the hw struct
3562  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3563  * @cmd_details: pointer to command details structure or NULL
3564  *
3565  * Stop or Shutdown the embedded LLDP Agent
3566  **/
3567 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3568                                 struct i40e_asq_cmd_details *cmd_details)
3569 {
3570         struct i40e_aq_desc desc;
3571         struct i40e_aqc_lldp_stop *cmd =
3572                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3573         i40e_status status;
3574
3575         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3576
3577         if (shutdown_agent)
3578                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3579
3580         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3581
3582         return status;
3583 }
3584
3585 /**
3586  * i40e_aq_start_lldp
3587  * @hw: pointer to the hw struct
3588  * @cmd_details: pointer to command details structure or NULL
3589  *
3590  * Start the embedded LLDP Agent on all ports.
3591  **/
3592 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3593                                 struct i40e_asq_cmd_details *cmd_details)
3594 {
3595         struct i40e_aq_desc desc;
3596         struct i40e_aqc_lldp_start *cmd =
3597                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3598         i40e_status status;
3599
3600         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3601
3602         cmd->command = I40E_AQ_LLDP_AGENT_START;
3603
3604         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3605
3606         return status;
3607 }
3608
3609 /**
3610  * i40e_aq_get_cee_dcb_config
3611  * @hw: pointer to the hw struct
3612  * @buff: response buffer that stores CEE operational configuration
3613  * @buff_size: size of the buffer passed
3614  * @cmd_details: pointer to command details structure or NULL
3615  *
3616  * Get CEE DCBX mode operational configuration from firmware
3617  **/
3618 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3619                                        void *buff, u16 buff_size,
3620                                        struct i40e_asq_cmd_details *cmd_details)
3621 {
3622         struct i40e_aq_desc desc;
3623         i40e_status status;
3624
3625         if (buff_size == 0 || !buff)
3626                 return I40E_ERR_PARAM;
3627
3628         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3629
3630         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3631         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3632                                        cmd_details);
3633
3634         return status;
3635 }
3636
3637 /**
3638  * i40e_aq_add_udp_tunnel
3639  * @hw: pointer to the hw struct
3640  * @udp_port: the UDP port to add in Host byte order
3641  * @header_len: length of the tunneling header length in DWords
3642  * @protocol_index: protocol index type
3643  * @filter_index: pointer to filter index
3644  * @cmd_details: pointer to command details structure or NULL
3645  *
3646  * Note: Firmware expects the udp_port value to be in Little Endian format,
3647  * and this function will call cpu_to_le16 to convert from Host byte order to
3648  * Little Endian order.
3649  **/
3650 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3651                                 u16 udp_port, u8 protocol_index,
3652                                 u8 *filter_index,
3653                                 struct i40e_asq_cmd_details *cmd_details)
3654 {
3655         struct i40e_aq_desc desc;
3656         struct i40e_aqc_add_udp_tunnel *cmd =
3657                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3658         struct i40e_aqc_del_udp_tunnel_completion *resp =
3659                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3660         i40e_status status;
3661
3662         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3663
3664         cmd->udp_port = cpu_to_le16(udp_port);
3665         cmd->protocol_type = protocol_index;
3666
3667         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3668
3669         if (!status && filter_index)
3670                 *filter_index = resp->index;
3671
3672         return status;
3673 }
3674
3675 /**
3676  * i40e_aq_del_udp_tunnel
3677  * @hw: pointer to the hw struct
3678  * @index: filter index
3679  * @cmd_details: pointer to command details structure or NULL
3680  **/
3681 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3682                                 struct i40e_asq_cmd_details *cmd_details)
3683 {
3684         struct i40e_aq_desc desc;
3685         struct i40e_aqc_remove_udp_tunnel *cmd =
3686                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3687         i40e_status status;
3688
3689         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3690
3691         cmd->index = index;
3692
3693         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3694
3695         return status;
3696 }
3697
3698 /**
3699  * i40e_aq_delete_element - Delete switch element
3700  * @hw: pointer to the hw struct
3701  * @seid: the SEID to delete from the switch
3702  * @cmd_details: pointer to command details structure or NULL
3703  *
3704  * This deletes a switch element from the switch.
3705  **/
3706 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3707                                 struct i40e_asq_cmd_details *cmd_details)
3708 {
3709         struct i40e_aq_desc desc;
3710         struct i40e_aqc_switch_seid *cmd =
3711                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3712         i40e_status status;
3713
3714         if (seid == 0)
3715                 return I40E_ERR_PARAM;
3716
3717         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3718
3719         cmd->seid = cpu_to_le16(seid);
3720
3721         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3722
3723         return status;
3724 }
3725
3726 /**
3727  * i40e_aq_dcb_updated - DCB Updated Command
3728  * @hw: pointer to the hw struct
3729  * @cmd_details: pointer to command details structure or NULL
3730  *
3731  * EMP will return when the shared RPB settings have been
3732  * recomputed and modified. The retval field in the descriptor
3733  * will be set to 0 when RPB is modified.
3734  **/
3735 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3736                                 struct i40e_asq_cmd_details *cmd_details)
3737 {
3738         struct i40e_aq_desc desc;
3739         i40e_status status;
3740
3741         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3742
3743         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3744
3745         return status;
3746 }
3747
3748 /**
3749  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3750  * @hw: pointer to the hw struct
3751  * @seid: seid for the physical port/switching component/vsi
3752  * @buff: Indirect buffer to hold data parameters and response
3753  * @buff_size: Indirect buffer size
3754  * @opcode: Tx scheduler AQ command opcode
3755  * @cmd_details: pointer to command details structure or NULL
3756  *
3757  * Generic command handler for Tx scheduler AQ commands
3758  **/
3759 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3760                                 void *buff, u16 buff_size,
3761                                  enum i40e_admin_queue_opc opcode,
3762                                 struct i40e_asq_cmd_details *cmd_details)
3763 {
3764         struct i40e_aq_desc desc;
3765         struct i40e_aqc_tx_sched_ind *cmd =
3766                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3767         i40e_status status;
3768         bool cmd_param_flag = false;
3769
3770         switch (opcode) {
3771         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3772         case i40e_aqc_opc_configure_vsi_tc_bw:
3773         case i40e_aqc_opc_enable_switching_comp_ets:
3774         case i40e_aqc_opc_modify_switching_comp_ets:
3775         case i40e_aqc_opc_disable_switching_comp_ets:
3776         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3777         case i40e_aqc_opc_configure_switching_comp_bw_config:
3778                 cmd_param_flag = true;
3779                 break;
3780         case i40e_aqc_opc_query_vsi_bw_config:
3781         case i40e_aqc_opc_query_vsi_ets_sla_config:
3782         case i40e_aqc_opc_query_switching_comp_ets_config:
3783         case i40e_aqc_opc_query_port_ets_config:
3784         case i40e_aqc_opc_query_switching_comp_bw_config:
3785                 cmd_param_flag = false;
3786                 break;
3787         default:
3788                 return I40E_ERR_PARAM;
3789         }
3790
3791         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3792
3793         /* Indirect command */
3794         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3795         if (cmd_param_flag)
3796                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3797         if (buff_size > I40E_AQ_LARGE_BUF)
3798                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3799
3800         desc.datalen = cpu_to_le16(buff_size);
3801
3802         cmd->vsi_seid = cpu_to_le16(seid);
3803
3804         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3805
3806         return status;
3807 }
3808
3809 /**
3810  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3811  * @hw: pointer to the hw struct
3812  * @seid: VSI seid
3813  * @credit: BW limit credits (0 = disabled)
3814  * @max_credit: Max BW limit credits
3815  * @cmd_details: pointer to command details structure or NULL
3816  **/
3817 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3818                                 u16 seid, u16 credit, u8 max_credit,
3819                                 struct i40e_asq_cmd_details *cmd_details)
3820 {
3821         struct i40e_aq_desc desc;
3822         struct i40e_aqc_configure_vsi_bw_limit *cmd =
3823                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3824         i40e_status status;
3825
3826         i40e_fill_default_direct_cmd_desc(&desc,
3827                                           i40e_aqc_opc_configure_vsi_bw_limit);
3828
3829         cmd->vsi_seid = cpu_to_le16(seid);
3830         cmd->credit = cpu_to_le16(credit);
3831         cmd->max_credit = max_credit;
3832
3833         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3834
3835         return status;
3836 }
3837
3838 /**
3839  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3840  * @hw: pointer to the hw struct
3841  * @seid: VSI seid
3842  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3843  * @cmd_details: pointer to command details structure or NULL
3844  **/
3845 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3846                         u16 seid,
3847                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3848                         struct i40e_asq_cmd_details *cmd_details)
3849 {
3850         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3851                                     i40e_aqc_opc_configure_vsi_tc_bw,
3852                                     cmd_details);
3853 }
3854
3855 /**
3856  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3857  * @hw: pointer to the hw struct
3858  * @seid: seid of the switching component connected to Physical Port
3859  * @ets_data: Buffer holding ETS parameters
3860  * @cmd_details: pointer to command details structure or NULL
3861  **/
3862 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3863                 u16 seid,
3864                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3865                 enum i40e_admin_queue_opc opcode,
3866                 struct i40e_asq_cmd_details *cmd_details)
3867 {
3868         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3869                                     sizeof(*ets_data), opcode, cmd_details);
3870 }
3871
3872 /**
3873  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3874  * @hw: pointer to the hw struct
3875  * @seid: seid of the switching component
3876  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3877  * @cmd_details: pointer to command details structure or NULL
3878  **/
3879 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3880         u16 seid,
3881         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3882         struct i40e_asq_cmd_details *cmd_details)
3883 {
3884         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3885                             i40e_aqc_opc_configure_switching_comp_bw_config,
3886                             cmd_details);
3887 }
3888
3889 /**
3890  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3891  * @hw: pointer to the hw struct
3892  * @seid: seid of the VSI
3893  * @bw_data: Buffer to hold VSI BW configuration
3894  * @cmd_details: pointer to command details structure or NULL
3895  **/
3896 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3897                         u16 seid,
3898                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3899                         struct i40e_asq_cmd_details *cmd_details)
3900 {
3901         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3902                                     i40e_aqc_opc_query_vsi_bw_config,
3903                                     cmd_details);
3904 }
3905
3906 /**
3907  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3908  * @hw: pointer to the hw struct
3909  * @seid: seid of the VSI
3910  * @bw_data: Buffer to hold VSI BW configuration per TC
3911  * @cmd_details: pointer to command details structure or NULL
3912  **/
3913 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3914                         u16 seid,
3915                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3916                         struct i40e_asq_cmd_details *cmd_details)
3917 {
3918         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3919                                     i40e_aqc_opc_query_vsi_ets_sla_config,
3920                                     cmd_details);
3921 }
3922
3923 /**
3924  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3925  * @hw: pointer to the hw struct
3926  * @seid: seid of the switching component
3927  * @bw_data: Buffer to hold switching component's per TC BW config
3928  * @cmd_details: pointer to command details structure or NULL
3929  **/
3930 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3931                 u16 seid,
3932                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3933                 struct i40e_asq_cmd_details *cmd_details)
3934 {
3935         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3936                                    i40e_aqc_opc_query_switching_comp_ets_config,
3937                                    cmd_details);
3938 }
3939
3940 /**
3941  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3942  * @hw: pointer to the hw struct
3943  * @seid: seid of the VSI or switching component connected to Physical Port
3944  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3945  * @cmd_details: pointer to command details structure or NULL
3946  **/
3947 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3948                         u16 seid,
3949                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
3950                         struct i40e_asq_cmd_details *cmd_details)
3951 {
3952         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3953                                     i40e_aqc_opc_query_port_ets_config,
3954                                     cmd_details);
3955 }
3956
3957 /**
3958  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3959  * @hw: pointer to the hw struct
3960  * @seid: seid of the switching component
3961  * @bw_data: Buffer to hold switching component's BW configuration
3962  * @cmd_details: pointer to command details structure or NULL
3963  **/
3964 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3965                 u16 seid,
3966                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3967                 struct i40e_asq_cmd_details *cmd_details)
3968 {
3969         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3970                                     i40e_aqc_opc_query_switching_comp_bw_config,
3971                                     cmd_details);
3972 }
3973
3974 /**
3975  * i40e_validate_filter_settings
3976  * @hw: pointer to the hardware structure
3977  * @settings: Filter control settings
3978  *
3979  * Check and validate the filter control settings passed.
3980  * The function checks for the valid filter/context sizes being
3981  * passed for FCoE and PE.
3982  *
3983  * Returns 0 if the values passed are valid and within
3984  * range else returns an error.
3985  **/
3986 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3987                                 struct i40e_filter_control_settings *settings)
3988 {
3989         u32 fcoe_cntx_size, fcoe_filt_size;
3990         u32 pe_cntx_size, pe_filt_size;
3991         u32 fcoe_fmax;
3992         u32 val;
3993
3994         /* Validate FCoE settings passed */
3995         switch (settings->fcoe_filt_num) {
3996         case I40E_HASH_FILTER_SIZE_1K:
3997         case I40E_HASH_FILTER_SIZE_2K:
3998         case I40E_HASH_FILTER_SIZE_4K:
3999         case I40E_HASH_FILTER_SIZE_8K:
4000         case I40E_HASH_FILTER_SIZE_16K:
4001         case I40E_HASH_FILTER_SIZE_32K:
4002                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4003                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4004                 break;
4005         default:
4006                 return I40E_ERR_PARAM;
4007         }
4008
4009         switch (settings->fcoe_cntx_num) {
4010         case I40E_DMA_CNTX_SIZE_512:
4011         case I40E_DMA_CNTX_SIZE_1K:
4012         case I40E_DMA_CNTX_SIZE_2K:
4013         case I40E_DMA_CNTX_SIZE_4K:
4014                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4015                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4016                 break;
4017         default:
4018                 return I40E_ERR_PARAM;
4019         }
4020
4021         /* Validate PE settings passed */
4022         switch (settings->pe_filt_num) {
4023         case I40E_HASH_FILTER_SIZE_1K:
4024         case I40E_HASH_FILTER_SIZE_2K:
4025         case I40E_HASH_FILTER_SIZE_4K:
4026         case I40E_HASH_FILTER_SIZE_8K:
4027         case I40E_HASH_FILTER_SIZE_16K:
4028         case I40E_HASH_FILTER_SIZE_32K:
4029         case I40E_HASH_FILTER_SIZE_64K:
4030         case I40E_HASH_FILTER_SIZE_128K:
4031         case I40E_HASH_FILTER_SIZE_256K:
4032         case I40E_HASH_FILTER_SIZE_512K:
4033         case I40E_HASH_FILTER_SIZE_1M:
4034                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4035                 pe_filt_size <<= (u32)settings->pe_filt_num;
4036                 break;
4037         default:
4038                 return I40E_ERR_PARAM;
4039         }
4040
4041         switch (settings->pe_cntx_num) {
4042         case I40E_DMA_CNTX_SIZE_512:
4043         case I40E_DMA_CNTX_SIZE_1K:
4044         case I40E_DMA_CNTX_SIZE_2K:
4045         case I40E_DMA_CNTX_SIZE_4K:
4046         case I40E_DMA_CNTX_SIZE_8K:
4047         case I40E_DMA_CNTX_SIZE_16K:
4048         case I40E_DMA_CNTX_SIZE_32K:
4049         case I40E_DMA_CNTX_SIZE_64K:
4050         case I40E_DMA_CNTX_SIZE_128K:
4051         case I40E_DMA_CNTX_SIZE_256K:
4052                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4053                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4054                 break;
4055         default:
4056                 return I40E_ERR_PARAM;
4057         }
4058
4059         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4060         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4061         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4062                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4063         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
4064                 return I40E_ERR_INVALID_SIZE;
4065
4066         return 0;
4067 }
4068
4069 /**
4070  * i40e_set_filter_control
4071  * @hw: pointer to the hardware structure
4072  * @settings: Filter control settings
4073  *
4074  * Set the Queue Filters for PE/FCoE and enable filters required
4075  * for a single PF. It is expected that these settings are programmed
4076  * at the driver initialization time.
4077  **/
4078 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
4079                                 struct i40e_filter_control_settings *settings)
4080 {
4081         i40e_status ret = 0;
4082         u32 hash_lut_size = 0;
4083         u32 val;
4084
4085         if (!settings)
4086                 return I40E_ERR_PARAM;
4087
4088         /* Validate the input settings */
4089         ret = i40e_validate_filter_settings(hw, settings);
4090         if (ret)
4091                 return ret;
4092
4093         /* Read the PF Queue Filter control register */
4094         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
4095
4096         /* Program required PE hash buckets for the PF */
4097         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4098         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4099                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4100         /* Program required PE contexts for the PF */
4101         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4102         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4103                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4104
4105         /* Program required FCoE hash buckets for the PF */
4106         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4107         val |= ((u32)settings->fcoe_filt_num <<
4108                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4109                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4110         /* Program required FCoE DDP contexts for the PF */
4111         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4112         val |= ((u32)settings->fcoe_cntx_num <<
4113                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4114                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4115
4116         /* Program Hash LUT size for the PF */
4117         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4118         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4119                 hash_lut_size = 1;
4120         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4121                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4122
4123         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4124         if (settings->enable_fdir)
4125                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4126         if (settings->enable_ethtype)
4127                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4128         if (settings->enable_macvlan)
4129                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4130
4131         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
4132
4133         return 0;
4134 }
4135
4136 /**
4137  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4138  * @hw: pointer to the hw struct
4139  * @mac_addr: MAC address to use in the filter
4140  * @ethtype: Ethertype to use in the filter
4141  * @flags: Flags that needs to be applied to the filter
4142  * @vsi_seid: seid of the control VSI
4143  * @queue: VSI queue number to send the packet to
4144  * @is_add: Add control packet filter if True else remove
4145  * @stats: Structure to hold information on control filter counts
4146  * @cmd_details: pointer to command details structure or NULL
4147  *
4148  * This command will Add or Remove control packet filter for a control VSI.
4149  * In return it will update the total number of perfect filter count in
4150  * the stats member.
4151  **/
4152 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4153                                 u8 *mac_addr, u16 ethtype, u16 flags,
4154                                 u16 vsi_seid, u16 queue, bool is_add,
4155                                 struct i40e_control_filter_stats *stats,
4156                                 struct i40e_asq_cmd_details *cmd_details)
4157 {
4158         struct i40e_aq_desc desc;
4159         struct i40e_aqc_add_remove_control_packet_filter *cmd =
4160                 (struct i40e_aqc_add_remove_control_packet_filter *)
4161                 &desc.params.raw;
4162         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4163                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4164                 &desc.params.raw;
4165         i40e_status status;
4166
4167         if (vsi_seid == 0)
4168                 return I40E_ERR_PARAM;
4169
4170         if (is_add) {
4171                 i40e_fill_default_direct_cmd_desc(&desc,
4172                                 i40e_aqc_opc_add_control_packet_filter);
4173                 cmd->queue = cpu_to_le16(queue);
4174         } else {
4175                 i40e_fill_default_direct_cmd_desc(&desc,
4176                                 i40e_aqc_opc_remove_control_packet_filter);
4177         }
4178
4179         if (mac_addr)
4180                 ether_addr_copy(cmd->mac, mac_addr);
4181
4182         cmd->etype = cpu_to_le16(ethtype);
4183         cmd->flags = cpu_to_le16(flags);
4184         cmd->seid = cpu_to_le16(vsi_seid);
4185
4186         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4187
4188         if (!status && stats) {
4189                 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4190                 stats->etype_used = le16_to_cpu(resp->etype_used);
4191                 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4192                 stats->etype_free = le16_to_cpu(resp->etype_free);
4193         }
4194
4195         return status;
4196 }
4197
4198 /**
4199  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4200  * @hw: pointer to the hw struct
4201  * @seid: VSI seid to add ethertype filter from
4202  **/
4203 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4204 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4205                                                     u16 seid)
4206 {
4207         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4208                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4209                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4210         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4211         i40e_status status;
4212
4213         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4214                                                        seid, 0, true, NULL,
4215                                                        NULL);
4216         if (status)
4217                 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4218 }
4219
4220 /**
4221  * i40e_aq_alternate_read
4222  * @hw: pointer to the hardware structure
4223  * @reg_addr0: address of first dword to be read
4224  * @reg_val0: pointer for data read from 'reg_addr0'
4225  * @reg_addr1: address of second dword to be read
4226  * @reg_val1: pointer for data read from 'reg_addr1'
4227  *
4228  * Read one or two dwords from alternate structure. Fields are indicated
4229  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4230  * is not passed then only register at 'reg_addr0' is read.
4231  *
4232  **/
4233 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4234                                           u32 reg_addr0, u32 *reg_val0,
4235                                           u32 reg_addr1, u32 *reg_val1)
4236 {
4237         struct i40e_aq_desc desc;
4238         struct i40e_aqc_alternate_write *cmd_resp =
4239                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4240         i40e_status status;
4241
4242         if (!reg_val0)
4243                 return I40E_ERR_PARAM;
4244
4245         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4246         cmd_resp->address0 = cpu_to_le32(reg_addr0);
4247         cmd_resp->address1 = cpu_to_le32(reg_addr1);
4248
4249         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4250
4251         if (!status) {
4252                 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4253
4254                 if (reg_val1)
4255                         *reg_val1 = le32_to_cpu(cmd_resp->data1);
4256         }
4257
4258         return status;
4259 }
4260
4261 /**
4262  * i40e_aq_resume_port_tx
4263  * @hw: pointer to the hardware structure
4264  * @cmd_details: pointer to command details structure or NULL
4265  *
4266  * Resume port's Tx traffic
4267  **/
4268 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4269                                    struct i40e_asq_cmd_details *cmd_details)
4270 {
4271         struct i40e_aq_desc desc;
4272         i40e_status status;
4273
4274         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4275
4276         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4277
4278         return status;
4279 }
4280
4281 /**
4282  * i40e_set_pci_config_data - store PCI bus info
4283  * @hw: pointer to hardware structure
4284  * @link_status: the link status word from PCI config space
4285  *
4286  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4287  **/
4288 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4289 {
4290         hw->bus.type = i40e_bus_type_pci_express;
4291
4292         switch (link_status & PCI_EXP_LNKSTA_NLW) {
4293         case PCI_EXP_LNKSTA_NLW_X1:
4294                 hw->bus.width = i40e_bus_width_pcie_x1;
4295                 break;
4296         case PCI_EXP_LNKSTA_NLW_X2:
4297                 hw->bus.width = i40e_bus_width_pcie_x2;
4298                 break;
4299         case PCI_EXP_LNKSTA_NLW_X4:
4300                 hw->bus.width = i40e_bus_width_pcie_x4;
4301                 break;
4302         case PCI_EXP_LNKSTA_NLW_X8:
4303                 hw->bus.width = i40e_bus_width_pcie_x8;
4304                 break;
4305         default:
4306                 hw->bus.width = i40e_bus_width_unknown;
4307                 break;
4308         }
4309
4310         switch (link_status & PCI_EXP_LNKSTA_CLS) {
4311         case PCI_EXP_LNKSTA_CLS_2_5GB:
4312                 hw->bus.speed = i40e_bus_speed_2500;
4313                 break;
4314         case PCI_EXP_LNKSTA_CLS_5_0GB:
4315                 hw->bus.speed = i40e_bus_speed_5000;
4316                 break;
4317         case PCI_EXP_LNKSTA_CLS_8_0GB:
4318                 hw->bus.speed = i40e_bus_speed_8000;
4319                 break;
4320         default:
4321                 hw->bus.speed = i40e_bus_speed_unknown;
4322                 break;
4323         }
4324 }
4325
4326 /**
4327  * i40e_aq_debug_dump
4328  * @hw: pointer to the hardware structure
4329  * @cluster_id: specific cluster to dump
4330  * @table_id: table id within cluster
4331  * @start_index: index of line in the block to read
4332  * @buff_size: dump buffer size
4333  * @buff: dump buffer
4334  * @ret_buff_size: actual buffer size returned
4335  * @ret_next_table: next block to read
4336  * @ret_next_index: next index to read
4337  *
4338  * Dump internal FW/HW data for debug purposes.
4339  *
4340  **/
4341 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4342                                u8 table_id, u32 start_index, u16 buff_size,
4343                                void *buff, u16 *ret_buff_size,
4344                                u8 *ret_next_table, u32 *ret_next_index,
4345                                struct i40e_asq_cmd_details *cmd_details)
4346 {
4347         struct i40e_aq_desc desc;
4348         struct i40e_aqc_debug_dump_internals *cmd =
4349                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4350         struct i40e_aqc_debug_dump_internals *resp =
4351                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4352         i40e_status status;
4353
4354         if (buff_size == 0 || !buff)
4355                 return I40E_ERR_PARAM;
4356
4357         i40e_fill_default_direct_cmd_desc(&desc,
4358                                           i40e_aqc_opc_debug_dump_internals);
4359         /* Indirect Command */
4360         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4361         if (buff_size > I40E_AQ_LARGE_BUF)
4362                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4363
4364         cmd->cluster_id = cluster_id;
4365         cmd->table_id = table_id;
4366         cmd->idx = cpu_to_le32(start_index);
4367
4368         desc.datalen = cpu_to_le16(buff_size);
4369
4370         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4371         if (!status) {
4372                 if (ret_buff_size)
4373                         *ret_buff_size = le16_to_cpu(desc.datalen);
4374                 if (ret_next_table)
4375                         *ret_next_table = resp->table_id;
4376                 if (ret_next_index)
4377                         *ret_next_index = le32_to_cpu(resp->idx);
4378         }
4379
4380         return status;
4381 }
4382
4383 /**
4384  * i40e_read_bw_from_alt_ram
4385  * @hw: pointer to the hardware structure
4386  * @max_bw: pointer for max_bw read
4387  * @min_bw: pointer for min_bw read
4388  * @min_valid: pointer for bool that is true if min_bw is a valid value
4389  * @max_valid: pointer for bool that is true if max_bw is a valid value
4390  *
4391  * Read bw from the alternate ram for the given pf
4392  **/
4393 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4394                                       u32 *max_bw, u32 *min_bw,
4395                                       bool *min_valid, bool *max_valid)
4396 {
4397         i40e_status status;
4398         u32 max_bw_addr, min_bw_addr;
4399
4400         /* Calculate the address of the min/max bw registers */
4401         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4402                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
4403                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4404         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4405                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
4406                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4407
4408         /* Read the bandwidths from alt ram */
4409         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4410                                         min_bw_addr, min_bw);
4411
4412         if (*min_bw & I40E_ALT_BW_VALID_MASK)
4413                 *min_valid = true;
4414         else
4415                 *min_valid = false;
4416
4417         if (*max_bw & I40E_ALT_BW_VALID_MASK)
4418                 *max_valid = true;
4419         else
4420                 *max_valid = false;
4421
4422         return status;
4423 }
4424
4425 /**
4426  * i40e_aq_configure_partition_bw
4427  * @hw: pointer to the hardware structure
4428  * @bw_data: Buffer holding valid pfs and bw limits
4429  * @cmd_details: pointer to command details
4430  *
4431  * Configure partitions guaranteed/max bw
4432  **/
4433 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4434                         struct i40e_aqc_configure_partition_bw_data *bw_data,
4435                         struct i40e_asq_cmd_details *cmd_details)
4436 {
4437         i40e_status status;
4438         struct i40e_aq_desc desc;
4439         u16 bwd_size = sizeof(*bw_data);
4440
4441         i40e_fill_default_direct_cmd_desc(&desc,
4442                                           i40e_aqc_opc_configure_partition_bw);
4443
4444         /* Indirect command */
4445         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4446         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4447
4448         if (bwd_size > I40E_AQ_LARGE_BUF)
4449                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4450
4451         desc.datalen = cpu_to_le16(bwd_size);
4452
4453         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4454                                        cmd_details);
4455
4456         return status;
4457 }
4458
4459 /**
4460  * i40e_read_phy_register_clause22
4461  * @hw: pointer to the HW structure
4462  * @reg: register address in the page
4463  * @phy_adr: PHY address on MDIO interface
4464  * @value: PHY register value
4465  *
4466  * Reads specified PHY register value
4467  **/
4468 i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
4469                                             u16 reg, u8 phy_addr, u16 *value)
4470 {
4471         i40e_status status = I40E_ERR_TIMEOUT;
4472         u8 port_num = (u8)hw->func_caps.mdio_port_num;
4473         u32 command = 0;
4474         u16 retry = 1000;
4475
4476         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4477                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4478                   (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4479                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4480                   (I40E_GLGEN_MSCA_MDICMD_MASK);
4481         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4482         do {
4483                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4484                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4485                         status = 0;
4486                         break;
4487                 }
4488                 udelay(10);
4489                 retry--;
4490         } while (retry);
4491
4492         if (status) {
4493                 i40e_debug(hw, I40E_DEBUG_PHY,
4494                            "PHY: Can't write command to external PHY.\n");
4495         } else {
4496                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4497                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4498                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4499         }
4500
4501         return status;
4502 }
4503
4504 /**
4505  * i40e_write_phy_register_clause22
4506  * @hw: pointer to the HW structure
4507  * @reg: register address in the page
4508  * @phy_adr: PHY address on MDIO interface
4509  * @value: PHY register value
4510  *
4511  * Writes specified PHY register value
4512  **/
4513 i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
4514                                              u16 reg, u8 phy_addr, u16 value)
4515 {
4516         i40e_status status = I40E_ERR_TIMEOUT;
4517         u8 port_num = (u8)hw->func_caps.mdio_port_num;
4518         u32 command  = 0;
4519         u16 retry = 1000;
4520
4521         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4522         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4523
4524         command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4525                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4526                   (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4527                   (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4528                   (I40E_GLGEN_MSCA_MDICMD_MASK);
4529
4530         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4531         do {
4532                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4533                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4534                         status = 0;
4535                         break;
4536                 }
4537                 udelay(10);
4538                 retry--;
4539         } while (retry);
4540
4541         return status;
4542 }
4543
4544 /**
4545  * i40e_read_phy_register_clause45
4546  * @hw: pointer to the HW structure
4547  * @page: registers page number
4548  * @reg: register address in the page
4549  * @phy_adr: PHY address on MDIO interface
4550  * @value: PHY register value
4551  *
4552  * Reads specified PHY register value
4553  **/
4554 i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
4555                                 u8 page, u16 reg, u8 phy_addr, u16 *value)
4556 {
4557         i40e_status status = I40E_ERR_TIMEOUT;
4558         u32 command = 0;
4559         u16 retry = 1000;
4560         u8 port_num = hw->func_caps.mdio_port_num;
4561
4562         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4563                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4564                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4565                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4566                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4567                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4568                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4569         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4570         do {
4571                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4572                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4573                         status = 0;
4574                         break;
4575                 }
4576                 usleep_range(10, 20);
4577                 retry--;
4578         } while (retry);
4579
4580         if (status) {
4581                 i40e_debug(hw, I40E_DEBUG_PHY,
4582                            "PHY: Can't write command to external PHY.\n");
4583                 goto phy_read_end;
4584         }
4585
4586         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4587                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4588                   (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4589                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4590                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4591                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4592         status = I40E_ERR_TIMEOUT;
4593         retry = 1000;
4594         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4595         do {
4596                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4597                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4598                         status = 0;
4599                         break;
4600                 }
4601                 usleep_range(10, 20);
4602                 retry--;
4603         } while (retry);
4604
4605         if (!status) {
4606                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4607                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4608                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4609         } else {
4610                 i40e_debug(hw, I40E_DEBUG_PHY,
4611                            "PHY: Can't read register value from external PHY.\n");
4612         }
4613
4614 phy_read_end:
4615         return status;
4616 }
4617
4618 /**
4619  * i40e_write_phy_register_clause45
4620  * @hw: pointer to the HW structure
4621  * @page: registers page number
4622  * @reg: register address in the page
4623  * @phy_adr: PHY address on MDIO interface
4624  * @value: PHY register value
4625  *
4626  * Writes value to specified PHY register
4627  **/
4628 i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
4629                                 u8 page, u16 reg, u8 phy_addr, u16 value)
4630 {
4631         i40e_status status = I40E_ERR_TIMEOUT;
4632         u32 command = 0;
4633         u16 retry = 1000;
4634         u8 port_num = hw->func_caps.mdio_port_num;
4635
4636         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4637                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4638                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4639                   (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4640                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4641                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4642                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4643         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4644         do {
4645                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4646                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4647                         status = 0;
4648                         break;
4649                 }
4650                 usleep_range(10, 20);
4651                 retry--;
4652         } while (retry);
4653         if (status) {
4654                 i40e_debug(hw, I40E_DEBUG_PHY,
4655                            "PHY: Can't write command to external PHY.\n");
4656                 goto phy_write_end;
4657         }
4658
4659         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4660         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4661
4662         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4663                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4664                   (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4665                   (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4666                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4667                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4668         status = I40E_ERR_TIMEOUT;
4669         retry = 1000;
4670         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4671         do {
4672                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4673                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4674                         status = 0;
4675                         break;
4676                 }
4677                 usleep_range(10, 20);
4678                 retry--;
4679         } while (retry);
4680
4681 phy_write_end:
4682         return status;
4683 }
4684
4685 /**
4686  * i40e_write_phy_register
4687  * @hw: pointer to the HW structure
4688  * @page: registers page number
4689  * @reg: register address in the page
4690  * @phy_adr: PHY address on MDIO interface
4691  * @value: PHY register value
4692  *
4693  * Writes value to specified PHY register
4694  **/
4695 i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4696                                     u8 page, u16 reg, u8 phy_addr, u16 value)
4697 {
4698         i40e_status status;
4699
4700         switch (hw->device_id) {
4701         case I40E_DEV_ID_1G_BASE_T_X722:
4702                 status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4703                                                           value);
4704                 break;
4705         case I40E_DEV_ID_10G_BASE_T:
4706         case I40E_DEV_ID_10G_BASE_T4:
4707         case I40E_DEV_ID_10G_BASE_T_X722:
4708         case I40E_DEV_ID_25G_B:
4709         case I40E_DEV_ID_25G_SFP28:
4710                 status = i40e_write_phy_register_clause45(hw, page, reg,
4711                                                           phy_addr, value);
4712                 break;
4713         default:
4714                 status = I40E_ERR_UNKNOWN_PHY;
4715                 break;
4716         }
4717
4718         return status;
4719 }
4720
4721 /**
4722  * i40e_read_phy_register
4723  * @hw: pointer to the HW structure
4724  * @page: registers page number
4725  * @reg: register address in the page
4726  * @phy_adr: PHY address on MDIO interface
4727  * @value: PHY register value
4728  *
4729  * Reads specified PHY register value
4730  **/
4731 i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4732                                    u8 page, u16 reg, u8 phy_addr, u16 *value)
4733 {
4734         i40e_status status;
4735
4736         switch (hw->device_id) {
4737         case I40E_DEV_ID_1G_BASE_T_X722:
4738                 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4739                                                          value);
4740                 break;
4741         case I40E_DEV_ID_10G_BASE_T:
4742         case I40E_DEV_ID_10G_BASE_T4:
4743         case I40E_DEV_ID_10G_BASE_T_X722:
4744         case I40E_DEV_ID_25G_B:
4745         case I40E_DEV_ID_25G_SFP28:
4746                 status = i40e_read_phy_register_clause45(hw, page, reg,
4747                                                          phy_addr, value);
4748                 break;
4749         default:
4750                 status = I40E_ERR_UNKNOWN_PHY;
4751                 break;
4752         }
4753
4754         return status;
4755 }
4756
4757 /**
4758  * i40e_get_phy_address
4759  * @hw: pointer to the HW structure
4760  * @dev_num: PHY port num that address we want
4761  * @phy_addr: Returned PHY address
4762  *
4763  * Gets PHY address for current port
4764  **/
4765 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4766 {
4767         u8 port_num = hw->func_caps.mdio_port_num;
4768         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4769
4770         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4771 }
4772
4773 /**
4774  * i40e_blink_phy_led
4775  * @hw: pointer to the HW structure
4776  * @time: time how long led will blinks in secs
4777  * @interval: gap between LED on and off in msecs
4778  *
4779  * Blinks PHY link LED
4780  **/
4781 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4782                                     u32 time, u32 interval)
4783 {
4784         i40e_status status = 0;
4785         u32 i;
4786         u16 led_ctl;
4787         u16 gpio_led_port;
4788         u16 led_reg;
4789         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4790         u8 phy_addr = 0;
4791         u8 port_num;
4792
4793         i = rd32(hw, I40E_PFGEN_PORTNUM);
4794         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4795         phy_addr = i40e_get_phy_address(hw, port_num);
4796
4797         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4798              led_addr++) {
4799                 status = i40e_read_phy_register_clause45(hw,
4800                                                          I40E_PHY_COM_REG_PAGE,
4801                                                          led_addr, phy_addr,
4802                                                          &led_reg);
4803                 if (status)
4804                         goto phy_blinking_end;
4805                 led_ctl = led_reg;
4806                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4807                         led_reg = 0;
4808                         status = i40e_write_phy_register_clause45(hw,
4809                                                          I40E_PHY_COM_REG_PAGE,
4810                                                          led_addr, phy_addr,
4811                                                          led_reg);
4812                         if (status)
4813                                 goto phy_blinking_end;
4814                         break;
4815                 }
4816         }
4817
4818         if (time > 0 && interval > 0) {
4819                 for (i = 0; i < time * 1000; i += interval) {
4820                         status = i40e_read_phy_register_clause45(hw,
4821                                                 I40E_PHY_COM_REG_PAGE,
4822                                                 led_addr, phy_addr, &led_reg);
4823                         if (status)
4824                                 goto restore_config;
4825                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
4826                                 led_reg = 0;
4827                         else
4828                                 led_reg = I40E_PHY_LED_MANUAL_ON;
4829                         status = i40e_write_phy_register_clause45(hw,
4830                                                 I40E_PHY_COM_REG_PAGE,
4831                                                 led_addr, phy_addr, led_reg);
4832                         if (status)
4833                                 goto restore_config;
4834                         msleep(interval);
4835                 }
4836         }
4837
4838 restore_config:
4839         status = i40e_write_phy_register_clause45(hw,
4840                                                   I40E_PHY_COM_REG_PAGE,
4841                                                   led_addr, phy_addr, led_ctl);
4842
4843 phy_blinking_end:
4844         return status;
4845 }
4846
4847 /**
4848  * i40e_led_get_phy - return current on/off mode
4849  * @hw: pointer to the hw struct
4850  * @led_addr: address of led register to use
4851  * @val: original value of register to use
4852  *
4853  **/
4854 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4855                              u16 *val)
4856 {
4857         i40e_status status = 0;
4858         u16 gpio_led_port;
4859         u8 phy_addr = 0;
4860         u16 reg_val;
4861         u16 temp_addr;
4862         u8 port_num;
4863         u32 i;
4864
4865         temp_addr = I40E_PHY_LED_PROV_REG_1;
4866         i = rd32(hw, I40E_PFGEN_PORTNUM);
4867         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4868         phy_addr = i40e_get_phy_address(hw, port_num);
4869
4870         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4871              temp_addr++) {
4872                 status = i40e_read_phy_register_clause45(hw,
4873                                                          I40E_PHY_COM_REG_PAGE,
4874                                                          temp_addr, phy_addr,
4875                                                          &reg_val);
4876                 if (status)
4877                         return status;
4878                 *val = reg_val;
4879                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4880                         *led_addr = temp_addr;
4881                         break;
4882                 }
4883         }
4884         return status;
4885 }
4886
4887 /**
4888  * i40e_led_set_phy
4889  * @hw: pointer to the HW structure
4890  * @on: true or false
4891  * @mode: original val plus bit for set or ignore
4892  * Set led's on or off when controlled by the PHY
4893  *
4894  **/
4895 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
4896                              u16 led_addr, u32 mode)
4897 {
4898         i40e_status status = 0;
4899         u16 led_ctl = 0;
4900         u16 led_reg = 0;
4901         u8 phy_addr = 0;
4902         u8 port_num;
4903         u32 i;
4904
4905         i = rd32(hw, I40E_PFGEN_PORTNUM);
4906         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4907         phy_addr = i40e_get_phy_address(hw, port_num);
4908         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4909                                                  led_addr, phy_addr, &led_reg);
4910         if (status)
4911                 return status;
4912         led_ctl = led_reg;
4913         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4914                 led_reg = 0;
4915                 status = i40e_write_phy_register_clause45(hw,
4916                                                           I40E_PHY_COM_REG_PAGE,
4917                                                           led_addr, phy_addr,
4918                                                           led_reg);
4919                 if (status)
4920                         return status;
4921         }
4922         status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4923                                                  led_addr, phy_addr, &led_reg);
4924         if (status)
4925                 goto restore_config;
4926         if (on)
4927                 led_reg = I40E_PHY_LED_MANUAL_ON;
4928         else
4929                 led_reg = 0;
4930         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4931                                                   led_addr, phy_addr, led_reg);
4932         if (status)
4933                 goto restore_config;
4934         if (mode & I40E_PHY_LED_MODE_ORIG) {
4935                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4936                 status = i40e_write_phy_register_clause45(hw,
4937                                                  I40E_PHY_COM_REG_PAGE,
4938                                                  led_addr, phy_addr, led_ctl);
4939         }
4940         return status;
4941 restore_config:
4942         status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4943                                                   led_addr, phy_addr, led_ctl);
4944         return status;
4945 }
4946
4947 /**
4948  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4949  * @hw: pointer to the hw struct
4950  * @reg_addr: register address
4951  * @reg_val: ptr to register value
4952  * @cmd_details: pointer to command details structure or NULL
4953  *
4954  * Use the firmware to read the Rx control register,
4955  * especially useful if the Rx unit is under heavy pressure
4956  **/
4957 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4958                                 u32 reg_addr, u32 *reg_val,
4959                                 struct i40e_asq_cmd_details *cmd_details)
4960 {
4961         struct i40e_aq_desc desc;
4962         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4963                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4964         i40e_status status;
4965
4966         if (!reg_val)
4967                 return I40E_ERR_PARAM;
4968
4969         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4970
4971         cmd_resp->address = cpu_to_le32(reg_addr);
4972
4973         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4974
4975         if (status == 0)
4976                 *reg_val = le32_to_cpu(cmd_resp->value);
4977
4978         return status;
4979 }
4980
4981 /**
4982  * i40e_read_rx_ctl - read from an Rx control register
4983  * @hw: pointer to the hw struct
4984  * @reg_addr: register address
4985  **/
4986 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4987 {
4988         i40e_status status = 0;
4989         bool use_register;
4990         int retry = 5;
4991         u32 val = 0;
4992
4993         use_register = (((hw->aq.api_maj_ver == 1) &&
4994                         (hw->aq.api_min_ver < 5)) ||
4995                         (hw->mac.type == I40E_MAC_X722));
4996         if (!use_register) {
4997 do_retry:
4998                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4999                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5000                         usleep_range(1000, 2000);
5001                         retry--;
5002                         goto do_retry;
5003                 }
5004         }
5005
5006         /* if the AQ access failed, try the old-fashioned way */
5007         if (status || use_register)
5008                 val = rd32(hw, reg_addr);
5009
5010         return val;
5011 }
5012
5013 /**
5014  * i40e_aq_rx_ctl_write_register
5015  * @hw: pointer to the hw struct
5016  * @reg_addr: register address
5017  * @reg_val: register value
5018  * @cmd_details: pointer to command details structure or NULL
5019  *
5020  * Use the firmware to write to an Rx control register,
5021  * especially useful if the Rx unit is under heavy pressure
5022  **/
5023 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
5024                                 u32 reg_addr, u32 reg_val,
5025                                 struct i40e_asq_cmd_details *cmd_details)
5026 {
5027         struct i40e_aq_desc desc;
5028         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
5029                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5030         i40e_status status;
5031
5032         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
5033
5034         cmd->address = cpu_to_le32(reg_addr);
5035         cmd->value = cpu_to_le32(reg_val);
5036
5037         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5038
5039         return status;
5040 }
5041
5042 /**
5043  * i40e_write_rx_ctl - write to an Rx control register
5044  * @hw: pointer to the hw struct
5045  * @reg_addr: register address
5046  * @reg_val: register value
5047  **/
5048 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5049 {
5050         i40e_status status = 0;
5051         bool use_register;
5052         int retry = 5;
5053
5054         use_register = (((hw->aq.api_maj_ver == 1) &&
5055                         (hw->aq.api_min_ver < 5)) ||
5056                         (hw->mac.type == I40E_MAC_X722));
5057         if (!use_register) {
5058 do_retry:
5059                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5060                                                        reg_val, NULL);
5061                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5062                         usleep_range(1000, 2000);
5063                         retry--;
5064                         goto do_retry;
5065                 }
5066         }
5067
5068         /* if the AQ access failed, try the old-fashioned way */
5069         if (status || use_register)
5070                 wr32(hw, reg_addr, reg_val);
5071 }
5072
5073 /**
5074  * i40e_aq_write_ppp - Write pipeline personalization profile (ppp)
5075  * @hw: pointer to the hw struct
5076  * @buff: command buffer (size in bytes = buff_size)
5077  * @buff_size: buffer size in bytes
5078  * @track_id: package tracking id
5079  * @error_offset: returns error offset
5080  * @error_info: returns error information
5081  * @cmd_details: pointer to command details structure or NULL
5082  **/
5083 enum
5084 i40e_status_code i40e_aq_write_ppp(struct i40e_hw *hw, void *buff,
5085                                    u16 buff_size, u32 track_id,
5086                                    u32 *error_offset, u32 *error_info,
5087                                    struct i40e_asq_cmd_details *cmd_details)
5088 {
5089         struct i40e_aq_desc desc;
5090         struct i40e_aqc_write_personalization_profile *cmd =
5091                 (struct i40e_aqc_write_personalization_profile *)
5092                 &desc.params.raw;
5093         struct i40e_aqc_write_ppp_resp *resp;
5094         i40e_status status;
5095
5096         i40e_fill_default_direct_cmd_desc(&desc,
5097                                           i40e_aqc_opc_write_personalization_profile);
5098
5099         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5100         if (buff_size > I40E_AQ_LARGE_BUF)
5101                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5102
5103         desc.datalen = cpu_to_le16(buff_size);
5104
5105         cmd->profile_track_id = cpu_to_le32(track_id);
5106
5107         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5108         if (!status) {
5109                 resp = (struct i40e_aqc_write_ppp_resp *)&desc.params.raw;
5110                 if (error_offset)
5111                         *error_offset = le32_to_cpu(resp->error_offset);
5112                 if (error_info)
5113                         *error_info = le32_to_cpu(resp->error_info);
5114         }
5115
5116         return status;
5117 }
5118
5119 /**
5120  * i40e_aq_get_ppp_list - Read pipeline personalization profile (ppp)
5121  * @hw: pointer to the hw struct
5122  * @buff: command buffer (size in bytes = buff_size)
5123  * @buff_size: buffer size in bytes
5124  * @cmd_details: pointer to command details structure or NULL
5125  **/
5126 enum
5127 i40e_status_code i40e_aq_get_ppp_list(struct i40e_hw *hw, void *buff,
5128                                       u16 buff_size, u8 flags,
5129                                       struct i40e_asq_cmd_details *cmd_details)
5130 {
5131         struct i40e_aq_desc desc;
5132         struct i40e_aqc_get_applied_profiles *cmd =
5133                 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5134         i40e_status status;
5135
5136         i40e_fill_default_direct_cmd_desc(&desc,
5137                                           i40e_aqc_opc_get_personalization_profile_list);
5138
5139         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5140         if (buff_size > I40E_AQ_LARGE_BUF)
5141                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5142         desc.datalen = cpu_to_le16(buff_size);
5143
5144         cmd->flags = flags;
5145
5146         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5147
5148         return status;
5149 }
5150
5151 /**
5152  * i40e_find_segment_in_package
5153  * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
5154  * @pkg_hdr: pointer to the package header to be searched
5155  *
5156  * This function searches a package file for a particular segment type. On
5157  * success it returns a pointer to the segment header, otherwise it will
5158  * return NULL.
5159  **/
5160 struct i40e_generic_seg_header *
5161 i40e_find_segment_in_package(u32 segment_type,
5162                              struct i40e_package_header *pkg_hdr)
5163 {
5164         struct i40e_generic_seg_header *segment;
5165         u32 i;
5166
5167         /* Search all package segments for the requested segment type */
5168         for (i = 0; i < pkg_hdr->segment_count; i++) {
5169                 segment =
5170                         (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5171                          pkg_hdr->segment_offset[i]);
5172
5173                 if (segment->type == segment_type)
5174                         return segment;
5175         }
5176
5177         return NULL;
5178 }
5179
5180 /**
5181  * i40e_write_profile
5182  * @hw: pointer to the hardware structure
5183  * @profile: pointer to the profile segment of the package to be downloaded
5184  * @track_id: package tracking id
5185  *
5186  * Handles the download of a complete package.
5187  */
5188 enum i40e_status_code
5189 i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5190                    u32 track_id)
5191 {
5192         i40e_status status = 0;
5193         struct i40e_section_table *sec_tbl;
5194         struct i40e_profile_section_header *sec = NULL;
5195         u32 dev_cnt;
5196         u32 vendor_dev_id;
5197         u32 *nvm;
5198         u32 section_size = 0;
5199         u32 offset = 0, info = 0;
5200         u32 i;
5201
5202         if (!track_id) {
5203                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Track_id can't be 0.");
5204                 return I40E_NOT_SUPPORTED;
5205         }
5206
5207         dev_cnt = profile->device_table_count;
5208
5209         for (i = 0; i < dev_cnt; i++) {
5210                 vendor_dev_id = profile->device_table[i].vendor_dev_id;
5211                 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL)
5212                         if (hw->device_id == (vendor_dev_id & 0xFFFF))
5213                                 break;
5214         }
5215         if (i == dev_cnt) {
5216                 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support PPP");
5217                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5218         }
5219
5220         nvm = (u32 *)&profile->device_table[dev_cnt];
5221         sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
5222
5223         for (i = 0; i < sec_tbl->section_count; i++) {
5224                 sec = (struct i40e_profile_section_header *)((u8 *)profile +
5225                                              sec_tbl->section_offset[i]);
5226
5227                 /* Skip 'AQ', 'note' and 'name' sections */
5228                 if (sec->section.type != SECTION_TYPE_MMIO)
5229                         continue;
5230
5231                 section_size = sec->section.size +
5232                         sizeof(struct i40e_profile_section_header);
5233
5234                 /* Write profile */
5235                 status = i40e_aq_write_ppp(hw, (void *)sec, (u16)section_size,
5236                                            track_id, &offset, &info, NULL);
5237                 if (status) {
5238                         i40e_debug(hw, I40E_DEBUG_PACKAGE,
5239                                    "Failed to write profile: offset %d, info %d",
5240                                    offset, info);
5241                         break;
5242                 }
5243         }
5244         return status;
5245 }
5246
5247 /**
5248  * i40e_add_pinfo_to_list
5249  * @hw: pointer to the hardware structure
5250  * @profile: pointer to the profile segment of the package
5251  * @profile_info_sec: buffer for information section
5252  * @track_id: package tracking id
5253  *
5254  * Register a profile to the list of loaded profiles.
5255  */
5256 enum i40e_status_code
5257 i40e_add_pinfo_to_list(struct i40e_hw *hw,
5258                        struct i40e_profile_segment *profile,
5259                        u8 *profile_info_sec, u32 track_id)
5260 {
5261         i40e_status status = 0;
5262         struct i40e_profile_section_header *sec = NULL;
5263         struct i40e_profile_info *pinfo;
5264         u32 offset = 0, info = 0;
5265
5266         sec = (struct i40e_profile_section_header *)profile_info_sec;
5267         sec->tbl_size = 1;
5268         sec->data_end = sizeof(struct i40e_profile_section_header) +
5269                         sizeof(struct i40e_profile_info);
5270         sec->section.type = SECTION_TYPE_INFO;
5271         sec->section.offset = sizeof(struct i40e_profile_section_header);
5272         sec->section.size = sizeof(struct i40e_profile_info);
5273         pinfo = (struct i40e_profile_info *)(profile_info_sec +
5274                                              sec->section.offset);
5275         pinfo->track_id = track_id;
5276         pinfo->version = profile->version;
5277         pinfo->op = I40E_PPP_ADD_TRACKID;
5278         memcpy(pinfo->name, profile->name, I40E_PPP_NAME_SIZE);
5279
5280         status = i40e_aq_write_ppp(hw, (void *)sec, sec->data_end,
5281                                    track_id, &offset, &info, NULL);
5282         return status;
5283 }