drivers/net/ethernet/intel/i40e/i40e_common.c

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2016 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #include "i40e_type.h"
  28 #include "i40e_adminq.h"
  29 #include "i40e_prototype.h"
  30 #include "i40e_virtchnl.h"
  31
  32 /**
  33  * i40e_set_mac_type - Sets MAC type
  34  * @hw: pointer to the HW structure
  35  *
  36  * This function sets the mac type of the adapter based on the
  37  * vendor ID and device ID stored in the hw structure.
  38  **/
  39 static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
  40 {
  41         i40e_status status = 0;
  42
  43         if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
  44                 switch (hw->device_id) {
  45                 case I40E_DEV_ID_SFP_XL710:
  46                 case I40E_DEV_ID_QEMU:
  47                 case I40E_DEV_ID_KX_B:
  48                 case I40E_DEV_ID_KX_C:
  49                 case I40E_DEV_ID_QSFP_A:
  50                 case I40E_DEV_ID_QSFP_B:
  51                 case I40E_DEV_ID_QSFP_C:
  52                 case I40E_DEV_ID_10G_BASE_T:
  53                 case I40E_DEV_ID_10G_BASE_T4:
  54                 case I40E_DEV_ID_20G_KR2:
  55                 case I40E_DEV_ID_20G_KR2_A:
  56                         hw->mac.type = I40E_MAC_XL710;
  57                         break;
  58                 case I40E_DEV_ID_KX_X722:
  59                 case I40E_DEV_ID_QSFP_X722:
  60                 case I40E_DEV_ID_SFP_X722:
  61                 case I40E_DEV_ID_1G_BASE_T_X722:
  62                 case I40E_DEV_ID_10G_BASE_T_X722:
  63                 case I40E_DEV_ID_SFP_I_X722:
  64                         hw->mac.type = I40E_MAC_X722;
  65                         break;
  66                 default:
  67                         hw->mac.type = I40E_MAC_GENERIC;
  68                         break;
  69                 }
  70         } else {
  71                 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
  72         }
  73
  74         hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
  75                   hw->mac.type, status);
  76         return status;
  77 }
  78
  79 /**
  80  * i40e_aq_str - convert AQ err code to a string
  81  * @hw: pointer to the HW structure
  82  * @aq_err: the AQ error code to convert
  83  **/
  84 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
  85 {
  86         switch (aq_err) {
  87         case I40E_AQ_RC_OK:
  88                 return "OK";
  89         case I40E_AQ_RC_EPERM:
  90                 return "I40E_AQ_RC_EPERM";
  91         case I40E_AQ_RC_ENOENT:
  92                 return "I40E_AQ_RC_ENOENT";
  93         case I40E_AQ_RC_ESRCH:
  94                 return "I40E_AQ_RC_ESRCH";
  95         case I40E_AQ_RC_EINTR:
  96                 return "I40E_AQ_RC_EINTR";
  97         case I40E_AQ_RC_EIO:
  98                 return "I40E_AQ_RC_EIO";
  99         case I40E_AQ_RC_ENXIO:
 100                 return "I40E_AQ_RC_ENXIO";
 101         case I40E_AQ_RC_E2BIG:
 102                 return "I40E_AQ_RC_E2BIG";
 103         case I40E_AQ_RC_EAGAIN:
 104                 return "I40E_AQ_RC_EAGAIN";
 105         case I40E_AQ_RC_ENOMEM:
 106                 return "I40E_AQ_RC_ENOMEM";
 107         case I40E_AQ_RC_EACCES:
 108                 return "I40E_AQ_RC_EACCES";
 109         case I40E_AQ_RC_EFAULT:
 110                 return "I40E_AQ_RC_EFAULT";
 111         case I40E_AQ_RC_EBUSY:
 112                 return "I40E_AQ_RC_EBUSY";
 113         case I40E_AQ_RC_EEXIST:
 114                 return "I40E_AQ_RC_EEXIST";
 115         case I40E_AQ_RC_EINVAL:
 116                 return "I40E_AQ_RC_EINVAL";
 117         case I40E_AQ_RC_ENOTTY:
 118                 return "I40E_AQ_RC_ENOTTY";
 119         case I40E_AQ_RC_ENOSPC:
 120                 return "I40E_AQ_RC_ENOSPC";
 121         case I40E_AQ_RC_ENOSYS:
 122                 return "I40E_AQ_RC_ENOSYS";
 123         case I40E_AQ_RC_ERANGE:
 124                 return "I40E_AQ_RC_ERANGE";
 125         case I40E_AQ_RC_EFLUSHED:
 126                 return "I40E_AQ_RC_EFLUSHED";
 127         case I40E_AQ_RC_BAD_ADDR:
 128                 return "I40E_AQ_RC_BAD_ADDR";
 129         case I40E_AQ_RC_EMODE:
 130                 return "I40E_AQ_RC_EMODE";
 131         case I40E_AQ_RC_EFBIG:
 132                 return "I40E_AQ_RC_EFBIG";
 133         }
 134
 135         snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
 136         return hw->err_str;
 137 }
 138
 139 /**
 140  * i40e_stat_str - convert status err code to a string
 141  * @hw: pointer to the HW structure
 142  * @stat_err: the status error code to convert
 143  **/
 144 const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
 145 {
 146         switch (stat_err) {
 147         case 0:
 148                 return "OK";
 149         case I40E_ERR_NVM:
 150                 return "I40E_ERR_NVM";
 151         case I40E_ERR_NVM_CHECKSUM:
 152                 return "I40E_ERR_NVM_CHECKSUM";
 153         case I40E_ERR_PHY:
 154                 return "I40E_ERR_PHY";
 155         case I40E_ERR_CONFIG:
 156                 return "I40E_ERR_CONFIG";
 157         case I40E_ERR_PARAM:
 158                 return "I40E_ERR_PARAM";
 159         case I40E_ERR_MAC_TYPE:
 160                 return "I40E_ERR_MAC_TYPE";
 161         case I40E_ERR_UNKNOWN_PHY:
 162                 return "I40E_ERR_UNKNOWN_PHY";
 163         case I40E_ERR_LINK_SETUP:
 164                 return "I40E_ERR_LINK_SETUP";
 165         case I40E_ERR_ADAPTER_STOPPED:
 166                 return "I40E_ERR_ADAPTER_STOPPED";
 167         case I40E_ERR_INVALID_MAC_ADDR:
 168                 return "I40E_ERR_INVALID_MAC_ADDR";
 169         case I40E_ERR_DEVICE_NOT_SUPPORTED:
 170                 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
 171         case I40E_ERR_MASTER_REQUESTS_PENDING:
 172                 return "I40E_ERR_MASTER_REQUESTS_PENDING";
 173         case I40E_ERR_INVALID_LINK_SETTINGS:
 174                 return "I40E_ERR_INVALID_LINK_SETTINGS";
 175         case I40E_ERR_AUTONEG_NOT_COMPLETE:
 176                 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
 177         case I40E_ERR_RESET_FAILED:
 178                 return "I40E_ERR_RESET_FAILED";
 179         case I40E_ERR_SWFW_SYNC:
 180                 return "I40E_ERR_SWFW_SYNC";
 181         case I40E_ERR_NO_AVAILABLE_VSI:
 182                 return "I40E_ERR_NO_AVAILABLE_VSI";
 183         case I40E_ERR_NO_MEMORY:
 184                 return "I40E_ERR_NO_MEMORY";
 185         case I40E_ERR_BAD_PTR:
 186                 return "I40E_ERR_BAD_PTR";
 187         case I40E_ERR_RING_FULL:
 188                 return "I40E_ERR_RING_FULL";
 189         case I40E_ERR_INVALID_PD_ID:
 190                 return "I40E_ERR_INVALID_PD_ID";
 191         case I40E_ERR_INVALID_QP_ID:
 192                 return "I40E_ERR_INVALID_QP_ID";
 193         case I40E_ERR_INVALID_CQ_ID:
 194                 return "I40E_ERR_INVALID_CQ_ID";
 195         case I40E_ERR_INVALID_CEQ_ID:
 196                 return "I40E_ERR_INVALID_CEQ_ID";
 197         case I40E_ERR_INVALID_AEQ_ID:
 198                 return "I40E_ERR_INVALID_AEQ_ID";
 199         case I40E_ERR_INVALID_SIZE:
 200                 return "I40E_ERR_INVALID_SIZE";
 201         case I40E_ERR_INVALID_ARP_INDEX:
 202                 return "I40E_ERR_INVALID_ARP_INDEX";
 203         case I40E_ERR_INVALID_FPM_FUNC_ID:
 204                 return "I40E_ERR_INVALID_FPM_FUNC_ID";
 205         case I40E_ERR_QP_INVALID_MSG_SIZE:
 206                 return "I40E_ERR_QP_INVALID_MSG_SIZE";
 207         case I40E_ERR_QP_TOOMANY_WRS_POSTED:
 208                 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
 209         case I40E_ERR_INVALID_FRAG_COUNT:
 210                 return "I40E_ERR_INVALID_FRAG_COUNT";
 211         case I40E_ERR_QUEUE_EMPTY:
 212                 return "I40E_ERR_QUEUE_EMPTY";
 213         case I40E_ERR_INVALID_ALIGNMENT:
 214                 return "I40E_ERR_INVALID_ALIGNMENT";
 215         case I40E_ERR_FLUSHED_QUEUE:
 216                 return "I40E_ERR_FLUSHED_QUEUE";
 217         case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
 218                 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
 219         case I40E_ERR_INVALID_IMM_DATA_SIZE:
 220                 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
 221         case I40E_ERR_TIMEOUT:
 222                 return "I40E_ERR_TIMEOUT";
 223         case I40E_ERR_OPCODE_MISMATCH:
 224                 return "I40E_ERR_OPCODE_MISMATCH";
 225         case I40E_ERR_CQP_COMPL_ERROR:
 226                 return "I40E_ERR_CQP_COMPL_ERROR";
 227         case I40E_ERR_INVALID_VF_ID:
 228                 return "I40E_ERR_INVALID_VF_ID";
 229         case I40E_ERR_INVALID_HMCFN_ID:
 230                 return "I40E_ERR_INVALID_HMCFN_ID";
 231         case I40E_ERR_BACKING_PAGE_ERROR:
 232                 return "I40E_ERR_BACKING_PAGE_ERROR";
 233         case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
 234                 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
 235         case I40E_ERR_INVALID_PBLE_INDEX:
 236                 return "I40E_ERR_INVALID_PBLE_INDEX";
 237         case I40E_ERR_INVALID_SD_INDEX:
 238                 return "I40E_ERR_INVALID_SD_INDEX";
 239         case I40E_ERR_INVALID_PAGE_DESC_INDEX:
 240                 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
 241         case I40E_ERR_INVALID_SD_TYPE:
 242                 return "I40E_ERR_INVALID_SD_TYPE";
 243         case I40E_ERR_MEMCPY_FAILED:
 244                 return "I40E_ERR_MEMCPY_FAILED";
 245         case I40E_ERR_INVALID_HMC_OBJ_INDEX:
 246                 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
 247         case I40E_ERR_INVALID_HMC_OBJ_COUNT:
 248                 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
 249         case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
 250                 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
 251         case I40E_ERR_SRQ_ENABLED:
 252                 return "I40E_ERR_SRQ_ENABLED";
 253         case I40E_ERR_ADMIN_QUEUE_ERROR:
 254                 return "I40E_ERR_ADMIN_QUEUE_ERROR";
 255         case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
 256                 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
 257         case I40E_ERR_BUF_TOO_SHORT:
 258                 return "I40E_ERR_BUF_TOO_SHORT";
 259         case I40E_ERR_ADMIN_QUEUE_FULL:
 260                 return "I40E_ERR_ADMIN_QUEUE_FULL";
 261         case I40E_ERR_ADMIN_QUEUE_NO_WORK:
 262                 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
 263         case I40E_ERR_BAD_IWARP_CQE:
 264                 return "I40E_ERR_BAD_IWARP_CQE";
 265         case I40E_ERR_NVM_BLANK_MODE:
 266                 return "I40E_ERR_NVM_BLANK_MODE";
 267         case I40E_ERR_NOT_IMPLEMENTED:
 268                 return "I40E_ERR_NOT_IMPLEMENTED";
 269         case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
 270                 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
 271         case I40E_ERR_DIAG_TEST_FAILED:
 272                 return "I40E_ERR_DIAG_TEST_FAILED";
 273         case I40E_ERR_NOT_READY:
 274                 return "I40E_ERR_NOT_READY";
 275         case I40E_NOT_SUPPORTED:
 276                 return "I40E_NOT_SUPPORTED";
 277         case I40E_ERR_FIRMWARE_API_VERSION:
 278                 return "I40E_ERR_FIRMWARE_API_VERSION";
 279         }
 280
 281         snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
 282         return hw->err_str;
 283 }
 284
 285 /**
 286  * i40e_debug_aq
 287  * @hw: debug mask related to admin queue
 288  * @mask: debug mask
 289  * @desc: pointer to admin queue descriptor
 290  * @buffer: pointer to command buffer
 291  * @buf_len: max length of buffer
 292  *
 293  * Dumps debug log about adminq command with descriptor contents.
 294  **/
 295 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
 296                    void *buffer, u16 buf_len)
 297 {
 298         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
 299         u16 len;
 300         u8 *buf = (u8 *)buffer;
 301         u16 i = 0;
 302
 303         if ((!(mask & hw->debug_mask)) || (desc == NULL))
 304                 return;
 305
 306         len = le16_to_cpu(aq_desc->datalen);
 307
 308         i40e_debug(hw, mask,
 309                    "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
 310                    le16_to_cpu(aq_desc->opcode),
 311                    le16_to_cpu(aq_desc->flags),
 312                    le16_to_cpu(aq_desc->datalen),
 313                    le16_to_cpu(aq_desc->retval));
 314         i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
 315                    le32_to_cpu(aq_desc->cookie_high),
 316                    le32_to_cpu(aq_desc->cookie_low));
 317         i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
 318                    le32_to_cpu(aq_desc->params.internal.param0),
 319                    le32_to_cpu(aq_desc->params.internal.param1));
 320         i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
 321                    le32_to_cpu(aq_desc->params.external.addr_high),
 322                    le32_to_cpu(aq_desc->params.external.addr_low));
 323
 324         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
 325                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
 326                 if (buf_len < len)
 327                         len = buf_len;
 328                 /* write the full 16-byte chunks */
 329                 for (i = 0; i < (len - 16); i += 16)
 330                         i40e_debug(hw, mask, "\t0x%04X  %16ph\n", i, buf + i);
 331                 /* write whatever's left over without overrunning the buffer */
 332                 if (i < len)
 333                         i40e_debug(hw, mask, "\t0x%04X  %*ph\n",
 334                                              i, len - i, buf + i);
 335         }
 336 }
 337
 338 /**
 339  * i40e_check_asq_alive
 340  * @hw: pointer to the hw struct
 341  *
 342  * Returns true if Queue is enabled else false.
 343  **/
 344 bool i40e_check_asq_alive(struct i40e_hw *hw)
 345 {
 346         if (hw->aq.asq.len)
 347                 return !!(rd32(hw, hw->aq.asq.len) &
 348                           I40E_PF_ATQLEN_ATQENABLE_MASK);
 349         else
 350                 return false;
 351 }
 352
 353 /**
 354  * i40e_aq_queue_shutdown
 355  * @hw: pointer to the hw struct
 356  * @unloading: is the driver unloading itself
 357  *
 358  * Tell the Firmware that we're shutting down the AdminQ and whether
 359  * or not the driver is unloading as well.
 360  **/
 361 i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
 362                                              bool unloading)
 363 {
 364         struct i40e_aq_desc desc;
 365         struct i40e_aqc_queue_shutdown *cmd =
 366                 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
 367         i40e_status status;
 368
 369         i40e_fill_default_direct_cmd_desc(&desc,
 370                                           i40e_aqc_opc_queue_shutdown);
 371
 372         if (unloading)
 373                 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
 374         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 375
 376         return status;
 377 }
 378
 379 /**
 380  * i40e_aq_get_set_rss_lut
 381  * @hw: pointer to the hardware structure
 382  * @vsi_id: vsi fw index
 383  * @pf_lut: for PF table set true, for VSI table set false
 384  * @lut: pointer to the lut buffer provided by the caller
 385  * @lut_size: size of the lut buffer
 386  * @set: set true to set the table, false to get the table
 387  *
 388  * Internal function to get or set RSS look up table
 389  **/
 390 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
 391                                            u16 vsi_id, bool pf_lut,
 392                                            u8 *lut, u16 lut_size,
 393                                            bool set)
 394 {
 395         i40e_status status;
 396         struct i40e_aq_desc desc;
 397         struct i40e_aqc_get_set_rss_lut *cmd_resp =
 398                    (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
 399
 400         if (set)
 401                 i40e_fill_default_direct_cmd_desc(&desc,
 402                                                   i40e_aqc_opc_set_rss_lut);
 403         else
 404                 i40e_fill_default_direct_cmd_desc(&desc,
 405                                                   i40e_aqc_opc_get_rss_lut);
 406
 407         /* Indirect command */
 408         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
 409         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
 410
 411         cmd_resp->vsi_id =
 412                         cpu_to_le16((u16)((vsi_id <<
 413                                           I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
 414                                           I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
 415         cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
 416
 417         if (pf_lut)
 418                 cmd_resp->flags |= cpu_to_le16((u16)
 419                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
 420                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 421                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 422         else
 423                 cmd_resp->flags |= cpu_to_le16((u16)
 424                                         ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
 425                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
 426                                         I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
 427
 428         status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
 429
 430         return status;
 431 }
 432
 433 /**
 434  * i40e_aq_get_rss_lut
 435  * @hw: pointer to the hardware structure
 436  * @vsi_id: vsi fw index
 437  * @pf_lut: for PF table set true, for VSI table set false
 438  * @lut: pointer to the lut buffer provided by the caller
 439  * @lut_size: size of the lut buffer
 440  *
 441  * get the RSS lookup table, PF or VSI type
 442  **/
 443 i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 444                                 bool pf_lut, u8 *lut, u16 lut_size)
 445 {
 446         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
 447                                        false);
 448 }
 449
 450 /**
 451  * i40e_aq_set_rss_lut
 452  * @hw: pointer to the hardware structure
 453  * @vsi_id: vsi fw index
 454  * @pf_lut: for PF table set true, for VSI table set false
 455  * @lut: pointer to the lut buffer provided by the caller
 456  * @lut_size: size of the lut buffer
 457  *
 458  * set the RSS lookup table, PF or VSI type
 459  **/
 460 i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
 461                                 bool pf_lut, u8 *lut, u16 lut_size)
 462 {
 463         return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
 464 }
 465
 466 /**
 467  * i40e_aq_get_set_rss_key
 468  * @hw: pointer to the hw struct
 469  * @vsi_id: vsi fw index
 470  * @key: pointer to key info struct
 471  * @set: set true to set the key, false to get the key
 472  *
 473  * get the RSS key per VSI
 474  **/
 475 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
 476                                       u16 vsi_id,
 477                                       struct i40e_aqc_get_set_rss_key_data *key,
 478                                       bool set)
 479 {
 480         i40e_status status;
 481         struct i40e_aq_desc desc;
 482         struct i40e_aqc_get_set_rss_key *cmd_resp =
 483                         (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
 484         u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
 485
 486         if (set)
 487                 i40e_fill_default_direct_cmd_desc(&desc,
 488                                                   i40e_aqc_opc_set_rss_key);
 489         else
 490                 i40e_fill_default_direct_cmd_desc(&desc,
 491                                                   i40e_aqc_opc_get_rss_key);
 492
 493         /* Indirect command */
 494         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
 495         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
 496
 497         cmd_resp->vsi_id =
 498                         cpu_to_le16((u16)((vsi_id <<
 499                                           I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
 500                                           I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
 501         cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
 502
 503         status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
 504
 505         return status;
 506 }
 507
 508 /**
 509  * i40e_aq_get_rss_key
 510  * @hw: pointer to the hw struct
 511  * @vsi_id: vsi fw index
 512  * @key: pointer to key info struct
 513  *
 514  **/
 515 i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
 516                                 u16 vsi_id,
 517                                 struct i40e_aqc_get_set_rss_key_data *key)
 518 {
 519         return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
 520 }
 521
 522 /**
 523  * i40e_aq_set_rss_key
 524  * @hw: pointer to the hw struct
 525  * @vsi_id: vsi fw index
 526  * @key: pointer to key info struct
 527  *
 528  * set the RSS key per VSI
 529  **/
 530 i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
 531                                 u16 vsi_id,
 532                                 struct i40e_aqc_get_set_rss_key_data *key)
 533 {
 534         return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
 535 }
 536
 537 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
 538  * hardware to a bit-field that can be used by SW to more easily determine the
 539  * packet type.
 540  *
 541  * Macros are used to shorten the table lines and make this table human
 542  * readable.
 543  *
 544  * We store the PTYPE in the top byte of the bit field - this is just so that
 545  * we can check that the table doesn't have a row missing, as the index into
 546  * the table should be the PTYPE.
 547  *
 548  * Typical work flow:
 549  *
 550  * IF NOT i40e_ptype_lookup[ptype].known
 551  * THEN
 552  *      Packet is unknown
 553  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
 554  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
 555  * ELSE
 556  *      Use the enum i40e_rx_l2_ptype to decode the packet type
 557  * ENDIF
 558  */
 559
 560 /* macro to make the table lines short */
 561 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
 562         {       PTYPE, \
 563                 1, \
 564                 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
 565                 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
 566                 I40E_RX_PTYPE_##OUTER_FRAG, \
 567                 I40E_RX_PTYPE_TUNNEL_##T, \
 568                 I40E_RX_PTYPE_TUNNEL_END_##TE, \
 569                 I40E_RX_PTYPE_##TEF, \
 570                 I40E_RX_PTYPE_INNER_PROT_##I, \
 571                 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
 572
 573 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
 574                 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
 575
 576 /* shorter macros makes the table fit but are terse */
 577 #define I40E_RX_PTYPE_NOF               I40E_RX_PTYPE_NOT_FRAG
 578 #define I40E_RX_PTYPE_FRG               I40E_RX_PTYPE_FRAG
 579 #define I40E_RX_PTYPE_INNER_PROT_TS     I40E_RX_PTYPE_INNER_PROT_TIMESYNC
 580
 581 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
 582 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
 583         /* L2 Packet types */
 584         I40E_PTT_UNUSED_ENTRY(0),
 585         I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 586         I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
 587         I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 588         I40E_PTT_UNUSED_ENTRY(4),
 589         I40E_PTT_UNUSED_ENTRY(5),
 590         I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 591         I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 592         I40E_PTT_UNUSED_ENTRY(8),
 593         I40E_PTT_UNUSED_ENTRY(9),
 594         I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
 595         I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
 596         I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 597         I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 598         I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 599         I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 600         I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 601         I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 602         I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 603         I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 604         I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 605         I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
 606
 607         /* Non Tunneled IPv4 */
 608         I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
 609         I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
 610         I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
 611         I40E_PTT_UNUSED_ENTRY(25),
 612         I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
 613         I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
 614         I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
 615
 616         /* IPv4 --> IPv4 */
 617         I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 618         I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 619         I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 620         I40E_PTT_UNUSED_ENTRY(32),
 621         I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 622         I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 623         I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 624
 625         /* IPv4 --> IPv6 */
 626         I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 627         I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 628         I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 629         I40E_PTT_UNUSED_ENTRY(39),
 630         I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 631         I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 632         I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 633
 634         /* IPv4 --> GRE/NAT */
 635         I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 636
 637         /* IPv4 --> GRE/NAT --> IPv4 */
 638         I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 639         I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 640         I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 641         I40E_PTT_UNUSED_ENTRY(47),
 642         I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 643         I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 644         I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 645
 646         /* IPv4 --> GRE/NAT --> IPv6 */
 647         I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 648         I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 649         I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 650         I40E_PTT_UNUSED_ENTRY(54),
 651         I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 652         I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 653         I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 654
 655         /* IPv4 --> GRE/NAT --> MAC */
 656         I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 657
 658         /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
 659         I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 660         I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 661         I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 662         I40E_PTT_UNUSED_ENTRY(62),
 663         I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 664         I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 665         I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 666
 667         /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
 668         I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 669         I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 670         I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 671         I40E_PTT_UNUSED_ENTRY(69),
 672         I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 673         I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 674         I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 675
 676         /* IPv4 --> GRE/NAT --> MAC/VLAN */
 677         I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 678
 679         /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
 680         I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 681         I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 682         I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 683         I40E_PTT_UNUSED_ENTRY(77),
 684         I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 685         I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 686         I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 687
 688         /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
 689         I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 690         I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 691         I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 692         I40E_PTT_UNUSED_ENTRY(84),
 693         I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 694         I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 695         I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 696
 697         /* Non Tunneled IPv6 */
 698         I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
 699         I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
 700         I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
 701         I40E_PTT_UNUSED_ENTRY(91),
 702         I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
 703         I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
 704         I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
 705
 706         /* IPv6 --> IPv4 */
 707         I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
 708         I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
 709         I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
 710         I40E_PTT_UNUSED_ENTRY(98),
 711         I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
 712         I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
 713         I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
 714
 715         /* IPv6 --> IPv6 */
 716         I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
 717         I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
 718         I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
 719         I40E_PTT_UNUSED_ENTRY(105),
 720         I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
 721         I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
 722         I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
 723
 724         /* IPv6 --> GRE/NAT */
 725         I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
 726
 727         /* IPv6 --> GRE/NAT -> IPv4 */
 728         I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
 729         I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
 730         I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
 731         I40E_PTT_UNUSED_ENTRY(113),
 732         I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
 733         I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
 734         I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
 735
 736         /* IPv6 --> GRE/NAT -> IPv6 */
 737         I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
 738         I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
 739         I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
 740         I40E_PTT_UNUSED_ENTRY(120),
 741         I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
 742         I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
 743         I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
 744
 745         /* IPv6 --> GRE/NAT -> MAC */
 746         I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
 747
 748         /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
 749         I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
 750         I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
 751         I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
 752         I40E_PTT_UNUSED_ENTRY(128),
 753         I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
 754         I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
 755         I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
 756
 757         /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
 758         I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
 759         I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
 760         I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
 761         I40E_PTT_UNUSED_ENTRY(135),
 762         I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
 763         I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
 764         I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
 765
 766         /* IPv6 --> GRE/NAT -> MAC/VLAN */
 767         I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
 768
 769         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
 770         I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
 771         I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
 772         I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
 773         I40E_PTT_UNUSED_ENTRY(143),
 774         I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
 775         I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
 776         I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
 777
 778         /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
 779         I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
 780         I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
 781         I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
 782         I40E_PTT_UNUSED_ENTRY(150),
 783         I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
 784         I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
 785         I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
 786
 787         /* unused entries */
 788         I40E_PTT_UNUSED_ENTRY(154),
 789         I40E_PTT_UNUSED_ENTRY(155),
 790         I40E_PTT_UNUSED_ENTRY(156),
 791         I40E_PTT_UNUSED_ENTRY(157),
 792         I40E_PTT_UNUSED_ENTRY(158),
 793         I40E_PTT_UNUSED_ENTRY(159),
 794
 795         I40E_PTT_UNUSED_ENTRY(160),
 796         I40E_PTT_UNUSED_ENTRY(161),
 797         I40E_PTT_UNUSED_ENTRY(162),
 798         I40E_PTT_UNUSED_ENTRY(163),
 799         I40E_PTT_UNUSED_ENTRY(164),
 800         I40E_PTT_UNUSED_ENTRY(165),
 801         I40E_PTT_UNUSED_ENTRY(166),
 802         I40E_PTT_UNUSED_ENTRY(167),
 803         I40E_PTT_UNUSED_ENTRY(168),
 804         I40E_PTT_UNUSED_ENTRY(169),
 805
 806         I40E_PTT_UNUSED_ENTRY(170),
 807         I40E_PTT_UNUSED_ENTRY(171),
 808         I40E_PTT_UNUSED_ENTRY(172),
 809         I40E_PTT_UNUSED_ENTRY(173),
 810         I40E_PTT_UNUSED_ENTRY(174),
 811         I40E_PTT_UNUSED_ENTRY(175),
 812         I40E_PTT_UNUSED_ENTRY(176),
 813         I40E_PTT_UNUSED_ENTRY(177),
 814         I40E_PTT_UNUSED_ENTRY(178),
 815         I40E_PTT_UNUSED_ENTRY(179),
 816
 817         I40E_PTT_UNUSED_ENTRY(180),
 818         I40E_PTT_UNUSED_ENTRY(181),
 819         I40E_PTT_UNUSED_ENTRY(182),
 820         I40E_PTT_UNUSED_ENTRY(183),
 821         I40E_PTT_UNUSED_ENTRY(184),
 822         I40E_PTT_UNUSED_ENTRY(185),
 823         I40E_PTT_UNUSED_ENTRY(186),
 824         I40E_PTT_UNUSED_ENTRY(187),
 825         I40E_PTT_UNUSED_ENTRY(188),
 826         I40E_PTT_UNUSED_ENTRY(189),
 827
 828         I40E_PTT_UNUSED_ENTRY(190),
 829         I40E_PTT_UNUSED_ENTRY(191),
 830         I40E_PTT_UNUSED_ENTRY(192),
 831         I40E_PTT_UNUSED_ENTRY(193),
 832         I40E_PTT_UNUSED_ENTRY(194),
 833         I40E_PTT_UNUSED_ENTRY(195),
 834         I40E_PTT_UNUSED_ENTRY(196),
 835         I40E_PTT_UNUSED_ENTRY(197),
 836         I40E_PTT_UNUSED_ENTRY(198),
 837         I40E_PTT_UNUSED_ENTRY(199),
 838
 839         I40E_PTT_UNUSED_ENTRY(200),
 840         I40E_PTT_UNUSED_ENTRY(201),
 841         I40E_PTT_UNUSED_ENTRY(202),
 842         I40E_PTT_UNUSED_ENTRY(203),
 843         I40E_PTT_UNUSED_ENTRY(204),
 844         I40E_PTT_UNUSED_ENTRY(205),
 845         I40E_PTT_UNUSED_ENTRY(206),
 846         I40E_PTT_UNUSED_ENTRY(207),
 847         I40E_PTT_UNUSED_ENTRY(208),
 848         I40E_PTT_UNUSED_ENTRY(209),
 849
 850         I40E_PTT_UNUSED_ENTRY(210),
 851         I40E_PTT_UNUSED_ENTRY(211),
 852         I40E_PTT_UNUSED_ENTRY(212),
 853         I40E_PTT_UNUSED_ENTRY(213),
 854         I40E_PTT_UNUSED_ENTRY(214),
 855         I40E_PTT_UNUSED_ENTRY(215),
 856         I40E_PTT_UNUSED_ENTRY(216),
 857         I40E_PTT_UNUSED_ENTRY(217),
 858         I40E_PTT_UNUSED_ENTRY(218),
 859         I40E_PTT_UNUSED_ENTRY(219),
 860
 861         I40E_PTT_UNUSED_ENTRY(220),
 862         I40E_PTT_UNUSED_ENTRY(221),
 863         I40E_PTT_UNUSED_ENTRY(222),
 864         I40E_PTT_UNUSED_ENTRY(223),
 865         I40E_PTT_UNUSED_ENTRY(224),
 866         I40E_PTT_UNUSED_ENTRY(225),
 867         I40E_PTT_UNUSED_ENTRY(226),
 868         I40E_PTT_UNUSED_ENTRY(227),
 869         I40E_PTT_UNUSED_ENTRY(228),
 870         I40E_PTT_UNUSED_ENTRY(229),
 871
 872         I40E_PTT_UNUSED_ENTRY(230),
 873         I40E_PTT_UNUSED_ENTRY(231),
 874         I40E_PTT_UNUSED_ENTRY(232),
 875         I40E_PTT_UNUSED_ENTRY(233),
 876         I40E_PTT_UNUSED_ENTRY(234),
 877         I40E_PTT_UNUSED_ENTRY(235),
 878         I40E_PTT_UNUSED_ENTRY(236),
 879         I40E_PTT_UNUSED_ENTRY(237),
 880         I40E_PTT_UNUSED_ENTRY(238),
 881         I40E_PTT_UNUSED_ENTRY(239),
 882
 883         I40E_PTT_UNUSED_ENTRY(240),
 884         I40E_PTT_UNUSED_ENTRY(241),
 885         I40E_PTT_UNUSED_ENTRY(242),
 886         I40E_PTT_UNUSED_ENTRY(243),
 887         I40E_PTT_UNUSED_ENTRY(244),
 888         I40E_PTT_UNUSED_ENTRY(245),
 889         I40E_PTT_UNUSED_ENTRY(246),
 890         I40E_PTT_UNUSED_ENTRY(247),
 891         I40E_PTT_UNUSED_ENTRY(248),
 892         I40E_PTT_UNUSED_ENTRY(249),
 893
 894         I40E_PTT_UNUSED_ENTRY(250),
 895         I40E_PTT_UNUSED_ENTRY(251),
 896         I40E_PTT_UNUSED_ENTRY(252),
 897         I40E_PTT_UNUSED_ENTRY(253),
 898         I40E_PTT_UNUSED_ENTRY(254),
 899         I40E_PTT_UNUSED_ENTRY(255)
 900 };
 901
 902 /**
 903  * i40e_init_shared_code - Initialize the shared code
 904  * @hw: pointer to hardware structure
 905  *
 906  * This assigns the MAC type and PHY code and inits the NVM.
 907  * Does not touch the hardware. This function must be called prior to any
 908  * other function in the shared code. The i40e_hw structure should be
 909  * memset to 0 prior to calling this function.  The following fields in
 910  * hw structure should be filled in prior to calling this function:
 911  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
 912  * subsystem_vendor_id, and revision_id
 913  **/
 914 i40e_status i40e_init_shared_code(struct i40e_hw *hw)
 915 {
 916         i40e_status status = 0;
 917         u32 port, ari, func_rid;
 918
 919         i40e_set_mac_type(hw);
 920
 921         switch (hw->mac.type) {
 922         case I40E_MAC_XL710:
 923         case I40E_MAC_X722:
 924                 break;
 925         default:
 926                 return I40E_ERR_DEVICE_NOT_SUPPORTED;
 927         }
 928
 929         hw->phy.get_link_info = true;
 930
 931         /* Determine port number and PF number*/
 932         port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
 933                                            >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
 934         hw->port = (u8)port;
 935         ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
 936                                                  I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
 937         func_rid = rd32(hw, I40E_PF_FUNC_RID);
 938         if (ari)
 939                 hw->pf_id = (u8)(func_rid & 0xff);
 940         else
 941                 hw->pf_id = (u8)(func_rid & 0x7);
 942
 943         if (hw->mac.type == I40E_MAC_X722)
 944                 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
 945
 946         status = i40e_init_nvm(hw);
 947         return status;
 948 }
 949
 950 /**
 951  * i40e_aq_mac_address_read - Retrieve the MAC addresses
 952  * @hw: pointer to the hw struct
 953  * @flags: a return indicator of what addresses were added to the addr store
 954  * @addrs: the requestor's mac addr store
 955  * @cmd_details: pointer to command details structure or NULL
 956  **/
 957 static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
 958                                    u16 *flags,
 959                                    struct i40e_aqc_mac_address_read_data *addrs,
 960                                    struct i40e_asq_cmd_details *cmd_details)
 961 {
 962         struct i40e_aq_desc desc;
 963         struct i40e_aqc_mac_address_read *cmd_data =
 964                 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
 965         i40e_status status;
 966
 967         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
 968         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
 969
 970         status = i40e_asq_send_command(hw, &desc, addrs,
 971                                        sizeof(*addrs), cmd_details);
 972         *flags = le16_to_cpu(cmd_data->command_flags);
 973
 974         return status;
 975 }
 976
 977 /**
 978  * i40e_aq_mac_address_write - Change the MAC addresses
 979  * @hw: pointer to the hw struct
 980  * @flags: indicates which MAC to be written
 981  * @mac_addr: address to write
 982  * @cmd_details: pointer to command details structure or NULL
 983  **/
 984 i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
 985                                     u16 flags, u8 *mac_addr,
 986                                     struct i40e_asq_cmd_details *cmd_details)
 987 {
 988         struct i40e_aq_desc desc;
 989         struct i40e_aqc_mac_address_write *cmd_data =
 990                 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
 991         i40e_status status;
 992
 993         i40e_fill_default_direct_cmd_desc(&desc,
 994                                           i40e_aqc_opc_mac_address_write);
 995         cmd_data->command_flags = cpu_to_le16(flags);
 996         cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
 997         cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
 998                                         ((u32)mac_addr[3] << 16) |
 999                                         ((u32)mac_addr[4] << 8) |
1000                                         mac_addr[5]);
1001
1002         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1003
1004         return status;
1005 }
1006
1007 /**
1008  * i40e_get_mac_addr - get MAC address
1009  * @hw: pointer to the HW structure
1010  * @mac_addr: pointer to MAC address
1011  *
1012  * Reads the adapter's MAC address from register
1013  **/
1014 i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1015 {
1016         struct i40e_aqc_mac_address_read_data addrs;
1017         i40e_status status;
1018         u16 flags = 0;
1019
1020         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1021
1022         if (flags & I40E_AQC_LAN_ADDR_VALID)
1023                 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1024
1025         return status;
1026 }
1027
1028 /**
1029  * i40e_get_port_mac_addr - get Port MAC address
1030  * @hw: pointer to the HW structure
1031  * @mac_addr: pointer to Port MAC address
1032  *
1033  * Reads the adapter's Port MAC address
1034  **/
1035 i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1036 {
1037         struct i40e_aqc_mac_address_read_data addrs;
1038         i40e_status status;
1039         u16 flags = 0;
1040
1041         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1042         if (status)
1043                 return status;
1044
1045         if (flags & I40E_AQC_PORT_ADDR_VALID)
1046                 ether_addr_copy(mac_addr, addrs.port_mac);
1047         else
1048                 status = I40E_ERR_INVALID_MAC_ADDR;
1049
1050         return status;
1051 }
1052
1053 /**
1054  * i40e_pre_tx_queue_cfg - pre tx queue configure
1055  * @hw: pointer to the HW structure
1056  * @queue: target PF queue index
1057  * @enable: state change request
1058  *
1059  * Handles hw requirement to indicate intention to enable
1060  * or disable target queue.
1061  **/
1062 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1063 {
1064         u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1065         u32 reg_block = 0;
1066         u32 reg_val;
1067
1068         if (abs_queue_idx >= 128) {
1069                 reg_block = abs_queue_idx / 128;
1070                 abs_queue_idx %= 128;
1071         }
1072
1073         reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1074         reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1075         reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1076
1077         if (enable)
1078                 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1079         else
1080                 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1081
1082         wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1083 }
1084 #ifdef I40E_FCOE
1085
1086 /**
1087  * i40e_get_san_mac_addr - get SAN MAC address
1088  * @hw: pointer to the HW structure
1089  * @mac_addr: pointer to SAN MAC address
1090  *
1091  * Reads the adapter's SAN MAC address from NVM
1092  **/
1093 i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1094 {
1095         struct i40e_aqc_mac_address_read_data addrs;
1096         i40e_status status;
1097         u16 flags = 0;
1098
1099         status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1100         if (status)
1101                 return status;
1102
1103         if (flags & I40E_AQC_SAN_ADDR_VALID)
1104                 ether_addr_copy(mac_addr, addrs.pf_san_mac);
1105         else
1106                 status = I40E_ERR_INVALID_MAC_ADDR;
1107
1108         return status;
1109 }
1110 #endif
1111
1112 /**
1113  *  i40e_read_pba_string - Reads part number string from EEPROM
1114  *  @hw: pointer to hardware structure
1115  *  @pba_num: stores the part number string from the EEPROM
1116  *  @pba_num_size: part number string buffer length
1117  *
1118  *  Reads the part number string from the EEPROM.
1119  **/
1120 i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1121                                  u32 pba_num_size)
1122 {
1123         i40e_status status = 0;
1124         u16 pba_word = 0;
1125         u16 pba_size = 0;
1126         u16 pba_ptr = 0;
1127         u16 i = 0;
1128
1129         status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1130         if (status || (pba_word != 0xFAFA)) {
1131                 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1132                 return status;
1133         }
1134
1135         status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1136         if (status) {
1137                 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1138                 return status;
1139         }
1140
1141         status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1142         if (status) {
1143                 hw_dbg(hw, "Failed to read PBA Block size.\n");
1144                 return status;
1145         }
1146
1147         /* Subtract one to get PBA word count (PBA Size word is included in
1148          * total size)
1149          */
1150         pba_size--;
1151         if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1152                 hw_dbg(hw, "Buffer to small for PBA data.\n");
1153                 return I40E_ERR_PARAM;
1154         }
1155
1156         for (i = 0; i < pba_size; i++) {
1157                 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1158                 if (status) {
1159                         hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1160                         return status;
1161                 }
1162
1163                 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1164                 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1165         }
1166         pba_num[(pba_size * 2)] = '\0';
1167
1168         return status;
1169 }
1170
1171 /**
1172  * i40e_get_media_type - Gets media type
1173  * @hw: pointer to the hardware structure
1174  **/
1175 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1176 {
1177         enum i40e_media_type media;
1178
1179         switch (hw->phy.link_info.phy_type) {
1180         case I40E_PHY_TYPE_10GBASE_SR:
1181         case I40E_PHY_TYPE_10GBASE_LR:
1182         case I40E_PHY_TYPE_1000BASE_SX:
1183         case I40E_PHY_TYPE_1000BASE_LX:
1184         case I40E_PHY_TYPE_40GBASE_SR4:
1185         case I40E_PHY_TYPE_40GBASE_LR4:
1186                 media = I40E_MEDIA_TYPE_FIBER;
1187                 break;
1188         case I40E_PHY_TYPE_100BASE_TX:
1189         case I40E_PHY_TYPE_1000BASE_T:
1190         case I40E_PHY_TYPE_10GBASE_T:
1191                 media = I40E_MEDIA_TYPE_BASET;
1192                 break;
1193         case I40E_PHY_TYPE_10GBASE_CR1_CU:
1194         case I40E_PHY_TYPE_40GBASE_CR4_CU:
1195         case I40E_PHY_TYPE_10GBASE_CR1:
1196         case I40E_PHY_TYPE_40GBASE_CR4:
1197         case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1198         case I40E_PHY_TYPE_40GBASE_AOC:
1199         case I40E_PHY_TYPE_10GBASE_AOC:
1200                 media = I40E_MEDIA_TYPE_DA;
1201                 break;
1202         case I40E_PHY_TYPE_1000BASE_KX:
1203         case I40E_PHY_TYPE_10GBASE_KX4:
1204         case I40E_PHY_TYPE_10GBASE_KR:
1205         case I40E_PHY_TYPE_40GBASE_KR4:
1206         case I40E_PHY_TYPE_20GBASE_KR2:
1207                 media = I40E_MEDIA_TYPE_BACKPLANE;
1208                 break;
1209         case I40E_PHY_TYPE_SGMII:
1210         case I40E_PHY_TYPE_XAUI:
1211         case I40E_PHY_TYPE_XFI:
1212         case I40E_PHY_TYPE_XLAUI:
1213         case I40E_PHY_TYPE_XLPPI:
1214         default:
1215                 media = I40E_MEDIA_TYPE_UNKNOWN;
1216                 break;
1217         }
1218
1219         return media;
1220 }
1221
1222 #define I40E_PF_RESET_WAIT_COUNT_A0     200
1223 #define I40E_PF_RESET_WAIT_COUNT        200
1224 /**
1225  * i40e_pf_reset - Reset the PF
1226  * @hw: pointer to the hardware structure
1227  *
1228  * Assuming someone else has triggered a global reset,
1229  * assure the global reset is complete and then reset the PF
1230  **/
1231 i40e_status i40e_pf_reset(struct i40e_hw *hw)
1232 {
1233         u32 cnt = 0;
1234         u32 cnt1 = 0;
1235         u32 reg = 0;
1236         u32 grst_del;
1237
1238         /* Poll for Global Reset steady state in case of recent GRST.
1239          * The grst delay value is in 100ms units, and we'll wait a
1240          * couple counts longer to be sure we don't just miss the end.
1241          */
1242         grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1243                     I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1244                     I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1245
1246         /* It can take upto 15 secs for GRST steady state.
1247          * Bump it to 16 secs max to be safe.
1248          */
1249         grst_del = grst_del * 20;
1250
1251         for (cnt = 0; cnt < grst_del; cnt++) {
1252                 reg = rd32(hw, I40E_GLGEN_RSTAT);
1253                 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1254                         break;
1255                 msleep(100);
1256         }
1257         if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1258                 hw_dbg(hw, "Global reset polling failed to complete.\n");
1259                 return I40E_ERR_RESET_FAILED;
1260         }
1261
1262         /* Now Wait for the FW to be ready */
1263         for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1264                 reg = rd32(hw, I40E_GLNVM_ULD);
1265                 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1266                         I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1267                 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1268                             I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1269                         hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1270                         break;
1271                 }
1272                 usleep_range(10000, 20000);
1273         }
1274         if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1275                      I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1276                 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1277                 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1278                 return I40E_ERR_RESET_FAILED;
1279         }
1280
1281         /* If there was a Global Reset in progress when we got here,
1282          * we don't need to do the PF Reset
1283          */
1284         if (!cnt) {
1285                 if (hw->revision_id == 0)
1286                         cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1287                 else
1288                         cnt = I40E_PF_RESET_WAIT_COUNT;
1289                 reg = rd32(hw, I40E_PFGEN_CTRL);
1290                 wr32(hw, I40E_PFGEN_CTRL,
1291                      (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1292                 for (; cnt; cnt--) {
1293                         reg = rd32(hw, I40E_PFGEN_CTRL);
1294                         if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1295                                 break;
1296                         usleep_range(1000, 2000);
1297                 }
1298                 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1299                         hw_dbg(hw, "PF reset polling failed to complete.\n");
1300                         return I40E_ERR_RESET_FAILED;
1301                 }
1302         }
1303
1304         i40e_clear_pxe_mode(hw);
1305
1306         return 0;
1307 }
1308
1309 /**
1310  * i40e_clear_hw - clear out any left over hw state
1311  * @hw: pointer to the hw struct
1312  *
1313  * Clear queues and interrupts, typically called at init time,
1314  * but after the capabilities have been found so we know how many
1315  * queues and msix vectors have been allocated.
1316  **/
1317 void i40e_clear_hw(struct i40e_hw *hw)
1318 {
1319         u32 num_queues, base_queue;
1320         u32 num_pf_int;
1321         u32 num_vf_int;
1322         u32 num_vfs;
1323         u32 i, j;
1324         u32 val;
1325         u32 eol = 0x7ff;
1326
1327         /* get number of interrupts, queues, and VFs */
1328         val = rd32(hw, I40E_GLPCI_CNF2);
1329         num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1330                      I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1331         num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1332                      I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1333
1334         val = rd32(hw, I40E_PFLAN_QALLOC);
1335         base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1336                      I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1337         j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1338             I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1339         if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1340                 num_queues = (j - base_queue) + 1;
1341         else
1342                 num_queues = 0;
1343
1344         val = rd32(hw, I40E_PF_VT_PFALLOC);
1345         i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1346             I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1347         j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1348             I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1349         if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1350                 num_vfs = (j - i) + 1;
1351         else
1352                 num_vfs = 0;
1353
1354         /* stop all the interrupts */
1355         wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1356         val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1357         for (i = 0; i < num_pf_int - 2; i++)
1358                 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1359
1360         /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1361         val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1362         wr32(hw, I40E_PFINT_LNKLST0, val);
1363         for (i = 0; i < num_pf_int - 2; i++)
1364                 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1365         val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1366         for (i = 0; i < num_vfs; i++)
1367                 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1368         for (i = 0; i < num_vf_int - 2; i++)
1369                 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1370
1371         /* warn the HW of the coming Tx disables */
1372         for (i = 0; i < num_queues; i++) {
1373                 u32 abs_queue_idx = base_queue + i;
1374                 u32 reg_block = 0;
1375
1376                 if (abs_queue_idx >= 128) {
1377                         reg_block = abs_queue_idx / 128;
1378                         abs_queue_idx %= 128;
1379                 }
1380
1381                 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1382                 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1383                 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1384                 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1385
1386                 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1387         }
1388         udelay(400);
1389
1390         /* stop all the queues */
1391         for (i = 0; i < num_queues; i++) {
1392                 wr32(hw, I40E_QINT_TQCTL(i), 0);
1393                 wr32(hw, I40E_QTX_ENA(i), 0);
1394                 wr32(hw, I40E_QINT_RQCTL(i), 0);
1395                 wr32(hw, I40E_QRX_ENA(i), 0);
1396         }
1397
1398         /* short wait for all queue disables to settle */
1399         udelay(50);
1400 }
1401
1402 /**
1403  * i40e_clear_pxe_mode - clear pxe operations mode
1404  * @hw: pointer to the hw struct
1405  *
1406  * Make sure all PXE mode settings are cleared, including things
1407  * like descriptor fetch/write-back mode.
1408  **/
1409 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1410 {
1411         u32 reg;
1412
1413         if (i40e_check_asq_alive(hw))
1414                 i40e_aq_clear_pxe_mode(hw, NULL);
1415
1416         /* Clear single descriptor fetch/write-back mode */
1417         reg = rd32(hw, I40E_GLLAN_RCTL_0);
1418
1419         if (hw->revision_id == 0) {
1420                 /* As a work around clear PXE_MODE instead of setting it */
1421                 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1422         } else {
1423                 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1424         }
1425 }
1426
1427 /**
1428  * i40e_led_is_mine - helper to find matching led
1429  * @hw: pointer to the hw struct
1430  * @idx: index into GPIO registers
1431  *
1432  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1433  */
1434 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1435 {
1436         u32 gpio_val = 0;
1437         u32 port;
1438
1439         if (!hw->func_caps.led[idx])
1440                 return 0;
1441
1442         gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1443         port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1444                 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1445
1446         /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1447          * if it is not our port then ignore
1448          */
1449         if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1450             (port != hw->port))
1451                 return 0;
1452
1453         return gpio_val;
1454 }
1455
1456 #define I40E_COMBINED_ACTIVITY 0xA
1457 #define I40E_FILTER_ACTIVITY 0xE
1458 #define I40E_LINK_ACTIVITY 0xC
1459 #define I40E_MAC_ACTIVITY 0xD
1460 #define I40E_LED0 22
1461
1462 /**
1463  * i40e_led_get - return current on/off mode
1464  * @hw: pointer to the hw struct
1465  *
1466  * The value returned is the 'mode' field as defined in the
1467  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1468  * values are variations of possible behaviors relating to
1469  * blink, link, and wire.
1470  **/
1471 u32 i40e_led_get(struct i40e_hw *hw)
1472 {
1473         u32 current_mode = 0;
1474         u32 mode = 0;
1475         int i;
1476
1477         /* as per the documentation GPIO 22-29 are the LED
1478          * GPIO pins named LED0..LED7
1479          */
1480         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1481                 u32 gpio_val = i40e_led_is_mine(hw, i);
1482
1483                 if (!gpio_val)
1484                         continue;
1485
1486                 /* ignore gpio LED src mode entries related to the activity
1487                  * LEDs
1488                  */
1489                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1490                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1491                 switch (current_mode) {
1492                 case I40E_COMBINED_ACTIVITY:
1493                 case I40E_FILTER_ACTIVITY:
1494                 case I40E_MAC_ACTIVITY:
1495                         continue;
1496                 default:
1497                         break;
1498                 }
1499
1500                 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1501                         I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1502                 break;
1503         }
1504
1505         return mode;
1506 }
1507
1508 /**
1509  * i40e_led_set - set new on/off mode
1510  * @hw: pointer to the hw struct
1511  * @mode: 0=off, 0xf=on (else see manual for mode details)
1512  * @blink: true if the LED should blink when on, false if steady
1513  *
1514  * if this function is used to turn on the blink it should
1515  * be used to disable the blink when restoring the original state.
1516  **/
1517 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1518 {
1519         u32 current_mode = 0;
1520         int i;
1521
1522         if (mode & 0xfffffff0)
1523                 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1524
1525         /* as per the documentation GPIO 22-29 are the LED
1526          * GPIO pins named LED0..LED7
1527          */
1528         for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1529                 u32 gpio_val = i40e_led_is_mine(hw, i);
1530
1531                 if (!gpio_val)
1532                         continue;
1533
1534                 /* ignore gpio LED src mode entries related to the activity
1535                  * LEDs
1536                  */
1537                 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1538                                 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1539                 switch (current_mode) {
1540                 case I40E_COMBINED_ACTIVITY:
1541                 case I40E_FILTER_ACTIVITY:
1542                 case I40E_MAC_ACTIVITY:
1543                         continue;
1544                 default:
1545                         break;
1546                 }
1547
1548                 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1549                 /* this & is a bit of paranoia, but serves as a range check */
1550                 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1551                              I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1552
1553                 if (mode == I40E_LINK_ACTIVITY)
1554                         blink = false;
1555
1556                 if (blink)
1557                         gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1558                 else
1559                         gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1560
1561                 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1562                 break;
1563         }
1564 }
1565
1566 /* Admin command wrappers */
1567
1568 /**
1569  * i40e_aq_get_phy_capabilities
1570  * @hw: pointer to the hw struct
1571  * @abilities: structure for PHY capabilities to be filled
1572  * @qualified_modules: report Qualified Modules
1573  * @report_init: report init capabilities (active are default)
1574  * @cmd_details: pointer to command details structure or NULL
1575  *
1576  * Returns the various PHY abilities supported on the Port.
1577  **/
1578 i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1579                         bool qualified_modules, bool report_init,
1580                         struct i40e_aq_get_phy_abilities_resp *abilities,
1581                         struct i40e_asq_cmd_details *cmd_details)
1582 {
1583         struct i40e_aq_desc desc;
1584         i40e_status status;
1585         u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1586
1587         if (!abilities)
1588                 return I40E_ERR_PARAM;
1589
1590         i40e_fill_default_direct_cmd_desc(&desc,
1591                                           i40e_aqc_opc_get_phy_abilities);
1592
1593         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1594         if (abilities_size > I40E_AQ_LARGE_BUF)
1595                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1596
1597         if (qualified_modules)
1598                 desc.params.external.param0 |=
1599                         cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1600
1601         if (report_init)
1602                 desc.params.external.param0 |=
1603                         cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1604
1605         status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1606                                        cmd_details);
1607
1608         if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1609                 status = I40E_ERR_UNKNOWN_PHY;
1610
1611         if (report_init)
1612                 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1613
1614         return status;
1615 }
1616
1617 /**
1618  * i40e_aq_set_phy_config
1619  * @hw: pointer to the hw struct
1620  * @config: structure with PHY configuration to be set
1621  * @cmd_details: pointer to command details structure or NULL
1622  *
1623  * Set the various PHY configuration parameters
1624  * supported on the Port.One or more of the Set PHY config parameters may be
1625  * ignored in an MFP mode as the PF may not have the privilege to set some
1626  * of the PHY Config parameters. This status will be indicated by the
1627  * command response.
1628  **/
1629 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1630                                 struct i40e_aq_set_phy_config *config,
1631                                 struct i40e_asq_cmd_details *cmd_details)
1632 {
1633         struct i40e_aq_desc desc;
1634         struct i40e_aq_set_phy_config *cmd =
1635                         (struct i40e_aq_set_phy_config *)&desc.params.raw;
1636         enum i40e_status_code status;
1637
1638         if (!config)
1639                 return I40E_ERR_PARAM;
1640
1641         i40e_fill_default_direct_cmd_desc(&desc,
1642                                           i40e_aqc_opc_set_phy_config);
1643
1644         *cmd = *config;
1645
1646         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1647
1648         return status;
1649 }
1650
1651 /**
1652  * i40e_set_fc
1653  * @hw: pointer to the hw struct
1654  *
1655  * Set the requested flow control mode using set_phy_config.
1656  **/
1657 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1658                                   bool atomic_restart)
1659 {
1660         enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1661         struct i40e_aq_get_phy_abilities_resp abilities;
1662         struct i40e_aq_set_phy_config config;
1663         enum i40e_status_code status;
1664         u8 pause_mask = 0x0;
1665
1666         *aq_failures = 0x0;
1667
1668         switch (fc_mode) {
1669         case I40E_FC_FULL:
1670                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1671                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1672                 break;
1673         case I40E_FC_RX_PAUSE:
1674                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1675                 break;
1676         case I40E_FC_TX_PAUSE:
1677                 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1678                 break;
1679         default:
1680                 break;
1681         }
1682
1683         /* Get the current phy config */
1684         status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1685                                               NULL);
1686         if (status) {
1687                 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1688                 return status;
1689         }
1690
1691         memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1692         /* clear the old pause settings */
1693         config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1694                            ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1695         /* set the new abilities */
1696         config.abilities |= pause_mask;
1697         /* If the abilities have changed, then set the new config */
1698         if (config.abilities != abilities.abilities) {
1699                 /* Auto restart link so settings take effect */
1700                 if (atomic_restart)
1701                         config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1702                 /* Copy over all the old settings */
1703                 config.phy_type = abilities.phy_type;
1704                 config.link_speed = abilities.link_speed;
1705                 config.eee_capability = abilities.eee_capability;
1706                 config.eeer = abilities.eeer_val;
1707                 config.low_power_ctrl = abilities.d3_lpan;
1708                 status = i40e_aq_set_phy_config(hw, &config, NULL);
1709
1710                 if (status)
1711                         *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1712         }
1713         /* Update the link info */
1714         status = i40e_update_link_info(hw);
1715         if (status) {
1716                 /* Wait a little bit (on 40G cards it sometimes takes a really
1717                  * long time for link to come back from the atomic reset)
1718                  * and try once more
1719                  */
1720                 msleep(1000);
1721                 status = i40e_update_link_info(hw);
1722         }
1723         if (status)
1724                 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1725
1726         return status;
1727 }
1728
1729 /**
1730  * i40e_aq_clear_pxe_mode
1731  * @hw: pointer to the hw struct
1732  * @cmd_details: pointer to command details structure or NULL
1733  *
1734  * Tell the firmware that the driver is taking over from PXE
1735  **/
1736 i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1737                                 struct i40e_asq_cmd_details *cmd_details)
1738 {
1739         i40e_status status;
1740         struct i40e_aq_desc desc;
1741         struct i40e_aqc_clear_pxe *cmd =
1742                 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1743
1744         i40e_fill_default_direct_cmd_desc(&desc,
1745                                           i40e_aqc_opc_clear_pxe_mode);
1746
1747         cmd->rx_cnt = 0x2;
1748
1749         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1750
1751         wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1752
1753         return status;
1754 }
1755
1756 /**
1757  * i40e_aq_set_link_restart_an
1758  * @hw: pointer to the hw struct
1759  * @enable_link: if true: enable link, if false: disable link
1760  * @cmd_details: pointer to command details structure or NULL
1761  *
1762  * Sets up the link and restarts the Auto-Negotiation over the link.
1763  **/
1764 i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1765                                         bool enable_link,
1766                                         struct i40e_asq_cmd_details *cmd_details)
1767 {
1768         struct i40e_aq_desc desc;
1769         struct i40e_aqc_set_link_restart_an *cmd =
1770                 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1771         i40e_status status;
1772
1773         i40e_fill_default_direct_cmd_desc(&desc,
1774                                           i40e_aqc_opc_set_link_restart_an);
1775
1776         cmd->command = I40E_AQ_PHY_RESTART_AN;
1777         if (enable_link)
1778                 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1779         else
1780                 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1781
1782         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1783
1784         return status;
1785 }
1786
1787 /**
1788  * i40e_aq_get_link_info
1789  * @hw: pointer to the hw struct
1790  * @enable_lse: enable/disable LinkStatusEvent reporting
1791  * @link: pointer to link status structure - optional
1792  * @cmd_details: pointer to command details structure or NULL
1793  *
1794  * Returns the link status of the adapter.
1795  **/
1796 i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1797                                 bool enable_lse, struct i40e_link_status *link,
1798                                 struct i40e_asq_cmd_details *cmd_details)
1799 {
1800         struct i40e_aq_desc desc;
1801         struct i40e_aqc_get_link_status *resp =
1802                 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1803         struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1804         i40e_status status;
1805         bool tx_pause, rx_pause;
1806         u16 command_flags;
1807
1808         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1809
1810         if (enable_lse)
1811                 command_flags = I40E_AQ_LSE_ENABLE;
1812         else
1813                 command_flags = I40E_AQ_LSE_DISABLE;
1814         resp->command_flags = cpu_to_le16(command_flags);
1815
1816         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1817
1818         if (status)
1819                 goto aq_get_link_info_exit;
1820
1821         /* save off old link status information */
1822         hw->phy.link_info_old = *hw_link_info;
1823
1824         /* update link status */
1825         hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1826         hw->phy.media_type = i40e_get_media_type(hw);
1827         hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1828         hw_link_info->link_info = resp->link_info;
1829         hw_link_info->an_info = resp->an_info;
1830         hw_link_info->ext_info = resp->ext_info;
1831         hw_link_info->loopback = resp->loopback;
1832         hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1833         hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1834
1835         /* update fc info */
1836         tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1837         rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1838         if (tx_pause & rx_pause)
1839                 hw->fc.current_mode = I40E_FC_FULL;
1840         else if (tx_pause)
1841                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1842         else if (rx_pause)
1843                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1844         else
1845                 hw->fc.current_mode = I40E_FC_NONE;
1846
1847         if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1848                 hw_link_info->crc_enable = true;
1849         else
1850                 hw_link_info->crc_enable = false;
1851
1852         if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1853                 hw_link_info->lse_enable = true;
1854         else
1855                 hw_link_info->lse_enable = false;
1856
1857         if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1858              hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1859                 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1860
1861         /* save link status information */
1862         if (link)
1863                 *link = *hw_link_info;
1864
1865         /* flag cleared so helper functions don't call AQ again */
1866         hw->phy.get_link_info = false;
1867
1868 aq_get_link_info_exit:
1869         return status;
1870 }
1871
1872 /**
1873  * i40e_aq_set_phy_int_mask
1874  * @hw: pointer to the hw struct
1875  * @mask: interrupt mask to be set
1876  * @cmd_details: pointer to command details structure or NULL
1877  *
1878  * Set link interrupt mask.
1879  **/
1880 i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1881                                      u16 mask,
1882                                      struct i40e_asq_cmd_details *cmd_details)
1883 {
1884         struct i40e_aq_desc desc;
1885         struct i40e_aqc_set_phy_int_mask *cmd =
1886                 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1887         i40e_status status;
1888
1889         i40e_fill_default_direct_cmd_desc(&desc,
1890                                           i40e_aqc_opc_set_phy_int_mask);
1891
1892         cmd->event_mask = cpu_to_le16(mask);
1893
1894         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1895
1896         return status;
1897 }
1898
1899 /**
1900  * i40e_aq_set_phy_debug
1901  * @hw: pointer to the hw struct
1902  * @cmd_flags: debug command flags
1903  * @cmd_details: pointer to command details structure or NULL
1904  *
1905  * Reset the external PHY.
1906  **/
1907 i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1908                                   struct i40e_asq_cmd_details *cmd_details)
1909 {
1910         struct i40e_aq_desc desc;
1911         struct i40e_aqc_set_phy_debug *cmd =
1912                 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1913         i40e_status status;
1914
1915         i40e_fill_default_direct_cmd_desc(&desc,
1916                                           i40e_aqc_opc_set_phy_debug);
1917
1918         cmd->command_flags = cmd_flags;
1919
1920         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1921
1922         return status;
1923 }
1924
1925 /**
1926  * i40e_is_aq_api_ver_ge
1927  * @aq: pointer to AdminQ info containing HW API version to compare
1928  * @maj: API major value
1929  * @min: API minor value
1930  *
1931  * Assert whether current HW API version is greater/equal than provided.
1932  **/
1933 static bool i40e_is_aq_api_ver_ge(struct i40e_adminq_info *aq, u16 maj,
1934                                   u16 min)
1935 {
1936         return (aq->api_maj_ver > maj ||
1937                 (aq->api_maj_ver == maj && aq->api_min_ver >= min));
1938 }
1939
1940 /**
1941  * i40e_aq_add_vsi
1942  * @hw: pointer to the hw struct
1943  * @vsi_ctx: pointer to a vsi context struct
1944  * @cmd_details: pointer to command details structure or NULL
1945  *
1946  * Add a VSI context to the hardware.
1947 **/
1948 i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1949                                 struct i40e_vsi_context *vsi_ctx,
1950                                 struct i40e_asq_cmd_details *cmd_details)
1951 {
1952         struct i40e_aq_desc desc;
1953         struct i40e_aqc_add_get_update_vsi *cmd =
1954                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1955         struct i40e_aqc_add_get_update_vsi_completion *resp =
1956                 (struct i40e_aqc_add_get_update_vsi_completion *)
1957                 &desc.params.raw;
1958         i40e_status status;
1959
1960         i40e_fill_default_direct_cmd_desc(&desc,
1961                                           i40e_aqc_opc_add_vsi);
1962
1963         cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1964         cmd->connection_type = vsi_ctx->connection_type;
1965         cmd->vf_id = vsi_ctx->vf_num;
1966         cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1967
1968         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1969
1970         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1971                                     sizeof(vsi_ctx->info), cmd_details);
1972
1973         if (status)
1974                 goto aq_add_vsi_exit;
1975
1976         vsi_ctx->seid = le16_to_cpu(resp->seid);
1977         vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1978         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1979         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1980
1981 aq_add_vsi_exit:
1982         return status;
1983 }
1984
1985 /**
1986  * i40e_aq_set_default_vsi
1987  * @hw: pointer to the hw struct
1988  * @seid: vsi number
1989  * @cmd_details: pointer to command details structure or NULL
1990  **/
1991 i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw,
1992                                     u16 seid,
1993                                     struct i40e_asq_cmd_details *cmd_details)
1994 {
1995         struct i40e_aq_desc desc;
1996         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1997                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1998                 &desc.params.raw;
1999         i40e_status status;
2000
2001         i40e_fill_default_direct_cmd_desc(&desc,
2002                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2003
2004         cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2005         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2006         cmd->seid = cpu_to_le16(seid);
2007
2008         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2009
2010         return status;
2011 }
2012
2013 /**
2014  * i40e_aq_clear_default_vsi
2015  * @hw: pointer to the hw struct
2016  * @seid: vsi number
2017  * @cmd_details: pointer to command details structure or NULL
2018  **/
2019 i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2020                                       u16 seid,
2021                                       struct i40e_asq_cmd_details *cmd_details)
2022 {
2023         struct i40e_aq_desc desc;
2024         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2025                 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2026                 &desc.params.raw;
2027         i40e_status status;
2028
2029         i40e_fill_default_direct_cmd_desc(&desc,
2030                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2031
2032         cmd->promiscuous_flags = cpu_to_le16(0);
2033         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
2034         cmd->seid = cpu_to_le16(seid);
2035
2036         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2037
2038         return status;
2039 }
2040
2041 /**
2042  * i40e_aq_set_vsi_unicast_promiscuous
2043  * @hw: pointer to the hw struct
2044  * @seid: vsi number
2045  * @set: set unicast promiscuous enable/disable
2046  * @cmd_details: pointer to command details structure or NULL
2047  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2048  **/
2049 i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2050                                 u16 seid, bool set,
2051                                 struct i40e_asq_cmd_details *cmd_details,
2052                                 bool rx_only_promisc)
2053 {
2054         struct i40e_aq_desc desc;
2055         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2056                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2057         i40e_status status;
2058         u16 flags = 0;
2059
2060         i40e_fill_default_direct_cmd_desc(&desc,
2061                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2062
2063         if (set) {
2064                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2065                 if (rx_only_promisc && i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2066                         flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2067         }
2068
2069         cmd->promiscuous_flags = cpu_to_le16(flags);
2070
2071         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2072         if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2073                 cmd->valid_flags |=
2074                         cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2075
2076         cmd->seid = cpu_to_le16(seid);
2077         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2078
2079         return status;
2080 }
2081
2082 /**
2083  * i40e_aq_set_vsi_multicast_promiscuous
2084  * @hw: pointer to the hw struct
2085  * @seid: vsi number
2086  * @set: set multicast promiscuous enable/disable
2087  * @cmd_details: pointer to command details structure or NULL
2088  **/
2089 i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2090                                 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2091 {
2092         struct i40e_aq_desc desc;
2093         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2094                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2095         i40e_status status;
2096         u16 flags = 0;
2097
2098         i40e_fill_default_direct_cmd_desc(&desc,
2099                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2100
2101         if (set)
2102                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2103
2104         cmd->promiscuous_flags = cpu_to_le16(flags);
2105
2106         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2107
2108         cmd->seid = cpu_to_le16(seid);
2109         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2110
2111         return status;
2112 }
2113
2114 /**
2115  * i40e_aq_set_vsi_mc_promisc_on_vlan
2116  * @hw: pointer to the hw struct
2117  * @seid: vsi number
2118  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2119  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2120  * @cmd_details: pointer to command details structure or NULL
2121  **/
2122 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2123                                                          u16 seid, bool enable,
2124                                                          u16 vid,
2125                                 struct i40e_asq_cmd_details *cmd_details)
2126 {
2127         struct i40e_aq_desc desc;
2128         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2129                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2130         enum i40e_status_code status;
2131         u16 flags = 0;
2132
2133         i40e_fill_default_direct_cmd_desc(&desc,
2134                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2135
2136         if (enable)
2137                 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2138
2139         cmd->promiscuous_flags = cpu_to_le16(flags);
2140         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2141         cmd->seid = cpu_to_le16(seid);
2142         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2143
2144         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2145
2146         return status;
2147 }
2148
2149 /**
2150  * i40e_aq_set_vsi_uc_promisc_on_vlan
2151  * @hw: pointer to the hw struct
2152  * @seid: vsi number
2153  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2154  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2155  * @cmd_details: pointer to command details structure or NULL
2156  **/
2157 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2158                                                          u16 seid, bool enable,
2159                                                          u16 vid,
2160                                 struct i40e_asq_cmd_details *cmd_details)
2161 {
2162         struct i40e_aq_desc desc;
2163         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2164                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2165         enum i40e_status_code status;
2166         u16 flags = 0;
2167
2168         i40e_fill_default_direct_cmd_desc(&desc,
2169                                           i40e_aqc_opc_set_vsi_promiscuous_modes);
2170
2171         if (enable) {
2172                 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2173                 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2174                         flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2175         }
2176
2177         cmd->promiscuous_flags = cpu_to_le16(flags);
2178         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2179         if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2180                 cmd->valid_flags |=
2181                         cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2182         cmd->seid = cpu_to_le16(seid);
2183         cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2184
2185         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2186
2187         return status;
2188 }
2189
2190 /**
2191  * i40e_aq_set_vsi_broadcast
2192  * @hw: pointer to the hw struct
2193  * @seid: vsi number
2194  * @set_filter: true to set filter, false to clear filter
2195  * @cmd_details: pointer to command details structure or NULL
2196  *
2197  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2198  **/
2199 i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2200                                 u16 seid, bool set_filter,
2201                                 struct i40e_asq_cmd_details *cmd_details)
2202 {
2203         struct i40e_aq_desc desc;
2204         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2205                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2206         i40e_status status;
2207
2208         i40e_fill_default_direct_cmd_desc(&desc,
2209                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2210
2211         if (set_filter)
2212                 cmd->promiscuous_flags
2213                             |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2214         else
2215                 cmd->promiscuous_flags
2216                             &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2217
2218         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2219         cmd->seid = cpu_to_le16(seid);
2220         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2221
2222         return status;
2223 }
2224
2225 /**
2226  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2227  * @hw: pointer to the hw struct
2228  * @seid: vsi number
2229  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2230  * @cmd_details: pointer to command details structure or NULL
2231  **/
2232 i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2233                                        u16 seid, bool enable,
2234                                        struct i40e_asq_cmd_details *cmd_details)
2235 {
2236         struct i40e_aq_desc desc;
2237         struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2238                 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2239         i40e_status status;
2240         u16 flags = 0;
2241
2242         i40e_fill_default_direct_cmd_desc(&desc,
2243                                         i40e_aqc_opc_set_vsi_promiscuous_modes);
2244         if (enable)
2245                 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2246
2247         cmd->promiscuous_flags = cpu_to_le16(flags);
2248         cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2249         cmd->seid = cpu_to_le16(seid);
2250
2251         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2252
2253         return status;
2254 }
2255
2256 /**
2257  * i40e_get_vsi_params - get VSI configuration info
2258  * @hw: pointer to the hw struct
2259  * @vsi_ctx: pointer to a vsi context struct
2260  * @cmd_details: pointer to command details structure or NULL
2261  **/
2262 i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2263                                 struct i40e_vsi_context *vsi_ctx,
2264                                 struct i40e_asq_cmd_details *cmd_details)
2265 {
2266         struct i40e_aq_desc desc;
2267         struct i40e_aqc_add_get_update_vsi *cmd =
2268                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2269         struct i40e_aqc_add_get_update_vsi_completion *resp =
2270                 (struct i40e_aqc_add_get_update_vsi_completion *)
2271                 &desc.params.raw;
2272         i40e_status status;
2273
2274         i40e_fill_default_direct_cmd_desc(&desc,
2275                                           i40e_aqc_opc_get_vsi_parameters);
2276
2277         cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2278
2279         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2280
2281         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2282                                     sizeof(vsi_ctx->info), NULL);
2283
2284         if (status)
2285                 goto aq_get_vsi_params_exit;
2286
2287         vsi_ctx->seid = le16_to_cpu(resp->seid);
2288         vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2289         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2290         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2291
2292 aq_get_vsi_params_exit:
2293         return status;
2294 }
2295
2296 /**
2297  * i40e_aq_update_vsi_params
2298  * @hw: pointer to the hw struct
2299  * @vsi_ctx: pointer to a vsi context struct
2300  * @cmd_details: pointer to command details structure or NULL
2301  *
2302  * Update a VSI context.
2303  **/
2304 i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2305                                 struct i40e_vsi_context *vsi_ctx,
2306                                 struct i40e_asq_cmd_details *cmd_details)
2307 {
2308         struct i40e_aq_desc desc;
2309         struct i40e_aqc_add_get_update_vsi *cmd =
2310                 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2311         struct i40e_aqc_add_get_update_vsi_completion *resp =
2312                 (struct i40e_aqc_add_get_update_vsi_completion *)
2313                 &desc.params.raw;
2314         i40e_status status;
2315
2316         i40e_fill_default_direct_cmd_desc(&desc,
2317                                           i40e_aqc_opc_update_vsi_parameters);
2318         cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2319
2320         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2321
2322         status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2323                                     sizeof(vsi_ctx->info), cmd_details);
2324
2325         vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2326         vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2327
2328         return status;
2329 }
2330
2331 /**
2332  * i40e_aq_get_switch_config
2333  * @hw: pointer to the hardware structure
2334  * @buf: pointer to the result buffer
2335  * @buf_size: length of input buffer
2336  * @start_seid: seid to start for the report, 0 == beginning
2337  * @cmd_details: pointer to command details structure or NULL
2338  *
2339  * Fill the buf with switch configuration returned from AdminQ command
2340  **/
2341 i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2342                                 struct i40e_aqc_get_switch_config_resp *buf,
2343                                 u16 buf_size, u16 *start_seid,
2344                                 struct i40e_asq_cmd_details *cmd_details)
2345 {
2346         struct i40e_aq_desc desc;
2347         struct i40e_aqc_switch_seid *scfg =
2348                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2349         i40e_status status;
2350
2351         i40e_fill_default_direct_cmd_desc(&desc,
2352                                           i40e_aqc_opc_get_switch_config);
2353         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2354         if (buf_size > I40E_AQ_LARGE_BUF)
2355                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2356         scfg->seid = cpu_to_le16(*start_seid);
2357
2358         status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2359         *start_seid = le16_to_cpu(scfg->seid);
2360
2361         return status;
2362 }
2363
2364 /**
2365  * i40e_aq_set_switch_config
2366  * @hw: pointer to the hardware structure
2367  * @flags: bit flag values to set
2368  * @valid_flags: which bit flags to set
2369  * @cmd_details: pointer to command details structure or NULL
2370  *
2371  * Set switch configuration bits
2372  **/
2373 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2374                                                 u16 flags,
2375                                                 u16 valid_flags,
2376                                 struct i40e_asq_cmd_details *cmd_details)
2377 {
2378         struct i40e_aq_desc desc;
2379         struct i40e_aqc_set_switch_config *scfg =
2380                 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2381         enum i40e_status_code status;
2382
2383         i40e_fill_default_direct_cmd_desc(&desc,
2384                                           i40e_aqc_opc_set_switch_config);
2385         scfg->flags = cpu_to_le16(flags);
2386         scfg->valid_flags = cpu_to_le16(valid_flags);
2387
2388         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2389
2390         return status;
2391 }
2392
2393 /**
2394  * i40e_aq_get_firmware_version
2395  * @hw: pointer to the hw struct
2396  * @fw_major_version: firmware major version
2397  * @fw_minor_version: firmware minor version
2398  * @fw_build: firmware build number
2399  * @api_major_version: major queue version
2400  * @api_minor_version: minor queue version
2401  * @cmd_details: pointer to command details structure or NULL
2402  *
2403  * Get the firmware version from the admin queue commands
2404  **/
2405 i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2406                                 u16 *fw_major_version, u16 *fw_minor_version,
2407                                 u32 *fw_build,
2408                                 u16 *api_major_version, u16 *api_minor_version,
2409                                 struct i40e_asq_cmd_details *cmd_details)
2410 {
2411         struct i40e_aq_desc desc;
2412         struct i40e_aqc_get_version *resp =
2413                 (struct i40e_aqc_get_version *)&desc.params.raw;
2414         i40e_status status;
2415
2416         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2417
2418         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2419
2420         if (!status) {
2421                 if (fw_major_version)
2422                         *fw_major_version = le16_to_cpu(resp->fw_major);
2423                 if (fw_minor_version)
2424                         *fw_minor_version = le16_to_cpu(resp->fw_minor);
2425                 if (fw_build)
2426                         *fw_build = le32_to_cpu(resp->fw_build);
2427                 if (api_major_version)
2428                         *api_major_version = le16_to_cpu(resp->api_major);
2429                 if (api_minor_version)
2430                         *api_minor_version = le16_to_cpu(resp->api_minor);
2431         }
2432
2433         return status;
2434 }
2435
2436 /**
2437  * i40e_aq_send_driver_version
2438  * @hw: pointer to the hw struct
2439  * @dv: driver's major, minor version
2440  * @cmd_details: pointer to command details structure or NULL
2441  *
2442  * Send the driver version to the firmware
2443  **/
2444 i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2445                                 struct i40e_driver_version *dv,
2446                                 struct i40e_asq_cmd_details *cmd_details)
2447 {
2448         struct i40e_aq_desc desc;
2449         struct i40e_aqc_driver_version *cmd =
2450                 (struct i40e_aqc_driver_version *)&desc.params.raw;
2451         i40e_status status;
2452         u16 len;
2453
2454         if (dv == NULL)
2455                 return I40E_ERR_PARAM;
2456
2457         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2458
2459         desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2460         cmd->driver_major_ver = dv->major_version;
2461         cmd->driver_minor_ver = dv->minor_version;
2462         cmd->driver_build_ver = dv->build_version;
2463         cmd->driver_subbuild_ver = dv->subbuild_version;
2464
2465         len = 0;
2466         while (len < sizeof(dv->driver_string) &&
2467                (dv->driver_string[len] < 0x80) &&
2468                dv->driver_string[len])
2469                 len++;
2470         status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2471                                        len, cmd_details);
2472
2473         return status;
2474 }
2475
2476 /**
2477  * i40e_get_link_status - get status of the HW network link
2478  * @hw: pointer to the hw struct
2479  * @link_up: pointer to bool (true/false = linkup/linkdown)
2480  *
2481  * Variable link_up true if link is up, false if link is down.
2482  * The variable link_up is invalid if returned value of status != 0
2483  *
2484  * Side effect: LinkStatusEvent reporting becomes enabled
2485  **/
2486 i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2487 {
2488         i40e_status status = 0;
2489
2490         if (hw->phy.get_link_info) {
2491                 status = i40e_update_link_info(hw);
2492
2493                 if (status)
2494                         i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2495                                    status);
2496         }
2497
2498         *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2499
2500         return status;
2501 }
2502
2503 /**
2504  * i40e_updatelink_status - update status of the HW network link
2505  * @hw: pointer to the hw struct
2506  **/
2507 i40e_status i40e_update_link_info(struct i40e_hw *hw)
2508 {
2509         struct i40e_aq_get_phy_abilities_resp abilities;
2510         i40e_status status = 0;
2511
2512         status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2513         if (status)
2514                 return status;
2515
2516         if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2517                 status = i40e_aq_get_phy_capabilities(hw, false, false,
2518                                                       &abilities, NULL);
2519                 if (status)
2520                         return status;
2521
2522                 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2523                        sizeof(hw->phy.link_info.module_type));
2524         }
2525
2526         return status;
2527 }
2528
2529 /**
2530  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2531  * @hw: pointer to the hw struct
2532  * @uplink_seid: the MAC or other gizmo SEID
2533  * @downlink_seid: the VSI SEID
2534  * @enabled_tc: bitmap of TCs to be enabled
2535  * @default_port: true for default port VSI, false for control port
2536  * @veb_seid: pointer to where to put the resulting VEB SEID
2537  * @enable_stats: true to turn on VEB stats
2538  * @cmd_details: pointer to command details structure or NULL
2539  *
2540  * This asks the FW to add a VEB between the uplink and downlink
2541  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2542  **/
2543 i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2544                                 u16 downlink_seid, u8 enabled_tc,
2545                                 bool default_port, u16 *veb_seid,
2546                                 bool enable_stats,
2547                                 struct i40e_asq_cmd_details *cmd_details)
2548 {
2549         struct i40e_aq_desc desc;
2550         struct i40e_aqc_add_veb *cmd =
2551                 (struct i40e_aqc_add_veb *)&desc.params.raw;
2552         struct i40e_aqc_add_veb_completion *resp =
2553                 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2554         i40e_status status;
2555         u16 veb_flags = 0;
2556
2557         /* SEIDs need to either both be set or both be 0 for floating VEB */
2558         if (!!uplink_seid != !!downlink_seid)
2559                 return I40E_ERR_PARAM;
2560
2561         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2562
2563         cmd->uplink_seid = cpu_to_le16(uplink_seid);
2564         cmd->downlink_seid = cpu_to_le16(downlink_seid);
2565         cmd->enable_tcs = enabled_tc;
2566         if (!uplink_seid)
2567                 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2568         if (default_port)
2569                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2570         else
2571                 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2572
2573         /* reverse logic here: set the bitflag to disable the stats */
2574         if (!enable_stats)
2575                 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2576
2577         cmd->veb_flags = cpu_to_le16(veb_flags);
2578
2579         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2580
2581         if (!status && veb_seid)
2582                 *veb_seid = le16_to_cpu(resp->veb_seid);
2583
2584         return status;
2585 }
2586
2587 /**
2588  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2589  * @hw: pointer to the hw struct
2590  * @veb_seid: the SEID of the VEB to query
2591  * @switch_id: the uplink switch id
2592  * @floating: set to true if the VEB is floating
2593  * @statistic_index: index of the stats counter block for this VEB
2594  * @vebs_used: number of VEB's used by function
2595  * @vebs_free: total VEB's not reserved by any function
2596  * @cmd_details: pointer to command details structure or NULL
2597  *
2598  * This retrieves the parameters for a particular VEB, specified by
2599  * uplink_seid, and returns them to the caller.
2600  **/
2601 i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2602                                 u16 veb_seid, u16 *switch_id,
2603                                 bool *floating, u16 *statistic_index,
2604                                 u16 *vebs_used, u16 *vebs_free,
2605                                 struct i40e_asq_cmd_details *cmd_details)
2606 {
2607         struct i40e_aq_desc desc;
2608         struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2609                 (struct i40e_aqc_get_veb_parameters_completion *)
2610                 &desc.params.raw;
2611         i40e_status status;
2612
2613         if (veb_seid == 0)
2614                 return I40E_ERR_PARAM;
2615
2616         i40e_fill_default_direct_cmd_desc(&desc,
2617                                           i40e_aqc_opc_get_veb_parameters);
2618         cmd_resp->seid = cpu_to_le16(veb_seid);
2619
2620         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2621         if (status)
2622                 goto get_veb_exit;
2623
2624         if (switch_id)
2625                 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2626         if (statistic_index)
2627                 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2628         if (vebs_used)
2629                 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2630         if (vebs_free)
2631                 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2632         if (floating) {
2633                 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2634
2635                 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2636                         *floating = true;
2637                 else
2638                         *floating = false;
2639         }
2640
2641 get_veb_exit:
2642         return status;
2643 }
2644
2645 /**
2646  * i40e_aq_add_macvlan
2647  * @hw: pointer to the hw struct
2648  * @seid: VSI for the mac address
2649  * @mv_list: list of macvlans to be added
2650  * @count: length of the list
2651  * @cmd_details: pointer to command details structure or NULL
2652  *
2653  * Add MAC/VLAN addresses to the HW filtering
2654  **/
2655 i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2656                         struct i40e_aqc_add_macvlan_element_data *mv_list,
2657                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2658 {
2659         struct i40e_aq_desc desc;
2660         struct i40e_aqc_macvlan *cmd =
2661                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2662         i40e_status status;
2663         u16 buf_size;
2664         int i;
2665
2666         if (count == 0 || !mv_list || !hw)
2667                 return I40E_ERR_PARAM;
2668
2669         buf_size = count * sizeof(*mv_list);
2670
2671         /* prep the rest of the request */
2672         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2673         cmd->num_addresses = cpu_to_le16(count);
2674         cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2675         cmd->seid[1] = 0;
2676         cmd->seid[2] = 0;
2677
2678         for (i = 0; i < count; i++)
2679                 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2680                         mv_list[i].flags |=
2681                                cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2682
2683         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2684         if (buf_size > I40E_AQ_LARGE_BUF)
2685                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2686
2687         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2688                                        cmd_details);
2689
2690         return status;
2691 }
2692
2693 /**
2694  * i40e_aq_remove_macvlan
2695  * @hw: pointer to the hw struct
2696  * @seid: VSI for the mac address
2697  * @mv_list: list of macvlans to be removed
2698  * @count: length of the list
2699  * @cmd_details: pointer to command details structure or NULL
2700  *
2701  * Remove MAC/VLAN addresses from the HW filtering
2702  **/
2703 i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2704                         struct i40e_aqc_remove_macvlan_element_data *mv_list,
2705                         u16 count, struct i40e_asq_cmd_details *cmd_details)
2706 {
2707         struct i40e_aq_desc desc;
2708         struct i40e_aqc_macvlan *cmd =
2709                 (struct i40e_aqc_macvlan *)&desc.params.raw;
2710         i40e_status status;
2711         u16 buf_size;
2712
2713         if (count == 0 || !mv_list || !hw)
2714                 return I40E_ERR_PARAM;
2715
2716         buf_size = count * sizeof(*mv_list);
2717
2718         /* prep the rest of the request */
2719         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2720         cmd->num_addresses = cpu_to_le16(count);
2721         cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2722         cmd->seid[1] = 0;
2723         cmd->seid[2] = 0;
2724
2725         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2726         if (buf_size > I40E_AQ_LARGE_BUF)
2727                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2728
2729         status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2730                                        cmd_details);
2731
2732         return status;
2733 }
2734
2735 /**
2736  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
2737  * @hw: pointer to the hw struct
2738  * @opcode: AQ opcode for add or delete mirror rule
2739  * @sw_seid: Switch SEID (to which rule refers)
2740  * @rule_type: Rule Type (ingress/egress/VLAN)
2741  * @id: Destination VSI SEID or Rule ID
2742  * @count: length of the list
2743  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2744  * @cmd_details: pointer to command details structure or NULL
2745  * @rule_id: Rule ID returned from FW
2746  * @rule_used: Number of rules used in internal switch
2747  * @rule_free: Number of rules free in internal switch
2748  *
2749  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
2750  * VEBs/VEPA elements only
2751  **/
2752 static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2753                                 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2754                                 u16 count, __le16 *mr_list,
2755                                 struct i40e_asq_cmd_details *cmd_details,
2756                                 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2757 {
2758         struct i40e_aq_desc desc;
2759         struct i40e_aqc_add_delete_mirror_rule *cmd =
2760                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2761         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2762         (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2763         i40e_status status;
2764         u16 buf_size;
2765
2766         buf_size = count * sizeof(*mr_list);
2767
2768         /* prep the rest of the request */
2769         i40e_fill_default_direct_cmd_desc(&desc, opcode);
2770         cmd->seid = cpu_to_le16(sw_seid);
2771         cmd->rule_type = cpu_to_le16(rule_type &
2772                                      I40E_AQC_MIRROR_RULE_TYPE_MASK);
2773         cmd->num_entries = cpu_to_le16(count);
2774         /* Dest VSI for add, rule_id for delete */
2775         cmd->destination = cpu_to_le16(id);
2776         if (mr_list) {
2777                 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2778                                                 I40E_AQ_FLAG_RD));
2779                 if (buf_size > I40E_AQ_LARGE_BUF)
2780                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2781         }
2782
2783         status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2784                                        cmd_details);
2785         if (!status ||
2786             hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2787                 if (rule_id)
2788                         *rule_id = le16_to_cpu(resp->rule_id);
2789                 if (rules_used)
2790                         *rules_used = le16_to_cpu(resp->mirror_rules_used);
2791                 if (rules_free)
2792                         *rules_free = le16_to_cpu(resp->mirror_rules_free);
2793         }
2794         return status;
2795 }
2796
2797 /**
2798  * i40e_aq_add_mirrorrule - add a mirror rule
2799  * @hw: pointer to the hw struct
2800  * @sw_seid: Switch SEID (to which rule refers)
2801  * @rule_type: Rule Type (ingress/egress/VLAN)
2802  * @dest_vsi: SEID of VSI to which packets will be mirrored
2803  * @count: length of the list
2804  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
2805  * @cmd_details: pointer to command details structure or NULL
2806  * @rule_id: Rule ID returned from FW
2807  * @rule_used: Number of rules used in internal switch
2808  * @rule_free: Number of rules free in internal switch
2809  *
2810  * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only
2811  **/
2812 i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2813                         u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2814                         struct i40e_asq_cmd_details *cmd_details,
2815                         u16 *rule_id, u16 *rules_used, u16 *rules_free)
2816 {
2817         if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2818             rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2819                 if (count == 0 || !mr_list)
2820                         return I40E_ERR_PARAM;
2821         }
2822
2823         return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2824                                   rule_type, dest_vsi, count, mr_list,
2825                                   cmd_details, rule_id, rules_used, rules_free);
2826 }
2827
2828 /**
2829  * i40e_aq_delete_mirrorrule - delete a mirror rule
2830  * @hw: pointer to the hw struct
2831  * @sw_seid: Switch SEID (to which rule refers)
2832  * @rule_type: Rule Type (ingress/egress/VLAN)
2833  * @count: length of the list
2834  * @rule_id: Rule ID that is returned in the receive desc as part of
2835  *              add_mirrorrule.
2836  * @mr_list: list of mirrored VLAN IDs to be removed
2837  * @cmd_details: pointer to command details structure or NULL
2838  * @rule_used: Number of rules used in internal switch
2839  * @rule_free: Number of rules free in internal switch
2840  *
2841  * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only
2842  **/
2843 i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2844                         u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2845                         struct i40e_asq_cmd_details *cmd_details,
2846                         u16 *rules_used, u16 *rules_free)
2847 {
2848         /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */
2849         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2850                 /* count and mr_list shall be valid for rule_type INGRESS VLAN
2851                  * mirroring. For other rule_type, count and rule_type should
2852                  * not matter.
2853                  */
2854                 if (count == 0 || !mr_list)
2855                         return I40E_ERR_PARAM;
2856         }
2857
2858         return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2859                                   rule_type, rule_id, count, mr_list,
2860                                   cmd_details, NULL, rules_used, rules_free);
2861 }
2862
2863 /**
2864  * i40e_aq_send_msg_to_vf
2865  * @hw: pointer to the hardware structure
2866  * @vfid: VF id to send msg
2867  * @v_opcode: opcodes for VF-PF communication
2868  * @v_retval: return error code
2869  * @msg: pointer to the msg buffer
2870  * @msglen: msg length
2871  * @cmd_details: pointer to command details
2872  *
2873  * send msg to vf
2874  **/
2875 i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2876                                 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2877                                 struct i40e_asq_cmd_details *cmd_details)
2878 {
2879         struct i40e_aq_desc desc;
2880         struct i40e_aqc_pf_vf_message *cmd =
2881                 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2882         i40e_status status;
2883
2884         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2885         cmd->id = cpu_to_le32(vfid);
2886         desc.cookie_high = cpu_to_le32(v_opcode);
2887         desc.cookie_low = cpu_to_le32(v_retval);
2888         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2889         if (msglen) {
2890                 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2891                                                 I40E_AQ_FLAG_RD));
2892                 if (msglen > I40E_AQ_LARGE_BUF)
2893                         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2894                 desc.datalen = cpu_to_le16(msglen);
2895         }
2896         status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2897
2898         return status;
2899 }
2900
2901 /**
2902  * i40e_aq_debug_read_register
2903  * @hw: pointer to the hw struct
2904  * @reg_addr: register address
2905  * @reg_val: register value
2906  * @cmd_details: pointer to command details structure or NULL
2907  *
2908  * Read the register using the admin queue commands
2909  **/
2910 i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2911                                 u32 reg_addr, u64 *reg_val,
2912                                 struct i40e_asq_cmd_details *cmd_details)
2913 {
2914         struct i40e_aq_desc desc;
2915         struct i40e_aqc_debug_reg_read_write *cmd_resp =
2916                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2917         i40e_status status;
2918
2919         if (reg_val == NULL)
2920                 return I40E_ERR_PARAM;
2921
2922         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2923
2924         cmd_resp->address = cpu_to_le32(reg_addr);
2925
2926         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2927
2928         if (!status) {
2929                 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2930                            (u64)le32_to_cpu(cmd_resp->value_low);
2931         }
2932
2933         return status;
2934 }
2935
2936 /**
2937  * i40e_aq_debug_write_register
2938  * @hw: pointer to the hw struct
2939  * @reg_addr: register address
2940  * @reg_val: register value
2941  * @cmd_details: pointer to command details structure or NULL
2942  *
2943  * Write to a register using the admin queue commands
2944  **/
2945 i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2946                                         u32 reg_addr, u64 reg_val,
2947                                         struct i40e_asq_cmd_details *cmd_details)
2948 {
2949         struct i40e_aq_desc desc;
2950         struct i40e_aqc_debug_reg_read_write *cmd =
2951                 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2952         i40e_status status;
2953
2954         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2955
2956         cmd->address = cpu_to_le32(reg_addr);
2957         cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2958         cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2959
2960         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2961
2962         return status;
2963 }
2964
2965 /**
2966  * i40e_aq_request_resource
2967  * @hw: pointer to the hw struct
2968  * @resource: resource id
2969  * @access: access type
2970  * @sdp_number: resource number
2971  * @timeout: the maximum time in ms that the driver may hold the resource
2972  * @cmd_details: pointer to command details structure or NULL
2973  *
2974  * requests common resource using the admin queue commands
2975  **/
2976 i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2977                                 enum i40e_aq_resources_ids resource,
2978                                 enum i40e_aq_resource_access_type access,
2979                                 u8 sdp_number, u64 *timeout,
2980                                 struct i40e_asq_cmd_details *cmd_details)
2981 {
2982         struct i40e_aq_desc desc;
2983         struct i40e_aqc_request_resource *cmd_resp =
2984                 (struct i40e_aqc_request_resource *)&desc.params.raw;
2985         i40e_status status;
2986
2987         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2988
2989         cmd_resp->resource_id = cpu_to_le16(resource);
2990         cmd_resp->access_type = cpu_to_le16(access);
2991         cmd_resp->resource_number = cpu_to_le32(sdp_number);
2992
2993         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2994         /* The completion specifies the maximum time in ms that the driver
2995          * may hold the resource in the Timeout field.
2996          * If the resource is held by someone else, the command completes with
2997          * busy return value and the timeout field indicates the maximum time
2998          * the current owner of the resource has to free it.
2999          */
3000         if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
3001                 *timeout = le32_to_cpu(cmd_resp->timeout);
3002
3003         return status;
3004 }
3005
3006 /**
3007  * i40e_aq_release_resource
3008  * @hw: pointer to the hw struct
3009  * @resource: resource id
3010  * @sdp_number: resource number
3011  * @cmd_details: pointer to command details structure or NULL
3012  *
3013  * release common resource using the admin queue commands
3014  **/
3015 i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
3016                                 enum i40e_aq_resources_ids resource,
3017                                 u8 sdp_number,
3018                                 struct i40e_asq_cmd_details *cmd_details)
3019 {
3020         struct i40e_aq_desc desc;
3021         struct i40e_aqc_request_resource *cmd =
3022                 (struct i40e_aqc_request_resource *)&desc.params.raw;
3023         i40e_status status;
3024
3025         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3026
3027         cmd->resource_id = cpu_to_le16(resource);
3028         cmd->resource_number = cpu_to_le32(sdp_number);
3029
3030         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3031
3032         return status;
3033 }
3034
3035 /**
3036  * i40e_aq_read_nvm
3037  * @hw: pointer to the hw struct
3038  * @module_pointer: module pointer location in words from the NVM beginning
3039  * @offset: byte offset from the module beginning
3040  * @length: length of the section to be read (in bytes from the offset)
3041  * @data: command buffer (size [bytes] = length)
3042  * @last_command: tells if this is the last command in a series
3043  * @cmd_details: pointer to command details structure or NULL
3044  *
3045  * Read the NVM using the admin queue commands
3046  **/
3047 i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3048                                 u32 offset, u16 length, void *data,
3049                                 bool last_command,
3050                                 struct i40e_asq_cmd_details *cmd_details)
3051 {
3052         struct i40e_aq_desc desc;
3053         struct i40e_aqc_nvm_update *cmd =
3054                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3055         i40e_status status;
3056
3057         /* In offset the highest byte must be zeroed. */
3058         if (offset & 0xFF000000) {
3059                 status = I40E_ERR_PARAM;
3060                 goto i40e_aq_read_nvm_exit;
3061         }
3062
3063         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3064
3065         /* If this is the last command in a series, set the proper flag. */
3066         if (last_command)
3067                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3068         cmd->module_pointer = module_pointer;
3069         cmd->offset = cpu_to_le32(offset);
3070         cmd->length = cpu_to_le16(length);
3071
3072         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3073         if (length > I40E_AQ_LARGE_BUF)
3074                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3075
3076         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3077
3078 i40e_aq_read_nvm_exit:
3079         return status;
3080 }
3081
3082 /**
3083  * i40e_aq_erase_nvm
3084  * @hw: pointer to the hw struct
3085  * @module_pointer: module pointer location in words from the NVM beginning
3086  * @offset: offset in the module (expressed in 4 KB from module's beginning)
3087  * @length: length of the section to be erased (expressed in 4 KB)
3088  * @last_command: tells if this is the last command in a series
3089  * @cmd_details: pointer to command details structure or NULL
3090  *
3091  * Erase the NVM sector using the admin queue commands
3092  **/
3093 i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3094                               u32 offset, u16 length, bool last_command,
3095                               struct i40e_asq_cmd_details *cmd_details)
3096 {
3097         struct i40e_aq_desc desc;
3098         struct i40e_aqc_nvm_update *cmd =
3099                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3100         i40e_status status;
3101
3102         /* In offset the highest byte must be zeroed. */
3103         if (offset & 0xFF000000) {
3104                 status = I40E_ERR_PARAM;
3105                 goto i40e_aq_erase_nvm_exit;
3106         }
3107
3108         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3109
3110         /* If this is the last command in a series, set the proper flag. */
3111         if (last_command)
3112                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3113         cmd->module_pointer = module_pointer;
3114         cmd->offset = cpu_to_le32(offset);
3115         cmd->length = cpu_to_le16(length);
3116
3117         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3118
3119 i40e_aq_erase_nvm_exit:
3120         return status;
3121 }
3122
3123 /**
3124  * i40e_parse_discover_capabilities
3125  * @hw: pointer to the hw struct
3126  * @buff: pointer to a buffer containing device/function capability records
3127  * @cap_count: number of capability records in the list
3128  * @list_type_opc: type of capabilities list to parse
3129  *
3130  * Parse the device/function capabilities list.
3131  **/
3132 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3133                                      u32 cap_count,
3134                                      enum i40e_admin_queue_opc list_type_opc)
3135 {
3136         struct i40e_aqc_list_capabilities_element_resp *cap;
3137         u32 valid_functions, num_functions;
3138         u32 number, logical_id, phys_id;
3139         struct i40e_hw_capabilities *p;
3140         u8 major_rev;
3141         u32 i = 0;
3142         u16 id;
3143
3144         cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3145
3146         if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3147                 p = &hw->dev_caps;
3148         else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3149                 p = &hw->func_caps;
3150         else
3151                 return;
3152
3153         for (i = 0; i < cap_count; i++, cap++) {
3154                 id = le16_to_cpu(cap->id);
3155                 number = le32_to_cpu(cap->number);
3156                 logical_id = le32_to_cpu(cap->logical_id);
3157                 phys_id = le32_to_cpu(cap->phys_id);
3158                 major_rev = cap->major_rev;
3159
3160                 switch (id) {
3161                 case I40E_AQ_CAP_ID_SWITCH_MODE:
3162                         p->switch_mode = number;
3163                         break;
3164                 case I40E_AQ_CAP_ID_MNG_MODE:
3165                         p->management_mode = number;
3166                         break;
3167                 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3168                         p->npar_enable = number;
3169                         break;
3170                 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3171                         p->os2bmc = number;
3172                         break;
3173                 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3174                         p->valid_functions = number;
3175                         break;
3176                 case I40E_AQ_CAP_ID_SRIOV:
3177                         if (number == 1)
3178                                 p->sr_iov_1_1 = true;
3179                         break;
3180                 case I40E_AQ_CAP_ID_VF:
3181                         p->num_vfs = number;
3182                         p->vf_base_id = logical_id;
3183                         break;
3184                 case I40E_AQ_CAP_ID_VMDQ:
3185                         if (number == 1)
3186                                 p->vmdq = true;
3187                         break;
3188                 case I40E_AQ_CAP_ID_8021QBG:
3189                         if (number == 1)
3190                                 p->evb_802_1_qbg = true;
3191                         break;
3192                 case I40E_AQ_CAP_ID_8021QBR:
3193                         if (number == 1)
3194                                 p->evb_802_1_qbh = true;
3195                         break;
3196                 case I40E_AQ_CAP_ID_VSI:
3197                         p->num_vsis = number;
3198                         break;
3199                 case I40E_AQ_CAP_ID_DCB:
3200                         if (number == 1) {
3201                                 p->dcb = true;
3202                                 p->enabled_tcmap = logical_id;
3203                                 p->maxtc = phys_id;
3204                         }
3205                         break;
3206                 case I40E_AQ_CAP_ID_FCOE:
3207                         if (number == 1)
3208                                 p->fcoe = true;
3209                         break;
3210                 case I40E_AQ_CAP_ID_ISCSI:
3211                         if (number == 1)
3212                                 p->iscsi = true;
3213                         break;
3214                 case I40E_AQ_CAP_ID_RSS:
3215                         p->rss = true;
3216                         p->rss_table_size = number;
3217                         p->rss_table_entry_width = logical_id;
3218                         break;
3219                 case I40E_AQ_CAP_ID_RXQ:
3220                         p->num_rx_qp = number;
3221                         p->base_queue = phys_id;
3222                         break;
3223                 case I40E_AQ_CAP_ID_TXQ:
3224                         p->num_tx_qp = number;
3225                         p->base_queue = phys_id;
3226                         break;
3227                 case I40E_AQ_CAP_ID_MSIX:
3228                         p->num_msix_vectors = number;
3229                         i40e_debug(hw, I40E_DEBUG_INIT,
3230                                    "HW Capability: MSIX vector count = %d\n",
3231                                    p->num_msix_vectors);
3232                         break;
3233                 case I40E_AQ_CAP_ID_VF_MSIX:
3234                         p->num_msix_vectors_vf = number;
3235                         break;
3236                 case I40E_AQ_CAP_ID_FLEX10:
3237                         if (major_rev == 1) {
3238                                 if (number == 1) {
3239                                         p->flex10_enable = true;
3240                                         p->flex10_capable = true;
3241                                 }
3242                         } else {
3243                                 /* Capability revision >= 2 */
3244                                 if (number & 1)
3245                                         p->flex10_enable = true;
3246                                 if (number & 2)
3247                                         p->flex10_capable = true;
3248                         }
3249                         p->flex10_mode = logical_id;
3250                         p->flex10_status = phys_id;
3251                         break;
3252                 case I40E_AQ_CAP_ID_CEM:
3253                         if (number == 1)
3254                                 p->mgmt_cem = true;
3255                         break;
3256                 case I40E_AQ_CAP_ID_IWARP:
3257                         if (number == 1)
3258                                 p->iwarp = true;
3259                         break;
3260                 case I40E_AQ_CAP_ID_LED:
3261                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3262                                 p->led[phys_id] = true;
3263                         break;
3264                 case I40E_AQ_CAP_ID_SDP:
3265                         if (phys_id < I40E_HW_CAP_MAX_GPIO)
3266                                 p->sdp[phys_id] = true;
3267                         break;
3268                 case I40E_AQ_CAP_ID_MDIO:
3269                         if (number == 1) {
3270                                 p->mdio_port_num = phys_id;
3271                                 p->mdio_port_mode = logical_id;
3272                         }
3273                         break;
3274                 case I40E_AQ_CAP_ID_1588:
3275                         if (number == 1)
3276                                 p->ieee_1588 = true;
3277                         break;
3278                 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3279                         p->fd = true;
3280                         p->fd_filters_guaranteed = number;
3281                         p->fd_filters_best_effort = logical_id;
3282                         break;
3283                 case I40E_AQ_CAP_ID_WSR_PROT:
3284                         p->wr_csr_prot = (u64)number;
3285                         p->wr_csr_prot |= (u64)logical_id << 32;
3286                         break;
3287                 case I40E_AQ_CAP_ID_NVM_MGMT:
3288                         if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3289                                 p->sec_rev_disabled = true;
3290                         if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3291                                 p->update_disabled = true;
3292                         break;
3293                 default:
3294                         break;
3295                 }
3296         }
3297
3298         if (p->fcoe)
3299                 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3300
3301         /* Software override ensuring FCoE is disabled if npar or mfp
3302          * mode because it is not supported in these modes.
3303          */
3304         if (p->npar_enable || p->flex10_enable)
3305                 p->fcoe = false;
3306
3307         /* count the enabled ports (aka the "not disabled" ports) */
3308         hw->num_ports = 0;
3309         for (i = 0; i < 4; i++) {
3310                 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3311                 u64 port_cfg = 0;
3312
3313                 /* use AQ read to get the physical register offset instead
3314                  * of the port relative offset
3315                  */
3316                 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3317                 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3318                         hw->num_ports++;
3319         }
3320
3321         valid_functions = p->valid_functions;
3322         num_functions = 0;
3323         while (valid_functions) {
3324                 if (valid_functions & 1)
3325                         num_functions++;
3326                 valid_functions >>= 1;
3327         }
3328
3329         /* partition id is 1-based, and functions are evenly spread
3330          * across the ports as partitions
3331          */
3332         hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3333         hw->num_partitions = num_functions / hw->num_ports;
3334
3335         /* additional HW specific goodies that might
3336          * someday be HW version specific
3337          */
3338         p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3339 }
3340
3341 /**
3342  * i40e_aq_discover_capabilities
3343  * @hw: pointer to the hw struct
3344  * @buff: a virtual buffer to hold the capabilities
3345  * @buff_size: Size of the virtual buffer
3346  * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
3347  * @list_type_opc: capabilities type to discover - pass in the command opcode
3348  * @cmd_details: pointer to command details structure or NULL
3349  *
3350  * Get the device capabilities descriptions from the firmware
3351  **/
3352 i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3353                                 void *buff, u16 buff_size, u16 *data_size,
3354                                 enum i40e_admin_queue_opc list_type_opc,
3355                                 struct i40e_asq_cmd_details *cmd_details)
3356 {
3357         struct i40e_aqc_list_capabilites *cmd;
3358         struct i40e_aq_desc desc;
3359         i40e_status status = 0;
3360
3361         cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3362
3363         if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3364                 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3365                 status = I40E_ERR_PARAM;
3366                 goto exit;
3367         }
3368
3369         i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3370
3371         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3372         if (buff_size > I40E_AQ_LARGE_BUF)
3373                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3374
3375         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3376         *data_size = le16_to_cpu(desc.datalen);
3377
3378         if (status)
3379                 goto exit;
3380
3381         i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3382                                          list_type_opc);
3383
3384 exit:
3385         return status;
3386 }
3387
3388 /**
3389  * i40e_aq_update_nvm
3390  * @hw: pointer to the hw struct
3391  * @module_pointer: module pointer location in words from the NVM beginning
3392  * @offset: byte offset from the module beginning
3393  * @length: length of the section to be written (in bytes from the offset)
3394  * @data: command buffer (size [bytes] = length)
3395  * @last_command: tells if this is the last command in a series
3396  * @cmd_details: pointer to command details structure or NULL
3397  *
3398  * Update the NVM using the admin queue commands
3399  **/
3400 i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3401                                u32 offset, u16 length, void *data,
3402                                bool last_command,
3403                                struct i40e_asq_cmd_details *cmd_details)
3404 {
3405         struct i40e_aq_desc desc;
3406         struct i40e_aqc_nvm_update *cmd =
3407                 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3408         i40e_status status;
3409
3410         /* In offset the highest byte must be zeroed. */
3411         if (offset & 0xFF000000) {
3412                 status = I40E_ERR_PARAM;
3413                 goto i40e_aq_update_nvm_exit;
3414         }
3415
3416         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3417
3418         /* If this is the last command in a series, set the proper flag. */
3419         if (last_command)
3420                 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3421         cmd->module_pointer = module_pointer;
3422         cmd->offset = cpu_to_le32(offset);
3423         cmd->length = cpu_to_le16(length);
3424
3425         desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3426         if (length > I40E_AQ_LARGE_BUF)
3427                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3428
3429         status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3430
3431 i40e_aq_update_nvm_exit:
3432         return status;
3433 }
3434
3435 /**
3436  * i40e_aq_get_lldp_mib
3437  * @hw: pointer to the hw struct
3438  * @bridge_type: type of bridge requested
3439  * @mib_type: Local, Remote or both Local and Remote MIBs
3440  * @buff: pointer to a user supplied buffer to store the MIB block
3441  * @buff_size: size of the buffer (in bytes)
3442  * @local_len : length of the returned Local LLDP MIB
3443  * @remote_len: length of the returned Remote LLDP MIB
3444  * @cmd_details: pointer to command details structure or NULL
3445  *
3446  * Requests the complete LLDP MIB (entire packet).
3447  **/
3448 i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3449                                 u8 mib_type, void *buff, u16 buff_size,
3450                                 u16 *local_len, u16 *remote_len,
3451                                 struct i40e_asq_cmd_details *cmd_details)
3452 {
3453         struct i40e_aq_desc desc;
3454         struct i40e_aqc_lldp_get_mib *cmd =
3455                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3456         struct i40e_aqc_lldp_get_mib *resp =
3457                 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3458         i40e_status status;
3459
3460         if (buff_size == 0 || !buff)
3461                 return I40E_ERR_PARAM;
3462
3463         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3464         /* Indirect Command */
3465         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3466
3467         cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3468         cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3469                        I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3470
3471         desc.datalen = cpu_to_le16(buff_size);
3472
3473         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3474         if (buff_size > I40E_AQ_LARGE_BUF)
3475                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3476
3477         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3478         if (!status) {
3479                 if (local_len != NULL)
3480                         *local_len = le16_to_cpu(resp->local_len);
3481                 if (remote_len != NULL)
3482                         *remote_len = le16_to_cpu(resp->remote_len);
3483         }
3484
3485         return status;
3486 }
3487
3488 /**
3489  * i40e_aq_cfg_lldp_mib_change_event
3490  * @hw: pointer to the hw struct
3491  * @enable_update: Enable or Disable event posting
3492  * @cmd_details: pointer to command details structure or NULL
3493  *
3494  * Enable or Disable posting of an event on ARQ when LLDP MIB
3495  * associated with the interface changes
3496  **/
3497 i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3498                                 bool enable_update,
3499                                 struct i40e_asq_cmd_details *cmd_details)
3500 {
3501         struct i40e_aq_desc desc;
3502         struct i40e_aqc_lldp_update_mib *cmd =
3503                 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3504         i40e_status status;
3505
3506         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3507
3508         if (!enable_update)
3509                 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3510
3511         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3512
3513         return status;
3514 }
3515
3516 /**
3517  * i40e_aq_stop_lldp
3518  * @hw: pointer to the hw struct
3519  * @shutdown_agent: True if LLDP Agent needs to be Shutdown
3520  * @cmd_details: pointer to command details structure or NULL
3521  *
3522  * Stop or Shutdown the embedded LLDP Agent
3523  **/
3524 i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3525                                 struct i40e_asq_cmd_details *cmd_details)
3526 {
3527         struct i40e_aq_desc desc;
3528         struct i40e_aqc_lldp_stop *cmd =
3529                 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3530         i40e_status status;
3531
3532         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3533
3534         if (shutdown_agent)
3535                 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3536
3537         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3538
3539         return status;
3540 }
3541
3542 /**
3543  * i40e_aq_start_lldp
3544  * @hw: pointer to the hw struct
3545  * @cmd_details: pointer to command details structure or NULL
3546  *
3547  * Start the embedded LLDP Agent on all ports.
3548  **/
3549 i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3550                                 struct i40e_asq_cmd_details *cmd_details)
3551 {
3552         struct i40e_aq_desc desc;
3553         struct i40e_aqc_lldp_start *cmd =
3554                 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3555         i40e_status status;
3556
3557         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3558
3559         cmd->command = I40E_AQ_LLDP_AGENT_START;
3560
3561         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3562
3563         return status;
3564 }
3565
3566 /**
3567  * i40e_aq_get_cee_dcb_config
3568  * @hw: pointer to the hw struct
3569  * @buff: response buffer that stores CEE operational configuration
3570  * @buff_size: size of the buffer passed
3571  * @cmd_details: pointer to command details structure or NULL
3572  *
3573  * Get CEE DCBX mode operational configuration from firmware
3574  **/
3575 i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3576                                        void *buff, u16 buff_size,
3577                                        struct i40e_asq_cmd_details *cmd_details)
3578 {
3579         struct i40e_aq_desc desc;
3580         i40e_status status;
3581
3582         if (buff_size == 0 || !buff)
3583                 return I40E_ERR_PARAM;
3584
3585         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3586
3587         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3588         status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3589                                        cmd_details);
3590
3591         return status;
3592 }
3593
3594 /**
3595  * i40e_aq_add_udp_tunnel
3596  * @hw: pointer to the hw struct
3597  * @udp_port: the UDP port to add
3598  * @header_len: length of the tunneling header length in DWords
3599  * @protocol_index: protocol index type
3600  * @filter_index: pointer to filter index
3601  * @cmd_details: pointer to command details structure or NULL
3602  **/
3603 i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3604                                 u16 udp_port, u8 protocol_index,
3605                                 u8 *filter_index,
3606                                 struct i40e_asq_cmd_details *cmd_details)
3607 {
3608         struct i40e_aq_desc desc;
3609         struct i40e_aqc_add_udp_tunnel *cmd =
3610                 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3611         struct i40e_aqc_del_udp_tunnel_completion *resp =
3612                 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3613         i40e_status status;
3614
3615         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3616
3617         cmd->udp_port = cpu_to_le16(udp_port);
3618         cmd->protocol_type = protocol_index;
3619
3620         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3621
3622         if (!status && filter_index)
3623                 *filter_index = resp->index;
3624
3625         return status;
3626 }
3627
3628 /**
3629  * i40e_aq_del_udp_tunnel
3630  * @hw: pointer to the hw struct
3631  * @index: filter index
3632  * @cmd_details: pointer to command details structure or NULL
3633  **/
3634 i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3635                                 struct i40e_asq_cmd_details *cmd_details)
3636 {
3637         struct i40e_aq_desc desc;
3638         struct i40e_aqc_remove_udp_tunnel *cmd =
3639                 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3640         i40e_status status;
3641
3642         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3643
3644         cmd->index = index;
3645
3646         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3647
3648         return status;
3649 }
3650
3651 /**
3652  * i40e_aq_delete_element - Delete switch element
3653  * @hw: pointer to the hw struct
3654  * @seid: the SEID to delete from the switch
3655  * @cmd_details: pointer to command details structure or NULL
3656  *
3657  * This deletes a switch element from the switch.
3658  **/
3659 i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3660                                 struct i40e_asq_cmd_details *cmd_details)
3661 {
3662         struct i40e_aq_desc desc;
3663         struct i40e_aqc_switch_seid *cmd =
3664                 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3665         i40e_status status;
3666
3667         if (seid == 0)
3668                 return I40E_ERR_PARAM;
3669
3670         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3671
3672         cmd->seid = cpu_to_le16(seid);
3673
3674         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3675
3676         return status;
3677 }
3678
3679 /**
3680  * i40e_aq_dcb_updated - DCB Updated Command
3681  * @hw: pointer to the hw struct
3682  * @cmd_details: pointer to command details structure or NULL
3683  *
3684  * EMP will return when the shared RPB settings have been
3685  * recomputed and modified. The retval field in the descriptor
3686  * will be set to 0 when RPB is modified.
3687  **/
3688 i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3689                                 struct i40e_asq_cmd_details *cmd_details)
3690 {
3691         struct i40e_aq_desc desc;
3692         i40e_status status;
3693
3694         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3695
3696         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3697
3698         return status;
3699 }
3700
3701 /**
3702  * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
3703  * @hw: pointer to the hw struct
3704  * @seid: seid for the physical port/switching component/vsi
3705  * @buff: Indirect buffer to hold data parameters and response
3706  * @buff_size: Indirect buffer size
3707  * @opcode: Tx scheduler AQ command opcode
3708  * @cmd_details: pointer to command details structure or NULL
3709  *
3710  * Generic command handler for Tx scheduler AQ commands
3711  **/
3712 static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3713                                 void *buff, u16 buff_size,
3714                                  enum i40e_admin_queue_opc opcode,
3715                                 struct i40e_asq_cmd_details *cmd_details)
3716 {
3717         struct i40e_aq_desc desc;
3718         struct i40e_aqc_tx_sched_ind *cmd =
3719                 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3720         i40e_status status;
3721         bool cmd_param_flag = false;
3722
3723         switch (opcode) {
3724         case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3725         case i40e_aqc_opc_configure_vsi_tc_bw:
3726         case i40e_aqc_opc_enable_switching_comp_ets:
3727         case i40e_aqc_opc_modify_switching_comp_ets:
3728         case i40e_aqc_opc_disable_switching_comp_ets:
3729         case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3730         case i40e_aqc_opc_configure_switching_comp_bw_config:
3731                 cmd_param_flag = true;
3732                 break;
3733         case i40e_aqc_opc_query_vsi_bw_config:
3734         case i40e_aqc_opc_query_vsi_ets_sla_config:
3735         case i40e_aqc_opc_query_switching_comp_ets_config:
3736         case i40e_aqc_opc_query_port_ets_config:
3737         case i40e_aqc_opc_query_switching_comp_bw_config:
3738                 cmd_param_flag = false;
3739                 break;
3740         default:
3741                 return I40E_ERR_PARAM;
3742         }
3743
3744         i40e_fill_default_direct_cmd_desc(&desc, opcode);
3745
3746         /* Indirect command */
3747         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3748         if (cmd_param_flag)
3749                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3750         if (buff_size > I40E_AQ_LARGE_BUF)
3751                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3752
3753         desc.datalen = cpu_to_le16(buff_size);
3754
3755         cmd->vsi_seid = cpu_to_le16(seid);
3756
3757         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3758
3759         return status;
3760 }
3761
3762 /**
3763  * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit
3764  * @hw: pointer to the hw struct
3765  * @seid: VSI seid
3766  * @credit: BW limit credits (0 = disabled)
3767  * @max_credit: Max BW limit credits
3768  * @cmd_details: pointer to command details structure or NULL
3769  **/
3770 i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3771                                 u16 seid, u16 credit, u8 max_credit,
3772                                 struct i40e_asq_cmd_details *cmd_details)
3773 {
3774         struct i40e_aq_desc desc;
3775         struct i40e_aqc_configure_vsi_bw_limit *cmd =
3776                 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3777         i40e_status status;
3778
3779         i40e_fill_default_direct_cmd_desc(&desc,
3780                                           i40e_aqc_opc_configure_vsi_bw_limit);
3781
3782         cmd->vsi_seid = cpu_to_le16(seid);
3783         cmd->credit = cpu_to_le16(credit);
3784         cmd->max_credit = max_credit;
3785
3786         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3787
3788         return status;
3789 }
3790
3791 /**
3792  * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
3793  * @hw: pointer to the hw struct
3794  * @seid: VSI seid
3795  * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
3796  * @cmd_details: pointer to command details structure or NULL
3797  **/
3798 i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3799                         u16 seid,
3800                         struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3801                         struct i40e_asq_cmd_details *cmd_details)
3802 {
3803         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3804                                     i40e_aqc_opc_configure_vsi_tc_bw,
3805                                     cmd_details);
3806 }
3807
3808 /**
3809  * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
3810  * @hw: pointer to the hw struct
3811  * @seid: seid of the switching component connected to Physical Port
3812  * @ets_data: Buffer holding ETS parameters
3813  * @cmd_details: pointer to command details structure or NULL
3814  **/
3815 i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3816                 u16 seid,
3817                 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3818                 enum i40e_admin_queue_opc opcode,
3819                 struct i40e_asq_cmd_details *cmd_details)
3820 {
3821         return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3822                                     sizeof(*ets_data), opcode, cmd_details);
3823 }
3824
3825 /**
3826  * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
3827  * @hw: pointer to the hw struct
3828  * @seid: seid of the switching component
3829  * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
3830  * @cmd_details: pointer to command details structure or NULL
3831  **/
3832 i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3833         u16 seid,
3834         struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3835         struct i40e_asq_cmd_details *cmd_details)
3836 {
3837         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3838                             i40e_aqc_opc_configure_switching_comp_bw_config,
3839                             cmd_details);
3840 }
3841
3842 /**
3843  * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
3844  * @hw: pointer to the hw struct
3845  * @seid: seid of the VSI
3846  * @bw_data: Buffer to hold VSI BW configuration
3847  * @cmd_details: pointer to command details structure or NULL
3848  **/
3849 i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3850                         u16 seid,
3851                         struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3852                         struct i40e_asq_cmd_details *cmd_details)
3853 {
3854         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3855                                     i40e_aqc_opc_query_vsi_bw_config,
3856                                     cmd_details);
3857 }
3858
3859 /**
3860  * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
3861  * @hw: pointer to the hw struct
3862  * @seid: seid of the VSI
3863  * @bw_data: Buffer to hold VSI BW configuration per TC
3864  * @cmd_details: pointer to command details structure or NULL
3865  **/
3866 i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3867                         u16 seid,
3868                         struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3869                         struct i40e_asq_cmd_details *cmd_details)
3870 {
3871         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3872                                     i40e_aqc_opc_query_vsi_ets_sla_config,
3873                                     cmd_details);
3874 }
3875
3876 /**
3877  * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
3878  * @hw: pointer to the hw struct
3879  * @seid: seid of the switching component
3880  * @bw_data: Buffer to hold switching component's per TC BW config
3881  * @cmd_details: pointer to command details structure or NULL
3882  **/
3883 i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3884                 u16 seid,
3885                 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3886                 struct i40e_asq_cmd_details *cmd_details)
3887 {
3888         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3889                                    i40e_aqc_opc_query_switching_comp_ets_config,
3890                                    cmd_details);
3891 }
3892
3893 /**
3894  * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
3895  * @hw: pointer to the hw struct
3896  * @seid: seid of the VSI or switching component connected to Physical Port
3897  * @bw_data: Buffer to hold current ETS configuration for the Physical Port
3898  * @cmd_details: pointer to command details structure or NULL
3899  **/
3900 i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3901                         u16 seid,
3902                         struct i40e_aqc_query_port_ets_config_resp *bw_data,
3903                         struct i40e_asq_cmd_details *cmd_details)
3904 {
3905         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3906                                     i40e_aqc_opc_query_port_ets_config,
3907                                     cmd_details);
3908 }
3909
3910 /**
3911  * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
3912  * @hw: pointer to the hw struct
3913  * @seid: seid of the switching component
3914  * @bw_data: Buffer to hold switching component's BW configuration
3915  * @cmd_details: pointer to command details structure or NULL
3916  **/
3917 i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3918                 u16 seid,
3919                 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3920                 struct i40e_asq_cmd_details *cmd_details)
3921 {
3922         return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3923                                     i40e_aqc_opc_query_switching_comp_bw_config,
3924                                     cmd_details);
3925 }
3926
3927 /**
3928  * i40e_validate_filter_settings
3929  * @hw: pointer to the hardware structure
3930  * @settings: Filter control settings
3931  *
3932  * Check and validate the filter control settings passed.
3933  * The function checks for the valid filter/context sizes being
3934  * passed for FCoE and PE.
3935  *
3936  * Returns 0 if the values passed are valid and within
3937  * range else returns an error.
3938  **/
3939 static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3940                                 struct i40e_filter_control_settings *settings)
3941 {
3942         u32 fcoe_cntx_size, fcoe_filt_size;
3943         u32 pe_cntx_size, pe_filt_size;
3944         u32 fcoe_fmax;
3945         u32 val;
3946
3947         /* Validate FCoE settings passed */
3948         switch (settings->fcoe_filt_num) {
3949         case I40E_HASH_FILTER_SIZE_1K:
3950         case I40E_HASH_FILTER_SIZE_2K:
3951         case I40E_HASH_FILTER_SIZE_4K:
3952         case I40E_HASH_FILTER_SIZE_8K:
3953         case I40E_HASH_FILTER_SIZE_16K:
3954         case I40E_HASH_FILTER_SIZE_32K:
3955                 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3956                 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3957                 break;
3958         default:
3959                 return I40E_ERR_PARAM;
3960         }
3961
3962         switch (settings->fcoe_cntx_num) {
3963         case I40E_DMA_CNTX_SIZE_512:
3964         case I40E_DMA_CNTX_SIZE_1K:
3965         case I40E_DMA_CNTX_SIZE_2K:
3966         case I40E_DMA_CNTX_SIZE_4K:
3967                 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3968                 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3969                 break;
3970         default:
3971                 return I40E_ERR_PARAM;
3972         }
3973
3974         /* Validate PE settings passed */
3975         switch (settings->pe_filt_num) {
3976         case I40E_HASH_FILTER_SIZE_1K:
3977         case I40E_HASH_FILTER_SIZE_2K:
3978         case I40E_HASH_FILTER_SIZE_4K:
3979         case I40E_HASH_FILTER_SIZE_8K:
3980         case I40E_HASH_FILTER_SIZE_16K:
3981         case I40E_HASH_FILTER_SIZE_32K:
3982         case I40E_HASH_FILTER_SIZE_64K:
3983         case I40E_HASH_FILTER_SIZE_128K:
3984         case I40E_HASH_FILTER_SIZE_256K:
3985         case I40E_HASH_FILTER_SIZE_512K:
3986         case I40E_HASH_FILTER_SIZE_1M:
3987                 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3988                 pe_filt_size <<= (u32)settings->pe_filt_num;
3989                 break;
3990         default:
3991                 return I40E_ERR_PARAM;
3992         }
3993
3994         switch (settings->pe_cntx_num) {
3995         case I40E_DMA_CNTX_SIZE_512:
3996         case I40E_DMA_CNTX_SIZE_1K:
3997         case I40E_DMA_CNTX_SIZE_2K:
3998         case I40E_DMA_CNTX_SIZE_4K:
3999         case I40E_DMA_CNTX_SIZE_8K:
4000         case I40E_DMA_CNTX_SIZE_16K:
4001         case I40E_DMA_CNTX_SIZE_32K:
4002         case I40E_DMA_CNTX_SIZE_64K:
4003         case I40E_DMA_CNTX_SIZE_128K:
4004         case I40E_DMA_CNTX_SIZE_256K:
4005                 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4006                 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4007                 break;
4008         default:
4009                 return I40E_ERR_PARAM;
4010         }
4011
4012         /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
4013         val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4014         fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4015                      >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4016         if (fcoe_filt_size + fcoe_cntx_size >  fcoe_fmax)
4017                 return I40E_ERR_INVALID_SIZE;
4018
4019         return 0;
4020 }
4021
4022 /**
4023  * i40e_set_filter_control
4024  * @hw: pointer to the hardware structure
4025  * @settings: Filter control settings
4026  *
4027  * Set the Queue Filters for PE/FCoE and enable filters required
4028  * for a single PF. It is expected that these settings are programmed
4029  * at the driver initialization time.
4030  **/
4031 i40e_status i40e_set_filter_control(struct i40e_hw *hw,
4032                                 struct i40e_filter_control_settings *settings)
4033 {
4034         i40e_status ret = 0;
4035         u32 hash_lut_size = 0;
4036         u32 val;
4037
4038         if (!settings)
4039                 return I40E_ERR_PARAM;
4040
4041         /* Validate the input settings */
4042         ret = i40e_validate_filter_settings(hw, settings);
4043         if (ret)
4044                 return ret;
4045
4046         /* Read the PF Queue Filter control register */
4047         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
4048
4049         /* Program required PE hash buckets for the PF */
4050         val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4051         val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4052                 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4053         /* Program required PE contexts for the PF */
4054         val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4055         val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4056                 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4057
4058         /* Program required FCoE hash buckets for the PF */
4059         val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4060         val |= ((u32)settings->fcoe_filt_num <<
4061                         I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4062                 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4063         /* Program required FCoE DDP contexts for the PF */
4064         val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4065         val |= ((u32)settings->fcoe_cntx_num <<
4066                         I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4067                 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4068
4069         /* Program Hash LUT size for the PF */
4070         val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4071         if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4072                 hash_lut_size = 1;
4073         val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4074                 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4075
4076         /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
4077         if (settings->enable_fdir)
4078                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4079         if (settings->enable_ethtype)
4080                 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4081         if (settings->enable_macvlan)
4082                 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4083
4084         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
4085
4086         return 0;
4087 }
4088
4089 /**
4090  * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
4091  * @hw: pointer to the hw struct
4092  * @mac_addr: MAC address to use in the filter
4093  * @ethtype: Ethertype to use in the filter
4094  * @flags: Flags that needs to be applied to the filter
4095  * @vsi_seid: seid of the control VSI
4096  * @queue: VSI queue number to send the packet to
4097  * @is_add: Add control packet filter if True else remove
4098  * @stats: Structure to hold information on control filter counts
4099  * @cmd_details: pointer to command details structure or NULL
4100  *
4101  * This command will Add or Remove control packet filter for a control VSI.
4102  * In return it will update the total number of perfect filter count in
4103  * the stats member.
4104  **/
4105 i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4106                                 u8 *mac_addr, u16 ethtype, u16 flags,
4107                                 u16 vsi_seid, u16 queue, bool is_add,
4108                                 struct i40e_control_filter_stats *stats,
4109                                 struct i40e_asq_cmd_details *cmd_details)
4110 {
4111         struct i40e_aq_desc desc;
4112         struct i40e_aqc_add_remove_control_packet_filter *cmd =
4113                 (struct i40e_aqc_add_remove_control_packet_filter *)
4114                 &desc.params.raw;
4115         struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4116                 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4117                 &desc.params.raw;
4118         i40e_status status;
4119
4120         if (vsi_seid == 0)
4121                 return I40E_ERR_PARAM;
4122
4123         if (is_add) {
4124                 i40e_fill_default_direct_cmd_desc(&desc,
4125                                 i40e_aqc_opc_add_control_packet_filter);
4126                 cmd->queue = cpu_to_le16(queue);
4127         } else {
4128                 i40e_fill_default_direct_cmd_desc(&desc,
4129                                 i40e_aqc_opc_remove_control_packet_filter);
4130         }
4131
4132         if (mac_addr)
4133                 ether_addr_copy(cmd->mac, mac_addr);
4134
4135         cmd->etype = cpu_to_le16(ethtype);
4136         cmd->flags = cpu_to_le16(flags);
4137         cmd->seid = cpu_to_le16(vsi_seid);
4138
4139         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4140
4141         if (!status && stats) {
4142                 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4143                 stats->etype_used = le16_to_cpu(resp->etype_used);
4144                 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4145                 stats->etype_free = le16_to_cpu(resp->etype_free);
4146         }
4147
4148         return status;
4149 }
4150
4151 /**
4152  * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control
4153  * @hw: pointer to the hw struct
4154  * @seid: VSI seid to add ethertype filter from
4155  **/
4156 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4157 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4158                                                     u16 seid)
4159 {
4160         u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4161                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4162                    I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4163         u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4164         i40e_status status;
4165
4166         status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4167                                                        seid, 0, true, NULL,
4168                                                        NULL);
4169         if (status)
4170                 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4171 }
4172
4173 /**
4174  * i40e_aq_alternate_read
4175  * @hw: pointer to the hardware structure
4176  * @reg_addr0: address of first dword to be read
4177  * @reg_val0: pointer for data read from 'reg_addr0'
4178  * @reg_addr1: address of second dword to be read
4179  * @reg_val1: pointer for data read from 'reg_addr1'
4180  *
4181  * Read one or two dwords from alternate structure. Fields are indicated
4182  * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer
4183  * is not passed then only register at 'reg_addr0' is read.
4184  *
4185  **/
4186 static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4187                                           u32 reg_addr0, u32 *reg_val0,
4188                                           u32 reg_addr1, u32 *reg_val1)
4189 {
4190         struct i40e_aq_desc desc;
4191         struct i40e_aqc_alternate_write *cmd_resp =
4192                 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4193         i40e_status status;
4194
4195         if (!reg_val0)
4196                 return I40E_ERR_PARAM;
4197
4198         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4199         cmd_resp->address0 = cpu_to_le32(reg_addr0);
4200         cmd_resp->address1 = cpu_to_le32(reg_addr1);
4201
4202         status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4203
4204         if (!status) {
4205                 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4206
4207                 if (reg_val1)
4208                         *reg_val1 = le32_to_cpu(cmd_resp->data1);
4209         }
4210
4211         return status;
4212 }
4213
4214 /**
4215  * i40e_aq_resume_port_tx
4216  * @hw: pointer to the hardware structure
4217  * @cmd_details: pointer to command details structure or NULL
4218  *
4219  * Resume port's Tx traffic
4220  **/
4221 i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4222                                    struct i40e_asq_cmd_details *cmd_details)
4223 {
4224         struct i40e_aq_desc desc;
4225         i40e_status status;
4226
4227         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4228
4229         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4230
4231         return status;
4232 }
4233
4234 /**
4235  * i40e_set_pci_config_data - store PCI bus info
4236  * @hw: pointer to hardware structure
4237  * @link_status: the link status word from PCI config space
4238  *
4239  * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
4240  **/
4241 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4242 {
4243         hw->bus.type = i40e_bus_type_pci_express;
4244
4245         switch (link_status & PCI_EXP_LNKSTA_NLW) {
4246         case PCI_EXP_LNKSTA_NLW_X1:
4247                 hw->bus.width = i40e_bus_width_pcie_x1;
4248                 break;
4249         case PCI_EXP_LNKSTA_NLW_X2:
4250                 hw->bus.width = i40e_bus_width_pcie_x2;
4251                 break;
4252         case PCI_EXP_LNKSTA_NLW_X4:
4253                 hw->bus.width = i40e_bus_width_pcie_x4;
4254                 break;
4255         case PCI_EXP_LNKSTA_NLW_X8:
4256                 hw->bus.width = i40e_bus_width_pcie_x8;
4257                 break;
4258         default:
4259                 hw->bus.width = i40e_bus_width_unknown;
4260                 break;
4261         }
4262
4263         switch (link_status & PCI_EXP_LNKSTA_CLS) {
4264         case PCI_EXP_LNKSTA_CLS_2_5GB:
4265                 hw->bus.speed = i40e_bus_speed_2500;
4266                 break;
4267         case PCI_EXP_LNKSTA_CLS_5_0GB:
4268                 hw->bus.speed = i40e_bus_speed_5000;
4269                 break;
4270         case PCI_EXP_LNKSTA_CLS_8_0GB:
4271                 hw->bus.speed = i40e_bus_speed_8000;
4272                 break;
4273         default:
4274                 hw->bus.speed = i40e_bus_speed_unknown;
4275                 break;
4276         }
4277 }
4278
4279 /**
4280  * i40e_aq_debug_dump
4281  * @hw: pointer to the hardware structure
4282  * @cluster_id: specific cluster to dump
4283  * @table_id: table id within cluster
4284  * @start_index: index of line in the block to read
4285  * @buff_size: dump buffer size
4286  * @buff: dump buffer
4287  * @ret_buff_size: actual buffer size returned
4288  * @ret_next_table: next block to read
4289  * @ret_next_index: next index to read
4290  *
4291  * Dump internal FW/HW data for debug purposes.
4292  *
4293  **/
4294 i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4295                                u8 table_id, u32 start_index, u16 buff_size,
4296                                void *buff, u16 *ret_buff_size,
4297                                u8 *ret_next_table, u32 *ret_next_index,
4298                                struct i40e_asq_cmd_details *cmd_details)
4299 {
4300         struct i40e_aq_desc desc;
4301         struct i40e_aqc_debug_dump_internals *cmd =
4302                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4303         struct i40e_aqc_debug_dump_internals *resp =
4304                 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4305         i40e_status status;
4306
4307         if (buff_size == 0 || !buff)
4308                 return I40E_ERR_PARAM;
4309
4310         i40e_fill_default_direct_cmd_desc(&desc,
4311                                           i40e_aqc_opc_debug_dump_internals);
4312         /* Indirect Command */
4313         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4314         if (buff_size > I40E_AQ_LARGE_BUF)
4315                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4316
4317         cmd->cluster_id = cluster_id;
4318         cmd->table_id = table_id;
4319         cmd->idx = cpu_to_le32(start_index);
4320
4321         desc.datalen = cpu_to_le16(buff_size);
4322
4323         status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4324         if (!status) {
4325                 if (ret_buff_size)
4326                         *ret_buff_size = le16_to_cpu(desc.datalen);
4327                 if (ret_next_table)
4328                         *ret_next_table = resp->table_id;
4329                 if (ret_next_index)
4330                         *ret_next_index = le32_to_cpu(resp->idx);
4331         }
4332
4333         return status;
4334 }
4335
4336 /**
4337  * i40e_read_bw_from_alt_ram
4338  * @hw: pointer to the hardware structure
4339  * @max_bw: pointer for max_bw read
4340  * @min_bw: pointer for min_bw read
4341  * @min_valid: pointer for bool that is true if min_bw is a valid value
4342  * @max_valid: pointer for bool that is true if max_bw is a valid value
4343  *
4344  * Read bw from the alternate ram for the given pf
4345  **/
4346 i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4347                                       u32 *max_bw, u32 *min_bw,
4348                                       bool *min_valid, bool *max_valid)
4349 {
4350         i40e_status status;
4351         u32 max_bw_addr, min_bw_addr;
4352
4353         /* Calculate the address of the min/max bw registers */
4354         max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4355                       I40E_ALT_STRUCT_MAX_BW_OFFSET +
4356                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4357         min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4358                       I40E_ALT_STRUCT_MIN_BW_OFFSET +
4359                       (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4360
4361         /* Read the bandwidths from alt ram */
4362         status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4363                                         min_bw_addr, min_bw);
4364
4365         if (*min_bw & I40E_ALT_BW_VALID_MASK)
4366                 *min_valid = true;
4367         else
4368                 *min_valid = false;
4369
4370         if (*max_bw & I40E_ALT_BW_VALID_MASK)
4371                 *max_valid = true;
4372         else
4373                 *max_valid = false;
4374
4375         return status;
4376 }
4377
4378 /**
4379  * i40e_aq_configure_partition_bw
4380  * @hw: pointer to the hardware structure
4381  * @bw_data: Buffer holding valid pfs and bw limits
4382  * @cmd_details: pointer to command details
4383  *
4384  * Configure partitions guaranteed/max bw
4385  **/
4386 i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4387                         struct i40e_aqc_configure_partition_bw_data *bw_data,
4388                         struct i40e_asq_cmd_details *cmd_details)
4389 {
4390         i40e_status status;
4391         struct i40e_aq_desc desc;
4392         u16 bwd_size = sizeof(*bw_data);
4393
4394         i40e_fill_default_direct_cmd_desc(&desc,
4395                                           i40e_aqc_opc_configure_partition_bw);
4396
4397         /* Indirect command */
4398         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4399         desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4400
4401         if (bwd_size > I40E_AQ_LARGE_BUF)
4402                 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4403
4404         desc.datalen = cpu_to_le16(bwd_size);
4405
4406         status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4407                                        cmd_details);
4408
4409         return status;
4410 }
4411
4412 /**
4413  * i40e_read_phy_register
4414  * @hw: pointer to the HW structure
4415  * @page: registers page number
4416  * @reg: register address in the page
4417  * @phy_adr: PHY address on MDIO interface
4418  * @value: PHY register value
4419  *
4420  * Reads specified PHY register value
4421  **/
4422 i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4423                                    u8 page, u16 reg, u8 phy_addr,
4424                                    u16 *value)
4425 {
4426         i40e_status status = I40E_ERR_TIMEOUT;
4427         u32 command = 0;
4428         u16 retry = 1000;
4429         u8 port_num = hw->func_caps.mdio_port_num;
4430
4431         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4432                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4433                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4434                   (I40E_MDIO_OPCODE_ADDRESS) |
4435                   (I40E_MDIO_STCODE) |
4436                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4437                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4438         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4439         do {
4440                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4441                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4442                         status = 0;
4443                         break;
4444                 }
4445                 usleep_range(10, 20);
4446                 retry--;
4447         } while (retry);
4448
4449         if (status) {
4450                 i40e_debug(hw, I40E_DEBUG_PHY,
4451                            "PHY: Can't write command to external PHY.\n");
4452                 goto phy_read_end;
4453         }
4454
4455         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4456                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4457                   (I40E_MDIO_OPCODE_READ) |
4458                   (I40E_MDIO_STCODE) |
4459                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4460                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4461         status = I40E_ERR_TIMEOUT;
4462         retry = 1000;
4463         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4464         do {
4465                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4466                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4467                         status = 0;
4468                         break;
4469                 }
4470                 usleep_range(10, 20);
4471                 retry--;
4472         } while (retry);
4473
4474         if (!status) {
4475                 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4476                 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4477                          I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4478         } else {
4479                 i40e_debug(hw, I40E_DEBUG_PHY,
4480                            "PHY: Can't read register value from external PHY.\n");
4481         }
4482
4483 phy_read_end:
4484         return status;
4485 }
4486
4487 /**
4488  * i40e_write_phy_register
4489  * @hw: pointer to the HW structure
4490  * @page: registers page number
4491  * @reg: register address in the page
4492  * @phy_adr: PHY address on MDIO interface
4493  * @value: PHY register value
4494  *
4495  * Writes value to specified PHY register
4496  **/
4497 i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4498                                     u8 page, u16 reg, u8 phy_addr,
4499                                     u16 value)
4500 {
4501         i40e_status status = I40E_ERR_TIMEOUT;
4502         u32 command = 0;
4503         u16 retry = 1000;
4504         u8 port_num = hw->func_caps.mdio_port_num;
4505
4506         command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4507                   (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4508                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4509                   (I40E_MDIO_OPCODE_ADDRESS) |
4510                   (I40E_MDIO_STCODE) |
4511                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4512                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4513         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4514         do {
4515                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4516                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4517                         status = 0;
4518                         break;
4519                 }
4520                 usleep_range(10, 20);
4521                 retry--;
4522         } while (retry);
4523         if (status) {
4524                 i40e_debug(hw, I40E_DEBUG_PHY,
4525                            "PHY: Can't write command to external PHY.\n");
4526                 goto phy_write_end;
4527         }
4528
4529         command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4530         wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4531
4532         command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4533                   (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4534                   (I40E_MDIO_OPCODE_WRITE) |
4535                   (I40E_MDIO_STCODE) |
4536                   (I40E_GLGEN_MSCA_MDICMD_MASK) |
4537                   (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4538         status = I40E_ERR_TIMEOUT;
4539         retry = 1000;
4540         wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4541         do {
4542                 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4543                 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4544                         status = 0;
4545                         break;
4546                 }
4547                 usleep_range(10, 20);
4548                 retry--;
4549         } while (retry);
4550
4551 phy_write_end:
4552         return status;
4553 }
4554
4555 /**
4556  * i40e_get_phy_address
4557  * @hw: pointer to the HW structure
4558  * @dev_num: PHY port num that address we want
4559  * @phy_addr: Returned PHY address
4560  *
4561  * Gets PHY address for current port
4562  **/
4563 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4564 {
4565         u8 port_num = hw->func_caps.mdio_port_num;
4566         u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4567
4568         return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4569 }
4570
4571 /**
4572  * i40e_blink_phy_led
4573  * @hw: pointer to the HW structure
4574  * @time: time how long led will blinks in secs
4575  * @interval: gap between LED on and off in msecs
4576  *
4577  * Blinks PHY link LED
4578  **/
4579 i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4580                                     u32 time, u32 interval)
4581 {
4582         i40e_status status = 0;
4583         u32 i;
4584         u16 led_ctl;
4585         u16 gpio_led_port;
4586         u16 led_reg;
4587         u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4588         u8 phy_addr = 0;
4589         u8 port_num;
4590
4591         i = rd32(hw, I40E_PFGEN_PORTNUM);
4592         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4593         phy_addr = i40e_get_phy_address(hw, port_num);
4594
4595         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4596              led_addr++) {
4597                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4598                                                 led_addr, phy_addr, &led_reg);
4599                 if (status)
4600                         goto phy_blinking_end;
4601                 led_ctl = led_reg;
4602                 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4603                         led_reg = 0;
4604                         status = i40e_write_phy_register(hw,
4605                                                          I40E_PHY_COM_REG_PAGE,
4606                                                          led_addr, phy_addr,
4607                                                          led_reg);
4608                         if (status)
4609                                 goto phy_blinking_end;
4610                         break;
4611                 }
4612         }
4613
4614         if (time > 0 && interval > 0) {
4615                 for (i = 0; i < time * 1000; i += interval) {
4616                         status = i40e_read_phy_register(hw,
4617                                                         I40E_PHY_COM_REG_PAGE,
4618                                                         led_addr, phy_addr,
4619                                                         &led_reg);
4620                         if (status)
4621                                 goto restore_config;
4622                         if (led_reg & I40E_PHY_LED_MANUAL_ON)
4623                                 led_reg = 0;
4624                         else
4625                                 led_reg = I40E_PHY_LED_MANUAL_ON;
4626                         status = i40e_write_phy_register(hw,
4627                                                          I40E_PHY_COM_REG_PAGE,
4628                                                          led_addr, phy_addr,
4629                                                          led_reg);
4630                         if (status)
4631                                 goto restore_config;
4632                         msleep(interval);
4633                 }
4634         }
4635
4636 restore_config:
4637         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4638                                          phy_addr, led_ctl);
4639
4640 phy_blinking_end:
4641         return status;
4642 }
4643
4644 /**
4645  * i40e_led_get_phy - return current on/off mode
4646  * @hw: pointer to the hw struct
4647  * @led_addr: address of led register to use
4648  * @val: original value of register to use
4649  *
4650  **/
4651 i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4652                              u16 *val)
4653 {
4654         i40e_status status = 0;
4655         u16 gpio_led_port;
4656         u8 phy_addr = 0;
4657         u16 reg_val;
4658         u16 temp_addr;
4659         u8 port_num;
4660         u32 i;
4661
4662         temp_addr = I40E_PHY_LED_PROV_REG_1;
4663         i = rd32(hw, I40E_PFGEN_PORTNUM);
4664         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4665         phy_addr = i40e_get_phy_address(hw, port_num);
4666
4667         for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4668              temp_addr++) {
4669                 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4670                                                 temp_addr, phy_addr, &reg_val);
4671                 if (status)
4672                         return status;
4673                 *val = reg_val;
4674                 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4675                         *led_addr = temp_addr;
4676                         break;
4677                 }
4678         }
4679         return status;
4680 }
4681
4682 /**
4683  * i40e_led_set_phy
4684  * @hw: pointer to the HW structure
4685  * @on: true or false
4686  * @mode: original val plus bit for set or ignore
4687  * Set led's on or off when controlled by the PHY
4688  *
4689  **/
4690 i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
4691                              u16 led_addr, u32 mode)
4692 {
4693         i40e_status status = 0;
4694         u16 led_ctl = 0;
4695         u16 led_reg = 0;
4696         u8 phy_addr = 0;
4697         u8 port_num;
4698         u32 i;
4699
4700         i = rd32(hw, I40E_PFGEN_PORTNUM);
4701         port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4702         phy_addr = i40e_get_phy_address(hw, port_num);
4703
4704         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4705                                         phy_addr, &led_reg);
4706         if (status)
4707                 return status;
4708         led_ctl = led_reg;
4709         if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4710                 led_reg = 0;
4711                 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4712                                                  led_addr, phy_addr, led_reg);
4713                 if (status)
4714                         return status;
4715         }
4716         status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4717                                         led_addr, phy_addr, &led_reg);
4718         if (status)
4719                 goto restore_config;
4720         if (on)
4721                 led_reg = I40E_PHY_LED_MANUAL_ON;
4722         else
4723                 led_reg = 0;
4724         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4725                                          led_addr, phy_addr, led_reg);
4726         if (status)
4727                 goto restore_config;
4728         if (mode & I40E_PHY_LED_MODE_ORIG) {
4729                 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4730                 status = i40e_write_phy_register(hw,
4731                                                  I40E_PHY_COM_REG_PAGE,
4732                                                  led_addr, phy_addr, led_ctl);
4733         }
4734         return status;
4735 restore_config:
4736         status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4737                                          phy_addr, led_ctl);
4738         return status;
4739 }
4740
4741 /**
4742  * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register
4743  * @hw: pointer to the hw struct
4744  * @reg_addr: register address
4745  * @reg_val: ptr to register value
4746  * @cmd_details: pointer to command details structure or NULL
4747  *
4748  * Use the firmware to read the Rx control register,
4749  * especially useful if the Rx unit is under heavy pressure
4750  **/
4751 i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4752                                 u32 reg_addr, u32 *reg_val,
4753                                 struct i40e_asq_cmd_details *cmd_details)
4754 {
4755         struct i40e_aq_desc desc;
4756         struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4757                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4758         i40e_status status;
4759
4760         if (!reg_val)
4761                 return I40E_ERR_PARAM;
4762
4763         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4764
4765         cmd_resp->address = cpu_to_le32(reg_addr);
4766
4767         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4768
4769         if (status == 0)
4770                 *reg_val = le32_to_cpu(cmd_resp->value);
4771
4772         return status;
4773 }
4774
4775 /**
4776  * i40e_read_rx_ctl - read from an Rx control register
4777  * @hw: pointer to the hw struct
4778  * @reg_addr: register address
4779  **/
4780 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4781 {
4782         i40e_status status = 0;
4783         bool use_register;
4784         int retry = 5;
4785         u32 val = 0;
4786
4787         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4788         if (!use_register) {
4789 do_retry:
4790                 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4791                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4792                         usleep_range(1000, 2000);
4793                         retry--;
4794                         goto do_retry;
4795                 }
4796         }
4797
4798         /* if the AQ access failed, try the old-fashioned way */
4799         if (status || use_register)
4800                 val = rd32(hw, reg_addr);
4801
4802         return val;
4803 }
4804
4805 /**
4806  * i40e_aq_rx_ctl_write_register
4807  * @hw: pointer to the hw struct
4808  * @reg_addr: register address
4809  * @reg_val: register value
4810  * @cmd_details: pointer to command details structure or NULL
4811  *
4812  * Use the firmware to write to an Rx control register,
4813  * especially useful if the Rx unit is under heavy pressure
4814  **/
4815 i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
4816                                 u32 reg_addr, u32 reg_val,
4817                                 struct i40e_asq_cmd_details *cmd_details)
4818 {
4819         struct i40e_aq_desc desc;
4820         struct i40e_aqc_rx_ctl_reg_read_write *cmd =
4821                 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4822         i40e_status status;
4823
4824         i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
4825
4826         cmd->address = cpu_to_le32(reg_addr);
4827         cmd->value = cpu_to_le32(reg_val);
4828
4829         status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4830
4831         return status;
4832 }
4833
4834 /**
4835  * i40e_write_rx_ctl - write to an Rx control register
4836  * @hw: pointer to the hw struct
4837  * @reg_addr: register address
4838  * @reg_val: register value
4839  **/
4840 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
4841 {
4842         i40e_status status = 0;
4843         bool use_register;
4844         int retry = 5;
4845
4846         use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4847         if (!use_register) {
4848 do_retry:
4849                 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
4850                                                        reg_val, NULL);
4851                 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4852                         usleep_range(1000, 2000);
4853                         retry--;
4854                         goto do_retry;
4855                 }
4856         }
4857
4858         /* if the AQ access failed, try the old-fashioned way */
4859         if (status || use_register)
4860                 wr32(hw, reg_addr, reg_val);
4861 }