1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/types.h>
10 #include <linux/avf/virtchnl.h>
11 #include <linux/net/intel/i40e_client.h>
12 #include <net/devlink.h>
13 #include <net/pkt_cls.h>
14 #include <net/udp_tunnel.h>
16 #include "i40e_debug.h"
17 #include "i40e_devlink.h"
19 #include "i40e_prototype.h"
20 #include "i40e_register.h"
21 #include "i40e_txrx.h"
23 /* Useful i40e defaults */
24 #define I40E_MAX_VEB 16
26 #define I40E_MAX_NUM_DESCRIPTORS 4096
27 #define I40E_MAX_NUM_DESCRIPTORS_XL710 8160
28 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
29 #define I40E_DEFAULT_NUM_DESCRIPTORS 512
30 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32
31 #define I40E_MIN_NUM_DESCRIPTORS 64
32 #define I40E_MIN_MSIX 2
33 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
34 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
36 #define i40e_default_queues_per_vmdq(pf) \
37 (test_bit(I40E_HW_CAP_RSS_AQ, (pf)->hw.caps) ? 4 : 1)
38 #define I40E_DEFAULT_QUEUES_PER_VF 4
39 #define I40E_MAX_VF_QUEUES 16
40 #define i40e_pf_get_max_q_per_tc(pf) \
41 (test_bit(I40E_HW_CAP_128_QP_RSS, (pf)->hw.caps) ? 128 : 64)
42 #define I40E_FDIR_RING_COUNT 32
43 #define I40E_MAX_AQ_BUF_SIZE 4096
44 #define I40E_AQ_LEN 256
45 #define I40E_MIN_ARQ_LEN 1
46 #define I40E_MIN_ASQ_LEN 2
47 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
48 #define I40E_MAX_USER_PRIORITY 8
49 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
50 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10
51 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
53 #define I40E_PHY_DEBUG_ALL \
54 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
55 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
57 #define I40E_OEM_EETRACK_ID 0xffffffff
58 #define I40E_NVM_VERSION_LO_MASK GENMASK(7, 0)
59 #define I40E_NVM_VERSION_HI_MASK GENMASK(15, 12)
60 #define I40E_OEM_VER_BUILD_MASK GENMASK(23, 8)
61 #define I40E_OEM_VER_PATCH_MASK GENMASK(7, 0)
62 #define I40E_OEM_VER_MASK GENMASK(31, 24)
63 #define I40E_OEM_GEN_MASK GENMASK(31, 24)
64 #define I40E_OEM_SNAP_MASK GENMASK(23, 16)
65 #define I40E_OEM_RELEASE_MASK GENMASK(15, 0)
67 #define I40E_RX_DESC(R, i) \
68 (&(((union i40e_rx_desc *)((R)->desc))[i]))
69 #define I40E_TX_DESC(R, i) \
70 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
71 #define I40E_TX_CTXTDESC(R, i) \
72 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
73 #define I40E_TX_FDIRDESC(R, i) \
74 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
76 /* BW rate limiting */
77 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
78 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
79 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */
81 /* driver state flags */
88 __I40E_ADMINQ_EVENT_PENDING,
89 __I40E_MDD_EVENT_PENDING,
90 __I40E_VFLR_EVENT_PENDING,
91 __I40E_RESET_RECOVERY_PENDING,
92 __I40E_TIMEOUT_RECOVERY_PENDING,
93 __I40E_MISC_IRQ_REQUESTED,
94 __I40E_RESET_INTR_RECEIVED,
95 __I40E_REINIT_REQUESTED,
96 __I40E_PF_RESET_REQUESTED,
97 __I40E_PF_RESET_AND_REBUILD_REQUESTED,
98 __I40E_CORE_RESET_REQUESTED,
99 __I40E_GLOBAL_RESET_REQUESTED,
100 __I40E_EMP_RESET_INTR_RECEIVED,
102 __I40E_PTP_TX_IN_PROGRESS,
104 __I40E_DOWN_REQUESTED,
105 __I40E_FD_FLUSH_REQUESTED,
106 __I40E_FD_ATR_AUTO_DISABLED,
107 __I40E_FD_SB_AUTO_DISABLED,
109 __I40E_PORT_SUSPENDED,
111 __I40E_MACVLAN_SYNC_PENDING,
112 __I40E_TEMP_LINK_POLLING,
113 __I40E_CLIENT_SERVICE_REQUESTED,
114 __I40E_CLIENT_L2_CHANGE,
116 __I40E_VIRTCHNL_OP_PENDING,
117 __I40E_RECOVERY_MODE,
118 __I40E_VF_RESETS_DISABLED, /* disable resets during i40e_remove */
120 __I40E_VFS_RELEASING,
121 /* This must be last as it determines the size of the BITMAP */
125 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
126 #define I40E_PF_RESET_AND_REBUILD_FLAG \
127 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)
129 /* VSI state flags */
130 enum i40e_vsi_state {
132 __I40E_VSI_NEEDS_RESTART,
133 __I40E_VSI_SYNCING_FILTERS,
134 __I40E_VSI_OVERFLOW_PROMISC,
135 __I40E_VSI_REINIT_REQUESTED,
136 __I40E_VSI_DOWN_REQUESTED,
137 __I40E_VSI_RELEASING,
138 /* This must be last as it determines the size of the BITMAP */
139 __I40E_VSI_STATE_SIZE__,
148 I40E_FLAG_DCB_CAPABLE,
151 I40E_FLAG_FD_ATR_ENA,
153 I40E_FLAG_HW_ATR_EVICT_ENA,
154 I40E_FLAG_VEB_MODE_ENA,
155 I40E_FLAG_VEB_STATS_ENA,
156 I40E_FLAG_LINK_POLLING_ENA,
157 I40E_FLAG_TRUE_PROMISC_ENA,
158 I40E_FLAG_LEGACY_RX_ENA,
161 I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA,
162 I40E_FLAG_SOURCE_PRUNING_DIS,
163 I40E_FLAG_TC_MQPRIO_ENA,
164 I40E_FLAG_FD_SB_INACTIVE,
165 I40E_FLAG_FD_SB_TO_CLOUD_FILTER,
166 I40E_FLAG_FW_LLDP_DIS,
168 I40E_FLAG_BASE_R_FEC,
169 /* TOTAL_PORT_SHUTDOWN_ENA
170 * Allows to physically disable the link on the NIC's port.
171 * If enabled, (after link down request from the OS)
172 * no link, traffic or led activity is possible on that port.
174 * If I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA is set, the
175 * I40E_FLAG_LINK_DOWN_ON_CLOSE_ENA must be explicitly forced
176 * to true and cannot be disabled by system admin at that time.
177 * The functionalities are exclusive in terms of configuration, but
178 * they also have similar behavior (allowing to disable physical
179 * link of the port), with following differences:
180 * - LINK_DOWN_ON_CLOSE_ENA is configurable at host OS run-time and
181 * is supported by whole family of 7xx Intel Ethernet Controllers
182 * - TOTAL_PORT_SHUTDOWN_ENA may be enabled only before OS loads
183 * (in BIOS) only if motherboard's BIOS and NIC's FW has support of it
184 * - when LINK_DOWN_ON_CLOSE_ENABLED is used, the link is being brought
185 * down by sending phy_type=0 to NIC's FW
186 * - when TOTAL_PORT_SHUTDOWN_ENA is used, phy_type is not altered,
187 * instead the link is being brought down by clearing
188 * bit (I40E_AQ_PHY_ENABLE_LINK) in abilities field of
189 * i40e_aq_set_phy_config structure
191 I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENA,
192 I40E_FLAG_VF_VLAN_PRUNING_ENA,
193 I40E_PF_FLAGS_NBITS, /* must be last */
196 enum i40e_interrupt_policy {
197 I40E_INTERRUPT_BEST_CASE,
198 I40E_INTERRUPT_MEDIUM,
199 I40E_INTERRUPT_LOWEST
202 struct i40e_lump_tracking {
205 #define I40E_PILE_VALID_BIT 0x8000
206 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
209 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20
210 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
211 #define I40E_FDIR_BUFFER_FULL_MARGIN 10
212 #define I40E_FDIR_BUFFER_HEAD_ROOM 32
213 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
215 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
216 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
217 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
219 enum i40e_fd_stat_idx {
222 I40E_FD_STAT_ATR_TUNNEL,
223 I40E_FD_STAT_PF_COUNT
225 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
226 #define I40E_FD_ATR_STAT_IDX(pf_id) \
227 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
228 #define I40E_FD_SB_STAT_IDX(pf_id) \
229 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
230 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
231 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
233 /* The following structure contains the data parsed from the user-defined
234 * field of the ethtool_rx_flow_spec structure.
236 struct i40e_rx_flow_userdef {
242 struct i40e_fdir_filter {
243 struct hlist_node fdir_node;
244 /* filter ipnut set */
247 /* TX packet view of src and dst */
258 /* Flexible data to match within the packet payload */
274 #define I40E_CLOUD_FIELD_OMAC BIT(0)
275 #define I40E_CLOUD_FIELD_IMAC BIT(1)
276 #define I40E_CLOUD_FIELD_IVLAN BIT(2)
277 #define I40E_CLOUD_FIELD_TEN_ID BIT(3)
278 #define I40E_CLOUD_FIELD_IIP BIT(4)
280 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
281 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
282 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
283 I40E_CLOUD_FIELD_IVLAN)
284 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
285 I40E_CLOUD_FIELD_TEN_ID)
286 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
287 I40E_CLOUD_FIELD_IMAC | \
288 I40E_CLOUD_FIELD_TEN_ID)
289 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
290 I40E_CLOUD_FIELD_IVLAN | \
291 I40E_CLOUD_FIELD_TEN_ID)
292 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
294 struct i40e_cloud_filter {
295 struct hlist_node cloud_node;
296 unsigned long cookie;
297 /* cloud filter input set follows */
298 u8 dst_mac[ETH_ALEN];
299 u8 src_mac[ETH_ALEN];
301 u16 seid; /* filter control */
307 struct in_addr dst_ip;
308 struct in_addr src_ip;
311 struct in6_addr dst_ip6;
312 struct in6_addr src_ip6;
315 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32
316 #define src_ipv6 ip.v6.src_ip6.s6_addr32
317 #define dst_ipv4 ip.v4.dst_ip.s_addr
318 #define src_ipv4 ip.v4.src_ip.s_addr
319 u16 n_proto; /* Ethernet Protocol */
320 u8 ip_proto; /* IPPROTO value */
322 #define I40E_CLOUD_TNL_TYPE_NONE 0xff
326 #define I40E_DCB_PRIO_TYPE_STRICT 0
327 #define I40E_DCB_PRIO_TYPE_ETS 1
328 #define I40E_DCB_STRICT_PRIO_CREDITS 127
329 /* DCB per TC information data structure */
330 struct i40e_tc_info {
331 u16 qoffset; /* Queue offset from base queue */
332 u16 qcount; /* Total Queues */
333 u8 netdev_tc; /* Netdev TC index if netdev associated */
336 /* TC configuration data structure */
337 struct i40e_tc_configuration {
338 u8 numtc; /* Total number of enabled TCs */
339 u8 enabled_tc; /* TC map */
340 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
343 #define I40E_UDP_PORT_INDEX_UNUSED 255
344 struct i40e_udp_port_config {
345 /* AdminQ command interface expects port number in Host byte order */
351 /* macros related to FLX_PIT */
352 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
353 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
354 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
355 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
356 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
357 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
358 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
359 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
360 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
361 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
362 I40E_FLEX_SET_FSIZE(fsize) | \
363 I40E_FLEX_SET_SRC_WORD(src))
366 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F
368 /* macros related to GLQF_ORT */
369 #define I40E_ORT_SET_IDX(idx) (((idx) << \
370 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
371 I40E_GLQF_ORT_PIT_INDX_MASK)
373 #define I40E_ORT_SET_COUNT(count) (((count) << \
374 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
375 I40E_GLQF_ORT_FIELD_CNT_MASK)
377 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
378 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
379 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
381 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
382 I40E_ORT_SET_COUNT(count) | \
383 I40E_ORT_SET_PAYLOAD(payload))
385 #define I40E_L3_GLQF_ORT_IDX 34
386 #define I40E_L4_GLQF_ORT_IDX 35
388 /* Flex PIT register index */
389 #define I40E_FLEX_PIT_IDX_START_L3 3
390 #define I40E_FLEX_PIT_IDX_START_L4 6
392 #define I40E_FLEX_PIT_TABLE_SIZE 3
394 #define I40E_FLEX_DEST_UNUSED 63
396 #define I40E_FLEX_INDEX_ENTRIES 8
398 /* Flex MASK to disable all flexible entries */
399 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
400 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
401 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
402 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
404 #define I40E_QINT_TQCTL_VAL(qp, vector, nextq_type) \
405 (I40E_QINT_TQCTL_CAUSE_ENA_MASK | \
406 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | \
407 ((vector) << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | \
408 ((qp) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | \
409 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT))
411 #define I40E_QINT_RQCTL_VAL(qp, vector, nextq_type) \
412 (I40E_QINT_RQCTL_CAUSE_ENA_MASK | \
413 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | \
414 ((vector) << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | \
415 ((qp) << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | \
416 (I40E_QUEUE_TYPE_##nextq_type << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT))
418 struct i40e_flex_pit {
419 struct list_head list;
424 struct i40e_fwd_adapter {
425 struct net_device *netdev;
429 struct i40e_channel {
430 struct list_head list;
433 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
434 u16 stat_counter_idx;
436 u16 num_queue_pairs; /* Requested by user */
440 struct i40e_aqc_vsi_properties_data info;
443 struct i40e_fwd_adapter *fwd;
445 /* track this channel belongs to which VSI */
446 struct i40e_vsi *parent_vsi;
449 struct i40e_ptp_pins_settings;
451 static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)
456 static inline const u8 *i40e_channel_mac(struct i40e_channel *ch)
458 if (i40e_is_channel_macvlan(ch))
459 return ch->fwd->netdev->dev_addr;
464 /* struct that defines the Ethernet device */
466 struct pci_dev *pdev;
467 struct devlink_port devlink_port;
469 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
470 struct msix_entry *msix_entries;
472 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
473 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
474 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
475 u16 num_req_vfs; /* num VFs requested for this PF */
476 u16 num_vf_qps; /* num queue pairs per VF */
477 u16 num_lan_qps; /* num lan queues this PF has set up */
478 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
479 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
480 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
481 int iwarp_base_vector;
482 int queues_left; /* queues left unclaimed */
483 u16 alloc_rss_size; /* allocated RSS queues */
484 u16 rss_size_max; /* HW defined max RSS queues */
485 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
486 u16 num_alloc_vsi; /* num VSIs this driver supports */
489 struct hlist_head fdir_filter_list;
490 u16 fdir_pf_active_filters;
491 unsigned long fd_flush_timestamp;
496 /* Book-keeping of side-band filter count per flow-type.
497 * This is used to detect and handle input set changes for
498 * respective flow-type.
500 u16 fd_tcp4_filter_cnt;
501 u16 fd_udp4_filter_cnt;
502 u16 fd_sctp4_filter_cnt;
503 u16 fd_ip4_filter_cnt;
505 u16 fd_tcp6_filter_cnt;
506 u16 fd_udp6_filter_cnt;
507 u16 fd_sctp6_filter_cnt;
508 u16 fd_ip6_filter_cnt;
510 /* Flexible filter table values that need to be programmed into
511 * hardware, which expects L3 and L4 to be programmed separately. We
512 * need to ensure that the values are in ascended order and don't have
513 * duplicates, so we track each L3 and L4 values in separate lists.
515 struct list_head l3_flex_pit_list;
516 struct list_head l4_flex_pit_list;
518 struct udp_tunnel_nic_shared udp_tunnel_shared;
519 struct udp_tunnel_nic_info udp_tunnel_nic;
521 struct hlist_head cloud_filter_list;
522 u16 num_cloud_filters;
527 char int_name[I40E_INT_NAME_STR_LEN];
528 unsigned long service_timer_period;
529 unsigned long service_timer_previous;
530 struct timer_list service_timer;
531 struct work_struct service_task;
533 DECLARE_BITMAP(flags, I40E_PF_FLAGS_NBITS);
534 struct i40e_client_instance *cinst;
535 bool stat_offsets_loaded;
536 struct i40e_hw_port_stats stats;
537 struct i40e_hw_port_stats stats_offsets;
538 u32 tx_timeout_count;
539 u32 tx_timeout_recovery_level;
540 unsigned long tx_timeout_last_recovery;
541 u32 hw_csum_rx_error;
543 u16 corer_count; /* Core reset count */
544 u16 globr_count; /* Global reset count */
545 u16 empr_count; /* EMP reset count */
546 u16 pfr_count; /* PF reset count */
547 u16 sw_int_count; /* SW interrupt count */
549 struct mutex switch_mutex;
550 u16 lan_vsi; /* our default LAN VSI */
551 u16 lan_veb; /* initial relay, if exists */
552 #define I40E_NO_VEB 0xffff
553 #define I40E_NO_VSI 0xffff
554 u16 next_vsi; /* Next unallocated VSI - 0-based! */
555 struct i40e_vsi **vsi;
556 struct i40e_veb *veb[I40E_MAX_VEB];
558 struct i40e_lump_tracking *qp_pile;
559 struct i40e_lump_tracking *irq_pile;
561 /* switch config info */
564 #ifdef CONFIG_DEBUG_FS
565 struct dentry *i40e_dbg_pf;
566 #endif /* CONFIG_DEBUG_FS */
569 /* sr-iov config info */
571 int num_alloc_vfs; /* actual number of VFs allocated */
573 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
575 /* DCBx/DCBNL capability for PF that indicates
576 * whether DCBx is managed by firmware or host
577 * based agent (LLDPAD). Also, indicates what
578 * flavor of DCBx protocol (IEEE/CEE) is supported
579 * by the device. For now we're supporting IEEE
584 struct i40e_filter_control_settings filter_settings;
585 struct i40e_rx_pb_config pb_cfg; /* Current Rx packet buffer config */
586 struct i40e_dcbx_config tmp_cfg;
588 /* GPIO defines used by PTP */
589 #define I40E_SDP3_2 18
590 #define I40E_SDP3_3 19
591 #define I40E_GPIO_4 20
592 #define I40E_LED2_0 26
593 #define I40E_LED2_1 27
594 #define I40E_LED3_0 28
595 #define I40E_LED3_1 29
596 #define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \
597 (1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
598 #define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \
599 (1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
600 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \
601 (0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
602 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \
603 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
604 #define I40E_GLGEN_GPIO_CTL_RESERVED BIT(2)
605 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \
606 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
607 #define I40E_GLGEN_GPIO_CTL_DIR_OUT \
608 (1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
609 #define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \
610 (1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
611 #define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \
612 (1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
613 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \
614 (3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
615 #define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \
616 (4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
617 #define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \
618 (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
619 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \
620 (1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
621 #define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \
622 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
623 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
624 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
625 #define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \
626 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
627 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
628 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
629 #define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \
630 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
631 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
632 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
633 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
634 #define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \
635 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
636 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
637 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
638 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
639 #define I40E_GLGEN_GPIO_CTL_LED_INIT \
640 (I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \
641 I40E_GLGEN_GPIO_CTL_DIR_OUT | \
642 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \
643 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
644 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \
645 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN)
646 #define I40E_PRTTSYN_AUX_1_INSTNT \
647 (1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
648 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE \
649 (1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
650 #define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD (3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
651 #define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \
652 (I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD)
653 #define I40E_PTP_HALF_SECOND 500000000LL /* nano seconds */
654 #define I40E_PTP_2_SEC_DELAY 2
656 struct ptp_clock *ptp_clock;
657 struct ptp_clock_info ptp_caps;
658 struct sk_buff *ptp_tx_skb;
659 unsigned long ptp_tx_start;
660 struct hwtstamp_config tstamp_config;
661 struct timespec64 ptp_prev_hw_time;
662 struct work_struct ptp_extts0_work;
663 ktime_t ptp_reset_start;
664 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
666 u32 tx_hwtstamp_timeouts;
667 u32 tx_hwtstamp_skipped;
668 u32 rx_hwtstamp_cleared;
669 u32 latch_event_flags;
670 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
671 unsigned long latch_events[4];
674 struct i40e_ptp_pins_settings *ptp_pins;
675 u16 rss_table_size; /* HW RSS table size */
683 u16 last_sw_conf_flags;
684 u16 last_sw_conf_valid_flags;
685 /* List to keep previous DDP profiles to be rolled back in the future */
686 struct list_head ddp_old_prof;
690 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
691 * @macaddr: the MAC Address as the base key
693 * Simply copies the address and returns it as a u64 for hashing
695 static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
699 ether_addr_copy((u8 *)&key, macaddr);
703 enum i40e_filter_state {
704 I40E_FILTER_INVALID = 0, /* Invalid state */
705 I40E_FILTER_NEW, /* New, not sent to FW yet */
706 I40E_FILTER_ACTIVE, /* Added to switch by FW */
707 I40E_FILTER_FAILED, /* Rejected by FW */
708 I40E_FILTER_REMOVE, /* To be removed */
709 /* There is no 'removed' state; the filter struct is freed */
711 struct i40e_mac_filter {
712 struct hlist_node hlist;
713 u8 macaddr[ETH_ALEN];
714 #define I40E_VLAN_ANY -1
716 enum i40e_filter_state state;
719 /* Wrapper structure to keep track of filters while we are preparing to send
720 * firmware commands. We cannot send firmware commands while holding a
721 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
722 * a separate structure, which will track the state change and update the real
723 * filter while under lock. We can't simply hold the filters in a separate
724 * list, as this opens a window for a race condition when adding new MAC
725 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
727 struct i40e_new_mac_filter {
728 struct hlist_node hlist;
729 struct i40e_mac_filter *f;
731 /* Track future changes to state separately */
732 enum i40e_filter_state state;
738 u16 veb_idx; /* index of VEB parent */
741 u16 stats_idx; /* index of VEB parent */
743 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
748 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
749 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
750 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
751 struct kobject *kobj;
752 bool stat_offsets_loaded;
753 struct i40e_eth_stats stats;
754 struct i40e_eth_stats stats_offsets;
755 struct i40e_veb_tc_stats tc_stats;
756 struct i40e_veb_tc_stats tc_stats_offsets;
759 /* struct that defines a VSI, associated with a dev */
761 struct net_device *netdev;
762 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
763 bool netdev_registered;
764 bool stat_offsets_loaded;
766 u32 current_netdev_flags;
767 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
768 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
769 #define I40E_VSI_FLAG_VEB_OWNER BIT(1)
772 /* Per VSI lock to protect elements/hash (MAC filter) */
773 spinlock_t mac_filter_hash_lock;
774 /* Fixed size hash table with 2^8 buckets for MAC filters */
775 DECLARE_HASHTABLE(mac_filter_hash, 8);
776 bool has_vlan_filter;
779 struct rtnl_link_stats64 net_stats;
780 struct rtnl_link_stats64 net_stats_offsets;
781 struct i40e_eth_stats eth_stats;
782 struct i40e_eth_stats eth_stats_offsets;
795 /* These are containers of ring pointers, allocated at run-time */
796 struct i40e_ring **rx_rings;
797 struct i40e_ring **tx_rings;
798 struct i40e_ring **xdp_rings; /* XDP Tx rings */
801 u32 promisc_threshold;
804 u16 int_rate_limit; /* value in usecs */
806 u16 rss_table_size; /* HW RSS table size */
807 u16 rss_size; /* Allocated RSS queues */
808 u8 *rss_hkey_user; /* User configured hash keys */
809 u8 *rss_lut_user; /* User configured lookup table entries */
815 struct bpf_prog *xdp_prog;
817 /* List of q_vectors allocated to this VSI */
818 struct i40e_q_vector **q_vectors;
823 u16 seid; /* HW index of this VSI (absolute index) */
824 u16 id; /* VSI number */
827 u16 base_queue; /* vsi's first queue in hw array */
828 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
829 u16 req_queue_pairs; /* User requested queue pairs */
830 u16 num_queue_pairs; /* Used tx and rx pairs */
833 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
834 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
836 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
837 struct i40e_tc_configuration tc_config;
838 struct i40e_aqc_vsi_properties_data info;
840 /* VSI BW limit (absolute across all TCs) */
841 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
842 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
844 /* Relative TC credits across VSIs */
845 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
846 /* TC BW limit credits within VSI */
847 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
848 /* TC BW limit max quanta within VSI */
849 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
851 struct i40e_pf *back; /* Backreference to associated PF */
852 u16 idx; /* index in pf->vsi[] */
853 u16 veb_idx; /* index of VEB parent */
854 struct kobject *kobj; /* sysfs object */
855 bool current_isup; /* Sync 'link up' logging */
856 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
858 /* channel specific fields */
859 u16 cnt_q_avail; /* num of queues available for channel usage */
861 u16 current_rss_size;
864 u16 next_base_queue; /* next queue to be used for channel setup */
866 struct list_head ch_list;
867 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
870 #define I40E_MAX_MACVLANS 128 /* Max HW vectors - 1 on FVL */
871 #define I40E_MIN_MACVLAN_VECTORS 2 /* Min vectors to enable macvlans */
872 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS);
873 struct list_head macvlan_list;
876 void *priv; /* client driver data reference. */
878 /* VSI specific handlers */
879 irqreturn_t (*irq_handler)(int irq, void *data);
881 unsigned long *af_xdp_zc_qps; /* tracks AF_XDP ZC enabled qps */
882 } ____cacheline_internodealigned_in_smp;
884 struct i40e_netdev_priv {
885 struct i40e_vsi *vsi;
888 extern struct ida i40e_client_ida;
890 /* struct that defines an interrupt vector */
891 struct i40e_q_vector {
892 struct i40e_vsi *vsi;
894 u16 v_idx; /* index in the vsi->q_vector array. */
895 u16 reg_idx; /* register index of the interrupt */
897 struct napi_struct napi;
899 struct i40e_ring_container rx;
900 struct i40e_ring_container tx;
902 u8 itr_countdown; /* when 0 should adjust adaptive ITR */
903 u8 num_ringpairs; /* total number of ring pairs in vector */
905 cpumask_t affinity_mask;
906 struct irq_affinity_notify affinity_notify;
908 struct rcu_head rcu; /* to avoid race with update stats on free */
909 char name[I40E_INT_NAME_STR_LEN];
912 int irq_num; /* IRQ assigned to this q_vector */
913 } ____cacheline_internodealigned_in_smp;
917 struct list_head list;
922 * i40e_info_nvm_ver - format the NVM version string
923 * @hw: ptr to the hardware info
924 * @buf: string buffer to store
927 * Formats NVM version string as:
928 * <gen>.<snap>.<release> when eetrackid == I40E_OEM_EETRACK_ID
929 * <nvm_major>.<nvm_minor> otherwise
931 static inline void i40e_info_nvm_ver(struct i40e_hw *hw, char *buf, size_t len)
933 struct i40e_nvm_info *nvm = &hw->nvm;
935 if (nvm->eetrack == I40E_OEM_EETRACK_ID) {
936 u32 full_ver = nvm->oem_ver;
940 gen = FIELD_GET(I40E_OEM_GEN_MASK, full_ver);
941 snap = FIELD_GET(I40E_OEM_SNAP_MASK, full_ver);
942 release = FIELD_GET(I40E_OEM_RELEASE_MASK, full_ver);
943 snprintf(buf, len, "%x.%x.%x", gen, snap, release);
947 major = FIELD_GET(I40E_NVM_VERSION_HI_MASK, nvm->version);
948 minor = FIELD_GET(I40E_NVM_VERSION_LO_MASK, nvm->version);
949 snprintf(buf, len, "%x.%02x", major, minor);
954 * i40e_info_eetrack - format the EETrackID string
955 * @hw: ptr to the hardware info
956 * @buf: string buffer to store
959 * Returns hexadecimally formated EETrackID if it is
960 * different from I40E_OEM_EETRACK_ID or empty string.
962 static inline void i40e_info_eetrack(struct i40e_hw *hw, char *buf, size_t len)
964 struct i40e_nvm_info *nvm = &hw->nvm;
967 if (nvm->eetrack != I40E_OEM_EETRACK_ID)
968 snprintf(buf, len, "0x%08x", nvm->eetrack);
972 * i40e_info_civd_ver - format the NVM version strings
973 * @hw: ptr to the hardware info
974 * @buf: string buffer to store
977 * Returns formated combo image version if adapter's EETrackID is
978 * different from I40E_OEM_EETRACK_ID or empty string.
980 static inline void i40e_info_civd_ver(struct i40e_hw *hw, char *buf, size_t len)
982 struct i40e_nvm_info *nvm = &hw->nvm;
985 if (nvm->eetrack != I40E_OEM_EETRACK_ID) {
986 u32 full_ver = nvm->oem_ver;
990 major = FIELD_GET(I40E_OEM_VER_MASK, full_ver);
991 build = FIELD_GET(I40E_OEM_VER_BUILD_MASK, full_ver);
992 minor = FIELD_GET(I40E_OEM_VER_PATCH_MASK, full_ver);
993 snprintf(buf, len, "%d.%d.%d", major, build, minor);
998 * i40e_nvm_version_str - format the NVM version strings
999 * @hw: ptr to the hardware info
1000 * @buf: string buffer to store
1003 static inline char *i40e_nvm_version_str(struct i40e_hw *hw, char *buf,
1008 /* Get NVM version */
1009 i40e_info_nvm_ver(hw, buf, len);
1011 /* Append EETrackID if provided */
1012 i40e_info_eetrack(hw, &ver[1], sizeof(ver) - 1);
1013 if (strlen(ver) > 1)
1014 strlcat(buf, ver, len);
1016 /* Append combo image version if provided */
1017 i40e_info_civd_ver(hw, &ver[1], sizeof(ver) - 1);
1018 if (strlen(ver) > 1)
1019 strlcat(buf, ver, len);
1025 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
1026 * @netdev: the corresponding netdev
1028 * Return the PF struct for the given netdev
1030 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
1032 struct i40e_netdev_priv *np = netdev_priv(netdev);
1033 struct i40e_vsi *vsi = np->vsi;
1038 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
1039 irqreturn_t (*irq_handler)(int, void *))
1041 vsi->irq_handler = irq_handler;
1045 * i40e_get_fd_cnt_all - get the total FD filter space available
1046 * @pf: pointer to the PF struct
1048 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
1050 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
1054 * i40e_read_fd_input_set - reads value of flow director input set register
1055 * @pf: pointer to the PF struct
1056 * @addr: register addr
1058 * This function reads value of flow director input set register
1059 * specified by 'addr' (which is specific to flow-type)
1061 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
1065 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
1067 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
1073 * i40e_write_fd_input_set - writes value into flow director input set register
1074 * @pf: pointer to the PF struct
1075 * @addr: register addr
1076 * @val: value to be written
1078 * This function writes specified value to the register specified by 'addr'.
1079 * This register is input set register based on flow-type.
1081 static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
1084 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
1086 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
1087 (u32)(val & 0xFFFFFFFFULL));
1091 * i40e_get_pf_count - get PCI PF count.
1092 * @hw: pointer to a hw.
1094 * Reports the function number of the highest PCI physical
1095 * function plus 1 as it is loaded from the NVM.
1097 * Return: PCI PF count.
1099 static inline u32 i40e_get_pf_count(struct i40e_hw *hw)
1101 return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK,
1102 rd32(hw, I40E_GLGEN_PCIFCNCNT));
1105 /* needed by i40e_ethtool.c */
1106 int i40e_up(struct i40e_vsi *vsi);
1107 void i40e_down(struct i40e_vsi *vsi);
1108 extern const char i40e_driver_name[];
1109 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
1110 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
1111 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1112 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1113 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
1114 u16 rss_table_size, u16 rss_size);
1115 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
1117 * i40e_find_vsi_by_type - Find and return Flow Director VSI
1118 * @pf: PF to search for VSI
1119 * @type: Value indicating type of VSI we are looking for
1121 static inline struct i40e_vsi *
1122 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
1126 for (i = 0; i < pf->num_alloc_vsi; i++) {
1127 struct i40e_vsi *vsi = pf->vsi[i];
1129 if (vsi && vsi->type == type)
1135 void i40e_update_stats(struct i40e_vsi *vsi);
1136 void i40e_update_veb_stats(struct i40e_veb *veb);
1137 void i40e_update_eth_stats(struct i40e_vsi *vsi);
1138 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
1139 int i40e_fetch_switch_configuration(struct i40e_pf *pf,
1142 int i40e_add_del_fdir(struct i40e_vsi *vsi,
1143 struct i40e_fdir_filter *input, bool add);
1144 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
1145 u32 i40e_get_current_fd_count(struct i40e_pf *pf);
1146 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1147 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
1148 u32 i40e_get_global_fd_count(struct i40e_pf *pf);
1149 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
1150 void i40e_set_ethtool_ops(struct net_device *netdev);
1151 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1152 const u8 *macaddr, s16 vlan);
1153 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1154 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1155 int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1156 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1157 u16 uplink, u32 param1);
1158 int i40e_vsi_release(struct i40e_vsi *vsi);
1159 void i40e_service_event_schedule(struct i40e_pf *pf);
1160 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1163 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
1165 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
1166 int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1167 void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1168 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
1169 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1170 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1171 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1172 u16 downlink_seid, u8 enabled_tc);
1173 void i40e_veb_release(struct i40e_veb *veb);
1175 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1176 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1177 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1178 void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1179 void i40e_pf_reset_stats(struct i40e_pf *pf);
1180 #ifdef CONFIG_DEBUG_FS
1181 void i40e_dbg_pf_init(struct i40e_pf *pf);
1182 void i40e_dbg_pf_exit(struct i40e_pf *pf);
1183 void i40e_dbg_init(void);
1184 void i40e_dbg_exit(void);
1186 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
1187 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
1188 static inline void i40e_dbg_init(void) {}
1189 static inline void i40e_dbg_exit(void) {}
1190 #endif /* CONFIG_DEBUG_FS*/
1191 /* needed by client drivers */
1192 int i40e_lan_add_device(struct i40e_pf *pf);
1193 int i40e_lan_del_device(struct i40e_pf *pf);
1194 void i40e_client_subtask(struct i40e_pf *pf);
1195 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1196 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1197 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1198 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1199 void i40e_client_update_msix_info(struct i40e_pf *pf);
1200 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1202 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1203 * @vsi: pointer to a vsi
1204 * @vector: enable a particular Hw Interrupt vector, without base_vector
1206 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1208 struct i40e_pf *pf = vsi->back;
1209 struct i40e_hw *hw = &pf->hw;
1212 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1213 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1214 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1215 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1216 /* skip the flush */
1219 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1220 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1221 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1222 int i40e_open(struct net_device *netdev);
1223 int i40e_close(struct net_device *netdev);
1224 int i40e_vsi_open(struct i40e_vsi *vsi);
1225 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1226 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1227 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1228 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1229 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1230 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1232 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1233 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1234 int i40e_count_filters(struct i40e_vsi *vsi);
1235 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1236 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1237 static inline bool i40e_is_sw_dcb(struct i40e_pf *pf)
1239 return test_bit(I40E_FLAG_FW_LLDP_DIS, pf->flags);
1242 #ifdef CONFIG_I40E_DCB
1243 void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1244 struct i40e_dcbx_config *old_cfg,
1245 struct i40e_dcbx_config *new_cfg);
1246 void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1247 void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1248 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1249 struct i40e_dcbx_config *old_cfg,
1250 struct i40e_dcbx_config *new_cfg);
1251 int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg);
1252 int i40e_dcb_sw_default_config(struct i40e_pf *pf);
1253 #endif /* CONFIG_I40E_DCB */
1254 void i40e_ptp_rx_hang(struct i40e_pf *pf);
1255 void i40e_ptp_tx_hang(struct i40e_pf *pf);
1256 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1257 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1258 void i40e_ptp_set_increment(struct i40e_pf *pf);
1259 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1260 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1261 void i40e_ptp_save_hw_time(struct i40e_pf *pf);
1262 void i40e_ptp_restore_hw_time(struct i40e_pf *pf);
1263 void i40e_ptp_init(struct i40e_pf *pf);
1264 void i40e_ptp_stop(struct i40e_pf *pf);
1265 int i40e_ptp_alloc_pins(struct i40e_pf *pf);
1266 int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset);
1267 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1268 int i40e_get_partition_bw_setting(struct i40e_pf *pf);
1269 int i40e_set_partition_bw_setting(struct i40e_pf *pf);
1270 int i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1271 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1273 void i40e_set_fec_in_flags(u8 fec_cfg, unsigned long *flags);
1275 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1277 return !!READ_ONCE(vsi->xdp_prog);
1280 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1281 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1282 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1283 struct i40e_cloud_filter *filter,
1285 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1286 struct i40e_cloud_filter *filter,
1290 * i40e_is_tc_mqprio_enabled - check if TC MQPRIO is enabled on PF
1291 * @pf: pointer to a pf.
1293 * Check and return state of flag I40E_FLAG_TC_MQPRIO.
1295 * Return: true/false if I40E_FLAG_TC_MQPRIO is set or not
1297 static inline bool i40e_is_tc_mqprio_enabled(struct i40e_pf *pf)
1299 return test_bit(I40E_FLAG_TC_MQPRIO_ENA, pf->flags);
1303 * i40e_hw_to_pf - get pf pointer from the hardware structure
1304 * @hw: pointer to the device HW structure
1306 static inline struct i40e_pf *i40e_hw_to_pf(struct i40e_hw *hw)
1308 return container_of(hw, struct i40e_pf, hw);
1311 struct device *i40e_hw_to_dev(struct i40e_hw *hw);
1313 #endif /* _I40E_H_ */