1 /* Intel(R) Ethernet Switch Host Interface Driver
2 * Copyright(c) 2013 - 2017 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
16 * Contact Information:
17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21 #include <linux/types.h>
22 #include <linux/module.h>
26 #include <linux/if_macvlan.h>
27 #include <linux/prefetch.h>
31 #define DRV_VERSION "0.21.7-k"
32 #define DRV_SUMMARY "Intel(R) Ethernet Switch Host Interface Driver"
33 const char fm10k_driver_version[] = DRV_VERSION;
34 char fm10k_driver_name[] = "fm10k";
35 static const char fm10k_driver_string[] = DRV_SUMMARY;
36 static const char fm10k_copyright[] =
37 "Copyright(c) 2013 - 2017 Intel Corporation.";
39 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
40 MODULE_DESCRIPTION(DRV_SUMMARY);
41 MODULE_LICENSE("GPL");
42 MODULE_VERSION(DRV_VERSION);
44 /* single workqueue for entire fm10k driver */
45 struct workqueue_struct *fm10k_workqueue;
48 * fm10k_init_module - Driver Registration Routine
50 * fm10k_init_module is the first routine called when the driver is
51 * loaded. All it does is register with the PCI subsystem.
53 static int __init fm10k_init_module(void)
55 pr_info("%s - version %s\n", fm10k_driver_string, fm10k_driver_version);
56 pr_info("%s\n", fm10k_copyright);
58 /* create driver workqueue */
59 fm10k_workqueue = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0,
66 return fm10k_register_pci_driver();
68 module_init(fm10k_init_module);
71 * fm10k_exit_module - Driver Exit Cleanup Routine
73 * fm10k_exit_module is called just before the driver is removed
76 static void __exit fm10k_exit_module(void)
78 fm10k_unregister_pci_driver();
82 /* destroy driver workqueue */
83 destroy_workqueue(fm10k_workqueue);
85 module_exit(fm10k_exit_module);
87 static bool fm10k_alloc_mapped_page(struct fm10k_ring *rx_ring,
88 struct fm10k_rx_buffer *bi)
90 struct page *page = bi->page;
93 /* Only page will be NULL if buffer was consumed */
97 /* alloc new page for storage */
98 page = dev_alloc_page();
99 if (unlikely(!page)) {
100 rx_ring->rx_stats.alloc_failed++;
104 /* map page for use */
105 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
107 /* if mapping failed free memory back to system since
108 * there isn't much point in holding memory we can't use
110 if (dma_mapping_error(rx_ring->dev, dma)) {
113 rx_ring->rx_stats.alloc_failed++;
125 * fm10k_alloc_rx_buffers - Replace used receive buffers
126 * @rx_ring: ring to place buffers on
127 * @cleaned_count: number of buffers to replace
129 void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count)
131 union fm10k_rx_desc *rx_desc;
132 struct fm10k_rx_buffer *bi;
133 u16 i = rx_ring->next_to_use;
139 rx_desc = FM10K_RX_DESC(rx_ring, i);
140 bi = &rx_ring->rx_buffer[i];
144 if (!fm10k_alloc_mapped_page(rx_ring, bi))
147 /* Refresh the desc even if buffer_addrs didn't change
148 * because each write-back erases this info.
150 rx_desc->q.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
156 rx_desc = FM10K_RX_DESC(rx_ring, 0);
157 bi = rx_ring->rx_buffer;
161 /* clear the status bits for the next_to_use descriptor */
162 rx_desc->d.staterr = 0;
165 } while (cleaned_count);
169 if (rx_ring->next_to_use != i) {
170 /* record the next descriptor to use */
171 rx_ring->next_to_use = i;
173 /* update next to alloc since we have filled the ring */
174 rx_ring->next_to_alloc = i;
176 /* Force memory writes to complete before letting h/w
177 * know there are new descriptors to fetch. (Only
178 * applicable for weak-ordered memory model archs,
183 /* notify hardware of new descriptors */
184 writel(i, rx_ring->tail);
189 * fm10k_reuse_rx_page - page flip buffer and store it back on the ring
190 * @rx_ring: rx descriptor ring to store buffers on
191 * @old_buff: donor buffer to have page reused
193 * Synchronizes page for reuse by the interface
195 static void fm10k_reuse_rx_page(struct fm10k_ring *rx_ring,
196 struct fm10k_rx_buffer *old_buff)
198 struct fm10k_rx_buffer *new_buff;
199 u16 nta = rx_ring->next_to_alloc;
201 new_buff = &rx_ring->rx_buffer[nta];
203 /* update, and store next to alloc */
205 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
207 /* transfer page from old buffer to new buffer */
208 *new_buff = *old_buff;
210 /* sync the buffer for use by the device */
211 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
212 old_buff->page_offset,
217 static inline bool fm10k_page_is_reserved(struct page *page)
219 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
222 static bool fm10k_can_reuse_rx_page(struct fm10k_rx_buffer *rx_buffer,
224 unsigned int __maybe_unused truesize)
226 /* avoid re-using remote pages */
227 if (unlikely(fm10k_page_is_reserved(page)))
230 #if (PAGE_SIZE < 8192)
231 /* if we are only owner of page we can reuse it */
232 if (unlikely(page_count(page) != 1))
235 /* flip page offset to other buffer */
236 rx_buffer->page_offset ^= FM10K_RX_BUFSZ;
238 /* move offset up to the next cache line */
239 rx_buffer->page_offset += truesize;
241 if (rx_buffer->page_offset > (PAGE_SIZE - FM10K_RX_BUFSZ))
245 /* Even if we own the page, we are not allowed to use atomic_set()
246 * This would break get_page_unless_zero() users.
254 * fm10k_add_rx_frag - Add contents of Rx buffer to sk_buff
255 * @rx_buffer: buffer containing page to add
256 * @size: packet size from rx_desc
257 * @rx_desc: descriptor containing length of buffer written by hardware
258 * @skb: sk_buff to place the data into
260 * This function will add the data contained in rx_buffer->page to the skb.
261 * This is done either through a direct copy if the data in the buffer is
262 * less than the skb header size, otherwise it will just attach the page as
265 * The function will then update the page offset if necessary and return
266 * true if the buffer can be reused by the interface.
268 static bool fm10k_add_rx_frag(struct fm10k_rx_buffer *rx_buffer,
270 union fm10k_rx_desc *rx_desc,
273 struct page *page = rx_buffer->page;
274 unsigned char *va = page_address(page) + rx_buffer->page_offset;
275 #if (PAGE_SIZE < 8192)
276 unsigned int truesize = FM10K_RX_BUFSZ;
278 unsigned int truesize = ALIGN(size, 512);
280 unsigned int pull_len;
282 if (unlikely(skb_is_nonlinear(skb)))
285 if (likely(size <= FM10K_RX_HDR_LEN)) {
286 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
288 /* page is not reserved, we can reuse buffer as-is */
289 if (likely(!fm10k_page_is_reserved(page)))
292 /* this page cannot be reused so discard it */
297 /* we need the header to contain the greater of either ETH_HLEN or
298 * 60 bytes if the skb->len is less than 60 for skb_pad.
300 pull_len = eth_get_headlen(va, FM10K_RX_HDR_LEN);
302 /* align pull length to size of long to optimize memcpy performance */
303 memcpy(__skb_put(skb, pull_len), va, ALIGN(pull_len, sizeof(long)));
305 /* update all of the pointers */
310 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
311 (unsigned long)va & ~PAGE_MASK, size, truesize);
313 return fm10k_can_reuse_rx_page(rx_buffer, page, truesize);
316 static struct sk_buff *fm10k_fetch_rx_buffer(struct fm10k_ring *rx_ring,
317 union fm10k_rx_desc *rx_desc,
320 unsigned int size = le16_to_cpu(rx_desc->w.length);
321 struct fm10k_rx_buffer *rx_buffer;
324 rx_buffer = &rx_ring->rx_buffer[rx_ring->next_to_clean];
325 page = rx_buffer->page;
329 void *page_addr = page_address(page) +
330 rx_buffer->page_offset;
332 /* prefetch first cache line of first page */
334 #if L1_CACHE_BYTES < 128
335 prefetch(page_addr + L1_CACHE_BYTES);
338 /* allocate a skb to store the frags */
339 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
341 if (unlikely(!skb)) {
342 rx_ring->rx_stats.alloc_failed++;
346 /* we will be copying header into skb->data in
347 * pskb_may_pull so it is in our interest to prefetch
348 * it now to avoid a possible cache miss
350 prefetchw(skb->data);
353 /* we are reusing so sync this buffer for CPU use */
354 dma_sync_single_range_for_cpu(rx_ring->dev,
356 rx_buffer->page_offset,
360 /* pull page into skb */
361 if (fm10k_add_rx_frag(rx_buffer, size, rx_desc, skb)) {
362 /* hand second half of page back to the ring */
363 fm10k_reuse_rx_page(rx_ring, rx_buffer);
365 /* we are not reusing the buffer so unmap it */
366 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
367 PAGE_SIZE, DMA_FROM_DEVICE);
370 /* clear contents of rx_buffer */
371 rx_buffer->page = NULL;
376 static inline void fm10k_rx_checksum(struct fm10k_ring *ring,
377 union fm10k_rx_desc *rx_desc,
380 skb_checksum_none_assert(skb);
382 /* Rx checksum disabled via ethtool */
383 if (!(ring->netdev->features & NETIF_F_RXCSUM))
386 /* TCP/UDP checksum error bit is set */
387 if (fm10k_test_staterr(rx_desc,
388 FM10K_RXD_STATUS_L4E |
389 FM10K_RXD_STATUS_L4E2 |
390 FM10K_RXD_STATUS_IPE |
391 FM10K_RXD_STATUS_IPE2)) {
392 ring->rx_stats.csum_err++;
396 /* It must be a TCP or UDP packet with a valid checksum */
397 if (fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_L4CS2))
398 skb->encapsulation = true;
399 else if (!fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_L4CS))
402 skb->ip_summed = CHECKSUM_UNNECESSARY;
404 ring->rx_stats.csum_good++;
407 #define FM10K_RSS_L4_TYPES_MASK \
408 (BIT(FM10K_RSSTYPE_IPV4_TCP) | \
409 BIT(FM10K_RSSTYPE_IPV4_UDP) | \
410 BIT(FM10K_RSSTYPE_IPV6_TCP) | \
411 BIT(FM10K_RSSTYPE_IPV6_UDP))
413 static inline void fm10k_rx_hash(struct fm10k_ring *ring,
414 union fm10k_rx_desc *rx_desc,
419 if (!(ring->netdev->features & NETIF_F_RXHASH))
422 rss_type = le16_to_cpu(rx_desc->w.pkt_info) & FM10K_RXD_RSSTYPE_MASK;
426 skb_set_hash(skb, le32_to_cpu(rx_desc->d.rss),
427 (BIT(rss_type) & FM10K_RSS_L4_TYPES_MASK) ?
428 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
431 static void fm10k_type_trans(struct fm10k_ring *rx_ring,
432 union fm10k_rx_desc __maybe_unused *rx_desc,
435 struct net_device *dev = rx_ring->netdev;
436 struct fm10k_l2_accel *l2_accel = rcu_dereference_bh(rx_ring->l2_accel);
438 /* check to see if DGLORT belongs to a MACVLAN */
440 u16 idx = le16_to_cpu(FM10K_CB(skb)->fi.w.dglort) - 1;
442 idx -= l2_accel->dglort;
443 if (idx < l2_accel->size && l2_accel->macvlan[idx])
444 dev = l2_accel->macvlan[idx];
449 skb->protocol = eth_type_trans(skb, dev);
454 /* update MACVLAN statistics */
455 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, 1,
456 !!(rx_desc->w.hdr_info &
457 cpu_to_le16(FM10K_RXD_HDR_INFO_XC_MASK)));
461 * fm10k_process_skb_fields - Populate skb header fields from Rx descriptor
462 * @rx_ring: rx descriptor ring packet is being transacted on
463 * @rx_desc: pointer to the EOP Rx descriptor
464 * @skb: pointer to current skb being populated
466 * This function checks the ring, descriptor, and packet information in
467 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
468 * other fields within the skb.
470 static unsigned int fm10k_process_skb_fields(struct fm10k_ring *rx_ring,
471 union fm10k_rx_desc *rx_desc,
474 unsigned int len = skb->len;
476 fm10k_rx_hash(rx_ring, rx_desc, skb);
478 fm10k_rx_checksum(rx_ring, rx_desc, skb);
480 FM10K_CB(skb)->tstamp = rx_desc->q.timestamp;
482 FM10K_CB(skb)->fi.w.vlan = rx_desc->w.vlan;
484 skb_record_rx_queue(skb, rx_ring->queue_index);
486 FM10K_CB(skb)->fi.d.glort = rx_desc->d.glort;
488 if (rx_desc->w.vlan) {
489 u16 vid = le16_to_cpu(rx_desc->w.vlan);
491 if ((vid & VLAN_VID_MASK) != rx_ring->vid)
492 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
493 else if (vid & VLAN_PRIO_MASK)
494 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
495 vid & VLAN_PRIO_MASK);
498 fm10k_type_trans(rx_ring, rx_desc, skb);
504 * fm10k_is_non_eop - process handling of non-EOP buffers
505 * @rx_ring: Rx ring being processed
506 * @rx_desc: Rx descriptor for current buffer
508 * This function updates next to clean. If the buffer is an EOP buffer
509 * this function exits returning false, otherwise it will place the
510 * sk_buff in the next buffer to be chained and return true indicating
511 * that this is in fact a non-EOP buffer.
513 static bool fm10k_is_non_eop(struct fm10k_ring *rx_ring,
514 union fm10k_rx_desc *rx_desc)
516 u32 ntc = rx_ring->next_to_clean + 1;
518 /* fetch, update, and store next to clean */
519 ntc = (ntc < rx_ring->count) ? ntc : 0;
520 rx_ring->next_to_clean = ntc;
522 prefetch(FM10K_RX_DESC(rx_ring, ntc));
524 if (likely(fm10k_test_staterr(rx_desc, FM10K_RXD_STATUS_EOP)))
531 * fm10k_cleanup_headers - Correct corrupted or empty headers
532 * @rx_ring: rx descriptor ring packet is being transacted on
533 * @rx_desc: pointer to the EOP Rx descriptor
534 * @skb: pointer to current skb being fixed
536 * Address the case where we are pulling data in on pages only
537 * and as such no data is present in the skb header.
539 * In addition if skb is not at least 60 bytes we need to pad it so that
540 * it is large enough to qualify as a valid Ethernet frame.
542 * Returns true if an error was encountered and skb was freed.
544 static bool fm10k_cleanup_headers(struct fm10k_ring *rx_ring,
545 union fm10k_rx_desc *rx_desc,
548 if (unlikely((fm10k_test_staterr(rx_desc,
549 FM10K_RXD_STATUS_RXE)))) {
550 #define FM10K_TEST_RXD_BIT(rxd, bit) \
551 ((rxd)->w.csum_err & cpu_to_le16(bit))
552 if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_SWITCH_ERROR))
553 rx_ring->rx_stats.switch_errors++;
554 if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_NO_DESCRIPTOR))
555 rx_ring->rx_stats.drops++;
556 if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_PP_ERROR))
557 rx_ring->rx_stats.pp_errors++;
558 if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_SWITCH_READY))
559 rx_ring->rx_stats.link_errors++;
560 if (FM10K_TEST_RXD_BIT(rx_desc, FM10K_RXD_ERR_TOO_BIG))
561 rx_ring->rx_stats.length_errors++;
562 dev_kfree_skb_any(skb);
563 rx_ring->rx_stats.errors++;
567 /* if eth_skb_pad returns an error the skb was freed */
568 if (eth_skb_pad(skb))
575 * fm10k_receive_skb - helper function to handle rx indications
576 * @q_vector: structure containing interrupt and ring information
577 * @skb: packet to send up
579 static void fm10k_receive_skb(struct fm10k_q_vector *q_vector,
582 napi_gro_receive(&q_vector->napi, skb);
585 static int fm10k_clean_rx_irq(struct fm10k_q_vector *q_vector,
586 struct fm10k_ring *rx_ring,
589 struct sk_buff *skb = rx_ring->skb;
590 unsigned int total_bytes = 0, total_packets = 0;
591 u16 cleaned_count = fm10k_desc_unused(rx_ring);
593 while (likely(total_packets < budget)) {
594 union fm10k_rx_desc *rx_desc;
596 /* return some buffers to hardware, one at a time is too slow */
597 if (cleaned_count >= FM10K_RX_BUFFER_WRITE) {
598 fm10k_alloc_rx_buffers(rx_ring, cleaned_count);
602 rx_desc = FM10K_RX_DESC(rx_ring, rx_ring->next_to_clean);
604 if (!rx_desc->d.staterr)
607 /* This memory barrier is needed to keep us from reading
608 * any other fields out of the rx_desc until we know the
609 * descriptor has been written back
613 /* retrieve a buffer from the ring */
614 skb = fm10k_fetch_rx_buffer(rx_ring, rx_desc, skb);
616 /* exit if we failed to retrieve a buffer */
622 /* fetch next buffer in frame if non-eop */
623 if (fm10k_is_non_eop(rx_ring, rx_desc))
626 /* verify the packet layout is correct */
627 if (fm10k_cleanup_headers(rx_ring, rx_desc, skb)) {
632 /* populate checksum, timestamp, VLAN, and protocol */
633 total_bytes += fm10k_process_skb_fields(rx_ring, rx_desc, skb);
635 fm10k_receive_skb(q_vector, skb);
637 /* reset skb pointer */
640 /* update budget accounting */
644 /* place incomplete frames back on ring for completion */
647 u64_stats_update_begin(&rx_ring->syncp);
648 rx_ring->stats.packets += total_packets;
649 rx_ring->stats.bytes += total_bytes;
650 u64_stats_update_end(&rx_ring->syncp);
651 q_vector->rx.total_packets += total_packets;
652 q_vector->rx.total_bytes += total_bytes;
654 return total_packets;
657 #define VXLAN_HLEN (sizeof(struct udphdr) + 8)
658 static struct ethhdr *fm10k_port_is_vxlan(struct sk_buff *skb)
660 struct fm10k_intfc *interface = netdev_priv(skb->dev);
661 struct fm10k_udp_port *vxlan_port;
663 /* we can only offload a vxlan if we recognize it as such */
664 vxlan_port = list_first_entry_or_null(&interface->vxlan_port,
665 struct fm10k_udp_port, list);
669 if (vxlan_port->port != udp_hdr(skb)->dest)
672 /* return offset of udp_hdr plus 8 bytes for VXLAN header */
673 return (struct ethhdr *)(skb_transport_header(skb) + VXLAN_HLEN);
676 #define FM10K_NVGRE_RESERVED0_FLAGS htons(0x9FFF)
677 #define NVGRE_TNI htons(0x2000)
678 struct fm10k_nvgre_hdr {
684 static struct ethhdr *fm10k_gre_is_nvgre(struct sk_buff *skb)
686 struct fm10k_nvgre_hdr *nvgre_hdr;
687 int hlen = ip_hdrlen(skb);
689 /* currently only IPv4 is supported due to hlen above */
690 if (vlan_get_protocol(skb) != htons(ETH_P_IP))
693 /* our transport header should be NVGRE */
694 nvgre_hdr = (struct fm10k_nvgre_hdr *)(skb_network_header(skb) + hlen);
696 /* verify all reserved flags are 0 */
697 if (nvgre_hdr->flags & FM10K_NVGRE_RESERVED0_FLAGS)
700 /* report start of ethernet header */
701 if (nvgre_hdr->flags & NVGRE_TNI)
702 return (struct ethhdr *)(nvgre_hdr + 1);
704 return (struct ethhdr *)(&nvgre_hdr->tni);
707 __be16 fm10k_tx_encap_offload(struct sk_buff *skb)
709 u8 l4_hdr = 0, inner_l4_hdr = 0, inner_l4_hlen;
710 struct ethhdr *eth_hdr;
712 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
713 skb->inner_protocol != htons(ETH_P_TEB))
716 switch (vlan_get_protocol(skb)) {
717 case htons(ETH_P_IP):
718 l4_hdr = ip_hdr(skb)->protocol;
720 case htons(ETH_P_IPV6):
721 l4_hdr = ipv6_hdr(skb)->nexthdr;
729 eth_hdr = fm10k_port_is_vxlan(skb);
732 eth_hdr = fm10k_gre_is_nvgre(skb);
741 switch (eth_hdr->h_proto) {
742 case htons(ETH_P_IP):
743 inner_l4_hdr = inner_ip_hdr(skb)->protocol;
745 case htons(ETH_P_IPV6):
746 inner_l4_hdr = inner_ipv6_hdr(skb)->nexthdr;
752 switch (inner_l4_hdr) {
754 inner_l4_hlen = inner_tcp_hdrlen(skb);
763 /* The hardware allows tunnel offloads only if the combined inner and
764 * outer header is 184 bytes or less
766 if (skb_inner_transport_header(skb) + inner_l4_hlen -
767 skb_mac_header(skb) > FM10K_TUNNEL_HEADER_LENGTH)
770 return eth_hdr->h_proto;
773 static int fm10k_tso(struct fm10k_ring *tx_ring,
774 struct fm10k_tx_buffer *first)
776 struct sk_buff *skb = first->skb;
777 struct fm10k_tx_desc *tx_desc;
781 if (skb->ip_summed != CHECKSUM_PARTIAL)
784 if (!skb_is_gso(skb))
787 /* compute header lengths */
788 if (skb->encapsulation) {
789 if (!fm10k_tx_encap_offload(skb))
791 th = skb_inner_transport_header(skb);
793 th = skb_transport_header(skb);
796 /* compute offset from SOF to transport header and add header len */
797 hdrlen = (th - skb->data) + (((struct tcphdr *)th)->doff << 2);
799 first->tx_flags |= FM10K_TX_FLAGS_CSUM;
801 /* update gso size and bytecount with header size */
802 first->gso_segs = skb_shinfo(skb)->gso_segs;
803 first->bytecount += (first->gso_segs - 1) * hdrlen;
805 /* populate Tx descriptor header size and mss */
806 tx_desc = FM10K_TX_DESC(tx_ring, tx_ring->next_to_use);
807 tx_desc->hdrlen = hdrlen;
808 tx_desc->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
812 tx_ring->netdev->features &= ~NETIF_F_GSO_UDP_TUNNEL;
813 if (!net_ratelimit())
814 netdev_err(tx_ring->netdev,
815 "TSO requested for unsupported tunnel, disabling offload\n");
819 static void fm10k_tx_csum(struct fm10k_ring *tx_ring,
820 struct fm10k_tx_buffer *first)
822 struct sk_buff *skb = first->skb;
823 struct fm10k_tx_desc *tx_desc;
826 struct ipv6hdr *ipv6;
834 if (skb->ip_summed != CHECKSUM_PARTIAL)
837 if (skb->encapsulation) {
838 protocol = fm10k_tx_encap_offload(skb);
840 if (skb_checksum_help(skb)) {
841 dev_warn(tx_ring->dev,
842 "failed to offload encap csum!\n");
843 tx_ring->tx_stats.csum_err++;
847 network_hdr.raw = skb_inner_network_header(skb);
848 transport_hdr = skb_inner_transport_header(skb);
850 protocol = vlan_get_protocol(skb);
851 network_hdr.raw = skb_network_header(skb);
852 transport_hdr = skb_transport_header(skb);
856 case htons(ETH_P_IP):
857 l4_hdr = network_hdr.ipv4->protocol;
859 case htons(ETH_P_IPV6):
860 l4_hdr = network_hdr.ipv6->nexthdr;
861 if (likely((transport_hdr - network_hdr.raw) ==
862 sizeof(struct ipv6hdr)))
864 ipv6_skip_exthdr(skb, network_hdr.raw - skb->data +
865 sizeof(struct ipv6hdr),
867 if (unlikely(frag_off))
868 l4_hdr = NEXTHDR_FRAGMENT;
879 if (skb->encapsulation)
882 if (unlikely(net_ratelimit())) {
883 dev_warn(tx_ring->dev,
884 "partial checksum, version=%d l4 proto=%x\n",
887 skb_checksum_help(skb);
888 tx_ring->tx_stats.csum_err++;
892 /* update TX checksum flag */
893 first->tx_flags |= FM10K_TX_FLAGS_CSUM;
894 tx_ring->tx_stats.csum_good++;
897 /* populate Tx descriptor header size and mss */
898 tx_desc = FM10K_TX_DESC(tx_ring, tx_ring->next_to_use);
903 #define FM10K_SET_FLAG(_input, _flag, _result) \
904 ((_flag <= _result) ? \
905 ((u32)(_input & _flag) * (_result / _flag)) : \
906 ((u32)(_input & _flag) / (_flag / _result)))
908 static u8 fm10k_tx_desc_flags(struct sk_buff *skb, u32 tx_flags)
910 /* set type for advanced descriptor with frame checksum insertion */
913 /* set checksum offload bits */
914 desc_flags |= FM10K_SET_FLAG(tx_flags, FM10K_TX_FLAGS_CSUM,
915 FM10K_TXD_FLAG_CSUM);
920 static bool fm10k_tx_desc_push(struct fm10k_ring *tx_ring,
921 struct fm10k_tx_desc *tx_desc, u16 i,
922 dma_addr_t dma, unsigned int size, u8 desc_flags)
924 /* set RS and INT for last frame in a cache line */
925 if ((++i & (FM10K_TXD_WB_FIFO_SIZE - 1)) == 0)
926 desc_flags |= FM10K_TXD_FLAG_RS | FM10K_TXD_FLAG_INT;
928 /* record values to descriptor */
929 tx_desc->buffer_addr = cpu_to_le64(dma);
930 tx_desc->flags = desc_flags;
931 tx_desc->buflen = cpu_to_le16(size);
933 /* return true if we just wrapped the ring */
934 return i == tx_ring->count;
937 static int __fm10k_maybe_stop_tx(struct fm10k_ring *tx_ring, u16 size)
939 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
941 /* Memory barrier before checking head and tail */
944 /* Check again in a case another CPU has just made room available */
945 if (likely(fm10k_desc_unused(tx_ring) < size))
948 /* A reprieve! - use start_queue because it doesn't call schedule */
949 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
950 ++tx_ring->tx_stats.restart_queue;
954 static inline int fm10k_maybe_stop_tx(struct fm10k_ring *tx_ring, u16 size)
956 if (likely(fm10k_desc_unused(tx_ring) >= size))
958 return __fm10k_maybe_stop_tx(tx_ring, size);
961 static void fm10k_tx_map(struct fm10k_ring *tx_ring,
962 struct fm10k_tx_buffer *first)
964 struct sk_buff *skb = first->skb;
965 struct fm10k_tx_buffer *tx_buffer;
966 struct fm10k_tx_desc *tx_desc;
967 struct skb_frag_struct *frag;
970 unsigned int data_len, size;
971 u32 tx_flags = first->tx_flags;
972 u16 i = tx_ring->next_to_use;
973 u8 flags = fm10k_tx_desc_flags(skb, tx_flags);
975 tx_desc = FM10K_TX_DESC(tx_ring, i);
977 /* add HW VLAN tag */
978 if (skb_vlan_tag_present(skb))
979 tx_desc->vlan = cpu_to_le16(skb_vlan_tag_get(skb));
983 size = skb_headlen(skb);
986 dma = dma_map_single(tx_ring->dev, data, size, DMA_TO_DEVICE);
988 data_len = skb->data_len;
991 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
992 if (dma_mapping_error(tx_ring->dev, dma))
995 /* record length, and DMA address */
996 dma_unmap_len_set(tx_buffer, len, size);
997 dma_unmap_addr_set(tx_buffer, dma, dma);
999 while (unlikely(size > FM10K_MAX_DATA_PER_TXD)) {
1000 if (fm10k_tx_desc_push(tx_ring, tx_desc++, i++, dma,
1001 FM10K_MAX_DATA_PER_TXD, flags)) {
1002 tx_desc = FM10K_TX_DESC(tx_ring, 0);
1006 dma += FM10K_MAX_DATA_PER_TXD;
1007 size -= FM10K_MAX_DATA_PER_TXD;
1010 if (likely(!data_len))
1013 if (fm10k_tx_desc_push(tx_ring, tx_desc++, i++,
1014 dma, size, flags)) {
1015 tx_desc = FM10K_TX_DESC(tx_ring, 0);
1019 size = skb_frag_size(frag);
1022 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1025 tx_buffer = &tx_ring->tx_buffer[i];
1028 /* write last descriptor with LAST bit set */
1029 flags |= FM10K_TXD_FLAG_LAST;
1031 if (fm10k_tx_desc_push(tx_ring, tx_desc, i++, dma, size, flags))
1034 /* record bytecount for BQL */
1035 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
1037 /* record SW timestamp if HW timestamp is not available */
1038 skb_tx_timestamp(first->skb);
1040 /* Force memory writes to complete before letting h/w know there
1041 * are new descriptors to fetch. (Only applicable for weak-ordered
1042 * memory model archs, such as IA-64).
1044 * We also need this memory barrier to make certain all of the
1045 * status bits have been updated before next_to_watch is written.
1049 /* set next_to_watch value indicating a packet is present */
1050 first->next_to_watch = tx_desc;
1052 tx_ring->next_to_use = i;
1054 /* Make sure there is space in the ring for the next send. */
1055 fm10k_maybe_stop_tx(tx_ring, DESC_NEEDED);
1057 /* notify HW of packet */
1058 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
1059 writel(i, tx_ring->tail);
1061 /* we need this if more than one processor can write to our tail
1062 * at a time, it synchronizes IO on IA64/Altix systems
1069 dev_err(tx_ring->dev, "TX DMA map failed\n");
1071 /* clear dma mappings for failed tx_buffer map */
1073 tx_buffer = &tx_ring->tx_buffer[i];
1074 fm10k_unmap_and_free_tx_resource(tx_ring, tx_buffer);
1075 if (tx_buffer == first)
1082 tx_ring->next_to_use = i;
1085 netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb,
1086 struct fm10k_ring *tx_ring)
1088 u16 count = TXD_USE_COUNT(skb_headlen(skb));
1089 struct fm10k_tx_buffer *first;
1094 /* need: 1 descriptor per page * PAGE_SIZE/FM10K_MAX_DATA_PER_TXD,
1095 * + 1 desc for skb_headlen/FM10K_MAX_DATA_PER_TXD,
1096 * + 2 desc gap to keep tail from touching head
1097 * otherwise try next time
1099 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1100 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1102 if (fm10k_maybe_stop_tx(tx_ring, count + 3)) {
1103 tx_ring->tx_stats.tx_busy++;
1104 return NETDEV_TX_BUSY;
1107 /* record the location of the first descriptor for this packet */
1108 first = &tx_ring->tx_buffer[tx_ring->next_to_use];
1110 first->bytecount = max_t(unsigned int, skb->len, ETH_ZLEN);
1111 first->gso_segs = 1;
1113 /* record initial flags and protocol */
1114 first->tx_flags = tx_flags;
1116 tso = fm10k_tso(tx_ring, first);
1120 fm10k_tx_csum(tx_ring, first);
1122 fm10k_tx_map(tx_ring, first);
1124 return NETDEV_TX_OK;
1127 dev_kfree_skb_any(first->skb);
1130 return NETDEV_TX_OK;
1133 static u64 fm10k_get_tx_completed(struct fm10k_ring *ring)
1135 return ring->stats.packets;
1139 * fm10k_get_tx_pending - how many Tx descriptors not processed
1140 * @ring: the ring structure
1141 * @in_sw: is tx_pending being checked in SW or in HW?
1143 u64 fm10k_get_tx_pending(struct fm10k_ring *ring, bool in_sw)
1145 struct fm10k_intfc *interface = ring->q_vector->interface;
1146 struct fm10k_hw *hw = &interface->hw;
1149 if (likely(in_sw)) {
1150 head = ring->next_to_clean;
1151 tail = ring->next_to_use;
1153 head = fm10k_read_reg(hw, FM10K_TDH(ring->reg_idx));
1154 tail = fm10k_read_reg(hw, FM10K_TDT(ring->reg_idx));
1157 return ((head <= tail) ? tail : tail + ring->count) - head;
1160 bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring)
1162 u32 tx_done = fm10k_get_tx_completed(tx_ring);
1163 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1164 u32 tx_pending = fm10k_get_tx_pending(tx_ring, true);
1166 clear_check_for_tx_hang(tx_ring);
1168 /* Check for a hung queue, but be thorough. This verifies
1169 * that a transmit has been completed since the previous
1170 * check AND there is at least one packet pending. By
1171 * requiring this to fail twice we avoid races with
1172 * clearing the ARMED bit and conditions where we
1173 * run the check_tx_hang logic with a transmit completion
1174 * pending but without time to complete it yet.
1176 if (!tx_pending || (tx_done_old != tx_done)) {
1177 /* update completed stats and continue */
1178 tx_ring->tx_stats.tx_done_old = tx_done;
1179 /* reset the countdown */
1180 clear_bit(__FM10K_HANG_CHECK_ARMED, tx_ring->state);
1185 /* make sure it is true for two checks in a row */
1186 return test_and_set_bit(__FM10K_HANG_CHECK_ARMED, tx_ring->state);
1190 * fm10k_tx_timeout_reset - initiate reset due to Tx timeout
1191 * @interface: driver private struct
1193 void fm10k_tx_timeout_reset(struct fm10k_intfc *interface)
1195 /* Do the reset outside of interrupt context */
1196 if (!test_bit(__FM10K_DOWN, interface->state)) {
1197 interface->tx_timeout_count++;
1198 set_bit(FM10K_FLAG_RESET_REQUESTED, interface->flags);
1199 fm10k_service_event_schedule(interface);
1204 * fm10k_clean_tx_irq - Reclaim resources after transmit completes
1205 * @q_vector: structure containing interrupt and ring information
1206 * @tx_ring: tx ring to clean
1207 * @napi_budget: Used to determine if we are in netpoll
1209 static bool fm10k_clean_tx_irq(struct fm10k_q_vector *q_vector,
1210 struct fm10k_ring *tx_ring, int napi_budget)
1212 struct fm10k_intfc *interface = q_vector->interface;
1213 struct fm10k_tx_buffer *tx_buffer;
1214 struct fm10k_tx_desc *tx_desc;
1215 unsigned int total_bytes = 0, total_packets = 0;
1216 unsigned int budget = q_vector->tx.work_limit;
1217 unsigned int i = tx_ring->next_to_clean;
1219 if (test_bit(__FM10K_DOWN, interface->state))
1222 tx_buffer = &tx_ring->tx_buffer[i];
1223 tx_desc = FM10K_TX_DESC(tx_ring, i);
1224 i -= tx_ring->count;
1227 struct fm10k_tx_desc *eop_desc = tx_buffer->next_to_watch;
1229 /* if next_to_watch is not set then there is no work pending */
1233 /* prevent any other reads prior to eop_desc */
1236 /* if DD is not set pending work has not been completed */
1237 if (!(eop_desc->flags & FM10K_TXD_FLAG_DONE))
1240 /* clear next_to_watch to prevent false hangs */
1241 tx_buffer->next_to_watch = NULL;
1243 /* update the statistics for this packet */
1244 total_bytes += tx_buffer->bytecount;
1245 total_packets += tx_buffer->gso_segs;
1248 napi_consume_skb(tx_buffer->skb, napi_budget);
1250 /* unmap skb header data */
1251 dma_unmap_single(tx_ring->dev,
1252 dma_unmap_addr(tx_buffer, dma),
1253 dma_unmap_len(tx_buffer, len),
1256 /* clear tx_buffer data */
1257 tx_buffer->skb = NULL;
1258 dma_unmap_len_set(tx_buffer, len, 0);
1260 /* unmap remaining buffers */
1261 while (tx_desc != eop_desc) {
1266 i -= tx_ring->count;
1267 tx_buffer = tx_ring->tx_buffer;
1268 tx_desc = FM10K_TX_DESC(tx_ring, 0);
1271 /* unmap any remaining paged data */
1272 if (dma_unmap_len(tx_buffer, len)) {
1273 dma_unmap_page(tx_ring->dev,
1274 dma_unmap_addr(tx_buffer, dma),
1275 dma_unmap_len(tx_buffer, len),
1277 dma_unmap_len_set(tx_buffer, len, 0);
1281 /* move us one more past the eop_desc for start of next pkt */
1286 i -= tx_ring->count;
1287 tx_buffer = tx_ring->tx_buffer;
1288 tx_desc = FM10K_TX_DESC(tx_ring, 0);
1291 /* issue prefetch for next Tx descriptor */
1294 /* update budget accounting */
1296 } while (likely(budget));
1298 i += tx_ring->count;
1299 tx_ring->next_to_clean = i;
1300 u64_stats_update_begin(&tx_ring->syncp);
1301 tx_ring->stats.bytes += total_bytes;
1302 tx_ring->stats.packets += total_packets;
1303 u64_stats_update_end(&tx_ring->syncp);
1304 q_vector->tx.total_bytes += total_bytes;
1305 q_vector->tx.total_packets += total_packets;
1307 if (check_for_tx_hang(tx_ring) && fm10k_check_tx_hang(tx_ring)) {
1308 /* schedule immediate reset if we believe we hung */
1309 struct fm10k_hw *hw = &interface->hw;
1311 netif_err(interface, drv, tx_ring->netdev,
1312 "Detected Tx Unit Hang\n"
1314 " TDH, TDT <%x>, <%x>\n"
1315 " next_to_use <%x>\n"
1316 " next_to_clean <%x>\n",
1317 tx_ring->queue_index,
1318 fm10k_read_reg(hw, FM10K_TDH(tx_ring->reg_idx)),
1319 fm10k_read_reg(hw, FM10K_TDT(tx_ring->reg_idx)),
1320 tx_ring->next_to_use, i);
1322 netif_stop_subqueue(tx_ring->netdev,
1323 tx_ring->queue_index);
1325 netif_info(interface, probe, tx_ring->netdev,
1326 "tx hang %d detected on queue %d, resetting interface\n",
1327 interface->tx_timeout_count + 1,
1328 tx_ring->queue_index);
1330 fm10k_tx_timeout_reset(interface);
1332 /* the netdev is about to reset, no point in enabling stuff */
1336 /* notify netdev of completed buffers */
1337 netdev_tx_completed_queue(txring_txq(tx_ring),
1338 total_packets, total_bytes);
1340 #define TX_WAKE_THRESHOLD min_t(u16, FM10K_MIN_TXD - 1, DESC_NEEDED * 2)
1341 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1342 (fm10k_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1343 /* Make sure that anybody stopping the queue after this
1344 * sees the new next_to_clean.
1347 if (__netif_subqueue_stopped(tx_ring->netdev,
1348 tx_ring->queue_index) &&
1349 !test_bit(__FM10K_DOWN, interface->state)) {
1350 netif_wake_subqueue(tx_ring->netdev,
1351 tx_ring->queue_index);
1352 ++tx_ring->tx_stats.restart_queue;
1360 * fm10k_update_itr - update the dynamic ITR value based on packet size
1362 * Stores a new ITR value based on strictly on packet size. The
1363 * divisors and thresholds used by this function were determined based
1364 * on theoretical maximum wire speed and testing data, in order to
1365 * minimize response time while increasing bulk throughput.
1367 * @ring_container: Container for rings to have ITR updated
1369 static void fm10k_update_itr(struct fm10k_ring_container *ring_container)
1371 unsigned int avg_wire_size, packets, itr_round;
1373 /* Only update ITR if we are using adaptive setting */
1374 if (!ITR_IS_ADAPTIVE(ring_container->itr))
1377 packets = ring_container->total_packets;
1381 avg_wire_size = ring_container->total_bytes / packets;
1383 /* The following is a crude approximation of:
1384 * wmem_default / (size + overhead) = desired_pkts_per_int
1385 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
1386 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
1388 * Assuming wmem_default is 212992 and overhead is 640 bytes per
1389 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
1392 * (34 * (size + 24)) / (size + 640) = ITR
1394 * We first do some math on the packet size and then finally bitshift
1395 * by 8 after rounding up. We also have to account for PCIe link speed
1396 * difference as ITR scales based on this.
1398 if (avg_wire_size <= 360) {
1399 /* Start at 250K ints/sec and gradually drop to 77K ints/sec */
1401 avg_wire_size += 376;
1402 } else if (avg_wire_size <= 1152) {
1403 /* 77K ints/sec to 45K ints/sec */
1405 avg_wire_size += 2176;
1406 } else if (avg_wire_size <= 1920) {
1407 /* 45K ints/sec to 38K ints/sec */
1408 avg_wire_size += 4480;
1410 /* plateau at a limit of 38K ints/sec */
1411 avg_wire_size = 6656;
1414 /* Perform final bitshift for division after rounding up to ensure
1415 * that the calculation will never get below a 1. The bit shift
1416 * accounts for changes in the ITR due to PCIe link speed.
1418 itr_round = READ_ONCE(ring_container->itr_scale) + 8;
1419 avg_wire_size += BIT(itr_round) - 1;
1420 avg_wire_size >>= itr_round;
1422 /* write back value and retain adaptive flag */
1423 ring_container->itr = avg_wire_size | FM10K_ITR_ADAPTIVE;
1426 ring_container->total_bytes = 0;
1427 ring_container->total_packets = 0;
1430 static void fm10k_qv_enable(struct fm10k_q_vector *q_vector)
1432 /* Enable auto-mask and clear the current mask */
1433 u32 itr = FM10K_ITR_ENABLE;
1436 fm10k_update_itr(&q_vector->tx);
1439 fm10k_update_itr(&q_vector->rx);
1441 /* Store Tx itr in timer slot 0 */
1442 itr |= (q_vector->tx.itr & FM10K_ITR_MAX);
1444 /* Shift Rx itr to timer slot 1 */
1445 itr |= (q_vector->rx.itr & FM10K_ITR_MAX) << FM10K_ITR_INTERVAL1_SHIFT;
1447 /* Write the final value to the ITR register */
1448 writel(itr, q_vector->itr);
1451 static int fm10k_poll(struct napi_struct *napi, int budget)
1453 struct fm10k_q_vector *q_vector =
1454 container_of(napi, struct fm10k_q_vector, napi);
1455 struct fm10k_ring *ring;
1456 int per_ring_budget, work_done = 0;
1457 bool clean_complete = true;
1459 fm10k_for_each_ring(ring, q_vector->tx) {
1460 if (!fm10k_clean_tx_irq(q_vector, ring, budget))
1461 clean_complete = false;
1464 /* Handle case where we are called by netpoll with a budget of 0 */
1468 /* attempt to distribute budget to each queue fairly, but don't
1469 * allow the budget to go below 1 because we'll exit polling
1471 if (q_vector->rx.count > 1)
1472 per_ring_budget = max(budget / q_vector->rx.count, 1);
1474 per_ring_budget = budget;
1476 fm10k_for_each_ring(ring, q_vector->rx) {
1477 int work = fm10k_clean_rx_irq(q_vector, ring, per_ring_budget);
1480 if (work >= per_ring_budget)
1481 clean_complete = false;
1484 /* If all work not completed, return budget and keep polling */
1485 if (!clean_complete)
1488 /* all work done, exit the polling mode */
1489 napi_complete_done(napi, work_done);
1491 /* re-enable the q_vector */
1492 fm10k_qv_enable(q_vector);
1494 return min(work_done, budget - 1);
1498 * fm10k_set_qos_queues: Allocate queues for a QOS-enabled device
1499 * @interface: board private structure to initialize
1501 * When QoS (Quality of Service) is enabled, allocate queues for
1502 * each traffic class. If multiqueue isn't available,then abort QoS
1505 * This function handles all combinations of Qos and RSS.
1508 static bool fm10k_set_qos_queues(struct fm10k_intfc *interface)
1510 struct net_device *dev = interface->netdev;
1511 struct fm10k_ring_feature *f;
1515 /* Map queue offset and counts onto allocated tx queues */
1516 pcs = netdev_get_num_tc(dev);
1521 /* set QoS mask and indices */
1522 f = &interface->ring_feature[RING_F_QOS];
1524 f->mask = BIT(fls(pcs - 1)) - 1;
1526 /* determine the upper limit for our current DCB mode */
1527 rss_i = interface->hw.mac.max_queues / pcs;
1528 rss_i = BIT(fls(rss_i) - 1);
1530 /* set RSS mask and indices */
1531 f = &interface->ring_feature[RING_F_RSS];
1532 rss_i = min_t(u16, rss_i, f->limit);
1534 f->mask = BIT(fls(rss_i - 1)) - 1;
1536 /* configure pause class to queue mapping */
1537 for (i = 0; i < pcs; i++)
1538 netdev_set_tc_queue(dev, i, rss_i, rss_i * i);
1540 interface->num_rx_queues = rss_i * pcs;
1541 interface->num_tx_queues = rss_i * pcs;
1547 * fm10k_set_rss_queues: Allocate queues for RSS
1548 * @interface: board private structure to initialize
1550 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
1551 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
1554 static bool fm10k_set_rss_queues(struct fm10k_intfc *interface)
1556 struct fm10k_ring_feature *f;
1559 f = &interface->ring_feature[RING_F_RSS];
1560 rss_i = min_t(u16, interface->hw.mac.max_queues, f->limit);
1562 /* record indices and power of 2 mask for RSS */
1564 f->mask = BIT(fls(rss_i - 1)) - 1;
1566 interface->num_rx_queues = rss_i;
1567 interface->num_tx_queues = rss_i;
1573 * fm10k_set_num_queues: Allocate queues for device, feature dependent
1574 * @interface: board private structure to initialize
1576 * This is the top level queue allocation routine. The order here is very
1577 * important, starting with the "most" number of features turned on at once,
1578 * and ending with the smallest set of features. This way large combinations
1579 * can be allocated if they're turned on, and smaller combinations are the
1580 * fallthrough conditions.
1583 static void fm10k_set_num_queues(struct fm10k_intfc *interface)
1585 /* Attempt to setup QoS and RSS first */
1586 if (fm10k_set_qos_queues(interface))
1589 /* If we don't have QoS, just fallback to only RSS. */
1590 fm10k_set_rss_queues(interface);
1594 * fm10k_reset_num_queues - Reset the number of queues to zero
1595 * @interface: board private structure
1597 * This function should be called whenever we need to reset the number of
1598 * queues after an error condition.
1600 static void fm10k_reset_num_queues(struct fm10k_intfc *interface)
1602 interface->num_tx_queues = 0;
1603 interface->num_rx_queues = 0;
1604 interface->num_q_vectors = 0;
1608 * fm10k_alloc_q_vector - Allocate memory for a single interrupt vector
1609 * @interface: board private structure to initialize
1610 * @v_count: q_vectors allocated on interface, used for ring interleaving
1611 * @v_idx: index of vector in interface struct
1612 * @txr_count: total number of Tx rings to allocate
1613 * @txr_idx: index of first Tx ring to allocate
1614 * @rxr_count: total number of Rx rings to allocate
1615 * @rxr_idx: index of first Rx ring to allocate
1617 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1619 static int fm10k_alloc_q_vector(struct fm10k_intfc *interface,
1620 unsigned int v_count, unsigned int v_idx,
1621 unsigned int txr_count, unsigned int txr_idx,
1622 unsigned int rxr_count, unsigned int rxr_idx)
1624 struct fm10k_q_vector *q_vector;
1625 struct fm10k_ring *ring;
1626 int ring_count, size;
1628 ring_count = txr_count + rxr_count;
1629 size = sizeof(struct fm10k_q_vector) +
1630 (sizeof(struct fm10k_ring) * ring_count);
1632 /* allocate q_vector and rings */
1633 q_vector = kzalloc(size, GFP_KERNEL);
1637 /* initialize NAPI */
1638 netif_napi_add(interface->netdev, &q_vector->napi,
1639 fm10k_poll, NAPI_POLL_WEIGHT);
1641 /* tie q_vector and interface together */
1642 interface->q_vector[v_idx] = q_vector;
1643 q_vector->interface = interface;
1644 q_vector->v_idx = v_idx;
1646 /* initialize pointer to rings */
1647 ring = q_vector->ring;
1649 /* save Tx ring container info */
1650 q_vector->tx.ring = ring;
1651 q_vector->tx.work_limit = FM10K_DEFAULT_TX_WORK;
1652 q_vector->tx.itr = interface->tx_itr;
1653 q_vector->tx.itr_scale = interface->hw.mac.itr_scale;
1654 q_vector->tx.count = txr_count;
1657 /* assign generic ring traits */
1658 ring->dev = &interface->pdev->dev;
1659 ring->netdev = interface->netdev;
1661 /* configure backlink on ring */
1662 ring->q_vector = q_vector;
1664 /* apply Tx specific ring traits */
1665 ring->count = interface->tx_ring_count;
1666 ring->queue_index = txr_idx;
1668 /* assign ring to interface */
1669 interface->tx_ring[txr_idx] = ring;
1671 /* update count and index */
1675 /* push pointer to next ring */
1679 /* save Rx ring container info */
1680 q_vector->rx.ring = ring;
1681 q_vector->rx.itr = interface->rx_itr;
1682 q_vector->rx.itr_scale = interface->hw.mac.itr_scale;
1683 q_vector->rx.count = rxr_count;
1686 /* assign generic ring traits */
1687 ring->dev = &interface->pdev->dev;
1688 ring->netdev = interface->netdev;
1689 rcu_assign_pointer(ring->l2_accel, interface->l2_accel);
1691 /* configure backlink on ring */
1692 ring->q_vector = q_vector;
1694 /* apply Rx specific ring traits */
1695 ring->count = interface->rx_ring_count;
1696 ring->queue_index = rxr_idx;
1698 /* assign ring to interface */
1699 interface->rx_ring[rxr_idx] = ring;
1701 /* update count and index */
1705 /* push pointer to next ring */
1709 fm10k_dbg_q_vector_init(q_vector);
1715 * fm10k_free_q_vector - Free memory allocated for specific interrupt vector
1716 * @interface: board private structure to initialize
1717 * @v_idx: Index of vector to be freed
1719 * This function frees the memory allocated to the q_vector. In addition if
1720 * NAPI is enabled it will delete any references to the NAPI struct prior
1721 * to freeing the q_vector.
1723 static void fm10k_free_q_vector(struct fm10k_intfc *interface, int v_idx)
1725 struct fm10k_q_vector *q_vector = interface->q_vector[v_idx];
1726 struct fm10k_ring *ring;
1728 fm10k_dbg_q_vector_exit(q_vector);
1730 fm10k_for_each_ring(ring, q_vector->tx)
1731 interface->tx_ring[ring->queue_index] = NULL;
1733 fm10k_for_each_ring(ring, q_vector->rx)
1734 interface->rx_ring[ring->queue_index] = NULL;
1736 interface->q_vector[v_idx] = NULL;
1737 netif_napi_del(&q_vector->napi);
1738 kfree_rcu(q_vector, rcu);
1742 * fm10k_alloc_q_vectors - Allocate memory for interrupt vectors
1743 * @interface: board private structure to initialize
1745 * We allocate one q_vector per queue interrupt. If allocation fails we
1748 static int fm10k_alloc_q_vectors(struct fm10k_intfc *interface)
1750 unsigned int q_vectors = interface->num_q_vectors;
1751 unsigned int rxr_remaining = interface->num_rx_queues;
1752 unsigned int txr_remaining = interface->num_tx_queues;
1753 unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1756 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1757 for (; rxr_remaining; v_idx++) {
1758 err = fm10k_alloc_q_vector(interface, q_vectors, v_idx,
1763 /* update counts and index */
1769 for (; v_idx < q_vectors; v_idx++) {
1770 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1771 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1773 err = fm10k_alloc_q_vector(interface, q_vectors, v_idx,
1780 /* update counts and index */
1781 rxr_remaining -= rqpv;
1782 txr_remaining -= tqpv;
1790 fm10k_reset_num_queues(interface);
1793 fm10k_free_q_vector(interface, v_idx);
1799 * fm10k_free_q_vectors - Free memory allocated for interrupt vectors
1800 * @interface: board private structure to initialize
1802 * This function frees the memory allocated to the q_vectors. In addition if
1803 * NAPI is enabled it will delete any references to the NAPI struct prior
1804 * to freeing the q_vector.
1806 static void fm10k_free_q_vectors(struct fm10k_intfc *interface)
1808 int v_idx = interface->num_q_vectors;
1810 fm10k_reset_num_queues(interface);
1813 fm10k_free_q_vector(interface, v_idx);
1817 * f10k_reset_msix_capability - reset MSI-X capability
1818 * @interface: board private structure to initialize
1820 * Reset the MSI-X capability back to its starting state
1822 static void fm10k_reset_msix_capability(struct fm10k_intfc *interface)
1824 pci_disable_msix(interface->pdev);
1825 kfree(interface->msix_entries);
1826 interface->msix_entries = NULL;
1830 * f10k_init_msix_capability - configure MSI-X capability
1831 * @interface: board private structure to initialize
1833 * Attempt to configure the interrupts using the best available
1834 * capabilities of the hardware and the kernel.
1836 static int fm10k_init_msix_capability(struct fm10k_intfc *interface)
1838 struct fm10k_hw *hw = &interface->hw;
1839 int v_budget, vector;
1841 /* It's easy to be greedy for MSI-X vectors, but it really
1842 * doesn't do us much good if we have a lot more vectors
1843 * than CPU's. So let's be conservative and only ask for
1844 * (roughly) the same number of vectors as there are CPU's.
1845 * the default is to use pairs of vectors
1847 v_budget = max(interface->num_rx_queues, interface->num_tx_queues);
1848 v_budget = min_t(u16, v_budget, num_online_cpus());
1850 /* account for vectors not related to queues */
1851 v_budget += NON_Q_VECTORS(hw);
1853 /* At the same time, hardware can only support a maximum of
1854 * hw.mac->max_msix_vectors vectors. With features
1855 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
1856 * descriptor queues supported by our device. Thus, we cap it off in
1857 * those rare cases where the cpu count also exceeds our vector limit.
1859 v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors);
1861 /* A failure in MSI-X entry allocation is fatal. */
1862 interface->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
1864 if (!interface->msix_entries)
1867 /* populate entry values */
1868 for (vector = 0; vector < v_budget; vector++)
1869 interface->msix_entries[vector].entry = vector;
1871 /* Attempt to enable MSI-X with requested value */
1872 v_budget = pci_enable_msix_range(interface->pdev,
1873 interface->msix_entries,
1877 kfree(interface->msix_entries);
1878 interface->msix_entries = NULL;
1882 /* record the number of queues available for q_vectors */
1883 interface->num_q_vectors = v_budget - NON_Q_VECTORS(hw);
1889 * fm10k_cache_ring_qos - Descriptor ring to register mapping for QoS
1890 * @interface: Interface structure continaining rings and devices
1892 * Cache the descriptor ring offsets for Qos
1894 static bool fm10k_cache_ring_qos(struct fm10k_intfc *interface)
1896 struct net_device *dev = interface->netdev;
1897 int pc, offset, rss_i, i, q_idx;
1898 u16 pc_stride = interface->ring_feature[RING_F_QOS].mask + 1;
1899 u8 num_pcs = netdev_get_num_tc(dev);
1904 rss_i = interface->ring_feature[RING_F_RSS].indices;
1906 for (pc = 0, offset = 0; pc < num_pcs; pc++, offset += rss_i) {
1908 for (i = 0; i < rss_i; i++) {
1909 interface->tx_ring[offset + i]->reg_idx = q_idx;
1910 interface->tx_ring[offset + i]->qos_pc = pc;
1911 interface->rx_ring[offset + i]->reg_idx = q_idx;
1912 interface->rx_ring[offset + i]->qos_pc = pc;
1921 * fm10k_cache_ring_rss - Descriptor ring to register mapping for RSS
1922 * @interface: Interface structure continaining rings and devices
1924 * Cache the descriptor ring offsets for RSS
1926 static void fm10k_cache_ring_rss(struct fm10k_intfc *interface)
1930 for (i = 0; i < interface->num_rx_queues; i++)
1931 interface->rx_ring[i]->reg_idx = i;
1933 for (i = 0; i < interface->num_tx_queues; i++)
1934 interface->tx_ring[i]->reg_idx = i;
1938 * fm10k_assign_rings - Map rings to network devices
1939 * @interface: Interface structure containing rings and devices
1941 * This function is meant to go though and configure both the network
1942 * devices so that they contain rings, and configure the rings so that
1943 * they function with their network devices.
1945 static void fm10k_assign_rings(struct fm10k_intfc *interface)
1947 if (fm10k_cache_ring_qos(interface))
1950 fm10k_cache_ring_rss(interface);
1953 static void fm10k_init_reta(struct fm10k_intfc *interface)
1955 u16 i, rss_i = interface->ring_feature[RING_F_RSS].indices;
1958 /* If the Rx flow indirection table has been configured manually, we
1959 * need to maintain it when possible.
1961 if (netif_is_rxfh_configured(interface->netdev)) {
1962 for (i = FM10K_RETA_SIZE; i--;) {
1963 reta = interface->reta[i];
1964 if ((((reta << 24) >> 24) < rss_i) &&
1965 (((reta << 16) >> 24) < rss_i) &&
1966 (((reta << 8) >> 24) < rss_i) &&
1967 (((reta) >> 24) < rss_i))
1970 /* this should never happen */
1971 dev_err(&interface->pdev->dev,
1972 "RSS indirection table assigned flows out of queue bounds. Reconfiguring.\n");
1973 goto repopulate_reta;
1976 /* do nothing if all of the elements are in bounds */
1981 fm10k_write_reta(interface, NULL);
1985 * fm10k_init_queueing_scheme - Determine proper queueing scheme
1986 * @interface: board private structure to initialize
1988 * We determine which queueing scheme to use based on...
1989 * - Hardware queue count (num_*_queues)
1990 * - defined by miscellaneous hardware support/features (RSS, etc.)
1992 int fm10k_init_queueing_scheme(struct fm10k_intfc *interface)
1996 /* Number of supported queues */
1997 fm10k_set_num_queues(interface);
1999 /* Configure MSI-X capability */
2000 err = fm10k_init_msix_capability(interface);
2002 dev_err(&interface->pdev->dev,
2003 "Unable to initialize MSI-X capability\n");
2007 /* Allocate memory for queues */
2008 err = fm10k_alloc_q_vectors(interface);
2010 dev_err(&interface->pdev->dev,
2011 "Unable to allocate queue vectors\n");
2012 goto err_alloc_q_vectors;
2015 /* Map rings to devices, and map devices to physical queues */
2016 fm10k_assign_rings(interface);
2018 /* Initialize RSS redirection table */
2019 fm10k_init_reta(interface);
2023 err_alloc_q_vectors:
2024 fm10k_reset_msix_capability(interface);
2026 fm10k_reset_num_queues(interface);
2031 * fm10k_clear_queueing_scheme - Clear the current queueing scheme settings
2032 * @interface: board private structure to clear queueing scheme on
2034 * We go through and clear queueing specific resources and reset the structure
2035 * to pre-load conditions
2037 void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface)
2039 fm10k_free_q_vectors(interface);
2040 fm10k_reset_msix_capability(interface);