1 /* Intel Ethernet Switch Host Interface Driver
2 * Copyright(c) 2013 - 2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
16 * Contact Information:
17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21 #include "fm10k_common.h"
24 * fm10k_get_bus_info_generic - Generic set PCI bus info
25 * @hw: pointer to hardware structure
27 * Gets the PCI bus info (speed, width, type) then calls helper function to
28 * store this data within the fm10k_hw structure.
30 s32 fm10k_get_bus_info_generic(struct fm10k_hw *hw)
32 u16 link_cap, link_status, device_cap, device_control;
34 /* Get the maximum link width and speed from PCIe config space */
35 link_cap = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_LINK_CAP);
37 switch (link_cap & FM10K_PCIE_LINK_WIDTH) {
38 case FM10K_PCIE_LINK_WIDTH_1:
39 hw->bus_caps.width = fm10k_bus_width_pcie_x1;
41 case FM10K_PCIE_LINK_WIDTH_2:
42 hw->bus_caps.width = fm10k_bus_width_pcie_x2;
44 case FM10K_PCIE_LINK_WIDTH_4:
45 hw->bus_caps.width = fm10k_bus_width_pcie_x4;
47 case FM10K_PCIE_LINK_WIDTH_8:
48 hw->bus_caps.width = fm10k_bus_width_pcie_x8;
51 hw->bus_caps.width = fm10k_bus_width_unknown;
55 switch (link_cap & FM10K_PCIE_LINK_SPEED) {
56 case FM10K_PCIE_LINK_SPEED_2500:
57 hw->bus_caps.speed = fm10k_bus_speed_2500;
59 case FM10K_PCIE_LINK_SPEED_5000:
60 hw->bus_caps.speed = fm10k_bus_speed_5000;
62 case FM10K_PCIE_LINK_SPEED_8000:
63 hw->bus_caps.speed = fm10k_bus_speed_8000;
66 hw->bus_caps.speed = fm10k_bus_speed_unknown;
70 /* Get the PCIe maximum payload size for the PCIe function */
71 device_cap = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_DEV_CAP);
73 switch (device_cap & FM10K_PCIE_DEV_CAP_PAYLOAD) {
74 case FM10K_PCIE_DEV_CAP_PAYLOAD_128:
75 hw->bus_caps.payload = fm10k_bus_payload_128;
77 case FM10K_PCIE_DEV_CAP_PAYLOAD_256:
78 hw->bus_caps.payload = fm10k_bus_payload_256;
80 case FM10K_PCIE_DEV_CAP_PAYLOAD_512:
81 hw->bus_caps.payload = fm10k_bus_payload_512;
84 hw->bus_caps.payload = fm10k_bus_payload_unknown;
88 /* Get the negotiated link width and speed from PCIe config space */
89 link_status = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_LINK_STATUS);
91 switch (link_status & FM10K_PCIE_LINK_WIDTH) {
92 case FM10K_PCIE_LINK_WIDTH_1:
93 hw->bus.width = fm10k_bus_width_pcie_x1;
95 case FM10K_PCIE_LINK_WIDTH_2:
96 hw->bus.width = fm10k_bus_width_pcie_x2;
98 case FM10K_PCIE_LINK_WIDTH_4:
99 hw->bus.width = fm10k_bus_width_pcie_x4;
101 case FM10K_PCIE_LINK_WIDTH_8:
102 hw->bus.width = fm10k_bus_width_pcie_x8;
105 hw->bus.width = fm10k_bus_width_unknown;
109 switch (link_status & FM10K_PCIE_LINK_SPEED) {
110 case FM10K_PCIE_LINK_SPEED_2500:
111 hw->bus.speed = fm10k_bus_speed_2500;
113 case FM10K_PCIE_LINK_SPEED_5000:
114 hw->bus.speed = fm10k_bus_speed_5000;
116 case FM10K_PCIE_LINK_SPEED_8000:
117 hw->bus.speed = fm10k_bus_speed_8000;
120 hw->bus.speed = fm10k_bus_speed_unknown;
124 /* Get the negotiated PCIe maximum payload size for the PCIe function */
125 device_control = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_DEV_CTRL);
127 switch (device_control & FM10K_PCIE_DEV_CTRL_PAYLOAD) {
128 case FM10K_PCIE_DEV_CTRL_PAYLOAD_128:
129 hw->bus.payload = fm10k_bus_payload_128;
131 case FM10K_PCIE_DEV_CTRL_PAYLOAD_256:
132 hw->bus.payload = fm10k_bus_payload_256;
134 case FM10K_PCIE_DEV_CTRL_PAYLOAD_512:
135 hw->bus.payload = fm10k_bus_payload_512;
138 hw->bus.payload = fm10k_bus_payload_unknown;
145 static u16 fm10k_get_pcie_msix_count_generic(struct fm10k_hw *hw)
149 /* read in value from MSI-X capability register */
150 msix_count = fm10k_read_pci_cfg_word(hw, FM10K_PCI_MSIX_MSG_CTRL);
151 msix_count &= FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK;
153 /* MSI-X count is zero-based in HW */
156 if (msix_count > FM10K_MAX_MSIX_VECTORS)
157 msix_count = FM10K_MAX_MSIX_VECTORS;
163 * fm10k_get_invariants_generic - Inits constant values
164 * @hw: pointer to the hardware structure
166 * Initialize the common invariants for the device.
168 s32 fm10k_get_invariants_generic(struct fm10k_hw *hw)
170 struct fm10k_mac_info *mac = &hw->mac;
172 /* initialize GLORT state to avoid any false hits */
173 mac->dglort_map = FM10K_DGLORTMAP_NONE;
175 /* record maximum number of MSI-X vectors */
176 mac->max_msix_vectors = fm10k_get_pcie_msix_count_generic(hw);
182 * fm10k_start_hw_generic - Prepare hardware for Tx/Rx
183 * @hw: pointer to hardware structure
185 * This function sets the Tx ready flag to indicate that the Tx path has
188 s32 fm10k_start_hw_generic(struct fm10k_hw *hw)
190 /* set flag indicating we are beginning Tx */
191 hw->mac.tx_ready = true;
197 * fm10k_disable_queues_generic - Stop Tx/Rx queues
198 * @hw: pointer to hardware structure
199 * @q_cnt: number of queues to be disabled
202 s32 fm10k_disable_queues_generic(struct fm10k_hw *hw, u16 q_cnt)
207 /* clear tx_ready to prevent any false hits for reset */
208 hw->mac.tx_ready = false;
210 /* clear the enable bit for all rings */
211 for (i = 0; i < q_cnt; i++) {
212 reg = fm10k_read_reg(hw, FM10K_TXDCTL(i));
213 fm10k_write_reg(hw, FM10K_TXDCTL(i),
214 reg & ~FM10K_TXDCTL_ENABLE);
215 reg = fm10k_read_reg(hw, FM10K_RXQCTL(i));
216 fm10k_write_reg(hw, FM10K_RXQCTL(i),
217 reg & ~FM10K_RXQCTL_ENABLE);
220 fm10k_write_flush(hw);
223 /* loop through all queues to verify that they are all disabled */
224 for (i = 0, time = FM10K_QUEUE_DISABLE_TIMEOUT; time;) {
225 /* if we are at end of rings all rings are disabled */
229 /* if queue enables cleared, then move to next ring pair */
230 reg = fm10k_read_reg(hw, FM10K_TXDCTL(i));
231 if (!~reg || !(reg & FM10K_TXDCTL_ENABLE)) {
232 reg = fm10k_read_reg(hw, FM10K_RXQCTL(i));
233 if (!~reg || !(reg & FM10K_RXQCTL_ENABLE)) {
239 /* decrement time and wait 1 usec */
245 return FM10K_ERR_REQUESTS_PENDING;
249 * fm10k_stop_hw_generic - Stop Tx/Rx units
250 * @hw: pointer to hardware structure
253 s32 fm10k_stop_hw_generic(struct fm10k_hw *hw)
255 return fm10k_disable_queues_generic(hw, hw->mac.max_queues);
259 * fm10k_read_hw_stats_32b - Reads value of 32-bit registers
260 * @hw: pointer to the hardware structure
261 * @addr: address of register containing a 32-bit value
263 * Function reads the content of the register and returns the delta
264 * between the base and the current value.
266 u32 fm10k_read_hw_stats_32b(struct fm10k_hw *hw, u32 addr,
267 struct fm10k_hw_stat *stat)
269 u32 delta = fm10k_read_reg(hw, addr) - stat->base_l;
271 if (FM10K_REMOVED(hw->hw_addr))
278 * fm10k_read_hw_stats_48b - Reads value of 48-bit registers
279 * @hw: pointer to the hardware structure
280 * @addr: address of register containing the lower 32-bit value
282 * Function reads the content of 2 registers, combined to represent a 48-bit
283 * statistical value. Extra processing is required to handle overflowing.
284 * Finally, a delta value is returned representing the difference between the
285 * values stored in registers and values stored in the statistic counters.
287 static u64 fm10k_read_hw_stats_48b(struct fm10k_hw *hw, u32 addr,
288 struct fm10k_hw_stat *stat)
295 count_h = fm10k_read_reg(hw, addr + 1);
297 /* Check for overflow */
300 count_l = fm10k_read_reg(hw, addr);
301 count_h = fm10k_read_reg(hw, addr + 1);
302 } while (count_h != count_tmp);
304 delta = ((u64)(count_h - stat->base_h) << 32) + count_l;
305 delta -= stat->base_l;
307 return delta & FM10K_48_BIT_MASK;
311 * fm10k_update_hw_base_48b - Updates 48-bit statistic base value
312 * @stat: pointer to the hardware statistic structure
313 * @delta: value to be updated into the hardware statistic structure
315 * Function receives a value and determines if an update is required based on
316 * a delta calculation. Only the base value will be updated.
318 static void fm10k_update_hw_base_48b(struct fm10k_hw_stat *stat, u64 delta)
323 /* update lower 32 bits */
324 delta += stat->base_l;
325 stat->base_l = (u32)delta;
327 /* update upper 32 bits */
328 stat->base_h += (u32)(delta >> 32);
332 * fm10k_update_hw_stats_tx_q - Updates TX queue statistics counters
333 * @hw: pointer to the hardware structure
334 * @q: pointer to the ring of hardware statistics queue
335 * @idx: index pointing to the start of the ring iteration
337 * Function updates the TX queue statistics counters that are related to the
340 static void fm10k_update_hw_stats_tx_q(struct fm10k_hw *hw,
341 struct fm10k_hw_stats_q *q,
344 u32 id_tx, id_tx_prev, tx_packets;
347 /* Retrieve TX Owner Data */
348 id_tx = fm10k_read_reg(hw, FM10K_TXQCTL(idx));
350 /* Process TX Ring */
352 tx_packets = fm10k_read_hw_stats_32b(hw, FM10K_QPTC(idx),
356 tx_bytes = fm10k_read_hw_stats_48b(hw,
360 /* Re-Check Owner Data */
362 id_tx = fm10k_read_reg(hw, FM10K_TXQCTL(idx));
363 } while ((id_tx ^ id_tx_prev) & FM10K_TXQCTL_ID_MASK);
365 /* drop non-ID bits and set VALID ID bit */
366 id_tx &= FM10K_TXQCTL_ID_MASK;
367 id_tx |= FM10K_STAT_VALID;
369 /* update packet counts */
370 if (q->tx_stats_idx == id_tx) {
371 q->tx_packets.count += tx_packets;
372 q->tx_bytes.count += tx_bytes;
375 /* update bases and record ID */
376 fm10k_update_hw_base_32b(&q->tx_packets, tx_packets);
377 fm10k_update_hw_base_48b(&q->tx_bytes, tx_bytes);
379 q->tx_stats_idx = id_tx;
383 * fm10k_update_hw_stats_rx_q - Updates RX queue statistics counters
384 * @hw: pointer to the hardware structure
385 * @q: pointer to the ring of hardware statistics queue
386 * @idx: index pointing to the start of the ring iteration
388 * Function updates the RX queue statistics counters that are related to the
391 static void fm10k_update_hw_stats_rx_q(struct fm10k_hw *hw,
392 struct fm10k_hw_stats_q *q,
395 u32 id_rx, id_rx_prev, rx_packets, rx_drops;
398 /* Retrieve RX Owner Data */
399 id_rx = fm10k_read_reg(hw, FM10K_RXQCTL(idx));
401 /* Process RX Ring */
403 rx_drops = fm10k_read_hw_stats_32b(hw, FM10K_QPRDC(idx),
406 rx_packets = fm10k_read_hw_stats_32b(hw, FM10K_QPRC(idx),
410 rx_bytes = fm10k_read_hw_stats_48b(hw,
414 /* Re-Check Owner Data */
416 id_rx = fm10k_read_reg(hw, FM10K_RXQCTL(idx));
417 } while ((id_rx ^ id_rx_prev) & FM10K_RXQCTL_ID_MASK);
419 /* drop non-ID bits and set VALID ID bit */
420 id_rx &= FM10K_RXQCTL_ID_MASK;
421 id_rx |= FM10K_STAT_VALID;
423 /* update packet counts */
424 if (q->rx_stats_idx == id_rx) {
425 q->rx_drops.count += rx_drops;
426 q->rx_packets.count += rx_packets;
427 q->rx_bytes.count += rx_bytes;
430 /* update bases and record ID */
431 fm10k_update_hw_base_32b(&q->rx_drops, rx_drops);
432 fm10k_update_hw_base_32b(&q->rx_packets, rx_packets);
433 fm10k_update_hw_base_48b(&q->rx_bytes, rx_bytes);
435 q->rx_stats_idx = id_rx;
439 * fm10k_update_hw_stats_q - Updates queue statistics counters
440 * @hw: pointer to the hardware structure
441 * @q: pointer to the ring of hardware statistics queue
442 * @idx: index pointing to the start of the ring iteration
443 * @count: number of queues to iterate over
445 * Function updates the queue statistics counters that are related to the
448 void fm10k_update_hw_stats_q(struct fm10k_hw *hw, struct fm10k_hw_stats_q *q,
453 for (i = 0; i < count; i++, idx++, q++) {
454 fm10k_update_hw_stats_tx_q(hw, q, idx);
455 fm10k_update_hw_stats_rx_q(hw, q, idx);
460 * fm10k_unbind_hw_stats_q - Unbind the queue counters from their queues
461 * @hw: pointer to the hardware structure
462 * @q: pointer to the ring of hardware statistics queue
463 * @idx: index pointing to the start of the ring iteration
464 * @count: number of queues to iterate over
466 * Function invalidates the index values for the queues so any updates that
467 * may have happened are ignored and the base for the queue stats is reset.
469 void fm10k_unbind_hw_stats_q(struct fm10k_hw_stats_q *q, u32 idx, u32 count)
473 for (i = 0; i < count; i++, idx++, q++) {
480 * fm10k_get_host_state_generic - Returns the state of the host
481 * @hw: pointer to hardware structure
482 * @host_ready: pointer to boolean value that will record host state
484 * This function will check the health of the mailbox and Tx queue 0
485 * in order to determine if we should report that the link is up or not.
487 s32 fm10k_get_host_state_generic(struct fm10k_hw *hw, bool *host_ready)
489 struct fm10k_mbx_info *mbx = &hw->mbx;
490 struct fm10k_mac_info *mac = &hw->mac;
492 u32 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(0));
494 /* process upstream mailbox in case interrupts were disabled */
495 mbx->ops.process(hw, mbx);
497 /* If Tx is no longer enabled link should come down */
498 if (!(~txdctl) || !(txdctl & FM10K_TXDCTL_ENABLE))
499 mac->get_host_state = true;
501 /* exit if not checking for link, or link cannot be changed */
502 if (!mac->get_host_state || !(~txdctl))
505 /* if we somehow dropped the Tx enable we should reset */
506 if (hw->mac.tx_ready && !(txdctl & FM10K_TXDCTL_ENABLE)) {
507 ret_val = FM10K_ERR_RESET_REQUESTED;
511 /* if Mailbox timed out we should request reset */
513 ret_val = FM10K_ERR_RESET_REQUESTED;
517 /* verify Mailbox is still valid */
518 if (!mbx->ops.tx_ready(mbx, FM10K_VFMBX_MSG_MTU))
521 /* interface cannot receive traffic without logical ports */
522 if (mac->dglort_map == FM10K_DGLORTMAP_NONE)
525 /* if we passed all the tests above then the switch is ready and we no
526 * longer need to check for link
528 mac->get_host_state = false;
531 *host_ready = !mac->get_host_state;