drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4 /* 82562G 10/100 Network Connection
   5  * 82562G-2 10/100 Network Connection
   6  * 82562GT 10/100 Network Connection
   7  * 82562GT-2 10/100 Network Connection
   8  * 82562V 10/100 Network Connection
   9  * 82562V-2 10/100 Network Connection
  10  * 82566DC-2 Gigabit Network Connection
  11  * 82566DC Gigabit Network Connection
  12  * 82566DM-2 Gigabit Network Connection
  13  * 82566DM Gigabit Network Connection
  14  * 82566MC Gigabit Network Connection
  15  * 82566MM Gigabit Network Connection
  16  * 82567LM Gigabit Network Connection
  17  * 82567LF Gigabit Network Connection
  18  * 82567V Gigabit Network Connection
  19  * 82567LM-2 Gigabit Network Connection
  20  * 82567LF-2 Gigabit Network Connection
  21  * 82567V-2 Gigabit Network Connection
  22  * 82567LF-3 Gigabit Network Connection
  23  * 82567LM-3 Gigabit Network Connection
  24  * 82567LM-4 Gigabit Network Connection
  25  * 82577LM Gigabit Network Connection
  26  * 82577LC Gigabit Network Connection
  27  * 82578DM Gigabit Network Connection
  28  * 82578DC Gigabit Network Connection
  29  * 82579LM Gigabit Network Connection
  30  * 82579V Gigabit Network Connection
  31  * Ethernet Connection I217-LM
  32  * Ethernet Connection I217-V
  33  * Ethernet Connection I218-V
  34  * Ethernet Connection I218-LM
  35  * Ethernet Connection (2) I218-LM
  36  * Ethernet Connection (2) I218-V
  37  * Ethernet Connection (3) I218-LM
  38  * Ethernet Connection (3) I218-V
  39  */
  40
  41 #include "e1000.h"
  42
  43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  44 /* Offset 04h HSFSTS */
  45 union ich8_hws_flash_status {
  46         struct ich8_hsfsts {
  47                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  48                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  49                 u16 dael:1;     /* bit 2 Direct Access error Log */
  50                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  51                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  52                 u16 reserved1:2;        /* bit 13:6 Reserved */
  53                 u16 reserved2:6;        /* bit 13:6 Reserved */
  54                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  55                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  56         } hsf_status;
  57         u16 regval;
  58 };
  59
  60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  61 /* Offset 06h FLCTL */
  62 union ich8_hws_flash_ctrl {
  63         struct ich8_hsflctl {
  64                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  65                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  66                 u16 reserved:5; /* 7:3 Reserved  */
  67                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  68                 u16 flockdn:6;  /* 15:10 Reserved */
  69         } hsf_ctrl;
  70         u16 regval;
  71 };
  72
  73 /* ICH Flash Region Access Permissions */
  74 union ich8_hws_flash_regacc {
  75         struct ich8_flracc {
  76                 u32 grra:8;     /* 0:7 GbE region Read Access */
  77                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  78                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  79                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  80         } hsf_flregacc;
  81         u16 regval;
  82 };
  83
  84 /* ICH Flash Protected Region */
  85 union ich8_flash_protected_range {
  86         struct ich8_pr {
  87                 u32 base:13;    /* 0:12 Protected Range Base */
  88                 u32 reserved1:2;        /* 13:14 Reserved */
  89                 u32 rpe:1;      /* 15 Read Protection Enable */
  90                 u32 limit:13;   /* 16:28 Protected Range Limit */
  91                 u32 reserved2:2;        /* 29:30 Reserved */
  92                 u32 wpe:1;      /* 31 Write Protection Enable */
  93         } range;
  94         u32 regval;
  95 };
  96
  97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
  98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
  99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 101                                                 u32 offset, u8 byte);
 102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 103                                          u8 *data);
 104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 105                                          u16 *data);
 106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 107                                          u8 size, u16 *data);
 108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 109                                            u32 *data);
 110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 111                                           u32 offset, u32 *data);
 112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 113                                             u32 offset, u32 data);
 114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 115                                                  u32 offset, u32 dword);
 116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
 135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
 140
 141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 142 {
 143         return readw(hw->flash_address + reg);
 144 }
 145
 146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 147 {
 148         return readl(hw->flash_address + reg);
 149 }
 150
 151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 152 {
 153         writew(val, hw->flash_address + reg);
 154 }
 155
 156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 157 {
 158         writel(val, hw->flash_address + reg);
 159 }
 160
 161 #define er16flash(reg)          __er16flash(hw, (reg))
 162 #define er32flash(reg)          __er32flash(hw, (reg))
 163 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 164 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 165
 166 /**
 167  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 168  *  @hw: pointer to the HW structure
 169  *
 170  *  Test access to the PHY registers by reading the PHY ID registers.  If
 171  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 172  *  otherwise assume the read PHY ID is correct if it is valid.
 173  *
 174  *  Assumes the sw/fw/hw semaphore is already acquired.
 175  **/
 176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 177 {
 178         u16 phy_reg = 0;
 179         u32 phy_id = 0;
 180         s32 ret_val = 0;
 181         u16 retry_count;
 182         u32 mac_reg = 0;
 183
 184         for (retry_count = 0; retry_count < 2; retry_count++) {
 185                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 186                 if (ret_val || (phy_reg == 0xFFFF))
 187                         continue;
 188                 phy_id = (u32)(phy_reg << 16);
 189
 190                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 191                 if (ret_val || (phy_reg == 0xFFFF)) {
 192                         phy_id = 0;
 193                         continue;
 194                 }
 195                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 196                 break;
 197         }
 198
 199         if (hw->phy.id) {
 200                 if (hw->phy.id == phy_id)
 201                         goto out;
 202         } else if (phy_id) {
 203                 hw->phy.id = phy_id;
 204                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 205                 goto out;
 206         }
 207
 208         /* In case the PHY needs to be in mdio slow mode,
 209          * set slow mode and try to get the PHY id again.
 210          */
 211         if (hw->mac.type < e1000_pch_lpt) {
 212                 hw->phy.ops.release(hw);
 213                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 214                 if (!ret_val)
 215                         ret_val = e1000e_get_phy_id(hw);
 216                 hw->phy.ops.acquire(hw);
 217         }
 218
 219         if (ret_val)
 220                 return false;
 221 out:
 222         if (hw->mac.type >= e1000_pch_lpt) {
 223                 /* Only unforce SMBus if ME is not active */
 224                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 225                         /* Unforce SMBus mode in PHY */
 226                         e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 227                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 228                         e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 229
 230                         /* Unforce SMBus mode in MAC */
 231                         mac_reg = er32(CTRL_EXT);
 232                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 233                         ew32(CTRL_EXT, mac_reg);
 234                 }
 235         }
 236
 237         return true;
 238 }
 239
 240 /**
 241  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 242  *  @hw: pointer to the HW structure
 243  *
 244  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 245  *  used to reset the PHY to a quiescent state when necessary.
 246  **/
 247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 248 {
 249         u32 mac_reg;
 250
 251         /* Set Phy Config Counter to 50msec */
 252         mac_reg = er32(FEXTNVM3);
 253         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 254         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 255         ew32(FEXTNVM3, mac_reg);
 256
 257         /* Toggle LANPHYPC Value bit */
 258         mac_reg = er32(CTRL);
 259         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 260         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 261         ew32(CTRL, mac_reg);
 262         e1e_flush();
 263         usleep_range(10, 20);
 264         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 265         ew32(CTRL, mac_reg);
 266         e1e_flush();
 267
 268         if (hw->mac.type < e1000_pch_lpt) {
 269                 msleep(50);
 270         } else {
 271                 u16 count = 20;
 272
 273                 do {
 274                         usleep_range(5000, 10000);
 275                 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
 276
 277                 msleep(30);
 278         }
 279 }
 280
 281 /**
 282  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 283  *  @hw: pointer to the HW structure
 284  *
 285  *  Workarounds/flow necessary for PHY initialization during driver load
 286  *  and resume paths.
 287  **/
 288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 289 {
 290         struct e1000_adapter *adapter = hw->adapter;
 291         u32 mac_reg, fwsm = er32(FWSM);
 292         s32 ret_val;
 293
 294         /* Gate automatic PHY configuration by hardware on managed and
 295          * non-managed 82579 and newer adapters.
 296          */
 297         e1000_gate_hw_phy_config_ich8lan(hw, true);
 298
 299         /* It is not possible to be certain of the current state of ULP
 300          * so forcibly disable it.
 301          */
 302         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 303         e1000_disable_ulp_lpt_lp(hw, true);
 304
 305         ret_val = hw->phy.ops.acquire(hw);
 306         if (ret_val) {
 307                 e_dbg("Failed to initialize PHY flow\n");
 308                 goto out;
 309         }
 310
 311         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 312          * inaccessible and resetting the PHY is not blocked, toggle the
 313          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 314          */
 315         switch (hw->mac.type) {
 316         case e1000_pch_lpt:
 317         case e1000_pch_spt:
 318         case e1000_pch_cnp:
 319                 if (e1000_phy_is_accessible_pchlan(hw))
 320                         break;
 321
 322                 /* Before toggling LANPHYPC, see if PHY is accessible by
 323                  * forcing MAC to SMBus mode first.
 324                  */
 325                 mac_reg = er32(CTRL_EXT);
 326                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 327                 ew32(CTRL_EXT, mac_reg);
 328
 329                 /* Wait 50 milliseconds for MAC to finish any retries
 330                  * that it might be trying to perform from previous
 331                  * attempts to acknowledge any phy read requests.
 332                  */
 333                 msleep(50);
 334
 335                 /* fall-through */
 336         case e1000_pch2lan:
 337                 if (e1000_phy_is_accessible_pchlan(hw))
 338                         break;
 339
 340                 /* fall-through */
 341         case e1000_pchlan:
 342                 if ((hw->mac.type == e1000_pchlan) &&
 343                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 344                         break;
 345
 346                 if (hw->phy.ops.check_reset_block(hw)) {
 347                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 348                         ret_val = -E1000_ERR_PHY;
 349                         break;
 350                 }
 351
 352                 /* Toggle LANPHYPC Value bit */
 353                 e1000_toggle_lanphypc_pch_lpt(hw);
 354                 if (hw->mac.type >= e1000_pch_lpt) {
 355                         if (e1000_phy_is_accessible_pchlan(hw))
 356                                 break;
 357
 358                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 359                          * so ensure that the MAC is also out of SMBus mode
 360                          */
 361                         mac_reg = er32(CTRL_EXT);
 362                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 363                         ew32(CTRL_EXT, mac_reg);
 364
 365                         if (e1000_phy_is_accessible_pchlan(hw))
 366                                 break;
 367
 368                         ret_val = -E1000_ERR_PHY;
 369                 }
 370                 break;
 371         default:
 372                 break;
 373         }
 374
 375         hw->phy.ops.release(hw);
 376         if (!ret_val) {
 377
 378                 /* Check to see if able to reset PHY.  Print error if not */
 379                 if (hw->phy.ops.check_reset_block(hw)) {
 380                         e_err("Reset blocked by ME\n");
 381                         goto out;
 382                 }
 383
 384                 /* Reset the PHY before any access to it.  Doing so, ensures
 385                  * that the PHY is in a known good state before we read/write
 386                  * PHY registers.  The generic reset is sufficient here,
 387                  * because we haven't determined the PHY type yet.
 388                  */
 389                 ret_val = e1000e_phy_hw_reset_generic(hw);
 390                 if (ret_val)
 391                         goto out;
 392
 393                 /* On a successful reset, possibly need to wait for the PHY
 394                  * to quiesce to an accessible state before returning control
 395                  * to the calling function.  If the PHY does not quiesce, then
 396                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 397                  *  the PHY is in.
 398                  */
 399                 ret_val = hw->phy.ops.check_reset_block(hw);
 400                 if (ret_val)
 401                         e_err("ME blocked access to PHY after reset\n");
 402         }
 403
 404 out:
 405         /* Ungate automatic PHY configuration on non-managed 82579 */
 406         if ((hw->mac.type == e1000_pch2lan) &&
 407             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 408                 usleep_range(10000, 20000);
 409                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 410         }
 411
 412         return ret_val;
 413 }
 414
 415 /**
 416  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 417  *  @hw: pointer to the HW structure
 418  *
 419  *  Initialize family-specific PHY parameters and function pointers.
 420  **/
 421 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 422 {
 423         struct e1000_phy_info *phy = &hw->phy;
 424         s32 ret_val;
 425
 426         phy->addr = 1;
 427         phy->reset_delay_us = 100;
 428
 429         phy->ops.set_page = e1000_set_page_igp;
 430         phy->ops.read_reg = e1000_read_phy_reg_hv;
 431         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 432         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 433         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 434         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 435         phy->ops.write_reg = e1000_write_phy_reg_hv;
 436         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 437         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 438         phy->ops.power_up = e1000_power_up_phy_copper;
 439         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 440         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 441
 442         phy->id = e1000_phy_unknown;
 443
 444         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 445         if (ret_val)
 446                 return ret_val;
 447
 448         if (phy->id == e1000_phy_unknown)
 449                 switch (hw->mac.type) {
 450                 default:
 451                         ret_val = e1000e_get_phy_id(hw);
 452                         if (ret_val)
 453                                 return ret_val;
 454                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 455                                 break;
 456                         /* fall-through */
 457                 case e1000_pch2lan:
 458                 case e1000_pch_lpt:
 459                 case e1000_pch_spt:
 460                 case e1000_pch_cnp:
 461                         /* In case the PHY needs to be in mdio slow mode,
 462                          * set slow mode and try to get the PHY id again.
 463                          */
 464                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 465                         if (ret_val)
 466                                 return ret_val;
 467                         ret_val = e1000e_get_phy_id(hw);
 468                         if (ret_val)
 469                                 return ret_val;
 470                         break;
 471                 }
 472         phy->type = e1000e_get_phy_type_from_id(phy->id);
 473
 474         switch (phy->type) {
 475         case e1000_phy_82577:
 476         case e1000_phy_82579:
 477         case e1000_phy_i217:
 478                 phy->ops.check_polarity = e1000_check_polarity_82577;
 479                 phy->ops.force_speed_duplex =
 480                     e1000_phy_force_speed_duplex_82577;
 481                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 482                 phy->ops.get_info = e1000_get_phy_info_82577;
 483                 phy->ops.commit = e1000e_phy_sw_reset;
 484                 break;
 485         case e1000_phy_82578:
 486                 phy->ops.check_polarity = e1000_check_polarity_m88;
 487                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 488                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 489                 phy->ops.get_info = e1000e_get_phy_info_m88;
 490                 break;
 491         default:
 492                 ret_val = -E1000_ERR_PHY;
 493                 break;
 494         }
 495
 496         return ret_val;
 497 }
 498
 499 /**
 500  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 501  *  @hw: pointer to the HW structure
 502  *
 503  *  Initialize family-specific PHY parameters and function pointers.
 504  **/
 505 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 506 {
 507         struct e1000_phy_info *phy = &hw->phy;
 508         s32 ret_val;
 509         u16 i = 0;
 510
 511         phy->addr = 1;
 512         phy->reset_delay_us = 100;
 513
 514         phy->ops.power_up = e1000_power_up_phy_copper;
 515         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 516
 517         /* We may need to do this twice - once for IGP and if that fails,
 518          * we'll set BM func pointers and try again
 519          */
 520         ret_val = e1000e_determine_phy_address(hw);
 521         if (ret_val) {
 522                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 523                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 524                 ret_val = e1000e_determine_phy_address(hw);
 525                 if (ret_val) {
 526                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 527                         return ret_val;
 528                 }
 529         }
 530
 531         phy->id = 0;
 532         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 533                (i++ < 100)) {
 534                 usleep_range(1000, 2000);
 535                 ret_val = e1000e_get_phy_id(hw);
 536                 if (ret_val)
 537                         return ret_val;
 538         }
 539
 540         /* Verify phy id */
 541         switch (phy->id) {
 542         case IGP03E1000_E_PHY_ID:
 543                 phy->type = e1000_phy_igp_3;
 544                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 545                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 546                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 547                 phy->ops.get_info = e1000e_get_phy_info_igp;
 548                 phy->ops.check_polarity = e1000_check_polarity_igp;
 549                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 550                 break;
 551         case IFE_E_PHY_ID:
 552         case IFE_PLUS_E_PHY_ID:
 553         case IFE_C_E_PHY_ID:
 554                 phy->type = e1000_phy_ife;
 555                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 556                 phy->ops.get_info = e1000_get_phy_info_ife;
 557                 phy->ops.check_polarity = e1000_check_polarity_ife;
 558                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 559                 break;
 560         case BME1000_E_PHY_ID:
 561                 phy->type = e1000_phy_bm;
 562                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 563                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 564                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 565                 phy->ops.commit = e1000e_phy_sw_reset;
 566                 phy->ops.get_info = e1000e_get_phy_info_m88;
 567                 phy->ops.check_polarity = e1000_check_polarity_m88;
 568                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 569                 break;
 570         default:
 571                 return -E1000_ERR_PHY;
 572         }
 573
 574         return 0;
 575 }
 576
 577 /**
 578  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 579  *  @hw: pointer to the HW structure
 580  *
 581  *  Initialize family-specific NVM parameters and function
 582  *  pointers.
 583  **/
 584 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 585 {
 586         struct e1000_nvm_info *nvm = &hw->nvm;
 587         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 588         u32 gfpreg, sector_base_addr, sector_end_addr;
 589         u16 i;
 590         u32 nvm_size;
 591
 592         nvm->type = e1000_nvm_flash_sw;
 593
 594         if (hw->mac.type >= e1000_pch_spt) {
 595                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 596                  * STRAP register. This is because in SPT the GbE Flash region
 597                  * is no longer accessed through the flash registers. Instead,
 598                  * the mechanism has changed, and the Flash region access
 599                  * registers are now implemented in GbE memory space.
 600                  */
 601                 nvm->flash_base_addr = 0;
 602                 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
 603                     * NVM_SIZE_MULTIPLIER;
 604                 nvm->flash_bank_size = nvm_size / 2;
 605                 /* Adjust to word count */
 606                 nvm->flash_bank_size /= sizeof(u16);
 607                 /* Set the base address for flash register access */
 608                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 609         } else {
 610                 /* Can't read flash registers if register set isn't mapped. */
 611                 if (!hw->flash_address) {
 612                         e_dbg("ERROR: Flash registers not mapped\n");
 613                         return -E1000_ERR_CONFIG;
 614                 }
 615
 616                 gfpreg = er32flash(ICH_FLASH_GFPREG);
 617
 618                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 619                  * Add 1 to sector_end_addr since this sector is included in
 620                  * the overall size.
 621                  */
 622                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 623                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 624
 625                 /* flash_base_addr is byte-aligned */
 626                 nvm->flash_base_addr = sector_base_addr
 627                     << FLASH_SECTOR_ADDR_SHIFT;
 628
 629                 /* find total size of the NVM, then cut in half since the total
 630                  * size represents two separate NVM banks.
 631                  */
 632                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 633                                         << FLASH_SECTOR_ADDR_SHIFT);
 634                 nvm->flash_bank_size /= 2;
 635                 /* Adjust to word count */
 636                 nvm->flash_bank_size /= sizeof(u16);
 637         }
 638
 639         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 640
 641         /* Clear shadow ram */
 642         for (i = 0; i < nvm->word_size; i++) {
 643                 dev_spec->shadow_ram[i].modified = false;
 644                 dev_spec->shadow_ram[i].value = 0xFFFF;
 645         }
 646
 647         return 0;
 648 }
 649
 650 /**
 651  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 652  *  @hw: pointer to the HW structure
 653  *
 654  *  Initialize family-specific MAC parameters and function
 655  *  pointers.
 656  **/
 657 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 658 {
 659         struct e1000_mac_info *mac = &hw->mac;
 660
 661         /* Set media type function pointer */
 662         hw->phy.media_type = e1000_media_type_copper;
 663
 664         /* Set mta register count */
 665         mac->mta_reg_count = 32;
 666         /* Set rar entry count */
 667         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 668         if (mac->type == e1000_ich8lan)
 669                 mac->rar_entry_count--;
 670         /* FWSM register */
 671         mac->has_fwsm = true;
 672         /* ARC subsystem not supported */
 673         mac->arc_subsystem_valid = false;
 674         /* Adaptive IFS supported */
 675         mac->adaptive_ifs = true;
 676
 677         /* LED and other operations */
 678         switch (mac->type) {
 679         case e1000_ich8lan:
 680         case e1000_ich9lan:
 681         case e1000_ich10lan:
 682                 /* check management mode */
 683                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 684                 /* ID LED init */
 685                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 686                 /* blink LED */
 687                 mac->ops.blink_led = e1000e_blink_led_generic;
 688                 /* setup LED */
 689                 mac->ops.setup_led = e1000e_setup_led_generic;
 690                 /* cleanup LED */
 691                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 692                 /* turn on/off LED */
 693                 mac->ops.led_on = e1000_led_on_ich8lan;
 694                 mac->ops.led_off = e1000_led_off_ich8lan;
 695                 break;
 696         case e1000_pch2lan:
 697                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 698                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 699                 /* fall-through */
 700         case e1000_pch_lpt:
 701         case e1000_pch_spt:
 702         case e1000_pch_cnp:
 703         case e1000_pchlan:
 704                 /* check management mode */
 705                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 706                 /* ID LED init */
 707                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 708                 /* setup LED */
 709                 mac->ops.setup_led = e1000_setup_led_pchlan;
 710                 /* cleanup LED */
 711                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 712                 /* turn on/off LED */
 713                 mac->ops.led_on = e1000_led_on_pchlan;
 714                 mac->ops.led_off = e1000_led_off_pchlan;
 715                 break;
 716         default:
 717                 break;
 718         }
 719
 720         if (mac->type >= e1000_pch_lpt) {
 721                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 722                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 723                 mac->ops.setup_physical_interface =
 724                     e1000_setup_copper_link_pch_lpt;
 725                 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
 726         }
 727
 728         /* Enable PCS Lock-loss workaround for ICH8 */
 729         if (mac->type == e1000_ich8lan)
 730                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 731
 732         return 0;
 733 }
 734
 735 /**
 736  *  __e1000_access_emi_reg_locked - Read/write EMI register
 737  *  @hw: pointer to the HW structure
 738  *  @addr: EMI address to program
 739  *  @data: pointer to value to read/write from/to the EMI address
 740  *  @read: boolean flag to indicate read or write
 741  *
 742  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 743  **/
 744 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 745                                          u16 *data, bool read)
 746 {
 747         s32 ret_val;
 748
 749         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 750         if (ret_val)
 751                 return ret_val;
 752
 753         if (read)
 754                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 755         else
 756                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 757
 758         return ret_val;
 759 }
 760
 761 /**
 762  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 763  *  @hw: pointer to the HW structure
 764  *  @addr: EMI address to program
 765  *  @data: value to be read from the EMI address
 766  *
 767  *  Assumes the SW/FW/HW Semaphore is already acquired.
 768  **/
 769 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 770 {
 771         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 772 }
 773
 774 /**
 775  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 776  *  @hw: pointer to the HW structure
 777  *  @addr: EMI address to program
 778  *  @data: value to be written to the EMI address
 779  *
 780  *  Assumes the SW/FW/HW Semaphore is already acquired.
 781  **/
 782 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 783 {
 784         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 785 }
 786
 787 /**
 788  *  e1000_set_eee_pchlan - Enable/disable EEE support
 789  *  @hw: pointer to the HW structure
 790  *
 791  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 792  *  the link and the EEE capabilities of the link partner.  The LPI Control
 793  *  register bits will remain set only if/when link is up.
 794  *
 795  *  EEE LPI must not be asserted earlier than one second after link is up.
 796  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 797  *  can be link issues with some switches.  Other devices can have EEE LPI
 798  *  enabled immediately upon link up since they have a timer in hardware which
 799  *  prevents LPI from being asserted too early.
 800  **/
 801 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 802 {
 803         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 804         s32 ret_val;
 805         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 806
 807         switch (hw->phy.type) {
 808         case e1000_phy_82579:
 809                 lpa = I82579_EEE_LP_ABILITY;
 810                 pcs_status = I82579_EEE_PCS_STATUS;
 811                 adv_addr = I82579_EEE_ADVERTISEMENT;
 812                 break;
 813         case e1000_phy_i217:
 814                 lpa = I217_EEE_LP_ABILITY;
 815                 pcs_status = I217_EEE_PCS_STATUS;
 816                 adv_addr = I217_EEE_ADVERTISEMENT;
 817                 break;
 818         default:
 819                 return 0;
 820         }
 821
 822         ret_val = hw->phy.ops.acquire(hw);
 823         if (ret_val)
 824                 return ret_val;
 825
 826         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 827         if (ret_val)
 828                 goto release;
 829
 830         /* Clear bits that enable EEE in various speeds */
 831         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 832
 833         /* Enable EEE if not disabled by user */
 834         if (!dev_spec->eee_disable) {
 835                 /* Save off link partner's EEE ability */
 836                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 837                                                     &dev_spec->eee_lp_ability);
 838                 if (ret_val)
 839                         goto release;
 840
 841                 /* Read EEE advertisement */
 842                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 843                 if (ret_val)
 844                         goto release;
 845
 846                 /* Enable EEE only for speeds in which the link partner is
 847                  * EEE capable and for which we advertise EEE.
 848                  */
 849                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 850                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 851
 852                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 853                         e1e_rphy_locked(hw, MII_LPA, &data);
 854                         if (data & LPA_100FULL)
 855                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 856                         else
 857                                 /* EEE is not supported in 100Half, so ignore
 858                                  * partner's EEE in 100 ability if full-duplex
 859                                  * is not advertised.
 860                                  */
 861                                 dev_spec->eee_lp_ability &=
 862                                     ~I82579_EEE_100_SUPPORTED;
 863                 }
 864         }
 865
 866         if (hw->phy.type == e1000_phy_82579) {
 867                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 868                                                     &data);
 869                 if (ret_val)
 870                         goto release;
 871
 872                 data &= ~I82579_LPI_100_PLL_SHUT;
 873                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 874                                                      data);
 875         }
 876
 877         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 878         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 879         if (ret_val)
 880                 goto release;
 881
 882         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 883 release:
 884         hw->phy.ops.release(hw);
 885
 886         return ret_val;
 887 }
 888
 889 /**
 890  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 891  *  @hw:   pointer to the HW structure
 892  *  @link: link up bool flag
 893  *
 894  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 895  *  preventing further DMA write requests.  Workaround the issue by disabling
 896  *  the de-assertion of the clock request when in 1Gpbs mode.
 897  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 898  *  speeds in order to avoid Tx hangs.
 899  **/
 900 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 901 {
 902         u32 fextnvm6 = er32(FEXTNVM6);
 903         u32 status = er32(STATUS);
 904         s32 ret_val = 0;
 905         u16 reg;
 906
 907         if (link && (status & E1000_STATUS_SPEED_1000)) {
 908                 ret_val = hw->phy.ops.acquire(hw);
 909                 if (ret_val)
 910                         return ret_val;
 911
 912                 ret_val =
 913                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 914                                                 &reg);
 915                 if (ret_val)
 916                         goto release;
 917
 918                 ret_val =
 919                     e1000e_write_kmrn_reg_locked(hw,
 920                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 921                                                  reg &
 922                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 923                 if (ret_val)
 924                         goto release;
 925
 926                 usleep_range(10, 20);
 927
 928                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 929
 930                 ret_val =
 931                     e1000e_write_kmrn_reg_locked(hw,
 932                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 933                                                  reg);
 934 release:
 935                 hw->phy.ops.release(hw);
 936         } else {
 937                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 938                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 939
 940                 if ((hw->phy.revision > 5) || !link ||
 941                     ((status & E1000_STATUS_SPEED_100) &&
 942                      (status & E1000_STATUS_FD)))
 943                         goto update_fextnvm6;
 944
 945                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 946                 if (ret_val)
 947                         return ret_val;
 948
 949                 /* Clear link status transmit timeout */
 950                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 951
 952                 if (status & E1000_STATUS_SPEED_100) {
 953                         /* Set inband Tx timeout to 5x10us for 100Half */
 954                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 955
 956                         /* Do not extend the K1 entry latency for 100Half */
 957                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 958                 } else {
 959                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 960                         reg |= 50 <<
 961                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 962
 963                         /* Extend the K1 entry latency for 10 Mbps */
 964                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 965                 }
 966
 967                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 968                 if (ret_val)
 969                         return ret_val;
 970
 971 update_fextnvm6:
 972                 ew32(FEXTNVM6, fextnvm6);
 973         }
 974
 975         return ret_val;
 976 }
 977
 978 /**
 979  *  e1000_platform_pm_pch_lpt - Set platform power management values
 980  *  @hw: pointer to the HW structure
 981  *  @link: bool indicating link status
 982  *
 983  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
 984  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
 985  *  when link is up (which must not exceed the maximum latency supported
 986  *  by the platform), otherwise specify there is no LTR requirement.
 987  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
 988  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
 989  *  Capability register set, on this device LTR is set by writing the
 990  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
 991  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
 992  *  message to the PMC.
 993  **/
 994 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
 995 {
 996         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
 997             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
 998         u32 max_ltr_enc_d = 0;  /* maximum LTR decoded by platform */
 999         u32 lat_enc_d = 0;      /* latency decoded */
1000         u16 lat_enc = 0;        /* latency encoded */
1001
1002         if (link) {
1003                 u16 speed, duplex, scale = 0;
1004                 u16 max_snoop, max_nosnoop;
1005                 u16 max_ltr_enc;        /* max LTR latency encoded */
1006                 u64 value;
1007                 u32 rxa;
1008
1009                 if (!hw->adapter->max_frame_size) {
1010                         e_dbg("max_frame_size not set.\n");
1011                         return -E1000_ERR_CONFIG;
1012                 }
1013
1014                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1015                 if (!speed) {
1016                         e_dbg("Speed not set.\n");
1017                         return -E1000_ERR_CONFIG;
1018                 }
1019
1020                 /* Rx Packet Buffer Allocation size (KB) */
1021                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1022
1023                 /* Determine the maximum latency tolerated by the device.
1024                  *
1025                  * Per the PCIe spec, the tolerated latencies are encoded as
1026                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1027                  * a 10-bit value (0-1023) to provide a range from 1 ns to
1028                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1029                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1030                  */
1031                 rxa *= 512;
1032                 value = (rxa > hw->adapter->max_frame_size) ?
1033                         (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1034                         0;
1035
1036                 while (value > PCI_LTR_VALUE_MASK) {
1037                         scale++;
1038                         value = DIV_ROUND_UP(value, BIT(5));
1039                 }
1040                 if (scale > E1000_LTRV_SCALE_MAX) {
1041                         e_dbg("Invalid LTR latency scale %d\n", scale);
1042                         return -E1000_ERR_CONFIG;
1043                 }
1044                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1045
1046                 /* Determine the maximum latency tolerated by the platform */
1047                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1048                                      &max_snoop);
1049                 pci_read_config_word(hw->adapter->pdev,
1050                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1051                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1052
1053                 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) *
1054                              (1U << (E1000_LTRV_SCALE_FACTOR *
1055                              ((lat_enc & E1000_LTRV_SCALE_MASK)
1056                              >> E1000_LTRV_SCALE_SHIFT)));
1057
1058                 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) *
1059                                  (1U << (E1000_LTRV_SCALE_FACTOR *
1060                                  ((max_ltr_enc & E1000_LTRV_SCALE_MASK)
1061                                  >> E1000_LTRV_SCALE_SHIFT)));
1062
1063                 if (lat_enc_d > max_ltr_enc_d)
1064                         lat_enc = max_ltr_enc;
1065         }
1066
1067         /* Set Snoop and No-Snoop latencies the same */
1068         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1069         ew32(LTRV, reg);
1070
1071         return 0;
1072 }
1073
1074 /**
1075  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1076  *  @hw: pointer to the HW structure
1077  *  @to_sx: boolean indicating a system power state transition to Sx
1078  *
1079  *  When link is down, configure ULP mode to significantly reduce the power
1080  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1081  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1082  *  system, configure the ULP mode by software.
1083  */
1084 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1085 {
1086         u32 mac_reg;
1087         s32 ret_val = 0;
1088         u16 phy_reg;
1089         u16 oem_reg = 0;
1090
1091         if ((hw->mac.type < e1000_pch_lpt) ||
1092             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1093             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1094             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1095             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1096             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1097                 return 0;
1098
1099         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1100                 /* Request ME configure ULP mode in the PHY */
1101                 mac_reg = er32(H2ME);
1102                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1103                 ew32(H2ME, mac_reg);
1104
1105                 goto out;
1106         }
1107
1108         if (!to_sx) {
1109                 int i = 0;
1110
1111                 /* Poll up to 5 seconds for Cable Disconnected indication */
1112                 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1113                         /* Bail if link is re-acquired */
1114                         if (er32(STATUS) & E1000_STATUS_LU)
1115                                 return -E1000_ERR_PHY;
1116
1117                         if (i++ == 100)
1118                                 break;
1119
1120                         msleep(50);
1121                 }
1122                 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1123                       (er32(FEXT) &
1124                        E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1125         }
1126
1127         ret_val = hw->phy.ops.acquire(hw);
1128         if (ret_val)
1129                 goto out;
1130
1131         /* Force SMBus mode in PHY */
1132         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1133         if (ret_val)
1134                 goto release;
1135         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1136         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1137
1138         /* Force SMBus mode in MAC */
1139         mac_reg = er32(CTRL_EXT);
1140         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1141         ew32(CTRL_EXT, mac_reg);
1142
1143         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1144          * LPLU and disable Gig speed when entering ULP
1145          */
1146         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1147                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1148                                                        &oem_reg);
1149                 if (ret_val)
1150                         goto release;
1151
1152                 phy_reg = oem_reg;
1153                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1154
1155                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1156                                                         phy_reg);
1157
1158                 if (ret_val)
1159                         goto release;
1160         }
1161
1162         /* Set Inband ULP Exit, Reset to SMBus mode and
1163          * Disable SMBus Release on PERST# in PHY
1164          */
1165         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1166         if (ret_val)
1167                 goto release;
1168         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1169                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1170         if (to_sx) {
1171                 if (er32(WUFC) & E1000_WUFC_LNKC)
1172                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1173                 else
1174                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1175
1176                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1177                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1178         } else {
1179                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1180                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1181                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1182         }
1183         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1184
1185         /* Set Disable SMBus Release on PERST# in MAC */
1186         mac_reg = er32(FEXTNVM7);
1187         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1188         ew32(FEXTNVM7, mac_reg);
1189
1190         /* Commit ULP changes in PHY by starting auto ULP configuration */
1191         phy_reg |= I218_ULP_CONFIG1_START;
1192         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1193
1194         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1195             to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1196                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1197                                                         oem_reg);
1198                 if (ret_val)
1199                         goto release;
1200         }
1201
1202 release:
1203         hw->phy.ops.release(hw);
1204 out:
1205         if (ret_val)
1206                 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1207         else
1208                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1209
1210         return ret_val;
1211 }
1212
1213 /**
1214  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1215  *  @hw: pointer to the HW structure
1216  *  @force: boolean indicating whether or not to force disabling ULP
1217  *
1218  *  Un-configure ULP mode when link is up, the system is transitioned from
1219  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1220  *  system, poll for an indication from ME that ULP has been un-configured.
1221  *  If not on an ME enabled system, un-configure the ULP mode by software.
1222  *
1223  *  During nominal operation, this function is called when link is acquired
1224  *  to disable ULP mode (force=false); otherwise, for example when unloading
1225  *  the driver or during Sx->S0 transitions, this is called with force=true
1226  *  to forcibly disable ULP.
1227  */
1228 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1229 {
1230         s32 ret_val = 0;
1231         u32 mac_reg;
1232         u16 phy_reg;
1233         int i = 0;
1234
1235         if ((hw->mac.type < e1000_pch_lpt) ||
1236             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1237             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1238             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1239             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1240             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1241                 return 0;
1242
1243         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1244                 if (force) {
1245                         /* Request ME un-configure ULP mode in the PHY */
1246                         mac_reg = er32(H2ME);
1247                         mac_reg &= ~E1000_H2ME_ULP;
1248                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1249                         ew32(H2ME, mac_reg);
1250                 }
1251
1252                 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1253                 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1254                         if (i++ == 30) {
1255                                 ret_val = -E1000_ERR_PHY;
1256                                 goto out;
1257                         }
1258
1259                         usleep_range(10000, 20000);
1260                 }
1261                 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1262
1263                 if (force) {
1264                         mac_reg = er32(H2ME);
1265                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1266                         ew32(H2ME, mac_reg);
1267                 } else {
1268                         /* Clear H2ME.ULP after ME ULP configuration */
1269                         mac_reg = er32(H2ME);
1270                         mac_reg &= ~E1000_H2ME_ULP;
1271                         ew32(H2ME, mac_reg);
1272                 }
1273
1274                 goto out;
1275         }
1276
1277         ret_val = hw->phy.ops.acquire(hw);
1278         if (ret_val)
1279                 goto out;
1280
1281         if (force)
1282                 /* Toggle LANPHYPC Value bit */
1283                 e1000_toggle_lanphypc_pch_lpt(hw);
1284
1285         /* Unforce SMBus mode in PHY */
1286         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1287         if (ret_val) {
1288                 /* The MAC might be in PCIe mode, so temporarily force to
1289                  * SMBus mode in order to access the PHY.
1290                  */
1291                 mac_reg = er32(CTRL_EXT);
1292                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1293                 ew32(CTRL_EXT, mac_reg);
1294
1295                 msleep(50);
1296
1297                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1298                                                        &phy_reg);
1299                 if (ret_val)
1300                         goto release;
1301         }
1302         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1303         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1304
1305         /* Unforce SMBus mode in MAC */
1306         mac_reg = er32(CTRL_EXT);
1307         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1308         ew32(CTRL_EXT, mac_reg);
1309
1310         /* When ULP mode was previously entered, K1 was disabled by the
1311          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1312          */
1313         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1314         if (ret_val)
1315                 goto release;
1316         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1317         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1318
1319         /* Clear ULP enabled configuration */
1320         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1321         if (ret_val)
1322                 goto release;
1323         phy_reg &= ~(I218_ULP_CONFIG1_IND |
1324                      I218_ULP_CONFIG1_STICKY_ULP |
1325                      I218_ULP_CONFIG1_RESET_TO_SMBUS |
1326                      I218_ULP_CONFIG1_WOL_HOST |
1327                      I218_ULP_CONFIG1_INBAND_EXIT |
1328                      I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1329                      I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1330                      I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1331         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1332
1333         /* Commit ULP changes by starting auto ULP configuration */
1334         phy_reg |= I218_ULP_CONFIG1_START;
1335         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1336
1337         /* Clear Disable SMBus Release on PERST# in MAC */
1338         mac_reg = er32(FEXTNVM7);
1339         mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1340         ew32(FEXTNVM7, mac_reg);
1341
1342 release:
1343         hw->phy.ops.release(hw);
1344         if (force) {
1345                 e1000_phy_hw_reset(hw);
1346                 msleep(50);
1347         }
1348 out:
1349         if (ret_val)
1350                 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1351         else
1352                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1353
1354         return ret_val;
1355 }
1356
1357 /**
1358  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1359  *  @hw: pointer to the HW structure
1360  *
1361  *  Checks to see of the link status of the hardware has changed.  If a
1362  *  change in link status has been detected, then we read the PHY registers
1363  *  to get the current speed/duplex if link exists.
1364  **/
1365 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1366 {
1367         struct e1000_mac_info *mac = &hw->mac;
1368         s32 ret_val, tipg_reg = 0;
1369         u16 emi_addr, emi_val = 0;
1370         bool link;
1371         u16 phy_reg;
1372
1373         /* We only want to go out to the PHY registers to see if Auto-Neg
1374          * has completed and/or if our link status has changed.  The
1375          * get_link_status flag is set upon receiving a Link Status
1376          * Change or Rx Sequence Error interrupt.
1377          */
1378         if (!mac->get_link_status)
1379                 return 0;
1380         mac->get_link_status = false;
1381
1382         /* First we want to see if the MII Status Register reports
1383          * link.  If so, then we want to get the current speed/duplex
1384          * of the PHY.
1385          */
1386         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1387         if (ret_val)
1388                 goto out;
1389
1390         if (hw->mac.type == e1000_pchlan) {
1391                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1392                 if (ret_val)
1393                         goto out;
1394         }
1395
1396         /* When connected at 10Mbps half-duplex, some parts are excessively
1397          * aggressive resulting in many collisions. To avoid this, increase
1398          * the IPG and reduce Rx latency in the PHY.
1399          */
1400         if ((hw->mac.type >= e1000_pch2lan) && link) {
1401                 u16 speed, duplex;
1402
1403                 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1404                 tipg_reg = er32(TIPG);
1405                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1406
1407                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1408                         tipg_reg |= 0xFF;
1409                         /* Reduce Rx latency in analog PHY */
1410                         emi_val = 0;
1411                 } else if (hw->mac.type >= e1000_pch_spt &&
1412                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1413                         tipg_reg |= 0xC;
1414                         emi_val = 1;
1415                 } else {
1416
1417                         /* Roll back the default values */
1418                         tipg_reg |= 0x08;
1419                         emi_val = 1;
1420                 }
1421
1422                 ew32(TIPG, tipg_reg);
1423
1424                 ret_val = hw->phy.ops.acquire(hw);
1425                 if (ret_val)
1426                         goto out;
1427
1428                 if (hw->mac.type == e1000_pch2lan)
1429                         emi_addr = I82579_RX_CONFIG;
1430                 else
1431                         emi_addr = I217_RX_CONFIG;
1432                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1433
1434                 if (hw->mac.type >= e1000_pch_lpt) {
1435                         u16 phy_reg;
1436
1437                         e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1438                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1439                         if (speed == SPEED_100 || speed == SPEED_10)
1440                                 phy_reg |= 0x3E8;
1441                         else
1442                                 phy_reg |= 0xFA;
1443                         e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1444
1445                         if (speed == SPEED_1000) {
1446                                 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1447                                                             &phy_reg);
1448
1449                                 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1450
1451                                 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1452                                                              phy_reg);
1453                         }
1454                 }
1455                 hw->phy.ops.release(hw);
1456
1457                 if (ret_val)
1458                         goto out;
1459
1460                 if (hw->mac.type >= e1000_pch_spt) {
1461                         u16 data;
1462                         u16 ptr_gap;
1463
1464                         if (speed == SPEED_1000) {
1465                                 ret_val = hw->phy.ops.acquire(hw);
1466                                 if (ret_val)
1467                                         goto out;
1468
1469                                 ret_val = e1e_rphy_locked(hw,
1470                                                           PHY_REG(776, 20),
1471                                                           &data);
1472                                 if (ret_val) {
1473                                         hw->phy.ops.release(hw);
1474                                         goto out;
1475                                 }
1476
1477                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1478                                 if (ptr_gap < 0x18) {
1479                                         data &= ~(0x3FF << 2);
1480                                         data |= (0x18 << 2);
1481                                         ret_val =
1482                                             e1e_wphy_locked(hw,
1483                                                             PHY_REG(776, 20),
1484                                                             data);
1485                                 }
1486                                 hw->phy.ops.release(hw);
1487                                 if (ret_val)
1488                                         goto out;
1489                         } else {
1490                                 ret_val = hw->phy.ops.acquire(hw);
1491                                 if (ret_val)
1492                                         goto out;
1493
1494                                 ret_val = e1e_wphy_locked(hw,
1495                                                           PHY_REG(776, 20),
1496                                                           0xC023);
1497                                 hw->phy.ops.release(hw);
1498                                 if (ret_val)
1499                                         goto out;
1500
1501                         }
1502                 }
1503         }
1504
1505         /* I217 Packet Loss issue:
1506          * ensure that FEXTNVM4 Beacon Duration is set correctly
1507          * on power up.
1508          * Set the Beacon Duration for I217 to 8 usec
1509          */
1510         if (hw->mac.type >= e1000_pch_lpt) {
1511                 u32 mac_reg;
1512
1513                 mac_reg = er32(FEXTNVM4);
1514                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1515                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1516                 ew32(FEXTNVM4, mac_reg);
1517         }
1518
1519         /* Work-around I218 hang issue */
1520         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1521             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1522             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1523             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1524                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1525                 if (ret_val)
1526                         goto out;
1527         }
1528         if (hw->mac.type >= e1000_pch_lpt) {
1529                 /* Set platform power management values for
1530                  * Latency Tolerance Reporting (LTR)
1531                  */
1532                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1533                 if (ret_val)
1534                         goto out;
1535         }
1536
1537         /* Clear link partner's EEE ability */
1538         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1539
1540         if (hw->mac.type >= e1000_pch_lpt) {
1541                 u32 fextnvm6 = er32(FEXTNVM6);
1542
1543                 if (hw->mac.type == e1000_pch_spt) {
1544                         /* FEXTNVM6 K1-off workaround - for SPT only */
1545                         u32 pcieanacfg = er32(PCIEANACFG);
1546
1547                         if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1548                                 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1549                         else
1550                                 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1551                 }
1552
1553                 ew32(FEXTNVM6, fextnvm6);
1554         }
1555
1556         if (!link)
1557                 goto out;
1558
1559         switch (hw->mac.type) {
1560         case e1000_pch2lan:
1561                 ret_val = e1000_k1_workaround_lv(hw);
1562                 if (ret_val)
1563                         return ret_val;
1564                 /* fall-thru */
1565         case e1000_pchlan:
1566                 if (hw->phy.type == e1000_phy_82578) {
1567                         ret_val = e1000_link_stall_workaround_hv(hw);
1568                         if (ret_val)
1569                                 return ret_val;
1570                 }
1571
1572                 /* Workaround for PCHx parts in half-duplex:
1573                  * Set the number of preambles removed from the packet
1574                  * when it is passed from the PHY to the MAC to prevent
1575                  * the MAC from misinterpreting the packet type.
1576                  */
1577                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1578                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1579
1580                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1581                         phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1582
1583                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1584                 break;
1585         default:
1586                 break;
1587         }
1588
1589         /* Check if there was DownShift, must be checked
1590          * immediately after link-up
1591          */
1592         e1000e_check_downshift(hw);
1593
1594         /* Enable/Disable EEE after link up */
1595         if (hw->phy.type > e1000_phy_82579) {
1596                 ret_val = e1000_set_eee_pchlan(hw);
1597                 if (ret_val)
1598                         return ret_val;
1599         }
1600
1601         /* If we are forcing speed/duplex, then we simply return since
1602          * we have already determined whether we have link or not.
1603          */
1604         if (!mac->autoneg)
1605                 return -E1000_ERR_CONFIG;
1606
1607         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1608          * of MAC speed/duplex configuration.  So we only need to
1609          * configure Collision Distance in the MAC.
1610          */
1611         mac->ops.config_collision_dist(hw);
1612
1613         /* Configure Flow Control now that Auto-Neg has completed.
1614          * First, we need to restore the desired flow control
1615          * settings because we may have had to re-autoneg with a
1616          * different link partner.
1617          */
1618         ret_val = e1000e_config_fc_after_link_up(hw);
1619         if (ret_val)
1620                 e_dbg("Error configuring flow control\n");
1621
1622         return ret_val;
1623
1624 out:
1625         mac->get_link_status = true;
1626         return ret_val;
1627 }
1628
1629 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1630 {
1631         struct e1000_hw *hw = &adapter->hw;
1632         s32 rc;
1633
1634         rc = e1000_init_mac_params_ich8lan(hw);
1635         if (rc)
1636                 return rc;
1637
1638         rc = e1000_init_nvm_params_ich8lan(hw);
1639         if (rc)
1640                 return rc;
1641
1642         switch (hw->mac.type) {
1643         case e1000_ich8lan:
1644         case e1000_ich9lan:
1645         case e1000_ich10lan:
1646                 rc = e1000_init_phy_params_ich8lan(hw);
1647                 break;
1648         case e1000_pchlan:
1649         case e1000_pch2lan:
1650         case e1000_pch_lpt:
1651         case e1000_pch_spt:
1652         case e1000_pch_cnp:
1653                 rc = e1000_init_phy_params_pchlan(hw);
1654                 break;
1655         default:
1656                 break;
1657         }
1658         if (rc)
1659                 return rc;
1660
1661         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1662          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1663          */
1664         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1665             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1666              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1667                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1668                 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1669
1670                 hw->mac.ops.blink_led = NULL;
1671         }
1672
1673         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1674             (adapter->hw.phy.type != e1000_phy_ife))
1675                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1676
1677         /* Enable workaround for 82579 w/ ME enabled */
1678         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1679             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1680                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1681
1682         return 0;
1683 }
1684
1685 static DEFINE_MUTEX(nvm_mutex);
1686
1687 /**
1688  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1689  *  @hw: pointer to the HW structure
1690  *
1691  *  Acquires the mutex for performing NVM operations.
1692  **/
1693 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1694 {
1695         mutex_lock(&nvm_mutex);
1696
1697         return 0;
1698 }
1699
1700 /**
1701  *  e1000_release_nvm_ich8lan - Release NVM mutex
1702  *  @hw: pointer to the HW structure
1703  *
1704  *  Releases the mutex used while performing NVM operations.
1705  **/
1706 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1707 {
1708         mutex_unlock(&nvm_mutex);
1709 }
1710
1711 /**
1712  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1713  *  @hw: pointer to the HW structure
1714  *
1715  *  Acquires the software control flag for performing PHY and select
1716  *  MAC CSR accesses.
1717  **/
1718 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1719 {
1720         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1721         s32 ret_val = 0;
1722
1723         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1724                              &hw->adapter->state)) {
1725                 e_dbg("contention for Phy access\n");
1726                 return -E1000_ERR_PHY;
1727         }
1728
1729         while (timeout) {
1730                 extcnf_ctrl = er32(EXTCNF_CTRL);
1731                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1732                         break;
1733
1734                 mdelay(1);
1735                 timeout--;
1736         }
1737
1738         if (!timeout) {
1739                 e_dbg("SW has already locked the resource.\n");
1740                 ret_val = -E1000_ERR_CONFIG;
1741                 goto out;
1742         }
1743
1744         timeout = SW_FLAG_TIMEOUT;
1745
1746         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1747         ew32(EXTCNF_CTRL, extcnf_ctrl);
1748
1749         while (timeout) {
1750                 extcnf_ctrl = er32(EXTCNF_CTRL);
1751                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1752                         break;
1753
1754                 mdelay(1);
1755                 timeout--;
1756         }
1757
1758         if (!timeout) {
1759                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1760                       er32(FWSM), extcnf_ctrl);
1761                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1762                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1763                 ret_val = -E1000_ERR_CONFIG;
1764                 goto out;
1765         }
1766
1767 out:
1768         if (ret_val)
1769                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1770
1771         return ret_val;
1772 }
1773
1774 /**
1775  *  e1000_release_swflag_ich8lan - Release software control flag
1776  *  @hw: pointer to the HW structure
1777  *
1778  *  Releases the software control flag for performing PHY and select
1779  *  MAC CSR accesses.
1780  **/
1781 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1782 {
1783         u32 extcnf_ctrl;
1784
1785         extcnf_ctrl = er32(EXTCNF_CTRL);
1786
1787         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1788                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1789                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1790         } else {
1791                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1792         }
1793
1794         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1795 }
1796
1797 /**
1798  *  e1000_check_mng_mode_ich8lan - Checks management mode
1799  *  @hw: pointer to the HW structure
1800  *
1801  *  This checks if the adapter has any manageability enabled.
1802  *  This is a function pointer entry point only called by read/write
1803  *  routines for the PHY and NVM parts.
1804  **/
1805 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1806 {
1807         u32 fwsm;
1808
1809         fwsm = er32(FWSM);
1810         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1811                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1812                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1813 }
1814
1815 /**
1816  *  e1000_check_mng_mode_pchlan - Checks management mode
1817  *  @hw: pointer to the HW structure
1818  *
1819  *  This checks if the adapter has iAMT enabled.
1820  *  This is a function pointer entry point only called by read/write
1821  *  routines for the PHY and NVM parts.
1822  **/
1823 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1824 {
1825         u32 fwsm;
1826
1827         fwsm = er32(FWSM);
1828         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1829             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1830 }
1831
1832 /**
1833  *  e1000_rar_set_pch2lan - Set receive address register
1834  *  @hw: pointer to the HW structure
1835  *  @addr: pointer to the receive address
1836  *  @index: receive address array register
1837  *
1838  *  Sets the receive address array register at index to the address passed
1839  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1840  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1841  *  Use SHRA[0-3] in place of those reserved for ME.
1842  **/
1843 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1844 {
1845         u32 rar_low, rar_high;
1846
1847         /* HW expects these in little endian so we reverse the byte order
1848          * from network order (big endian) to little endian
1849          */
1850         rar_low = ((u32)addr[0] |
1851                    ((u32)addr[1] << 8) |
1852                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1853
1854         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1855
1856         /* If MAC address zero, no need to set the AV bit */
1857         if (rar_low || rar_high)
1858                 rar_high |= E1000_RAH_AV;
1859
1860         if (index == 0) {
1861                 ew32(RAL(index), rar_low);
1862                 e1e_flush();
1863                 ew32(RAH(index), rar_high);
1864                 e1e_flush();
1865                 return 0;
1866         }
1867
1868         /* RAR[1-6] are owned by manageability.  Skip those and program the
1869          * next address into the SHRA register array.
1870          */
1871         if (index < (u32)(hw->mac.rar_entry_count)) {
1872                 s32 ret_val;
1873
1874                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1875                 if (ret_val)
1876                         goto out;
1877
1878                 ew32(SHRAL(index - 1), rar_low);
1879                 e1e_flush();
1880                 ew32(SHRAH(index - 1), rar_high);
1881                 e1e_flush();
1882
1883                 e1000_release_swflag_ich8lan(hw);
1884
1885                 /* verify the register updates */
1886                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1887                     (er32(SHRAH(index - 1)) == rar_high))
1888                         return 0;
1889
1890                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1891                       (index - 1), er32(FWSM));
1892         }
1893
1894 out:
1895         e_dbg("Failed to write receive address at index %d\n", index);
1896         return -E1000_ERR_CONFIG;
1897 }
1898
1899 /**
1900  *  e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1901  *  @hw: pointer to the HW structure
1902  *
1903  *  Get the number of available receive registers that the Host can
1904  *  program. SHRA[0-10] are the shared receive address registers
1905  *  that are shared between the Host and manageability engine (ME).
1906  *  ME can reserve any number of addresses and the host needs to be
1907  *  able to tell how many available registers it has access to.
1908  **/
1909 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1910 {
1911         u32 wlock_mac;
1912         u32 num_entries;
1913
1914         wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1915         wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1916
1917         switch (wlock_mac) {
1918         case 0:
1919                 /* All SHRA[0..10] and RAR[0] available */
1920                 num_entries = hw->mac.rar_entry_count;
1921                 break;
1922         case 1:
1923                 /* Only RAR[0] available */
1924                 num_entries = 1;
1925                 break;
1926         default:
1927                 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1928                 num_entries = wlock_mac + 1;
1929                 break;
1930         }
1931
1932         return num_entries;
1933 }
1934
1935 /**
1936  *  e1000_rar_set_pch_lpt - Set receive address registers
1937  *  @hw: pointer to the HW structure
1938  *  @addr: pointer to the receive address
1939  *  @index: receive address array register
1940  *
1941  *  Sets the receive address register array at index to the address passed
1942  *  in by addr. For LPT, RAR[0] is the base address register that is to
1943  *  contain the MAC address. SHRA[0-10] are the shared receive address
1944  *  registers that are shared between the Host and manageability engine (ME).
1945  **/
1946 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1947 {
1948         u32 rar_low, rar_high;
1949         u32 wlock_mac;
1950
1951         /* HW expects these in little endian so we reverse the byte order
1952          * from network order (big endian) to little endian
1953          */
1954         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1955                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1956
1957         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1958
1959         /* If MAC address zero, no need to set the AV bit */
1960         if (rar_low || rar_high)
1961                 rar_high |= E1000_RAH_AV;
1962
1963         if (index == 0) {
1964                 ew32(RAL(index), rar_low);
1965                 e1e_flush();
1966                 ew32(RAH(index), rar_high);
1967                 e1e_flush();
1968                 return 0;
1969         }
1970
1971         /* The manageability engine (ME) can lock certain SHRAR registers that
1972          * it is using - those registers are unavailable for use.
1973          */
1974         if (index < hw->mac.rar_entry_count) {
1975                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1976                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1977
1978                 /* Check if all SHRAR registers are locked */
1979                 if (wlock_mac == 1)
1980                         goto out;
1981
1982                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1983                         s32 ret_val;
1984
1985                         ret_val = e1000_acquire_swflag_ich8lan(hw);
1986
1987                         if (ret_val)
1988                                 goto out;
1989
1990                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1991                         e1e_flush();
1992                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1993                         e1e_flush();
1994
1995                         e1000_release_swflag_ich8lan(hw);
1996
1997                         /* verify the register updates */
1998                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1999                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
2000                                 return 0;
2001                 }
2002         }
2003
2004 out:
2005         e_dbg("Failed to write receive address at index %d\n", index);
2006         return -E1000_ERR_CONFIG;
2007 }
2008
2009 /**
2010  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2011  *  @hw: pointer to the HW structure
2012  *
2013  *  Checks if firmware is blocking the reset of the PHY.
2014  *  This is a function pointer entry point only called by
2015  *  reset routines.
2016  **/
2017 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2018 {
2019         bool blocked = false;
2020         int i = 0;
2021
2022         while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2023                (i++ < 30))
2024                 usleep_range(10000, 20000);
2025         return blocked ? E1000_BLK_PHY_RESET : 0;
2026 }
2027
2028 /**
2029  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2030  *  @hw: pointer to the HW structure
2031  *
2032  *  Assumes semaphore already acquired.
2033  *
2034  **/
2035 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2036 {
2037         u16 phy_data;
2038         u32 strap = er32(STRAP);
2039         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2040             E1000_STRAP_SMT_FREQ_SHIFT;
2041         s32 ret_val;
2042
2043         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2044
2045         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2046         if (ret_val)
2047                 return ret_val;
2048
2049         phy_data &= ~HV_SMB_ADDR_MASK;
2050         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2051         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2052
2053         if (hw->phy.type == e1000_phy_i217) {
2054                 /* Restore SMBus frequency */
2055                 if (freq--) {
2056                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2057                         phy_data |= (freq & BIT(0)) <<
2058                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
2059                         phy_data |= (freq & BIT(1)) <<
2060                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2061                 } else {
2062                         e_dbg("Unsupported SMB frequency in PHY\n");
2063                 }
2064         }
2065
2066         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2067 }
2068
2069 /**
2070  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2071  *  @hw:   pointer to the HW structure
2072  *
2073  *  SW should configure the LCD from the NVM extended configuration region
2074  *  as a workaround for certain parts.
2075  **/
2076 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2077 {
2078         struct e1000_phy_info *phy = &hw->phy;
2079         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2080         s32 ret_val = 0;
2081         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2082
2083         /* Initialize the PHY from the NVM on ICH platforms.  This
2084          * is needed due to an issue where the NVM configuration is
2085          * not properly autoloaded after power transitions.
2086          * Therefore, after each PHY reset, we will load the
2087          * configuration data out of the NVM manually.
2088          */
2089         switch (hw->mac.type) {
2090         case e1000_ich8lan:
2091                 if (phy->type != e1000_phy_igp_3)
2092                         return ret_val;
2093
2094                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2095                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2096                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2097                         break;
2098                 }
2099                 /* Fall-thru */
2100         case e1000_pchlan:
2101         case e1000_pch2lan:
2102         case e1000_pch_lpt:
2103         case e1000_pch_spt:
2104         case e1000_pch_cnp:
2105                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2106                 break;
2107         default:
2108                 return ret_val;
2109         }
2110
2111         ret_val = hw->phy.ops.acquire(hw);
2112         if (ret_val)
2113                 return ret_val;
2114
2115         data = er32(FEXTNVM);
2116         if (!(data & sw_cfg_mask))
2117                 goto release;
2118
2119         /* Make sure HW does not configure LCD from PHY
2120          * extended configuration before SW configuration
2121          */
2122         data = er32(EXTCNF_CTRL);
2123         if ((hw->mac.type < e1000_pch2lan) &&
2124             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2125                 goto release;
2126
2127         cnf_size = er32(EXTCNF_SIZE);
2128         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2129         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2130         if (!cnf_size)
2131                 goto release;
2132
2133         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2134         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2135
2136         if (((hw->mac.type == e1000_pchlan) &&
2137              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2138             (hw->mac.type > e1000_pchlan)) {
2139                 /* HW configures the SMBus address and LEDs when the
2140                  * OEM and LCD Write Enable bits are set in the NVM.
2141                  * When both NVM bits are cleared, SW will configure
2142                  * them instead.
2143                  */
2144                 ret_val = e1000_write_smbus_addr(hw);
2145                 if (ret_val)
2146                         goto release;
2147
2148                 data = er32(LEDCTL);
2149                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2150                                                         (u16)data);
2151                 if (ret_val)
2152                         goto release;
2153         }
2154
2155         /* Configure LCD from extended configuration region. */
2156
2157         /* cnf_base_addr is in DWORD */
2158         word_addr = (u16)(cnf_base_addr << 1);
2159
2160         for (i = 0; i < cnf_size; i++) {
2161                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
2162                 if (ret_val)
2163                         goto release;
2164
2165                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2166                                          1, &reg_addr);
2167                 if (ret_val)
2168                         goto release;
2169
2170                 /* Save off the PHY page for future writes. */
2171                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2172                         phy_page = reg_data;
2173                         continue;
2174                 }
2175
2176                 reg_addr &= PHY_REG_MASK;
2177                 reg_addr |= phy_page;
2178
2179                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2180                 if (ret_val)
2181                         goto release;
2182         }
2183
2184 release:
2185         hw->phy.ops.release(hw);
2186         return ret_val;
2187 }
2188
2189 /**
2190  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2191  *  @hw:   pointer to the HW structure
2192  *  @link: link up bool flag
2193  *
2194  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2195  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2196  *  If link is down, the function will restore the default K1 setting located
2197  *  in the NVM.
2198  **/
2199 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2200 {
2201         s32 ret_val = 0;
2202         u16 status_reg = 0;
2203         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2204
2205         if (hw->mac.type != e1000_pchlan)
2206                 return 0;
2207
2208         /* Wrap the whole flow with the sw flag */
2209         ret_val = hw->phy.ops.acquire(hw);
2210         if (ret_val)
2211                 return ret_val;
2212
2213         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2214         if (link) {
2215                 if (hw->phy.type == e1000_phy_82578) {
2216                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2217                                                   &status_reg);
2218                         if (ret_val)
2219                                 goto release;
2220
2221                         status_reg &= (BM_CS_STATUS_LINK_UP |
2222                                        BM_CS_STATUS_RESOLVED |
2223                                        BM_CS_STATUS_SPEED_MASK);
2224
2225                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2226                                            BM_CS_STATUS_RESOLVED |
2227                                            BM_CS_STATUS_SPEED_1000))
2228                                 k1_enable = false;
2229                 }
2230
2231                 if (hw->phy.type == e1000_phy_82577) {
2232                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2233                         if (ret_val)
2234                                 goto release;
2235
2236                         status_reg &= (HV_M_STATUS_LINK_UP |
2237                                        HV_M_STATUS_AUTONEG_COMPLETE |
2238                                        HV_M_STATUS_SPEED_MASK);
2239
2240                         if (status_reg == (HV_M_STATUS_LINK_UP |
2241                                            HV_M_STATUS_AUTONEG_COMPLETE |
2242                                            HV_M_STATUS_SPEED_1000))
2243                                 k1_enable = false;
2244                 }
2245
2246                 /* Link stall fix for link up */
2247                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2248                 if (ret_val)
2249                         goto release;
2250
2251         } else {
2252                 /* Link stall fix for link down */
2253                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2254                 if (ret_val)
2255                         goto release;
2256         }
2257
2258         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2259
2260 release:
2261         hw->phy.ops.release(hw);
2262
2263         return ret_val;
2264 }
2265
2266 /**
2267  *  e1000_configure_k1_ich8lan - Configure K1 power state
2268  *  @hw: pointer to the HW structure
2269  *  @enable: K1 state to configure
2270  *
2271  *  Configure the K1 power state based on the provided parameter.
2272  *  Assumes semaphore already acquired.
2273  *
2274  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2275  **/
2276 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2277 {
2278         s32 ret_val;
2279         u32 ctrl_reg = 0;
2280         u32 ctrl_ext = 0;
2281         u32 reg = 0;
2282         u16 kmrn_reg = 0;
2283
2284         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2285                                               &kmrn_reg);
2286         if (ret_val)
2287                 return ret_val;
2288
2289         if (k1_enable)
2290                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2291         else
2292                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2293
2294         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2295                                                kmrn_reg);
2296         if (ret_val)
2297                 return ret_val;
2298
2299         usleep_range(20, 40);
2300         ctrl_ext = er32(CTRL_EXT);
2301         ctrl_reg = er32(CTRL);
2302
2303         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2304         reg |= E1000_CTRL_FRCSPD;
2305         ew32(CTRL, reg);
2306
2307         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2308         e1e_flush();
2309         usleep_range(20, 40);
2310         ew32(CTRL, ctrl_reg);
2311         ew32(CTRL_EXT, ctrl_ext);
2312         e1e_flush();
2313         usleep_range(20, 40);
2314
2315         return 0;
2316 }
2317
2318 /**
2319  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2320  *  @hw:       pointer to the HW structure
2321  *  @d0_state: boolean if entering d0 or d3 device state
2322  *
2323  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2324  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2325  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2326  **/
2327 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2328 {
2329         s32 ret_val = 0;
2330         u32 mac_reg;
2331         u16 oem_reg;
2332
2333         if (hw->mac.type < e1000_pchlan)
2334                 return ret_val;
2335
2336         ret_val = hw->phy.ops.acquire(hw);
2337         if (ret_val)
2338                 return ret_val;
2339
2340         if (hw->mac.type == e1000_pchlan) {
2341                 mac_reg = er32(EXTCNF_CTRL);
2342                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2343                         goto release;
2344         }
2345
2346         mac_reg = er32(FEXTNVM);
2347         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2348                 goto release;
2349
2350         mac_reg = er32(PHY_CTRL);
2351
2352         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2353         if (ret_val)
2354                 goto release;
2355
2356         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2357
2358         if (d0_state) {
2359                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2360                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2361
2362                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2363                         oem_reg |= HV_OEM_BITS_LPLU;
2364         } else {
2365                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2366                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2367                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2368
2369                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2370                                E1000_PHY_CTRL_NOND0A_LPLU))
2371                         oem_reg |= HV_OEM_BITS_LPLU;
2372         }
2373
2374         /* Set Restart auto-neg to activate the bits */
2375         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2376             !hw->phy.ops.check_reset_block(hw))
2377                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2378
2379         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2380
2381 release:
2382         hw->phy.ops.release(hw);
2383
2384         return ret_val;
2385 }
2386
2387 /**
2388  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2389  *  @hw:   pointer to the HW structure
2390  **/
2391 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2392 {
2393         s32 ret_val;
2394         u16 data;
2395
2396         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2397         if (ret_val)
2398                 return ret_val;
2399
2400         data |= HV_KMRN_MDIO_SLOW;
2401
2402         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2403
2404         return ret_val;
2405 }
2406
2407 /**
2408  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2409  *  done after every PHY reset.
2410  **/
2411 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2412 {
2413         s32 ret_val = 0;
2414         u16 phy_data;
2415
2416         if (hw->mac.type != e1000_pchlan)
2417                 return 0;
2418
2419         /* Set MDIO slow mode before any other MDIO access */
2420         if (hw->phy.type == e1000_phy_82577) {
2421                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2422                 if (ret_val)
2423                         return ret_val;
2424         }
2425
2426         if (((hw->phy.type == e1000_phy_82577) &&
2427              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2428             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2429                 /* Disable generation of early preamble */
2430                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2431                 if (ret_val)
2432                         return ret_val;
2433
2434                 /* Preamble tuning for SSC */
2435                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2436                 if (ret_val)
2437                         return ret_val;
2438         }
2439
2440         if (hw->phy.type == e1000_phy_82578) {
2441                 /* Return registers to default by doing a soft reset then
2442                  * writing 0x3140 to the control register.
2443                  */
2444                 if (hw->phy.revision < 2) {
2445                         e1000e_phy_sw_reset(hw);
2446                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2447                         if (ret_val)
2448                                 return ret_val;
2449                 }
2450         }
2451
2452         /* Select page 0 */
2453         ret_val = hw->phy.ops.acquire(hw);
2454         if (ret_val)
2455                 return ret_val;
2456
2457         hw->phy.addr = 1;
2458         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2459         hw->phy.ops.release(hw);
2460         if (ret_val)
2461                 return ret_val;
2462
2463         /* Configure the K1 Si workaround during phy reset assuming there is
2464          * link so that it disables K1 if link is in 1Gbps.
2465          */
2466         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2467         if (ret_val)
2468                 return ret_val;
2469
2470         /* Workaround for link disconnects on a busy hub in half duplex */
2471         ret_val = hw->phy.ops.acquire(hw);
2472         if (ret_val)
2473                 return ret_val;
2474         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2475         if (ret_val)
2476                 goto release;
2477         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2478         if (ret_val)
2479                 goto release;
2480
2481         /* set MSE higher to enable link to stay up when noise is high */
2482         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2483 release:
2484         hw->phy.ops.release(hw);
2485
2486         return ret_val;
2487 }
2488
2489 /**
2490  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2491  *  @hw:   pointer to the HW structure
2492  **/
2493 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2494 {
2495         u32 mac_reg;
2496         u16 i, phy_reg = 0;
2497         s32 ret_val;
2498
2499         ret_val = hw->phy.ops.acquire(hw);
2500         if (ret_val)
2501                 return;
2502         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2503         if (ret_val)
2504                 goto release;
2505
2506         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2507         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2508                 mac_reg = er32(RAL(i));
2509                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2510                                            (u16)(mac_reg & 0xFFFF));
2511                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2512                                            (u16)((mac_reg >> 16) & 0xFFFF));
2513
2514                 mac_reg = er32(RAH(i));
2515                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2516                                            (u16)(mac_reg & 0xFFFF));
2517                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2518                                            (u16)((mac_reg & E1000_RAH_AV)
2519                                                  >> 16));
2520         }
2521
2522         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2523
2524 release:
2525         hw->phy.ops.release(hw);
2526 }
2527
2528 /**
2529  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2530  *  with 82579 PHY
2531  *  @hw: pointer to the HW structure
2532  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2533  **/
2534 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2535 {
2536         s32 ret_val = 0;
2537         u16 phy_reg, data;
2538         u32 mac_reg;
2539         u16 i;
2540
2541         if (hw->mac.type < e1000_pch2lan)
2542                 return 0;
2543
2544         /* disable Rx path while enabling/disabling workaround */
2545         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2546         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2547         if (ret_val)
2548                 return ret_val;
2549
2550         if (enable) {
2551                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2552                  * SHRAL/H) and initial CRC values to the MAC
2553                  */
2554                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2555                         u8 mac_addr[ETH_ALEN] = { 0 };
2556                         u32 addr_high, addr_low;
2557
2558                         addr_high = er32(RAH(i));
2559                         if (!(addr_high & E1000_RAH_AV))
2560                                 continue;
2561                         addr_low = er32(RAL(i));
2562                         mac_addr[0] = (addr_low & 0xFF);
2563                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2564                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2565                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2566                         mac_addr[4] = (addr_high & 0xFF);
2567                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2568
2569                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2570                 }
2571
2572                 /* Write Rx addresses to the PHY */
2573                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2574
2575                 /* Enable jumbo frame workaround in the MAC */
2576                 mac_reg = er32(FFLT_DBG);
2577                 mac_reg &= ~BIT(14);
2578                 mac_reg |= (7 << 15);
2579                 ew32(FFLT_DBG, mac_reg);
2580
2581                 mac_reg = er32(RCTL);
2582                 mac_reg |= E1000_RCTL_SECRC;
2583                 ew32(RCTL, mac_reg);
2584
2585                 ret_val = e1000e_read_kmrn_reg(hw,
2586                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2587                                                &data);
2588                 if (ret_val)
2589                         return ret_val;
2590                 ret_val = e1000e_write_kmrn_reg(hw,
2591                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2592                                                 data | BIT(0));
2593                 if (ret_val)
2594                         return ret_val;
2595                 ret_val = e1000e_read_kmrn_reg(hw,
2596                                                E1000_KMRNCTRLSTA_HD_CTRL,
2597                                                &data);
2598                 if (ret_val)
2599                         return ret_val;
2600                 data &= ~(0xF << 8);
2601                 data |= (0xB << 8);
2602                 ret_val = e1000e_write_kmrn_reg(hw,
2603                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2604                                                 data);
2605                 if (ret_val)
2606                         return ret_val;
2607
2608                 /* Enable jumbo frame workaround in the PHY */
2609                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2610                 data &= ~(0x7F << 5);
2611                 data |= (0x37 << 5);
2612                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2613                 if (ret_val)
2614                         return ret_val;
2615                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2616                 data &= ~BIT(13);
2617                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2618                 if (ret_val)
2619                         return ret_val;
2620                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2621                 data &= ~(0x3FF << 2);
2622                 data |= (E1000_TX_PTR_GAP << 2);
2623                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2624                 if (ret_val)
2625                         return ret_val;
2626                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2627                 if (ret_val)
2628                         return ret_val;
2629                 e1e_rphy(hw, HV_PM_CTRL, &data);
2630                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2631                 if (ret_val)
2632                         return ret_val;
2633         } else {
2634                 /* Write MAC register values back to h/w defaults */
2635                 mac_reg = er32(FFLT_DBG);
2636                 mac_reg &= ~(0xF << 14);
2637                 ew32(FFLT_DBG, mac_reg);
2638
2639                 mac_reg = er32(RCTL);
2640                 mac_reg &= ~E1000_RCTL_SECRC;
2641                 ew32(RCTL, mac_reg);
2642
2643                 ret_val = e1000e_read_kmrn_reg(hw,
2644                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2645                                                &data);
2646                 if (ret_val)
2647                         return ret_val;
2648                 ret_val = e1000e_write_kmrn_reg(hw,
2649                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2650                                                 data & ~BIT(0));
2651                 if (ret_val)
2652                         return ret_val;
2653                 ret_val = e1000e_read_kmrn_reg(hw,
2654                                                E1000_KMRNCTRLSTA_HD_CTRL,
2655                                                &data);
2656                 if (ret_val)
2657                         return ret_val;
2658                 data &= ~(0xF << 8);
2659                 data |= (0xB << 8);
2660                 ret_val = e1000e_write_kmrn_reg(hw,
2661                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2662                                                 data);
2663                 if (ret_val)
2664                         return ret_val;
2665
2666                 /* Write PHY register values back to h/w defaults */
2667                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2668                 data &= ~(0x7F << 5);
2669                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2670                 if (ret_val)
2671                         return ret_val;
2672                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2673                 data |= BIT(13);
2674                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2675                 if (ret_val)
2676                         return ret_val;
2677                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2678                 data &= ~(0x3FF << 2);
2679                 data |= (0x8 << 2);
2680                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2681                 if (ret_val)
2682                         return ret_val;
2683                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2684                 if (ret_val)
2685                         return ret_val;
2686                 e1e_rphy(hw, HV_PM_CTRL, &data);
2687                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2688                 if (ret_val)
2689                         return ret_val;
2690         }
2691
2692         /* re-enable Rx path after enabling/disabling workaround */
2693         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2694 }
2695
2696 /**
2697  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2698  *  done after every PHY reset.
2699  **/
2700 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2701 {
2702         s32 ret_val = 0;
2703
2704         if (hw->mac.type != e1000_pch2lan)
2705                 return 0;
2706
2707         /* Set MDIO slow mode before any other MDIO access */
2708         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2709         if (ret_val)
2710                 return ret_val;
2711
2712         ret_val = hw->phy.ops.acquire(hw);
2713         if (ret_val)
2714                 return ret_val;
2715         /* set MSE higher to enable link to stay up when noise is high */
2716         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2717         if (ret_val)
2718                 goto release;
2719         /* drop link after 5 times MSE threshold was reached */
2720         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2721 release:
2722         hw->phy.ops.release(hw);
2723
2724         return ret_val;
2725 }
2726
2727 /**
2728  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2729  *  @hw:   pointer to the HW structure
2730  *
2731  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2732  *  Disable K1 in 1000Mbps and 100Mbps
2733  **/
2734 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2735 {
2736         s32 ret_val = 0;
2737         u16 status_reg = 0;
2738
2739         if (hw->mac.type != e1000_pch2lan)
2740                 return 0;
2741
2742         /* Set K1 beacon duration based on 10Mbs speed */
2743         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2744         if (ret_val)
2745                 return ret_val;
2746
2747         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2748             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2749                 if (status_reg &
2750                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2751                         u16 pm_phy_reg;
2752
2753                         /* LV 1G/100 Packet drop issue wa  */
2754                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2755                         if (ret_val)
2756                                 return ret_val;
2757                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2758                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2759                         if (ret_val)
2760                                 return ret_val;
2761                 } else {
2762                         u32 mac_reg;
2763
2764                         mac_reg = er32(FEXTNVM4);
2765                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2766                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2767                         ew32(FEXTNVM4, mac_reg);
2768                 }
2769         }
2770
2771         return ret_val;
2772 }
2773
2774 /**
2775  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2776  *  @hw:   pointer to the HW structure
2777  *  @gate: boolean set to true to gate, false to ungate
2778  *
2779  *  Gate/ungate the automatic PHY configuration via hardware; perform
2780  *  the configuration via software instead.
2781  **/
2782 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2783 {
2784         u32 extcnf_ctrl;
2785
2786         if (hw->mac.type < e1000_pch2lan)
2787                 return;
2788
2789         extcnf_ctrl = er32(EXTCNF_CTRL);
2790
2791         if (gate)
2792                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2793         else
2794                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2795
2796         ew32(EXTCNF_CTRL, extcnf_ctrl);
2797 }
2798
2799 /**
2800  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2801  *  @hw: pointer to the HW structure
2802  *
2803  *  Check the appropriate indication the MAC has finished configuring the
2804  *  PHY after a software reset.
2805  **/
2806 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2807 {
2808         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2809
2810         /* Wait for basic configuration completes before proceeding */
2811         do {
2812                 data = er32(STATUS);
2813                 data &= E1000_STATUS_LAN_INIT_DONE;
2814                 usleep_range(100, 200);
2815         } while ((!data) && --loop);
2816
2817         /* If basic configuration is incomplete before the above loop
2818          * count reaches 0, loading the configuration from NVM will
2819          * leave the PHY in a bad state possibly resulting in no link.
2820          */
2821         if (loop == 0)
2822                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2823
2824         /* Clear the Init Done bit for the next init event */
2825         data = er32(STATUS);
2826         data &= ~E1000_STATUS_LAN_INIT_DONE;
2827         ew32(STATUS, data);
2828 }
2829
2830 /**
2831  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2832  *  @hw: pointer to the HW structure
2833  **/
2834 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2835 {
2836         s32 ret_val = 0;
2837         u16 reg;
2838
2839         if (hw->phy.ops.check_reset_block(hw))
2840                 return 0;
2841
2842         /* Allow time for h/w to get to quiescent state after reset */
2843         usleep_range(10000, 20000);
2844
2845         /* Perform any necessary post-reset workarounds */
2846         switch (hw->mac.type) {
2847         case e1000_pchlan:
2848                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2849                 if (ret_val)
2850                         return ret_val;
2851                 break;
2852         case e1000_pch2lan:
2853                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2854                 if (ret_val)
2855                         return ret_val;
2856                 break;
2857         default:
2858                 break;
2859         }
2860
2861         /* Clear the host wakeup bit after lcd reset */
2862         if (hw->mac.type >= e1000_pchlan) {
2863                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2864                 reg &= ~BM_WUC_HOST_WU_BIT;
2865                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2866         }
2867
2868         /* Configure the LCD with the extended configuration region in NVM */
2869         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2870         if (ret_val)
2871                 return ret_val;
2872
2873         /* Configure the LCD with the OEM bits in NVM */
2874         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2875
2876         if (hw->mac.type == e1000_pch2lan) {
2877                 /* Ungate automatic PHY configuration on non-managed 82579 */
2878                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2879                         usleep_range(10000, 20000);
2880                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2881                 }
2882
2883                 /* Set EEE LPI Update Timer to 200usec */
2884                 ret_val = hw->phy.ops.acquire(hw);
2885                 if (ret_val)
2886                         return ret_val;
2887                 ret_val = e1000_write_emi_reg_locked(hw,
2888                                                      I82579_LPI_UPDATE_TIMER,
2889                                                      0x1387);
2890                 hw->phy.ops.release(hw);
2891         }
2892
2893         return ret_val;
2894 }
2895
2896 /**
2897  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2898  *  @hw: pointer to the HW structure
2899  *
2900  *  Resets the PHY
2901  *  This is a function pointer entry point called by drivers
2902  *  or other shared routines.
2903  **/
2904 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2905 {
2906         s32 ret_val = 0;
2907
2908         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2909         if ((hw->mac.type == e1000_pch2lan) &&
2910             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2911                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2912
2913         ret_val = e1000e_phy_hw_reset_generic(hw);
2914         if (ret_val)
2915                 return ret_val;
2916
2917         return e1000_post_phy_reset_ich8lan(hw);
2918 }
2919
2920 /**
2921  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2922  *  @hw: pointer to the HW structure
2923  *  @active: true to enable LPLU, false to disable
2924  *
2925  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2926  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2927  *  the phy speed. This function will manually set the LPLU bit and restart
2928  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2929  *  since it configures the same bit.
2930  **/
2931 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2932 {
2933         s32 ret_val;
2934         u16 oem_reg;
2935
2936         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2937         if (ret_val)
2938                 return ret_val;
2939
2940         if (active)
2941                 oem_reg |= HV_OEM_BITS_LPLU;
2942         else
2943                 oem_reg &= ~HV_OEM_BITS_LPLU;
2944
2945         if (!hw->phy.ops.check_reset_block(hw))
2946                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2947
2948         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2949 }
2950
2951 /**
2952  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2953  *  @hw: pointer to the HW structure
2954  *  @active: true to enable LPLU, false to disable
2955  *
2956  *  Sets the LPLU D0 state according to the active flag.  When
2957  *  activating LPLU this function also disables smart speed
2958  *  and vice versa.  LPLU will not be activated unless the
2959  *  device autonegotiation advertisement meets standards of
2960  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2961  *  This is a function pointer entry point only called by
2962  *  PHY setup routines.
2963  **/
2964 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2965 {
2966         struct e1000_phy_info *phy = &hw->phy;
2967         u32 phy_ctrl;
2968         s32 ret_val = 0;
2969         u16 data;
2970
2971         if (phy->type == e1000_phy_ife)
2972                 return 0;
2973
2974         phy_ctrl = er32(PHY_CTRL);
2975
2976         if (active) {
2977                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2978                 ew32(PHY_CTRL, phy_ctrl);
2979
2980                 if (phy->type != e1000_phy_igp_3)
2981                         return 0;
2982
2983                 /* Call gig speed drop workaround on LPLU before accessing
2984                  * any PHY registers
2985                  */
2986                 if (hw->mac.type == e1000_ich8lan)
2987                         e1000e_gig_downshift_workaround_ich8lan(hw);
2988
2989                 /* When LPLU is enabled, we should disable SmartSpeed */
2990                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2991                 if (ret_val)
2992                         return ret_val;
2993                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2994                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2995                 if (ret_val)
2996                         return ret_val;
2997         } else {
2998                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2999                 ew32(PHY_CTRL, phy_ctrl);
3000
3001                 if (phy->type != e1000_phy_igp_3)
3002                         return 0;
3003
3004                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3005                  * during Dx states where the power conservation is most
3006                  * important.  During driver activity we should enable
3007                  * SmartSpeed, so performance is maintained.
3008                  */
3009                 if (phy->smart_speed == e1000_smart_speed_on) {
3010                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3011                                            &data);
3012                         if (ret_val)
3013                                 return ret_val;
3014
3015                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3016                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3017                                            data);
3018                         if (ret_val)
3019                                 return ret_val;
3020                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3021                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3022                                            &data);
3023                         if (ret_val)
3024                                 return ret_val;
3025
3026                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3027                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3028                                            data);
3029                         if (ret_val)
3030                                 return ret_val;
3031                 }
3032         }
3033
3034         return 0;
3035 }
3036
3037 /**
3038  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3039  *  @hw: pointer to the HW structure
3040  *  @active: true to enable LPLU, false to disable
3041  *
3042  *  Sets the LPLU D3 state according to the active flag.  When
3043  *  activating LPLU this function also disables smart speed
3044  *  and vice versa.  LPLU will not be activated unless the
3045  *  device autonegotiation advertisement meets standards of
3046  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3047  *  This is a function pointer entry point only called by
3048  *  PHY setup routines.
3049  **/
3050 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3051 {
3052         struct e1000_phy_info *phy = &hw->phy;
3053         u32 phy_ctrl;
3054         s32 ret_val = 0;
3055         u16 data;
3056
3057         phy_ctrl = er32(PHY_CTRL);
3058
3059         if (!active) {
3060                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3061                 ew32(PHY_CTRL, phy_ctrl);
3062
3063                 if (phy->type != e1000_phy_igp_3)
3064                         return 0;
3065
3066                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3067                  * during Dx states where the power conservation is most
3068                  * important.  During driver activity we should enable
3069                  * SmartSpeed, so performance is maintained.
3070                  */
3071                 if (phy->smart_speed == e1000_smart_speed_on) {
3072                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3073                                            &data);
3074                         if (ret_val)
3075                                 return ret_val;
3076
3077                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3078                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3079                                            data);
3080                         if (ret_val)
3081                                 return ret_val;
3082                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3083                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3084                                            &data);
3085                         if (ret_val)
3086                                 return ret_val;
3087
3088                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3089                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3090                                            data);
3091                         if (ret_val)
3092                                 return ret_val;
3093                 }
3094         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3095                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3096                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3097                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3098                 ew32(PHY_CTRL, phy_ctrl);
3099
3100                 if (phy->type != e1000_phy_igp_3)
3101                         return 0;
3102
3103                 /* Call gig speed drop workaround on LPLU before accessing
3104                  * any PHY registers
3105                  */
3106                 if (hw->mac.type == e1000_ich8lan)
3107                         e1000e_gig_downshift_workaround_ich8lan(hw);
3108
3109                 /* When LPLU is enabled, we should disable SmartSpeed */
3110                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3111                 if (ret_val)
3112                         return ret_val;
3113
3114                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3115                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3116         }
3117
3118         return ret_val;
3119 }
3120
3121 /**
3122  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3123  *  @hw: pointer to the HW structure
3124  *  @bank:  pointer to the variable that returns the active bank
3125  *
3126  *  Reads signature byte from the NVM using the flash access registers.
3127  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3128  **/
3129 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3130 {
3131         u32 eecd;
3132         struct e1000_nvm_info *nvm = &hw->nvm;
3133         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3134         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3135         u32 nvm_dword = 0;
3136         u8 sig_byte = 0;
3137         s32 ret_val;
3138
3139         switch (hw->mac.type) {
3140         case e1000_pch_spt:
3141         case e1000_pch_cnp:
3142                 bank1_offset = nvm->flash_bank_size;
3143                 act_offset = E1000_ICH_NVM_SIG_WORD;
3144
3145                 /* set bank to 0 in case flash read fails */
3146                 *bank = 0;
3147
3148                 /* Check bank 0 */
3149                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3150                                                          &nvm_dword);
3151                 if (ret_val)
3152                         return ret_val;
3153                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3154                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3155                     E1000_ICH_NVM_SIG_VALUE) {
3156                         *bank = 0;
3157                         return 0;
3158                 }
3159
3160                 /* Check bank 1 */
3161                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3162                                                          bank1_offset,
3163                                                          &nvm_dword);
3164                 if (ret_val)
3165                         return ret_val;
3166                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3167                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3168                     E1000_ICH_NVM_SIG_VALUE) {
3169                         *bank = 1;
3170                         return 0;
3171                 }
3172
3173                 e_dbg("ERROR: No valid NVM bank present\n");
3174                 return -E1000_ERR_NVM;
3175         case e1000_ich8lan:
3176         case e1000_ich9lan:
3177                 eecd = er32(EECD);
3178                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3179                     E1000_EECD_SEC1VAL_VALID_MASK) {
3180                         if (eecd & E1000_EECD_SEC1VAL)
3181                                 *bank = 1;
3182                         else
3183                                 *bank = 0;
3184
3185                         return 0;
3186                 }
3187                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3188                 /* fall-thru */
3189         default:
3190                 /* set bank to 0 in case flash read fails */
3191                 *bank = 0;
3192
3193                 /* Check bank 0 */
3194                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3195                                                         &sig_byte);
3196                 if (ret_val)
3197                         return ret_val;
3198                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3199                     E1000_ICH_NVM_SIG_VALUE) {
3200                         *bank = 0;
3201                         return 0;
3202                 }
3203
3204                 /* Check bank 1 */
3205                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3206                                                         bank1_offset,
3207                                                         &sig_byte);
3208                 if (ret_val)
3209                         return ret_val;
3210                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3211                     E1000_ICH_NVM_SIG_VALUE) {
3212                         *bank = 1;
3213                         return 0;
3214                 }
3215
3216                 e_dbg("ERROR: No valid NVM bank present\n");
3217                 return -E1000_ERR_NVM;
3218         }
3219 }
3220
3221 /**
3222  *  e1000_read_nvm_spt - NVM access for SPT
3223  *  @hw: pointer to the HW structure
3224  *  @offset: The offset (in bytes) of the word(s) to read.
3225  *  @words: Size of data to read in words.
3226  *  @data: pointer to the word(s) to read at offset.
3227  *
3228  *  Reads a word(s) from the NVM
3229  **/
3230 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3231                               u16 *data)
3232 {
3233         struct e1000_nvm_info *nvm = &hw->nvm;
3234         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3235         u32 act_offset;
3236         s32 ret_val = 0;
3237         u32 bank = 0;
3238         u32 dword = 0;
3239         u16 offset_to_read;
3240         u16 i;
3241
3242         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3243             (words == 0)) {
3244                 e_dbg("nvm parameter(s) out of bounds\n");
3245                 ret_val = -E1000_ERR_NVM;
3246                 goto out;
3247         }
3248
3249         nvm->ops.acquire(hw);
3250
3251         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3252         if (ret_val) {
3253                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3254                 bank = 0;
3255         }
3256
3257         act_offset = (bank) ? nvm->flash_bank_size : 0;
3258         act_offset += offset;
3259
3260         ret_val = 0;
3261
3262         for (i = 0; i < words; i += 2) {
3263                 if (words - i == 1) {
3264                         if (dev_spec->shadow_ram[offset + i].modified) {
3265                                 data[i] =
3266                                     dev_spec->shadow_ram[offset + i].value;
3267                         } else {
3268                                 offset_to_read = act_offset + i -
3269                                     ((act_offset + i) % 2);
3270                                 ret_val =
3271                                   e1000_read_flash_dword_ich8lan(hw,
3272                                                                  offset_to_read,
3273                                                                  &dword);
3274                                 if (ret_val)
3275                                         break;
3276                                 if ((act_offset + i) % 2 == 0)
3277                                         data[i] = (u16)(dword & 0xFFFF);
3278                                 else
3279                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3280                         }
3281                 } else {
3282                         offset_to_read = act_offset + i;
3283                         if (!(dev_spec->shadow_ram[offset + i].modified) ||
3284                             !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3285                                 ret_val =
3286                                   e1000_read_flash_dword_ich8lan(hw,
3287                                                                  offset_to_read,
3288                                                                  &dword);
3289                                 if (ret_val)
3290                                         break;
3291                         }
3292                         if (dev_spec->shadow_ram[offset + i].modified)
3293                                 data[i] =
3294                                     dev_spec->shadow_ram[offset + i].value;
3295                         else
3296                                 data[i] = (u16)(dword & 0xFFFF);
3297                         if (dev_spec->shadow_ram[offset + i].modified)
3298                                 data[i + 1] =
3299                                     dev_spec->shadow_ram[offset + i + 1].value;
3300                         else
3301                                 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3302                 }
3303         }
3304
3305         nvm->ops.release(hw);
3306
3307 out:
3308         if (ret_val)
3309                 e_dbg("NVM read error: %d\n", ret_val);
3310
3311         return ret_val;
3312 }
3313
3314 /**
3315  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3316  *  @hw: pointer to the HW structure
3317  *  @offset: The offset (in bytes) of the word(s) to read.
3318  *  @words: Size of data to read in words
3319  *  @data: Pointer to the word(s) to read at offset.
3320  *
3321  *  Reads a word(s) from the NVM using the flash access registers.
3322  **/
3323 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3324                                   u16 *data)
3325 {
3326         struct e1000_nvm_info *nvm = &hw->nvm;
3327         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3328         u32 act_offset;
3329         s32 ret_val = 0;
3330         u32 bank = 0;
3331         u16 i, word;
3332
3333         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3334             (words == 0)) {
3335                 e_dbg("nvm parameter(s) out of bounds\n");
3336                 ret_val = -E1000_ERR_NVM;
3337                 goto out;
3338         }
3339
3340         nvm->ops.acquire(hw);
3341
3342         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3343         if (ret_val) {
3344                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3345                 bank = 0;
3346         }
3347
3348         act_offset = (bank) ? nvm->flash_bank_size : 0;
3349         act_offset += offset;
3350
3351         ret_val = 0;
3352         for (i = 0; i < words; i++) {
3353                 if (dev_spec->shadow_ram[offset + i].modified) {
3354                         data[i] = dev_spec->shadow_ram[offset + i].value;
3355                 } else {
3356                         ret_val = e1000_read_flash_word_ich8lan(hw,
3357                                                                 act_offset + i,
3358                                                                 &word);
3359                         if (ret_val)
3360                                 break;
3361                         data[i] = word;
3362                 }
3363         }
3364
3365         nvm->ops.release(hw);
3366
3367 out:
3368         if (ret_val)
3369                 e_dbg("NVM read error: %d\n", ret_val);
3370
3371         return ret_val;
3372 }
3373
3374 /**
3375  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3376  *  @hw: pointer to the HW structure
3377  *
3378  *  This function does initial flash setup so that a new read/write/erase cycle
3379  *  can be started.
3380  **/
3381 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3382 {
3383         union ich8_hws_flash_status hsfsts;
3384         s32 ret_val = -E1000_ERR_NVM;
3385
3386         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3387
3388         /* Check if the flash descriptor is valid */
3389         if (!hsfsts.hsf_status.fldesvalid) {
3390                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
3391                 return -E1000_ERR_NVM;
3392         }
3393
3394         /* Clear FCERR and DAEL in hw status by writing 1 */
3395         hsfsts.hsf_status.flcerr = 1;
3396         hsfsts.hsf_status.dael = 1;
3397         if (hw->mac.type >= e1000_pch_spt)
3398                 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3399         else
3400                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3401
3402         /* Either we should have a hardware SPI cycle in progress
3403          * bit to check against, in order to start a new cycle or
3404          * FDONE bit should be changed in the hardware so that it
3405          * is 1 after hardware reset, which can then be used as an
3406          * indication whether a cycle is in progress or has been
3407          * completed.
3408          */
3409
3410         if (!hsfsts.hsf_status.flcinprog) {
3411                 /* There is no cycle running at present,
3412                  * so we can start a cycle.
3413                  * Begin by setting Flash Cycle Done.
3414                  */
3415                 hsfsts.hsf_status.flcdone = 1;
3416                 if (hw->mac.type >= e1000_pch_spt)
3417                         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3418                 else
3419                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3420                 ret_val = 0;
3421         } else {
3422                 s32 i;
3423
3424                 /* Otherwise poll for sometime so the current
3425                  * cycle has a chance to end before giving up.
3426                  */
3427                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3428                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3429                         if (!hsfsts.hsf_status.flcinprog) {
3430                                 ret_val = 0;
3431                                 break;
3432                         }
3433                         udelay(1);
3434                 }
3435                 if (!ret_val) {
3436                         /* Successful in waiting for previous cycle to timeout,
3437                          * now set the Flash Cycle Done.
3438                          */
3439                         hsfsts.hsf_status.flcdone = 1;
3440                         if (hw->mac.type >= e1000_pch_spt)
3441                                 ew32flash(ICH_FLASH_HSFSTS,
3442                                           hsfsts.regval & 0xFFFF);
3443                         else
3444                                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3445                 } else {
3446                         e_dbg("Flash controller busy, cannot get access\n");
3447                 }
3448         }
3449
3450         return ret_val;
3451 }
3452
3453 /**
3454  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3455  *  @hw: pointer to the HW structure
3456  *  @timeout: maximum time to wait for completion
3457  *
3458  *  This function starts a flash cycle and waits for its completion.
3459  **/
3460 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3461 {
3462         union ich8_hws_flash_ctrl hsflctl;
3463         union ich8_hws_flash_status hsfsts;
3464         u32 i = 0;
3465
3466         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3467         if (hw->mac.type >= e1000_pch_spt)
3468                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3469         else
3470                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3471         hsflctl.hsf_ctrl.flcgo = 1;
3472
3473         if (hw->mac.type >= e1000_pch_spt)
3474                 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3475         else
3476                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3477
3478         /* wait till FDONE bit is set to 1 */
3479         do {
3480                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3481                 if (hsfsts.hsf_status.flcdone)
3482                         break;
3483                 udelay(1);
3484         } while (i++ < timeout);
3485
3486         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3487                 return 0;
3488
3489         return -E1000_ERR_NVM;
3490 }
3491
3492 /**
3493  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3494  *  @hw: pointer to the HW structure
3495  *  @offset: offset to data location
3496  *  @data: pointer to the location for storing the data
3497  *
3498  *  Reads the flash dword at offset into data.  Offset is converted
3499  *  to bytes before read.
3500  **/
3501 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3502                                           u32 *data)
3503 {
3504         /* Must convert word offset into bytes. */
3505         offset <<= 1;
3506         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3507 }
3508
3509 /**
3510  *  e1000_read_flash_word_ich8lan - Read word from flash
3511  *  @hw: pointer to the HW structure
3512  *  @offset: offset to data location
3513  *  @data: pointer to the location for storing the data
3514  *
3515  *  Reads the flash word at offset into data.  Offset is converted
3516  *  to bytes before read.
3517  **/
3518 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3519                                          u16 *data)
3520 {
3521         /* Must convert offset into bytes. */
3522         offset <<= 1;
3523
3524         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3525 }
3526
3527 /**
3528  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3529  *  @hw: pointer to the HW structure
3530  *  @offset: The offset of the byte to read.
3531  *  @data: Pointer to a byte to store the value read.
3532  *
3533  *  Reads a single byte from the NVM using the flash access registers.
3534  **/
3535 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3536                                          u8 *data)
3537 {
3538         s32 ret_val;
3539         u16 word = 0;
3540
3541         /* In SPT, only 32 bits access is supported,
3542          * so this function should not be called.
3543          */
3544         if (hw->mac.type >= e1000_pch_spt)
3545                 return -E1000_ERR_NVM;
3546         else
3547                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3548
3549         if (ret_val)
3550                 return ret_val;
3551
3552         *data = (u8)word;
3553
3554         return 0;
3555 }
3556
3557 /**
3558  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3559  *  @hw: pointer to the HW structure
3560  *  @offset: The offset (in bytes) of the byte or word to read.
3561  *  @size: Size of data to read, 1=byte 2=word
3562  *  @data: Pointer to the word to store the value read.
3563  *
3564  *  Reads a byte or word from the NVM using the flash access registers.
3565  **/
3566 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3567                                          u8 size, u16 *data)
3568 {
3569         union ich8_hws_flash_status hsfsts;
3570         union ich8_hws_flash_ctrl hsflctl;
3571         u32 flash_linear_addr;
3572         u32 flash_data = 0;
3573         s32 ret_val = -E1000_ERR_NVM;
3574         u8 count = 0;
3575
3576         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3577                 return -E1000_ERR_NVM;
3578
3579         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3580                              hw->nvm.flash_base_addr);
3581
3582         do {
3583                 udelay(1);
3584                 /* Steps */
3585                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3586                 if (ret_val)
3587                         break;
3588
3589                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3590                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3591                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3592                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3593                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3594
3595                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3596
3597                 ret_val =
3598                     e1000_flash_cycle_ich8lan(hw,
3599                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3600
3601                 /* Check if FCERR is set to 1, if set to 1, clear it
3602                  * and try the whole sequence a few more times, else
3603                  * read in (shift in) the Flash Data0, the order is
3604                  * least significant byte first msb to lsb
3605                  */
3606                 if (!ret_val) {
3607                         flash_data = er32flash(ICH_FLASH_FDATA0);
3608                         if (size == 1)
3609                                 *data = (u8)(flash_data & 0x000000FF);
3610                         else if (size == 2)
3611                                 *data = (u16)(flash_data & 0x0000FFFF);
3612                         break;
3613                 } else {
3614                         /* If we've gotten here, then things are probably
3615                          * completely hosed, but if the error condition is
3616                          * detected, it won't hurt to give it another try...
3617                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3618                          */
3619                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3620                         if (hsfsts.hsf_status.flcerr) {
3621                                 /* Repeat for some time before giving up. */
3622                                 continue;
3623                         } else if (!hsfsts.hsf_status.flcdone) {
3624                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3625                                 break;
3626                         }
3627                 }
3628         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3629
3630         return ret_val;
3631 }
3632
3633 /**
3634  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3635  *  @hw: pointer to the HW structure
3636  *  @offset: The offset (in bytes) of the dword to read.
3637  *  @data: Pointer to the dword to store the value read.
3638  *
3639  *  Reads a byte or word from the NVM using the flash access registers.
3640  **/
3641
3642 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3643                                            u32 *data)
3644 {
3645         union ich8_hws_flash_status hsfsts;
3646         union ich8_hws_flash_ctrl hsflctl;
3647         u32 flash_linear_addr;
3648         s32 ret_val = -E1000_ERR_NVM;
3649         u8 count = 0;
3650
3651         if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3652                 return -E1000_ERR_NVM;
3653         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3654                              hw->nvm.flash_base_addr);
3655
3656         do {
3657                 udelay(1);
3658                 /* Steps */
3659                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3660                 if (ret_val)
3661                         break;
3662                 /* In SPT, This register is in Lan memory space, not flash.
3663                  * Therefore, only 32 bit access is supported
3664                  */
3665                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3666
3667                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3668                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3669                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3670                 /* In SPT, This register is in Lan memory space, not flash.
3671                  * Therefore, only 32 bit access is supported
3672                  */
3673                 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3674                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3675
3676                 ret_val =
3677                    e1000_flash_cycle_ich8lan(hw,
3678                                              ICH_FLASH_READ_COMMAND_TIMEOUT);
3679
3680                 /* Check if FCERR is set to 1, if set to 1, clear it
3681                  * and try the whole sequence a few more times, else
3682                  * read in (shift in) the Flash Data0, the order is
3683                  * least significant byte first msb to lsb
3684                  */
3685                 if (!ret_val) {
3686                         *data = er32flash(ICH_FLASH_FDATA0);
3687                         break;
3688                 } else {
3689                         /* If we've gotten here, then things are probably
3690                          * completely hosed, but if the error condition is
3691                          * detected, it won't hurt to give it another try...
3692                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3693                          */
3694                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3695                         if (hsfsts.hsf_status.flcerr) {
3696                                 /* Repeat for some time before giving up. */
3697                                 continue;
3698                         } else if (!hsfsts.hsf_status.flcdone) {
3699                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3700                                 break;
3701                         }
3702                 }
3703         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3704
3705         return ret_val;
3706 }
3707
3708 /**
3709  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3710  *  @hw: pointer to the HW structure
3711  *  @offset: The offset (in bytes) of the word(s) to write.
3712  *  @words: Size of data to write in words
3713  *  @data: Pointer to the word(s) to write at offset.
3714  *
3715  *  Writes a byte or word to the NVM using the flash access registers.
3716  **/
3717 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3718                                    u16 *data)
3719 {
3720         struct e1000_nvm_info *nvm = &hw->nvm;
3721         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3722         u16 i;
3723
3724         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3725             (words == 0)) {
3726                 e_dbg("nvm parameter(s) out of bounds\n");
3727                 return -E1000_ERR_NVM;
3728         }
3729
3730         nvm->ops.acquire(hw);
3731
3732         for (i = 0; i < words; i++) {
3733                 dev_spec->shadow_ram[offset + i].modified = true;
3734                 dev_spec->shadow_ram[offset + i].value = data[i];
3735         }
3736
3737         nvm->ops.release(hw);
3738
3739         return 0;
3740 }
3741
3742 /**
3743  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3744  *  @hw: pointer to the HW structure
3745  *
3746  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3747  *  which writes the checksum to the shadow ram.  The changes in the shadow
3748  *  ram are then committed to the EEPROM by processing each bank at a time
3749  *  checking for the modified bit and writing only the pending changes.
3750  *  After a successful commit, the shadow ram is cleared and is ready for
3751  *  future writes.
3752  **/
3753 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3754 {
3755         struct e1000_nvm_info *nvm = &hw->nvm;
3756         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3757         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3758         s32 ret_val;
3759         u32 dword = 0;
3760
3761         ret_val = e1000e_update_nvm_checksum_generic(hw);
3762         if (ret_val)
3763                 goto out;
3764
3765         if (nvm->type != e1000_nvm_flash_sw)
3766                 goto out;
3767
3768         nvm->ops.acquire(hw);
3769
3770         /* We're writing to the opposite bank so if we're on bank 1,
3771          * write to bank 0 etc.  We also need to erase the segment that
3772          * is going to be written
3773          */
3774         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3775         if (ret_val) {
3776                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3777                 bank = 0;
3778         }
3779
3780         if (bank == 0) {
3781                 new_bank_offset = nvm->flash_bank_size;
3782                 old_bank_offset = 0;
3783                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3784                 if (ret_val)
3785                         goto release;
3786         } else {
3787                 old_bank_offset = nvm->flash_bank_size;
3788                 new_bank_offset = 0;
3789                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3790                 if (ret_val)
3791                         goto release;
3792         }
3793         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3794                 /* Determine whether to write the value stored
3795                  * in the other NVM bank or a modified value stored
3796                  * in the shadow RAM
3797                  */
3798                 ret_val = e1000_read_flash_dword_ich8lan(hw,
3799                                                          i + old_bank_offset,
3800                                                          &dword);
3801
3802                 if (dev_spec->shadow_ram[i].modified) {
3803                         dword &= 0xffff0000;
3804                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3805                 }
3806                 if (dev_spec->shadow_ram[i + 1].modified) {
3807                         dword &= 0x0000ffff;
3808                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3809                                   << 16);
3810                 }
3811                 if (ret_val)
3812                         break;
3813
3814                 /* If the word is 0x13, then make sure the signature bits
3815                  * (15:14) are 11b until the commit has completed.
3816                  * This will allow us to write 10b which indicates the
3817                  * signature is valid.  We want to do this after the write
3818                  * has completed so that we don't mark the segment valid
3819                  * while the write is still in progress
3820                  */
3821                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3822                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
3823
3824                 /* Convert offset to bytes. */
3825                 act_offset = (i + new_bank_offset) << 1;
3826
3827                 usleep_range(100, 200);
3828
3829                 /* Write the data to the new bank. Offset in words */
3830                 act_offset = i + new_bank_offset;
3831                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3832                                                                 dword);
3833                 if (ret_val)
3834                         break;
3835         }
3836
3837         /* Don't bother writing the segment valid bits if sector
3838          * programming failed.
3839          */
3840         if (ret_val) {
3841                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3842                 e_dbg("Flash commit failed.\n");
3843                 goto release;
3844         }
3845
3846         /* Finally validate the new segment by setting bit 15:14
3847          * to 10b in word 0x13 , this can be done without an
3848          * erase as well since these bits are 11 to start with
3849          * and we need to change bit 14 to 0b
3850          */
3851         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3852
3853         /*offset in words but we read dword */
3854         --act_offset;
3855         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3856
3857         if (ret_val)
3858                 goto release;
3859
3860         dword &= 0xBFFFFFFF;
3861         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3862
3863         if (ret_val)
3864                 goto release;
3865
3866         /* And invalidate the previously valid segment by setting
3867          * its signature word (0x13) high_byte to 0b. This can be
3868          * done without an erase because flash erase sets all bits
3869          * to 1's. We can write 1's to 0's without an erase
3870          */
3871         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3872
3873         /* offset in words but we read dword */
3874         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3875         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3876
3877         if (ret_val)
3878                 goto release;
3879
3880         dword &= 0x00FFFFFF;
3881         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3882
3883         if (ret_val)
3884                 goto release;
3885
3886         /* Great!  Everything worked, we can now clear the cached entries. */
3887         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3888                 dev_spec->shadow_ram[i].modified = false;
3889                 dev_spec->shadow_ram[i].value = 0xFFFF;
3890         }
3891
3892 release:
3893         nvm->ops.release(hw);
3894
3895         /* Reload the EEPROM, or else modifications will not appear
3896          * until after the next adapter reset.
3897          */
3898         if (!ret_val) {
3899                 nvm->ops.reload(hw);
3900                 usleep_range(10000, 20000);
3901         }
3902
3903 out:
3904         if (ret_val)
3905                 e_dbg("NVM update error: %d\n", ret_val);
3906
3907         return ret_val;
3908 }
3909
3910 /**
3911  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3912  *  @hw: pointer to the HW structure
3913  *
3914  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3915  *  which writes the checksum to the shadow ram.  The changes in the shadow
3916  *  ram are then committed to the EEPROM by processing each bank at a time
3917  *  checking for the modified bit and writing only the pending changes.
3918  *  After a successful commit, the shadow ram is cleared and is ready for
3919  *  future writes.
3920  **/
3921 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3922 {
3923         struct e1000_nvm_info *nvm = &hw->nvm;
3924         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3925         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3926         s32 ret_val;
3927         u16 data = 0;
3928
3929         ret_val = e1000e_update_nvm_checksum_generic(hw);
3930         if (ret_val)
3931                 goto out;
3932
3933         if (nvm->type != e1000_nvm_flash_sw)
3934                 goto out;
3935
3936         nvm->ops.acquire(hw);
3937
3938         /* We're writing to the opposite bank so if we're on bank 1,
3939          * write to bank 0 etc.  We also need to erase the segment that
3940          * is going to be written
3941          */
3942         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3943         if (ret_val) {
3944                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3945                 bank = 0;
3946         }
3947
3948         if (bank == 0) {
3949                 new_bank_offset = nvm->flash_bank_size;
3950                 old_bank_offset = 0;
3951                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3952                 if (ret_val)
3953                         goto release;
3954         } else {
3955                 old_bank_offset = nvm->flash_bank_size;
3956                 new_bank_offset = 0;
3957                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3958                 if (ret_val)
3959                         goto release;
3960         }
3961         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3962                 if (dev_spec->shadow_ram[i].modified) {
3963                         data = dev_spec->shadow_ram[i].value;
3964                 } else {
3965                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3966                                                                 old_bank_offset,
3967                                                                 &data);
3968                         if (ret_val)
3969                                 break;
3970                 }
3971
3972                 /* If the word is 0x13, then make sure the signature bits
3973                  * (15:14) are 11b until the commit has completed.
3974                  * This will allow us to write 10b which indicates the
3975                  * signature is valid.  We want to do this after the write
3976                  * has completed so that we don't mark the segment valid
3977                  * while the write is still in progress
3978                  */
3979                 if (i == E1000_ICH_NVM_SIG_WORD)
3980                         data |= E1000_ICH_NVM_SIG_MASK;
3981
3982                 /* Convert offset to bytes. */
3983                 act_offset = (i + new_bank_offset) << 1;
3984
3985                 usleep_range(100, 200);
3986                 /* Write the bytes to the new bank. */
3987                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3988                                                                act_offset,
3989                                                                (u8)data);
3990                 if (ret_val)
3991                         break;
3992
3993                 usleep_range(100, 200);
3994                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3995                                                                act_offset + 1,
3996                                                                (u8)(data >> 8));
3997                 if (ret_val)
3998                         break;
3999         }
4000
4001         /* Don't bother writing the segment valid bits if sector
4002          * programming failed.
4003          */
4004         if (ret_val) {
4005                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4006                 e_dbg("Flash commit failed.\n");
4007                 goto release;
4008         }
4009
4010         /* Finally validate the new segment by setting bit 15:14
4011          * to 10b in word 0x13 , this can be done without an
4012          * erase as well since these bits are 11 to start with
4013          * and we need to change bit 14 to 0b
4014          */
4015         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4016         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4017         if (ret_val)
4018                 goto release;
4019
4020         data &= 0xBFFF;
4021         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4022                                                        act_offset * 2 + 1,
4023                                                        (u8)(data >> 8));
4024         if (ret_val)
4025                 goto release;
4026
4027         /* And invalidate the previously valid segment by setting
4028          * its signature word (0x13) high_byte to 0b. This can be
4029          * done without an erase because flash erase sets all bits
4030          * to 1's. We can write 1's to 0's without an erase
4031          */
4032         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4033         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4034         if (ret_val)
4035                 goto release;
4036
4037         /* Great!  Everything worked, we can now clear the cached entries. */
4038         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4039                 dev_spec->shadow_ram[i].modified = false;
4040                 dev_spec->shadow_ram[i].value = 0xFFFF;
4041         }
4042
4043 release:
4044         nvm->ops.release(hw);
4045
4046         /* Reload the EEPROM, or else modifications will not appear
4047          * until after the next adapter reset.
4048          */
4049         if (!ret_val) {
4050                 nvm->ops.reload(hw);
4051                 usleep_range(10000, 20000);
4052         }
4053
4054 out:
4055         if (ret_val)
4056                 e_dbg("NVM update error: %d\n", ret_val);
4057
4058         return ret_val;
4059 }
4060
4061 /**
4062  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4063  *  @hw: pointer to the HW structure
4064  *
4065  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4066  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4067  *  calculated, in which case we need to calculate the checksum and set bit 6.
4068  **/
4069 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4070 {
4071         s32 ret_val;
4072         u16 data;
4073         u16 word;
4074         u16 valid_csum_mask;
4075
4076         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4077          * the checksum needs to be fixed.  This bit is an indication that
4078          * the NVM was prepared by OEM software and did not calculate
4079          * the checksum...a likely scenario.
4080          */
4081         switch (hw->mac.type) {
4082         case e1000_pch_lpt:
4083         case e1000_pch_spt:
4084         case e1000_pch_cnp:
4085                 word = NVM_COMPAT;
4086                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4087                 break;
4088         default:
4089                 word = NVM_FUTURE_INIT_WORD1;
4090                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4091                 break;
4092         }
4093
4094         ret_val = e1000_read_nvm(hw, word, 1, &data);
4095         if (ret_val)
4096                 return ret_val;
4097
4098         if (!(data & valid_csum_mask)) {
4099                 data |= valid_csum_mask;
4100                 ret_val = e1000_write_nvm(hw, word, 1, &data);
4101                 if (ret_val)
4102                         return ret_val;
4103                 ret_val = e1000e_update_nvm_checksum(hw);
4104                 if (ret_val)
4105                         return ret_val;
4106         }
4107
4108         return e1000e_validate_nvm_checksum_generic(hw);
4109 }
4110
4111 /**
4112  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4113  *  @hw: pointer to the HW structure
4114  *
4115  *  To prevent malicious write/erase of the NVM, set it to be read-only
4116  *  so that the hardware ignores all write/erase cycles of the NVM via
4117  *  the flash control registers.  The shadow-ram copy of the NVM will
4118  *  still be updated, however any updates to this copy will not stick
4119  *  across driver reloads.
4120  **/
4121 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4122 {
4123         struct e1000_nvm_info *nvm = &hw->nvm;
4124         union ich8_flash_protected_range pr0;
4125         union ich8_hws_flash_status hsfsts;
4126         u32 gfpreg;
4127
4128         nvm->ops.acquire(hw);
4129
4130         gfpreg = er32flash(ICH_FLASH_GFPREG);
4131
4132         /* Write-protect GbE Sector of NVM */
4133         pr0.regval = er32flash(ICH_FLASH_PR0);
4134         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4135         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4136         pr0.range.wpe = true;
4137         ew32flash(ICH_FLASH_PR0, pr0.regval);
4138
4139         /* Lock down a subset of GbE Flash Control Registers, e.g.
4140          * PR0 to prevent the write-protection from being lifted.
4141          * Once FLOCKDN is set, the registers protected by it cannot
4142          * be written until FLOCKDN is cleared by a hardware reset.
4143          */
4144         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4145         hsfsts.hsf_status.flockdn = true;
4146         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4147
4148         nvm->ops.release(hw);
4149 }
4150
4151 /**
4152  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4153  *  @hw: pointer to the HW structure
4154  *  @offset: The offset (in bytes) of the byte/word to read.
4155  *  @size: Size of data to read, 1=byte 2=word
4156  *  @data: The byte(s) to write to the NVM.
4157  *
4158  *  Writes one/two bytes to the NVM using the flash access registers.
4159  **/
4160 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4161                                           u8 size, u16 data)
4162 {
4163         union ich8_hws_flash_status hsfsts;
4164         union ich8_hws_flash_ctrl hsflctl;
4165         u32 flash_linear_addr;
4166         u32 flash_data = 0;
4167         s32 ret_val;
4168         u8 count = 0;
4169
4170         if (hw->mac.type >= e1000_pch_spt) {
4171                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4172                         return -E1000_ERR_NVM;
4173         } else {
4174                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4175                         return -E1000_ERR_NVM;
4176         }
4177
4178         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4179                              hw->nvm.flash_base_addr);
4180
4181         do {
4182                 udelay(1);
4183                 /* Steps */
4184                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4185                 if (ret_val)
4186                         break;
4187                 /* In SPT, This register is in Lan memory space, not
4188                  * flash.  Therefore, only 32 bit access is supported
4189                  */
4190                 if (hw->mac.type >= e1000_pch_spt)
4191                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4192                 else
4193                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4194
4195                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4196                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4197                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4198                 /* In SPT, This register is in Lan memory space,
4199                  * not flash.  Therefore, only 32 bit access is
4200                  * supported
4201                  */
4202                 if (hw->mac.type >= e1000_pch_spt)
4203                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4204                 else
4205                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4206
4207                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4208
4209                 if (size == 1)
4210                         flash_data = (u32)data & 0x00FF;
4211                 else
4212                         flash_data = (u32)data;
4213
4214                 ew32flash(ICH_FLASH_FDATA0, flash_data);
4215
4216                 /* check if FCERR is set to 1 , if set to 1, clear it
4217                  * and try the whole sequence a few more times else done
4218                  */
4219                 ret_val =
4220                     e1000_flash_cycle_ich8lan(hw,
4221                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4222                 if (!ret_val)
4223                         break;
4224
4225                 /* If we're here, then things are most likely
4226                  * completely hosed, but if the error condition
4227                  * is detected, it won't hurt to give it another
4228                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4229                  */
4230                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4231                 if (hsfsts.hsf_status.flcerr)
4232                         /* Repeat for some time before giving up. */
4233                         continue;
4234                 if (!hsfsts.hsf_status.flcdone) {
4235                         e_dbg("Timeout error - flash cycle did not complete.\n");
4236                         break;
4237                 }
4238         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4239
4240         return ret_val;
4241 }
4242
4243 /**
4244 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4245 *  @hw: pointer to the HW structure
4246 *  @offset: The offset (in bytes) of the dwords to read.
4247 *  @data: The 4 bytes to write to the NVM.
4248 *
4249 *  Writes one/two/four bytes to the NVM using the flash access registers.
4250 **/
4251 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4252                                             u32 data)
4253 {
4254         union ich8_hws_flash_status hsfsts;
4255         union ich8_hws_flash_ctrl hsflctl;
4256         u32 flash_linear_addr;
4257         s32 ret_val;
4258         u8 count = 0;
4259
4260         if (hw->mac.type >= e1000_pch_spt) {
4261                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4262                         return -E1000_ERR_NVM;
4263         }
4264         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4265                              hw->nvm.flash_base_addr);
4266         do {
4267                 udelay(1);
4268                 /* Steps */
4269                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4270                 if (ret_val)
4271                         break;
4272
4273                 /* In SPT, This register is in Lan memory space, not
4274                  * flash.  Therefore, only 32 bit access is supported
4275                  */
4276                 if (hw->mac.type >= e1000_pch_spt)
4277                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4278                             >> 16;
4279                 else
4280                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4281
4282                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4283                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4284
4285                 /* In SPT, This register is in Lan memory space,
4286                  * not flash.  Therefore, only 32 bit access is
4287                  * supported
4288                  */
4289                 if (hw->mac.type >= e1000_pch_spt)
4290                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4291                 else
4292                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4293
4294                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4295
4296                 ew32flash(ICH_FLASH_FDATA0, data);
4297
4298                 /* check if FCERR is set to 1 , if set to 1, clear it
4299                  * and try the whole sequence a few more times else done
4300                  */
4301                 ret_val =
4302                    e1000_flash_cycle_ich8lan(hw,
4303                                              ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4304
4305                 if (!ret_val)
4306                         break;
4307
4308                 /* If we're here, then things are most likely
4309                  * completely hosed, but if the error condition
4310                  * is detected, it won't hurt to give it another
4311                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4312                  */
4313                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4314
4315                 if (hsfsts.hsf_status.flcerr)
4316                         /* Repeat for some time before giving up. */
4317                         continue;
4318                 if (!hsfsts.hsf_status.flcdone) {
4319                         e_dbg("Timeout error - flash cycle did not complete.\n");
4320                         break;
4321                 }
4322         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4323
4324         return ret_val;
4325 }
4326
4327 /**
4328  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4329  *  @hw: pointer to the HW structure
4330  *  @offset: The index of the byte to read.
4331  *  @data: The byte to write to the NVM.
4332  *
4333  *  Writes a single byte to the NVM using the flash access registers.
4334  **/
4335 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4336                                           u8 data)
4337 {
4338         u16 word = (u16)data;
4339
4340         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4341 }
4342
4343 /**
4344 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4345 *  @hw: pointer to the HW structure
4346 *  @offset: The offset of the word to write.
4347 *  @dword: The dword to write to the NVM.
4348 *
4349 *  Writes a single dword to the NVM using the flash access registers.
4350 *  Goes through a retry algorithm before giving up.
4351 **/
4352 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4353                                                  u32 offset, u32 dword)
4354 {
4355         s32 ret_val;
4356         u16 program_retries;
4357
4358         /* Must convert word offset into bytes. */
4359         offset <<= 1;
4360         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4361
4362         if (!ret_val)
4363                 return ret_val;
4364         for (program_retries = 0; program_retries < 100; program_retries++) {
4365                 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4366                 usleep_range(100, 200);
4367                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4368                 if (!ret_val)
4369                         break;
4370         }
4371         if (program_retries == 100)
4372                 return -E1000_ERR_NVM;
4373
4374         return 0;
4375 }
4376
4377 /**
4378  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4379  *  @hw: pointer to the HW structure
4380  *  @offset: The offset of the byte to write.
4381  *  @byte: The byte to write to the NVM.
4382  *
4383  *  Writes a single byte to the NVM using the flash access registers.
4384  *  Goes through a retry algorithm before giving up.
4385  **/
4386 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4387                                                 u32 offset, u8 byte)
4388 {
4389         s32 ret_val;
4390         u16 program_retries;
4391
4392         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4393         if (!ret_val)
4394                 return ret_val;
4395
4396         for (program_retries = 0; program_retries < 100; program_retries++) {
4397                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4398                 usleep_range(100, 200);
4399                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4400                 if (!ret_val)
4401                         break;
4402         }
4403         if (program_retries == 100)
4404                 return -E1000_ERR_NVM;
4405
4406         return 0;
4407 }
4408
4409 /**
4410  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4411  *  @hw: pointer to the HW structure
4412  *  @bank: 0 for first bank, 1 for second bank, etc.
4413  *
4414  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4415  *  bank N is 4096 * N + flash_reg_addr.
4416  **/
4417 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4418 {
4419         struct e1000_nvm_info *nvm = &hw->nvm;
4420         union ich8_hws_flash_status hsfsts;
4421         union ich8_hws_flash_ctrl hsflctl;
4422         u32 flash_linear_addr;
4423         /* bank size is in 16bit words - adjust to bytes */
4424         u32 flash_bank_size = nvm->flash_bank_size * 2;
4425         s32 ret_val;
4426         s32 count = 0;
4427         s32 j, iteration, sector_size;
4428
4429         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4430
4431         /* Determine HW Sector size: Read BERASE bits of hw flash status
4432          * register
4433          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4434          *     consecutive sectors.  The start index for the nth Hw sector
4435          *     can be calculated as = bank * 4096 + n * 256
4436          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4437          *     The start index for the nth Hw sector can be calculated
4438          *     as = bank * 4096
4439          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4440          *     (ich9 only, otherwise error condition)
4441          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4442          */
4443         switch (hsfsts.hsf_status.berasesz) {
4444         case 0:
4445                 /* Hw sector size 256 */
4446                 sector_size = ICH_FLASH_SEG_SIZE_256;
4447                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4448                 break;
4449         case 1:
4450                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4451                 iteration = 1;
4452                 break;
4453         case 2:
4454                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4455                 iteration = 1;
4456                 break;
4457         case 3:
4458                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4459                 iteration = 1;
4460                 break;
4461         default:
4462                 return -E1000_ERR_NVM;
4463         }
4464
4465         /* Start with the base address, then add the sector offset. */
4466         flash_linear_addr = hw->nvm.flash_base_addr;
4467         flash_linear_addr += (bank) ? flash_bank_size : 0;
4468
4469         for (j = 0; j < iteration; j++) {
4470                 do {
4471                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4472
4473                         /* Steps */
4474                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4475                         if (ret_val)
4476                                 return ret_val;
4477
4478                         /* Write a value 11 (block Erase) in Flash
4479                          * Cycle field in hw flash control
4480                          */
4481                         if (hw->mac.type >= e1000_pch_spt)
4482                                 hsflctl.regval =
4483                                     er32flash(ICH_FLASH_HSFSTS) >> 16;
4484                         else
4485                                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4486
4487                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4488                         if (hw->mac.type >= e1000_pch_spt)
4489                                 ew32flash(ICH_FLASH_HSFSTS,
4490                                           hsflctl.regval << 16);
4491                         else
4492                                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4493
4494                         /* Write the last 24 bits of an index within the
4495                          * block into Flash Linear address field in Flash
4496                          * Address.
4497                          */
4498                         flash_linear_addr += (j * sector_size);
4499                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4500
4501                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4502                         if (!ret_val)
4503                                 break;
4504
4505                         /* Check if FCERR is set to 1.  If 1,
4506                          * clear it and try the whole sequence
4507                          * a few more times else Done
4508                          */
4509                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4510                         if (hsfsts.hsf_status.flcerr)
4511                                 /* repeat for some time before giving up */
4512                                 continue;
4513                         else if (!hsfsts.hsf_status.flcdone)
4514                                 return ret_val;
4515                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4516         }
4517
4518         return 0;
4519 }
4520
4521 /**
4522  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4523  *  @hw: pointer to the HW structure
4524  *  @data: Pointer to the LED settings
4525  *
4526  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4527  *  settings is all 0's or F's, set the LED default to a valid LED default
4528  *  setting.
4529  **/
4530 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4531 {
4532         s32 ret_val;
4533
4534         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4535         if (ret_val) {
4536                 e_dbg("NVM Read Error\n");
4537                 return ret_val;
4538         }
4539
4540         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4541                 *data = ID_LED_DEFAULT_ICH8LAN;
4542
4543         return 0;
4544 }
4545
4546 /**
4547  *  e1000_id_led_init_pchlan - store LED configurations
4548  *  @hw: pointer to the HW structure
4549  *
4550  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4551  *  the PHY LED configuration register.
4552  *
4553  *  PCH also does not have an "always on" or "always off" mode which
4554  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4555  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4556  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4557  *  link based on logic in e1000_led_[on|off]_pchlan().
4558  **/
4559 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4560 {
4561         struct e1000_mac_info *mac = &hw->mac;
4562         s32 ret_val;
4563         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4564         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4565         u16 data, i, temp, shift;
4566
4567         /* Get default ID LED modes */
4568         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4569         if (ret_val)
4570                 return ret_val;
4571
4572         mac->ledctl_default = er32(LEDCTL);
4573         mac->ledctl_mode1 = mac->ledctl_default;
4574         mac->ledctl_mode2 = mac->ledctl_default;
4575
4576         for (i = 0; i < 4; i++) {
4577                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4578                 shift = (i * 5);
4579                 switch (temp) {
4580                 case ID_LED_ON1_DEF2:
4581                 case ID_LED_ON1_ON2:
4582                 case ID_LED_ON1_OFF2:
4583                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4584                         mac->ledctl_mode1 |= (ledctl_on << shift);
4585                         break;
4586                 case ID_LED_OFF1_DEF2:
4587                 case ID_LED_OFF1_ON2:
4588                 case ID_LED_OFF1_OFF2:
4589                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4590                         mac->ledctl_mode1 |= (ledctl_off << shift);
4591                         break;
4592                 default:
4593                         /* Do nothing */
4594                         break;
4595                 }
4596                 switch (temp) {
4597                 case ID_LED_DEF1_ON2:
4598                 case ID_LED_ON1_ON2:
4599                 case ID_LED_OFF1_ON2:
4600                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4601                         mac->ledctl_mode2 |= (ledctl_on << shift);
4602                         break;
4603                 case ID_LED_DEF1_OFF2:
4604                 case ID_LED_ON1_OFF2:
4605                 case ID_LED_OFF1_OFF2:
4606                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4607                         mac->ledctl_mode2 |= (ledctl_off << shift);
4608                         break;
4609                 default:
4610                         /* Do nothing */
4611                         break;
4612                 }
4613         }
4614
4615         return 0;
4616 }
4617
4618 /**
4619  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4620  *  @hw: pointer to the HW structure
4621  *
4622  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4623  *  register, so the the bus width is hard coded.
4624  **/
4625 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4626 {
4627         struct e1000_bus_info *bus = &hw->bus;
4628         s32 ret_val;
4629
4630         ret_val = e1000e_get_bus_info_pcie(hw);
4631
4632         /* ICH devices are "PCI Express"-ish.  They have
4633          * a configuration space, but do not contain
4634          * PCI Express Capability registers, so bus width
4635          * must be hardcoded.
4636          */
4637         if (bus->width == e1000_bus_width_unknown)
4638                 bus->width = e1000_bus_width_pcie_x1;
4639
4640         return ret_val;
4641 }
4642
4643 /**
4644  *  e1000_reset_hw_ich8lan - Reset the hardware
4645  *  @hw: pointer to the HW structure
4646  *
4647  *  Does a full reset of the hardware which includes a reset of the PHY and
4648  *  MAC.
4649  **/
4650 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4651 {
4652         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4653         u16 kum_cfg;
4654         u32 ctrl, reg;
4655         s32 ret_val;
4656
4657         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4658          * on the last TLP read/write transaction when MAC is reset.
4659          */
4660         ret_val = e1000e_disable_pcie_master(hw);
4661         if (ret_val)
4662                 e_dbg("PCI-E Master disable polling has failed.\n");
4663
4664         e_dbg("Masking off all interrupts\n");
4665         ew32(IMC, 0xffffffff);
4666
4667         /* Disable the Transmit and Receive units.  Then delay to allow
4668          * any pending transactions to complete before we hit the MAC
4669          * with the global reset.
4670          */
4671         ew32(RCTL, 0);
4672         ew32(TCTL, E1000_TCTL_PSP);
4673         e1e_flush();
4674
4675         usleep_range(10000, 20000);
4676
4677         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4678         if (hw->mac.type == e1000_ich8lan) {
4679                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4680                 ew32(PBA, E1000_PBA_8K);
4681                 /* Set Packet Buffer Size to 16k. */
4682                 ew32(PBS, E1000_PBS_16K);
4683         }
4684
4685         if (hw->mac.type == e1000_pchlan) {
4686                 /* Save the NVM K1 bit setting */
4687                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4688                 if (ret_val)
4689                         return ret_val;
4690
4691                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4692                         dev_spec->nvm_k1_enabled = true;
4693                 else
4694                         dev_spec->nvm_k1_enabled = false;
4695         }
4696
4697         ctrl = er32(CTRL);
4698
4699         if (!hw->phy.ops.check_reset_block(hw)) {
4700                 /* Full-chip reset requires MAC and PHY reset at the same
4701                  * time to make sure the interface between MAC and the
4702                  * external PHY is reset.
4703                  */
4704                 ctrl |= E1000_CTRL_PHY_RST;
4705
4706                 /* Gate automatic PHY configuration by hardware on
4707                  * non-managed 82579
4708                  */
4709                 if ((hw->mac.type == e1000_pch2lan) &&
4710                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4711                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4712         }
4713         ret_val = e1000_acquire_swflag_ich8lan(hw);
4714         e_dbg("Issuing a global reset to ich8lan\n");
4715         ew32(CTRL, (ctrl | E1000_CTRL_RST));
4716         /* cannot issue a flush here because it hangs the hardware */
4717         msleep(20);
4718
4719         /* Set Phy Config Counter to 50msec */
4720         if (hw->mac.type == e1000_pch2lan) {
4721                 reg = er32(FEXTNVM3);
4722                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4723                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4724                 ew32(FEXTNVM3, reg);
4725         }
4726
4727         if (!ret_val)
4728                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4729
4730         if (ctrl & E1000_CTRL_PHY_RST) {
4731                 ret_val = hw->phy.ops.get_cfg_done(hw);
4732                 if (ret_val)
4733                         return ret_val;
4734
4735                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4736                 if (ret_val)
4737                         return ret_val;
4738         }
4739
4740         /* For PCH, this write will make sure that any noise
4741          * will be detected as a CRC error and be dropped rather than show up
4742          * as a bad packet to the DMA engine.
4743          */
4744         if (hw->mac.type == e1000_pchlan)
4745                 ew32(CRC_OFFSET, 0x65656565);
4746
4747         ew32(IMC, 0xffffffff);
4748         er32(ICR);
4749
4750         reg = er32(KABGTXD);
4751         reg |= E1000_KABGTXD_BGSQLBIAS;
4752         ew32(KABGTXD, reg);
4753
4754         return 0;
4755 }
4756
4757 /**
4758  *  e1000_init_hw_ich8lan - Initialize the hardware
4759  *  @hw: pointer to the HW structure
4760  *
4761  *  Prepares the hardware for transmit and receive by doing the following:
4762  *   - initialize hardware bits
4763  *   - initialize LED identification
4764  *   - setup receive address registers
4765  *   - setup flow control
4766  *   - setup transmit descriptors
4767  *   - clear statistics
4768  **/
4769 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4770 {
4771         struct e1000_mac_info *mac = &hw->mac;
4772         u32 ctrl_ext, txdctl, snoop;
4773         s32 ret_val;
4774         u16 i;
4775
4776         e1000_initialize_hw_bits_ich8lan(hw);
4777
4778         /* Initialize identification LED */
4779         ret_val = mac->ops.id_led_init(hw);
4780         /* An error is not fatal and we should not stop init due to this */
4781         if (ret_val)
4782                 e_dbg("Error initializing identification LED\n");
4783
4784         /* Setup the receive address. */
4785         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4786
4787         /* Zero out the Multicast HASH table */
4788         e_dbg("Zeroing the MTA\n");
4789         for (i = 0; i < mac->mta_reg_count; i++)
4790                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4791
4792         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4793          * the ME.  Disable wakeup by clearing the host wakeup bit.
4794          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4795          */
4796         if (hw->phy.type == e1000_phy_82578) {
4797                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4798                 i &= ~BM_WUC_HOST_WU_BIT;
4799                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4800                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4801                 if (ret_val)
4802                         return ret_val;
4803         }
4804
4805         /* Setup link and flow control */
4806         ret_val = mac->ops.setup_link(hw);
4807
4808         /* Set the transmit descriptor write-back policy for both queues */
4809         txdctl = er32(TXDCTL(0));
4810         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4811                   E1000_TXDCTL_FULL_TX_DESC_WB);
4812         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4813                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4814         ew32(TXDCTL(0), txdctl);
4815         txdctl = er32(TXDCTL(1));
4816         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4817                   E1000_TXDCTL_FULL_TX_DESC_WB);
4818         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4819                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4820         ew32(TXDCTL(1), txdctl);
4821
4822         /* ICH8 has opposite polarity of no_snoop bits.
4823          * By default, we should use snoop behavior.
4824          */
4825         if (mac->type == e1000_ich8lan)
4826                 snoop = PCIE_ICH8_SNOOP_ALL;
4827         else
4828                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4829         e1000e_set_pcie_no_snoop(hw, snoop);
4830
4831         ctrl_ext = er32(CTRL_EXT);
4832         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4833         ew32(CTRL_EXT, ctrl_ext);
4834
4835         /* Clear all of the statistics registers (clear on read).  It is
4836          * important that we do this after we have tried to establish link
4837          * because the symbol error count will increment wildly if there
4838          * is no link.
4839          */
4840         e1000_clear_hw_cntrs_ich8lan(hw);
4841
4842         return ret_val;
4843 }
4844
4845 /**
4846  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4847  *  @hw: pointer to the HW structure
4848  *
4849  *  Sets/Clears required hardware bits necessary for correctly setting up the
4850  *  hardware for transmit and receive.
4851  **/
4852 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4853 {
4854         u32 reg;
4855
4856         /* Extended Device Control */
4857         reg = er32(CTRL_EXT);
4858         reg |= BIT(22);
4859         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4860         if (hw->mac.type >= e1000_pchlan)
4861                 reg |= E1000_CTRL_EXT_PHYPDEN;
4862         ew32(CTRL_EXT, reg);
4863
4864         /* Transmit Descriptor Control 0 */
4865         reg = er32(TXDCTL(0));
4866         reg |= BIT(22);
4867         ew32(TXDCTL(0), reg);
4868
4869         /* Transmit Descriptor Control 1 */
4870         reg = er32(TXDCTL(1));
4871         reg |= BIT(22);
4872         ew32(TXDCTL(1), reg);
4873
4874         /* Transmit Arbitration Control 0 */
4875         reg = er32(TARC(0));
4876         if (hw->mac.type == e1000_ich8lan)
4877                 reg |= BIT(28) | BIT(29);
4878         reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4879         ew32(TARC(0), reg);
4880
4881         /* Transmit Arbitration Control 1 */
4882         reg = er32(TARC(1));
4883         if (er32(TCTL) & E1000_TCTL_MULR)
4884                 reg &= ~BIT(28);
4885         else
4886                 reg |= BIT(28);
4887         reg |= BIT(24) | BIT(26) | BIT(30);
4888         ew32(TARC(1), reg);
4889
4890         /* Device Status */
4891         if (hw->mac.type == e1000_ich8lan) {
4892                 reg = er32(STATUS);
4893                 reg &= ~BIT(31);
4894                 ew32(STATUS, reg);
4895         }
4896
4897         /* work-around descriptor data corruption issue during nfs v2 udp
4898          * traffic, just disable the nfs filtering capability
4899          */
4900         reg = er32(RFCTL);
4901         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4902
4903         /* Disable IPv6 extension header parsing because some malformed
4904          * IPv6 headers can hang the Rx.
4905          */
4906         if (hw->mac.type == e1000_ich8lan)
4907                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4908         ew32(RFCTL, reg);
4909
4910         /* Enable ECC on Lynxpoint */
4911         if (hw->mac.type >= e1000_pch_lpt) {
4912                 reg = er32(PBECCSTS);
4913                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4914                 ew32(PBECCSTS, reg);
4915
4916                 reg = er32(CTRL);
4917                 reg |= E1000_CTRL_MEHE;
4918                 ew32(CTRL, reg);
4919         }
4920 }
4921
4922 /**
4923  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4924  *  @hw: pointer to the HW structure
4925  *
4926  *  Determines which flow control settings to use, then configures flow
4927  *  control.  Calls the appropriate media-specific link configuration
4928  *  function.  Assuming the adapter has a valid link partner, a valid link
4929  *  should be established.  Assumes the hardware has previously been reset
4930  *  and the transmitter and receiver are not enabled.
4931  **/
4932 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4933 {
4934         s32 ret_val;
4935
4936         if (hw->phy.ops.check_reset_block(hw))
4937                 return 0;
4938
4939         /* ICH parts do not have a word in the NVM to determine
4940          * the default flow control setting, so we explicitly
4941          * set it to full.
4942          */
4943         if (hw->fc.requested_mode == e1000_fc_default) {
4944                 /* Workaround h/w hang when Tx flow control enabled */
4945                 if (hw->mac.type == e1000_pchlan)
4946                         hw->fc.requested_mode = e1000_fc_rx_pause;
4947                 else
4948                         hw->fc.requested_mode = e1000_fc_full;
4949         }
4950
4951         /* Save off the requested flow control mode for use later.  Depending
4952          * on the link partner's capabilities, we may or may not use this mode.
4953          */
4954         hw->fc.current_mode = hw->fc.requested_mode;
4955
4956         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4957
4958         /* Continue to configure the copper link. */
4959         ret_val = hw->mac.ops.setup_physical_interface(hw);
4960         if (ret_val)
4961                 return ret_val;
4962
4963         ew32(FCTTV, hw->fc.pause_time);
4964         if ((hw->phy.type == e1000_phy_82578) ||
4965             (hw->phy.type == e1000_phy_82579) ||
4966             (hw->phy.type == e1000_phy_i217) ||
4967             (hw->phy.type == e1000_phy_82577)) {
4968                 ew32(FCRTV_PCH, hw->fc.refresh_time);
4969
4970                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4971                                    hw->fc.pause_time);
4972                 if (ret_val)
4973                         return ret_val;
4974         }
4975
4976         return e1000e_set_fc_watermarks(hw);
4977 }
4978
4979 /**
4980  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4981  *  @hw: pointer to the HW structure
4982  *
4983  *  Configures the kumeran interface to the PHY to wait the appropriate time
4984  *  when polling the PHY, then call the generic setup_copper_link to finish
4985  *  configuring the copper link.
4986  **/
4987 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4988 {
4989         u32 ctrl;
4990         s32 ret_val;
4991         u16 reg_data;
4992
4993         ctrl = er32(CTRL);
4994         ctrl |= E1000_CTRL_SLU;
4995         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4996         ew32(CTRL, ctrl);
4997
4998         /* Set the mac to wait the maximum time between each iteration
4999          * and increase the max iterations when polling the phy;
5000          * this fixes erroneous timeouts at 10Mbps.
5001          */
5002         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5003         if (ret_val)
5004                 return ret_val;
5005         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5006                                        &reg_data);
5007         if (ret_val)
5008                 return ret_val;
5009         reg_data |= 0x3F;
5010         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5011                                         reg_data);
5012         if (ret_val)
5013                 return ret_val;
5014
5015         switch (hw->phy.type) {
5016         case e1000_phy_igp_3:
5017                 ret_val = e1000e_copper_link_setup_igp(hw);
5018                 if (ret_val)
5019                         return ret_val;
5020                 break;
5021         case e1000_phy_bm:
5022         case e1000_phy_82578:
5023                 ret_val = e1000e_copper_link_setup_m88(hw);
5024                 if (ret_val)
5025                         return ret_val;
5026                 break;
5027         case e1000_phy_82577:
5028         case e1000_phy_82579:
5029                 ret_val = e1000_copper_link_setup_82577(hw);
5030                 if (ret_val)
5031                         return ret_val;
5032                 break;
5033         case e1000_phy_ife:
5034                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
5035                 if (ret_val)
5036                         return ret_val;
5037
5038                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5039
5040                 switch (hw->phy.mdix) {
5041                 case 1:
5042                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5043                         break;
5044                 case 2:
5045                         reg_data |= IFE_PMC_FORCE_MDIX;
5046                         break;
5047                 case 0:
5048                 default:
5049                         reg_data |= IFE_PMC_AUTO_MDIX;
5050                         break;
5051                 }
5052                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5053                 if (ret_val)
5054                         return ret_val;
5055                 break;
5056         default:
5057                 break;
5058         }
5059
5060         return e1000e_setup_copper_link(hw);
5061 }
5062
5063 /**
5064  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5065  *  @hw: pointer to the HW structure
5066  *
5067  *  Calls the PHY specific link setup function and then calls the
5068  *  generic setup_copper_link to finish configuring the link for
5069  *  Lynxpoint PCH devices
5070  **/
5071 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5072 {
5073         u32 ctrl;
5074         s32 ret_val;
5075
5076         ctrl = er32(CTRL);
5077         ctrl |= E1000_CTRL_SLU;
5078         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5079         ew32(CTRL, ctrl);
5080
5081         ret_val = e1000_copper_link_setup_82577(hw);
5082         if (ret_val)
5083                 return ret_val;
5084
5085         return e1000e_setup_copper_link(hw);
5086 }
5087
5088 /**
5089  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5090  *  @hw: pointer to the HW structure
5091  *  @speed: pointer to store current link speed
5092  *  @duplex: pointer to store the current link duplex
5093  *
5094  *  Calls the generic get_speed_and_duplex to retrieve the current link
5095  *  information and then calls the Kumeran lock loss workaround for links at
5096  *  gigabit speeds.
5097  **/
5098 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5099                                           u16 *duplex)
5100 {
5101         s32 ret_val;
5102
5103         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5104         if (ret_val)
5105                 return ret_val;
5106
5107         if ((hw->mac.type == e1000_ich8lan) &&
5108             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5109                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5110         }
5111
5112         return ret_val;
5113 }
5114
5115 /**
5116  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5117  *  @hw: pointer to the HW structure
5118  *
5119  *  Work-around for 82566 Kumeran PCS lock loss:
5120  *  On link status change (i.e. PCI reset, speed change) and link is up and
5121  *  speed is gigabit-
5122  *    0) if workaround is optionally disabled do nothing
5123  *    1) wait 1ms for Kumeran link to come up
5124  *    2) check Kumeran Diagnostic register PCS lock loss bit
5125  *    3) if not set the link is locked (all is good), otherwise...
5126  *    4) reset the PHY
5127  *    5) repeat up to 10 times
5128  *  Note: this is only called for IGP3 copper when speed is 1gb.
5129  **/
5130 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5131 {
5132         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5133         u32 phy_ctrl;
5134         s32 ret_val;
5135         u16 i, data;
5136         bool link;
5137
5138         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5139                 return 0;
5140
5141         /* Make sure link is up before proceeding.  If not just return.
5142          * Attempting this while link is negotiating fouled up link
5143          * stability
5144          */
5145         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5146         if (!link)
5147                 return 0;
5148
5149         for (i = 0; i < 10; i++) {
5150                 /* read once to clear */
5151                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5152                 if (ret_val)
5153                         return ret_val;
5154                 /* and again to get new status */
5155                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5156                 if (ret_val)
5157                         return ret_val;
5158
5159                 /* check for PCS lock */
5160                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5161                         return 0;
5162
5163                 /* Issue PHY reset */
5164                 e1000_phy_hw_reset(hw);
5165                 mdelay(5);
5166         }
5167         /* Disable GigE link negotiation */
5168         phy_ctrl = er32(PHY_CTRL);
5169         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5170                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5171         ew32(PHY_CTRL, phy_ctrl);
5172
5173         /* Call gig speed drop workaround on Gig disable before accessing
5174          * any PHY registers
5175          */
5176         e1000e_gig_downshift_workaround_ich8lan(hw);
5177
5178         /* unable to acquire PCS lock */
5179         return -E1000_ERR_PHY;
5180 }
5181
5182 /**
5183  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5184  *  @hw: pointer to the HW structure
5185  *  @state: boolean value used to set the current Kumeran workaround state
5186  *
5187  *  If ICH8, set the current Kumeran workaround state (enabled - true
5188  *  /disabled - false).
5189  **/
5190 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5191                                                   bool state)
5192 {
5193         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5194
5195         if (hw->mac.type != e1000_ich8lan) {
5196                 e_dbg("Workaround applies to ICH8 only.\n");
5197                 return;
5198         }
5199
5200         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5201 }
5202
5203 /**
5204  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5205  *  @hw: pointer to the HW structure
5206  *
5207  *  Workaround for 82566 power-down on D3 entry:
5208  *    1) disable gigabit link
5209  *    2) write VR power-down enable
5210  *    3) read it back
5211  *  Continue if successful, else issue LCD reset and repeat
5212  **/
5213 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5214 {
5215         u32 reg;
5216         u16 data;
5217         u8 retry = 0;
5218
5219         if (hw->phy.type != e1000_phy_igp_3)
5220                 return;
5221
5222         /* Try the workaround twice (if needed) */
5223         do {
5224                 /* Disable link */
5225                 reg = er32(PHY_CTRL);
5226                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5227                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5228                 ew32(PHY_CTRL, reg);
5229
5230                 /* Call gig speed drop workaround on Gig disable before
5231                  * accessing any PHY registers
5232                  */
5233                 if (hw->mac.type == e1000_ich8lan)
5234                         e1000e_gig_downshift_workaround_ich8lan(hw);
5235
5236                 /* Write VR power-down enable */
5237                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5238                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5239                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5240
5241                 /* Read it back and test */
5242                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5243                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5244                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5245                         break;
5246
5247                 /* Issue PHY reset and repeat at most one more time */
5248                 reg = er32(CTRL);
5249                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5250                 retry++;
5251         } while (retry);
5252 }
5253
5254 /**
5255  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5256  *  @hw: pointer to the HW structure
5257  *
5258  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5259  *  LPLU, Gig disable, MDIC PHY reset):
5260  *    1) Set Kumeran Near-end loopback
5261  *    2) Clear Kumeran Near-end loopback
5262  *  Should only be called for ICH8[m] devices with any 1G Phy.
5263  **/
5264 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5265 {
5266         s32 ret_val;
5267         u16 reg_data;
5268
5269         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5270                 return;
5271
5272         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5273                                        &reg_data);
5274         if (ret_val)
5275                 return;
5276         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5277         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5278                                         reg_data);
5279         if (ret_val)
5280                 return;
5281         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5282         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5283 }
5284
5285 /**
5286  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5287  *  @hw: pointer to the HW structure
5288  *
5289  *  During S0 to Sx transition, it is possible the link remains at gig
5290  *  instead of negotiating to a lower speed.  Before going to Sx, set
5291  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5292  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5293  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5294  *  needs to be written.
5295  *  Parts that support (and are linked to a partner which support) EEE in
5296  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5297  *  than 10Mbps w/o EEE.
5298  **/
5299 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5300 {
5301         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5302         u32 phy_ctrl;
5303         s32 ret_val;
5304
5305         phy_ctrl = er32(PHY_CTRL);
5306         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5307
5308         if (hw->phy.type == e1000_phy_i217) {
5309                 u16 phy_reg, device_id = hw->adapter->pdev->device;
5310
5311                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5312                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5313                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5314                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5315                     (hw->mac.type >= e1000_pch_spt)) {
5316                         u32 fextnvm6 = er32(FEXTNVM6);
5317
5318                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5319                 }
5320
5321                 ret_val = hw->phy.ops.acquire(hw);
5322                 if (ret_val)
5323                         goto out;
5324
5325                 if (!dev_spec->eee_disable) {
5326                         u16 eee_advert;
5327
5328                         ret_val =
5329                             e1000_read_emi_reg_locked(hw,
5330                                                       I217_EEE_ADVERTISEMENT,
5331                                                       &eee_advert);
5332                         if (ret_val)
5333                                 goto release;
5334
5335                         /* Disable LPLU if both link partners support 100BaseT
5336                          * EEE and 100Full is advertised on both ends of the
5337                          * link, and enable Auto Enable LPI since there will
5338                          * be no driver to enable LPI while in Sx.
5339                          */
5340                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5341                             (dev_spec->eee_lp_ability &
5342                              I82579_EEE_100_SUPPORTED) &&
5343                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5344                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5345                                               E1000_PHY_CTRL_NOND0A_LPLU);
5346
5347                                 /* Set Auto Enable LPI after link up */
5348                                 e1e_rphy_locked(hw,
5349                                                 I217_LPI_GPIO_CTRL, &phy_reg);
5350                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5351                                 e1e_wphy_locked(hw,
5352                                                 I217_LPI_GPIO_CTRL, phy_reg);
5353                         }
5354                 }
5355
5356                 /* For i217 Intel Rapid Start Technology support,
5357                  * when the system is going into Sx and no manageability engine
5358                  * is present, the driver must configure proxy to reset only on
5359                  * power good.  LPI (Low Power Idle) state must also reset only
5360                  * on power good, as well as the MTA (Multicast table array).
5361                  * The SMBus release must also be disabled on LCD reset.
5362                  */
5363                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5364                         /* Enable proxy to reset only on power good. */
5365                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5366                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5367                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5368
5369                         /* Set bit enable LPI (EEE) to reset only on
5370                          * power good.
5371                          */
5372                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5373                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5374                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5375
5376                         /* Disable the SMB release on LCD reset. */
5377                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5378                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5379                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5380                 }
5381
5382                 /* Enable MTA to reset for Intel Rapid Start Technology
5383                  * Support
5384                  */
5385                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5386                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5387                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5388
5389 release:
5390                 hw->phy.ops.release(hw);
5391         }
5392 out:
5393         ew32(PHY_CTRL, phy_ctrl);
5394
5395         if (hw->mac.type == e1000_ich8lan)
5396                 e1000e_gig_downshift_workaround_ich8lan(hw);
5397
5398         if (hw->mac.type >= e1000_pchlan) {
5399                 e1000_oem_bits_config_ich8lan(hw, false);
5400
5401                 /* Reset PHY to activate OEM bits on 82577/8 */
5402                 if (hw->mac.type == e1000_pchlan)
5403                         e1000e_phy_hw_reset_generic(hw);
5404
5405                 ret_val = hw->phy.ops.acquire(hw);
5406                 if (ret_val)
5407                         return;
5408                 e1000_write_smbus_addr(hw);
5409                 hw->phy.ops.release(hw);
5410         }
5411 }
5412
5413 /**
5414  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5415  *  @hw: pointer to the HW structure
5416  *
5417  *  During Sx to S0 transitions on non-managed devices or managed devices
5418  *  on which PHY resets are not blocked, if the PHY registers cannot be
5419  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5420  *  the PHY.
5421  *  On i217, setup Intel Rapid Start Technology.
5422  **/
5423 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5424 {
5425         s32 ret_val;
5426
5427         if (hw->mac.type < e1000_pch2lan)
5428                 return;
5429
5430         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5431         if (ret_val) {
5432                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5433                 return;
5434         }
5435
5436         /* For i217 Intel Rapid Start Technology support when the system
5437          * is transitioning from Sx and no manageability engine is present
5438          * configure SMBus to restore on reset, disable proxy, and enable
5439          * the reset on MTA (Multicast table array).
5440          */
5441         if (hw->phy.type == e1000_phy_i217) {
5442                 u16 phy_reg;
5443
5444                 ret_val = hw->phy.ops.acquire(hw);
5445                 if (ret_val) {
5446                         e_dbg("Failed to setup iRST\n");
5447                         return;
5448                 }
5449
5450                 /* Clear Auto Enable LPI after link up */
5451                 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5452                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5453                 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5454
5455                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5456                         /* Restore clear on SMB if no manageability engine
5457                          * is present
5458                          */
5459                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5460                         if (ret_val)
5461                                 goto release;
5462                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5463                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5464
5465                         /* Disable Proxy */
5466                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5467                 }
5468                 /* Enable reset on MTA */
5469                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5470                 if (ret_val)
5471                         goto release;
5472                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5473                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5474 release:
5475                 if (ret_val)
5476                         e_dbg("Error %d in resume workarounds\n", ret_val);
5477                 hw->phy.ops.release(hw);
5478         }
5479 }
5480
5481 /**
5482  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5483  *  @hw: pointer to the HW structure
5484  *
5485  *  Return the LED back to the default configuration.
5486  **/
5487 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5488 {
5489         if (hw->phy.type == e1000_phy_ife)
5490                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5491
5492         ew32(LEDCTL, hw->mac.ledctl_default);
5493         return 0;
5494 }
5495
5496 /**
5497  *  e1000_led_on_ich8lan - Turn LEDs on
5498  *  @hw: pointer to the HW structure
5499  *
5500  *  Turn on the LEDs.
5501  **/
5502 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5503 {
5504         if (hw->phy.type == e1000_phy_ife)
5505                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5506                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5507
5508         ew32(LEDCTL, hw->mac.ledctl_mode2);
5509         return 0;
5510 }
5511
5512 /**
5513  *  e1000_led_off_ich8lan - Turn LEDs off
5514  *  @hw: pointer to the HW structure
5515  *
5516  *  Turn off the LEDs.
5517  **/
5518 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5519 {
5520         if (hw->phy.type == e1000_phy_ife)
5521                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5522                                 (IFE_PSCL_PROBE_MODE |
5523                                  IFE_PSCL_PROBE_LEDS_OFF));
5524
5525         ew32(LEDCTL, hw->mac.ledctl_mode1);
5526         return 0;
5527 }
5528
5529 /**
5530  *  e1000_setup_led_pchlan - Configures SW controllable LED
5531  *  @hw: pointer to the HW structure
5532  *
5533  *  This prepares the SW controllable LED for use.
5534  **/
5535 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5536 {
5537         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5538 }
5539
5540 /**
5541  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5542  *  @hw: pointer to the HW structure
5543  *
5544  *  Return the LED back to the default configuration.
5545  **/
5546 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5547 {
5548         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5549 }
5550
5551 /**
5552  *  e1000_led_on_pchlan - Turn LEDs on
5553  *  @hw: pointer to the HW structure
5554  *
5555  *  Turn on the LEDs.
5556  **/
5557 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5558 {
5559         u16 data = (u16)hw->mac.ledctl_mode2;
5560         u32 i, led;
5561
5562         /* If no link, then turn LED on by setting the invert bit
5563          * for each LED that's mode is "link_up" in ledctl_mode2.
5564          */
5565         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5566                 for (i = 0; i < 3; i++) {
5567                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5568                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5569                             E1000_LEDCTL_MODE_LINK_UP)
5570                                 continue;
5571                         if (led & E1000_PHY_LED0_IVRT)
5572                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5573                         else
5574                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5575                 }
5576         }
5577
5578         return e1e_wphy(hw, HV_LED_CONFIG, data);
5579 }
5580
5581 /**
5582  *  e1000_led_off_pchlan - Turn LEDs off
5583  *  @hw: pointer to the HW structure
5584  *
5585  *  Turn off the LEDs.
5586  **/
5587 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5588 {
5589         u16 data = (u16)hw->mac.ledctl_mode1;
5590         u32 i, led;
5591
5592         /* If no link, then turn LED off by clearing the invert bit
5593          * for each LED that's mode is "link_up" in ledctl_mode1.
5594          */
5595         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5596                 for (i = 0; i < 3; i++) {
5597                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5598                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5599                             E1000_LEDCTL_MODE_LINK_UP)
5600                                 continue;
5601                         if (led & E1000_PHY_LED0_IVRT)
5602                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5603                         else
5604                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5605                 }
5606         }
5607
5608         return e1e_wphy(hw, HV_LED_CONFIG, data);
5609 }
5610
5611 /**
5612  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5613  *  @hw: pointer to the HW structure
5614  *
5615  *  Read appropriate register for the config done bit for completion status
5616  *  and configure the PHY through s/w for EEPROM-less parts.
5617  *
5618  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5619  *  config done bit, so only an error is logged and continues.  If we were
5620  *  to return with error, EEPROM-less silicon would not be able to be reset
5621  *  or change link.
5622  **/
5623 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5624 {
5625         s32 ret_val = 0;
5626         u32 bank = 0;
5627         u32 status;
5628
5629         e1000e_get_cfg_done_generic(hw);
5630
5631         /* Wait for indication from h/w that it has completed basic config */
5632         if (hw->mac.type >= e1000_ich10lan) {
5633                 e1000_lan_init_done_ich8lan(hw);
5634         } else {
5635                 ret_val = e1000e_get_auto_rd_done(hw);
5636                 if (ret_val) {
5637                         /* When auto config read does not complete, do not
5638                          * return with an error. This can happen in situations
5639                          * where there is no eeprom and prevents getting link.
5640                          */
5641                         e_dbg("Auto Read Done did not complete\n");
5642                         ret_val = 0;
5643                 }
5644         }
5645
5646         /* Clear PHY Reset Asserted bit */
5647         status = er32(STATUS);
5648         if (status & E1000_STATUS_PHYRA)
5649                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5650         else
5651                 e_dbg("PHY Reset Asserted not set - needs delay\n");
5652
5653         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5654         if (hw->mac.type <= e1000_ich9lan) {
5655                 if (!(er32(EECD) & E1000_EECD_PRES) &&
5656                     (hw->phy.type == e1000_phy_igp_3)) {
5657                         e1000e_phy_init_script_igp3(hw);
5658                 }
5659         } else {
5660                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5661                         /* Maybe we should do a basic PHY config */
5662                         e_dbg("EEPROM not present\n");
5663                         ret_val = -E1000_ERR_CONFIG;
5664                 }
5665         }
5666
5667         return ret_val;
5668 }
5669
5670 /**
5671  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5672  * @hw: pointer to the HW structure
5673  *
5674  * In the case of a PHY power down to save power, or to turn off link during a
5675  * driver unload, or wake on lan is not enabled, remove the link.
5676  **/
5677 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5678 {
5679         /* If the management interface is not enabled, then power down */
5680         if (!(hw->mac.ops.check_mng_mode(hw) ||
5681               hw->phy.ops.check_reset_block(hw)))
5682                 e1000_power_down_phy_copper(hw);
5683 }
5684
5685 /**
5686  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5687  *  @hw: pointer to the HW structure
5688  *
5689  *  Clears hardware counters specific to the silicon family and calls
5690  *  clear_hw_cntrs_generic to clear all general purpose counters.
5691  **/
5692 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5693 {
5694         u16 phy_data;
5695         s32 ret_val;
5696
5697         e1000e_clear_hw_cntrs_base(hw);
5698
5699         er32(ALGNERRC);
5700         er32(RXERRC);
5701         er32(TNCRS);
5702         er32(CEXTERR);
5703         er32(TSCTC);
5704         er32(TSCTFC);
5705
5706         er32(MGTPRC);
5707         er32(MGTPDC);
5708         er32(MGTPTC);
5709
5710         er32(IAC);
5711         er32(ICRXOC);
5712
5713         /* Clear PHY statistics registers */
5714         if ((hw->phy.type == e1000_phy_82578) ||
5715             (hw->phy.type == e1000_phy_82579) ||
5716             (hw->phy.type == e1000_phy_i217) ||
5717             (hw->phy.type == e1000_phy_82577)) {
5718                 ret_val = hw->phy.ops.acquire(hw);
5719                 if (ret_val)
5720                         return;
5721                 ret_val = hw->phy.ops.set_page(hw,
5722                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5723                 if (ret_val)
5724                         goto release;
5725                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5726                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5727                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5728                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5729                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5730                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5731                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5732                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5733                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5734                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5735                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5736                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5737                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5738                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5739 release:
5740                 hw->phy.ops.release(hw);
5741         }
5742 }
5743
5744 static const struct e1000_mac_operations ich8_mac_ops = {
5745         /* check_mng_mode dependent on mac type */
5746         .check_for_link         = e1000_check_for_copper_link_ich8lan,
5747         /* cleanup_led dependent on mac type */
5748         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
5749         .get_bus_info           = e1000_get_bus_info_ich8lan,
5750         .set_lan_id             = e1000_set_lan_id_single_port,
5751         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
5752         /* led_on dependent on mac type */
5753         /* led_off dependent on mac type */
5754         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
5755         .reset_hw               = e1000_reset_hw_ich8lan,
5756         .init_hw                = e1000_init_hw_ich8lan,
5757         .setup_link             = e1000_setup_link_ich8lan,
5758         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5759         /* id_led_init dependent on mac type */
5760         .config_collision_dist  = e1000e_config_collision_dist_generic,
5761         .rar_set                = e1000e_rar_set_generic,
5762         .rar_get_count          = e1000e_rar_get_count_generic,
5763 };
5764
5765 static const struct e1000_phy_operations ich8_phy_ops = {
5766         .acquire                = e1000_acquire_swflag_ich8lan,
5767         .check_reset_block      = e1000_check_reset_block_ich8lan,
5768         .commit                 = NULL,
5769         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
5770         .get_cable_length       = e1000e_get_cable_length_igp_2,
5771         .read_reg               = e1000e_read_phy_reg_igp,
5772         .release                = e1000_release_swflag_ich8lan,
5773         .reset                  = e1000_phy_hw_reset_ich8lan,
5774         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
5775         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
5776         .write_reg              = e1000e_write_phy_reg_igp,
5777 };
5778
5779 static const struct e1000_nvm_operations ich8_nvm_ops = {
5780         .acquire                = e1000_acquire_nvm_ich8lan,
5781         .read                   = e1000_read_nvm_ich8lan,
5782         .release                = e1000_release_nvm_ich8lan,
5783         .reload                 = e1000e_reload_nvm_generic,
5784         .update                 = e1000_update_nvm_checksum_ich8lan,
5785         .valid_led_default      = e1000_valid_led_default_ich8lan,
5786         .validate               = e1000_validate_nvm_checksum_ich8lan,
5787         .write                  = e1000_write_nvm_ich8lan,
5788 };
5789
5790 static const struct e1000_nvm_operations spt_nvm_ops = {
5791         .acquire                = e1000_acquire_nvm_ich8lan,
5792         .release                = e1000_release_nvm_ich8lan,
5793         .read                   = e1000_read_nvm_spt,
5794         .update                 = e1000_update_nvm_checksum_spt,
5795         .reload                 = e1000e_reload_nvm_generic,
5796         .valid_led_default      = e1000_valid_led_default_ich8lan,
5797         .validate               = e1000_validate_nvm_checksum_ich8lan,
5798         .write                  = e1000_write_nvm_ich8lan,
5799 };
5800
5801 const struct e1000_info e1000_ich8_info = {
5802         .mac                    = e1000_ich8lan,
5803         .flags                  = FLAG_HAS_WOL
5804                                   | FLAG_IS_ICH
5805                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5806                                   | FLAG_HAS_AMT
5807                                   | FLAG_HAS_FLASH
5808                                   | FLAG_APME_IN_WUC,
5809         .pba                    = 8,
5810         .max_hw_frame_size      = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5811         .get_variants           = e1000_get_variants_ich8lan,
5812         .mac_ops                = &ich8_mac_ops,
5813         .phy_ops                = &ich8_phy_ops,
5814         .nvm_ops                = &ich8_nvm_ops,
5815 };
5816
5817 const struct e1000_info e1000_ich9_info = {
5818         .mac                    = e1000_ich9lan,
5819         .flags                  = FLAG_HAS_JUMBO_FRAMES
5820                                   | FLAG_IS_ICH
5821                                   | FLAG_HAS_WOL
5822                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5823                                   | FLAG_HAS_AMT
5824                                   | FLAG_HAS_FLASH
5825                                   | FLAG_APME_IN_WUC,
5826         .pba                    = 18,
5827         .max_hw_frame_size      = DEFAULT_JUMBO,
5828         .get_variants           = e1000_get_variants_ich8lan,
5829         .mac_ops                = &ich8_mac_ops,
5830         .phy_ops                = &ich8_phy_ops,
5831         .nvm_ops                = &ich8_nvm_ops,
5832 };
5833
5834 const struct e1000_info e1000_ich10_info = {
5835         .mac                    = e1000_ich10lan,
5836         .flags                  = FLAG_HAS_JUMBO_FRAMES
5837                                   | FLAG_IS_ICH
5838                                   | FLAG_HAS_WOL
5839                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5840                                   | FLAG_HAS_AMT
5841                                   | FLAG_HAS_FLASH
5842                                   | FLAG_APME_IN_WUC,
5843         .pba                    = 18,
5844         .max_hw_frame_size      = DEFAULT_JUMBO,
5845         .get_variants           = e1000_get_variants_ich8lan,
5846         .mac_ops                = &ich8_mac_ops,
5847         .phy_ops                = &ich8_phy_ops,
5848         .nvm_ops                = &ich8_nvm_ops,
5849 };
5850
5851 const struct e1000_info e1000_pch_info = {
5852         .mac                    = e1000_pchlan,
5853         .flags                  = FLAG_IS_ICH
5854                                   | FLAG_HAS_WOL
5855                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5856                                   | FLAG_HAS_AMT
5857                                   | FLAG_HAS_FLASH
5858                                   | FLAG_HAS_JUMBO_FRAMES
5859                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5860                                   | FLAG_APME_IN_WUC,
5861         .flags2                 = FLAG2_HAS_PHY_STATS,
5862         .pba                    = 26,
5863         .max_hw_frame_size      = 4096,
5864         .get_variants           = e1000_get_variants_ich8lan,
5865         .mac_ops                = &ich8_mac_ops,
5866         .phy_ops                = &ich8_phy_ops,
5867         .nvm_ops                = &ich8_nvm_ops,
5868 };
5869
5870 const struct e1000_info e1000_pch2_info = {
5871         .mac                    = e1000_pch2lan,
5872         .flags                  = FLAG_IS_ICH
5873                                   | FLAG_HAS_WOL
5874                                   | FLAG_HAS_HW_TIMESTAMP
5875                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5876                                   | FLAG_HAS_AMT
5877                                   | FLAG_HAS_FLASH
5878                                   | FLAG_HAS_JUMBO_FRAMES
5879                                   | FLAG_APME_IN_WUC,
5880         .flags2                 = FLAG2_HAS_PHY_STATS
5881                                   | FLAG2_HAS_EEE
5882                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
5883         .pba                    = 26,
5884         .max_hw_frame_size      = 9022,
5885         .get_variants           = e1000_get_variants_ich8lan,
5886         .mac_ops                = &ich8_mac_ops,
5887         .phy_ops                = &ich8_phy_ops,
5888         .nvm_ops                = &ich8_nvm_ops,
5889 };
5890
5891 const struct e1000_info e1000_pch_lpt_info = {
5892         .mac                    = e1000_pch_lpt,
5893         .flags                  = FLAG_IS_ICH
5894                                   | FLAG_HAS_WOL
5895                                   | FLAG_HAS_HW_TIMESTAMP
5896                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5897                                   | FLAG_HAS_AMT
5898                                   | FLAG_HAS_FLASH
5899                                   | FLAG_HAS_JUMBO_FRAMES
5900                                   | FLAG_APME_IN_WUC,
5901         .flags2                 = FLAG2_HAS_PHY_STATS
5902                                   | FLAG2_HAS_EEE
5903                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
5904         .pba                    = 26,
5905         .max_hw_frame_size      = 9022,
5906         .get_variants           = e1000_get_variants_ich8lan,
5907         .mac_ops                = &ich8_mac_ops,
5908         .phy_ops                = &ich8_phy_ops,
5909         .nvm_ops                = &ich8_nvm_ops,
5910 };
5911
5912 const struct e1000_info e1000_pch_spt_info = {
5913         .mac                    = e1000_pch_spt,
5914         .flags                  = FLAG_IS_ICH
5915                                   | FLAG_HAS_WOL
5916                                   | FLAG_HAS_HW_TIMESTAMP
5917                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5918                                   | FLAG_HAS_AMT
5919                                   | FLAG_HAS_FLASH
5920                                   | FLAG_HAS_JUMBO_FRAMES
5921                                   | FLAG_APME_IN_WUC,
5922         .flags2                 = FLAG2_HAS_PHY_STATS
5923                                   | FLAG2_HAS_EEE,
5924         .pba                    = 26,
5925         .max_hw_frame_size      = 9022,
5926         .get_variants           = e1000_get_variants_ich8lan,
5927         .mac_ops                = &ich8_mac_ops,
5928         .phy_ops                = &ich8_phy_ops,
5929         .nvm_ops                = &spt_nvm_ops,
5930 };
5931
5932 const struct e1000_info e1000_pch_cnp_info = {
5933         .mac                    = e1000_pch_cnp,
5934         .flags                  = FLAG_IS_ICH
5935                                   | FLAG_HAS_WOL
5936                                   | FLAG_HAS_HW_TIMESTAMP
5937                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5938                                   | FLAG_HAS_AMT
5939                                   | FLAG_HAS_FLASH
5940                                   | FLAG_HAS_JUMBO_FRAMES
5941                                   | FLAG_APME_IN_WUC,
5942         .flags2                 = FLAG2_HAS_PHY_STATS
5943                                   | FLAG2_HAS_EEE,
5944         .pba                    = 26,
5945         .max_hw_frame_size      = 9022,
5946         .get_variants           = e1000_get_variants_ich8lan,
5947         .mac_ops                = &ich8_mac_ops,
5948         .phy_ops                = &ich8_phy_ops,
5949         .nvm_ops                = &spt_nvm_ops,
5950 };