drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /* Intel PRO/1000 Linux driver
   2  * Copyright(c) 1999 - 2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * The full GNU General Public License is included in this distribution in
  14  * the file called "COPYING".
  15  *
  16  * Contact Information:
  17  * Linux NICS <linux.nics@intel.com>
  18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20  */
  21
  22 /* 82562G 10/100 Network Connection
  23  * 82562G-2 10/100 Network Connection
  24  * 82562GT 10/100 Network Connection
  25  * 82562GT-2 10/100 Network Connection
  26  * 82562V 10/100 Network Connection
  27  * 82562V-2 10/100 Network Connection
  28  * 82566DC-2 Gigabit Network Connection
  29  * 82566DC Gigabit Network Connection
  30  * 82566DM-2 Gigabit Network Connection
  31  * 82566DM Gigabit Network Connection
  32  * 82566MC Gigabit Network Connection
  33  * 82566MM Gigabit Network Connection
  34  * 82567LM Gigabit Network Connection
  35  * 82567LF Gigabit Network Connection
  36  * 82567V Gigabit Network Connection
  37  * 82567LM-2 Gigabit Network Connection
  38  * 82567LF-2 Gigabit Network Connection
  39  * 82567V-2 Gigabit Network Connection
  40  * 82567LF-3 Gigabit Network Connection
  41  * 82567LM-3 Gigabit Network Connection
  42  * 82567LM-4 Gigabit Network Connection
  43  * 82577LM Gigabit Network Connection
  44  * 82577LC Gigabit Network Connection
  45  * 82578DM Gigabit Network Connection
  46  * 82578DC Gigabit Network Connection
  47  * 82579LM Gigabit Network Connection
  48  * 82579V Gigabit Network Connection
  49  * Ethernet Connection I217-LM
  50  * Ethernet Connection I217-V
  51  * Ethernet Connection I218-V
  52  * Ethernet Connection I218-LM
  53  * Ethernet Connection (2) I218-LM
  54  * Ethernet Connection (2) I218-V
  55  * Ethernet Connection (3) I218-LM
  56  * Ethernet Connection (3) I218-V
  57  */
  58
  59 #include "e1000.h"
  60
  61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
  62 /* Offset 04h HSFSTS */
  63 union ich8_hws_flash_status {
  64         struct ich8_hsfsts {
  65                 u16 flcdone:1;  /* bit 0 Flash Cycle Done */
  66                 u16 flcerr:1;   /* bit 1 Flash Cycle Error */
  67                 u16 dael:1;     /* bit 2 Direct Access error Log */
  68                 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
  69                 u16 flcinprog:1;        /* bit 5 flash cycle in Progress */
  70                 u16 reserved1:2;        /* bit 13:6 Reserved */
  71                 u16 reserved2:6;        /* bit 13:6 Reserved */
  72                 u16 fldesvalid:1;       /* bit 14 Flash Descriptor Valid */
  73                 u16 flockdn:1;  /* bit 15 Flash Config Lock-Down */
  74         } hsf_status;
  75         u16 regval;
  76 };
  77
  78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
  79 /* Offset 06h FLCTL */
  80 union ich8_hws_flash_ctrl {
  81         struct ich8_hsflctl {
  82                 u16 flcgo:1;    /* 0 Flash Cycle Go */
  83                 u16 flcycle:2;  /* 2:1 Flash Cycle */
  84                 u16 reserved:5; /* 7:3 Reserved  */
  85                 u16 fldbcount:2;        /* 9:8 Flash Data Byte Count */
  86                 u16 flockdn:6;  /* 15:10 Reserved */
  87         } hsf_ctrl;
  88         u16 regval;
  89 };
  90
  91 /* ICH Flash Region Access Permissions */
  92 union ich8_hws_flash_regacc {
  93         struct ich8_flracc {
  94                 u32 grra:8;     /* 0:7 GbE region Read Access */
  95                 u32 grwa:8;     /* 8:15 GbE region Write Access */
  96                 u32 gmrag:8;    /* 23:16 GbE Master Read Access Grant */
  97                 u32 gmwag:8;    /* 31:24 GbE Master Write Access Grant */
  98         } hsf_flregacc;
  99         u16 regval;
 100 };
 101
 102 /* ICH Flash Protected Region */
 103 union ich8_flash_protected_range {
 104         struct ich8_pr {
 105                 u32 base:13;    /* 0:12 Protected Range Base */
 106                 u32 reserved1:2;        /* 13:14 Reserved */
 107                 u32 rpe:1;      /* 15 Read Protection Enable */
 108                 u32 limit:13;   /* 16:28 Protected Range Limit */
 109                 u32 reserved2:2;        /* 29:30 Reserved */
 110                 u32 wpe:1;      /* 31 Write Protection Enable */
 111         } range;
 112         u32 regval;
 113 };
 114
 115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 119                                                 u32 offset, u8 byte);
 120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 121                                          u8 *data);
 122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 123                                          u16 *data);
 124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 125                                          u8 size, u16 *data);
 126 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
 127                                            u32 *data);
 128 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
 129                                           u32 offset, u32 *data);
 130 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
 131                                             u32 offset, u32 data);
 132 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
 133                                                  u32 offset, u32 dword);
 134 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 135 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 136 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 137 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 138 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 139 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 140 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 141 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 142 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 143 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 144 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 145 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 146 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 147 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 148 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 149 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 150 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 151 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
 152 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
 153 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 154 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 155 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
 156 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
 157 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
 158
 159 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 160 {
 161         return readw(hw->flash_address + reg);
 162 }
 163
 164 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 165 {
 166         return readl(hw->flash_address + reg);
 167 }
 168
 169 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 170 {
 171         writew(val, hw->flash_address + reg);
 172 }
 173
 174 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 175 {
 176         writel(val, hw->flash_address + reg);
 177 }
 178
 179 #define er16flash(reg)          __er16flash(hw, (reg))
 180 #define er32flash(reg)          __er32flash(hw, (reg))
 181 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 182 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 183
 184 /**
 185  *  e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
 186  *  @hw: pointer to the HW structure
 187  *
 188  *  Test access to the PHY registers by reading the PHY ID registers.  If
 189  *  the PHY ID is already known (e.g. resume path) compare it with known ID,
 190  *  otherwise assume the read PHY ID is correct if it is valid.
 191  *
 192  *  Assumes the sw/fw/hw semaphore is already acquired.
 193  **/
 194 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
 195 {
 196         u16 phy_reg = 0;
 197         u32 phy_id = 0;
 198         s32 ret_val = 0;
 199         u16 retry_count;
 200         u32 mac_reg = 0;
 201
 202         for (retry_count = 0; retry_count < 2; retry_count++) {
 203                 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
 204                 if (ret_val || (phy_reg == 0xFFFF))
 205                         continue;
 206                 phy_id = (u32)(phy_reg << 16);
 207
 208                 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
 209                 if (ret_val || (phy_reg == 0xFFFF)) {
 210                         phy_id = 0;
 211                         continue;
 212                 }
 213                 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
 214                 break;
 215         }
 216
 217         if (hw->phy.id) {
 218                 if (hw->phy.id == phy_id)
 219                         goto out;
 220         } else if (phy_id) {
 221                 hw->phy.id = phy_id;
 222                 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
 223                 goto out;
 224         }
 225
 226         /* In case the PHY needs to be in mdio slow mode,
 227          * set slow mode and try to get the PHY id again.
 228          */
 229         if (hw->mac.type < e1000_pch_lpt) {
 230                 hw->phy.ops.release(hw);
 231                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 232                 if (!ret_val)
 233                         ret_val = e1000e_get_phy_id(hw);
 234                 hw->phy.ops.acquire(hw);
 235         }
 236
 237         if (ret_val)
 238                 return false;
 239 out:
 240         if (hw->mac.type >= e1000_pch_lpt) {
 241                 /* Only unforce SMBus if ME is not active */
 242                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 243                         /* Unforce SMBus mode in PHY */
 244                         e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
 245                         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
 246                         e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
 247
 248                         /* Unforce SMBus mode in MAC */
 249                         mac_reg = er32(CTRL_EXT);
 250                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 251                         ew32(CTRL_EXT, mac_reg);
 252                 }
 253         }
 254
 255         return true;
 256 }
 257
 258 /**
 259  *  e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
 260  *  @hw: pointer to the HW structure
 261  *
 262  *  Toggling the LANPHYPC pin value fully power-cycles the PHY and is
 263  *  used to reset the PHY to a quiescent state when necessary.
 264  **/
 265 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
 266 {
 267         u32 mac_reg;
 268
 269         /* Set Phy Config Counter to 50msec */
 270         mac_reg = er32(FEXTNVM3);
 271         mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
 272         mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
 273         ew32(FEXTNVM3, mac_reg);
 274
 275         /* Toggle LANPHYPC Value bit */
 276         mac_reg = er32(CTRL);
 277         mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
 278         mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
 279         ew32(CTRL, mac_reg);
 280         e1e_flush();
 281         usleep_range(10, 20);
 282         mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 283         ew32(CTRL, mac_reg);
 284         e1e_flush();
 285
 286         if (hw->mac.type < e1000_pch_lpt) {
 287                 msleep(50);
 288         } else {
 289                 u16 count = 20;
 290
 291                 do {
 292                         usleep_range(5000, 10000);
 293                 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
 294
 295                 msleep(30);
 296         }
 297 }
 298
 299 /**
 300  *  e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
 301  *  @hw: pointer to the HW structure
 302  *
 303  *  Workarounds/flow necessary for PHY initialization during driver load
 304  *  and resume paths.
 305  **/
 306 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
 307 {
 308         struct e1000_adapter *adapter = hw->adapter;
 309         u32 mac_reg, fwsm = er32(FWSM);
 310         s32 ret_val;
 311
 312         /* Gate automatic PHY configuration by hardware on managed and
 313          * non-managed 82579 and newer adapters.
 314          */
 315         e1000_gate_hw_phy_config_ich8lan(hw, true);
 316
 317         /* It is not possible to be certain of the current state of ULP
 318          * so forcibly disable it.
 319          */
 320         hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
 321         e1000_disable_ulp_lpt_lp(hw, true);
 322
 323         ret_val = hw->phy.ops.acquire(hw);
 324         if (ret_val) {
 325                 e_dbg("Failed to initialize PHY flow\n");
 326                 goto out;
 327         }
 328
 329         /* The MAC-PHY interconnect may be in SMBus mode.  If the PHY is
 330          * inaccessible and resetting the PHY is not blocked, toggle the
 331          * LANPHYPC Value bit to force the interconnect to PCIe mode.
 332          */
 333         switch (hw->mac.type) {
 334         case e1000_pch_lpt:
 335         case e1000_pch_spt:
 336         case e1000_pch_cnp:
 337                 if (e1000_phy_is_accessible_pchlan(hw))
 338                         break;
 339
 340                 /* Before toggling LANPHYPC, see if PHY is accessible by
 341                  * forcing MAC to SMBus mode first.
 342                  */
 343                 mac_reg = er32(CTRL_EXT);
 344                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
 345                 ew32(CTRL_EXT, mac_reg);
 346
 347                 /* Wait 50 milliseconds for MAC to finish any retries
 348                  * that it might be trying to perform from previous
 349                  * attempts to acknowledge any phy read requests.
 350                  */
 351                 msleep(50);
 352
 353                 /* fall-through */
 354         case e1000_pch2lan:
 355                 if (e1000_phy_is_accessible_pchlan(hw))
 356                         break;
 357
 358                 /* fall-through */
 359         case e1000_pchlan:
 360                 if ((hw->mac.type == e1000_pchlan) &&
 361                     (fwsm & E1000_ICH_FWSM_FW_VALID))
 362                         break;
 363
 364                 if (hw->phy.ops.check_reset_block(hw)) {
 365                         e_dbg("Required LANPHYPC toggle blocked by ME\n");
 366                         ret_val = -E1000_ERR_PHY;
 367                         break;
 368                 }
 369
 370                 /* Toggle LANPHYPC Value bit */
 371                 e1000_toggle_lanphypc_pch_lpt(hw);
 372                 if (hw->mac.type >= e1000_pch_lpt) {
 373                         if (e1000_phy_is_accessible_pchlan(hw))
 374                                 break;
 375
 376                         /* Toggling LANPHYPC brings the PHY out of SMBus mode
 377                          * so ensure that the MAC is also out of SMBus mode
 378                          */
 379                         mac_reg = er32(CTRL_EXT);
 380                         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
 381                         ew32(CTRL_EXT, mac_reg);
 382
 383                         if (e1000_phy_is_accessible_pchlan(hw))
 384                                 break;
 385
 386                         ret_val = -E1000_ERR_PHY;
 387                 }
 388                 break;
 389         default:
 390                 break;
 391         }
 392
 393         hw->phy.ops.release(hw);
 394         if (!ret_val) {
 395
 396                 /* Check to see if able to reset PHY.  Print error if not */
 397                 if (hw->phy.ops.check_reset_block(hw)) {
 398                         e_err("Reset blocked by ME\n");
 399                         goto out;
 400                 }
 401
 402                 /* Reset the PHY before any access to it.  Doing so, ensures
 403                  * that the PHY is in a known good state before we read/write
 404                  * PHY registers.  The generic reset is sufficient here,
 405                  * because we haven't determined the PHY type yet.
 406                  */
 407                 ret_val = e1000e_phy_hw_reset_generic(hw);
 408                 if (ret_val)
 409                         goto out;
 410
 411                 /* On a successful reset, possibly need to wait for the PHY
 412                  * to quiesce to an accessible state before returning control
 413                  * to the calling function.  If the PHY does not quiesce, then
 414                  * return E1000E_BLK_PHY_RESET, as this is the condition that
 415                  *  the PHY is in.
 416                  */
 417                 ret_val = hw->phy.ops.check_reset_block(hw);
 418                 if (ret_val)
 419                         e_err("ME blocked access to PHY after reset\n");
 420         }
 421
 422 out:
 423         /* Ungate automatic PHY configuration on non-managed 82579 */
 424         if ((hw->mac.type == e1000_pch2lan) &&
 425             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 426                 usleep_range(10000, 20000);
 427                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 428         }
 429
 430         return ret_val;
 431 }
 432
 433 /**
 434  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 435  *  @hw: pointer to the HW structure
 436  *
 437  *  Initialize family-specific PHY parameters and function pointers.
 438  **/
 439 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 440 {
 441         struct e1000_phy_info *phy = &hw->phy;
 442         s32 ret_val;
 443
 444         phy->addr = 1;
 445         phy->reset_delay_us = 100;
 446
 447         phy->ops.set_page = e1000_set_page_igp;
 448         phy->ops.read_reg = e1000_read_phy_reg_hv;
 449         phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
 450         phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
 451         phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
 452         phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
 453         phy->ops.write_reg = e1000_write_phy_reg_hv;
 454         phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
 455         phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
 456         phy->ops.power_up = e1000_power_up_phy_copper;
 457         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 458         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 459
 460         phy->id = e1000_phy_unknown;
 461
 462         ret_val = e1000_init_phy_workarounds_pchlan(hw);
 463         if (ret_val)
 464                 return ret_val;
 465
 466         if (phy->id == e1000_phy_unknown)
 467                 switch (hw->mac.type) {
 468                 default:
 469                         ret_val = e1000e_get_phy_id(hw);
 470                         if (ret_val)
 471                                 return ret_val;
 472                         if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 473                                 break;
 474                         /* fall-through */
 475                 case e1000_pch2lan:
 476                 case e1000_pch_lpt:
 477                 case e1000_pch_spt:
 478                 case e1000_pch_cnp:
 479                         /* In case the PHY needs to be in mdio slow mode,
 480                          * set slow mode and try to get the PHY id again.
 481                          */
 482                         ret_val = e1000_set_mdio_slow_mode_hv(hw);
 483                         if (ret_val)
 484                                 return ret_val;
 485                         ret_val = e1000e_get_phy_id(hw);
 486                         if (ret_val)
 487                                 return ret_val;
 488                         break;
 489                 }
 490         phy->type = e1000e_get_phy_type_from_id(phy->id);
 491
 492         switch (phy->type) {
 493         case e1000_phy_82577:
 494         case e1000_phy_82579:
 495         case e1000_phy_i217:
 496                 phy->ops.check_polarity = e1000_check_polarity_82577;
 497                 phy->ops.force_speed_duplex =
 498                     e1000_phy_force_speed_duplex_82577;
 499                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 500                 phy->ops.get_info = e1000_get_phy_info_82577;
 501                 phy->ops.commit = e1000e_phy_sw_reset;
 502                 break;
 503         case e1000_phy_82578:
 504                 phy->ops.check_polarity = e1000_check_polarity_m88;
 505                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 506                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 507                 phy->ops.get_info = e1000e_get_phy_info_m88;
 508                 break;
 509         default:
 510                 ret_val = -E1000_ERR_PHY;
 511                 break;
 512         }
 513
 514         return ret_val;
 515 }
 516
 517 /**
 518  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 519  *  @hw: pointer to the HW structure
 520  *
 521  *  Initialize family-specific PHY parameters and function pointers.
 522  **/
 523 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 524 {
 525         struct e1000_phy_info *phy = &hw->phy;
 526         s32 ret_val;
 527         u16 i = 0;
 528
 529         phy->addr = 1;
 530         phy->reset_delay_us = 100;
 531
 532         phy->ops.power_up = e1000_power_up_phy_copper;
 533         phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
 534
 535         /* We may need to do this twice - once for IGP and if that fails,
 536          * we'll set BM func pointers and try again
 537          */
 538         ret_val = e1000e_determine_phy_address(hw);
 539         if (ret_val) {
 540                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 541                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 542                 ret_val = e1000e_determine_phy_address(hw);
 543                 if (ret_val) {
 544                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 545                         return ret_val;
 546                 }
 547         }
 548
 549         phy->id = 0;
 550         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 551                (i++ < 100)) {
 552                 usleep_range(1000, 2000);
 553                 ret_val = e1000e_get_phy_id(hw);
 554                 if (ret_val)
 555                         return ret_val;
 556         }
 557
 558         /* Verify phy id */
 559         switch (phy->id) {
 560         case IGP03E1000_E_PHY_ID:
 561                 phy->type = e1000_phy_igp_3;
 562                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 563                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 564                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 565                 phy->ops.get_info = e1000e_get_phy_info_igp;
 566                 phy->ops.check_polarity = e1000_check_polarity_igp;
 567                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 568                 break;
 569         case IFE_E_PHY_ID:
 570         case IFE_PLUS_E_PHY_ID:
 571         case IFE_C_E_PHY_ID:
 572                 phy->type = e1000_phy_ife;
 573                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 574                 phy->ops.get_info = e1000_get_phy_info_ife;
 575                 phy->ops.check_polarity = e1000_check_polarity_ife;
 576                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 577                 break;
 578         case BME1000_E_PHY_ID:
 579                 phy->type = e1000_phy_bm;
 580                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 581                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 582                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 583                 phy->ops.commit = e1000e_phy_sw_reset;
 584                 phy->ops.get_info = e1000e_get_phy_info_m88;
 585                 phy->ops.check_polarity = e1000_check_polarity_m88;
 586                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 587                 break;
 588         default:
 589                 return -E1000_ERR_PHY;
 590         }
 591
 592         return 0;
 593 }
 594
 595 /**
 596  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 597  *  @hw: pointer to the HW structure
 598  *
 599  *  Initialize family-specific NVM parameters and function
 600  *  pointers.
 601  **/
 602 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 603 {
 604         struct e1000_nvm_info *nvm = &hw->nvm;
 605         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 606         u32 gfpreg, sector_base_addr, sector_end_addr;
 607         u16 i;
 608         u32 nvm_size;
 609
 610         nvm->type = e1000_nvm_flash_sw;
 611
 612         if (hw->mac.type >= e1000_pch_spt) {
 613                 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
 614                  * STRAP register. This is because in SPT the GbE Flash region
 615                  * is no longer accessed through the flash registers. Instead,
 616                  * the mechanism has changed, and the Flash region access
 617                  * registers are now implemented in GbE memory space.
 618                  */
 619                 nvm->flash_base_addr = 0;
 620                 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
 621                     * NVM_SIZE_MULTIPLIER;
 622                 nvm->flash_bank_size = nvm_size / 2;
 623                 /* Adjust to word count */
 624                 nvm->flash_bank_size /= sizeof(u16);
 625                 /* Set the base address for flash register access */
 626                 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
 627         } else {
 628                 /* Can't read flash registers if register set isn't mapped. */
 629                 if (!hw->flash_address) {
 630                         e_dbg("ERROR: Flash registers not mapped\n");
 631                         return -E1000_ERR_CONFIG;
 632                 }
 633
 634                 gfpreg = er32flash(ICH_FLASH_GFPREG);
 635
 636                 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
 637                  * Add 1 to sector_end_addr since this sector is included in
 638                  * the overall size.
 639                  */
 640                 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 641                 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 642
 643                 /* flash_base_addr is byte-aligned */
 644                 nvm->flash_base_addr = sector_base_addr
 645                     << FLASH_SECTOR_ADDR_SHIFT;
 646
 647                 /* find total size of the NVM, then cut in half since the total
 648                  * size represents two separate NVM banks.
 649                  */
 650                 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
 651                                         << FLASH_SECTOR_ADDR_SHIFT);
 652                 nvm->flash_bank_size /= 2;
 653                 /* Adjust to word count */
 654                 nvm->flash_bank_size /= sizeof(u16);
 655         }
 656
 657         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 658
 659         /* Clear shadow ram */
 660         for (i = 0; i < nvm->word_size; i++) {
 661                 dev_spec->shadow_ram[i].modified = false;
 662                 dev_spec->shadow_ram[i].value = 0xFFFF;
 663         }
 664
 665         return 0;
 666 }
 667
 668 /**
 669  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 670  *  @hw: pointer to the HW structure
 671  *
 672  *  Initialize family-specific MAC parameters and function
 673  *  pointers.
 674  **/
 675 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 676 {
 677         struct e1000_mac_info *mac = &hw->mac;
 678
 679         /* Set media type function pointer */
 680         hw->phy.media_type = e1000_media_type_copper;
 681
 682         /* Set mta register count */
 683         mac->mta_reg_count = 32;
 684         /* Set rar entry count */
 685         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 686         if (mac->type == e1000_ich8lan)
 687                 mac->rar_entry_count--;
 688         /* FWSM register */
 689         mac->has_fwsm = true;
 690         /* ARC subsystem not supported */
 691         mac->arc_subsystem_valid = false;
 692         /* Adaptive IFS supported */
 693         mac->adaptive_ifs = true;
 694
 695         /* LED and other operations */
 696         switch (mac->type) {
 697         case e1000_ich8lan:
 698         case e1000_ich9lan:
 699         case e1000_ich10lan:
 700                 /* check management mode */
 701                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 702                 /* ID LED init */
 703                 mac->ops.id_led_init = e1000e_id_led_init_generic;
 704                 /* blink LED */
 705                 mac->ops.blink_led = e1000e_blink_led_generic;
 706                 /* setup LED */
 707                 mac->ops.setup_led = e1000e_setup_led_generic;
 708                 /* cleanup LED */
 709                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 710                 /* turn on/off LED */
 711                 mac->ops.led_on = e1000_led_on_ich8lan;
 712                 mac->ops.led_off = e1000_led_off_ich8lan;
 713                 break;
 714         case e1000_pch2lan:
 715                 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
 716                 mac->ops.rar_set = e1000_rar_set_pch2lan;
 717                 /* fall-through */
 718         case e1000_pch_lpt:
 719         case e1000_pch_spt:
 720         case e1000_pch_cnp:
 721         case e1000_pchlan:
 722                 /* check management mode */
 723                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 724                 /* ID LED init */
 725                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 726                 /* setup LED */
 727                 mac->ops.setup_led = e1000_setup_led_pchlan;
 728                 /* cleanup LED */
 729                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 730                 /* turn on/off LED */
 731                 mac->ops.led_on = e1000_led_on_pchlan;
 732                 mac->ops.led_off = e1000_led_off_pchlan;
 733                 break;
 734         default:
 735                 break;
 736         }
 737
 738         if (mac->type >= e1000_pch_lpt) {
 739                 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
 740                 mac->ops.rar_set = e1000_rar_set_pch_lpt;
 741                 mac->ops.setup_physical_interface =
 742                     e1000_setup_copper_link_pch_lpt;
 743                 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
 744         }
 745
 746         /* Enable PCS Lock-loss workaround for ICH8 */
 747         if (mac->type == e1000_ich8lan)
 748                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 749
 750         return 0;
 751 }
 752
 753 /**
 754  *  __e1000_access_emi_reg_locked - Read/write EMI register
 755  *  @hw: pointer to the HW structure
 756  *  @addr: EMI address to program
 757  *  @data: pointer to value to read/write from/to the EMI address
 758  *  @read: boolean flag to indicate read or write
 759  *
 760  *  This helper function assumes the SW/FW/HW Semaphore is already acquired.
 761  **/
 762 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
 763                                          u16 *data, bool read)
 764 {
 765         s32 ret_val;
 766
 767         ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
 768         if (ret_val)
 769                 return ret_val;
 770
 771         if (read)
 772                 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
 773         else
 774                 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
 775
 776         return ret_val;
 777 }
 778
 779 /**
 780  *  e1000_read_emi_reg_locked - Read Extended Management Interface register
 781  *  @hw: pointer to the HW structure
 782  *  @addr: EMI address to program
 783  *  @data: value to be read from the EMI address
 784  *
 785  *  Assumes the SW/FW/HW Semaphore is already acquired.
 786  **/
 787 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
 788 {
 789         return __e1000_access_emi_reg_locked(hw, addr, data, true);
 790 }
 791
 792 /**
 793  *  e1000_write_emi_reg_locked - Write Extended Management Interface register
 794  *  @hw: pointer to the HW structure
 795  *  @addr: EMI address to program
 796  *  @data: value to be written to the EMI address
 797  *
 798  *  Assumes the SW/FW/HW Semaphore is already acquired.
 799  **/
 800 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
 801 {
 802         return __e1000_access_emi_reg_locked(hw, addr, &data, false);
 803 }
 804
 805 /**
 806  *  e1000_set_eee_pchlan - Enable/disable EEE support
 807  *  @hw: pointer to the HW structure
 808  *
 809  *  Enable/disable EEE based on setting in dev_spec structure, the duplex of
 810  *  the link and the EEE capabilities of the link partner.  The LPI Control
 811  *  register bits will remain set only if/when link is up.
 812  *
 813  *  EEE LPI must not be asserted earlier than one second after link is up.
 814  *  On 82579, EEE LPI should not be enabled until such time otherwise there
 815  *  can be link issues with some switches.  Other devices can have EEE LPI
 816  *  enabled immediately upon link up since they have a timer in hardware which
 817  *  prevents LPI from being asserted too early.
 818  **/
 819 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 820 {
 821         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 822         s32 ret_val;
 823         u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
 824
 825         switch (hw->phy.type) {
 826         case e1000_phy_82579:
 827                 lpa = I82579_EEE_LP_ABILITY;
 828                 pcs_status = I82579_EEE_PCS_STATUS;
 829                 adv_addr = I82579_EEE_ADVERTISEMENT;
 830                 break;
 831         case e1000_phy_i217:
 832                 lpa = I217_EEE_LP_ABILITY;
 833                 pcs_status = I217_EEE_PCS_STATUS;
 834                 adv_addr = I217_EEE_ADVERTISEMENT;
 835                 break;
 836         default:
 837                 return 0;
 838         }
 839
 840         ret_val = hw->phy.ops.acquire(hw);
 841         if (ret_val)
 842                 return ret_val;
 843
 844         ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
 845         if (ret_val)
 846                 goto release;
 847
 848         /* Clear bits that enable EEE in various speeds */
 849         lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
 850
 851         /* Enable EEE if not disabled by user */
 852         if (!dev_spec->eee_disable) {
 853                 /* Save off link partner's EEE ability */
 854                 ret_val = e1000_read_emi_reg_locked(hw, lpa,
 855                                                     &dev_spec->eee_lp_ability);
 856                 if (ret_val)
 857                         goto release;
 858
 859                 /* Read EEE advertisement */
 860                 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
 861                 if (ret_val)
 862                         goto release;
 863
 864                 /* Enable EEE only for speeds in which the link partner is
 865                  * EEE capable and for which we advertise EEE.
 866                  */
 867                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
 868                         lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
 869
 870                 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
 871                         e1e_rphy_locked(hw, MII_LPA, &data);
 872                         if (data & LPA_100FULL)
 873                                 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
 874                         else
 875                                 /* EEE is not supported in 100Half, so ignore
 876                                  * partner's EEE in 100 ability if full-duplex
 877                                  * is not advertised.
 878                                  */
 879                                 dev_spec->eee_lp_ability &=
 880                                     ~I82579_EEE_100_SUPPORTED;
 881                 }
 882         }
 883
 884         if (hw->phy.type == e1000_phy_82579) {
 885                 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 886                                                     &data);
 887                 if (ret_val)
 888                         goto release;
 889
 890                 data &= ~I82579_LPI_100_PLL_SHUT;
 891                 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
 892                                                      data);
 893         }
 894
 895         /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
 896         ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
 897         if (ret_val)
 898                 goto release;
 899
 900         ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
 901 release:
 902         hw->phy.ops.release(hw);
 903
 904         return ret_val;
 905 }
 906
 907 /**
 908  *  e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
 909  *  @hw:   pointer to the HW structure
 910  *  @link: link up bool flag
 911  *
 912  *  When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
 913  *  preventing further DMA write requests.  Workaround the issue by disabling
 914  *  the de-assertion of the clock request when in 1Gpbs mode.
 915  *  Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
 916  *  speeds in order to avoid Tx hangs.
 917  **/
 918 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
 919 {
 920         u32 fextnvm6 = er32(FEXTNVM6);
 921         u32 status = er32(STATUS);
 922         s32 ret_val = 0;
 923         u16 reg;
 924
 925         if (link && (status & E1000_STATUS_SPEED_1000)) {
 926                 ret_val = hw->phy.ops.acquire(hw);
 927                 if (ret_val)
 928                         return ret_val;
 929
 930                 ret_val =
 931                     e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
 932                                                 &reg);
 933                 if (ret_val)
 934                         goto release;
 935
 936                 ret_val =
 937                     e1000e_write_kmrn_reg_locked(hw,
 938                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 939                                                  reg &
 940                                                  ~E1000_KMRNCTRLSTA_K1_ENABLE);
 941                 if (ret_val)
 942                         goto release;
 943
 944                 usleep_range(10, 20);
 945
 946                 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
 947
 948                 ret_val =
 949                     e1000e_write_kmrn_reg_locked(hw,
 950                                                  E1000_KMRNCTRLSTA_K1_CONFIG,
 951                                                  reg);
 952 release:
 953                 hw->phy.ops.release(hw);
 954         } else {
 955                 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
 956                 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
 957
 958                 if ((hw->phy.revision > 5) || !link ||
 959                     ((status & E1000_STATUS_SPEED_100) &&
 960                      (status & E1000_STATUS_FD)))
 961                         goto update_fextnvm6;
 962
 963                 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
 964                 if (ret_val)
 965                         return ret_val;
 966
 967                 /* Clear link status transmit timeout */
 968                 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
 969
 970                 if (status & E1000_STATUS_SPEED_100) {
 971                         /* Set inband Tx timeout to 5x10us for 100Half */
 972                         reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 973
 974                         /* Do not extend the K1 entry latency for 100Half */
 975                         fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 976                 } else {
 977                         /* Set inband Tx timeout to 50x10us for 10Full/Half */
 978                         reg |= 50 <<
 979                             I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
 980
 981                         /* Extend the K1 entry latency for 10 Mbps */
 982                         fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
 983                 }
 984
 985                 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
 986                 if (ret_val)
 987                         return ret_val;
 988
 989 update_fextnvm6:
 990                 ew32(FEXTNVM6, fextnvm6);
 991         }
 992
 993         return ret_val;
 994 }
 995
 996 /**
 997  *  e1000_platform_pm_pch_lpt - Set platform power management values
 998  *  @hw: pointer to the HW structure
 999  *  @link: bool indicating link status
1000  *
1001  *  Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1002  *  GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1003  *  when link is up (which must not exceed the maximum latency supported
1004  *  by the platform), otherwise specify there is no LTR requirement.
1005  *  Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1006  *  latencies in the LTR Extended Capability Structure in the PCIe Extended
1007  *  Capability register set, on this device LTR is set by writing the
1008  *  equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1009  *  set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1010  *  message to the PMC.
1011  **/
1012 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1013 {
1014         u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1015             link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1016         u32 max_ltr_enc_d = 0;  /* maximum LTR decoded by platform */
1017         u32 lat_enc_d = 0;      /* latency decoded */
1018         u16 lat_enc = 0;        /* latency encoded */
1019
1020         if (link) {
1021                 u16 speed, duplex, scale = 0;
1022                 u16 max_snoop, max_nosnoop;
1023                 u16 max_ltr_enc;        /* max LTR latency encoded */
1024                 u64 value;
1025                 u32 rxa;
1026
1027                 if (!hw->adapter->max_frame_size) {
1028                         e_dbg("max_frame_size not set.\n");
1029                         return -E1000_ERR_CONFIG;
1030                 }
1031
1032                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1033                 if (!speed) {
1034                         e_dbg("Speed not set.\n");
1035                         return -E1000_ERR_CONFIG;
1036                 }
1037
1038                 /* Rx Packet Buffer Allocation size (KB) */
1039                 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1040
1041                 /* Determine the maximum latency tolerated by the device.
1042                  *
1043                  * Per the PCIe spec, the tolerated latencies are encoded as
1044                  * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1045                  * a 10-bit value (0-1023) to provide a range from 1 ns to
1046                  * 2^25*(2^10-1) ns.  The scale is encoded as 0=2^0ns,
1047                  * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1048                  */
1049                 rxa *= 512;
1050                 value = (rxa > hw->adapter->max_frame_size) ?
1051                         (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1052                         0;
1053
1054                 while (value > PCI_LTR_VALUE_MASK) {
1055                         scale++;
1056                         value = DIV_ROUND_UP(value, BIT(5));
1057                 }
1058                 if (scale > E1000_LTRV_SCALE_MAX) {
1059                         e_dbg("Invalid LTR latency scale %d\n", scale);
1060                         return -E1000_ERR_CONFIG;
1061                 }
1062                 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1063
1064                 /* Determine the maximum latency tolerated by the platform */
1065                 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1066                                      &max_snoop);
1067                 pci_read_config_word(hw->adapter->pdev,
1068                                      E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1069                 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1070
1071                 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) *
1072                              (1U << (E1000_LTRV_SCALE_FACTOR *
1073                              ((lat_enc & E1000_LTRV_SCALE_MASK)
1074                              >> E1000_LTRV_SCALE_SHIFT)));
1075
1076                 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) *
1077                                  (1U << (E1000_LTRV_SCALE_FACTOR *
1078                                  ((max_ltr_enc & E1000_LTRV_SCALE_MASK)
1079                                  >> E1000_LTRV_SCALE_SHIFT)));
1080
1081                 if (lat_enc_d > max_ltr_enc_d)
1082                         lat_enc = max_ltr_enc;
1083         }
1084
1085         /* Set Snoop and No-Snoop latencies the same */
1086         reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1087         ew32(LTRV, reg);
1088
1089         return 0;
1090 }
1091
1092 /**
1093  *  e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1094  *  @hw: pointer to the HW structure
1095  *  @to_sx: boolean indicating a system power state transition to Sx
1096  *
1097  *  When link is down, configure ULP mode to significantly reduce the power
1098  *  to the PHY.  If on a Manageability Engine (ME) enabled system, tell the
1099  *  ME firmware to start the ULP configuration.  If not on an ME enabled
1100  *  system, configure the ULP mode by software.
1101  */
1102 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1103 {
1104         u32 mac_reg;
1105         s32 ret_val = 0;
1106         u16 phy_reg;
1107         u16 oem_reg = 0;
1108
1109         if ((hw->mac.type < e1000_pch_lpt) ||
1110             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1111             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1112             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1113             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1114             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1115                 return 0;
1116
1117         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1118                 /* Request ME configure ULP mode in the PHY */
1119                 mac_reg = er32(H2ME);
1120                 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1121                 ew32(H2ME, mac_reg);
1122
1123                 goto out;
1124         }
1125
1126         if (!to_sx) {
1127                 int i = 0;
1128
1129                 /* Poll up to 5 seconds for Cable Disconnected indication */
1130                 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1131                         /* Bail if link is re-acquired */
1132                         if (er32(STATUS) & E1000_STATUS_LU)
1133                                 return -E1000_ERR_PHY;
1134
1135                         if (i++ == 100)
1136                                 break;
1137
1138                         msleep(50);
1139                 }
1140                 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1141                       (er32(FEXT) &
1142                        E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1143         }
1144
1145         ret_val = hw->phy.ops.acquire(hw);
1146         if (ret_val)
1147                 goto out;
1148
1149         /* Force SMBus mode in PHY */
1150         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1151         if (ret_val)
1152                 goto release;
1153         phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1154         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1155
1156         /* Force SMBus mode in MAC */
1157         mac_reg = er32(CTRL_EXT);
1158         mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1159         ew32(CTRL_EXT, mac_reg);
1160
1161         /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
1162          * LPLU and disable Gig speed when entering ULP
1163          */
1164         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1165                 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1166                                                        &oem_reg);
1167                 if (ret_val)
1168                         goto release;
1169
1170                 phy_reg = oem_reg;
1171                 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1172
1173                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1174                                                         phy_reg);
1175
1176                 if (ret_val)
1177                         goto release;
1178         }
1179
1180         /* Set Inband ULP Exit, Reset to SMBus mode and
1181          * Disable SMBus Release on PERST# in PHY
1182          */
1183         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1184         if (ret_val)
1185                 goto release;
1186         phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1187                     I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1188         if (to_sx) {
1189                 if (er32(WUFC) & E1000_WUFC_LNKC)
1190                         phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1191                 else
1192                         phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1193
1194                 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1195                 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1196         } else {
1197                 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1198                 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1199                 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1200         }
1201         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1202
1203         /* Set Disable SMBus Release on PERST# in MAC */
1204         mac_reg = er32(FEXTNVM7);
1205         mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1206         ew32(FEXTNVM7, mac_reg);
1207
1208         /* Commit ULP changes in PHY by starting auto ULP configuration */
1209         phy_reg |= I218_ULP_CONFIG1_START;
1210         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1211
1212         if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1213             to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1214                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1215                                                         oem_reg);
1216                 if (ret_val)
1217                         goto release;
1218         }
1219
1220 release:
1221         hw->phy.ops.release(hw);
1222 out:
1223         if (ret_val)
1224                 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1225         else
1226                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1227
1228         return ret_val;
1229 }
1230
1231 /**
1232  *  e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1233  *  @hw: pointer to the HW structure
1234  *  @force: boolean indicating whether or not to force disabling ULP
1235  *
1236  *  Un-configure ULP mode when link is up, the system is transitioned from
1237  *  Sx or the driver is unloaded.  If on a Manageability Engine (ME) enabled
1238  *  system, poll for an indication from ME that ULP has been un-configured.
1239  *  If not on an ME enabled system, un-configure the ULP mode by software.
1240  *
1241  *  During nominal operation, this function is called when link is acquired
1242  *  to disable ULP mode (force=false); otherwise, for example when unloading
1243  *  the driver or during Sx->S0 transitions, this is called with force=true
1244  *  to forcibly disable ULP.
1245  */
1246 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1247 {
1248         s32 ret_val = 0;
1249         u32 mac_reg;
1250         u16 phy_reg;
1251         int i = 0;
1252
1253         if ((hw->mac.type < e1000_pch_lpt) ||
1254             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1255             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1256             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1257             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1258             (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1259                 return 0;
1260
1261         if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1262                 if (force) {
1263                         /* Request ME un-configure ULP mode in the PHY */
1264                         mac_reg = er32(H2ME);
1265                         mac_reg &= ~E1000_H2ME_ULP;
1266                         mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1267                         ew32(H2ME, mac_reg);
1268                 }
1269
1270                 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1271                 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1272                         if (i++ == 30) {
1273                                 ret_val = -E1000_ERR_PHY;
1274                                 goto out;
1275                         }
1276
1277                         usleep_range(10000, 20000);
1278                 }
1279                 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1280
1281                 if (force) {
1282                         mac_reg = er32(H2ME);
1283                         mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1284                         ew32(H2ME, mac_reg);
1285                 } else {
1286                         /* Clear H2ME.ULP after ME ULP configuration */
1287                         mac_reg = er32(H2ME);
1288                         mac_reg &= ~E1000_H2ME_ULP;
1289                         ew32(H2ME, mac_reg);
1290                 }
1291
1292                 goto out;
1293         }
1294
1295         ret_val = hw->phy.ops.acquire(hw);
1296         if (ret_val)
1297                 goto out;
1298
1299         if (force)
1300                 /* Toggle LANPHYPC Value bit */
1301                 e1000_toggle_lanphypc_pch_lpt(hw);
1302
1303         /* Unforce SMBus mode in PHY */
1304         ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1305         if (ret_val) {
1306                 /* The MAC might be in PCIe mode, so temporarily force to
1307                  * SMBus mode in order to access the PHY.
1308                  */
1309                 mac_reg = er32(CTRL_EXT);
1310                 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1311                 ew32(CTRL_EXT, mac_reg);
1312
1313                 msleep(50);
1314
1315                 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1316                                                        &phy_reg);
1317                 if (ret_val)
1318                         goto release;
1319         }
1320         phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1321         e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1322
1323         /* Unforce SMBus mode in MAC */
1324         mac_reg = er32(CTRL_EXT);
1325         mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1326         ew32(CTRL_EXT, mac_reg);
1327
1328         /* When ULP mode was previously entered, K1 was disabled by the
1329          * hardware.  Re-Enable K1 in the PHY when exiting ULP.
1330          */
1331         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1332         if (ret_val)
1333                 goto release;
1334         phy_reg |= HV_PM_CTRL_K1_ENABLE;
1335         e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1336
1337         /* Clear ULP enabled configuration */
1338         ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1339         if (ret_val)
1340                 goto release;
1341         phy_reg &= ~(I218_ULP_CONFIG1_IND |
1342                      I218_ULP_CONFIG1_STICKY_ULP |
1343                      I218_ULP_CONFIG1_RESET_TO_SMBUS |
1344                      I218_ULP_CONFIG1_WOL_HOST |
1345                      I218_ULP_CONFIG1_INBAND_EXIT |
1346                      I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1347                      I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1348                      I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1349         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1350
1351         /* Commit ULP changes by starting auto ULP configuration */
1352         phy_reg |= I218_ULP_CONFIG1_START;
1353         e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1354
1355         /* Clear Disable SMBus Release on PERST# in MAC */
1356         mac_reg = er32(FEXTNVM7);
1357         mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1358         ew32(FEXTNVM7, mac_reg);
1359
1360 release:
1361         hw->phy.ops.release(hw);
1362         if (force) {
1363                 e1000_phy_hw_reset(hw);
1364                 msleep(50);
1365         }
1366 out:
1367         if (ret_val)
1368                 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1369         else
1370                 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1371
1372         return ret_val;
1373 }
1374
1375 /**
1376  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1377  *  @hw: pointer to the HW structure
1378  *
1379  *  Checks to see of the link status of the hardware has changed.  If a
1380  *  change in link status has been detected, then we read the PHY registers
1381  *  to get the current speed/duplex if link exists.
1382  **/
1383 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1384 {
1385         struct e1000_mac_info *mac = &hw->mac;
1386         s32 ret_val, tipg_reg = 0;
1387         u16 emi_addr, emi_val = 0;
1388         bool link;
1389         u16 phy_reg;
1390
1391         /* We only want to go out to the PHY registers to see if Auto-Neg
1392          * has completed and/or if our link status has changed.  The
1393          * get_link_status flag is set upon receiving a Link Status
1394          * Change or Rx Sequence Error interrupt.
1395          */
1396         if (!mac->get_link_status)
1397                 return 0;
1398         mac->get_link_status = false;
1399
1400         /* First we want to see if the MII Status Register reports
1401          * link.  If so, then we want to get the current speed/duplex
1402          * of the PHY.
1403          */
1404         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1405         if (ret_val)
1406                 goto out;
1407
1408         if (hw->mac.type == e1000_pchlan) {
1409                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1410                 if (ret_val)
1411                         goto out;
1412         }
1413
1414         /* When connected at 10Mbps half-duplex, some parts are excessively
1415          * aggressive resulting in many collisions. To avoid this, increase
1416          * the IPG and reduce Rx latency in the PHY.
1417          */
1418         if ((hw->mac.type >= e1000_pch2lan) && link) {
1419                 u16 speed, duplex;
1420
1421                 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1422                 tipg_reg = er32(TIPG);
1423                 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1424
1425                 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1426                         tipg_reg |= 0xFF;
1427                         /* Reduce Rx latency in analog PHY */
1428                         emi_val = 0;
1429                 } else if (hw->mac.type >= e1000_pch_spt &&
1430                            duplex == FULL_DUPLEX && speed != SPEED_1000) {
1431                         tipg_reg |= 0xC;
1432                         emi_val = 1;
1433                 } else {
1434
1435                         /* Roll back the default values */
1436                         tipg_reg |= 0x08;
1437                         emi_val = 1;
1438                 }
1439
1440                 ew32(TIPG, tipg_reg);
1441
1442                 ret_val = hw->phy.ops.acquire(hw);
1443                 if (ret_val)
1444                         goto out;
1445
1446                 if (hw->mac.type == e1000_pch2lan)
1447                         emi_addr = I82579_RX_CONFIG;
1448                 else
1449                         emi_addr = I217_RX_CONFIG;
1450                 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1451
1452                 if (hw->mac.type >= e1000_pch_lpt) {
1453                         u16 phy_reg;
1454
1455                         e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1456                         phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1457                         if (speed == SPEED_100 || speed == SPEED_10)
1458                                 phy_reg |= 0x3E8;
1459                         else
1460                                 phy_reg |= 0xFA;
1461                         e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1462
1463                         if (speed == SPEED_1000) {
1464                                 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1465                                                             &phy_reg);
1466
1467                                 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1468
1469                                 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1470                                                              phy_reg);
1471                         }
1472                 }
1473                 hw->phy.ops.release(hw);
1474
1475                 if (ret_val)
1476                         goto out;
1477
1478                 if (hw->mac.type >= e1000_pch_spt) {
1479                         u16 data;
1480                         u16 ptr_gap;
1481
1482                         if (speed == SPEED_1000) {
1483                                 ret_val = hw->phy.ops.acquire(hw);
1484                                 if (ret_val)
1485                                         goto out;
1486
1487                                 ret_val = e1e_rphy_locked(hw,
1488                                                           PHY_REG(776, 20),
1489                                                           &data);
1490                                 if (ret_val) {
1491                                         hw->phy.ops.release(hw);
1492                                         goto out;
1493                                 }
1494
1495                                 ptr_gap = (data & (0x3FF << 2)) >> 2;
1496                                 if (ptr_gap < 0x18) {
1497                                         data &= ~(0x3FF << 2);
1498                                         data |= (0x18 << 2);
1499                                         ret_val =
1500                                             e1e_wphy_locked(hw,
1501                                                             PHY_REG(776, 20),
1502                                                             data);
1503                                 }
1504                                 hw->phy.ops.release(hw);
1505                                 if (ret_val)
1506                                         goto out;
1507                         } else {
1508                                 ret_val = hw->phy.ops.acquire(hw);
1509                                 if (ret_val)
1510                                         goto out;
1511
1512                                 ret_val = e1e_wphy_locked(hw,
1513                                                           PHY_REG(776, 20),
1514                                                           0xC023);
1515                                 hw->phy.ops.release(hw);
1516                                 if (ret_val)
1517                                         goto out;
1518
1519                         }
1520                 }
1521         }
1522
1523         /* I217 Packet Loss issue:
1524          * ensure that FEXTNVM4 Beacon Duration is set correctly
1525          * on power up.
1526          * Set the Beacon Duration for I217 to 8 usec
1527          */
1528         if (hw->mac.type >= e1000_pch_lpt) {
1529                 u32 mac_reg;
1530
1531                 mac_reg = er32(FEXTNVM4);
1532                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1533                 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1534                 ew32(FEXTNVM4, mac_reg);
1535         }
1536
1537         /* Work-around I218 hang issue */
1538         if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1539             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1540             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1541             (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1542                 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1543                 if (ret_val)
1544                         goto out;
1545         }
1546         if (hw->mac.type >= e1000_pch_lpt) {
1547                 /* Set platform power management values for
1548                  * Latency Tolerance Reporting (LTR)
1549                  */
1550                 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1551                 if (ret_val)
1552                         goto out;
1553         }
1554
1555         /* Clear link partner's EEE ability */
1556         hw->dev_spec.ich8lan.eee_lp_ability = 0;
1557
1558         if (hw->mac.type >= e1000_pch_lpt) {
1559                 u32 fextnvm6 = er32(FEXTNVM6);
1560
1561                 if (hw->mac.type == e1000_pch_spt) {
1562                         /* FEXTNVM6 K1-off workaround - for SPT only */
1563                         u32 pcieanacfg = er32(PCIEANACFG);
1564
1565                         if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1566                                 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1567                         else
1568                                 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1569                 }
1570
1571                 ew32(FEXTNVM6, fextnvm6);
1572         }
1573
1574         if (!link)
1575                 goto out;
1576
1577         switch (hw->mac.type) {
1578         case e1000_pch2lan:
1579                 ret_val = e1000_k1_workaround_lv(hw);
1580                 if (ret_val)
1581                         return ret_val;
1582                 /* fall-thru */
1583         case e1000_pchlan:
1584                 if (hw->phy.type == e1000_phy_82578) {
1585                         ret_val = e1000_link_stall_workaround_hv(hw);
1586                         if (ret_val)
1587                                 return ret_val;
1588                 }
1589
1590                 /* Workaround for PCHx parts in half-duplex:
1591                  * Set the number of preambles removed from the packet
1592                  * when it is passed from the PHY to the MAC to prevent
1593                  * the MAC from misinterpreting the packet type.
1594                  */
1595                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1596                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1597
1598                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1599                         phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1600
1601                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1602                 break;
1603         default:
1604                 break;
1605         }
1606
1607         /* Check if there was DownShift, must be checked
1608          * immediately after link-up
1609          */
1610         e1000e_check_downshift(hw);
1611
1612         /* Enable/Disable EEE after link up */
1613         if (hw->phy.type > e1000_phy_82579) {
1614                 ret_val = e1000_set_eee_pchlan(hw);
1615                 if (ret_val)
1616                         return ret_val;
1617         }
1618
1619         /* If we are forcing speed/duplex, then we simply return since
1620          * we have already determined whether we have link or not.
1621          */
1622         if (!mac->autoneg)
1623                 return 1;
1624
1625         /* Auto-Neg is enabled.  Auto Speed Detection takes care
1626          * of MAC speed/duplex configuration.  So we only need to
1627          * configure Collision Distance in the MAC.
1628          */
1629         mac->ops.config_collision_dist(hw);
1630
1631         /* Configure Flow Control now that Auto-Neg has completed.
1632          * First, we need to restore the desired flow control
1633          * settings because we may have had to re-autoneg with a
1634          * different link partner.
1635          */
1636         ret_val = e1000e_config_fc_after_link_up(hw);
1637         if (ret_val)
1638                 e_dbg("Error configuring flow control\n");
1639
1640         return ret_val;
1641
1642 out:
1643         mac->get_link_status = true;
1644         return ret_val;
1645 }
1646
1647 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1648 {
1649         struct e1000_hw *hw = &adapter->hw;
1650         s32 rc;
1651
1652         rc = e1000_init_mac_params_ich8lan(hw);
1653         if (rc)
1654                 return rc;
1655
1656         rc = e1000_init_nvm_params_ich8lan(hw);
1657         if (rc)
1658                 return rc;
1659
1660         switch (hw->mac.type) {
1661         case e1000_ich8lan:
1662         case e1000_ich9lan:
1663         case e1000_ich10lan:
1664                 rc = e1000_init_phy_params_ich8lan(hw);
1665                 break;
1666         case e1000_pchlan:
1667         case e1000_pch2lan:
1668         case e1000_pch_lpt:
1669         case e1000_pch_spt:
1670         case e1000_pch_cnp:
1671                 rc = e1000_init_phy_params_pchlan(hw);
1672                 break;
1673         default:
1674                 break;
1675         }
1676         if (rc)
1677                 return rc;
1678
1679         /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1680          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1681          */
1682         if ((adapter->hw.phy.type == e1000_phy_ife) ||
1683             ((adapter->hw.mac.type >= e1000_pch2lan) &&
1684              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1685                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1686                 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1687
1688                 hw->mac.ops.blink_led = NULL;
1689         }
1690
1691         if ((adapter->hw.mac.type == e1000_ich8lan) &&
1692             (adapter->hw.phy.type != e1000_phy_ife))
1693                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1694
1695         /* Enable workaround for 82579 w/ ME enabled */
1696         if ((adapter->hw.mac.type == e1000_pch2lan) &&
1697             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1698                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1699
1700         return 0;
1701 }
1702
1703 static DEFINE_MUTEX(nvm_mutex);
1704
1705 /**
1706  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1707  *  @hw: pointer to the HW structure
1708  *
1709  *  Acquires the mutex for performing NVM operations.
1710  **/
1711 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1712 {
1713         mutex_lock(&nvm_mutex);
1714
1715         return 0;
1716 }
1717
1718 /**
1719  *  e1000_release_nvm_ich8lan - Release NVM mutex
1720  *  @hw: pointer to the HW structure
1721  *
1722  *  Releases the mutex used while performing NVM operations.
1723  **/
1724 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1725 {
1726         mutex_unlock(&nvm_mutex);
1727 }
1728
1729 /**
1730  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
1731  *  @hw: pointer to the HW structure
1732  *
1733  *  Acquires the software control flag for performing PHY and select
1734  *  MAC CSR accesses.
1735  **/
1736 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1737 {
1738         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1739         s32 ret_val = 0;
1740
1741         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1742                              &hw->adapter->state)) {
1743                 e_dbg("contention for Phy access\n");
1744                 return -E1000_ERR_PHY;
1745         }
1746
1747         while (timeout) {
1748                 extcnf_ctrl = er32(EXTCNF_CTRL);
1749                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1750                         break;
1751
1752                 mdelay(1);
1753                 timeout--;
1754         }
1755
1756         if (!timeout) {
1757                 e_dbg("SW has already locked the resource.\n");
1758                 ret_val = -E1000_ERR_CONFIG;
1759                 goto out;
1760         }
1761
1762         timeout = SW_FLAG_TIMEOUT;
1763
1764         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1765         ew32(EXTCNF_CTRL, extcnf_ctrl);
1766
1767         while (timeout) {
1768                 extcnf_ctrl = er32(EXTCNF_CTRL);
1769                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1770                         break;
1771
1772                 mdelay(1);
1773                 timeout--;
1774         }
1775
1776         if (!timeout) {
1777                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1778                       er32(FWSM), extcnf_ctrl);
1779                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1780                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1781                 ret_val = -E1000_ERR_CONFIG;
1782                 goto out;
1783         }
1784
1785 out:
1786         if (ret_val)
1787                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1788
1789         return ret_val;
1790 }
1791
1792 /**
1793  *  e1000_release_swflag_ich8lan - Release software control flag
1794  *  @hw: pointer to the HW structure
1795  *
1796  *  Releases the software control flag for performing PHY and select
1797  *  MAC CSR accesses.
1798  **/
1799 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1800 {
1801         u32 extcnf_ctrl;
1802
1803         extcnf_ctrl = er32(EXTCNF_CTRL);
1804
1805         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1806                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1807                 ew32(EXTCNF_CTRL, extcnf_ctrl);
1808         } else {
1809                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1810         }
1811
1812         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1813 }
1814
1815 /**
1816  *  e1000_check_mng_mode_ich8lan - Checks management mode
1817  *  @hw: pointer to the HW structure
1818  *
1819  *  This checks if the adapter has any manageability enabled.
1820  *  This is a function pointer entry point only called by read/write
1821  *  routines for the PHY and NVM parts.
1822  **/
1823 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1824 {
1825         u32 fwsm;
1826
1827         fwsm = er32(FWSM);
1828         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1829                 ((fwsm & E1000_FWSM_MODE_MASK) ==
1830                  (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1831 }
1832
1833 /**
1834  *  e1000_check_mng_mode_pchlan - Checks management mode
1835  *  @hw: pointer to the HW structure
1836  *
1837  *  This checks if the adapter has iAMT enabled.
1838  *  This is a function pointer entry point only called by read/write
1839  *  routines for the PHY and NVM parts.
1840  **/
1841 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1842 {
1843         u32 fwsm;
1844
1845         fwsm = er32(FWSM);
1846         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1847             (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1848 }
1849
1850 /**
1851  *  e1000_rar_set_pch2lan - Set receive address register
1852  *  @hw: pointer to the HW structure
1853  *  @addr: pointer to the receive address
1854  *  @index: receive address array register
1855  *
1856  *  Sets the receive address array register at index to the address passed
1857  *  in by addr.  For 82579, RAR[0] is the base address register that is to
1858  *  contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1859  *  Use SHRA[0-3] in place of those reserved for ME.
1860  **/
1861 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1862 {
1863         u32 rar_low, rar_high;
1864
1865         /* HW expects these in little endian so we reverse the byte order
1866          * from network order (big endian) to little endian
1867          */
1868         rar_low = ((u32)addr[0] |
1869                    ((u32)addr[1] << 8) |
1870                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1871
1872         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1873
1874         /* If MAC address zero, no need to set the AV bit */
1875         if (rar_low || rar_high)
1876                 rar_high |= E1000_RAH_AV;
1877
1878         if (index == 0) {
1879                 ew32(RAL(index), rar_low);
1880                 e1e_flush();
1881                 ew32(RAH(index), rar_high);
1882                 e1e_flush();
1883                 return 0;
1884         }
1885
1886         /* RAR[1-6] are owned by manageability.  Skip those and program the
1887          * next address into the SHRA register array.
1888          */
1889         if (index < (u32)(hw->mac.rar_entry_count)) {
1890                 s32 ret_val;
1891
1892                 ret_val = e1000_acquire_swflag_ich8lan(hw);
1893                 if (ret_val)
1894                         goto out;
1895
1896                 ew32(SHRAL(index - 1), rar_low);
1897                 e1e_flush();
1898                 ew32(SHRAH(index - 1), rar_high);
1899                 e1e_flush();
1900
1901                 e1000_release_swflag_ich8lan(hw);
1902
1903                 /* verify the register updates */
1904                 if ((er32(SHRAL(index - 1)) == rar_low) &&
1905                     (er32(SHRAH(index - 1)) == rar_high))
1906                         return 0;
1907
1908                 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1909                       (index - 1), er32(FWSM));
1910         }
1911
1912 out:
1913         e_dbg("Failed to write receive address at index %d\n", index);
1914         return -E1000_ERR_CONFIG;
1915 }
1916
1917 /**
1918  *  e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1919  *  @hw: pointer to the HW structure
1920  *
1921  *  Get the number of available receive registers that the Host can
1922  *  program. SHRA[0-10] are the shared receive address registers
1923  *  that are shared between the Host and manageability engine (ME).
1924  *  ME can reserve any number of addresses and the host needs to be
1925  *  able to tell how many available registers it has access to.
1926  **/
1927 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1928 {
1929         u32 wlock_mac;
1930         u32 num_entries;
1931
1932         wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1933         wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1934
1935         switch (wlock_mac) {
1936         case 0:
1937                 /* All SHRA[0..10] and RAR[0] available */
1938                 num_entries = hw->mac.rar_entry_count;
1939                 break;
1940         case 1:
1941                 /* Only RAR[0] available */
1942                 num_entries = 1;
1943                 break;
1944         default:
1945                 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1946                 num_entries = wlock_mac + 1;
1947                 break;
1948         }
1949
1950         return num_entries;
1951 }
1952
1953 /**
1954  *  e1000_rar_set_pch_lpt - Set receive address registers
1955  *  @hw: pointer to the HW structure
1956  *  @addr: pointer to the receive address
1957  *  @index: receive address array register
1958  *
1959  *  Sets the receive address register array at index to the address passed
1960  *  in by addr. For LPT, RAR[0] is the base address register that is to
1961  *  contain the MAC address. SHRA[0-10] are the shared receive address
1962  *  registers that are shared between the Host and manageability engine (ME).
1963  **/
1964 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1965 {
1966         u32 rar_low, rar_high;
1967         u32 wlock_mac;
1968
1969         /* HW expects these in little endian so we reverse the byte order
1970          * from network order (big endian) to little endian
1971          */
1972         rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1973                    ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1974
1975         rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1976
1977         /* If MAC address zero, no need to set the AV bit */
1978         if (rar_low || rar_high)
1979                 rar_high |= E1000_RAH_AV;
1980
1981         if (index == 0) {
1982                 ew32(RAL(index), rar_low);
1983                 e1e_flush();
1984                 ew32(RAH(index), rar_high);
1985                 e1e_flush();
1986                 return 0;
1987         }
1988
1989         /* The manageability engine (ME) can lock certain SHRAR registers that
1990          * it is using - those registers are unavailable for use.
1991          */
1992         if (index < hw->mac.rar_entry_count) {
1993                 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1994                 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1995
1996                 /* Check if all SHRAR registers are locked */
1997                 if (wlock_mac == 1)
1998                         goto out;
1999
2000                 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2001                         s32 ret_val;
2002
2003                         ret_val = e1000_acquire_swflag_ich8lan(hw);
2004
2005                         if (ret_val)
2006                                 goto out;
2007
2008                         ew32(SHRAL_PCH_LPT(index - 1), rar_low);
2009                         e1e_flush();
2010                         ew32(SHRAH_PCH_LPT(index - 1), rar_high);
2011                         e1e_flush();
2012
2013                         e1000_release_swflag_ich8lan(hw);
2014
2015                         /* verify the register updates */
2016                         if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2017                             (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
2018                                 return 0;
2019                 }
2020         }
2021
2022 out:
2023         e_dbg("Failed to write receive address at index %d\n", index);
2024         return -E1000_ERR_CONFIG;
2025 }
2026
2027 /**
2028  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2029  *  @hw: pointer to the HW structure
2030  *
2031  *  Checks if firmware is blocking the reset of the PHY.
2032  *  This is a function pointer entry point only called by
2033  *  reset routines.
2034  **/
2035 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2036 {
2037         bool blocked = false;
2038         int i = 0;
2039
2040         while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2041                (i++ < 30))
2042                 usleep_range(10000, 20000);
2043         return blocked ? E1000_BLK_PHY_RESET : 0;
2044 }
2045
2046 /**
2047  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2048  *  @hw: pointer to the HW structure
2049  *
2050  *  Assumes semaphore already acquired.
2051  *
2052  **/
2053 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2054 {
2055         u16 phy_data;
2056         u32 strap = er32(STRAP);
2057         u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2058             E1000_STRAP_SMT_FREQ_SHIFT;
2059         s32 ret_val;
2060
2061         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2062
2063         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2064         if (ret_val)
2065                 return ret_val;
2066
2067         phy_data &= ~HV_SMB_ADDR_MASK;
2068         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2069         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2070
2071         if (hw->phy.type == e1000_phy_i217) {
2072                 /* Restore SMBus frequency */
2073                 if (freq--) {
2074                         phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2075                         phy_data |= (freq & BIT(0)) <<
2076                             HV_SMB_ADDR_FREQ_LOW_SHIFT;
2077                         phy_data |= (freq & BIT(1)) <<
2078                             (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2079                 } else {
2080                         e_dbg("Unsupported SMB frequency in PHY\n");
2081                 }
2082         }
2083
2084         return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2085 }
2086
2087 /**
2088  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2089  *  @hw:   pointer to the HW structure
2090  *
2091  *  SW should configure the LCD from the NVM extended configuration region
2092  *  as a workaround for certain parts.
2093  **/
2094 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2095 {
2096         struct e1000_phy_info *phy = &hw->phy;
2097         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2098         s32 ret_val = 0;
2099         u16 word_addr, reg_data, reg_addr, phy_page = 0;
2100
2101         /* Initialize the PHY from the NVM on ICH platforms.  This
2102          * is needed due to an issue where the NVM configuration is
2103          * not properly autoloaded after power transitions.
2104          * Therefore, after each PHY reset, we will load the
2105          * configuration data out of the NVM manually.
2106          */
2107         switch (hw->mac.type) {
2108         case e1000_ich8lan:
2109                 if (phy->type != e1000_phy_igp_3)
2110                         return ret_val;
2111
2112                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2113                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2114                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2115                         break;
2116                 }
2117                 /* Fall-thru */
2118         case e1000_pchlan:
2119         case e1000_pch2lan:
2120         case e1000_pch_lpt:
2121         case e1000_pch_spt:
2122         case e1000_pch_cnp:
2123                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2124                 break;
2125         default:
2126                 return ret_val;
2127         }
2128
2129         ret_val = hw->phy.ops.acquire(hw);
2130         if (ret_val)
2131                 return ret_val;
2132
2133         data = er32(FEXTNVM);
2134         if (!(data & sw_cfg_mask))
2135                 goto release;
2136
2137         /* Make sure HW does not configure LCD from PHY
2138          * extended configuration before SW configuration
2139          */
2140         data = er32(EXTCNF_CTRL);
2141         if ((hw->mac.type < e1000_pch2lan) &&
2142             (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2143                 goto release;
2144
2145         cnf_size = er32(EXTCNF_SIZE);
2146         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2147         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2148         if (!cnf_size)
2149                 goto release;
2150
2151         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2152         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2153
2154         if (((hw->mac.type == e1000_pchlan) &&
2155              !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2156             (hw->mac.type > e1000_pchlan)) {
2157                 /* HW configures the SMBus address and LEDs when the
2158                  * OEM and LCD Write Enable bits are set in the NVM.
2159                  * When both NVM bits are cleared, SW will configure
2160                  * them instead.
2161                  */
2162                 ret_val = e1000_write_smbus_addr(hw);
2163                 if (ret_val)
2164                         goto release;
2165
2166                 data = er32(LEDCTL);
2167                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2168                                                         (u16)data);
2169                 if (ret_val)
2170                         goto release;
2171         }
2172
2173         /* Configure LCD from extended configuration region. */
2174
2175         /* cnf_base_addr is in DWORD */
2176         word_addr = (u16)(cnf_base_addr << 1);
2177
2178         for (i = 0; i < cnf_size; i++) {
2179                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
2180                 if (ret_val)
2181                         goto release;
2182
2183                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2184                                          1, &reg_addr);
2185                 if (ret_val)
2186                         goto release;
2187
2188                 /* Save off the PHY page for future writes. */
2189                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2190                         phy_page = reg_data;
2191                         continue;
2192                 }
2193
2194                 reg_addr &= PHY_REG_MASK;
2195                 reg_addr |= phy_page;
2196
2197                 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2198                 if (ret_val)
2199                         goto release;
2200         }
2201
2202 release:
2203         hw->phy.ops.release(hw);
2204         return ret_val;
2205 }
2206
2207 /**
2208  *  e1000_k1_gig_workaround_hv - K1 Si workaround
2209  *  @hw:   pointer to the HW structure
2210  *  @link: link up bool flag
2211  *
2212  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2213  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
2214  *  If link is down, the function will restore the default K1 setting located
2215  *  in the NVM.
2216  **/
2217 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2218 {
2219         s32 ret_val = 0;
2220         u16 status_reg = 0;
2221         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2222
2223         if (hw->mac.type != e1000_pchlan)
2224                 return 0;
2225
2226         /* Wrap the whole flow with the sw flag */
2227         ret_val = hw->phy.ops.acquire(hw);
2228         if (ret_val)
2229                 return ret_val;
2230
2231         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2232         if (link) {
2233                 if (hw->phy.type == e1000_phy_82578) {
2234                         ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2235                                                   &status_reg);
2236                         if (ret_val)
2237                                 goto release;
2238
2239                         status_reg &= (BM_CS_STATUS_LINK_UP |
2240                                        BM_CS_STATUS_RESOLVED |
2241                                        BM_CS_STATUS_SPEED_MASK);
2242
2243                         if (status_reg == (BM_CS_STATUS_LINK_UP |
2244                                            BM_CS_STATUS_RESOLVED |
2245                                            BM_CS_STATUS_SPEED_1000))
2246                                 k1_enable = false;
2247                 }
2248
2249                 if (hw->phy.type == e1000_phy_82577) {
2250                         ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2251                         if (ret_val)
2252                                 goto release;
2253
2254                         status_reg &= (HV_M_STATUS_LINK_UP |
2255                                        HV_M_STATUS_AUTONEG_COMPLETE |
2256                                        HV_M_STATUS_SPEED_MASK);
2257
2258                         if (status_reg == (HV_M_STATUS_LINK_UP |
2259                                            HV_M_STATUS_AUTONEG_COMPLETE |
2260                                            HV_M_STATUS_SPEED_1000))
2261                                 k1_enable = false;
2262                 }
2263
2264                 /* Link stall fix for link up */
2265                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2266                 if (ret_val)
2267                         goto release;
2268
2269         } else {
2270                 /* Link stall fix for link down */
2271                 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2272                 if (ret_val)
2273                         goto release;
2274         }
2275
2276         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2277
2278 release:
2279         hw->phy.ops.release(hw);
2280
2281         return ret_val;
2282 }
2283
2284 /**
2285  *  e1000_configure_k1_ich8lan - Configure K1 power state
2286  *  @hw: pointer to the HW structure
2287  *  @enable: K1 state to configure
2288  *
2289  *  Configure the K1 power state based on the provided parameter.
2290  *  Assumes semaphore already acquired.
2291  *
2292  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2293  **/
2294 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2295 {
2296         s32 ret_val;
2297         u32 ctrl_reg = 0;
2298         u32 ctrl_ext = 0;
2299         u32 reg = 0;
2300         u16 kmrn_reg = 0;
2301
2302         ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2303                                               &kmrn_reg);
2304         if (ret_val)
2305                 return ret_val;
2306
2307         if (k1_enable)
2308                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2309         else
2310                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2311
2312         ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2313                                                kmrn_reg);
2314         if (ret_val)
2315                 return ret_val;
2316
2317         usleep_range(20, 40);
2318         ctrl_ext = er32(CTRL_EXT);
2319         ctrl_reg = er32(CTRL);
2320
2321         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2322         reg |= E1000_CTRL_FRCSPD;
2323         ew32(CTRL, reg);
2324
2325         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2326         e1e_flush();
2327         usleep_range(20, 40);
2328         ew32(CTRL, ctrl_reg);
2329         ew32(CTRL_EXT, ctrl_ext);
2330         e1e_flush();
2331         usleep_range(20, 40);
2332
2333         return 0;
2334 }
2335
2336 /**
2337  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2338  *  @hw:       pointer to the HW structure
2339  *  @d0_state: boolean if entering d0 or d3 device state
2340  *
2341  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2342  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
2343  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
2344  **/
2345 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2346 {
2347         s32 ret_val = 0;
2348         u32 mac_reg;
2349         u16 oem_reg;
2350
2351         if (hw->mac.type < e1000_pchlan)
2352                 return ret_val;
2353
2354         ret_val = hw->phy.ops.acquire(hw);
2355         if (ret_val)
2356                 return ret_val;
2357
2358         if (hw->mac.type == e1000_pchlan) {
2359                 mac_reg = er32(EXTCNF_CTRL);
2360                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2361                         goto release;
2362         }
2363
2364         mac_reg = er32(FEXTNVM);
2365         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2366                 goto release;
2367
2368         mac_reg = er32(PHY_CTRL);
2369
2370         ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2371         if (ret_val)
2372                 goto release;
2373
2374         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2375
2376         if (d0_state) {
2377                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2378                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2379
2380                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2381                         oem_reg |= HV_OEM_BITS_LPLU;
2382         } else {
2383                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2384                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2385                         oem_reg |= HV_OEM_BITS_GBE_DIS;
2386
2387                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2388                                E1000_PHY_CTRL_NOND0A_LPLU))
2389                         oem_reg |= HV_OEM_BITS_LPLU;
2390         }
2391
2392         /* Set Restart auto-neg to activate the bits */
2393         if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2394             !hw->phy.ops.check_reset_block(hw))
2395                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2396
2397         ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2398
2399 release:
2400         hw->phy.ops.release(hw);
2401
2402         return ret_val;
2403 }
2404
2405 /**
2406  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2407  *  @hw:   pointer to the HW structure
2408  **/
2409 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2410 {
2411         s32 ret_val;
2412         u16 data;
2413
2414         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2415         if (ret_val)
2416                 return ret_val;
2417
2418         data |= HV_KMRN_MDIO_SLOW;
2419
2420         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2421
2422         return ret_val;
2423 }
2424
2425 /**
2426  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2427  *  done after every PHY reset.
2428  **/
2429 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2430 {
2431         s32 ret_val = 0;
2432         u16 phy_data;
2433
2434         if (hw->mac.type != e1000_pchlan)
2435                 return 0;
2436
2437         /* Set MDIO slow mode before any other MDIO access */
2438         if (hw->phy.type == e1000_phy_82577) {
2439                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2440                 if (ret_val)
2441                         return ret_val;
2442         }
2443
2444         if (((hw->phy.type == e1000_phy_82577) &&
2445              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2446             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2447                 /* Disable generation of early preamble */
2448                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2449                 if (ret_val)
2450                         return ret_val;
2451
2452                 /* Preamble tuning for SSC */
2453                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2454                 if (ret_val)
2455                         return ret_val;
2456         }
2457
2458         if (hw->phy.type == e1000_phy_82578) {
2459                 /* Return registers to default by doing a soft reset then
2460                  * writing 0x3140 to the control register.
2461                  */
2462                 if (hw->phy.revision < 2) {
2463                         e1000e_phy_sw_reset(hw);
2464                         ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2465                         if (ret_val)
2466                                 return ret_val;
2467                 }
2468         }
2469
2470         /* Select page 0 */
2471         ret_val = hw->phy.ops.acquire(hw);
2472         if (ret_val)
2473                 return ret_val;
2474
2475         hw->phy.addr = 1;
2476         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2477         hw->phy.ops.release(hw);
2478         if (ret_val)
2479                 return ret_val;
2480
2481         /* Configure the K1 Si workaround during phy reset assuming there is
2482          * link so that it disables K1 if link is in 1Gbps.
2483          */
2484         ret_val = e1000_k1_gig_workaround_hv(hw, true);
2485         if (ret_val)
2486                 return ret_val;
2487
2488         /* Workaround for link disconnects on a busy hub in half duplex */
2489         ret_val = hw->phy.ops.acquire(hw);
2490         if (ret_val)
2491                 return ret_val;
2492         ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2493         if (ret_val)
2494                 goto release;
2495         ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2496         if (ret_val)
2497                 goto release;
2498
2499         /* set MSE higher to enable link to stay up when noise is high */
2500         ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2501 release:
2502         hw->phy.ops.release(hw);
2503
2504         return ret_val;
2505 }
2506
2507 /**
2508  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2509  *  @hw:   pointer to the HW structure
2510  **/
2511 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2512 {
2513         u32 mac_reg;
2514         u16 i, phy_reg = 0;
2515         s32 ret_val;
2516
2517         ret_val = hw->phy.ops.acquire(hw);
2518         if (ret_val)
2519                 return;
2520         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2521         if (ret_val)
2522                 goto release;
2523
2524         /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2525         for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2526                 mac_reg = er32(RAL(i));
2527                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2528                                            (u16)(mac_reg & 0xFFFF));
2529                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2530                                            (u16)((mac_reg >> 16) & 0xFFFF));
2531
2532                 mac_reg = er32(RAH(i));
2533                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2534                                            (u16)(mac_reg & 0xFFFF));
2535                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2536                                            (u16)((mac_reg & E1000_RAH_AV)
2537                                                  >> 16));
2538         }
2539
2540         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2541
2542 release:
2543         hw->phy.ops.release(hw);
2544 }
2545
2546 /**
2547  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2548  *  with 82579 PHY
2549  *  @hw: pointer to the HW structure
2550  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
2551  **/
2552 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2553 {
2554         s32 ret_val = 0;
2555         u16 phy_reg, data;
2556         u32 mac_reg;
2557         u16 i;
2558
2559         if (hw->mac.type < e1000_pch2lan)
2560                 return 0;
2561
2562         /* disable Rx path while enabling/disabling workaround */
2563         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2564         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2565         if (ret_val)
2566                 return ret_val;
2567
2568         if (enable) {
2569                 /* Write Rx addresses (rar_entry_count for RAL/H, and
2570                  * SHRAL/H) and initial CRC values to the MAC
2571                  */
2572                 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2573                         u8 mac_addr[ETH_ALEN] = { 0 };
2574                         u32 addr_high, addr_low;
2575
2576                         addr_high = er32(RAH(i));
2577                         if (!(addr_high & E1000_RAH_AV))
2578                                 continue;
2579                         addr_low = er32(RAL(i));
2580                         mac_addr[0] = (addr_low & 0xFF);
2581                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
2582                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
2583                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
2584                         mac_addr[4] = (addr_high & 0xFF);
2585                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
2586
2587                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2588                 }
2589
2590                 /* Write Rx addresses to the PHY */
2591                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2592
2593                 /* Enable jumbo frame workaround in the MAC */
2594                 mac_reg = er32(FFLT_DBG);
2595                 mac_reg &= ~BIT(14);
2596                 mac_reg |= (7 << 15);
2597                 ew32(FFLT_DBG, mac_reg);
2598
2599                 mac_reg = er32(RCTL);
2600                 mac_reg |= E1000_RCTL_SECRC;
2601                 ew32(RCTL, mac_reg);
2602
2603                 ret_val = e1000e_read_kmrn_reg(hw,
2604                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2605                                                &data);
2606                 if (ret_val)
2607                         return ret_val;
2608                 ret_val = e1000e_write_kmrn_reg(hw,
2609                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2610                                                 data | BIT(0));
2611                 if (ret_val)
2612                         return ret_val;
2613                 ret_val = e1000e_read_kmrn_reg(hw,
2614                                                E1000_KMRNCTRLSTA_HD_CTRL,
2615                                                &data);
2616                 if (ret_val)
2617                         return ret_val;
2618                 data &= ~(0xF << 8);
2619                 data |= (0xB << 8);
2620                 ret_val = e1000e_write_kmrn_reg(hw,
2621                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2622                                                 data);
2623                 if (ret_val)
2624                         return ret_val;
2625
2626                 /* Enable jumbo frame workaround in the PHY */
2627                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2628                 data &= ~(0x7F << 5);
2629                 data |= (0x37 << 5);
2630                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2631                 if (ret_val)
2632                         return ret_val;
2633                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2634                 data &= ~BIT(13);
2635                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2636                 if (ret_val)
2637                         return ret_val;
2638                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2639                 data &= ~(0x3FF << 2);
2640                 data |= (E1000_TX_PTR_GAP << 2);
2641                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2642                 if (ret_val)
2643                         return ret_val;
2644                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2645                 if (ret_val)
2646                         return ret_val;
2647                 e1e_rphy(hw, HV_PM_CTRL, &data);
2648                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2649                 if (ret_val)
2650                         return ret_val;
2651         } else {
2652                 /* Write MAC register values back to h/w defaults */
2653                 mac_reg = er32(FFLT_DBG);
2654                 mac_reg &= ~(0xF << 14);
2655                 ew32(FFLT_DBG, mac_reg);
2656
2657                 mac_reg = er32(RCTL);
2658                 mac_reg &= ~E1000_RCTL_SECRC;
2659                 ew32(RCTL, mac_reg);
2660
2661                 ret_val = e1000e_read_kmrn_reg(hw,
2662                                                E1000_KMRNCTRLSTA_CTRL_OFFSET,
2663                                                &data);
2664                 if (ret_val)
2665                         return ret_val;
2666                 ret_val = e1000e_write_kmrn_reg(hw,
2667                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2668                                                 data & ~BIT(0));
2669                 if (ret_val)
2670                         return ret_val;
2671                 ret_val = e1000e_read_kmrn_reg(hw,
2672                                                E1000_KMRNCTRLSTA_HD_CTRL,
2673                                                &data);
2674                 if (ret_val)
2675                         return ret_val;
2676                 data &= ~(0xF << 8);
2677                 data |= (0xB << 8);
2678                 ret_val = e1000e_write_kmrn_reg(hw,
2679                                                 E1000_KMRNCTRLSTA_HD_CTRL,
2680                                                 data);
2681                 if (ret_val)
2682                         return ret_val;
2683
2684                 /* Write PHY register values back to h/w defaults */
2685                 e1e_rphy(hw, PHY_REG(769, 23), &data);
2686                 data &= ~(0x7F << 5);
2687                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2688                 if (ret_val)
2689                         return ret_val;
2690                 e1e_rphy(hw, PHY_REG(769, 16), &data);
2691                 data |= BIT(13);
2692                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2693                 if (ret_val)
2694                         return ret_val;
2695                 e1e_rphy(hw, PHY_REG(776, 20), &data);
2696                 data &= ~(0x3FF << 2);
2697                 data |= (0x8 << 2);
2698                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2699                 if (ret_val)
2700                         return ret_val;
2701                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2702                 if (ret_val)
2703                         return ret_val;
2704                 e1e_rphy(hw, HV_PM_CTRL, &data);
2705                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2706                 if (ret_val)
2707                         return ret_val;
2708         }
2709
2710         /* re-enable Rx path after enabling/disabling workaround */
2711         return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2712 }
2713
2714 /**
2715  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2716  *  done after every PHY reset.
2717  **/
2718 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2719 {
2720         s32 ret_val = 0;
2721
2722         if (hw->mac.type != e1000_pch2lan)
2723                 return 0;
2724
2725         /* Set MDIO slow mode before any other MDIO access */
2726         ret_val = e1000_set_mdio_slow_mode_hv(hw);
2727         if (ret_val)
2728                 return ret_val;
2729
2730         ret_val = hw->phy.ops.acquire(hw);
2731         if (ret_val)
2732                 return ret_val;
2733         /* set MSE higher to enable link to stay up when noise is high */
2734         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2735         if (ret_val)
2736                 goto release;
2737         /* drop link after 5 times MSE threshold was reached */
2738         ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2739 release:
2740         hw->phy.ops.release(hw);
2741
2742         return ret_val;
2743 }
2744
2745 /**
2746  *  e1000_k1_gig_workaround_lv - K1 Si workaround
2747  *  @hw:   pointer to the HW structure
2748  *
2749  *  Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2750  *  Disable K1 in 1000Mbps and 100Mbps
2751  **/
2752 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2753 {
2754         s32 ret_val = 0;
2755         u16 status_reg = 0;
2756
2757         if (hw->mac.type != e1000_pch2lan)
2758                 return 0;
2759
2760         /* Set K1 beacon duration based on 10Mbs speed */
2761         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2762         if (ret_val)
2763                 return ret_val;
2764
2765         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2766             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2767                 if (status_reg &
2768                     (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2769                         u16 pm_phy_reg;
2770
2771                         /* LV 1G/100 Packet drop issue wa  */
2772                         ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2773                         if (ret_val)
2774                                 return ret_val;
2775                         pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2776                         ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2777                         if (ret_val)
2778                                 return ret_val;
2779                 } else {
2780                         u32 mac_reg;
2781
2782                         mac_reg = er32(FEXTNVM4);
2783                         mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2784                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2785                         ew32(FEXTNVM4, mac_reg);
2786                 }
2787         }
2788
2789         return ret_val;
2790 }
2791
2792 /**
2793  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2794  *  @hw:   pointer to the HW structure
2795  *  @gate: boolean set to true to gate, false to ungate
2796  *
2797  *  Gate/ungate the automatic PHY configuration via hardware; perform
2798  *  the configuration via software instead.
2799  **/
2800 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2801 {
2802         u32 extcnf_ctrl;
2803
2804         if (hw->mac.type < e1000_pch2lan)
2805                 return;
2806
2807         extcnf_ctrl = er32(EXTCNF_CTRL);
2808
2809         if (gate)
2810                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2811         else
2812                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2813
2814         ew32(EXTCNF_CTRL, extcnf_ctrl);
2815 }
2816
2817 /**
2818  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
2819  *  @hw: pointer to the HW structure
2820  *
2821  *  Check the appropriate indication the MAC has finished configuring the
2822  *  PHY after a software reset.
2823  **/
2824 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2825 {
2826         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2827
2828         /* Wait for basic configuration completes before proceeding */
2829         do {
2830                 data = er32(STATUS);
2831                 data &= E1000_STATUS_LAN_INIT_DONE;
2832                 usleep_range(100, 200);
2833         } while ((!data) && --loop);
2834
2835         /* If basic configuration is incomplete before the above loop
2836          * count reaches 0, loading the configuration from NVM will
2837          * leave the PHY in a bad state possibly resulting in no link.
2838          */
2839         if (loop == 0)
2840                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2841
2842         /* Clear the Init Done bit for the next init event */
2843         data = er32(STATUS);
2844         data &= ~E1000_STATUS_LAN_INIT_DONE;
2845         ew32(STATUS, data);
2846 }
2847
2848 /**
2849  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2850  *  @hw: pointer to the HW structure
2851  **/
2852 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2853 {
2854         s32 ret_val = 0;
2855         u16 reg;
2856
2857         if (hw->phy.ops.check_reset_block(hw))
2858                 return 0;
2859
2860         /* Allow time for h/w to get to quiescent state after reset */
2861         usleep_range(10000, 20000);
2862
2863         /* Perform any necessary post-reset workarounds */
2864         switch (hw->mac.type) {
2865         case e1000_pchlan:
2866                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2867                 if (ret_val)
2868                         return ret_val;
2869                 break;
2870         case e1000_pch2lan:
2871                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2872                 if (ret_val)
2873                         return ret_val;
2874                 break;
2875         default:
2876                 break;
2877         }
2878
2879         /* Clear the host wakeup bit after lcd reset */
2880         if (hw->mac.type >= e1000_pchlan) {
2881                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2882                 reg &= ~BM_WUC_HOST_WU_BIT;
2883                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2884         }
2885
2886         /* Configure the LCD with the extended configuration region in NVM */
2887         ret_val = e1000_sw_lcd_config_ich8lan(hw);
2888         if (ret_val)
2889                 return ret_val;
2890
2891         /* Configure the LCD with the OEM bits in NVM */
2892         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2893
2894         if (hw->mac.type == e1000_pch2lan) {
2895                 /* Ungate automatic PHY configuration on non-managed 82579 */
2896                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2897                         usleep_range(10000, 20000);
2898                         e1000_gate_hw_phy_config_ich8lan(hw, false);
2899                 }
2900
2901                 /* Set EEE LPI Update Timer to 200usec */
2902                 ret_val = hw->phy.ops.acquire(hw);
2903                 if (ret_val)
2904                         return ret_val;
2905                 ret_val = e1000_write_emi_reg_locked(hw,
2906                                                      I82579_LPI_UPDATE_TIMER,
2907                                                      0x1387);
2908                 hw->phy.ops.release(hw);
2909         }
2910
2911         return ret_val;
2912 }
2913
2914 /**
2915  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2916  *  @hw: pointer to the HW structure
2917  *
2918  *  Resets the PHY
2919  *  This is a function pointer entry point called by drivers
2920  *  or other shared routines.
2921  **/
2922 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2923 {
2924         s32 ret_val = 0;
2925
2926         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2927         if ((hw->mac.type == e1000_pch2lan) &&
2928             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2929                 e1000_gate_hw_phy_config_ich8lan(hw, true);
2930
2931         ret_val = e1000e_phy_hw_reset_generic(hw);
2932         if (ret_val)
2933                 return ret_val;
2934
2935         return e1000_post_phy_reset_ich8lan(hw);
2936 }
2937
2938 /**
2939  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2940  *  @hw: pointer to the HW structure
2941  *  @active: true to enable LPLU, false to disable
2942  *
2943  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
2944  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2945  *  the phy speed. This function will manually set the LPLU bit and restart
2946  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
2947  *  since it configures the same bit.
2948  **/
2949 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2950 {
2951         s32 ret_val;
2952         u16 oem_reg;
2953
2954         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2955         if (ret_val)
2956                 return ret_val;
2957
2958         if (active)
2959                 oem_reg |= HV_OEM_BITS_LPLU;
2960         else
2961                 oem_reg &= ~HV_OEM_BITS_LPLU;
2962
2963         if (!hw->phy.ops.check_reset_block(hw))
2964                 oem_reg |= HV_OEM_BITS_RESTART_AN;
2965
2966         return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2967 }
2968
2969 /**
2970  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2971  *  @hw: pointer to the HW structure
2972  *  @active: true to enable LPLU, false to disable
2973  *
2974  *  Sets the LPLU D0 state according to the active flag.  When
2975  *  activating LPLU this function also disables smart speed
2976  *  and vice versa.  LPLU will not be activated unless the
2977  *  device autonegotiation advertisement meets standards of
2978  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2979  *  This is a function pointer entry point only called by
2980  *  PHY setup routines.
2981  **/
2982 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2983 {
2984         struct e1000_phy_info *phy = &hw->phy;
2985         u32 phy_ctrl;
2986         s32 ret_val = 0;
2987         u16 data;
2988
2989         if (phy->type == e1000_phy_ife)
2990                 return 0;
2991
2992         phy_ctrl = er32(PHY_CTRL);
2993
2994         if (active) {
2995                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2996                 ew32(PHY_CTRL, phy_ctrl);
2997
2998                 if (phy->type != e1000_phy_igp_3)
2999                         return 0;
3000
3001                 /* Call gig speed drop workaround on LPLU before accessing
3002                  * any PHY registers
3003                  */
3004                 if (hw->mac.type == e1000_ich8lan)
3005                         e1000e_gig_downshift_workaround_ich8lan(hw);
3006
3007                 /* When LPLU is enabled, we should disable SmartSpeed */
3008                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3009                 if (ret_val)
3010                         return ret_val;
3011                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3012                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3013                 if (ret_val)
3014                         return ret_val;
3015         } else {
3016                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3017                 ew32(PHY_CTRL, phy_ctrl);
3018
3019                 if (phy->type != e1000_phy_igp_3)
3020                         return 0;
3021
3022                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3023                  * during Dx states where the power conservation is most
3024                  * important.  During driver activity we should enable
3025                  * SmartSpeed, so performance is maintained.
3026                  */
3027                 if (phy->smart_speed == e1000_smart_speed_on) {
3028                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3029                                            &data);
3030                         if (ret_val)
3031                                 return ret_val;
3032
3033                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3034                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3035                                            data);
3036                         if (ret_val)
3037                                 return ret_val;
3038                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3039                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3040                                            &data);
3041                         if (ret_val)
3042                                 return ret_val;
3043
3044                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3045                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3046                                            data);
3047                         if (ret_val)
3048                                 return ret_val;
3049                 }
3050         }
3051
3052         return 0;
3053 }
3054
3055 /**
3056  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3057  *  @hw: pointer to the HW structure
3058  *  @active: true to enable LPLU, false to disable
3059  *
3060  *  Sets the LPLU D3 state according to the active flag.  When
3061  *  activating LPLU this function also disables smart speed
3062  *  and vice versa.  LPLU will not be activated unless the
3063  *  device autonegotiation advertisement meets standards of
3064  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
3065  *  This is a function pointer entry point only called by
3066  *  PHY setup routines.
3067  **/
3068 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3069 {
3070         struct e1000_phy_info *phy = &hw->phy;
3071         u32 phy_ctrl;
3072         s32 ret_val = 0;
3073         u16 data;
3074
3075         phy_ctrl = er32(PHY_CTRL);
3076
3077         if (!active) {
3078                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3079                 ew32(PHY_CTRL, phy_ctrl);
3080
3081                 if (phy->type != e1000_phy_igp_3)
3082                         return 0;
3083
3084                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
3085                  * during Dx states where the power conservation is most
3086                  * important.  During driver activity we should enable
3087                  * SmartSpeed, so performance is maintained.
3088                  */
3089                 if (phy->smart_speed == e1000_smart_speed_on) {
3090                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3091                                            &data);
3092                         if (ret_val)
3093                                 return ret_val;
3094
3095                         data |= IGP01E1000_PSCFR_SMART_SPEED;
3096                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3097                                            data);
3098                         if (ret_val)
3099                                 return ret_val;
3100                 } else if (phy->smart_speed == e1000_smart_speed_off) {
3101                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3102                                            &data);
3103                         if (ret_val)
3104                                 return ret_val;
3105
3106                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3107                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3108                                            data);
3109                         if (ret_val)
3110                                 return ret_val;
3111                 }
3112         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3113                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3114                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3115                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3116                 ew32(PHY_CTRL, phy_ctrl);
3117
3118                 if (phy->type != e1000_phy_igp_3)
3119                         return 0;
3120
3121                 /* Call gig speed drop workaround on LPLU before accessing
3122                  * any PHY registers
3123                  */
3124                 if (hw->mac.type == e1000_ich8lan)
3125                         e1000e_gig_downshift_workaround_ich8lan(hw);
3126
3127                 /* When LPLU is enabled, we should disable SmartSpeed */
3128                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3129                 if (ret_val)
3130                         return ret_val;
3131
3132                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3133                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3134         }
3135
3136         return ret_val;
3137 }
3138
3139 /**
3140  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3141  *  @hw: pointer to the HW structure
3142  *  @bank:  pointer to the variable that returns the active bank
3143  *
3144  *  Reads signature byte from the NVM using the flash access registers.
3145  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3146  **/
3147 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3148 {
3149         u32 eecd;
3150         struct e1000_nvm_info *nvm = &hw->nvm;
3151         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3152         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3153         u32 nvm_dword = 0;
3154         u8 sig_byte = 0;
3155         s32 ret_val;
3156
3157         switch (hw->mac.type) {
3158         case e1000_pch_spt:
3159         case e1000_pch_cnp:
3160                 bank1_offset = nvm->flash_bank_size;
3161                 act_offset = E1000_ICH_NVM_SIG_WORD;
3162
3163                 /* set bank to 0 in case flash read fails */
3164                 *bank = 0;
3165
3166                 /* Check bank 0 */
3167                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3168                                                          &nvm_dword);
3169                 if (ret_val)
3170                         return ret_val;
3171                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3172                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3173                     E1000_ICH_NVM_SIG_VALUE) {
3174                         *bank = 0;
3175                         return 0;
3176                 }
3177
3178                 /* Check bank 1 */
3179                 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3180                                                          bank1_offset,
3181                                                          &nvm_dword);
3182                 if (ret_val)
3183                         return ret_val;
3184                 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3185                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3186                     E1000_ICH_NVM_SIG_VALUE) {
3187                         *bank = 1;
3188                         return 0;
3189                 }
3190
3191                 e_dbg("ERROR: No valid NVM bank present\n");
3192                 return -E1000_ERR_NVM;
3193         case e1000_ich8lan:
3194         case e1000_ich9lan:
3195                 eecd = er32(EECD);
3196                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3197                     E1000_EECD_SEC1VAL_VALID_MASK) {
3198                         if (eecd & E1000_EECD_SEC1VAL)
3199                                 *bank = 1;
3200                         else
3201                                 *bank = 0;
3202
3203                         return 0;
3204                 }
3205                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3206                 /* fall-thru */
3207         default:
3208                 /* set bank to 0 in case flash read fails */
3209                 *bank = 0;
3210
3211                 /* Check bank 0 */
3212                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3213                                                         &sig_byte);
3214                 if (ret_val)
3215                         return ret_val;
3216                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3217                     E1000_ICH_NVM_SIG_VALUE) {
3218                         *bank = 0;
3219                         return 0;
3220                 }
3221
3222                 /* Check bank 1 */
3223                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3224                                                         bank1_offset,
3225                                                         &sig_byte);
3226                 if (ret_val)
3227                         return ret_val;
3228                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3229                     E1000_ICH_NVM_SIG_VALUE) {
3230                         *bank = 1;
3231                         return 0;
3232                 }
3233
3234                 e_dbg("ERROR: No valid NVM bank present\n");
3235                 return -E1000_ERR_NVM;
3236         }
3237 }
3238
3239 /**
3240  *  e1000_read_nvm_spt - NVM access for SPT
3241  *  @hw: pointer to the HW structure
3242  *  @offset: The offset (in bytes) of the word(s) to read.
3243  *  @words: Size of data to read in words.
3244  *  @data: pointer to the word(s) to read at offset.
3245  *
3246  *  Reads a word(s) from the NVM
3247  **/
3248 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3249                               u16 *data)
3250 {
3251         struct e1000_nvm_info *nvm = &hw->nvm;
3252         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3253         u32 act_offset;
3254         s32 ret_val = 0;
3255         u32 bank = 0;
3256         u32 dword = 0;
3257         u16 offset_to_read;
3258         u16 i;
3259
3260         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3261             (words == 0)) {
3262                 e_dbg("nvm parameter(s) out of bounds\n");
3263                 ret_val = -E1000_ERR_NVM;
3264                 goto out;
3265         }
3266
3267         nvm->ops.acquire(hw);
3268
3269         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3270         if (ret_val) {
3271                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3272                 bank = 0;
3273         }
3274
3275         act_offset = (bank) ? nvm->flash_bank_size : 0;
3276         act_offset += offset;
3277
3278         ret_val = 0;
3279
3280         for (i = 0; i < words; i += 2) {
3281                 if (words - i == 1) {
3282                         if (dev_spec->shadow_ram[offset + i].modified) {
3283                                 data[i] =
3284                                     dev_spec->shadow_ram[offset + i].value;
3285                         } else {
3286                                 offset_to_read = act_offset + i -
3287                                     ((act_offset + i) % 2);
3288                                 ret_val =
3289                                   e1000_read_flash_dword_ich8lan(hw,
3290                                                                  offset_to_read,
3291                                                                  &dword);
3292                                 if (ret_val)
3293                                         break;
3294                                 if ((act_offset + i) % 2 == 0)
3295                                         data[i] = (u16)(dword & 0xFFFF);
3296                                 else
3297                                         data[i] = (u16)((dword >> 16) & 0xFFFF);
3298                         }
3299                 } else {
3300                         offset_to_read = act_offset + i;
3301                         if (!(dev_spec->shadow_ram[offset + i].modified) ||
3302                             !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3303                                 ret_val =
3304                                   e1000_read_flash_dword_ich8lan(hw,
3305                                                                  offset_to_read,
3306                                                                  &dword);
3307                                 if (ret_val)
3308                                         break;
3309                         }
3310                         if (dev_spec->shadow_ram[offset + i].modified)
3311                                 data[i] =
3312                                     dev_spec->shadow_ram[offset + i].value;
3313                         else
3314                                 data[i] = (u16)(dword & 0xFFFF);
3315                         if (dev_spec->shadow_ram[offset + i].modified)
3316                                 data[i + 1] =
3317                                     dev_spec->shadow_ram[offset + i + 1].value;
3318                         else
3319                                 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3320                 }
3321         }
3322
3323         nvm->ops.release(hw);
3324
3325 out:
3326         if (ret_val)
3327                 e_dbg("NVM read error: %d\n", ret_val);
3328
3329         return ret_val;
3330 }
3331
3332 /**
3333  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
3334  *  @hw: pointer to the HW structure
3335  *  @offset: The offset (in bytes) of the word(s) to read.
3336  *  @words: Size of data to read in words
3337  *  @data: Pointer to the word(s) to read at offset.
3338  *
3339  *  Reads a word(s) from the NVM using the flash access registers.
3340  **/
3341 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3342                                   u16 *data)
3343 {
3344         struct e1000_nvm_info *nvm = &hw->nvm;
3345         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3346         u32 act_offset;
3347         s32 ret_val = 0;
3348         u32 bank = 0;
3349         u16 i, word;
3350
3351         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3352             (words == 0)) {
3353                 e_dbg("nvm parameter(s) out of bounds\n");
3354                 ret_val = -E1000_ERR_NVM;
3355                 goto out;
3356         }
3357
3358         nvm->ops.acquire(hw);
3359
3360         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3361         if (ret_val) {
3362                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3363                 bank = 0;
3364         }
3365
3366         act_offset = (bank) ? nvm->flash_bank_size : 0;
3367         act_offset += offset;
3368
3369         ret_val = 0;
3370         for (i = 0; i < words; i++) {
3371                 if (dev_spec->shadow_ram[offset + i].modified) {
3372                         data[i] = dev_spec->shadow_ram[offset + i].value;
3373                 } else {
3374                         ret_val = e1000_read_flash_word_ich8lan(hw,
3375                                                                 act_offset + i,
3376                                                                 &word);
3377                         if (ret_val)
3378                                 break;
3379                         data[i] = word;
3380                 }
3381         }
3382
3383         nvm->ops.release(hw);
3384
3385 out:
3386         if (ret_val)
3387                 e_dbg("NVM read error: %d\n", ret_val);
3388
3389         return ret_val;
3390 }
3391
3392 /**
3393  *  e1000_flash_cycle_init_ich8lan - Initialize flash
3394  *  @hw: pointer to the HW structure
3395  *
3396  *  This function does initial flash setup so that a new read/write/erase cycle
3397  *  can be started.
3398  **/
3399 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3400 {
3401         union ich8_hws_flash_status hsfsts;
3402         s32 ret_val = -E1000_ERR_NVM;
3403
3404         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3405
3406         /* Check if the flash descriptor is valid */
3407         if (!hsfsts.hsf_status.fldesvalid) {
3408                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
3409                 return -E1000_ERR_NVM;
3410         }
3411
3412         /* Clear FCERR and DAEL in hw status by writing 1 */
3413         hsfsts.hsf_status.flcerr = 1;
3414         hsfsts.hsf_status.dael = 1;
3415         if (hw->mac.type >= e1000_pch_spt)
3416                 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3417         else
3418                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3419
3420         /* Either we should have a hardware SPI cycle in progress
3421          * bit to check against, in order to start a new cycle or
3422          * FDONE bit should be changed in the hardware so that it
3423          * is 1 after hardware reset, which can then be used as an
3424          * indication whether a cycle is in progress or has been
3425          * completed.
3426          */
3427
3428         if (!hsfsts.hsf_status.flcinprog) {
3429                 /* There is no cycle running at present,
3430                  * so we can start a cycle.
3431                  * Begin by setting Flash Cycle Done.
3432                  */
3433                 hsfsts.hsf_status.flcdone = 1;
3434                 if (hw->mac.type >= e1000_pch_spt)
3435                         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3436                 else
3437                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3438                 ret_val = 0;
3439         } else {
3440                 s32 i;
3441
3442                 /* Otherwise poll for sometime so the current
3443                  * cycle has a chance to end before giving up.
3444                  */
3445                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3446                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3447                         if (!hsfsts.hsf_status.flcinprog) {
3448                                 ret_val = 0;
3449                                 break;
3450                         }
3451                         udelay(1);
3452                 }
3453                 if (!ret_val) {
3454                         /* Successful in waiting for previous cycle to timeout,
3455                          * now set the Flash Cycle Done.
3456                          */
3457                         hsfsts.hsf_status.flcdone = 1;
3458                         if (hw->mac.type >= e1000_pch_spt)
3459                                 ew32flash(ICH_FLASH_HSFSTS,
3460                                           hsfsts.regval & 0xFFFF);
3461                         else
3462                                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3463                 } else {
3464                         e_dbg("Flash controller busy, cannot get access\n");
3465                 }
3466         }
3467
3468         return ret_val;
3469 }
3470
3471 /**
3472  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3473  *  @hw: pointer to the HW structure
3474  *  @timeout: maximum time to wait for completion
3475  *
3476  *  This function starts a flash cycle and waits for its completion.
3477  **/
3478 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3479 {
3480         union ich8_hws_flash_ctrl hsflctl;
3481         union ich8_hws_flash_status hsfsts;
3482         u32 i = 0;
3483
3484         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3485         if (hw->mac.type >= e1000_pch_spt)
3486                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3487         else
3488                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3489         hsflctl.hsf_ctrl.flcgo = 1;
3490
3491         if (hw->mac.type >= e1000_pch_spt)
3492                 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3493         else
3494                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3495
3496         /* wait till FDONE bit is set to 1 */
3497         do {
3498                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3499                 if (hsfsts.hsf_status.flcdone)
3500                         break;
3501                 udelay(1);
3502         } while (i++ < timeout);
3503
3504         if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3505                 return 0;
3506
3507         return -E1000_ERR_NVM;
3508 }
3509
3510 /**
3511  *  e1000_read_flash_dword_ich8lan - Read dword from flash
3512  *  @hw: pointer to the HW structure
3513  *  @offset: offset to data location
3514  *  @data: pointer to the location for storing the data
3515  *
3516  *  Reads the flash dword at offset into data.  Offset is converted
3517  *  to bytes before read.
3518  **/
3519 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3520                                           u32 *data)
3521 {
3522         /* Must convert word offset into bytes. */
3523         offset <<= 1;
3524         return e1000_read_flash_data32_ich8lan(hw, offset, data);
3525 }
3526
3527 /**
3528  *  e1000_read_flash_word_ich8lan - Read word from flash
3529  *  @hw: pointer to the HW structure
3530  *  @offset: offset to data location
3531  *  @data: pointer to the location for storing the data
3532  *
3533  *  Reads the flash word at offset into data.  Offset is converted
3534  *  to bytes before read.
3535  **/
3536 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3537                                          u16 *data)
3538 {
3539         /* Must convert offset into bytes. */
3540         offset <<= 1;
3541
3542         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3543 }
3544
3545 /**
3546  *  e1000_read_flash_byte_ich8lan - Read byte from flash
3547  *  @hw: pointer to the HW structure
3548  *  @offset: The offset of the byte to read.
3549  *  @data: Pointer to a byte to store the value read.
3550  *
3551  *  Reads a single byte from the NVM using the flash access registers.
3552  **/
3553 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3554                                          u8 *data)
3555 {
3556         s32 ret_val;
3557         u16 word = 0;
3558
3559         /* In SPT, only 32 bits access is supported,
3560          * so this function should not be called.
3561          */
3562         if (hw->mac.type >= e1000_pch_spt)
3563                 return -E1000_ERR_NVM;
3564         else
3565                 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3566
3567         if (ret_val)
3568                 return ret_val;
3569
3570         *data = (u8)word;
3571
3572         return 0;
3573 }
3574
3575 /**
3576  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
3577  *  @hw: pointer to the HW structure
3578  *  @offset: The offset (in bytes) of the byte or word to read.
3579  *  @size: Size of data to read, 1=byte 2=word
3580  *  @data: Pointer to the word to store the value read.
3581  *
3582  *  Reads a byte or word from the NVM using the flash access registers.
3583  **/
3584 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3585                                          u8 size, u16 *data)
3586 {
3587         union ich8_hws_flash_status hsfsts;
3588         union ich8_hws_flash_ctrl hsflctl;
3589         u32 flash_linear_addr;
3590         u32 flash_data = 0;
3591         s32 ret_val = -E1000_ERR_NVM;
3592         u8 count = 0;
3593
3594         if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3595                 return -E1000_ERR_NVM;
3596
3597         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3598                              hw->nvm.flash_base_addr);
3599
3600         do {
3601                 udelay(1);
3602                 /* Steps */
3603                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3604                 if (ret_val)
3605                         break;
3606
3607                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3608                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3609                 hsflctl.hsf_ctrl.fldbcount = size - 1;
3610                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3611                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3612
3613                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3614
3615                 ret_val =
3616                     e1000_flash_cycle_ich8lan(hw,
3617                                               ICH_FLASH_READ_COMMAND_TIMEOUT);
3618
3619                 /* Check if FCERR is set to 1, if set to 1, clear it
3620                  * and try the whole sequence a few more times, else
3621                  * read in (shift in) the Flash Data0, the order is
3622                  * least significant byte first msb to lsb
3623                  */
3624                 if (!ret_val) {
3625                         flash_data = er32flash(ICH_FLASH_FDATA0);
3626                         if (size == 1)
3627                                 *data = (u8)(flash_data & 0x000000FF);
3628                         else if (size == 2)
3629                                 *data = (u16)(flash_data & 0x0000FFFF);
3630                         break;
3631                 } else {
3632                         /* If we've gotten here, then things are probably
3633                          * completely hosed, but if the error condition is
3634                          * detected, it won't hurt to give it another try...
3635                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3636                          */
3637                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3638                         if (hsfsts.hsf_status.flcerr) {
3639                                 /* Repeat for some time before giving up. */
3640                                 continue;
3641                         } else if (!hsfsts.hsf_status.flcdone) {
3642                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3643                                 break;
3644                         }
3645                 }
3646         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3647
3648         return ret_val;
3649 }
3650
3651 /**
3652  *  e1000_read_flash_data32_ich8lan - Read dword from NVM
3653  *  @hw: pointer to the HW structure
3654  *  @offset: The offset (in bytes) of the dword to read.
3655  *  @data: Pointer to the dword to store the value read.
3656  *
3657  *  Reads a byte or word from the NVM using the flash access registers.
3658  **/
3659
3660 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3661                                            u32 *data)
3662 {
3663         union ich8_hws_flash_status hsfsts;
3664         union ich8_hws_flash_ctrl hsflctl;
3665         u32 flash_linear_addr;
3666         s32 ret_val = -E1000_ERR_NVM;
3667         u8 count = 0;
3668
3669         if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3670                 return -E1000_ERR_NVM;
3671         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3672                              hw->nvm.flash_base_addr);
3673
3674         do {
3675                 udelay(1);
3676                 /* Steps */
3677                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3678                 if (ret_val)
3679                         break;
3680                 /* In SPT, This register is in Lan memory space, not flash.
3681                  * Therefore, only 32 bit access is supported
3682                  */
3683                 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3684
3685                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3686                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3687                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3688                 /* In SPT, This register is in Lan memory space, not flash.
3689                  * Therefore, only 32 bit access is supported
3690                  */
3691                 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3692                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3693
3694                 ret_val =
3695                    e1000_flash_cycle_ich8lan(hw,
3696                                              ICH_FLASH_READ_COMMAND_TIMEOUT);
3697
3698                 /* Check if FCERR is set to 1, if set to 1, clear it
3699                  * and try the whole sequence a few more times, else
3700                  * read in (shift in) the Flash Data0, the order is
3701                  * least significant byte first msb to lsb
3702                  */
3703                 if (!ret_val) {
3704                         *data = er32flash(ICH_FLASH_FDATA0);
3705                         break;
3706                 } else {
3707                         /* If we've gotten here, then things are probably
3708                          * completely hosed, but if the error condition is
3709                          * detected, it won't hurt to give it another try...
3710                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3711                          */
3712                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3713                         if (hsfsts.hsf_status.flcerr) {
3714                                 /* Repeat for some time before giving up. */
3715                                 continue;
3716                         } else if (!hsfsts.hsf_status.flcdone) {
3717                                 e_dbg("Timeout error - flash cycle did not complete.\n");
3718                                 break;
3719                         }
3720                 }
3721         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3722
3723         return ret_val;
3724 }
3725
3726 /**
3727  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
3728  *  @hw: pointer to the HW structure
3729  *  @offset: The offset (in bytes) of the word(s) to write.
3730  *  @words: Size of data to write in words
3731  *  @data: Pointer to the word(s) to write at offset.
3732  *
3733  *  Writes a byte or word to the NVM using the flash access registers.
3734  **/
3735 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3736                                    u16 *data)
3737 {
3738         struct e1000_nvm_info *nvm = &hw->nvm;
3739         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3740         u16 i;
3741
3742         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3743             (words == 0)) {
3744                 e_dbg("nvm parameter(s) out of bounds\n");
3745                 return -E1000_ERR_NVM;
3746         }
3747
3748         nvm->ops.acquire(hw);
3749
3750         for (i = 0; i < words; i++) {
3751                 dev_spec->shadow_ram[offset + i].modified = true;
3752                 dev_spec->shadow_ram[offset + i].value = data[i];
3753         }
3754
3755         nvm->ops.release(hw);
3756
3757         return 0;
3758 }
3759
3760 /**
3761  *  e1000_update_nvm_checksum_spt - Update the checksum for NVM
3762  *  @hw: pointer to the HW structure
3763  *
3764  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3765  *  which writes the checksum to the shadow ram.  The changes in the shadow
3766  *  ram are then committed to the EEPROM by processing each bank at a time
3767  *  checking for the modified bit and writing only the pending changes.
3768  *  After a successful commit, the shadow ram is cleared and is ready for
3769  *  future writes.
3770  **/
3771 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3772 {
3773         struct e1000_nvm_info *nvm = &hw->nvm;
3774         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3775         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3776         s32 ret_val;
3777         u32 dword = 0;
3778
3779         ret_val = e1000e_update_nvm_checksum_generic(hw);
3780         if (ret_val)
3781                 goto out;
3782
3783         if (nvm->type != e1000_nvm_flash_sw)
3784                 goto out;
3785
3786         nvm->ops.acquire(hw);
3787
3788         /* We're writing to the opposite bank so if we're on bank 1,
3789          * write to bank 0 etc.  We also need to erase the segment that
3790          * is going to be written
3791          */
3792         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3793         if (ret_val) {
3794                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3795                 bank = 0;
3796         }
3797
3798         if (bank == 0) {
3799                 new_bank_offset = nvm->flash_bank_size;
3800                 old_bank_offset = 0;
3801                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3802                 if (ret_val)
3803                         goto release;
3804         } else {
3805                 old_bank_offset = nvm->flash_bank_size;
3806                 new_bank_offset = 0;
3807                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3808                 if (ret_val)
3809                         goto release;
3810         }
3811         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3812                 /* Determine whether to write the value stored
3813                  * in the other NVM bank or a modified value stored
3814                  * in the shadow RAM
3815                  */
3816                 ret_val = e1000_read_flash_dword_ich8lan(hw,
3817                                                          i + old_bank_offset,
3818                                                          &dword);
3819
3820                 if (dev_spec->shadow_ram[i].modified) {
3821                         dword &= 0xffff0000;
3822                         dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3823                 }
3824                 if (dev_spec->shadow_ram[i + 1].modified) {
3825                         dword &= 0x0000ffff;
3826                         dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3827                                   << 16);
3828                 }
3829                 if (ret_val)
3830                         break;
3831
3832                 /* If the word is 0x13, then make sure the signature bits
3833                  * (15:14) are 11b until the commit has completed.
3834                  * This will allow us to write 10b which indicates the
3835                  * signature is valid.  We want to do this after the write
3836                  * has completed so that we don't mark the segment valid
3837                  * while the write is still in progress
3838                  */
3839                 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3840                         dword |= E1000_ICH_NVM_SIG_MASK << 16;
3841
3842                 /* Convert offset to bytes. */
3843                 act_offset = (i + new_bank_offset) << 1;
3844
3845                 usleep_range(100, 200);
3846
3847                 /* Write the data to the new bank. Offset in words */
3848                 act_offset = i + new_bank_offset;
3849                 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3850                                                                 dword);
3851                 if (ret_val)
3852                         break;
3853         }
3854
3855         /* Don't bother writing the segment valid bits if sector
3856          * programming failed.
3857          */
3858         if (ret_val) {
3859                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3860                 e_dbg("Flash commit failed.\n");
3861                 goto release;
3862         }
3863
3864         /* Finally validate the new segment by setting bit 15:14
3865          * to 10b in word 0x13 , this can be done without an
3866          * erase as well since these bits are 11 to start with
3867          * and we need to change bit 14 to 0b
3868          */
3869         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3870
3871         /*offset in words but we read dword */
3872         --act_offset;
3873         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3874
3875         if (ret_val)
3876                 goto release;
3877
3878         dword &= 0xBFFFFFFF;
3879         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3880
3881         if (ret_val)
3882                 goto release;
3883
3884         /* And invalidate the previously valid segment by setting
3885          * its signature word (0x13) high_byte to 0b. This can be
3886          * done without an erase because flash erase sets all bits
3887          * to 1's. We can write 1's to 0's without an erase
3888          */
3889         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3890
3891         /* offset in words but we read dword */
3892         act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3893         ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3894
3895         if (ret_val)
3896                 goto release;
3897
3898         dword &= 0x00FFFFFF;
3899         ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3900
3901         if (ret_val)
3902                 goto release;
3903
3904         /* Great!  Everything worked, we can now clear the cached entries. */
3905         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3906                 dev_spec->shadow_ram[i].modified = false;
3907                 dev_spec->shadow_ram[i].value = 0xFFFF;
3908         }
3909
3910 release:
3911         nvm->ops.release(hw);
3912
3913         /* Reload the EEPROM, or else modifications will not appear
3914          * until after the next adapter reset.
3915          */
3916         if (!ret_val) {
3917                 nvm->ops.reload(hw);
3918                 usleep_range(10000, 20000);
3919         }
3920
3921 out:
3922         if (ret_val)
3923                 e_dbg("NVM update error: %d\n", ret_val);
3924
3925         return ret_val;
3926 }
3927
3928 /**
3929  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3930  *  @hw: pointer to the HW structure
3931  *
3932  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
3933  *  which writes the checksum to the shadow ram.  The changes in the shadow
3934  *  ram are then committed to the EEPROM by processing each bank at a time
3935  *  checking for the modified bit and writing only the pending changes.
3936  *  After a successful commit, the shadow ram is cleared and is ready for
3937  *  future writes.
3938  **/
3939 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3940 {
3941         struct e1000_nvm_info *nvm = &hw->nvm;
3942         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3943         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3944         s32 ret_val;
3945         u16 data = 0;
3946
3947         ret_val = e1000e_update_nvm_checksum_generic(hw);
3948         if (ret_val)
3949                 goto out;
3950
3951         if (nvm->type != e1000_nvm_flash_sw)
3952                 goto out;
3953
3954         nvm->ops.acquire(hw);
3955
3956         /* We're writing to the opposite bank so if we're on bank 1,
3957          * write to bank 0 etc.  We also need to erase the segment that
3958          * is going to be written
3959          */
3960         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3961         if (ret_val) {
3962                 e_dbg("Could not detect valid bank, assuming bank 0\n");
3963                 bank = 0;
3964         }
3965
3966         if (bank == 0) {
3967                 new_bank_offset = nvm->flash_bank_size;
3968                 old_bank_offset = 0;
3969                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3970                 if (ret_val)
3971                         goto release;
3972         } else {
3973                 old_bank_offset = nvm->flash_bank_size;
3974                 new_bank_offset = 0;
3975                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3976                 if (ret_val)
3977                         goto release;
3978         }
3979         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3980                 if (dev_spec->shadow_ram[i].modified) {
3981                         data = dev_spec->shadow_ram[i].value;
3982                 } else {
3983                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
3984                                                                 old_bank_offset,
3985                                                                 &data);
3986                         if (ret_val)
3987                                 break;
3988                 }
3989
3990                 /* If the word is 0x13, then make sure the signature bits
3991                  * (15:14) are 11b until the commit has completed.
3992                  * This will allow us to write 10b which indicates the
3993                  * signature is valid.  We want to do this after the write
3994                  * has completed so that we don't mark the segment valid
3995                  * while the write is still in progress
3996                  */
3997                 if (i == E1000_ICH_NVM_SIG_WORD)
3998                         data |= E1000_ICH_NVM_SIG_MASK;
3999
4000                 /* Convert offset to bytes. */
4001                 act_offset = (i + new_bank_offset) << 1;
4002
4003                 usleep_range(100, 200);
4004                 /* Write the bytes to the new bank. */
4005                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4006                                                                act_offset,
4007                                                                (u8)data);
4008                 if (ret_val)
4009                         break;
4010
4011                 usleep_range(100, 200);
4012                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4013                                                                act_offset + 1,
4014                                                                (u8)(data >> 8));
4015                 if (ret_val)
4016                         break;
4017         }
4018
4019         /* Don't bother writing the segment valid bits if sector
4020          * programming failed.
4021          */
4022         if (ret_val) {
4023                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4024                 e_dbg("Flash commit failed.\n");
4025                 goto release;
4026         }
4027
4028         /* Finally validate the new segment by setting bit 15:14
4029          * to 10b in word 0x13 , this can be done without an
4030          * erase as well since these bits are 11 to start with
4031          * and we need to change bit 14 to 0b
4032          */
4033         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4034         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4035         if (ret_val)
4036                 goto release;
4037
4038         data &= 0xBFFF;
4039         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4040                                                        act_offset * 2 + 1,
4041                                                        (u8)(data >> 8));
4042         if (ret_val)
4043                 goto release;
4044
4045         /* And invalidate the previously valid segment by setting
4046          * its signature word (0x13) high_byte to 0b. This can be
4047          * done without an erase because flash erase sets all bits
4048          * to 1's. We can write 1's to 0's without an erase
4049          */
4050         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4051         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4052         if (ret_val)
4053                 goto release;
4054
4055         /* Great!  Everything worked, we can now clear the cached entries. */
4056         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4057                 dev_spec->shadow_ram[i].modified = false;
4058                 dev_spec->shadow_ram[i].value = 0xFFFF;
4059         }
4060
4061 release:
4062         nvm->ops.release(hw);
4063
4064         /* Reload the EEPROM, or else modifications will not appear
4065          * until after the next adapter reset.
4066          */
4067         if (!ret_val) {
4068                 nvm->ops.reload(hw);
4069                 usleep_range(10000, 20000);
4070         }
4071
4072 out:
4073         if (ret_val)
4074                 e_dbg("NVM update error: %d\n", ret_val);
4075
4076         return ret_val;
4077 }
4078
4079 /**
4080  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4081  *  @hw: pointer to the HW structure
4082  *
4083  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4084  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
4085  *  calculated, in which case we need to calculate the checksum and set bit 6.
4086  **/
4087 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4088 {
4089         s32 ret_val;
4090         u16 data;
4091         u16 word;
4092         u16 valid_csum_mask;
4093
4094         /* Read NVM and check Invalid Image CSUM bit.  If this bit is 0,
4095          * the checksum needs to be fixed.  This bit is an indication that
4096          * the NVM was prepared by OEM software and did not calculate
4097          * the checksum...a likely scenario.
4098          */
4099         switch (hw->mac.type) {
4100         case e1000_pch_lpt:
4101         case e1000_pch_spt:
4102         case e1000_pch_cnp:
4103                 word = NVM_COMPAT;
4104                 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4105                 break;
4106         default:
4107                 word = NVM_FUTURE_INIT_WORD1;
4108                 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4109                 break;
4110         }
4111
4112         ret_val = e1000_read_nvm(hw, word, 1, &data);
4113         if (ret_val)
4114                 return ret_val;
4115
4116         if (!(data & valid_csum_mask)) {
4117                 data |= valid_csum_mask;
4118                 ret_val = e1000_write_nvm(hw, word, 1, &data);
4119                 if (ret_val)
4120                         return ret_val;
4121                 ret_val = e1000e_update_nvm_checksum(hw);
4122                 if (ret_val)
4123                         return ret_val;
4124         }
4125
4126         return e1000e_validate_nvm_checksum_generic(hw);
4127 }
4128
4129 /**
4130  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4131  *  @hw: pointer to the HW structure
4132  *
4133  *  To prevent malicious write/erase of the NVM, set it to be read-only
4134  *  so that the hardware ignores all write/erase cycles of the NVM via
4135  *  the flash control registers.  The shadow-ram copy of the NVM will
4136  *  still be updated, however any updates to this copy will not stick
4137  *  across driver reloads.
4138  **/
4139 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4140 {
4141         struct e1000_nvm_info *nvm = &hw->nvm;
4142         union ich8_flash_protected_range pr0;
4143         union ich8_hws_flash_status hsfsts;
4144         u32 gfpreg;
4145
4146         nvm->ops.acquire(hw);
4147
4148         gfpreg = er32flash(ICH_FLASH_GFPREG);
4149
4150         /* Write-protect GbE Sector of NVM */
4151         pr0.regval = er32flash(ICH_FLASH_PR0);
4152         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4153         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4154         pr0.range.wpe = true;
4155         ew32flash(ICH_FLASH_PR0, pr0.regval);
4156
4157         /* Lock down a subset of GbE Flash Control Registers, e.g.
4158          * PR0 to prevent the write-protection from being lifted.
4159          * Once FLOCKDN is set, the registers protected by it cannot
4160          * be written until FLOCKDN is cleared by a hardware reset.
4161          */
4162         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4163         hsfsts.hsf_status.flockdn = true;
4164         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4165
4166         nvm->ops.release(hw);
4167 }
4168
4169 /**
4170  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4171  *  @hw: pointer to the HW structure
4172  *  @offset: The offset (in bytes) of the byte/word to read.
4173  *  @size: Size of data to read, 1=byte 2=word
4174  *  @data: The byte(s) to write to the NVM.
4175  *
4176  *  Writes one/two bytes to the NVM using the flash access registers.
4177  **/
4178 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4179                                           u8 size, u16 data)
4180 {
4181         union ich8_hws_flash_status hsfsts;
4182         union ich8_hws_flash_ctrl hsflctl;
4183         u32 flash_linear_addr;
4184         u32 flash_data = 0;
4185         s32 ret_val;
4186         u8 count = 0;
4187
4188         if (hw->mac.type >= e1000_pch_spt) {
4189                 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4190                         return -E1000_ERR_NVM;
4191         } else {
4192                 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4193                         return -E1000_ERR_NVM;
4194         }
4195
4196         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4197                              hw->nvm.flash_base_addr);
4198
4199         do {
4200                 udelay(1);
4201                 /* Steps */
4202                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4203                 if (ret_val)
4204                         break;
4205                 /* In SPT, This register is in Lan memory space, not
4206                  * flash.  Therefore, only 32 bit access is supported
4207                  */
4208                 if (hw->mac.type >= e1000_pch_spt)
4209                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4210                 else
4211                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4212
4213                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4214                 hsflctl.hsf_ctrl.fldbcount = size - 1;
4215                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4216                 /* In SPT, This register is in Lan memory space,
4217                  * not flash.  Therefore, only 32 bit access is
4218                  * supported
4219                  */
4220                 if (hw->mac.type >= e1000_pch_spt)
4221                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4222                 else
4223                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4224
4225                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4226
4227                 if (size == 1)
4228                         flash_data = (u32)data & 0x00FF;
4229                 else
4230                         flash_data = (u32)data;
4231
4232                 ew32flash(ICH_FLASH_FDATA0, flash_data);
4233
4234                 /* check if FCERR is set to 1 , if set to 1, clear it
4235                  * and try the whole sequence a few more times else done
4236                  */
4237                 ret_val =
4238                     e1000_flash_cycle_ich8lan(hw,
4239                                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4240                 if (!ret_val)
4241                         break;
4242
4243                 /* If we're here, then things are most likely
4244                  * completely hosed, but if the error condition
4245                  * is detected, it won't hurt to give it another
4246                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4247                  */
4248                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4249                 if (hsfsts.hsf_status.flcerr)
4250                         /* Repeat for some time before giving up. */
4251                         continue;
4252                 if (!hsfsts.hsf_status.flcdone) {
4253                         e_dbg("Timeout error - flash cycle did not complete.\n");
4254                         break;
4255                 }
4256         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4257
4258         return ret_val;
4259 }
4260
4261 /**
4262 *  e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4263 *  @hw: pointer to the HW structure
4264 *  @offset: The offset (in bytes) of the dwords to read.
4265 *  @data: The 4 bytes to write to the NVM.
4266 *
4267 *  Writes one/two/four bytes to the NVM using the flash access registers.
4268 **/
4269 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4270                                             u32 data)
4271 {
4272         union ich8_hws_flash_status hsfsts;
4273         union ich8_hws_flash_ctrl hsflctl;
4274         u32 flash_linear_addr;
4275         s32 ret_val;
4276         u8 count = 0;
4277
4278         if (hw->mac.type >= e1000_pch_spt) {
4279                 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4280                         return -E1000_ERR_NVM;
4281         }
4282         flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4283                              hw->nvm.flash_base_addr);
4284         do {
4285                 udelay(1);
4286                 /* Steps */
4287                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4288                 if (ret_val)
4289                         break;
4290
4291                 /* In SPT, This register is in Lan memory space, not
4292                  * flash.  Therefore, only 32 bit access is supported
4293                  */
4294                 if (hw->mac.type >= e1000_pch_spt)
4295                         hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4296                             >> 16;
4297                 else
4298                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4299
4300                 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4301                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4302
4303                 /* In SPT, This register is in Lan memory space,
4304                  * not flash.  Therefore, only 32 bit access is
4305                  * supported
4306                  */
4307                 if (hw->mac.type >= e1000_pch_spt)
4308                         ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4309                 else
4310                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4311
4312                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4313
4314                 ew32flash(ICH_FLASH_FDATA0, data);
4315
4316                 /* check if FCERR is set to 1 , if set to 1, clear it
4317                  * and try the whole sequence a few more times else done
4318                  */
4319                 ret_val =
4320                    e1000_flash_cycle_ich8lan(hw,
4321                                              ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4322
4323                 if (!ret_val)
4324                         break;
4325
4326                 /* If we're here, then things are most likely
4327                  * completely hosed, but if the error condition
4328                  * is detected, it won't hurt to give it another
4329                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4330                  */
4331                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4332
4333                 if (hsfsts.hsf_status.flcerr)
4334                         /* Repeat for some time before giving up. */
4335                         continue;
4336                 if (!hsfsts.hsf_status.flcdone) {
4337                         e_dbg("Timeout error - flash cycle did not complete.\n");
4338                         break;
4339                 }
4340         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4341
4342         return ret_val;
4343 }
4344
4345 /**
4346  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4347  *  @hw: pointer to the HW structure
4348  *  @offset: The index of the byte to read.
4349  *  @data: The byte to write to the NVM.
4350  *
4351  *  Writes a single byte to the NVM using the flash access registers.
4352  **/
4353 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4354                                           u8 data)
4355 {
4356         u16 word = (u16)data;
4357
4358         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4359 }
4360
4361 /**
4362 *  e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4363 *  @hw: pointer to the HW structure
4364 *  @offset: The offset of the word to write.
4365 *  @dword: The dword to write to the NVM.
4366 *
4367 *  Writes a single dword to the NVM using the flash access registers.
4368 *  Goes through a retry algorithm before giving up.
4369 **/
4370 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4371                                                  u32 offset, u32 dword)
4372 {
4373         s32 ret_val;
4374         u16 program_retries;
4375
4376         /* Must convert word offset into bytes. */
4377         offset <<= 1;
4378         ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4379
4380         if (!ret_val)
4381                 return ret_val;
4382         for (program_retries = 0; program_retries < 100; program_retries++) {
4383                 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4384                 usleep_range(100, 200);
4385                 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4386                 if (!ret_val)
4387                         break;
4388         }
4389         if (program_retries == 100)
4390                 return -E1000_ERR_NVM;
4391
4392         return 0;
4393 }
4394
4395 /**
4396  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4397  *  @hw: pointer to the HW structure
4398  *  @offset: The offset of the byte to write.
4399  *  @byte: The byte to write to the NVM.
4400  *
4401  *  Writes a single byte to the NVM using the flash access registers.
4402  *  Goes through a retry algorithm before giving up.
4403  **/
4404 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4405                                                 u32 offset, u8 byte)
4406 {
4407         s32 ret_val;
4408         u16 program_retries;
4409
4410         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4411         if (!ret_val)
4412                 return ret_val;
4413
4414         for (program_retries = 0; program_retries < 100; program_retries++) {
4415                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4416                 usleep_range(100, 200);
4417                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4418                 if (!ret_val)
4419                         break;
4420         }
4421         if (program_retries == 100)
4422                 return -E1000_ERR_NVM;
4423
4424         return 0;
4425 }
4426
4427 /**
4428  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4429  *  @hw: pointer to the HW structure
4430  *  @bank: 0 for first bank, 1 for second bank, etc.
4431  *
4432  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4433  *  bank N is 4096 * N + flash_reg_addr.
4434  **/
4435 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4436 {
4437         struct e1000_nvm_info *nvm = &hw->nvm;
4438         union ich8_hws_flash_status hsfsts;
4439         union ich8_hws_flash_ctrl hsflctl;
4440         u32 flash_linear_addr;
4441         /* bank size is in 16bit words - adjust to bytes */
4442         u32 flash_bank_size = nvm->flash_bank_size * 2;
4443         s32 ret_val;
4444         s32 count = 0;
4445         s32 j, iteration, sector_size;
4446
4447         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4448
4449         /* Determine HW Sector size: Read BERASE bits of hw flash status
4450          * register
4451          * 00: The Hw sector is 256 bytes, hence we need to erase 16
4452          *     consecutive sectors.  The start index for the nth Hw sector
4453          *     can be calculated as = bank * 4096 + n * 256
4454          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4455          *     The start index for the nth Hw sector can be calculated
4456          *     as = bank * 4096
4457          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4458          *     (ich9 only, otherwise error condition)
4459          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4460          */
4461         switch (hsfsts.hsf_status.berasesz) {
4462         case 0:
4463                 /* Hw sector size 256 */
4464                 sector_size = ICH_FLASH_SEG_SIZE_256;
4465                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4466                 break;
4467         case 1:
4468                 sector_size = ICH_FLASH_SEG_SIZE_4K;
4469                 iteration = 1;
4470                 break;
4471         case 2:
4472                 sector_size = ICH_FLASH_SEG_SIZE_8K;
4473                 iteration = 1;
4474                 break;
4475         case 3:
4476                 sector_size = ICH_FLASH_SEG_SIZE_64K;
4477                 iteration = 1;
4478                 break;
4479         default:
4480                 return -E1000_ERR_NVM;
4481         }
4482
4483         /* Start with the base address, then add the sector offset. */
4484         flash_linear_addr = hw->nvm.flash_base_addr;
4485         flash_linear_addr += (bank) ? flash_bank_size : 0;
4486
4487         for (j = 0; j < iteration; j++) {
4488                 do {
4489                         u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4490
4491                         /* Steps */
4492                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
4493                         if (ret_val)
4494                                 return ret_val;
4495
4496                         /* Write a value 11 (block Erase) in Flash
4497                          * Cycle field in hw flash control
4498                          */
4499                         if (hw->mac.type >= e1000_pch_spt)
4500                                 hsflctl.regval =
4501                                     er32flash(ICH_FLASH_HSFSTS) >> 16;
4502                         else
4503                                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4504
4505                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4506                         if (hw->mac.type >= e1000_pch_spt)
4507                                 ew32flash(ICH_FLASH_HSFSTS,
4508                                           hsflctl.regval << 16);
4509                         else
4510                                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4511
4512                         /* Write the last 24 bits of an index within the
4513                          * block into Flash Linear address field in Flash
4514                          * Address.
4515                          */
4516                         flash_linear_addr += (j * sector_size);
4517                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4518
4519                         ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4520                         if (!ret_val)
4521                                 break;
4522
4523                         /* Check if FCERR is set to 1.  If 1,
4524                          * clear it and try the whole sequence
4525                          * a few more times else Done
4526                          */
4527                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4528                         if (hsfsts.hsf_status.flcerr)
4529                                 /* repeat for some time before giving up */
4530                                 continue;
4531                         else if (!hsfsts.hsf_status.flcdone)
4532                                 return ret_val;
4533                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4534         }
4535
4536         return 0;
4537 }
4538
4539 /**
4540  *  e1000_valid_led_default_ich8lan - Set the default LED settings
4541  *  @hw: pointer to the HW structure
4542  *  @data: Pointer to the LED settings
4543  *
4544  *  Reads the LED default settings from the NVM to data.  If the NVM LED
4545  *  settings is all 0's or F's, set the LED default to a valid LED default
4546  *  setting.
4547  **/
4548 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4549 {
4550         s32 ret_val;
4551
4552         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4553         if (ret_val) {
4554                 e_dbg("NVM Read Error\n");
4555                 return ret_val;
4556         }
4557
4558         if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4559                 *data = ID_LED_DEFAULT_ICH8LAN;
4560
4561         return 0;
4562 }
4563
4564 /**
4565  *  e1000_id_led_init_pchlan - store LED configurations
4566  *  @hw: pointer to the HW structure
4567  *
4568  *  PCH does not control LEDs via the LEDCTL register, rather it uses
4569  *  the PHY LED configuration register.
4570  *
4571  *  PCH also does not have an "always on" or "always off" mode which
4572  *  complicates the ID feature.  Instead of using the "on" mode to indicate
4573  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4574  *  use "link_up" mode.  The LEDs will still ID on request if there is no
4575  *  link based on logic in e1000_led_[on|off]_pchlan().
4576  **/
4577 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4578 {
4579         struct e1000_mac_info *mac = &hw->mac;
4580         s32 ret_val;
4581         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4582         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4583         u16 data, i, temp, shift;
4584
4585         /* Get default ID LED modes */
4586         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4587         if (ret_val)
4588                 return ret_val;
4589
4590         mac->ledctl_default = er32(LEDCTL);
4591         mac->ledctl_mode1 = mac->ledctl_default;
4592         mac->ledctl_mode2 = mac->ledctl_default;
4593
4594         for (i = 0; i < 4; i++) {
4595                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4596                 shift = (i * 5);
4597                 switch (temp) {
4598                 case ID_LED_ON1_DEF2:
4599                 case ID_LED_ON1_ON2:
4600                 case ID_LED_ON1_OFF2:
4601                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4602                         mac->ledctl_mode1 |= (ledctl_on << shift);
4603                         break;
4604                 case ID_LED_OFF1_DEF2:
4605                 case ID_LED_OFF1_ON2:
4606                 case ID_LED_OFF1_OFF2:
4607                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4608                         mac->ledctl_mode1 |= (ledctl_off << shift);
4609                         break;
4610                 default:
4611                         /* Do nothing */
4612                         break;
4613                 }
4614                 switch (temp) {
4615                 case ID_LED_DEF1_ON2:
4616                 case ID_LED_ON1_ON2:
4617                 case ID_LED_OFF1_ON2:
4618                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4619                         mac->ledctl_mode2 |= (ledctl_on << shift);
4620                         break;
4621                 case ID_LED_DEF1_OFF2:
4622                 case ID_LED_ON1_OFF2:
4623                 case ID_LED_OFF1_OFF2:
4624                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4625                         mac->ledctl_mode2 |= (ledctl_off << shift);
4626                         break;
4627                 default:
4628                         /* Do nothing */
4629                         break;
4630                 }
4631         }
4632
4633         return 0;
4634 }
4635
4636 /**
4637  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4638  *  @hw: pointer to the HW structure
4639  *
4640  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4641  *  register, so the the bus width is hard coded.
4642  **/
4643 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4644 {
4645         struct e1000_bus_info *bus = &hw->bus;
4646         s32 ret_val;
4647
4648         ret_val = e1000e_get_bus_info_pcie(hw);
4649
4650         /* ICH devices are "PCI Express"-ish.  They have
4651          * a configuration space, but do not contain
4652          * PCI Express Capability registers, so bus width
4653          * must be hardcoded.
4654          */
4655         if (bus->width == e1000_bus_width_unknown)
4656                 bus->width = e1000_bus_width_pcie_x1;
4657
4658         return ret_val;
4659 }
4660
4661 /**
4662  *  e1000_reset_hw_ich8lan - Reset the hardware
4663  *  @hw: pointer to the HW structure
4664  *
4665  *  Does a full reset of the hardware which includes a reset of the PHY and
4666  *  MAC.
4667  **/
4668 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4669 {
4670         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4671         u16 kum_cfg;
4672         u32 ctrl, reg;
4673         s32 ret_val;
4674
4675         /* Prevent the PCI-E bus from sticking if there is no TLP connection
4676          * on the last TLP read/write transaction when MAC is reset.
4677          */
4678         ret_val = e1000e_disable_pcie_master(hw);
4679         if (ret_val)
4680                 e_dbg("PCI-E Master disable polling has failed.\n");
4681
4682         e_dbg("Masking off all interrupts\n");
4683         ew32(IMC, 0xffffffff);
4684
4685         /* Disable the Transmit and Receive units.  Then delay to allow
4686          * any pending transactions to complete before we hit the MAC
4687          * with the global reset.
4688          */
4689         ew32(RCTL, 0);
4690         ew32(TCTL, E1000_TCTL_PSP);
4691         e1e_flush();
4692
4693         usleep_range(10000, 20000);
4694
4695         /* Workaround for ICH8 bit corruption issue in FIFO memory */
4696         if (hw->mac.type == e1000_ich8lan) {
4697                 /* Set Tx and Rx buffer allocation to 8k apiece. */
4698                 ew32(PBA, E1000_PBA_8K);
4699                 /* Set Packet Buffer Size to 16k. */
4700                 ew32(PBS, E1000_PBS_16K);
4701         }
4702
4703         if (hw->mac.type == e1000_pchlan) {
4704                 /* Save the NVM K1 bit setting */
4705                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4706                 if (ret_val)
4707                         return ret_val;
4708
4709                 if (kum_cfg & E1000_NVM_K1_ENABLE)
4710                         dev_spec->nvm_k1_enabled = true;
4711                 else
4712                         dev_spec->nvm_k1_enabled = false;
4713         }
4714
4715         ctrl = er32(CTRL);
4716
4717         if (!hw->phy.ops.check_reset_block(hw)) {
4718                 /* Full-chip reset requires MAC and PHY reset at the same
4719                  * time to make sure the interface between MAC and the
4720                  * external PHY is reset.
4721                  */
4722                 ctrl |= E1000_CTRL_PHY_RST;
4723
4724                 /* Gate automatic PHY configuration by hardware on
4725                  * non-managed 82579
4726                  */
4727                 if ((hw->mac.type == e1000_pch2lan) &&
4728                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4729                         e1000_gate_hw_phy_config_ich8lan(hw, true);
4730         }
4731         ret_val = e1000_acquire_swflag_ich8lan(hw);
4732         e_dbg("Issuing a global reset to ich8lan\n");
4733         ew32(CTRL, (ctrl | E1000_CTRL_RST));
4734         /* cannot issue a flush here because it hangs the hardware */
4735         msleep(20);
4736
4737         /* Set Phy Config Counter to 50msec */
4738         if (hw->mac.type == e1000_pch2lan) {
4739                 reg = er32(FEXTNVM3);
4740                 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4741                 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4742                 ew32(FEXTNVM3, reg);
4743         }
4744
4745         if (!ret_val)
4746                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4747
4748         if (ctrl & E1000_CTRL_PHY_RST) {
4749                 ret_val = hw->phy.ops.get_cfg_done(hw);
4750                 if (ret_val)
4751                         return ret_val;
4752
4753                 ret_val = e1000_post_phy_reset_ich8lan(hw);
4754                 if (ret_val)
4755                         return ret_val;
4756         }
4757
4758         /* For PCH, this write will make sure that any noise
4759          * will be detected as a CRC error and be dropped rather than show up
4760          * as a bad packet to the DMA engine.
4761          */
4762         if (hw->mac.type == e1000_pchlan)
4763                 ew32(CRC_OFFSET, 0x65656565);
4764
4765         ew32(IMC, 0xffffffff);
4766         er32(ICR);
4767
4768         reg = er32(KABGTXD);
4769         reg |= E1000_KABGTXD_BGSQLBIAS;
4770         ew32(KABGTXD, reg);
4771
4772         return 0;
4773 }
4774
4775 /**
4776  *  e1000_init_hw_ich8lan - Initialize the hardware
4777  *  @hw: pointer to the HW structure
4778  *
4779  *  Prepares the hardware for transmit and receive by doing the following:
4780  *   - initialize hardware bits
4781  *   - initialize LED identification
4782  *   - setup receive address registers
4783  *   - setup flow control
4784  *   - setup transmit descriptors
4785  *   - clear statistics
4786  **/
4787 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4788 {
4789         struct e1000_mac_info *mac = &hw->mac;
4790         u32 ctrl_ext, txdctl, snoop;
4791         s32 ret_val;
4792         u16 i;
4793
4794         e1000_initialize_hw_bits_ich8lan(hw);
4795
4796         /* Initialize identification LED */
4797         ret_val = mac->ops.id_led_init(hw);
4798         /* An error is not fatal and we should not stop init due to this */
4799         if (ret_val)
4800                 e_dbg("Error initializing identification LED\n");
4801
4802         /* Setup the receive address. */
4803         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4804
4805         /* Zero out the Multicast HASH table */
4806         e_dbg("Zeroing the MTA\n");
4807         for (i = 0; i < mac->mta_reg_count; i++)
4808                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4809
4810         /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4811          * the ME.  Disable wakeup by clearing the host wakeup bit.
4812          * Reset the phy after disabling host wakeup to reset the Rx buffer.
4813          */
4814         if (hw->phy.type == e1000_phy_82578) {
4815                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4816                 i &= ~BM_WUC_HOST_WU_BIT;
4817                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4818                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4819                 if (ret_val)
4820                         return ret_val;
4821         }
4822
4823         /* Setup link and flow control */
4824         ret_val = mac->ops.setup_link(hw);
4825
4826         /* Set the transmit descriptor write-back policy for both queues */
4827         txdctl = er32(TXDCTL(0));
4828         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4829                   E1000_TXDCTL_FULL_TX_DESC_WB);
4830         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4831                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4832         ew32(TXDCTL(0), txdctl);
4833         txdctl = er32(TXDCTL(1));
4834         txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4835                   E1000_TXDCTL_FULL_TX_DESC_WB);
4836         txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4837                   E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4838         ew32(TXDCTL(1), txdctl);
4839
4840         /* ICH8 has opposite polarity of no_snoop bits.
4841          * By default, we should use snoop behavior.
4842          */
4843         if (mac->type == e1000_ich8lan)
4844                 snoop = PCIE_ICH8_SNOOP_ALL;
4845         else
4846                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4847         e1000e_set_pcie_no_snoop(hw, snoop);
4848
4849         ctrl_ext = er32(CTRL_EXT);
4850         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4851         ew32(CTRL_EXT, ctrl_ext);
4852
4853         /* Clear all of the statistics registers (clear on read).  It is
4854          * important that we do this after we have tried to establish link
4855          * because the symbol error count will increment wildly if there
4856          * is no link.
4857          */
4858         e1000_clear_hw_cntrs_ich8lan(hw);
4859
4860         return ret_val;
4861 }
4862
4863 /**
4864  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4865  *  @hw: pointer to the HW structure
4866  *
4867  *  Sets/Clears required hardware bits necessary for correctly setting up the
4868  *  hardware for transmit and receive.
4869  **/
4870 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4871 {
4872         u32 reg;
4873
4874         /* Extended Device Control */
4875         reg = er32(CTRL_EXT);
4876         reg |= BIT(22);
4877         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4878         if (hw->mac.type >= e1000_pchlan)
4879                 reg |= E1000_CTRL_EXT_PHYPDEN;
4880         ew32(CTRL_EXT, reg);
4881
4882         /* Transmit Descriptor Control 0 */
4883         reg = er32(TXDCTL(0));
4884         reg |= BIT(22);
4885         ew32(TXDCTL(0), reg);
4886
4887         /* Transmit Descriptor Control 1 */
4888         reg = er32(TXDCTL(1));
4889         reg |= BIT(22);
4890         ew32(TXDCTL(1), reg);
4891
4892         /* Transmit Arbitration Control 0 */
4893         reg = er32(TARC(0));
4894         if (hw->mac.type == e1000_ich8lan)
4895                 reg |= BIT(28) | BIT(29);
4896         reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4897         ew32(TARC(0), reg);
4898
4899         /* Transmit Arbitration Control 1 */
4900         reg = er32(TARC(1));
4901         if (er32(TCTL) & E1000_TCTL_MULR)
4902                 reg &= ~BIT(28);
4903         else
4904                 reg |= BIT(28);
4905         reg |= BIT(24) | BIT(26) | BIT(30);
4906         ew32(TARC(1), reg);
4907
4908         /* Device Status */
4909         if (hw->mac.type == e1000_ich8lan) {
4910                 reg = er32(STATUS);
4911                 reg &= ~BIT(31);
4912                 ew32(STATUS, reg);
4913         }
4914
4915         /* work-around descriptor data corruption issue during nfs v2 udp
4916          * traffic, just disable the nfs filtering capability
4917          */
4918         reg = er32(RFCTL);
4919         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4920
4921         /* Disable IPv6 extension header parsing because some malformed
4922          * IPv6 headers can hang the Rx.
4923          */
4924         if (hw->mac.type == e1000_ich8lan)
4925                 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4926         ew32(RFCTL, reg);
4927
4928         /* Enable ECC on Lynxpoint */
4929         if (hw->mac.type >= e1000_pch_lpt) {
4930                 reg = er32(PBECCSTS);
4931                 reg |= E1000_PBECCSTS_ECC_ENABLE;
4932                 ew32(PBECCSTS, reg);
4933
4934                 reg = er32(CTRL);
4935                 reg |= E1000_CTRL_MEHE;
4936                 ew32(CTRL, reg);
4937         }
4938 }
4939
4940 /**
4941  *  e1000_setup_link_ich8lan - Setup flow control and link settings
4942  *  @hw: pointer to the HW structure
4943  *
4944  *  Determines which flow control settings to use, then configures flow
4945  *  control.  Calls the appropriate media-specific link configuration
4946  *  function.  Assuming the adapter has a valid link partner, a valid link
4947  *  should be established.  Assumes the hardware has previously been reset
4948  *  and the transmitter and receiver are not enabled.
4949  **/
4950 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4951 {
4952         s32 ret_val;
4953
4954         if (hw->phy.ops.check_reset_block(hw))
4955                 return 0;
4956
4957         /* ICH parts do not have a word in the NVM to determine
4958          * the default flow control setting, so we explicitly
4959          * set it to full.
4960          */
4961         if (hw->fc.requested_mode == e1000_fc_default) {
4962                 /* Workaround h/w hang when Tx flow control enabled */
4963                 if (hw->mac.type == e1000_pchlan)
4964                         hw->fc.requested_mode = e1000_fc_rx_pause;
4965                 else
4966                         hw->fc.requested_mode = e1000_fc_full;
4967         }
4968
4969         /* Save off the requested flow control mode for use later.  Depending
4970          * on the link partner's capabilities, we may or may not use this mode.
4971          */
4972         hw->fc.current_mode = hw->fc.requested_mode;
4973
4974         e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4975
4976         /* Continue to configure the copper link. */
4977         ret_val = hw->mac.ops.setup_physical_interface(hw);
4978         if (ret_val)
4979                 return ret_val;
4980
4981         ew32(FCTTV, hw->fc.pause_time);
4982         if ((hw->phy.type == e1000_phy_82578) ||
4983             (hw->phy.type == e1000_phy_82579) ||
4984             (hw->phy.type == e1000_phy_i217) ||
4985             (hw->phy.type == e1000_phy_82577)) {
4986                 ew32(FCRTV_PCH, hw->fc.refresh_time);
4987
4988                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4989                                    hw->fc.pause_time);
4990                 if (ret_val)
4991                         return ret_val;
4992         }
4993
4994         return e1000e_set_fc_watermarks(hw);
4995 }
4996
4997 /**
4998  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4999  *  @hw: pointer to the HW structure
5000  *
5001  *  Configures the kumeran interface to the PHY to wait the appropriate time
5002  *  when polling the PHY, then call the generic setup_copper_link to finish
5003  *  configuring the copper link.
5004  **/
5005 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5006 {
5007         u32 ctrl;
5008         s32 ret_val;
5009         u16 reg_data;
5010
5011         ctrl = er32(CTRL);
5012         ctrl |= E1000_CTRL_SLU;
5013         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5014         ew32(CTRL, ctrl);
5015
5016         /* Set the mac to wait the maximum time between each iteration
5017          * and increase the max iterations when polling the phy;
5018          * this fixes erroneous timeouts at 10Mbps.
5019          */
5020         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5021         if (ret_val)
5022                 return ret_val;
5023         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5024                                        &reg_data);
5025         if (ret_val)
5026                 return ret_val;
5027         reg_data |= 0x3F;
5028         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5029                                         reg_data);
5030         if (ret_val)
5031                 return ret_val;
5032
5033         switch (hw->phy.type) {
5034         case e1000_phy_igp_3:
5035                 ret_val = e1000e_copper_link_setup_igp(hw);
5036                 if (ret_val)
5037                         return ret_val;
5038                 break;
5039         case e1000_phy_bm:
5040         case e1000_phy_82578:
5041                 ret_val = e1000e_copper_link_setup_m88(hw);
5042                 if (ret_val)
5043                         return ret_val;
5044                 break;
5045         case e1000_phy_82577:
5046         case e1000_phy_82579:
5047                 ret_val = e1000_copper_link_setup_82577(hw);
5048                 if (ret_val)
5049                         return ret_val;
5050                 break;
5051         case e1000_phy_ife:
5052                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
5053                 if (ret_val)
5054                         return ret_val;
5055
5056                 reg_data &= ~IFE_PMC_AUTO_MDIX;
5057
5058                 switch (hw->phy.mdix) {
5059                 case 1:
5060                         reg_data &= ~IFE_PMC_FORCE_MDIX;
5061                         break;
5062                 case 2:
5063                         reg_data |= IFE_PMC_FORCE_MDIX;
5064                         break;
5065                 case 0:
5066                 default:
5067                         reg_data |= IFE_PMC_AUTO_MDIX;
5068                         break;
5069                 }
5070                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5071                 if (ret_val)
5072                         return ret_val;
5073                 break;
5074         default:
5075                 break;
5076         }
5077
5078         return e1000e_setup_copper_link(hw);
5079 }
5080
5081 /**
5082  *  e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5083  *  @hw: pointer to the HW structure
5084  *
5085  *  Calls the PHY specific link setup function and then calls the
5086  *  generic setup_copper_link to finish configuring the link for
5087  *  Lynxpoint PCH devices
5088  **/
5089 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5090 {
5091         u32 ctrl;
5092         s32 ret_val;
5093
5094         ctrl = er32(CTRL);
5095         ctrl |= E1000_CTRL_SLU;
5096         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5097         ew32(CTRL, ctrl);
5098
5099         ret_val = e1000_copper_link_setup_82577(hw);
5100         if (ret_val)
5101                 return ret_val;
5102
5103         return e1000e_setup_copper_link(hw);
5104 }
5105
5106 /**
5107  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5108  *  @hw: pointer to the HW structure
5109  *  @speed: pointer to store current link speed
5110  *  @duplex: pointer to store the current link duplex
5111  *
5112  *  Calls the generic get_speed_and_duplex to retrieve the current link
5113  *  information and then calls the Kumeran lock loss workaround for links at
5114  *  gigabit speeds.
5115  **/
5116 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5117                                           u16 *duplex)
5118 {
5119         s32 ret_val;
5120
5121         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5122         if (ret_val)
5123                 return ret_val;
5124
5125         if ((hw->mac.type == e1000_ich8lan) &&
5126             (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5127                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5128         }
5129
5130         return ret_val;
5131 }
5132
5133 /**
5134  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5135  *  @hw: pointer to the HW structure
5136  *
5137  *  Work-around for 82566 Kumeran PCS lock loss:
5138  *  On link status change (i.e. PCI reset, speed change) and link is up and
5139  *  speed is gigabit-
5140  *    0) if workaround is optionally disabled do nothing
5141  *    1) wait 1ms for Kumeran link to come up
5142  *    2) check Kumeran Diagnostic register PCS lock loss bit
5143  *    3) if not set the link is locked (all is good), otherwise...
5144  *    4) reset the PHY
5145  *    5) repeat up to 10 times
5146  *  Note: this is only called for IGP3 copper when speed is 1gb.
5147  **/
5148 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5149 {
5150         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5151         u32 phy_ctrl;
5152         s32 ret_val;
5153         u16 i, data;
5154         bool link;
5155
5156         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5157                 return 0;
5158
5159         /* Make sure link is up before proceeding.  If not just return.
5160          * Attempting this while link is negotiating fouled up link
5161          * stability
5162          */
5163         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5164         if (!link)
5165                 return 0;
5166
5167         for (i = 0; i < 10; i++) {
5168                 /* read once to clear */
5169                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5170                 if (ret_val)
5171                         return ret_val;
5172                 /* and again to get new status */
5173                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5174                 if (ret_val)
5175                         return ret_val;
5176
5177                 /* check for PCS lock */
5178                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5179                         return 0;
5180
5181                 /* Issue PHY reset */
5182                 e1000_phy_hw_reset(hw);
5183                 mdelay(5);
5184         }
5185         /* Disable GigE link negotiation */
5186         phy_ctrl = er32(PHY_CTRL);
5187         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5188                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5189         ew32(PHY_CTRL, phy_ctrl);
5190
5191         /* Call gig speed drop workaround on Gig disable before accessing
5192          * any PHY registers
5193          */
5194         e1000e_gig_downshift_workaround_ich8lan(hw);
5195
5196         /* unable to acquire PCS lock */
5197         return -E1000_ERR_PHY;
5198 }
5199
5200 /**
5201  *  e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5202  *  @hw: pointer to the HW structure
5203  *  @state: boolean value used to set the current Kumeran workaround state
5204  *
5205  *  If ICH8, set the current Kumeran workaround state (enabled - true
5206  *  /disabled - false).
5207  **/
5208 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5209                                                   bool state)
5210 {
5211         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5212
5213         if (hw->mac.type != e1000_ich8lan) {
5214                 e_dbg("Workaround applies to ICH8 only.\n");
5215                 return;
5216         }
5217
5218         dev_spec->kmrn_lock_loss_workaround_enabled = state;
5219 }
5220
5221 /**
5222  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5223  *  @hw: pointer to the HW structure
5224  *
5225  *  Workaround for 82566 power-down on D3 entry:
5226  *    1) disable gigabit link
5227  *    2) write VR power-down enable
5228  *    3) read it back
5229  *  Continue if successful, else issue LCD reset and repeat
5230  **/
5231 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5232 {
5233         u32 reg;
5234         u16 data;
5235         u8 retry = 0;
5236
5237         if (hw->phy.type != e1000_phy_igp_3)
5238                 return;
5239
5240         /* Try the workaround twice (if needed) */
5241         do {
5242                 /* Disable link */
5243                 reg = er32(PHY_CTRL);
5244                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5245                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5246                 ew32(PHY_CTRL, reg);
5247
5248                 /* Call gig speed drop workaround on Gig disable before
5249                  * accessing any PHY registers
5250                  */
5251                 if (hw->mac.type == e1000_ich8lan)
5252                         e1000e_gig_downshift_workaround_ich8lan(hw);
5253
5254                 /* Write VR power-down enable */
5255                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5256                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5257                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5258
5259                 /* Read it back and test */
5260                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5261                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5262                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5263                         break;
5264
5265                 /* Issue PHY reset and repeat at most one more time */
5266                 reg = er32(CTRL);
5267                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5268                 retry++;
5269         } while (retry);
5270 }
5271
5272 /**
5273  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5274  *  @hw: pointer to the HW structure
5275  *
5276  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5277  *  LPLU, Gig disable, MDIC PHY reset):
5278  *    1) Set Kumeran Near-end loopback
5279  *    2) Clear Kumeran Near-end loopback
5280  *  Should only be called for ICH8[m] devices with any 1G Phy.
5281  **/
5282 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5283 {
5284         s32 ret_val;
5285         u16 reg_data;
5286
5287         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5288                 return;
5289
5290         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5291                                        &reg_data);
5292         if (ret_val)
5293                 return;
5294         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5295         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5296                                         reg_data);
5297         if (ret_val)
5298                 return;
5299         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5300         e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5301 }
5302
5303 /**
5304  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5305  *  @hw: pointer to the HW structure
5306  *
5307  *  During S0 to Sx transition, it is possible the link remains at gig
5308  *  instead of negotiating to a lower speed.  Before going to Sx, set
5309  *  'Gig Disable' to force link speed negotiation to a lower speed based on
5310  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
5311  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5312  *  needs to be written.
5313  *  Parts that support (and are linked to a partner which support) EEE in
5314  *  100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5315  *  than 10Mbps w/o EEE.
5316  **/
5317 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5318 {
5319         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5320         u32 phy_ctrl;
5321         s32 ret_val;
5322
5323         phy_ctrl = er32(PHY_CTRL);
5324         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5325
5326         if (hw->phy.type == e1000_phy_i217) {
5327                 u16 phy_reg, device_id = hw->adapter->pdev->device;
5328
5329                 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5330                     (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5331                     (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5332                     (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5333                     (hw->mac.type >= e1000_pch_spt)) {
5334                         u32 fextnvm6 = er32(FEXTNVM6);
5335
5336                         ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5337                 }
5338
5339                 ret_val = hw->phy.ops.acquire(hw);
5340                 if (ret_val)
5341                         goto out;
5342
5343                 if (!dev_spec->eee_disable) {
5344                         u16 eee_advert;
5345
5346                         ret_val =
5347                             e1000_read_emi_reg_locked(hw,
5348                                                       I217_EEE_ADVERTISEMENT,
5349                                                       &eee_advert);
5350                         if (ret_val)
5351                                 goto release;
5352
5353                         /* Disable LPLU if both link partners support 100BaseT
5354                          * EEE and 100Full is advertised on both ends of the
5355                          * link, and enable Auto Enable LPI since there will
5356                          * be no driver to enable LPI while in Sx.
5357                          */
5358                         if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5359                             (dev_spec->eee_lp_ability &
5360                              I82579_EEE_100_SUPPORTED) &&
5361                             (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5362                                 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5363                                               E1000_PHY_CTRL_NOND0A_LPLU);
5364
5365                                 /* Set Auto Enable LPI after link up */
5366                                 e1e_rphy_locked(hw,
5367                                                 I217_LPI_GPIO_CTRL, &phy_reg);
5368                                 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5369                                 e1e_wphy_locked(hw,
5370                                                 I217_LPI_GPIO_CTRL, phy_reg);
5371                         }
5372                 }
5373
5374                 /* For i217 Intel Rapid Start Technology support,
5375                  * when the system is going into Sx and no manageability engine
5376                  * is present, the driver must configure proxy to reset only on
5377                  * power good.  LPI (Low Power Idle) state must also reset only
5378                  * on power good, as well as the MTA (Multicast table array).
5379                  * The SMBus release must also be disabled on LCD reset.
5380                  */
5381                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5382                         /* Enable proxy to reset only on power good. */
5383                         e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5384                         phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5385                         e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5386
5387                         /* Set bit enable LPI (EEE) to reset only on
5388                          * power good.
5389                          */
5390                         e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5391                         phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5392                         e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5393
5394                         /* Disable the SMB release on LCD reset. */
5395                         e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5396                         phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5397                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5398                 }
5399
5400                 /* Enable MTA to reset for Intel Rapid Start Technology
5401                  * Support
5402                  */
5403                 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5404                 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5405                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5406
5407 release:
5408                 hw->phy.ops.release(hw);
5409         }
5410 out:
5411         ew32(PHY_CTRL, phy_ctrl);
5412
5413         if (hw->mac.type == e1000_ich8lan)
5414                 e1000e_gig_downshift_workaround_ich8lan(hw);
5415
5416         if (hw->mac.type >= e1000_pchlan) {
5417                 e1000_oem_bits_config_ich8lan(hw, false);
5418
5419                 /* Reset PHY to activate OEM bits on 82577/8 */
5420                 if (hw->mac.type == e1000_pchlan)
5421                         e1000e_phy_hw_reset_generic(hw);
5422
5423                 ret_val = hw->phy.ops.acquire(hw);
5424                 if (ret_val)
5425                         return;
5426                 e1000_write_smbus_addr(hw);
5427                 hw->phy.ops.release(hw);
5428         }
5429 }
5430
5431 /**
5432  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5433  *  @hw: pointer to the HW structure
5434  *
5435  *  During Sx to S0 transitions on non-managed devices or managed devices
5436  *  on which PHY resets are not blocked, if the PHY registers cannot be
5437  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
5438  *  the PHY.
5439  *  On i217, setup Intel Rapid Start Technology.
5440  **/
5441 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5442 {
5443         s32 ret_val;
5444
5445         if (hw->mac.type < e1000_pch2lan)
5446                 return;
5447
5448         ret_val = e1000_init_phy_workarounds_pchlan(hw);
5449         if (ret_val) {
5450                 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5451                 return;
5452         }
5453
5454         /* For i217 Intel Rapid Start Technology support when the system
5455          * is transitioning from Sx and no manageability engine is present
5456          * configure SMBus to restore on reset, disable proxy, and enable
5457          * the reset on MTA (Multicast table array).
5458          */
5459         if (hw->phy.type == e1000_phy_i217) {
5460                 u16 phy_reg;
5461
5462                 ret_val = hw->phy.ops.acquire(hw);
5463                 if (ret_val) {
5464                         e_dbg("Failed to setup iRST\n");
5465                         return;
5466                 }
5467
5468                 /* Clear Auto Enable LPI after link up */
5469                 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5470                 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5471                 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5472
5473                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5474                         /* Restore clear on SMB if no manageability engine
5475                          * is present
5476                          */
5477                         ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5478                         if (ret_val)
5479                                 goto release;
5480                         phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5481                         e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5482
5483                         /* Disable Proxy */
5484                         e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5485                 }
5486                 /* Enable reset on MTA */
5487                 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5488                 if (ret_val)
5489                         goto release;
5490                 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5491                 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5492 release:
5493                 if (ret_val)
5494                         e_dbg("Error %d in resume workarounds\n", ret_val);
5495                 hw->phy.ops.release(hw);
5496         }
5497 }
5498
5499 /**
5500  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
5501  *  @hw: pointer to the HW structure
5502  *
5503  *  Return the LED back to the default configuration.
5504  **/
5505 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5506 {
5507         if (hw->phy.type == e1000_phy_ife)
5508                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5509
5510         ew32(LEDCTL, hw->mac.ledctl_default);
5511         return 0;
5512 }
5513
5514 /**
5515  *  e1000_led_on_ich8lan - Turn LEDs on
5516  *  @hw: pointer to the HW structure
5517  *
5518  *  Turn on the LEDs.
5519  **/
5520 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5521 {
5522         if (hw->phy.type == e1000_phy_ife)
5523                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5524                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5525
5526         ew32(LEDCTL, hw->mac.ledctl_mode2);
5527         return 0;
5528 }
5529
5530 /**
5531  *  e1000_led_off_ich8lan - Turn LEDs off
5532  *  @hw: pointer to the HW structure
5533  *
5534  *  Turn off the LEDs.
5535  **/
5536 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5537 {
5538         if (hw->phy.type == e1000_phy_ife)
5539                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5540                                 (IFE_PSCL_PROBE_MODE |
5541                                  IFE_PSCL_PROBE_LEDS_OFF));
5542
5543         ew32(LEDCTL, hw->mac.ledctl_mode1);
5544         return 0;
5545 }
5546
5547 /**
5548  *  e1000_setup_led_pchlan - Configures SW controllable LED
5549  *  @hw: pointer to the HW structure
5550  *
5551  *  This prepares the SW controllable LED for use.
5552  **/
5553 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5554 {
5555         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5556 }
5557
5558 /**
5559  *  e1000_cleanup_led_pchlan - Restore the default LED operation
5560  *  @hw: pointer to the HW structure
5561  *
5562  *  Return the LED back to the default configuration.
5563  **/
5564 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5565 {
5566         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5567 }
5568
5569 /**
5570  *  e1000_led_on_pchlan - Turn LEDs on
5571  *  @hw: pointer to the HW structure
5572  *
5573  *  Turn on the LEDs.
5574  **/
5575 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5576 {
5577         u16 data = (u16)hw->mac.ledctl_mode2;
5578         u32 i, led;
5579
5580         /* If no link, then turn LED on by setting the invert bit
5581          * for each LED that's mode is "link_up" in ledctl_mode2.
5582          */
5583         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5584                 for (i = 0; i < 3; i++) {
5585                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5586                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5587                             E1000_LEDCTL_MODE_LINK_UP)
5588                                 continue;
5589                         if (led & E1000_PHY_LED0_IVRT)
5590                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5591                         else
5592                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5593                 }
5594         }
5595
5596         return e1e_wphy(hw, HV_LED_CONFIG, data);
5597 }
5598
5599 /**
5600  *  e1000_led_off_pchlan - Turn LEDs off
5601  *  @hw: pointer to the HW structure
5602  *
5603  *  Turn off the LEDs.
5604  **/
5605 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5606 {
5607         u16 data = (u16)hw->mac.ledctl_mode1;
5608         u32 i, led;
5609
5610         /* If no link, then turn LED off by clearing the invert bit
5611          * for each LED that's mode is "link_up" in ledctl_mode1.
5612          */
5613         if (!(er32(STATUS) & E1000_STATUS_LU)) {
5614                 for (i = 0; i < 3; i++) {
5615                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5616                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
5617                             E1000_LEDCTL_MODE_LINK_UP)
5618                                 continue;
5619                         if (led & E1000_PHY_LED0_IVRT)
5620                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5621                         else
5622                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5623                 }
5624         }
5625
5626         return e1e_wphy(hw, HV_LED_CONFIG, data);
5627 }
5628
5629 /**
5630  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5631  *  @hw: pointer to the HW structure
5632  *
5633  *  Read appropriate register for the config done bit for completion status
5634  *  and configure the PHY through s/w for EEPROM-less parts.
5635  *
5636  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
5637  *  config done bit, so only an error is logged and continues.  If we were
5638  *  to return with error, EEPROM-less silicon would not be able to be reset
5639  *  or change link.
5640  **/
5641 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5642 {
5643         s32 ret_val = 0;
5644         u32 bank = 0;
5645         u32 status;
5646
5647         e1000e_get_cfg_done_generic(hw);
5648
5649         /* Wait for indication from h/w that it has completed basic config */
5650         if (hw->mac.type >= e1000_ich10lan) {
5651                 e1000_lan_init_done_ich8lan(hw);
5652         } else {
5653                 ret_val = e1000e_get_auto_rd_done(hw);
5654                 if (ret_val) {
5655                         /* When auto config read does not complete, do not
5656                          * return with an error. This can happen in situations
5657                          * where there is no eeprom and prevents getting link.
5658                          */
5659                         e_dbg("Auto Read Done did not complete\n");
5660                         ret_val = 0;
5661                 }
5662         }
5663
5664         /* Clear PHY Reset Asserted bit */
5665         status = er32(STATUS);
5666         if (status & E1000_STATUS_PHYRA)
5667                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5668         else
5669                 e_dbg("PHY Reset Asserted not set - needs delay\n");
5670
5671         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5672         if (hw->mac.type <= e1000_ich9lan) {
5673                 if (!(er32(EECD) & E1000_EECD_PRES) &&
5674                     (hw->phy.type == e1000_phy_igp_3)) {
5675                         e1000e_phy_init_script_igp3(hw);
5676                 }
5677         } else {
5678                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5679                         /* Maybe we should do a basic PHY config */
5680                         e_dbg("EEPROM not present\n");
5681                         ret_val = -E1000_ERR_CONFIG;
5682                 }
5683         }
5684
5685         return ret_val;
5686 }
5687
5688 /**
5689  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5690  * @hw: pointer to the HW structure
5691  *
5692  * In the case of a PHY power down to save power, or to turn off link during a
5693  * driver unload, or wake on lan is not enabled, remove the link.
5694  **/
5695 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5696 {
5697         /* If the management interface is not enabled, then power down */
5698         if (!(hw->mac.ops.check_mng_mode(hw) ||
5699               hw->phy.ops.check_reset_block(hw)))
5700                 e1000_power_down_phy_copper(hw);
5701 }
5702
5703 /**
5704  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5705  *  @hw: pointer to the HW structure
5706  *
5707  *  Clears hardware counters specific to the silicon family and calls
5708  *  clear_hw_cntrs_generic to clear all general purpose counters.
5709  **/
5710 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5711 {
5712         u16 phy_data;
5713         s32 ret_val;
5714
5715         e1000e_clear_hw_cntrs_base(hw);
5716
5717         er32(ALGNERRC);
5718         er32(RXERRC);
5719         er32(TNCRS);
5720         er32(CEXTERR);
5721         er32(TSCTC);
5722         er32(TSCTFC);
5723
5724         er32(MGTPRC);
5725         er32(MGTPDC);
5726         er32(MGTPTC);
5727
5728         er32(IAC);
5729         er32(ICRXOC);
5730
5731         /* Clear PHY statistics registers */
5732         if ((hw->phy.type == e1000_phy_82578) ||
5733             (hw->phy.type == e1000_phy_82579) ||
5734             (hw->phy.type == e1000_phy_i217) ||
5735             (hw->phy.type == e1000_phy_82577)) {
5736                 ret_val = hw->phy.ops.acquire(hw);
5737                 if (ret_val)
5738                         return;
5739                 ret_val = hw->phy.ops.set_page(hw,
5740                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
5741                 if (ret_val)
5742                         goto release;
5743                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5744                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5745                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5746                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5747                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5748                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5749                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5750                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5751                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5752                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5753                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5754                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5755                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5756                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5757 release:
5758                 hw->phy.ops.release(hw);
5759         }
5760 }
5761
5762 static const struct e1000_mac_operations ich8_mac_ops = {
5763         /* check_mng_mode dependent on mac type */
5764         .check_for_link         = e1000_check_for_copper_link_ich8lan,
5765         /* cleanup_led dependent on mac type */
5766         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
5767         .get_bus_info           = e1000_get_bus_info_ich8lan,
5768         .set_lan_id             = e1000_set_lan_id_single_port,
5769         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
5770         /* led_on dependent on mac type */
5771         /* led_off dependent on mac type */
5772         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
5773         .reset_hw               = e1000_reset_hw_ich8lan,
5774         .init_hw                = e1000_init_hw_ich8lan,
5775         .setup_link             = e1000_setup_link_ich8lan,
5776         .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5777         /* id_led_init dependent on mac type */
5778         .config_collision_dist  = e1000e_config_collision_dist_generic,
5779         .rar_set                = e1000e_rar_set_generic,
5780         .rar_get_count          = e1000e_rar_get_count_generic,
5781 };
5782
5783 static const struct e1000_phy_operations ich8_phy_ops = {
5784         .acquire                = e1000_acquire_swflag_ich8lan,
5785         .check_reset_block      = e1000_check_reset_block_ich8lan,
5786         .commit                 = NULL,
5787         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
5788         .get_cable_length       = e1000e_get_cable_length_igp_2,
5789         .read_reg               = e1000e_read_phy_reg_igp,
5790         .release                = e1000_release_swflag_ich8lan,
5791         .reset                  = e1000_phy_hw_reset_ich8lan,
5792         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
5793         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
5794         .write_reg              = e1000e_write_phy_reg_igp,
5795 };
5796
5797 static const struct e1000_nvm_operations ich8_nvm_ops = {
5798         .acquire                = e1000_acquire_nvm_ich8lan,
5799         .read                   = e1000_read_nvm_ich8lan,
5800         .release                = e1000_release_nvm_ich8lan,
5801         .reload                 = e1000e_reload_nvm_generic,
5802         .update                 = e1000_update_nvm_checksum_ich8lan,
5803         .valid_led_default      = e1000_valid_led_default_ich8lan,
5804         .validate               = e1000_validate_nvm_checksum_ich8lan,
5805         .write                  = e1000_write_nvm_ich8lan,
5806 };
5807
5808 static const struct e1000_nvm_operations spt_nvm_ops = {
5809         .acquire                = e1000_acquire_nvm_ich8lan,
5810         .release                = e1000_release_nvm_ich8lan,
5811         .read                   = e1000_read_nvm_spt,
5812         .update                 = e1000_update_nvm_checksum_spt,
5813         .reload                 = e1000e_reload_nvm_generic,
5814         .valid_led_default      = e1000_valid_led_default_ich8lan,
5815         .validate               = e1000_validate_nvm_checksum_ich8lan,
5816         .write                  = e1000_write_nvm_ich8lan,
5817 };
5818
5819 const struct e1000_info e1000_ich8_info = {
5820         .mac                    = e1000_ich8lan,
5821         .flags                  = FLAG_HAS_WOL
5822                                   | FLAG_IS_ICH
5823                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5824                                   | FLAG_HAS_AMT
5825                                   | FLAG_HAS_FLASH
5826                                   | FLAG_APME_IN_WUC,
5827         .pba                    = 8,
5828         .max_hw_frame_size      = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5829         .get_variants           = e1000_get_variants_ich8lan,
5830         .mac_ops                = &ich8_mac_ops,
5831         .phy_ops                = &ich8_phy_ops,
5832         .nvm_ops                = &ich8_nvm_ops,
5833 };
5834
5835 const struct e1000_info e1000_ich9_info = {
5836         .mac                    = e1000_ich9lan,
5837         .flags                  = FLAG_HAS_JUMBO_FRAMES
5838                                   | FLAG_IS_ICH
5839                                   | FLAG_HAS_WOL
5840                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5841                                   | FLAG_HAS_AMT
5842                                   | FLAG_HAS_FLASH
5843                                   | FLAG_APME_IN_WUC,
5844         .pba                    = 18,
5845         .max_hw_frame_size      = DEFAULT_JUMBO,
5846         .get_variants           = e1000_get_variants_ich8lan,
5847         .mac_ops                = &ich8_mac_ops,
5848         .phy_ops                = &ich8_phy_ops,
5849         .nvm_ops                = &ich8_nvm_ops,
5850 };
5851
5852 const struct e1000_info e1000_ich10_info = {
5853         .mac                    = e1000_ich10lan,
5854         .flags                  = FLAG_HAS_JUMBO_FRAMES
5855                                   | FLAG_IS_ICH
5856                                   | FLAG_HAS_WOL
5857                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5858                                   | FLAG_HAS_AMT
5859                                   | FLAG_HAS_FLASH
5860                                   | FLAG_APME_IN_WUC,
5861         .pba                    = 18,
5862         .max_hw_frame_size      = DEFAULT_JUMBO,
5863         .get_variants           = e1000_get_variants_ich8lan,
5864         .mac_ops                = &ich8_mac_ops,
5865         .phy_ops                = &ich8_phy_ops,
5866         .nvm_ops                = &ich8_nvm_ops,
5867 };
5868
5869 const struct e1000_info e1000_pch_info = {
5870         .mac                    = e1000_pchlan,
5871         .flags                  = FLAG_IS_ICH
5872                                   | FLAG_HAS_WOL
5873                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5874                                   | FLAG_HAS_AMT
5875                                   | FLAG_HAS_FLASH
5876                                   | FLAG_HAS_JUMBO_FRAMES
5877                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5878                                   | FLAG_APME_IN_WUC,
5879         .flags2                 = FLAG2_HAS_PHY_STATS,
5880         .pba                    = 26,
5881         .max_hw_frame_size      = 4096,
5882         .get_variants           = e1000_get_variants_ich8lan,
5883         .mac_ops                = &ich8_mac_ops,
5884         .phy_ops                = &ich8_phy_ops,
5885         .nvm_ops                = &ich8_nvm_ops,
5886 };
5887
5888 const struct e1000_info e1000_pch2_info = {
5889         .mac                    = e1000_pch2lan,
5890         .flags                  = FLAG_IS_ICH
5891                                   | FLAG_HAS_WOL
5892                                   | FLAG_HAS_HW_TIMESTAMP
5893                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5894                                   | FLAG_HAS_AMT
5895                                   | FLAG_HAS_FLASH
5896                                   | FLAG_HAS_JUMBO_FRAMES
5897                                   | FLAG_APME_IN_WUC,
5898         .flags2                 = FLAG2_HAS_PHY_STATS
5899                                   | FLAG2_HAS_EEE
5900                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
5901         .pba                    = 26,
5902         .max_hw_frame_size      = 9022,
5903         .get_variants           = e1000_get_variants_ich8lan,
5904         .mac_ops                = &ich8_mac_ops,
5905         .phy_ops                = &ich8_phy_ops,
5906         .nvm_ops                = &ich8_nvm_ops,
5907 };
5908
5909 const struct e1000_info e1000_pch_lpt_info = {
5910         .mac                    = e1000_pch_lpt,
5911         .flags                  = FLAG_IS_ICH
5912                                   | FLAG_HAS_WOL
5913                                   | FLAG_HAS_HW_TIMESTAMP
5914                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5915                                   | FLAG_HAS_AMT
5916                                   | FLAG_HAS_FLASH
5917                                   | FLAG_HAS_JUMBO_FRAMES
5918                                   | FLAG_APME_IN_WUC,
5919         .flags2                 = FLAG2_HAS_PHY_STATS
5920                                   | FLAG2_HAS_EEE
5921                                   | FLAG2_CHECK_SYSTIM_OVERFLOW,
5922         .pba                    = 26,
5923         .max_hw_frame_size      = 9022,
5924         .get_variants           = e1000_get_variants_ich8lan,
5925         .mac_ops                = &ich8_mac_ops,
5926         .phy_ops                = &ich8_phy_ops,
5927         .nvm_ops                = &ich8_nvm_ops,
5928 };
5929
5930 const struct e1000_info e1000_pch_spt_info = {
5931         .mac                    = e1000_pch_spt,
5932         .flags                  = FLAG_IS_ICH
5933                                   | FLAG_HAS_WOL
5934                                   | FLAG_HAS_HW_TIMESTAMP
5935                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5936                                   | FLAG_HAS_AMT
5937                                   | FLAG_HAS_FLASH
5938                                   | FLAG_HAS_JUMBO_FRAMES
5939                                   | FLAG_APME_IN_WUC,
5940         .flags2                 = FLAG2_HAS_PHY_STATS
5941                                   | FLAG2_HAS_EEE,
5942         .pba                    = 26,
5943         .max_hw_frame_size      = 9022,
5944         .get_variants           = e1000_get_variants_ich8lan,
5945         .mac_ops                = &ich8_mac_ops,
5946         .phy_ops                = &ich8_phy_ops,
5947         .nvm_ops                = &spt_nvm_ops,
5948 };
5949
5950 const struct e1000_info e1000_pch_cnp_info = {
5951         .mac                    = e1000_pch_cnp,
5952         .flags                  = FLAG_IS_ICH
5953                                   | FLAG_HAS_WOL
5954                                   | FLAG_HAS_HW_TIMESTAMP
5955                                   | FLAG_HAS_CTRLEXT_ON_LOAD
5956                                   | FLAG_HAS_AMT
5957                                   | FLAG_HAS_FLASH
5958                                   | FLAG_HAS_JUMBO_FRAMES
5959                                   | FLAG_APME_IN_WUC,
5960         .flags2                 = FLAG2_HAS_PHY_STATS
5961                                   | FLAG2_HAS_EEE,
5962         .pba                    = 26,
5963         .max_hw_frame_size      = 9022,
5964         .get_variants           = e1000_get_variants_ich8lan,
5965         .mac_ops                = &ich8_mac_ops,
5966         .phy_ops                = &ich8_phy_ops,
5967         .nvm_ops                = &spt_nvm_ops,
5968 };