1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2015 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 /* 82562G 10/100 Network Connection
23 * 82562G-2 10/100 Network Connection
24 * 82562GT 10/100 Network Connection
25 * 82562GT-2 10/100 Network Connection
26 * 82562V 10/100 Network Connection
27 * 82562V-2 10/100 Network Connection
28 * 82566DC-2 Gigabit Network Connection
29 * 82566DC Gigabit Network Connection
30 * 82566DM-2 Gigabit Network Connection
31 * 82566DM Gigabit Network Connection
32 * 82566MC Gigabit Network Connection
33 * 82566MM Gigabit Network Connection
34 * 82567LM Gigabit Network Connection
35 * 82567LF Gigabit Network Connection
36 * 82567V Gigabit Network Connection
37 * 82567LM-2 Gigabit Network Connection
38 * 82567LF-2 Gigabit Network Connection
39 * 82567V-2 Gigabit Network Connection
40 * 82567LF-3 Gigabit Network Connection
41 * 82567LM-3 Gigabit Network Connection
42 * 82567LM-4 Gigabit Network Connection
43 * 82577LM Gigabit Network Connection
44 * 82577LC Gigabit Network Connection
45 * 82578DM Gigabit Network Connection
46 * 82578DC Gigabit Network Connection
47 * 82579LM Gigabit Network Connection
48 * 82579V Gigabit Network Connection
49 * Ethernet Connection I217-LM
50 * Ethernet Connection I217-V
51 * Ethernet Connection I218-V
52 * Ethernet Connection I218-LM
53 * Ethernet Connection (2) I218-LM
54 * Ethernet Connection (2) I218-V
55 * Ethernet Connection (3) I218-LM
56 * Ethernet Connection (3) I218-V
61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
62 /* Offset 04h HSFSTS */
63 union ich8_hws_flash_status {
65 u16 flcdone:1; /* bit 0 Flash Cycle Done */
66 u16 flcerr:1; /* bit 1 Flash Cycle Error */
67 u16 dael:1; /* bit 2 Direct Access error Log */
68 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
69 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
70 u16 reserved1:2; /* bit 13:6 Reserved */
71 u16 reserved2:6; /* bit 13:6 Reserved */
72 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
73 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
79 /* Offset 06h FLCTL */
80 union ich8_hws_flash_ctrl {
82 u16 flcgo:1; /* 0 Flash Cycle Go */
83 u16 flcycle:2; /* 2:1 Flash Cycle */
84 u16 reserved:5; /* 7:3 Reserved */
85 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
86 u16 flockdn:6; /* 15:10 Reserved */
91 /* ICH Flash Region Access Permissions */
92 union ich8_hws_flash_regacc {
94 u32 grra:8; /* 0:7 GbE region Read Access */
95 u32 grwa:8; /* 8:15 GbE region Write Access */
96 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
97 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
102 /* ICH Flash Protected Region */
103 union ich8_flash_protected_range {
105 u32 base:13; /* 0:12 Protected Range Base */
106 u32 reserved1:2; /* 13:14 Reserved */
107 u32 rpe:1; /* 15 Read Protection Enable */
108 u32 limit:13; /* 16:28 Protected Range Limit */
109 u32 reserved2:2; /* 29:30 Reserved */
110 u32 wpe:1; /* 31 Write Protection Enable */
115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
119 u32 offset, u8 byte);
120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
126 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
128 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
129 u32 offset, u32 *data);
130 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
131 u32 offset, u32 data);
132 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
133 u32 offset, u32 dword);
134 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
135 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
136 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
137 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
138 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
139 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
140 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
141 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
142 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
143 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
144 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
145 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
146 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
147 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
148 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
149 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
150 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
151 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
152 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
153 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
154 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
155 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
156 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
157 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
159 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
161 return readw(hw->flash_address + reg);
164 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
166 return readl(hw->flash_address + reg);
169 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
171 writew(val, hw->flash_address + reg);
174 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
176 writel(val, hw->flash_address + reg);
179 #define er16flash(reg) __er16flash(hw, (reg))
180 #define er32flash(reg) __er32flash(hw, (reg))
181 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
182 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
185 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
186 * @hw: pointer to the HW structure
188 * Test access to the PHY registers by reading the PHY ID registers. If
189 * the PHY ID is already known (e.g. resume path) compare it with known ID,
190 * otherwise assume the read PHY ID is correct if it is valid.
192 * Assumes the sw/fw/hw semaphore is already acquired.
194 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
202 for (retry_count = 0; retry_count < 2; retry_count++) {
203 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
204 if (ret_val || (phy_reg == 0xFFFF))
206 phy_id = (u32)(phy_reg << 16);
208 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
209 if (ret_val || (phy_reg == 0xFFFF)) {
213 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
218 if (hw->phy.id == phy_id)
222 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
226 /* In case the PHY needs to be in mdio slow mode,
227 * set slow mode and try to get the PHY id again.
229 if (hw->mac.type < e1000_pch_lpt) {
230 hw->phy.ops.release(hw);
231 ret_val = e1000_set_mdio_slow_mode_hv(hw);
233 ret_val = e1000e_get_phy_id(hw);
234 hw->phy.ops.acquire(hw);
240 if (hw->mac.type >= e1000_pch_lpt) {
241 /* Only unforce SMBus if ME is not active */
242 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
243 /* Unforce SMBus mode in PHY */
244 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
245 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
246 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
248 /* Unforce SMBus mode in MAC */
249 mac_reg = er32(CTRL_EXT);
250 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
251 ew32(CTRL_EXT, mac_reg);
259 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
260 * @hw: pointer to the HW structure
262 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
263 * used to reset the PHY to a quiescent state when necessary.
265 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
269 /* Set Phy Config Counter to 50msec */
270 mac_reg = er32(FEXTNVM3);
271 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
272 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
273 ew32(FEXTNVM3, mac_reg);
275 /* Toggle LANPHYPC Value bit */
276 mac_reg = er32(CTRL);
277 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
278 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
281 usleep_range(10, 20);
282 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
286 if (hw->mac.type < e1000_pch_lpt) {
292 usleep_range(5000, 10000);
293 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
300 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
301 * @hw: pointer to the HW structure
303 * Workarounds/flow necessary for PHY initialization during driver load
306 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
308 struct e1000_adapter *adapter = hw->adapter;
309 u32 mac_reg, fwsm = er32(FWSM);
312 /* Gate automatic PHY configuration by hardware on managed and
313 * non-managed 82579 and newer adapters.
315 e1000_gate_hw_phy_config_ich8lan(hw, true);
317 /* It is not possible to be certain of the current state of ULP
318 * so forcibly disable it.
320 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
321 e1000_disable_ulp_lpt_lp(hw, true);
323 ret_val = hw->phy.ops.acquire(hw);
325 e_dbg("Failed to initialize PHY flow\n");
329 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
330 * inaccessible and resetting the PHY is not blocked, toggle the
331 * LANPHYPC Value bit to force the interconnect to PCIe mode.
333 switch (hw->mac.type) {
337 if (e1000_phy_is_accessible_pchlan(hw))
340 /* Before toggling LANPHYPC, see if PHY is accessible by
341 * forcing MAC to SMBus mode first.
343 mac_reg = er32(CTRL_EXT);
344 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
345 ew32(CTRL_EXT, mac_reg);
347 /* Wait 50 milliseconds for MAC to finish any retries
348 * that it might be trying to perform from previous
349 * attempts to acknowledge any phy read requests.
355 if (e1000_phy_is_accessible_pchlan(hw))
360 if ((hw->mac.type == e1000_pchlan) &&
361 (fwsm & E1000_ICH_FWSM_FW_VALID))
364 if (hw->phy.ops.check_reset_block(hw)) {
365 e_dbg("Required LANPHYPC toggle blocked by ME\n");
366 ret_val = -E1000_ERR_PHY;
370 /* Toggle LANPHYPC Value bit */
371 e1000_toggle_lanphypc_pch_lpt(hw);
372 if (hw->mac.type >= e1000_pch_lpt) {
373 if (e1000_phy_is_accessible_pchlan(hw))
376 /* Toggling LANPHYPC brings the PHY out of SMBus mode
377 * so ensure that the MAC is also out of SMBus mode
379 mac_reg = er32(CTRL_EXT);
380 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
381 ew32(CTRL_EXT, mac_reg);
383 if (e1000_phy_is_accessible_pchlan(hw))
386 ret_val = -E1000_ERR_PHY;
393 hw->phy.ops.release(hw);
396 /* Check to see if able to reset PHY. Print error if not */
397 if (hw->phy.ops.check_reset_block(hw)) {
398 e_err("Reset blocked by ME\n");
402 /* Reset the PHY before any access to it. Doing so, ensures
403 * that the PHY is in a known good state before we read/write
404 * PHY registers. The generic reset is sufficient here,
405 * because we haven't determined the PHY type yet.
407 ret_val = e1000e_phy_hw_reset_generic(hw);
411 /* On a successful reset, possibly need to wait for the PHY
412 * to quiesce to an accessible state before returning control
413 * to the calling function. If the PHY does not quiesce, then
414 * return E1000E_BLK_PHY_RESET, as this is the condition that
417 ret_val = hw->phy.ops.check_reset_block(hw);
419 e_err("ME blocked access to PHY after reset\n");
423 /* Ungate automatic PHY configuration on non-managed 82579 */
424 if ((hw->mac.type == e1000_pch2lan) &&
425 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
426 usleep_range(10000, 20000);
427 e1000_gate_hw_phy_config_ich8lan(hw, false);
434 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
435 * @hw: pointer to the HW structure
437 * Initialize family-specific PHY parameters and function pointers.
439 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
441 struct e1000_phy_info *phy = &hw->phy;
445 phy->reset_delay_us = 100;
447 phy->ops.set_page = e1000_set_page_igp;
448 phy->ops.read_reg = e1000_read_phy_reg_hv;
449 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
450 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
451 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
452 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
453 phy->ops.write_reg = e1000_write_phy_reg_hv;
454 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
455 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
456 phy->ops.power_up = e1000_power_up_phy_copper;
457 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
458 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
460 phy->id = e1000_phy_unknown;
462 ret_val = e1000_init_phy_workarounds_pchlan(hw);
466 if (phy->id == e1000_phy_unknown)
467 switch (hw->mac.type) {
469 ret_val = e1000e_get_phy_id(hw);
472 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
479 /* In case the PHY needs to be in mdio slow mode,
480 * set slow mode and try to get the PHY id again.
482 ret_val = e1000_set_mdio_slow_mode_hv(hw);
485 ret_val = e1000e_get_phy_id(hw);
490 phy->type = e1000e_get_phy_type_from_id(phy->id);
493 case e1000_phy_82577:
494 case e1000_phy_82579:
496 phy->ops.check_polarity = e1000_check_polarity_82577;
497 phy->ops.force_speed_duplex =
498 e1000_phy_force_speed_duplex_82577;
499 phy->ops.get_cable_length = e1000_get_cable_length_82577;
500 phy->ops.get_info = e1000_get_phy_info_82577;
501 phy->ops.commit = e1000e_phy_sw_reset;
503 case e1000_phy_82578:
504 phy->ops.check_polarity = e1000_check_polarity_m88;
505 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
506 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
507 phy->ops.get_info = e1000e_get_phy_info_m88;
510 ret_val = -E1000_ERR_PHY;
518 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
519 * @hw: pointer to the HW structure
521 * Initialize family-specific PHY parameters and function pointers.
523 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
525 struct e1000_phy_info *phy = &hw->phy;
530 phy->reset_delay_us = 100;
532 phy->ops.power_up = e1000_power_up_phy_copper;
533 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
535 /* We may need to do this twice - once for IGP and if that fails,
536 * we'll set BM func pointers and try again
538 ret_val = e1000e_determine_phy_address(hw);
540 phy->ops.write_reg = e1000e_write_phy_reg_bm;
541 phy->ops.read_reg = e1000e_read_phy_reg_bm;
542 ret_val = e1000e_determine_phy_address(hw);
544 e_dbg("Cannot determine PHY addr. Erroring out\n");
550 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
552 usleep_range(1000, 2000);
553 ret_val = e1000e_get_phy_id(hw);
560 case IGP03E1000_E_PHY_ID:
561 phy->type = e1000_phy_igp_3;
562 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
563 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
564 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
565 phy->ops.get_info = e1000e_get_phy_info_igp;
566 phy->ops.check_polarity = e1000_check_polarity_igp;
567 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
570 case IFE_PLUS_E_PHY_ID:
572 phy->type = e1000_phy_ife;
573 phy->autoneg_mask = E1000_ALL_NOT_GIG;
574 phy->ops.get_info = e1000_get_phy_info_ife;
575 phy->ops.check_polarity = e1000_check_polarity_ife;
576 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
578 case BME1000_E_PHY_ID:
579 phy->type = e1000_phy_bm;
580 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
581 phy->ops.read_reg = e1000e_read_phy_reg_bm;
582 phy->ops.write_reg = e1000e_write_phy_reg_bm;
583 phy->ops.commit = e1000e_phy_sw_reset;
584 phy->ops.get_info = e1000e_get_phy_info_m88;
585 phy->ops.check_polarity = e1000_check_polarity_m88;
586 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
589 return -E1000_ERR_PHY;
596 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
597 * @hw: pointer to the HW structure
599 * Initialize family-specific NVM parameters and function
602 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
604 struct e1000_nvm_info *nvm = &hw->nvm;
605 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
606 u32 gfpreg, sector_base_addr, sector_end_addr;
610 nvm->type = e1000_nvm_flash_sw;
612 if (hw->mac.type >= e1000_pch_spt) {
613 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
614 * STRAP register. This is because in SPT the GbE Flash region
615 * is no longer accessed through the flash registers. Instead,
616 * the mechanism has changed, and the Flash region access
617 * registers are now implemented in GbE memory space.
619 nvm->flash_base_addr = 0;
620 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
621 * NVM_SIZE_MULTIPLIER;
622 nvm->flash_bank_size = nvm_size / 2;
623 /* Adjust to word count */
624 nvm->flash_bank_size /= sizeof(u16);
625 /* Set the base address for flash register access */
626 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
628 /* Can't read flash registers if register set isn't mapped. */
629 if (!hw->flash_address) {
630 e_dbg("ERROR: Flash registers not mapped\n");
631 return -E1000_ERR_CONFIG;
634 gfpreg = er32flash(ICH_FLASH_GFPREG);
636 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
637 * Add 1 to sector_end_addr since this sector is included in
640 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
641 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
643 /* flash_base_addr is byte-aligned */
644 nvm->flash_base_addr = sector_base_addr
645 << FLASH_SECTOR_ADDR_SHIFT;
647 /* find total size of the NVM, then cut in half since the total
648 * size represents two separate NVM banks.
650 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
651 << FLASH_SECTOR_ADDR_SHIFT);
652 nvm->flash_bank_size /= 2;
653 /* Adjust to word count */
654 nvm->flash_bank_size /= sizeof(u16);
657 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
659 /* Clear shadow ram */
660 for (i = 0; i < nvm->word_size; i++) {
661 dev_spec->shadow_ram[i].modified = false;
662 dev_spec->shadow_ram[i].value = 0xFFFF;
669 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
670 * @hw: pointer to the HW structure
672 * Initialize family-specific MAC parameters and function
675 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
677 struct e1000_mac_info *mac = &hw->mac;
679 /* Set media type function pointer */
680 hw->phy.media_type = e1000_media_type_copper;
682 /* Set mta register count */
683 mac->mta_reg_count = 32;
684 /* Set rar entry count */
685 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
686 if (mac->type == e1000_ich8lan)
687 mac->rar_entry_count--;
689 mac->has_fwsm = true;
690 /* ARC subsystem not supported */
691 mac->arc_subsystem_valid = false;
692 /* Adaptive IFS supported */
693 mac->adaptive_ifs = true;
695 /* LED and other operations */
700 /* check management mode */
701 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
703 mac->ops.id_led_init = e1000e_id_led_init_generic;
705 mac->ops.blink_led = e1000e_blink_led_generic;
707 mac->ops.setup_led = e1000e_setup_led_generic;
709 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
710 /* turn on/off LED */
711 mac->ops.led_on = e1000_led_on_ich8lan;
712 mac->ops.led_off = e1000_led_off_ich8lan;
715 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
716 mac->ops.rar_set = e1000_rar_set_pch2lan;
722 /* check management mode */
723 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
725 mac->ops.id_led_init = e1000_id_led_init_pchlan;
727 mac->ops.setup_led = e1000_setup_led_pchlan;
729 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
730 /* turn on/off LED */
731 mac->ops.led_on = e1000_led_on_pchlan;
732 mac->ops.led_off = e1000_led_off_pchlan;
738 if (mac->type >= e1000_pch_lpt) {
739 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
740 mac->ops.rar_set = e1000_rar_set_pch_lpt;
741 mac->ops.setup_physical_interface =
742 e1000_setup_copper_link_pch_lpt;
743 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
746 /* Enable PCS Lock-loss workaround for ICH8 */
747 if (mac->type == e1000_ich8lan)
748 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
754 * __e1000_access_emi_reg_locked - Read/write EMI register
755 * @hw: pointer to the HW structure
756 * @addr: EMI address to program
757 * @data: pointer to value to read/write from/to the EMI address
758 * @read: boolean flag to indicate read or write
760 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
762 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
763 u16 *data, bool read)
767 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
772 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
774 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
780 * e1000_read_emi_reg_locked - Read Extended Management Interface register
781 * @hw: pointer to the HW structure
782 * @addr: EMI address to program
783 * @data: value to be read from the EMI address
785 * Assumes the SW/FW/HW Semaphore is already acquired.
787 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
789 return __e1000_access_emi_reg_locked(hw, addr, data, true);
793 * e1000_write_emi_reg_locked - Write Extended Management Interface register
794 * @hw: pointer to the HW structure
795 * @addr: EMI address to program
796 * @data: value to be written to the EMI address
798 * Assumes the SW/FW/HW Semaphore is already acquired.
800 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
802 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
806 * e1000_set_eee_pchlan - Enable/disable EEE support
807 * @hw: pointer to the HW structure
809 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
810 * the link and the EEE capabilities of the link partner. The LPI Control
811 * register bits will remain set only if/when link is up.
813 * EEE LPI must not be asserted earlier than one second after link is up.
814 * On 82579, EEE LPI should not be enabled until such time otherwise there
815 * can be link issues with some switches. Other devices can have EEE LPI
816 * enabled immediately upon link up since they have a timer in hardware which
817 * prevents LPI from being asserted too early.
819 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
821 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
823 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
825 switch (hw->phy.type) {
826 case e1000_phy_82579:
827 lpa = I82579_EEE_LP_ABILITY;
828 pcs_status = I82579_EEE_PCS_STATUS;
829 adv_addr = I82579_EEE_ADVERTISEMENT;
832 lpa = I217_EEE_LP_ABILITY;
833 pcs_status = I217_EEE_PCS_STATUS;
834 adv_addr = I217_EEE_ADVERTISEMENT;
840 ret_val = hw->phy.ops.acquire(hw);
844 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
848 /* Clear bits that enable EEE in various speeds */
849 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
851 /* Enable EEE if not disabled by user */
852 if (!dev_spec->eee_disable) {
853 /* Save off link partner's EEE ability */
854 ret_val = e1000_read_emi_reg_locked(hw, lpa,
855 &dev_spec->eee_lp_ability);
859 /* Read EEE advertisement */
860 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
864 /* Enable EEE only for speeds in which the link partner is
865 * EEE capable and for which we advertise EEE.
867 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
868 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
870 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
871 e1e_rphy_locked(hw, MII_LPA, &data);
872 if (data & LPA_100FULL)
873 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
875 /* EEE is not supported in 100Half, so ignore
876 * partner's EEE in 100 ability if full-duplex
879 dev_spec->eee_lp_ability &=
880 ~I82579_EEE_100_SUPPORTED;
884 if (hw->phy.type == e1000_phy_82579) {
885 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
890 data &= ~I82579_LPI_100_PLL_SHUT;
891 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
895 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
896 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
900 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
902 hw->phy.ops.release(hw);
908 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
909 * @hw: pointer to the HW structure
910 * @link: link up bool flag
912 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
913 * preventing further DMA write requests. Workaround the issue by disabling
914 * the de-assertion of the clock request when in 1Gpbs mode.
915 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
916 * speeds in order to avoid Tx hangs.
918 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
920 u32 fextnvm6 = er32(FEXTNVM6);
921 u32 status = er32(STATUS);
925 if (link && (status & E1000_STATUS_SPEED_1000)) {
926 ret_val = hw->phy.ops.acquire(hw);
931 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
937 e1000e_write_kmrn_reg_locked(hw,
938 E1000_KMRNCTRLSTA_K1_CONFIG,
940 ~E1000_KMRNCTRLSTA_K1_ENABLE);
944 usleep_range(10, 20);
946 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
949 e1000e_write_kmrn_reg_locked(hw,
950 E1000_KMRNCTRLSTA_K1_CONFIG,
953 hw->phy.ops.release(hw);
955 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
956 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
958 if ((hw->phy.revision > 5) || !link ||
959 ((status & E1000_STATUS_SPEED_100) &&
960 (status & E1000_STATUS_FD)))
961 goto update_fextnvm6;
963 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®);
967 /* Clear link status transmit timeout */
968 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
970 if (status & E1000_STATUS_SPEED_100) {
971 /* Set inband Tx timeout to 5x10us for 100Half */
972 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
974 /* Do not extend the K1 entry latency for 100Half */
975 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
977 /* Set inband Tx timeout to 50x10us for 10Full/Half */
979 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
981 /* Extend the K1 entry latency for 10 Mbps */
982 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
985 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
990 ew32(FEXTNVM6, fextnvm6);
997 * e1000_platform_pm_pch_lpt - Set platform power management values
998 * @hw: pointer to the HW structure
999 * @link: bool indicating link status
1001 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1002 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1003 * when link is up (which must not exceed the maximum latency supported
1004 * by the platform), otherwise specify there is no LTR requirement.
1005 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1006 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1007 * Capability register set, on this device LTR is set by writing the
1008 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1009 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1010 * message to the PMC.
1012 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1014 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1015 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1016 u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */
1017 u32 lat_enc_d = 0; /* latency decoded */
1018 u16 lat_enc = 0; /* latency encoded */
1021 u16 speed, duplex, scale = 0;
1022 u16 max_snoop, max_nosnoop;
1023 u16 max_ltr_enc; /* max LTR latency encoded */
1027 if (!hw->adapter->max_frame_size) {
1028 e_dbg("max_frame_size not set.\n");
1029 return -E1000_ERR_CONFIG;
1032 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1034 e_dbg("Speed not set.\n");
1035 return -E1000_ERR_CONFIG;
1038 /* Rx Packet Buffer Allocation size (KB) */
1039 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1041 /* Determine the maximum latency tolerated by the device.
1043 * Per the PCIe spec, the tolerated latencies are encoded as
1044 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1045 * a 10-bit value (0-1023) to provide a range from 1 ns to
1046 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1047 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1050 value = (rxa > hw->adapter->max_frame_size) ?
1051 (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1054 while (value > PCI_LTR_VALUE_MASK) {
1056 value = DIV_ROUND_UP(value, BIT(5));
1058 if (scale > E1000_LTRV_SCALE_MAX) {
1059 e_dbg("Invalid LTR latency scale %d\n", scale);
1060 return -E1000_ERR_CONFIG;
1062 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1064 /* Determine the maximum latency tolerated by the platform */
1065 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1067 pci_read_config_word(hw->adapter->pdev,
1068 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1069 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1071 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) *
1072 (1U << (E1000_LTRV_SCALE_FACTOR *
1073 ((lat_enc & E1000_LTRV_SCALE_MASK)
1074 >> E1000_LTRV_SCALE_SHIFT)));
1076 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) *
1077 (1U << (E1000_LTRV_SCALE_FACTOR *
1078 ((max_ltr_enc & E1000_LTRV_SCALE_MASK)
1079 >> E1000_LTRV_SCALE_SHIFT)));
1081 if (lat_enc_d > max_ltr_enc_d)
1082 lat_enc = max_ltr_enc;
1085 /* Set Snoop and No-Snoop latencies the same */
1086 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1093 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1094 * @hw: pointer to the HW structure
1095 * @to_sx: boolean indicating a system power state transition to Sx
1097 * When link is down, configure ULP mode to significantly reduce the power
1098 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1099 * ME firmware to start the ULP configuration. If not on an ME enabled
1100 * system, configure the ULP mode by software.
1102 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1109 if ((hw->mac.type < e1000_pch_lpt) ||
1110 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1111 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1112 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1113 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1114 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1117 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1118 /* Request ME configure ULP mode in the PHY */
1119 mac_reg = er32(H2ME);
1120 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1121 ew32(H2ME, mac_reg);
1129 /* Poll up to 5 seconds for Cable Disconnected indication */
1130 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1131 /* Bail if link is re-acquired */
1132 if (er32(STATUS) & E1000_STATUS_LU)
1133 return -E1000_ERR_PHY;
1140 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1142 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1145 ret_val = hw->phy.ops.acquire(hw);
1149 /* Force SMBus mode in PHY */
1150 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1153 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1154 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1156 /* Force SMBus mode in MAC */
1157 mac_reg = er32(CTRL_EXT);
1158 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1159 ew32(CTRL_EXT, mac_reg);
1161 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1162 * LPLU and disable Gig speed when entering ULP
1164 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1165 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1171 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1173 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1180 /* Set Inband ULP Exit, Reset to SMBus mode and
1181 * Disable SMBus Release on PERST# in PHY
1183 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1186 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1187 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1189 if (er32(WUFC) & E1000_WUFC_LNKC)
1190 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1192 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1194 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1195 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1197 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1198 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1199 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1201 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1203 /* Set Disable SMBus Release on PERST# in MAC */
1204 mac_reg = er32(FEXTNVM7);
1205 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1206 ew32(FEXTNVM7, mac_reg);
1208 /* Commit ULP changes in PHY by starting auto ULP configuration */
1209 phy_reg |= I218_ULP_CONFIG1_START;
1210 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1212 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1213 to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1214 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1221 hw->phy.ops.release(hw);
1224 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1226 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1232 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1233 * @hw: pointer to the HW structure
1234 * @force: boolean indicating whether or not to force disabling ULP
1236 * Un-configure ULP mode when link is up, the system is transitioned from
1237 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1238 * system, poll for an indication from ME that ULP has been un-configured.
1239 * If not on an ME enabled system, un-configure the ULP mode by software.
1241 * During nominal operation, this function is called when link is acquired
1242 * to disable ULP mode (force=false); otherwise, for example when unloading
1243 * the driver or during Sx->S0 transitions, this is called with force=true
1244 * to forcibly disable ULP.
1246 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1253 if ((hw->mac.type < e1000_pch_lpt) ||
1254 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1255 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1256 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1257 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1258 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1261 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1263 /* Request ME un-configure ULP mode in the PHY */
1264 mac_reg = er32(H2ME);
1265 mac_reg &= ~E1000_H2ME_ULP;
1266 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1267 ew32(H2ME, mac_reg);
1270 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1271 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1273 ret_val = -E1000_ERR_PHY;
1277 usleep_range(10000, 20000);
1279 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1282 mac_reg = er32(H2ME);
1283 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1284 ew32(H2ME, mac_reg);
1286 /* Clear H2ME.ULP after ME ULP configuration */
1287 mac_reg = er32(H2ME);
1288 mac_reg &= ~E1000_H2ME_ULP;
1289 ew32(H2ME, mac_reg);
1295 ret_val = hw->phy.ops.acquire(hw);
1300 /* Toggle LANPHYPC Value bit */
1301 e1000_toggle_lanphypc_pch_lpt(hw);
1303 /* Unforce SMBus mode in PHY */
1304 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1306 /* The MAC might be in PCIe mode, so temporarily force to
1307 * SMBus mode in order to access the PHY.
1309 mac_reg = er32(CTRL_EXT);
1310 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1311 ew32(CTRL_EXT, mac_reg);
1315 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1320 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1321 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1323 /* Unforce SMBus mode in MAC */
1324 mac_reg = er32(CTRL_EXT);
1325 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1326 ew32(CTRL_EXT, mac_reg);
1328 /* When ULP mode was previously entered, K1 was disabled by the
1329 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1331 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1334 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1335 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1337 /* Clear ULP enabled configuration */
1338 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1341 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1342 I218_ULP_CONFIG1_STICKY_ULP |
1343 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1344 I218_ULP_CONFIG1_WOL_HOST |
1345 I218_ULP_CONFIG1_INBAND_EXIT |
1346 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1347 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1348 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1349 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1351 /* Commit ULP changes by starting auto ULP configuration */
1352 phy_reg |= I218_ULP_CONFIG1_START;
1353 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1355 /* Clear Disable SMBus Release on PERST# in MAC */
1356 mac_reg = er32(FEXTNVM7);
1357 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1358 ew32(FEXTNVM7, mac_reg);
1361 hw->phy.ops.release(hw);
1363 e1000_phy_hw_reset(hw);
1368 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1370 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1376 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1377 * @hw: pointer to the HW structure
1379 * Checks to see of the link status of the hardware has changed. If a
1380 * change in link status has been detected, then we read the PHY registers
1381 * to get the current speed/duplex if link exists.
1383 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1385 struct e1000_mac_info *mac = &hw->mac;
1386 s32 ret_val, tipg_reg = 0;
1387 u16 emi_addr, emi_val = 0;
1391 /* We only want to go out to the PHY registers to see if Auto-Neg
1392 * has completed and/or if our link status has changed. The
1393 * get_link_status flag is set upon receiving a Link Status
1394 * Change or Rx Sequence Error interrupt.
1396 if (!mac->get_link_status)
1398 mac->get_link_status = false;
1400 /* First we want to see if the MII Status Register reports
1401 * link. If so, then we want to get the current speed/duplex
1404 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1408 if (hw->mac.type == e1000_pchlan) {
1409 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1414 /* When connected at 10Mbps half-duplex, some parts are excessively
1415 * aggressive resulting in many collisions. To avoid this, increase
1416 * the IPG and reduce Rx latency in the PHY.
1418 if ((hw->mac.type >= e1000_pch2lan) && link) {
1421 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1422 tipg_reg = er32(TIPG);
1423 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1425 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1427 /* Reduce Rx latency in analog PHY */
1429 } else if (hw->mac.type >= e1000_pch_spt &&
1430 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1435 /* Roll back the default values */
1440 ew32(TIPG, tipg_reg);
1442 ret_val = hw->phy.ops.acquire(hw);
1446 if (hw->mac.type == e1000_pch2lan)
1447 emi_addr = I82579_RX_CONFIG;
1449 emi_addr = I217_RX_CONFIG;
1450 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1452 if (hw->mac.type >= e1000_pch_lpt) {
1455 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1456 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1457 if (speed == SPEED_100 || speed == SPEED_10)
1461 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1463 if (speed == SPEED_1000) {
1464 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1467 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1469 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1473 hw->phy.ops.release(hw);
1478 if (hw->mac.type >= e1000_pch_spt) {
1482 if (speed == SPEED_1000) {
1483 ret_val = hw->phy.ops.acquire(hw);
1487 ret_val = e1e_rphy_locked(hw,
1491 hw->phy.ops.release(hw);
1495 ptr_gap = (data & (0x3FF << 2)) >> 2;
1496 if (ptr_gap < 0x18) {
1497 data &= ~(0x3FF << 2);
1498 data |= (0x18 << 2);
1504 hw->phy.ops.release(hw);
1508 ret_val = hw->phy.ops.acquire(hw);
1512 ret_val = e1e_wphy_locked(hw,
1515 hw->phy.ops.release(hw);
1523 /* I217 Packet Loss issue:
1524 * ensure that FEXTNVM4 Beacon Duration is set correctly
1526 * Set the Beacon Duration for I217 to 8 usec
1528 if (hw->mac.type >= e1000_pch_lpt) {
1531 mac_reg = er32(FEXTNVM4);
1532 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1533 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1534 ew32(FEXTNVM4, mac_reg);
1537 /* Work-around I218 hang issue */
1538 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1539 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1540 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1541 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1542 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1546 if (hw->mac.type >= e1000_pch_lpt) {
1547 /* Set platform power management values for
1548 * Latency Tolerance Reporting (LTR)
1550 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1555 /* Clear link partner's EEE ability */
1556 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1558 if (hw->mac.type >= e1000_pch_lpt) {
1559 u32 fextnvm6 = er32(FEXTNVM6);
1561 if (hw->mac.type == e1000_pch_spt) {
1562 /* FEXTNVM6 K1-off workaround - for SPT only */
1563 u32 pcieanacfg = er32(PCIEANACFG);
1565 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1566 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1568 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1571 ew32(FEXTNVM6, fextnvm6);
1577 switch (hw->mac.type) {
1579 ret_val = e1000_k1_workaround_lv(hw);
1584 if (hw->phy.type == e1000_phy_82578) {
1585 ret_val = e1000_link_stall_workaround_hv(hw);
1590 /* Workaround for PCHx parts in half-duplex:
1591 * Set the number of preambles removed from the packet
1592 * when it is passed from the PHY to the MAC to prevent
1593 * the MAC from misinterpreting the packet type.
1595 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1596 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1598 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1599 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1601 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1607 /* Check if there was DownShift, must be checked
1608 * immediately after link-up
1610 e1000e_check_downshift(hw);
1612 /* Enable/Disable EEE after link up */
1613 if (hw->phy.type > e1000_phy_82579) {
1614 ret_val = e1000_set_eee_pchlan(hw);
1619 /* If we are forcing speed/duplex, then we simply return since
1620 * we have already determined whether we have link or not.
1625 /* Auto-Neg is enabled. Auto Speed Detection takes care
1626 * of MAC speed/duplex configuration. So we only need to
1627 * configure Collision Distance in the MAC.
1629 mac->ops.config_collision_dist(hw);
1631 /* Configure Flow Control now that Auto-Neg has completed.
1632 * First, we need to restore the desired flow control
1633 * settings because we may have had to re-autoneg with a
1634 * different link partner.
1636 ret_val = e1000e_config_fc_after_link_up(hw);
1638 e_dbg("Error configuring flow control\n");
1643 mac->get_link_status = true;
1647 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1649 struct e1000_hw *hw = &adapter->hw;
1652 rc = e1000_init_mac_params_ich8lan(hw);
1656 rc = e1000_init_nvm_params_ich8lan(hw);
1660 switch (hw->mac.type) {
1663 case e1000_ich10lan:
1664 rc = e1000_init_phy_params_ich8lan(hw);
1671 rc = e1000_init_phy_params_pchlan(hw);
1679 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1680 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1682 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1683 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1684 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1685 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1686 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1688 hw->mac.ops.blink_led = NULL;
1691 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1692 (adapter->hw.phy.type != e1000_phy_ife))
1693 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1695 /* Enable workaround for 82579 w/ ME enabled */
1696 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1697 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1698 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1703 static DEFINE_MUTEX(nvm_mutex);
1706 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1707 * @hw: pointer to the HW structure
1709 * Acquires the mutex for performing NVM operations.
1711 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1713 mutex_lock(&nvm_mutex);
1719 * e1000_release_nvm_ich8lan - Release NVM mutex
1720 * @hw: pointer to the HW structure
1722 * Releases the mutex used while performing NVM operations.
1724 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1726 mutex_unlock(&nvm_mutex);
1730 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1731 * @hw: pointer to the HW structure
1733 * Acquires the software control flag for performing PHY and select
1736 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1738 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1741 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1742 &hw->adapter->state)) {
1743 e_dbg("contention for Phy access\n");
1744 return -E1000_ERR_PHY;
1748 extcnf_ctrl = er32(EXTCNF_CTRL);
1749 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1757 e_dbg("SW has already locked the resource.\n");
1758 ret_val = -E1000_ERR_CONFIG;
1762 timeout = SW_FLAG_TIMEOUT;
1764 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1765 ew32(EXTCNF_CTRL, extcnf_ctrl);
1768 extcnf_ctrl = er32(EXTCNF_CTRL);
1769 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1777 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1778 er32(FWSM), extcnf_ctrl);
1779 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1780 ew32(EXTCNF_CTRL, extcnf_ctrl);
1781 ret_val = -E1000_ERR_CONFIG;
1787 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1793 * e1000_release_swflag_ich8lan - Release software control flag
1794 * @hw: pointer to the HW structure
1796 * Releases the software control flag for performing PHY and select
1799 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1803 extcnf_ctrl = er32(EXTCNF_CTRL);
1805 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1806 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1807 ew32(EXTCNF_CTRL, extcnf_ctrl);
1809 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1812 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1816 * e1000_check_mng_mode_ich8lan - Checks management mode
1817 * @hw: pointer to the HW structure
1819 * This checks if the adapter has any manageability enabled.
1820 * This is a function pointer entry point only called by read/write
1821 * routines for the PHY and NVM parts.
1823 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1828 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1829 ((fwsm & E1000_FWSM_MODE_MASK) ==
1830 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1834 * e1000_check_mng_mode_pchlan - Checks management mode
1835 * @hw: pointer to the HW structure
1837 * This checks if the adapter has iAMT enabled.
1838 * This is a function pointer entry point only called by read/write
1839 * routines for the PHY and NVM parts.
1841 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1846 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1847 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1851 * e1000_rar_set_pch2lan - Set receive address register
1852 * @hw: pointer to the HW structure
1853 * @addr: pointer to the receive address
1854 * @index: receive address array register
1856 * Sets the receive address array register at index to the address passed
1857 * in by addr. For 82579, RAR[0] is the base address register that is to
1858 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1859 * Use SHRA[0-3] in place of those reserved for ME.
1861 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1863 u32 rar_low, rar_high;
1865 /* HW expects these in little endian so we reverse the byte order
1866 * from network order (big endian) to little endian
1868 rar_low = ((u32)addr[0] |
1869 ((u32)addr[1] << 8) |
1870 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1872 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1874 /* If MAC address zero, no need to set the AV bit */
1875 if (rar_low || rar_high)
1876 rar_high |= E1000_RAH_AV;
1879 ew32(RAL(index), rar_low);
1881 ew32(RAH(index), rar_high);
1886 /* RAR[1-6] are owned by manageability. Skip those and program the
1887 * next address into the SHRA register array.
1889 if (index < (u32)(hw->mac.rar_entry_count)) {
1892 ret_val = e1000_acquire_swflag_ich8lan(hw);
1896 ew32(SHRAL(index - 1), rar_low);
1898 ew32(SHRAH(index - 1), rar_high);
1901 e1000_release_swflag_ich8lan(hw);
1903 /* verify the register updates */
1904 if ((er32(SHRAL(index - 1)) == rar_low) &&
1905 (er32(SHRAH(index - 1)) == rar_high))
1908 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1909 (index - 1), er32(FWSM));
1913 e_dbg("Failed to write receive address at index %d\n", index);
1914 return -E1000_ERR_CONFIG;
1918 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1919 * @hw: pointer to the HW structure
1921 * Get the number of available receive registers that the Host can
1922 * program. SHRA[0-10] are the shared receive address registers
1923 * that are shared between the Host and manageability engine (ME).
1924 * ME can reserve any number of addresses and the host needs to be
1925 * able to tell how many available registers it has access to.
1927 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1932 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1933 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1935 switch (wlock_mac) {
1937 /* All SHRA[0..10] and RAR[0] available */
1938 num_entries = hw->mac.rar_entry_count;
1941 /* Only RAR[0] available */
1945 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1946 num_entries = wlock_mac + 1;
1954 * e1000_rar_set_pch_lpt - Set receive address registers
1955 * @hw: pointer to the HW structure
1956 * @addr: pointer to the receive address
1957 * @index: receive address array register
1959 * Sets the receive address register array at index to the address passed
1960 * in by addr. For LPT, RAR[0] is the base address register that is to
1961 * contain the MAC address. SHRA[0-10] are the shared receive address
1962 * registers that are shared between the Host and manageability engine (ME).
1964 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1966 u32 rar_low, rar_high;
1969 /* HW expects these in little endian so we reverse the byte order
1970 * from network order (big endian) to little endian
1972 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1973 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1975 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1977 /* If MAC address zero, no need to set the AV bit */
1978 if (rar_low || rar_high)
1979 rar_high |= E1000_RAH_AV;
1982 ew32(RAL(index), rar_low);
1984 ew32(RAH(index), rar_high);
1989 /* The manageability engine (ME) can lock certain SHRAR registers that
1990 * it is using - those registers are unavailable for use.
1992 if (index < hw->mac.rar_entry_count) {
1993 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1994 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1996 /* Check if all SHRAR registers are locked */
2000 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2003 ret_val = e1000_acquire_swflag_ich8lan(hw);
2008 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
2010 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
2013 e1000_release_swflag_ich8lan(hw);
2015 /* verify the register updates */
2016 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2017 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
2023 e_dbg("Failed to write receive address at index %d\n", index);
2024 return -E1000_ERR_CONFIG;
2028 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2029 * @hw: pointer to the HW structure
2031 * Checks if firmware is blocking the reset of the PHY.
2032 * This is a function pointer entry point only called by
2035 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2037 bool blocked = false;
2040 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2042 usleep_range(10000, 20000);
2043 return blocked ? E1000_BLK_PHY_RESET : 0;
2047 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2048 * @hw: pointer to the HW structure
2050 * Assumes semaphore already acquired.
2053 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2056 u32 strap = er32(STRAP);
2057 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2058 E1000_STRAP_SMT_FREQ_SHIFT;
2061 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2063 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2067 phy_data &= ~HV_SMB_ADDR_MASK;
2068 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2069 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2071 if (hw->phy.type == e1000_phy_i217) {
2072 /* Restore SMBus frequency */
2074 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2075 phy_data |= (freq & BIT(0)) <<
2076 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2077 phy_data |= (freq & BIT(1)) <<
2078 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2080 e_dbg("Unsupported SMB frequency in PHY\n");
2084 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2088 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2089 * @hw: pointer to the HW structure
2091 * SW should configure the LCD from the NVM extended configuration region
2092 * as a workaround for certain parts.
2094 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2096 struct e1000_phy_info *phy = &hw->phy;
2097 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2099 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2101 /* Initialize the PHY from the NVM on ICH platforms. This
2102 * is needed due to an issue where the NVM configuration is
2103 * not properly autoloaded after power transitions.
2104 * Therefore, after each PHY reset, we will load the
2105 * configuration data out of the NVM manually.
2107 switch (hw->mac.type) {
2109 if (phy->type != e1000_phy_igp_3)
2112 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2113 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2114 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2123 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2129 ret_val = hw->phy.ops.acquire(hw);
2133 data = er32(FEXTNVM);
2134 if (!(data & sw_cfg_mask))
2137 /* Make sure HW does not configure LCD from PHY
2138 * extended configuration before SW configuration
2140 data = er32(EXTCNF_CTRL);
2141 if ((hw->mac.type < e1000_pch2lan) &&
2142 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2145 cnf_size = er32(EXTCNF_SIZE);
2146 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2147 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2151 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2152 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2154 if (((hw->mac.type == e1000_pchlan) &&
2155 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2156 (hw->mac.type > e1000_pchlan)) {
2157 /* HW configures the SMBus address and LEDs when the
2158 * OEM and LCD Write Enable bits are set in the NVM.
2159 * When both NVM bits are cleared, SW will configure
2162 ret_val = e1000_write_smbus_addr(hw);
2166 data = er32(LEDCTL);
2167 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2173 /* Configure LCD from extended configuration region. */
2175 /* cnf_base_addr is in DWORD */
2176 word_addr = (u16)(cnf_base_addr << 1);
2178 for (i = 0; i < cnf_size; i++) {
2179 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data);
2183 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2188 /* Save off the PHY page for future writes. */
2189 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2190 phy_page = reg_data;
2194 reg_addr &= PHY_REG_MASK;
2195 reg_addr |= phy_page;
2197 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2203 hw->phy.ops.release(hw);
2208 * e1000_k1_gig_workaround_hv - K1 Si workaround
2209 * @hw: pointer to the HW structure
2210 * @link: link up bool flag
2212 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2213 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2214 * If link is down, the function will restore the default K1 setting located
2217 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2221 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2223 if (hw->mac.type != e1000_pchlan)
2226 /* Wrap the whole flow with the sw flag */
2227 ret_val = hw->phy.ops.acquire(hw);
2231 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2233 if (hw->phy.type == e1000_phy_82578) {
2234 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2239 status_reg &= (BM_CS_STATUS_LINK_UP |
2240 BM_CS_STATUS_RESOLVED |
2241 BM_CS_STATUS_SPEED_MASK);
2243 if (status_reg == (BM_CS_STATUS_LINK_UP |
2244 BM_CS_STATUS_RESOLVED |
2245 BM_CS_STATUS_SPEED_1000))
2249 if (hw->phy.type == e1000_phy_82577) {
2250 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2254 status_reg &= (HV_M_STATUS_LINK_UP |
2255 HV_M_STATUS_AUTONEG_COMPLETE |
2256 HV_M_STATUS_SPEED_MASK);
2258 if (status_reg == (HV_M_STATUS_LINK_UP |
2259 HV_M_STATUS_AUTONEG_COMPLETE |
2260 HV_M_STATUS_SPEED_1000))
2264 /* Link stall fix for link up */
2265 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2270 /* Link stall fix for link down */
2271 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2276 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2279 hw->phy.ops.release(hw);
2285 * e1000_configure_k1_ich8lan - Configure K1 power state
2286 * @hw: pointer to the HW structure
2287 * @enable: K1 state to configure
2289 * Configure the K1 power state based on the provided parameter.
2290 * Assumes semaphore already acquired.
2292 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2294 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2302 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2308 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2310 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2312 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2317 usleep_range(20, 40);
2318 ctrl_ext = er32(CTRL_EXT);
2319 ctrl_reg = er32(CTRL);
2321 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2322 reg |= E1000_CTRL_FRCSPD;
2325 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2327 usleep_range(20, 40);
2328 ew32(CTRL, ctrl_reg);
2329 ew32(CTRL_EXT, ctrl_ext);
2331 usleep_range(20, 40);
2337 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2338 * @hw: pointer to the HW structure
2339 * @d0_state: boolean if entering d0 or d3 device state
2341 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2342 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2343 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2345 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2351 if (hw->mac.type < e1000_pchlan)
2354 ret_val = hw->phy.ops.acquire(hw);
2358 if (hw->mac.type == e1000_pchlan) {
2359 mac_reg = er32(EXTCNF_CTRL);
2360 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2364 mac_reg = er32(FEXTNVM);
2365 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2368 mac_reg = er32(PHY_CTRL);
2370 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2374 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2377 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2378 oem_reg |= HV_OEM_BITS_GBE_DIS;
2380 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2381 oem_reg |= HV_OEM_BITS_LPLU;
2383 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2384 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2385 oem_reg |= HV_OEM_BITS_GBE_DIS;
2387 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2388 E1000_PHY_CTRL_NOND0A_LPLU))
2389 oem_reg |= HV_OEM_BITS_LPLU;
2392 /* Set Restart auto-neg to activate the bits */
2393 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2394 !hw->phy.ops.check_reset_block(hw))
2395 oem_reg |= HV_OEM_BITS_RESTART_AN;
2397 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2400 hw->phy.ops.release(hw);
2406 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2407 * @hw: pointer to the HW structure
2409 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2414 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2418 data |= HV_KMRN_MDIO_SLOW;
2420 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2426 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2427 * done after every PHY reset.
2429 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2434 if (hw->mac.type != e1000_pchlan)
2437 /* Set MDIO slow mode before any other MDIO access */
2438 if (hw->phy.type == e1000_phy_82577) {
2439 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2444 if (((hw->phy.type == e1000_phy_82577) &&
2445 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2446 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2447 /* Disable generation of early preamble */
2448 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2452 /* Preamble tuning for SSC */
2453 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2458 if (hw->phy.type == e1000_phy_82578) {
2459 /* Return registers to default by doing a soft reset then
2460 * writing 0x3140 to the control register.
2462 if (hw->phy.revision < 2) {
2463 e1000e_phy_sw_reset(hw);
2464 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2471 ret_val = hw->phy.ops.acquire(hw);
2476 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2477 hw->phy.ops.release(hw);
2481 /* Configure the K1 Si workaround during phy reset assuming there is
2482 * link so that it disables K1 if link is in 1Gbps.
2484 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2488 /* Workaround for link disconnects on a busy hub in half duplex */
2489 ret_val = hw->phy.ops.acquire(hw);
2492 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2495 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2499 /* set MSE higher to enable link to stay up when noise is high */
2500 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2502 hw->phy.ops.release(hw);
2508 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2509 * @hw: pointer to the HW structure
2511 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2517 ret_val = hw->phy.ops.acquire(hw);
2520 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2524 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2525 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2526 mac_reg = er32(RAL(i));
2527 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2528 (u16)(mac_reg & 0xFFFF));
2529 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2530 (u16)((mac_reg >> 16) & 0xFFFF));
2532 mac_reg = er32(RAH(i));
2533 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2534 (u16)(mac_reg & 0xFFFF));
2535 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2536 (u16)((mac_reg & E1000_RAH_AV)
2540 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2543 hw->phy.ops.release(hw);
2547 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2549 * @hw: pointer to the HW structure
2550 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2552 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2559 if (hw->mac.type < e1000_pch2lan)
2562 /* disable Rx path while enabling/disabling workaround */
2563 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2564 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2569 /* Write Rx addresses (rar_entry_count for RAL/H, and
2570 * SHRAL/H) and initial CRC values to the MAC
2572 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2573 u8 mac_addr[ETH_ALEN] = { 0 };
2574 u32 addr_high, addr_low;
2576 addr_high = er32(RAH(i));
2577 if (!(addr_high & E1000_RAH_AV))
2579 addr_low = er32(RAL(i));
2580 mac_addr[0] = (addr_low & 0xFF);
2581 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2582 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2583 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2584 mac_addr[4] = (addr_high & 0xFF);
2585 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2587 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2590 /* Write Rx addresses to the PHY */
2591 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2593 /* Enable jumbo frame workaround in the MAC */
2594 mac_reg = er32(FFLT_DBG);
2595 mac_reg &= ~BIT(14);
2596 mac_reg |= (7 << 15);
2597 ew32(FFLT_DBG, mac_reg);
2599 mac_reg = er32(RCTL);
2600 mac_reg |= E1000_RCTL_SECRC;
2601 ew32(RCTL, mac_reg);
2603 ret_val = e1000e_read_kmrn_reg(hw,
2604 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2608 ret_val = e1000e_write_kmrn_reg(hw,
2609 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2613 ret_val = e1000e_read_kmrn_reg(hw,
2614 E1000_KMRNCTRLSTA_HD_CTRL,
2618 data &= ~(0xF << 8);
2620 ret_val = e1000e_write_kmrn_reg(hw,
2621 E1000_KMRNCTRLSTA_HD_CTRL,
2626 /* Enable jumbo frame workaround in the PHY */
2627 e1e_rphy(hw, PHY_REG(769, 23), &data);
2628 data &= ~(0x7F << 5);
2629 data |= (0x37 << 5);
2630 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2633 e1e_rphy(hw, PHY_REG(769, 16), &data);
2635 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2638 e1e_rphy(hw, PHY_REG(776, 20), &data);
2639 data &= ~(0x3FF << 2);
2640 data |= (E1000_TX_PTR_GAP << 2);
2641 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2644 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2647 e1e_rphy(hw, HV_PM_CTRL, &data);
2648 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2652 /* Write MAC register values back to h/w defaults */
2653 mac_reg = er32(FFLT_DBG);
2654 mac_reg &= ~(0xF << 14);
2655 ew32(FFLT_DBG, mac_reg);
2657 mac_reg = er32(RCTL);
2658 mac_reg &= ~E1000_RCTL_SECRC;
2659 ew32(RCTL, mac_reg);
2661 ret_val = e1000e_read_kmrn_reg(hw,
2662 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2666 ret_val = e1000e_write_kmrn_reg(hw,
2667 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2671 ret_val = e1000e_read_kmrn_reg(hw,
2672 E1000_KMRNCTRLSTA_HD_CTRL,
2676 data &= ~(0xF << 8);
2678 ret_val = e1000e_write_kmrn_reg(hw,
2679 E1000_KMRNCTRLSTA_HD_CTRL,
2684 /* Write PHY register values back to h/w defaults */
2685 e1e_rphy(hw, PHY_REG(769, 23), &data);
2686 data &= ~(0x7F << 5);
2687 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2690 e1e_rphy(hw, PHY_REG(769, 16), &data);
2692 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2695 e1e_rphy(hw, PHY_REG(776, 20), &data);
2696 data &= ~(0x3FF << 2);
2698 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2701 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2704 e1e_rphy(hw, HV_PM_CTRL, &data);
2705 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2710 /* re-enable Rx path after enabling/disabling workaround */
2711 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2715 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2716 * done after every PHY reset.
2718 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2722 if (hw->mac.type != e1000_pch2lan)
2725 /* Set MDIO slow mode before any other MDIO access */
2726 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2730 ret_val = hw->phy.ops.acquire(hw);
2733 /* set MSE higher to enable link to stay up when noise is high */
2734 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2737 /* drop link after 5 times MSE threshold was reached */
2738 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2740 hw->phy.ops.release(hw);
2746 * e1000_k1_gig_workaround_lv - K1 Si workaround
2747 * @hw: pointer to the HW structure
2749 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2750 * Disable K1 in 1000Mbps and 100Mbps
2752 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2757 if (hw->mac.type != e1000_pch2lan)
2760 /* Set K1 beacon duration based on 10Mbs speed */
2761 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2765 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2766 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2768 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2771 /* LV 1G/100 Packet drop issue wa */
2772 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2775 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2776 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2782 mac_reg = er32(FEXTNVM4);
2783 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2784 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2785 ew32(FEXTNVM4, mac_reg);
2793 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2794 * @hw: pointer to the HW structure
2795 * @gate: boolean set to true to gate, false to ungate
2797 * Gate/ungate the automatic PHY configuration via hardware; perform
2798 * the configuration via software instead.
2800 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2804 if (hw->mac.type < e1000_pch2lan)
2807 extcnf_ctrl = er32(EXTCNF_CTRL);
2810 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2812 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2814 ew32(EXTCNF_CTRL, extcnf_ctrl);
2818 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2819 * @hw: pointer to the HW structure
2821 * Check the appropriate indication the MAC has finished configuring the
2822 * PHY after a software reset.
2824 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2826 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2828 /* Wait for basic configuration completes before proceeding */
2830 data = er32(STATUS);
2831 data &= E1000_STATUS_LAN_INIT_DONE;
2832 usleep_range(100, 200);
2833 } while ((!data) && --loop);
2835 /* If basic configuration is incomplete before the above loop
2836 * count reaches 0, loading the configuration from NVM will
2837 * leave the PHY in a bad state possibly resulting in no link.
2840 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2842 /* Clear the Init Done bit for the next init event */
2843 data = er32(STATUS);
2844 data &= ~E1000_STATUS_LAN_INIT_DONE;
2849 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2850 * @hw: pointer to the HW structure
2852 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2857 if (hw->phy.ops.check_reset_block(hw))
2860 /* Allow time for h/w to get to quiescent state after reset */
2861 usleep_range(10000, 20000);
2863 /* Perform any necessary post-reset workarounds */
2864 switch (hw->mac.type) {
2866 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2871 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2879 /* Clear the host wakeup bit after lcd reset */
2880 if (hw->mac.type >= e1000_pchlan) {
2881 e1e_rphy(hw, BM_PORT_GEN_CFG, ®);
2882 reg &= ~BM_WUC_HOST_WU_BIT;
2883 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2886 /* Configure the LCD with the extended configuration region in NVM */
2887 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2891 /* Configure the LCD with the OEM bits in NVM */
2892 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2894 if (hw->mac.type == e1000_pch2lan) {
2895 /* Ungate automatic PHY configuration on non-managed 82579 */
2896 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2897 usleep_range(10000, 20000);
2898 e1000_gate_hw_phy_config_ich8lan(hw, false);
2901 /* Set EEE LPI Update Timer to 200usec */
2902 ret_val = hw->phy.ops.acquire(hw);
2905 ret_val = e1000_write_emi_reg_locked(hw,
2906 I82579_LPI_UPDATE_TIMER,
2908 hw->phy.ops.release(hw);
2915 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2916 * @hw: pointer to the HW structure
2919 * This is a function pointer entry point called by drivers
2920 * or other shared routines.
2922 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2926 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2927 if ((hw->mac.type == e1000_pch2lan) &&
2928 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2929 e1000_gate_hw_phy_config_ich8lan(hw, true);
2931 ret_val = e1000e_phy_hw_reset_generic(hw);
2935 return e1000_post_phy_reset_ich8lan(hw);
2939 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2940 * @hw: pointer to the HW structure
2941 * @active: true to enable LPLU, false to disable
2943 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2944 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2945 * the phy speed. This function will manually set the LPLU bit and restart
2946 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2947 * since it configures the same bit.
2949 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2954 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2959 oem_reg |= HV_OEM_BITS_LPLU;
2961 oem_reg &= ~HV_OEM_BITS_LPLU;
2963 if (!hw->phy.ops.check_reset_block(hw))
2964 oem_reg |= HV_OEM_BITS_RESTART_AN;
2966 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2970 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2971 * @hw: pointer to the HW structure
2972 * @active: true to enable LPLU, false to disable
2974 * Sets the LPLU D0 state according to the active flag. When
2975 * activating LPLU this function also disables smart speed
2976 * and vice versa. LPLU will not be activated unless the
2977 * device autonegotiation advertisement meets standards of
2978 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2979 * This is a function pointer entry point only called by
2980 * PHY setup routines.
2982 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2984 struct e1000_phy_info *phy = &hw->phy;
2989 if (phy->type == e1000_phy_ife)
2992 phy_ctrl = er32(PHY_CTRL);
2995 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2996 ew32(PHY_CTRL, phy_ctrl);
2998 if (phy->type != e1000_phy_igp_3)
3001 /* Call gig speed drop workaround on LPLU before accessing
3004 if (hw->mac.type == e1000_ich8lan)
3005 e1000e_gig_downshift_workaround_ich8lan(hw);
3007 /* When LPLU is enabled, we should disable SmartSpeed */
3008 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3011 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3012 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3016 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3017 ew32(PHY_CTRL, phy_ctrl);
3019 if (phy->type != e1000_phy_igp_3)
3022 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3023 * during Dx states where the power conservation is most
3024 * important. During driver activity we should enable
3025 * SmartSpeed, so performance is maintained.
3027 if (phy->smart_speed == e1000_smart_speed_on) {
3028 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3033 data |= IGP01E1000_PSCFR_SMART_SPEED;
3034 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3038 } else if (phy->smart_speed == e1000_smart_speed_off) {
3039 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3044 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3045 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3056 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3057 * @hw: pointer to the HW structure
3058 * @active: true to enable LPLU, false to disable
3060 * Sets the LPLU D3 state according to the active flag. When
3061 * activating LPLU this function also disables smart speed
3062 * and vice versa. LPLU will not be activated unless the
3063 * device autonegotiation advertisement meets standards of
3064 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3065 * This is a function pointer entry point only called by
3066 * PHY setup routines.
3068 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3070 struct e1000_phy_info *phy = &hw->phy;
3075 phy_ctrl = er32(PHY_CTRL);
3078 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3079 ew32(PHY_CTRL, phy_ctrl);
3081 if (phy->type != e1000_phy_igp_3)
3084 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3085 * during Dx states where the power conservation is most
3086 * important. During driver activity we should enable
3087 * SmartSpeed, so performance is maintained.
3089 if (phy->smart_speed == e1000_smart_speed_on) {
3090 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3095 data |= IGP01E1000_PSCFR_SMART_SPEED;
3096 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3100 } else if (phy->smart_speed == e1000_smart_speed_off) {
3101 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3106 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3107 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3112 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3113 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3114 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3115 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3116 ew32(PHY_CTRL, phy_ctrl);
3118 if (phy->type != e1000_phy_igp_3)
3121 /* Call gig speed drop workaround on LPLU before accessing
3124 if (hw->mac.type == e1000_ich8lan)
3125 e1000e_gig_downshift_workaround_ich8lan(hw);
3127 /* When LPLU is enabled, we should disable SmartSpeed */
3128 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3132 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3133 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3140 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3141 * @hw: pointer to the HW structure
3142 * @bank: pointer to the variable that returns the active bank
3144 * Reads signature byte from the NVM using the flash access registers.
3145 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3147 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3150 struct e1000_nvm_info *nvm = &hw->nvm;
3151 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3152 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3157 switch (hw->mac.type) {
3160 bank1_offset = nvm->flash_bank_size;
3161 act_offset = E1000_ICH_NVM_SIG_WORD;
3163 /* set bank to 0 in case flash read fails */
3167 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3171 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3172 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3173 E1000_ICH_NVM_SIG_VALUE) {
3179 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3184 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3185 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3186 E1000_ICH_NVM_SIG_VALUE) {
3191 e_dbg("ERROR: No valid NVM bank present\n");
3192 return -E1000_ERR_NVM;
3196 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3197 E1000_EECD_SEC1VAL_VALID_MASK) {
3198 if (eecd & E1000_EECD_SEC1VAL)
3205 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3208 /* set bank to 0 in case flash read fails */
3212 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3216 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3217 E1000_ICH_NVM_SIG_VALUE) {
3223 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3228 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3229 E1000_ICH_NVM_SIG_VALUE) {
3234 e_dbg("ERROR: No valid NVM bank present\n");
3235 return -E1000_ERR_NVM;
3240 * e1000_read_nvm_spt - NVM access for SPT
3241 * @hw: pointer to the HW structure
3242 * @offset: The offset (in bytes) of the word(s) to read.
3243 * @words: Size of data to read in words.
3244 * @data: pointer to the word(s) to read at offset.
3246 * Reads a word(s) from the NVM
3248 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3251 struct e1000_nvm_info *nvm = &hw->nvm;
3252 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3260 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3262 e_dbg("nvm parameter(s) out of bounds\n");
3263 ret_val = -E1000_ERR_NVM;
3267 nvm->ops.acquire(hw);
3269 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3271 e_dbg("Could not detect valid bank, assuming bank 0\n");
3275 act_offset = (bank) ? nvm->flash_bank_size : 0;
3276 act_offset += offset;
3280 for (i = 0; i < words; i += 2) {
3281 if (words - i == 1) {
3282 if (dev_spec->shadow_ram[offset + i].modified) {
3284 dev_spec->shadow_ram[offset + i].value;
3286 offset_to_read = act_offset + i -
3287 ((act_offset + i) % 2);
3289 e1000_read_flash_dword_ich8lan(hw,
3294 if ((act_offset + i) % 2 == 0)
3295 data[i] = (u16)(dword & 0xFFFF);
3297 data[i] = (u16)((dword >> 16) & 0xFFFF);
3300 offset_to_read = act_offset + i;
3301 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3302 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3304 e1000_read_flash_dword_ich8lan(hw,
3310 if (dev_spec->shadow_ram[offset + i].modified)
3312 dev_spec->shadow_ram[offset + i].value;
3314 data[i] = (u16)(dword & 0xFFFF);
3315 if (dev_spec->shadow_ram[offset + i].modified)
3317 dev_spec->shadow_ram[offset + i + 1].value;
3319 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3323 nvm->ops.release(hw);
3327 e_dbg("NVM read error: %d\n", ret_val);
3333 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3334 * @hw: pointer to the HW structure
3335 * @offset: The offset (in bytes) of the word(s) to read.
3336 * @words: Size of data to read in words
3337 * @data: Pointer to the word(s) to read at offset.
3339 * Reads a word(s) from the NVM using the flash access registers.
3341 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3344 struct e1000_nvm_info *nvm = &hw->nvm;
3345 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3351 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3353 e_dbg("nvm parameter(s) out of bounds\n");
3354 ret_val = -E1000_ERR_NVM;
3358 nvm->ops.acquire(hw);
3360 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3362 e_dbg("Could not detect valid bank, assuming bank 0\n");
3366 act_offset = (bank) ? nvm->flash_bank_size : 0;
3367 act_offset += offset;
3370 for (i = 0; i < words; i++) {
3371 if (dev_spec->shadow_ram[offset + i].modified) {
3372 data[i] = dev_spec->shadow_ram[offset + i].value;
3374 ret_val = e1000_read_flash_word_ich8lan(hw,
3383 nvm->ops.release(hw);
3387 e_dbg("NVM read error: %d\n", ret_val);
3393 * e1000_flash_cycle_init_ich8lan - Initialize flash
3394 * @hw: pointer to the HW structure
3396 * This function does initial flash setup so that a new read/write/erase cycle
3399 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3401 union ich8_hws_flash_status hsfsts;
3402 s32 ret_val = -E1000_ERR_NVM;
3404 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3406 /* Check if the flash descriptor is valid */
3407 if (!hsfsts.hsf_status.fldesvalid) {
3408 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3409 return -E1000_ERR_NVM;
3412 /* Clear FCERR and DAEL in hw status by writing 1 */
3413 hsfsts.hsf_status.flcerr = 1;
3414 hsfsts.hsf_status.dael = 1;
3415 if (hw->mac.type >= e1000_pch_spt)
3416 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3418 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3420 /* Either we should have a hardware SPI cycle in progress
3421 * bit to check against, in order to start a new cycle or
3422 * FDONE bit should be changed in the hardware so that it
3423 * is 1 after hardware reset, which can then be used as an
3424 * indication whether a cycle is in progress or has been
3428 if (!hsfsts.hsf_status.flcinprog) {
3429 /* There is no cycle running at present,
3430 * so we can start a cycle.
3431 * Begin by setting Flash Cycle Done.
3433 hsfsts.hsf_status.flcdone = 1;
3434 if (hw->mac.type >= e1000_pch_spt)
3435 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3437 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3442 /* Otherwise poll for sometime so the current
3443 * cycle has a chance to end before giving up.
3445 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3446 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3447 if (!hsfsts.hsf_status.flcinprog) {
3454 /* Successful in waiting for previous cycle to timeout,
3455 * now set the Flash Cycle Done.
3457 hsfsts.hsf_status.flcdone = 1;
3458 if (hw->mac.type >= e1000_pch_spt)
3459 ew32flash(ICH_FLASH_HSFSTS,
3460 hsfsts.regval & 0xFFFF);
3462 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3464 e_dbg("Flash controller busy, cannot get access\n");
3472 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3473 * @hw: pointer to the HW structure
3474 * @timeout: maximum time to wait for completion
3476 * This function starts a flash cycle and waits for its completion.
3478 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3480 union ich8_hws_flash_ctrl hsflctl;
3481 union ich8_hws_flash_status hsfsts;
3484 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3485 if (hw->mac.type >= e1000_pch_spt)
3486 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3488 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3489 hsflctl.hsf_ctrl.flcgo = 1;
3491 if (hw->mac.type >= e1000_pch_spt)
3492 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3494 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3496 /* wait till FDONE bit is set to 1 */
3498 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3499 if (hsfsts.hsf_status.flcdone)
3502 } while (i++ < timeout);
3504 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3507 return -E1000_ERR_NVM;
3511 * e1000_read_flash_dword_ich8lan - Read dword from flash
3512 * @hw: pointer to the HW structure
3513 * @offset: offset to data location
3514 * @data: pointer to the location for storing the data
3516 * Reads the flash dword at offset into data. Offset is converted
3517 * to bytes before read.
3519 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3522 /* Must convert word offset into bytes. */
3524 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3528 * e1000_read_flash_word_ich8lan - Read word from flash
3529 * @hw: pointer to the HW structure
3530 * @offset: offset to data location
3531 * @data: pointer to the location for storing the data
3533 * Reads the flash word at offset into data. Offset is converted
3534 * to bytes before read.
3536 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3539 /* Must convert offset into bytes. */
3542 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3546 * e1000_read_flash_byte_ich8lan - Read byte from flash
3547 * @hw: pointer to the HW structure
3548 * @offset: The offset of the byte to read.
3549 * @data: Pointer to a byte to store the value read.
3551 * Reads a single byte from the NVM using the flash access registers.
3553 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3559 /* In SPT, only 32 bits access is supported,
3560 * so this function should not be called.
3562 if (hw->mac.type >= e1000_pch_spt)
3563 return -E1000_ERR_NVM;
3565 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3576 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3577 * @hw: pointer to the HW structure
3578 * @offset: The offset (in bytes) of the byte or word to read.
3579 * @size: Size of data to read, 1=byte 2=word
3580 * @data: Pointer to the word to store the value read.
3582 * Reads a byte or word from the NVM using the flash access registers.
3584 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3587 union ich8_hws_flash_status hsfsts;
3588 union ich8_hws_flash_ctrl hsflctl;
3589 u32 flash_linear_addr;
3591 s32 ret_val = -E1000_ERR_NVM;
3594 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3595 return -E1000_ERR_NVM;
3597 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3598 hw->nvm.flash_base_addr);
3603 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3607 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3608 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3609 hsflctl.hsf_ctrl.fldbcount = size - 1;
3610 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3611 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3613 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3616 e1000_flash_cycle_ich8lan(hw,
3617 ICH_FLASH_READ_COMMAND_TIMEOUT);
3619 /* Check if FCERR is set to 1, if set to 1, clear it
3620 * and try the whole sequence a few more times, else
3621 * read in (shift in) the Flash Data0, the order is
3622 * least significant byte first msb to lsb
3625 flash_data = er32flash(ICH_FLASH_FDATA0);
3627 *data = (u8)(flash_data & 0x000000FF);
3629 *data = (u16)(flash_data & 0x0000FFFF);
3632 /* If we've gotten here, then things are probably
3633 * completely hosed, but if the error condition is
3634 * detected, it won't hurt to give it another try...
3635 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3637 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3638 if (hsfsts.hsf_status.flcerr) {
3639 /* Repeat for some time before giving up. */
3641 } else if (!hsfsts.hsf_status.flcdone) {
3642 e_dbg("Timeout error - flash cycle did not complete.\n");
3646 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3652 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3653 * @hw: pointer to the HW structure
3654 * @offset: The offset (in bytes) of the dword to read.
3655 * @data: Pointer to the dword to store the value read.
3657 * Reads a byte or word from the NVM using the flash access registers.
3660 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3663 union ich8_hws_flash_status hsfsts;
3664 union ich8_hws_flash_ctrl hsflctl;
3665 u32 flash_linear_addr;
3666 s32 ret_val = -E1000_ERR_NVM;
3669 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3670 return -E1000_ERR_NVM;
3671 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3672 hw->nvm.flash_base_addr);
3677 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3680 /* In SPT, This register is in Lan memory space, not flash.
3681 * Therefore, only 32 bit access is supported
3683 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3685 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3686 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3687 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3688 /* In SPT, This register is in Lan memory space, not flash.
3689 * Therefore, only 32 bit access is supported
3691 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3692 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3695 e1000_flash_cycle_ich8lan(hw,
3696 ICH_FLASH_READ_COMMAND_TIMEOUT);
3698 /* Check if FCERR is set to 1, if set to 1, clear it
3699 * and try the whole sequence a few more times, else
3700 * read in (shift in) the Flash Data0, the order is
3701 * least significant byte first msb to lsb
3704 *data = er32flash(ICH_FLASH_FDATA0);
3707 /* If we've gotten here, then things are probably
3708 * completely hosed, but if the error condition is
3709 * detected, it won't hurt to give it another try...
3710 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3712 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3713 if (hsfsts.hsf_status.flcerr) {
3714 /* Repeat for some time before giving up. */
3716 } else if (!hsfsts.hsf_status.flcdone) {
3717 e_dbg("Timeout error - flash cycle did not complete.\n");
3721 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3727 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3728 * @hw: pointer to the HW structure
3729 * @offset: The offset (in bytes) of the word(s) to write.
3730 * @words: Size of data to write in words
3731 * @data: Pointer to the word(s) to write at offset.
3733 * Writes a byte or word to the NVM using the flash access registers.
3735 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3738 struct e1000_nvm_info *nvm = &hw->nvm;
3739 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3742 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3744 e_dbg("nvm parameter(s) out of bounds\n");
3745 return -E1000_ERR_NVM;
3748 nvm->ops.acquire(hw);
3750 for (i = 0; i < words; i++) {
3751 dev_spec->shadow_ram[offset + i].modified = true;
3752 dev_spec->shadow_ram[offset + i].value = data[i];
3755 nvm->ops.release(hw);
3761 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3762 * @hw: pointer to the HW structure
3764 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3765 * which writes the checksum to the shadow ram. The changes in the shadow
3766 * ram are then committed to the EEPROM by processing each bank at a time
3767 * checking for the modified bit and writing only the pending changes.
3768 * After a successful commit, the shadow ram is cleared and is ready for
3771 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3773 struct e1000_nvm_info *nvm = &hw->nvm;
3774 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3775 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3779 ret_val = e1000e_update_nvm_checksum_generic(hw);
3783 if (nvm->type != e1000_nvm_flash_sw)
3786 nvm->ops.acquire(hw);
3788 /* We're writing to the opposite bank so if we're on bank 1,
3789 * write to bank 0 etc. We also need to erase the segment that
3790 * is going to be written
3792 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3794 e_dbg("Could not detect valid bank, assuming bank 0\n");
3799 new_bank_offset = nvm->flash_bank_size;
3800 old_bank_offset = 0;
3801 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3805 old_bank_offset = nvm->flash_bank_size;
3806 new_bank_offset = 0;
3807 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3811 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3812 /* Determine whether to write the value stored
3813 * in the other NVM bank or a modified value stored
3816 ret_val = e1000_read_flash_dword_ich8lan(hw,
3817 i + old_bank_offset,
3820 if (dev_spec->shadow_ram[i].modified) {
3821 dword &= 0xffff0000;
3822 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3824 if (dev_spec->shadow_ram[i + 1].modified) {
3825 dword &= 0x0000ffff;
3826 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3832 /* If the word is 0x13, then make sure the signature bits
3833 * (15:14) are 11b until the commit has completed.
3834 * This will allow us to write 10b which indicates the
3835 * signature is valid. We want to do this after the write
3836 * has completed so that we don't mark the segment valid
3837 * while the write is still in progress
3839 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3840 dword |= E1000_ICH_NVM_SIG_MASK << 16;
3842 /* Convert offset to bytes. */
3843 act_offset = (i + new_bank_offset) << 1;
3845 usleep_range(100, 200);
3847 /* Write the data to the new bank. Offset in words */
3848 act_offset = i + new_bank_offset;
3849 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3855 /* Don't bother writing the segment valid bits if sector
3856 * programming failed.
3859 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3860 e_dbg("Flash commit failed.\n");
3864 /* Finally validate the new segment by setting bit 15:14
3865 * to 10b in word 0x13 , this can be done without an
3866 * erase as well since these bits are 11 to start with
3867 * and we need to change bit 14 to 0b
3869 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3871 /*offset in words but we read dword */
3873 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3878 dword &= 0xBFFFFFFF;
3879 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3884 /* And invalidate the previously valid segment by setting
3885 * its signature word (0x13) high_byte to 0b. This can be
3886 * done without an erase because flash erase sets all bits
3887 * to 1's. We can write 1's to 0's without an erase
3889 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3891 /* offset in words but we read dword */
3892 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3893 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3898 dword &= 0x00FFFFFF;
3899 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3904 /* Great! Everything worked, we can now clear the cached entries. */
3905 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3906 dev_spec->shadow_ram[i].modified = false;
3907 dev_spec->shadow_ram[i].value = 0xFFFF;
3911 nvm->ops.release(hw);
3913 /* Reload the EEPROM, or else modifications will not appear
3914 * until after the next adapter reset.
3917 nvm->ops.reload(hw);
3918 usleep_range(10000, 20000);
3923 e_dbg("NVM update error: %d\n", ret_val);
3929 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3930 * @hw: pointer to the HW structure
3932 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3933 * which writes the checksum to the shadow ram. The changes in the shadow
3934 * ram are then committed to the EEPROM by processing each bank at a time
3935 * checking for the modified bit and writing only the pending changes.
3936 * After a successful commit, the shadow ram is cleared and is ready for
3939 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3941 struct e1000_nvm_info *nvm = &hw->nvm;
3942 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3943 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3947 ret_val = e1000e_update_nvm_checksum_generic(hw);
3951 if (nvm->type != e1000_nvm_flash_sw)
3954 nvm->ops.acquire(hw);
3956 /* We're writing to the opposite bank so if we're on bank 1,
3957 * write to bank 0 etc. We also need to erase the segment that
3958 * is going to be written
3960 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3962 e_dbg("Could not detect valid bank, assuming bank 0\n");
3967 new_bank_offset = nvm->flash_bank_size;
3968 old_bank_offset = 0;
3969 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3973 old_bank_offset = nvm->flash_bank_size;
3974 new_bank_offset = 0;
3975 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3979 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3980 if (dev_spec->shadow_ram[i].modified) {
3981 data = dev_spec->shadow_ram[i].value;
3983 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3990 /* If the word is 0x13, then make sure the signature bits
3991 * (15:14) are 11b until the commit has completed.
3992 * This will allow us to write 10b which indicates the
3993 * signature is valid. We want to do this after the write
3994 * has completed so that we don't mark the segment valid
3995 * while the write is still in progress
3997 if (i == E1000_ICH_NVM_SIG_WORD)
3998 data |= E1000_ICH_NVM_SIG_MASK;
4000 /* Convert offset to bytes. */
4001 act_offset = (i + new_bank_offset) << 1;
4003 usleep_range(100, 200);
4004 /* Write the bytes to the new bank. */
4005 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4011 usleep_range(100, 200);
4012 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4019 /* Don't bother writing the segment valid bits if sector
4020 * programming failed.
4023 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4024 e_dbg("Flash commit failed.\n");
4028 /* Finally validate the new segment by setting bit 15:14
4029 * to 10b in word 0x13 , this can be done without an
4030 * erase as well since these bits are 11 to start with
4031 * and we need to change bit 14 to 0b
4033 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4034 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4039 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4045 /* And invalidate the previously valid segment by setting
4046 * its signature word (0x13) high_byte to 0b. This can be
4047 * done without an erase because flash erase sets all bits
4048 * to 1's. We can write 1's to 0's without an erase
4050 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4051 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4055 /* Great! Everything worked, we can now clear the cached entries. */
4056 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4057 dev_spec->shadow_ram[i].modified = false;
4058 dev_spec->shadow_ram[i].value = 0xFFFF;
4062 nvm->ops.release(hw);
4064 /* Reload the EEPROM, or else modifications will not appear
4065 * until after the next adapter reset.
4068 nvm->ops.reload(hw);
4069 usleep_range(10000, 20000);
4074 e_dbg("NVM update error: %d\n", ret_val);
4080 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4081 * @hw: pointer to the HW structure
4083 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4084 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4085 * calculated, in which case we need to calculate the checksum and set bit 6.
4087 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4092 u16 valid_csum_mask;
4094 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4095 * the checksum needs to be fixed. This bit is an indication that
4096 * the NVM was prepared by OEM software and did not calculate
4097 * the checksum...a likely scenario.
4099 switch (hw->mac.type) {
4104 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4107 word = NVM_FUTURE_INIT_WORD1;
4108 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4112 ret_val = e1000_read_nvm(hw, word, 1, &data);
4116 if (!(data & valid_csum_mask)) {
4117 data |= valid_csum_mask;
4118 ret_val = e1000_write_nvm(hw, word, 1, &data);
4121 ret_val = e1000e_update_nvm_checksum(hw);
4126 return e1000e_validate_nvm_checksum_generic(hw);
4130 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4131 * @hw: pointer to the HW structure
4133 * To prevent malicious write/erase of the NVM, set it to be read-only
4134 * so that the hardware ignores all write/erase cycles of the NVM via
4135 * the flash control registers. The shadow-ram copy of the NVM will
4136 * still be updated, however any updates to this copy will not stick
4137 * across driver reloads.
4139 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4141 struct e1000_nvm_info *nvm = &hw->nvm;
4142 union ich8_flash_protected_range pr0;
4143 union ich8_hws_flash_status hsfsts;
4146 nvm->ops.acquire(hw);
4148 gfpreg = er32flash(ICH_FLASH_GFPREG);
4150 /* Write-protect GbE Sector of NVM */
4151 pr0.regval = er32flash(ICH_FLASH_PR0);
4152 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4153 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4154 pr0.range.wpe = true;
4155 ew32flash(ICH_FLASH_PR0, pr0.regval);
4157 /* Lock down a subset of GbE Flash Control Registers, e.g.
4158 * PR0 to prevent the write-protection from being lifted.
4159 * Once FLOCKDN is set, the registers protected by it cannot
4160 * be written until FLOCKDN is cleared by a hardware reset.
4162 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4163 hsfsts.hsf_status.flockdn = true;
4164 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4166 nvm->ops.release(hw);
4170 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4171 * @hw: pointer to the HW structure
4172 * @offset: The offset (in bytes) of the byte/word to read.
4173 * @size: Size of data to read, 1=byte 2=word
4174 * @data: The byte(s) to write to the NVM.
4176 * Writes one/two bytes to the NVM using the flash access registers.
4178 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4181 union ich8_hws_flash_status hsfsts;
4182 union ich8_hws_flash_ctrl hsflctl;
4183 u32 flash_linear_addr;
4188 if (hw->mac.type >= e1000_pch_spt) {
4189 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4190 return -E1000_ERR_NVM;
4192 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4193 return -E1000_ERR_NVM;
4196 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4197 hw->nvm.flash_base_addr);
4202 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4205 /* In SPT, This register is in Lan memory space, not
4206 * flash. Therefore, only 32 bit access is supported
4208 if (hw->mac.type >= e1000_pch_spt)
4209 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4211 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4213 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4214 hsflctl.hsf_ctrl.fldbcount = size - 1;
4215 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4216 /* In SPT, This register is in Lan memory space,
4217 * not flash. Therefore, only 32 bit access is
4220 if (hw->mac.type >= e1000_pch_spt)
4221 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4223 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4225 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4228 flash_data = (u32)data & 0x00FF;
4230 flash_data = (u32)data;
4232 ew32flash(ICH_FLASH_FDATA0, flash_data);
4234 /* check if FCERR is set to 1 , if set to 1, clear it
4235 * and try the whole sequence a few more times else done
4238 e1000_flash_cycle_ich8lan(hw,
4239 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4243 /* If we're here, then things are most likely
4244 * completely hosed, but if the error condition
4245 * is detected, it won't hurt to give it another
4246 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4248 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4249 if (hsfsts.hsf_status.flcerr)
4250 /* Repeat for some time before giving up. */
4252 if (!hsfsts.hsf_status.flcdone) {
4253 e_dbg("Timeout error - flash cycle did not complete.\n");
4256 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4262 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4263 * @hw: pointer to the HW structure
4264 * @offset: The offset (in bytes) of the dwords to read.
4265 * @data: The 4 bytes to write to the NVM.
4267 * Writes one/two/four bytes to the NVM using the flash access registers.
4269 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4272 union ich8_hws_flash_status hsfsts;
4273 union ich8_hws_flash_ctrl hsflctl;
4274 u32 flash_linear_addr;
4278 if (hw->mac.type >= e1000_pch_spt) {
4279 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4280 return -E1000_ERR_NVM;
4282 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4283 hw->nvm.flash_base_addr);
4287 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4291 /* In SPT, This register is in Lan memory space, not
4292 * flash. Therefore, only 32 bit access is supported
4294 if (hw->mac.type >= e1000_pch_spt)
4295 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4298 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4300 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4301 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4303 /* In SPT, This register is in Lan memory space,
4304 * not flash. Therefore, only 32 bit access is
4307 if (hw->mac.type >= e1000_pch_spt)
4308 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4310 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4312 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4314 ew32flash(ICH_FLASH_FDATA0, data);
4316 /* check if FCERR is set to 1 , if set to 1, clear it
4317 * and try the whole sequence a few more times else done
4320 e1000_flash_cycle_ich8lan(hw,
4321 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4326 /* If we're here, then things are most likely
4327 * completely hosed, but if the error condition
4328 * is detected, it won't hurt to give it another
4329 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4331 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4333 if (hsfsts.hsf_status.flcerr)
4334 /* Repeat for some time before giving up. */
4336 if (!hsfsts.hsf_status.flcdone) {
4337 e_dbg("Timeout error - flash cycle did not complete.\n");
4340 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4346 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4347 * @hw: pointer to the HW structure
4348 * @offset: The index of the byte to read.
4349 * @data: The byte to write to the NVM.
4351 * Writes a single byte to the NVM using the flash access registers.
4353 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4356 u16 word = (u16)data;
4358 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4362 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4363 * @hw: pointer to the HW structure
4364 * @offset: The offset of the word to write.
4365 * @dword: The dword to write to the NVM.
4367 * Writes a single dword to the NVM using the flash access registers.
4368 * Goes through a retry algorithm before giving up.
4370 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4371 u32 offset, u32 dword)
4374 u16 program_retries;
4376 /* Must convert word offset into bytes. */
4378 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4382 for (program_retries = 0; program_retries < 100; program_retries++) {
4383 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4384 usleep_range(100, 200);
4385 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4389 if (program_retries == 100)
4390 return -E1000_ERR_NVM;
4396 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4397 * @hw: pointer to the HW structure
4398 * @offset: The offset of the byte to write.
4399 * @byte: The byte to write to the NVM.
4401 * Writes a single byte to the NVM using the flash access registers.
4402 * Goes through a retry algorithm before giving up.
4404 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4405 u32 offset, u8 byte)
4408 u16 program_retries;
4410 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4414 for (program_retries = 0; program_retries < 100; program_retries++) {
4415 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4416 usleep_range(100, 200);
4417 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4421 if (program_retries == 100)
4422 return -E1000_ERR_NVM;
4428 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4429 * @hw: pointer to the HW structure
4430 * @bank: 0 for first bank, 1 for second bank, etc.
4432 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4433 * bank N is 4096 * N + flash_reg_addr.
4435 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4437 struct e1000_nvm_info *nvm = &hw->nvm;
4438 union ich8_hws_flash_status hsfsts;
4439 union ich8_hws_flash_ctrl hsflctl;
4440 u32 flash_linear_addr;
4441 /* bank size is in 16bit words - adjust to bytes */
4442 u32 flash_bank_size = nvm->flash_bank_size * 2;
4445 s32 j, iteration, sector_size;
4447 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4449 /* Determine HW Sector size: Read BERASE bits of hw flash status
4451 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4452 * consecutive sectors. The start index for the nth Hw sector
4453 * can be calculated as = bank * 4096 + n * 256
4454 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4455 * The start index for the nth Hw sector can be calculated
4457 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4458 * (ich9 only, otherwise error condition)
4459 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4461 switch (hsfsts.hsf_status.berasesz) {
4463 /* Hw sector size 256 */
4464 sector_size = ICH_FLASH_SEG_SIZE_256;
4465 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4468 sector_size = ICH_FLASH_SEG_SIZE_4K;
4472 sector_size = ICH_FLASH_SEG_SIZE_8K;
4476 sector_size = ICH_FLASH_SEG_SIZE_64K;
4480 return -E1000_ERR_NVM;
4483 /* Start with the base address, then add the sector offset. */
4484 flash_linear_addr = hw->nvm.flash_base_addr;
4485 flash_linear_addr += (bank) ? flash_bank_size : 0;
4487 for (j = 0; j < iteration; j++) {
4489 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4492 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4496 /* Write a value 11 (block Erase) in Flash
4497 * Cycle field in hw flash control
4499 if (hw->mac.type >= e1000_pch_spt)
4501 er32flash(ICH_FLASH_HSFSTS) >> 16;
4503 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4505 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4506 if (hw->mac.type >= e1000_pch_spt)
4507 ew32flash(ICH_FLASH_HSFSTS,
4508 hsflctl.regval << 16);
4510 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4512 /* Write the last 24 bits of an index within the
4513 * block into Flash Linear address field in Flash
4516 flash_linear_addr += (j * sector_size);
4517 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4519 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4523 /* Check if FCERR is set to 1. If 1,
4524 * clear it and try the whole sequence
4525 * a few more times else Done
4527 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4528 if (hsfsts.hsf_status.flcerr)
4529 /* repeat for some time before giving up */
4531 else if (!hsfsts.hsf_status.flcdone)
4533 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4540 * e1000_valid_led_default_ich8lan - Set the default LED settings
4541 * @hw: pointer to the HW structure
4542 * @data: Pointer to the LED settings
4544 * Reads the LED default settings from the NVM to data. If the NVM LED
4545 * settings is all 0's or F's, set the LED default to a valid LED default
4548 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4552 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4554 e_dbg("NVM Read Error\n");
4558 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4559 *data = ID_LED_DEFAULT_ICH8LAN;
4565 * e1000_id_led_init_pchlan - store LED configurations
4566 * @hw: pointer to the HW structure
4568 * PCH does not control LEDs via the LEDCTL register, rather it uses
4569 * the PHY LED configuration register.
4571 * PCH also does not have an "always on" or "always off" mode which
4572 * complicates the ID feature. Instead of using the "on" mode to indicate
4573 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4574 * use "link_up" mode. The LEDs will still ID on request if there is no
4575 * link based on logic in e1000_led_[on|off]_pchlan().
4577 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4579 struct e1000_mac_info *mac = &hw->mac;
4581 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4582 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4583 u16 data, i, temp, shift;
4585 /* Get default ID LED modes */
4586 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4590 mac->ledctl_default = er32(LEDCTL);
4591 mac->ledctl_mode1 = mac->ledctl_default;
4592 mac->ledctl_mode2 = mac->ledctl_default;
4594 for (i = 0; i < 4; i++) {
4595 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4598 case ID_LED_ON1_DEF2:
4599 case ID_LED_ON1_ON2:
4600 case ID_LED_ON1_OFF2:
4601 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4602 mac->ledctl_mode1 |= (ledctl_on << shift);
4604 case ID_LED_OFF1_DEF2:
4605 case ID_LED_OFF1_ON2:
4606 case ID_LED_OFF1_OFF2:
4607 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4608 mac->ledctl_mode1 |= (ledctl_off << shift);
4615 case ID_LED_DEF1_ON2:
4616 case ID_LED_ON1_ON2:
4617 case ID_LED_OFF1_ON2:
4618 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4619 mac->ledctl_mode2 |= (ledctl_on << shift);
4621 case ID_LED_DEF1_OFF2:
4622 case ID_LED_ON1_OFF2:
4623 case ID_LED_OFF1_OFF2:
4624 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4625 mac->ledctl_mode2 |= (ledctl_off << shift);
4637 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4638 * @hw: pointer to the HW structure
4640 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4641 * register, so the the bus width is hard coded.
4643 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4645 struct e1000_bus_info *bus = &hw->bus;
4648 ret_val = e1000e_get_bus_info_pcie(hw);
4650 /* ICH devices are "PCI Express"-ish. They have
4651 * a configuration space, but do not contain
4652 * PCI Express Capability registers, so bus width
4653 * must be hardcoded.
4655 if (bus->width == e1000_bus_width_unknown)
4656 bus->width = e1000_bus_width_pcie_x1;
4662 * e1000_reset_hw_ich8lan - Reset the hardware
4663 * @hw: pointer to the HW structure
4665 * Does a full reset of the hardware which includes a reset of the PHY and
4668 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4670 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4675 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4676 * on the last TLP read/write transaction when MAC is reset.
4678 ret_val = e1000e_disable_pcie_master(hw);
4680 e_dbg("PCI-E Master disable polling has failed.\n");
4682 e_dbg("Masking off all interrupts\n");
4683 ew32(IMC, 0xffffffff);
4685 /* Disable the Transmit and Receive units. Then delay to allow
4686 * any pending transactions to complete before we hit the MAC
4687 * with the global reset.
4690 ew32(TCTL, E1000_TCTL_PSP);
4693 usleep_range(10000, 20000);
4695 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4696 if (hw->mac.type == e1000_ich8lan) {
4697 /* Set Tx and Rx buffer allocation to 8k apiece. */
4698 ew32(PBA, E1000_PBA_8K);
4699 /* Set Packet Buffer Size to 16k. */
4700 ew32(PBS, E1000_PBS_16K);
4703 if (hw->mac.type == e1000_pchlan) {
4704 /* Save the NVM K1 bit setting */
4705 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4709 if (kum_cfg & E1000_NVM_K1_ENABLE)
4710 dev_spec->nvm_k1_enabled = true;
4712 dev_spec->nvm_k1_enabled = false;
4717 if (!hw->phy.ops.check_reset_block(hw)) {
4718 /* Full-chip reset requires MAC and PHY reset at the same
4719 * time to make sure the interface between MAC and the
4720 * external PHY is reset.
4722 ctrl |= E1000_CTRL_PHY_RST;
4724 /* Gate automatic PHY configuration by hardware on
4727 if ((hw->mac.type == e1000_pch2lan) &&
4728 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4729 e1000_gate_hw_phy_config_ich8lan(hw, true);
4731 ret_val = e1000_acquire_swflag_ich8lan(hw);
4732 e_dbg("Issuing a global reset to ich8lan\n");
4733 ew32(CTRL, (ctrl | E1000_CTRL_RST));
4734 /* cannot issue a flush here because it hangs the hardware */
4737 /* Set Phy Config Counter to 50msec */
4738 if (hw->mac.type == e1000_pch2lan) {
4739 reg = er32(FEXTNVM3);
4740 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4741 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4742 ew32(FEXTNVM3, reg);
4746 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4748 if (ctrl & E1000_CTRL_PHY_RST) {
4749 ret_val = hw->phy.ops.get_cfg_done(hw);
4753 ret_val = e1000_post_phy_reset_ich8lan(hw);
4758 /* For PCH, this write will make sure that any noise
4759 * will be detected as a CRC error and be dropped rather than show up
4760 * as a bad packet to the DMA engine.
4762 if (hw->mac.type == e1000_pchlan)
4763 ew32(CRC_OFFSET, 0x65656565);
4765 ew32(IMC, 0xffffffff);
4768 reg = er32(KABGTXD);
4769 reg |= E1000_KABGTXD_BGSQLBIAS;
4776 * e1000_init_hw_ich8lan - Initialize the hardware
4777 * @hw: pointer to the HW structure
4779 * Prepares the hardware for transmit and receive by doing the following:
4780 * - initialize hardware bits
4781 * - initialize LED identification
4782 * - setup receive address registers
4783 * - setup flow control
4784 * - setup transmit descriptors
4785 * - clear statistics
4787 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4789 struct e1000_mac_info *mac = &hw->mac;
4790 u32 ctrl_ext, txdctl, snoop;
4794 e1000_initialize_hw_bits_ich8lan(hw);
4796 /* Initialize identification LED */
4797 ret_val = mac->ops.id_led_init(hw);
4798 /* An error is not fatal and we should not stop init due to this */
4800 e_dbg("Error initializing identification LED\n");
4802 /* Setup the receive address. */
4803 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4805 /* Zero out the Multicast HASH table */
4806 e_dbg("Zeroing the MTA\n");
4807 for (i = 0; i < mac->mta_reg_count; i++)
4808 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4810 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4811 * the ME. Disable wakeup by clearing the host wakeup bit.
4812 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4814 if (hw->phy.type == e1000_phy_82578) {
4815 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4816 i &= ~BM_WUC_HOST_WU_BIT;
4817 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4818 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4823 /* Setup link and flow control */
4824 ret_val = mac->ops.setup_link(hw);
4826 /* Set the transmit descriptor write-back policy for both queues */
4827 txdctl = er32(TXDCTL(0));
4828 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4829 E1000_TXDCTL_FULL_TX_DESC_WB);
4830 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4831 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4832 ew32(TXDCTL(0), txdctl);
4833 txdctl = er32(TXDCTL(1));
4834 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4835 E1000_TXDCTL_FULL_TX_DESC_WB);
4836 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4837 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4838 ew32(TXDCTL(1), txdctl);
4840 /* ICH8 has opposite polarity of no_snoop bits.
4841 * By default, we should use snoop behavior.
4843 if (mac->type == e1000_ich8lan)
4844 snoop = PCIE_ICH8_SNOOP_ALL;
4846 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4847 e1000e_set_pcie_no_snoop(hw, snoop);
4849 ctrl_ext = er32(CTRL_EXT);
4850 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4851 ew32(CTRL_EXT, ctrl_ext);
4853 /* Clear all of the statistics registers (clear on read). It is
4854 * important that we do this after we have tried to establish link
4855 * because the symbol error count will increment wildly if there
4858 e1000_clear_hw_cntrs_ich8lan(hw);
4864 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4865 * @hw: pointer to the HW structure
4867 * Sets/Clears required hardware bits necessary for correctly setting up the
4868 * hardware for transmit and receive.
4870 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4874 /* Extended Device Control */
4875 reg = er32(CTRL_EXT);
4877 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4878 if (hw->mac.type >= e1000_pchlan)
4879 reg |= E1000_CTRL_EXT_PHYPDEN;
4880 ew32(CTRL_EXT, reg);
4882 /* Transmit Descriptor Control 0 */
4883 reg = er32(TXDCTL(0));
4885 ew32(TXDCTL(0), reg);
4887 /* Transmit Descriptor Control 1 */
4888 reg = er32(TXDCTL(1));
4890 ew32(TXDCTL(1), reg);
4892 /* Transmit Arbitration Control 0 */
4893 reg = er32(TARC(0));
4894 if (hw->mac.type == e1000_ich8lan)
4895 reg |= BIT(28) | BIT(29);
4896 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4899 /* Transmit Arbitration Control 1 */
4900 reg = er32(TARC(1));
4901 if (er32(TCTL) & E1000_TCTL_MULR)
4905 reg |= BIT(24) | BIT(26) | BIT(30);
4909 if (hw->mac.type == e1000_ich8lan) {
4915 /* work-around descriptor data corruption issue during nfs v2 udp
4916 * traffic, just disable the nfs filtering capability
4919 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4921 /* Disable IPv6 extension header parsing because some malformed
4922 * IPv6 headers can hang the Rx.
4924 if (hw->mac.type == e1000_ich8lan)
4925 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4928 /* Enable ECC on Lynxpoint */
4929 if (hw->mac.type >= e1000_pch_lpt) {
4930 reg = er32(PBECCSTS);
4931 reg |= E1000_PBECCSTS_ECC_ENABLE;
4932 ew32(PBECCSTS, reg);
4935 reg |= E1000_CTRL_MEHE;
4941 * e1000_setup_link_ich8lan - Setup flow control and link settings
4942 * @hw: pointer to the HW structure
4944 * Determines which flow control settings to use, then configures flow
4945 * control. Calls the appropriate media-specific link configuration
4946 * function. Assuming the adapter has a valid link partner, a valid link
4947 * should be established. Assumes the hardware has previously been reset
4948 * and the transmitter and receiver are not enabled.
4950 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4954 if (hw->phy.ops.check_reset_block(hw))
4957 /* ICH parts do not have a word in the NVM to determine
4958 * the default flow control setting, so we explicitly
4961 if (hw->fc.requested_mode == e1000_fc_default) {
4962 /* Workaround h/w hang when Tx flow control enabled */
4963 if (hw->mac.type == e1000_pchlan)
4964 hw->fc.requested_mode = e1000_fc_rx_pause;
4966 hw->fc.requested_mode = e1000_fc_full;
4969 /* Save off the requested flow control mode for use later. Depending
4970 * on the link partner's capabilities, we may or may not use this mode.
4972 hw->fc.current_mode = hw->fc.requested_mode;
4974 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4976 /* Continue to configure the copper link. */
4977 ret_val = hw->mac.ops.setup_physical_interface(hw);
4981 ew32(FCTTV, hw->fc.pause_time);
4982 if ((hw->phy.type == e1000_phy_82578) ||
4983 (hw->phy.type == e1000_phy_82579) ||
4984 (hw->phy.type == e1000_phy_i217) ||
4985 (hw->phy.type == e1000_phy_82577)) {
4986 ew32(FCRTV_PCH, hw->fc.refresh_time);
4988 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4994 return e1000e_set_fc_watermarks(hw);
4998 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4999 * @hw: pointer to the HW structure
5001 * Configures the kumeran interface to the PHY to wait the appropriate time
5002 * when polling the PHY, then call the generic setup_copper_link to finish
5003 * configuring the copper link.
5005 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5012 ctrl |= E1000_CTRL_SLU;
5013 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5016 /* Set the mac to wait the maximum time between each iteration
5017 * and increase the max iterations when polling the phy;
5018 * this fixes erroneous timeouts at 10Mbps.
5020 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5023 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5028 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5033 switch (hw->phy.type) {
5034 case e1000_phy_igp_3:
5035 ret_val = e1000e_copper_link_setup_igp(hw);
5040 case e1000_phy_82578:
5041 ret_val = e1000e_copper_link_setup_m88(hw);
5045 case e1000_phy_82577:
5046 case e1000_phy_82579:
5047 ret_val = e1000_copper_link_setup_82577(hw);
5052 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data);
5056 reg_data &= ~IFE_PMC_AUTO_MDIX;
5058 switch (hw->phy.mdix) {
5060 reg_data &= ~IFE_PMC_FORCE_MDIX;
5063 reg_data |= IFE_PMC_FORCE_MDIX;
5067 reg_data |= IFE_PMC_AUTO_MDIX;
5070 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5078 return e1000e_setup_copper_link(hw);
5082 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5083 * @hw: pointer to the HW structure
5085 * Calls the PHY specific link setup function and then calls the
5086 * generic setup_copper_link to finish configuring the link for
5087 * Lynxpoint PCH devices
5089 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5095 ctrl |= E1000_CTRL_SLU;
5096 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5099 ret_val = e1000_copper_link_setup_82577(hw);
5103 return e1000e_setup_copper_link(hw);
5107 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5108 * @hw: pointer to the HW structure
5109 * @speed: pointer to store current link speed
5110 * @duplex: pointer to store the current link duplex
5112 * Calls the generic get_speed_and_duplex to retrieve the current link
5113 * information and then calls the Kumeran lock loss workaround for links at
5116 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5121 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5125 if ((hw->mac.type == e1000_ich8lan) &&
5126 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5127 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5134 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5135 * @hw: pointer to the HW structure
5137 * Work-around for 82566 Kumeran PCS lock loss:
5138 * On link status change (i.e. PCI reset, speed change) and link is up and
5140 * 0) if workaround is optionally disabled do nothing
5141 * 1) wait 1ms for Kumeran link to come up
5142 * 2) check Kumeran Diagnostic register PCS lock loss bit
5143 * 3) if not set the link is locked (all is good), otherwise...
5145 * 5) repeat up to 10 times
5146 * Note: this is only called for IGP3 copper when speed is 1gb.
5148 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5150 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5156 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5159 /* Make sure link is up before proceeding. If not just return.
5160 * Attempting this while link is negotiating fouled up link
5163 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5167 for (i = 0; i < 10; i++) {
5168 /* read once to clear */
5169 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5172 /* and again to get new status */
5173 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5177 /* check for PCS lock */
5178 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5181 /* Issue PHY reset */
5182 e1000_phy_hw_reset(hw);
5185 /* Disable GigE link negotiation */
5186 phy_ctrl = er32(PHY_CTRL);
5187 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5188 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5189 ew32(PHY_CTRL, phy_ctrl);
5191 /* Call gig speed drop workaround on Gig disable before accessing
5194 e1000e_gig_downshift_workaround_ich8lan(hw);
5196 /* unable to acquire PCS lock */
5197 return -E1000_ERR_PHY;
5201 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5202 * @hw: pointer to the HW structure
5203 * @state: boolean value used to set the current Kumeran workaround state
5205 * If ICH8, set the current Kumeran workaround state (enabled - true
5206 * /disabled - false).
5208 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5211 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5213 if (hw->mac.type != e1000_ich8lan) {
5214 e_dbg("Workaround applies to ICH8 only.\n");
5218 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5222 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5223 * @hw: pointer to the HW structure
5225 * Workaround for 82566 power-down on D3 entry:
5226 * 1) disable gigabit link
5227 * 2) write VR power-down enable
5229 * Continue if successful, else issue LCD reset and repeat
5231 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5237 if (hw->phy.type != e1000_phy_igp_3)
5240 /* Try the workaround twice (if needed) */
5243 reg = er32(PHY_CTRL);
5244 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5245 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5246 ew32(PHY_CTRL, reg);
5248 /* Call gig speed drop workaround on Gig disable before
5249 * accessing any PHY registers
5251 if (hw->mac.type == e1000_ich8lan)
5252 e1000e_gig_downshift_workaround_ich8lan(hw);
5254 /* Write VR power-down enable */
5255 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5256 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5257 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5259 /* Read it back and test */
5260 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5261 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5262 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5265 /* Issue PHY reset and repeat at most one more time */
5267 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5273 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5274 * @hw: pointer to the HW structure
5276 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5277 * LPLU, Gig disable, MDIC PHY reset):
5278 * 1) Set Kumeran Near-end loopback
5279 * 2) Clear Kumeran Near-end loopback
5280 * Should only be called for ICH8[m] devices with any 1G Phy.
5282 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5287 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5290 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5294 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5295 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5299 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5300 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5304 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5305 * @hw: pointer to the HW structure
5307 * During S0 to Sx transition, it is possible the link remains at gig
5308 * instead of negotiating to a lower speed. Before going to Sx, set
5309 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5310 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5311 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5312 * needs to be written.
5313 * Parts that support (and are linked to a partner which support) EEE in
5314 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5315 * than 10Mbps w/o EEE.
5317 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5319 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5323 phy_ctrl = er32(PHY_CTRL);
5324 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5326 if (hw->phy.type == e1000_phy_i217) {
5327 u16 phy_reg, device_id = hw->adapter->pdev->device;
5329 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5330 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5331 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5332 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5333 (hw->mac.type >= e1000_pch_spt)) {
5334 u32 fextnvm6 = er32(FEXTNVM6);
5336 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5339 ret_val = hw->phy.ops.acquire(hw);
5343 if (!dev_spec->eee_disable) {
5347 e1000_read_emi_reg_locked(hw,
5348 I217_EEE_ADVERTISEMENT,
5353 /* Disable LPLU if both link partners support 100BaseT
5354 * EEE and 100Full is advertised on both ends of the
5355 * link, and enable Auto Enable LPI since there will
5356 * be no driver to enable LPI while in Sx.
5358 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5359 (dev_spec->eee_lp_ability &
5360 I82579_EEE_100_SUPPORTED) &&
5361 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5362 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5363 E1000_PHY_CTRL_NOND0A_LPLU);
5365 /* Set Auto Enable LPI after link up */
5367 I217_LPI_GPIO_CTRL, &phy_reg);
5368 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5370 I217_LPI_GPIO_CTRL, phy_reg);
5374 /* For i217 Intel Rapid Start Technology support,
5375 * when the system is going into Sx and no manageability engine
5376 * is present, the driver must configure proxy to reset only on
5377 * power good. LPI (Low Power Idle) state must also reset only
5378 * on power good, as well as the MTA (Multicast table array).
5379 * The SMBus release must also be disabled on LCD reset.
5381 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5382 /* Enable proxy to reset only on power good. */
5383 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5384 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5385 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5387 /* Set bit enable LPI (EEE) to reset only on
5390 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5391 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5392 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5394 /* Disable the SMB release on LCD reset. */
5395 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5396 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5397 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5400 /* Enable MTA to reset for Intel Rapid Start Technology
5403 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5404 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5405 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5408 hw->phy.ops.release(hw);
5411 ew32(PHY_CTRL, phy_ctrl);
5413 if (hw->mac.type == e1000_ich8lan)
5414 e1000e_gig_downshift_workaround_ich8lan(hw);
5416 if (hw->mac.type >= e1000_pchlan) {
5417 e1000_oem_bits_config_ich8lan(hw, false);
5419 /* Reset PHY to activate OEM bits on 82577/8 */
5420 if (hw->mac.type == e1000_pchlan)
5421 e1000e_phy_hw_reset_generic(hw);
5423 ret_val = hw->phy.ops.acquire(hw);
5426 e1000_write_smbus_addr(hw);
5427 hw->phy.ops.release(hw);
5432 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5433 * @hw: pointer to the HW structure
5435 * During Sx to S0 transitions on non-managed devices or managed devices
5436 * on which PHY resets are not blocked, if the PHY registers cannot be
5437 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5439 * On i217, setup Intel Rapid Start Technology.
5441 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5445 if (hw->mac.type < e1000_pch2lan)
5448 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5450 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5454 /* For i217 Intel Rapid Start Technology support when the system
5455 * is transitioning from Sx and no manageability engine is present
5456 * configure SMBus to restore on reset, disable proxy, and enable
5457 * the reset on MTA (Multicast table array).
5459 if (hw->phy.type == e1000_phy_i217) {
5462 ret_val = hw->phy.ops.acquire(hw);
5464 e_dbg("Failed to setup iRST\n");
5468 /* Clear Auto Enable LPI after link up */
5469 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5470 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5471 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5473 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5474 /* Restore clear on SMB if no manageability engine
5477 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5480 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5481 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5484 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5486 /* Enable reset on MTA */
5487 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5490 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5491 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5494 e_dbg("Error %d in resume workarounds\n", ret_val);
5495 hw->phy.ops.release(hw);
5500 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5501 * @hw: pointer to the HW structure
5503 * Return the LED back to the default configuration.
5505 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5507 if (hw->phy.type == e1000_phy_ife)
5508 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5510 ew32(LEDCTL, hw->mac.ledctl_default);
5515 * e1000_led_on_ich8lan - Turn LEDs on
5516 * @hw: pointer to the HW structure
5520 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5522 if (hw->phy.type == e1000_phy_ife)
5523 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5524 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5526 ew32(LEDCTL, hw->mac.ledctl_mode2);
5531 * e1000_led_off_ich8lan - Turn LEDs off
5532 * @hw: pointer to the HW structure
5534 * Turn off the LEDs.
5536 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5538 if (hw->phy.type == e1000_phy_ife)
5539 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5540 (IFE_PSCL_PROBE_MODE |
5541 IFE_PSCL_PROBE_LEDS_OFF));
5543 ew32(LEDCTL, hw->mac.ledctl_mode1);
5548 * e1000_setup_led_pchlan - Configures SW controllable LED
5549 * @hw: pointer to the HW structure
5551 * This prepares the SW controllable LED for use.
5553 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5555 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5559 * e1000_cleanup_led_pchlan - Restore the default LED operation
5560 * @hw: pointer to the HW structure
5562 * Return the LED back to the default configuration.
5564 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5566 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5570 * e1000_led_on_pchlan - Turn LEDs on
5571 * @hw: pointer to the HW structure
5575 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5577 u16 data = (u16)hw->mac.ledctl_mode2;
5580 /* If no link, then turn LED on by setting the invert bit
5581 * for each LED that's mode is "link_up" in ledctl_mode2.
5583 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5584 for (i = 0; i < 3; i++) {
5585 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5586 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5587 E1000_LEDCTL_MODE_LINK_UP)
5589 if (led & E1000_PHY_LED0_IVRT)
5590 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5592 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5596 return e1e_wphy(hw, HV_LED_CONFIG, data);
5600 * e1000_led_off_pchlan - Turn LEDs off
5601 * @hw: pointer to the HW structure
5603 * Turn off the LEDs.
5605 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5607 u16 data = (u16)hw->mac.ledctl_mode1;
5610 /* If no link, then turn LED off by clearing the invert bit
5611 * for each LED that's mode is "link_up" in ledctl_mode1.
5613 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5614 for (i = 0; i < 3; i++) {
5615 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5616 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5617 E1000_LEDCTL_MODE_LINK_UP)
5619 if (led & E1000_PHY_LED0_IVRT)
5620 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5622 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5626 return e1e_wphy(hw, HV_LED_CONFIG, data);
5630 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5631 * @hw: pointer to the HW structure
5633 * Read appropriate register for the config done bit for completion status
5634 * and configure the PHY through s/w for EEPROM-less parts.
5636 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5637 * config done bit, so only an error is logged and continues. If we were
5638 * to return with error, EEPROM-less silicon would not be able to be reset
5641 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5647 e1000e_get_cfg_done_generic(hw);
5649 /* Wait for indication from h/w that it has completed basic config */
5650 if (hw->mac.type >= e1000_ich10lan) {
5651 e1000_lan_init_done_ich8lan(hw);
5653 ret_val = e1000e_get_auto_rd_done(hw);
5655 /* When auto config read does not complete, do not
5656 * return with an error. This can happen in situations
5657 * where there is no eeprom and prevents getting link.
5659 e_dbg("Auto Read Done did not complete\n");
5664 /* Clear PHY Reset Asserted bit */
5665 status = er32(STATUS);
5666 if (status & E1000_STATUS_PHYRA)
5667 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5669 e_dbg("PHY Reset Asserted not set - needs delay\n");
5671 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5672 if (hw->mac.type <= e1000_ich9lan) {
5673 if (!(er32(EECD) & E1000_EECD_PRES) &&
5674 (hw->phy.type == e1000_phy_igp_3)) {
5675 e1000e_phy_init_script_igp3(hw);
5678 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5679 /* Maybe we should do a basic PHY config */
5680 e_dbg("EEPROM not present\n");
5681 ret_val = -E1000_ERR_CONFIG;
5689 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5690 * @hw: pointer to the HW structure
5692 * In the case of a PHY power down to save power, or to turn off link during a
5693 * driver unload, or wake on lan is not enabled, remove the link.
5695 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5697 /* If the management interface is not enabled, then power down */
5698 if (!(hw->mac.ops.check_mng_mode(hw) ||
5699 hw->phy.ops.check_reset_block(hw)))
5700 e1000_power_down_phy_copper(hw);
5704 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5705 * @hw: pointer to the HW structure
5707 * Clears hardware counters specific to the silicon family and calls
5708 * clear_hw_cntrs_generic to clear all general purpose counters.
5710 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5715 e1000e_clear_hw_cntrs_base(hw);
5731 /* Clear PHY statistics registers */
5732 if ((hw->phy.type == e1000_phy_82578) ||
5733 (hw->phy.type == e1000_phy_82579) ||
5734 (hw->phy.type == e1000_phy_i217) ||
5735 (hw->phy.type == e1000_phy_82577)) {
5736 ret_val = hw->phy.ops.acquire(hw);
5739 ret_val = hw->phy.ops.set_page(hw,
5740 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5743 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5744 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5745 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5746 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5747 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5748 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5749 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5750 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5751 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5752 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5753 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5754 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5755 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5756 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5758 hw->phy.ops.release(hw);
5762 static const struct e1000_mac_operations ich8_mac_ops = {
5763 /* check_mng_mode dependent on mac type */
5764 .check_for_link = e1000_check_for_copper_link_ich8lan,
5765 /* cleanup_led dependent on mac type */
5766 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5767 .get_bus_info = e1000_get_bus_info_ich8lan,
5768 .set_lan_id = e1000_set_lan_id_single_port,
5769 .get_link_up_info = e1000_get_link_up_info_ich8lan,
5770 /* led_on dependent on mac type */
5771 /* led_off dependent on mac type */
5772 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
5773 .reset_hw = e1000_reset_hw_ich8lan,
5774 .init_hw = e1000_init_hw_ich8lan,
5775 .setup_link = e1000_setup_link_ich8lan,
5776 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5777 /* id_led_init dependent on mac type */
5778 .config_collision_dist = e1000e_config_collision_dist_generic,
5779 .rar_set = e1000e_rar_set_generic,
5780 .rar_get_count = e1000e_rar_get_count_generic,
5783 static const struct e1000_phy_operations ich8_phy_ops = {
5784 .acquire = e1000_acquire_swflag_ich8lan,
5785 .check_reset_block = e1000_check_reset_block_ich8lan,
5787 .get_cfg_done = e1000_get_cfg_done_ich8lan,
5788 .get_cable_length = e1000e_get_cable_length_igp_2,
5789 .read_reg = e1000e_read_phy_reg_igp,
5790 .release = e1000_release_swflag_ich8lan,
5791 .reset = e1000_phy_hw_reset_ich8lan,
5792 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5793 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
5794 .write_reg = e1000e_write_phy_reg_igp,
5797 static const struct e1000_nvm_operations ich8_nvm_ops = {
5798 .acquire = e1000_acquire_nvm_ich8lan,
5799 .read = e1000_read_nvm_ich8lan,
5800 .release = e1000_release_nvm_ich8lan,
5801 .reload = e1000e_reload_nvm_generic,
5802 .update = e1000_update_nvm_checksum_ich8lan,
5803 .valid_led_default = e1000_valid_led_default_ich8lan,
5804 .validate = e1000_validate_nvm_checksum_ich8lan,
5805 .write = e1000_write_nvm_ich8lan,
5808 static const struct e1000_nvm_operations spt_nvm_ops = {
5809 .acquire = e1000_acquire_nvm_ich8lan,
5810 .release = e1000_release_nvm_ich8lan,
5811 .read = e1000_read_nvm_spt,
5812 .update = e1000_update_nvm_checksum_spt,
5813 .reload = e1000e_reload_nvm_generic,
5814 .valid_led_default = e1000_valid_led_default_ich8lan,
5815 .validate = e1000_validate_nvm_checksum_ich8lan,
5816 .write = e1000_write_nvm_ich8lan,
5819 const struct e1000_info e1000_ich8_info = {
5820 .mac = e1000_ich8lan,
5821 .flags = FLAG_HAS_WOL
5823 | FLAG_HAS_CTRLEXT_ON_LOAD
5828 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5829 .get_variants = e1000_get_variants_ich8lan,
5830 .mac_ops = &ich8_mac_ops,
5831 .phy_ops = &ich8_phy_ops,
5832 .nvm_ops = &ich8_nvm_ops,
5835 const struct e1000_info e1000_ich9_info = {
5836 .mac = e1000_ich9lan,
5837 .flags = FLAG_HAS_JUMBO_FRAMES
5840 | FLAG_HAS_CTRLEXT_ON_LOAD
5845 .max_hw_frame_size = DEFAULT_JUMBO,
5846 .get_variants = e1000_get_variants_ich8lan,
5847 .mac_ops = &ich8_mac_ops,
5848 .phy_ops = &ich8_phy_ops,
5849 .nvm_ops = &ich8_nvm_ops,
5852 const struct e1000_info e1000_ich10_info = {
5853 .mac = e1000_ich10lan,
5854 .flags = FLAG_HAS_JUMBO_FRAMES
5857 | FLAG_HAS_CTRLEXT_ON_LOAD
5862 .max_hw_frame_size = DEFAULT_JUMBO,
5863 .get_variants = e1000_get_variants_ich8lan,
5864 .mac_ops = &ich8_mac_ops,
5865 .phy_ops = &ich8_phy_ops,
5866 .nvm_ops = &ich8_nvm_ops,
5869 const struct e1000_info e1000_pch_info = {
5870 .mac = e1000_pchlan,
5871 .flags = FLAG_IS_ICH
5873 | FLAG_HAS_CTRLEXT_ON_LOAD
5876 | FLAG_HAS_JUMBO_FRAMES
5877 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5879 .flags2 = FLAG2_HAS_PHY_STATS,
5881 .max_hw_frame_size = 4096,
5882 .get_variants = e1000_get_variants_ich8lan,
5883 .mac_ops = &ich8_mac_ops,
5884 .phy_ops = &ich8_phy_ops,
5885 .nvm_ops = &ich8_nvm_ops,
5888 const struct e1000_info e1000_pch2_info = {
5889 .mac = e1000_pch2lan,
5890 .flags = FLAG_IS_ICH
5892 | FLAG_HAS_HW_TIMESTAMP
5893 | FLAG_HAS_CTRLEXT_ON_LOAD
5896 | FLAG_HAS_JUMBO_FRAMES
5898 .flags2 = FLAG2_HAS_PHY_STATS
5900 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5902 .max_hw_frame_size = 9022,
5903 .get_variants = e1000_get_variants_ich8lan,
5904 .mac_ops = &ich8_mac_ops,
5905 .phy_ops = &ich8_phy_ops,
5906 .nvm_ops = &ich8_nvm_ops,
5909 const struct e1000_info e1000_pch_lpt_info = {
5910 .mac = e1000_pch_lpt,
5911 .flags = FLAG_IS_ICH
5913 | FLAG_HAS_HW_TIMESTAMP
5914 | FLAG_HAS_CTRLEXT_ON_LOAD
5917 | FLAG_HAS_JUMBO_FRAMES
5919 .flags2 = FLAG2_HAS_PHY_STATS
5921 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5923 .max_hw_frame_size = 9022,
5924 .get_variants = e1000_get_variants_ich8lan,
5925 .mac_ops = &ich8_mac_ops,
5926 .phy_ops = &ich8_phy_ops,
5927 .nvm_ops = &ich8_nvm_ops,
5930 const struct e1000_info e1000_pch_spt_info = {
5931 .mac = e1000_pch_spt,
5932 .flags = FLAG_IS_ICH
5934 | FLAG_HAS_HW_TIMESTAMP
5935 | FLAG_HAS_CTRLEXT_ON_LOAD
5938 | FLAG_HAS_JUMBO_FRAMES
5940 .flags2 = FLAG2_HAS_PHY_STATS
5943 .max_hw_frame_size = 9022,
5944 .get_variants = e1000_get_variants_ich8lan,
5945 .mac_ops = &ich8_mac_ops,
5946 .phy_ops = &ich8_phy_ops,
5947 .nvm_ops = &spt_nvm_ops,
5950 const struct e1000_info e1000_pch_cnp_info = {
5951 .mac = e1000_pch_cnp,
5952 .flags = FLAG_IS_ICH
5954 | FLAG_HAS_HW_TIMESTAMP
5955 | FLAG_HAS_CTRLEXT_ON_LOAD
5958 | FLAG_HAS_JUMBO_FRAMES
5960 .flags2 = FLAG2_HAS_PHY_STATS
5963 .max_hw_frame_size = 9022,
5964 .get_variants = e1000_get_variants_ich8lan,
5965 .mac_ops = &ich8_mac_ops,
5966 .phy_ops = &ich8_phy_ops,
5967 .nvm_ops = &spt_nvm_ops,