drivers/net/ethernet/intel/e1000e/hw.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
   3
   4 #ifndef _E1000_HW_H_
   5 #define _E1000_HW_H_
   6
   7 #include "regs.h"
   8 #include "defines.h"
   9
  10 struct e1000_hw;
  11
  12 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  13 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  14 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  15 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  16 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  17 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  18 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  19 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  20 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  21 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  22 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  23 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  24 #define E1000_DEV_ID_82572EI                    0x10B9
  25 #define E1000_DEV_ID_82573E                     0x108B
  26 #define E1000_DEV_ID_82573E_IAMT                0x108C
  27 #define E1000_DEV_ID_82573L                     0x109A
  28 #define E1000_DEV_ID_82574L                     0x10D3
  29 #define E1000_DEV_ID_82574LA                    0x10F6
  30 #define E1000_DEV_ID_82583V                     0x150C
  31 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
  32 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
  33 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
  34 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
  35 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
  36 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
  37 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
  38 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
  39 #define E1000_DEV_ID_ICH8_IFE                   0x104C
  40 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
  41 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
  42 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
  43 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
  44 #define E1000_DEV_ID_ICH9_BM                    0x10E5
  45 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
  46 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
  47 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
  48 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
  49 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
  50 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
  51 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
  52 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
  53 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
  54 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
  55 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
  56 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
  57 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
  58 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
  59 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
  60 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
  61 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
  62 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
  63 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
  64 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
  65 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
  66 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
  67 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
  68 #define E1000_DEV_ID_PCH_I218_LM2               0x15A0
  69 #define E1000_DEV_ID_PCH_I218_V2                0x15A1
  70 #define E1000_DEV_ID_PCH_I218_LM3               0x15A2  /* Wildcat Point PCH */
  71 #define E1000_DEV_ID_PCH_I218_V3                0x15A3  /* Wildcat Point PCH */
  72 #define E1000_DEV_ID_PCH_SPT_I219_LM            0x156F  /* SPT PCH */
  73 #define E1000_DEV_ID_PCH_SPT_I219_V             0x1570  /* SPT PCH */
  74 #define E1000_DEV_ID_PCH_SPT_I219_LM2           0x15B7  /* SPT-H PCH */
  75 #define E1000_DEV_ID_PCH_SPT_I219_V2            0x15B8  /* SPT-H PCH */
  76 #define E1000_DEV_ID_PCH_LBG_I219_LM3           0x15B9  /* LBG PCH */
  77 #define E1000_DEV_ID_PCH_SPT_I219_LM4           0x15D7
  78 #define E1000_DEV_ID_PCH_SPT_I219_V4            0x15D8
  79 #define E1000_DEV_ID_PCH_SPT_I219_LM5           0x15E3
  80 #define E1000_DEV_ID_PCH_SPT_I219_V5            0x15D6
  81 #define E1000_DEV_ID_PCH_CNP_I219_LM6           0x15BD
  82 #define E1000_DEV_ID_PCH_CNP_I219_V6            0x15BE
  83 #define E1000_DEV_ID_PCH_CNP_I219_LM7           0x15BB
  84 #define E1000_DEV_ID_PCH_CNP_I219_V7            0x15BC
  85 #define E1000_DEV_ID_PCH_ICP_I219_LM8           0x15DF
  86 #define E1000_DEV_ID_PCH_ICP_I219_V8            0x15E0
  87 #define E1000_DEV_ID_PCH_ICP_I219_LM9           0x15E1
  88 #define E1000_DEV_ID_PCH_ICP_I219_V9            0x15E2
  89
  90 #define E1000_REVISION_4        4
  91
  92 #define E1000_FUNC_1            1
  93
  94 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
  95 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
  96
  97 enum e1000_mac_type {
  98         e1000_82571,
  99         e1000_82572,
 100         e1000_82573,
 101         e1000_82574,
 102         e1000_82583,
 103         e1000_80003es2lan,
 104         e1000_ich8lan,
 105         e1000_ich9lan,
 106         e1000_ich10lan,
 107         e1000_pchlan,
 108         e1000_pch2lan,
 109         e1000_pch_lpt,
 110         e1000_pch_spt,
 111         e1000_pch_cnp,
 112 };
 113
 114 enum e1000_media_type {
 115         e1000_media_type_unknown = 0,
 116         e1000_media_type_copper = 1,
 117         e1000_media_type_fiber = 2,
 118         e1000_media_type_internal_serdes = 3,
 119         e1000_num_media_types
 120 };
 121
 122 enum e1000_nvm_type {
 123         e1000_nvm_unknown = 0,
 124         e1000_nvm_none,
 125         e1000_nvm_eeprom_spi,
 126         e1000_nvm_flash_hw,
 127         e1000_nvm_flash_sw
 128 };
 129
 130 enum e1000_nvm_override {
 131         e1000_nvm_override_none = 0,
 132         e1000_nvm_override_spi_small,
 133         e1000_nvm_override_spi_large
 134 };
 135
 136 enum e1000_phy_type {
 137         e1000_phy_unknown = 0,
 138         e1000_phy_none,
 139         e1000_phy_m88,
 140         e1000_phy_igp,
 141         e1000_phy_igp_2,
 142         e1000_phy_gg82563,
 143         e1000_phy_igp_3,
 144         e1000_phy_ife,
 145         e1000_phy_bm,
 146         e1000_phy_82578,
 147         e1000_phy_82577,
 148         e1000_phy_82579,
 149         e1000_phy_i217,
 150 };
 151
 152 enum e1000_bus_width {
 153         e1000_bus_width_unknown = 0,
 154         e1000_bus_width_pcie_x1,
 155         e1000_bus_width_pcie_x2,
 156         e1000_bus_width_pcie_x4 = 4,
 157         e1000_bus_width_pcie_x8 = 8,
 158         e1000_bus_width_32,
 159         e1000_bus_width_64,
 160         e1000_bus_width_reserved
 161 };
 162
 163 enum e1000_1000t_rx_status {
 164         e1000_1000t_rx_status_not_ok = 0,
 165         e1000_1000t_rx_status_ok,
 166         e1000_1000t_rx_status_undefined = 0xFF
 167 };
 168
 169 enum e1000_rev_polarity {
 170         e1000_rev_polarity_normal = 0,
 171         e1000_rev_polarity_reversed,
 172         e1000_rev_polarity_undefined = 0xFF
 173 };
 174
 175 enum e1000_fc_mode {
 176         e1000_fc_none = 0,
 177         e1000_fc_rx_pause,
 178         e1000_fc_tx_pause,
 179         e1000_fc_full,
 180         e1000_fc_default = 0xFF
 181 };
 182
 183 enum e1000_ms_type {
 184         e1000_ms_hw_default = 0,
 185         e1000_ms_force_master,
 186         e1000_ms_force_slave,
 187         e1000_ms_auto
 188 };
 189
 190 enum e1000_smart_speed {
 191         e1000_smart_speed_default = 0,
 192         e1000_smart_speed_on,
 193         e1000_smart_speed_off
 194 };
 195
 196 enum e1000_serdes_link_state {
 197         e1000_serdes_link_down = 0,
 198         e1000_serdes_link_autoneg_progress,
 199         e1000_serdes_link_autoneg_complete,
 200         e1000_serdes_link_forced_up
 201 };
 202
 203 /* Receive Descriptor - Extended */
 204 union e1000_rx_desc_extended {
 205         struct {
 206                 __le64 buffer_addr;
 207                 __le64 reserved;
 208         } read;
 209         struct {
 210                 struct {
 211                         __le32 mrq;           /* Multiple Rx Queues */
 212                         union {
 213                                 __le32 rss;         /* RSS Hash */
 214                                 struct {
 215                                         __le16 ip_id;  /* IP id */
 216                                         __le16 csum;   /* Packet Checksum */
 217                                 } csum_ip;
 218                         } hi_dword;
 219                 } lower;
 220                 struct {
 221                         __le32 status_error;     /* ext status/error */
 222                         __le16 length;
 223                         __le16 vlan;         /* VLAN tag */
 224                 } upper;
 225         } wb;  /* writeback */
 226 };
 227
 228 #define MAX_PS_BUFFERS 4
 229
 230 /* Number of packet split data buffers (not including the header buffer) */
 231 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 232
 233 /* Receive Descriptor - Packet Split */
 234 union e1000_rx_desc_packet_split {
 235         struct {
 236                 /* one buffer for protocol header(s), three data buffers */
 237                 __le64 buffer_addr[MAX_PS_BUFFERS];
 238         } read;
 239         struct {
 240                 struct {
 241                         __le32 mrq;           /* Multiple Rx Queues */
 242                         union {
 243                                 __le32 rss;           /* RSS Hash */
 244                                 struct {
 245                                         __le16 ip_id;    /* IP id */
 246                                         __le16 csum;     /* Packet Checksum */
 247                                 } csum_ip;
 248                         } hi_dword;
 249                 } lower;
 250                 struct {
 251                         __le32 status_error;     /* ext status/error */
 252                         __le16 length0;   /* length of buffer 0 */
 253                         __le16 vlan;         /* VLAN tag */
 254                 } middle;
 255                 struct {
 256                         __le16 header_status;
 257                         /* length of buffers 1-3 */
 258                         __le16 length[PS_PAGE_BUFFERS];
 259                 } upper;
 260                 __le64 reserved;
 261         } wb; /* writeback */
 262 };
 263
 264 /* Transmit Descriptor */
 265 struct e1000_tx_desc {
 266         __le64 buffer_addr;      /* Address of the descriptor's data buffer */
 267         union {
 268                 __le32 data;
 269                 struct {
 270                         __le16 length;    /* Data buffer length */
 271                         u8 cso; /* Checksum offset */
 272                         u8 cmd; /* Descriptor control */
 273                 } flags;
 274         } lower;
 275         union {
 276                 __le32 data;
 277                 struct {
 278                         u8 status;     /* Descriptor status */
 279                         u8 css; /* Checksum start */
 280                         __le16 special;
 281                 } fields;
 282         } upper;
 283 };
 284
 285 /* Offload Context Descriptor */
 286 struct e1000_context_desc {
 287         union {
 288                 __le32 ip_config;
 289                 struct {
 290                         u8 ipcss;      /* IP checksum start */
 291                         u8 ipcso;      /* IP checksum offset */
 292                         __le16 ipcse;     /* IP checksum end */
 293                 } ip_fields;
 294         } lower_setup;
 295         union {
 296                 __le32 tcp_config;
 297                 struct {
 298                         u8 tucss;      /* TCP checksum start */
 299                         u8 tucso;      /* TCP checksum offset */
 300                         __le16 tucse;     /* TCP checksum end */
 301                 } tcp_fields;
 302         } upper_setup;
 303         __le32 cmd_and_length;
 304         union {
 305                 __le32 data;
 306                 struct {
 307                         u8 status;     /* Descriptor status */
 308                         u8 hdr_len;    /* Header length */
 309                         __le16 mss;       /* Maximum segment size */
 310                 } fields;
 311         } tcp_seg_setup;
 312 };
 313
 314 /* Offload data descriptor */
 315 struct e1000_data_desc {
 316         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 317         union {
 318                 __le32 data;
 319                 struct {
 320                         __le16 length;    /* Data buffer length */
 321                         u8 typ_len_ext;
 322                         u8 cmd;
 323                 } flags;
 324         } lower;
 325         union {
 326                 __le32 data;
 327                 struct {
 328                         u8 status;     /* Descriptor status */
 329                         u8 popts;      /* Packet Options */
 330                         __le16 special;
 331                 } fields;
 332         } upper;
 333 };
 334
 335 /* Statistics counters collected by the MAC */
 336 struct e1000_hw_stats {
 337         u64 crcerrs;
 338         u64 algnerrc;
 339         u64 symerrs;
 340         u64 rxerrc;
 341         u64 mpc;
 342         u64 scc;
 343         u64 ecol;
 344         u64 mcc;
 345         u64 latecol;
 346         u64 colc;
 347         u64 dc;
 348         u64 tncrs;
 349         u64 sec;
 350         u64 cexterr;
 351         u64 rlec;
 352         u64 xonrxc;
 353         u64 xontxc;
 354         u64 xoffrxc;
 355         u64 xofftxc;
 356         u64 fcruc;
 357         u64 prc64;
 358         u64 prc127;
 359         u64 prc255;
 360         u64 prc511;
 361         u64 prc1023;
 362         u64 prc1522;
 363         u64 gprc;
 364         u64 bprc;
 365         u64 mprc;
 366         u64 gptc;
 367         u64 gorc;
 368         u64 gotc;
 369         u64 rnbc;
 370         u64 ruc;
 371         u64 rfc;
 372         u64 roc;
 373         u64 rjc;
 374         u64 mgprc;
 375         u64 mgpdc;
 376         u64 mgptc;
 377         u64 tor;
 378         u64 tot;
 379         u64 tpr;
 380         u64 tpt;
 381         u64 ptc64;
 382         u64 ptc127;
 383         u64 ptc255;
 384         u64 ptc511;
 385         u64 ptc1023;
 386         u64 ptc1522;
 387         u64 mptc;
 388         u64 bptc;
 389         u64 tsctc;
 390         u64 tsctfc;
 391         u64 iac;
 392         u64 icrxptc;
 393         u64 icrxatc;
 394         u64 ictxptc;
 395         u64 ictxatc;
 396         u64 ictxqec;
 397         u64 ictxqmtc;
 398         u64 icrxdmtc;
 399         u64 icrxoc;
 400 };
 401
 402 struct e1000_phy_stats {
 403         u32 idle_errors;
 404         u32 receive_errors;
 405 };
 406
 407 struct e1000_host_mng_dhcp_cookie {
 408         u32 signature;
 409         u8 status;
 410         u8 reserved0;
 411         u16 vlan_id;
 412         u32 reserved1;
 413         u16 reserved2;
 414         u8 reserved3;
 415         u8 checksum;
 416 };
 417
 418 /* Host Interface "Rev 1" */
 419 struct e1000_host_command_header {
 420         u8 command_id;
 421         u8 command_length;
 422         u8 command_options;
 423         u8 checksum;
 424 };
 425
 426 #define E1000_HI_MAX_DATA_LENGTH        252
 427 struct e1000_host_command_info {
 428         struct e1000_host_command_header command_header;
 429         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 430 };
 431
 432 /* Host Interface "Rev 2" */
 433 struct e1000_host_mng_command_header {
 434         u8 command_id;
 435         u8 checksum;
 436         u16 reserved1;
 437         u16 reserved2;
 438         u16 command_length;
 439 };
 440
 441 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 442 struct e1000_host_mng_command_info {
 443         struct e1000_host_mng_command_header command_header;
 444         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 445 };
 446
 447 #include "mac.h"
 448 #include "phy.h"
 449 #include "nvm.h"
 450 #include "manage.h"
 451
 452 /* Function pointers for the MAC. */
 453 struct e1000_mac_operations {
 454         s32  (*id_led_init)(struct e1000_hw *);
 455         s32  (*blink_led)(struct e1000_hw *);
 456         bool (*check_mng_mode)(struct e1000_hw *);
 457         s32  (*check_for_link)(struct e1000_hw *);
 458         s32  (*cleanup_led)(struct e1000_hw *);
 459         void (*clear_hw_cntrs)(struct e1000_hw *);
 460         void (*clear_vfta)(struct e1000_hw *);
 461         s32  (*get_bus_info)(struct e1000_hw *);
 462         void (*set_lan_id)(struct e1000_hw *);
 463         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 464         s32  (*led_on)(struct e1000_hw *);
 465         s32  (*led_off)(struct e1000_hw *);
 466         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 467         s32  (*reset_hw)(struct e1000_hw *);
 468         s32  (*init_hw)(struct e1000_hw *);
 469         s32  (*setup_link)(struct e1000_hw *);
 470         s32  (*setup_physical_interface)(struct e1000_hw *);
 471         s32  (*setup_led)(struct e1000_hw *);
 472         void (*write_vfta)(struct e1000_hw *, u32, u32);
 473         void (*config_collision_dist)(struct e1000_hw *);
 474         int  (*rar_set)(struct e1000_hw *, u8 *, u32);
 475         s32  (*read_mac_addr)(struct e1000_hw *);
 476         u32  (*rar_get_count)(struct e1000_hw *);
 477 };
 478
 479 /* When to use various PHY register access functions:
 480  *
 481  *                 Func   Caller
 482  *   Function      Does   Does    When to use
 483  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 484  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 485  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 486  *                                on different pages
 487  *   X_reg_page    A      L,P     for multiple accesses of different regs
 488  *                                on the same page
 489  *
 490  * Where X=[read|write], L=locking, P=sets page, A=register access
 491  *
 492  */
 493 struct e1000_phy_operations {
 494         s32  (*acquire)(struct e1000_hw *);
 495         s32  (*cfg_on_link_up)(struct e1000_hw *);
 496         s32  (*check_polarity)(struct e1000_hw *);
 497         s32  (*check_reset_block)(struct e1000_hw *);
 498         s32  (*commit)(struct e1000_hw *);
 499         s32  (*force_speed_duplex)(struct e1000_hw *);
 500         s32  (*get_cfg_done)(struct e1000_hw *hw);
 501         s32  (*get_cable_length)(struct e1000_hw *);
 502         s32  (*get_info)(struct e1000_hw *);
 503         s32  (*set_page)(struct e1000_hw *, u16);
 504         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 505         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 506         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 507         void (*release)(struct e1000_hw *);
 508         s32  (*reset)(struct e1000_hw *);
 509         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 510         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 511         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 512         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 513         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 514         void (*power_up)(struct e1000_hw *);
 515         void (*power_down)(struct e1000_hw *);
 516 };
 517
 518 /* Function pointers for the NVM. */
 519 struct e1000_nvm_operations {
 520         s32  (*acquire)(struct e1000_hw *);
 521         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 522         void (*release)(struct e1000_hw *);
 523         void (*reload)(struct e1000_hw *);
 524         s32  (*update)(struct e1000_hw *);
 525         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 526         s32  (*validate)(struct e1000_hw *);
 527         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 528 };
 529
 530 struct e1000_mac_info {
 531         struct e1000_mac_operations ops;
 532         u8 addr[ETH_ALEN];
 533         u8 perm_addr[ETH_ALEN];
 534
 535         enum e1000_mac_type type;
 536
 537         u32 collision_delta;
 538         u32 ledctl_default;
 539         u32 ledctl_mode1;
 540         u32 ledctl_mode2;
 541         u32 mc_filter_type;
 542         u32 tx_packet_delta;
 543         u32 txcw;
 544
 545         u16 current_ifs_val;
 546         u16 ifs_max_val;
 547         u16 ifs_min_val;
 548         u16 ifs_ratio;
 549         u16 ifs_step_size;
 550         u16 mta_reg_count;
 551
 552         /* Maximum size of the MTA register table in all supported adapters */
 553 #define MAX_MTA_REG 128
 554         u32 mta_shadow[MAX_MTA_REG];
 555         u16 rar_entry_count;
 556
 557         u8 forced_speed_duplex;
 558
 559         bool adaptive_ifs;
 560         bool has_fwsm;
 561         bool arc_subsystem_valid;
 562         bool autoneg;
 563         bool autoneg_failed;
 564         bool get_link_status;
 565         bool in_ifs_mode;
 566         bool serdes_has_link;
 567         bool tx_pkt_filtering;
 568         enum e1000_serdes_link_state serdes_link_state;
 569 };
 570
 571 struct e1000_phy_info {
 572         struct e1000_phy_operations ops;
 573
 574         enum e1000_phy_type type;
 575
 576         enum e1000_1000t_rx_status local_rx;
 577         enum e1000_1000t_rx_status remote_rx;
 578         enum e1000_ms_type ms_type;
 579         enum e1000_ms_type original_ms_type;
 580         enum e1000_rev_polarity cable_polarity;
 581         enum e1000_smart_speed smart_speed;
 582
 583         u32 addr;
 584         u32 id;
 585         u32 reset_delay_us;     /* in usec */
 586         u32 revision;
 587
 588         enum e1000_media_type media_type;
 589
 590         u16 autoneg_advertised;
 591         u16 autoneg_mask;
 592         u16 cable_length;
 593         u16 max_cable_length;
 594         u16 min_cable_length;
 595
 596         u8 mdix;
 597
 598         bool disable_polarity_correction;
 599         bool is_mdix;
 600         bool polarity_correction;
 601         bool speed_downgraded;
 602         bool autoneg_wait_to_complete;
 603 };
 604
 605 struct e1000_nvm_info {
 606         struct e1000_nvm_operations ops;
 607
 608         enum e1000_nvm_type type;
 609         enum e1000_nvm_override override;
 610
 611         u32 flash_bank_size;
 612         u32 flash_base_addr;
 613
 614         u16 word_size;
 615         u16 delay_usec;
 616         u16 address_bits;
 617         u16 opcode_bits;
 618         u16 page_size;
 619 };
 620
 621 struct e1000_bus_info {
 622         enum e1000_bus_width width;
 623
 624         u16 func;
 625 };
 626
 627 struct e1000_fc_info {
 628         u32 high_water;          /* Flow control high-water mark */
 629         u32 low_water;           /* Flow control low-water mark */
 630         u16 pause_time;          /* Flow control pause timer */
 631         u16 refresh_time;        /* Flow control refresh timer */
 632         bool send_xon;           /* Flow control send XON */
 633         bool strict_ieee;        /* Strict IEEE mode */
 634         enum e1000_fc_mode current_mode; /* FC mode in effect */
 635         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 636 };
 637
 638 struct e1000_dev_spec_82571 {
 639         bool laa_is_present;
 640         u32 smb_counter;
 641 };
 642
 643 struct e1000_dev_spec_80003es2lan {
 644         bool mdic_wa_enable;
 645 };
 646
 647 struct e1000_shadow_ram {
 648         u16 value;
 649         bool modified;
 650 };
 651
 652 #define E1000_ICH8_SHADOW_RAM_WORDS             2048
 653
 654 /* I218 PHY Ultra Low Power (ULP) states */
 655 enum e1000_ulp_state {
 656         e1000_ulp_state_unknown,
 657         e1000_ulp_state_off,
 658         e1000_ulp_state_on,
 659 };
 660
 661 struct e1000_dev_spec_ich8lan {
 662         bool kmrn_lock_loss_workaround_enabled;
 663         struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
 664         bool nvm_k1_enabled;
 665         bool eee_disable;
 666         u16 eee_lp_ability;
 667         enum e1000_ulp_state ulp_state;
 668 };
 669
 670 struct e1000_hw {
 671         struct e1000_adapter *adapter;
 672
 673         void __iomem *hw_addr;
 674         void __iomem *flash_address;
 675
 676         struct e1000_mac_info mac;
 677         struct e1000_fc_info fc;
 678         struct e1000_phy_info phy;
 679         struct e1000_nvm_info nvm;
 680         struct e1000_bus_info bus;
 681         struct e1000_host_mng_dhcp_cookie mng_cookie;
 682
 683         union {
 684                 struct e1000_dev_spec_82571 e82571;
 685                 struct e1000_dev_spec_80003es2lan e80003es2lan;
 686                 struct e1000_dev_spec_ich8lan ich8lan;
 687         } dev_spec;
 688 };
 689
 690 #include "82571.h"
 691 #include "80003es2lan.h"
 692 #include "ich8lan.h"
 693
 694 #endif