1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Huawei HiNIC PCI Express Linux driver
4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
7 #ifndef HINIC_HW_QP_CTXT_H
8 #define HINIC_HW_QP_CTXT_H
10 #include <linux/types.h>
12 #include "hinic_hw_cmdq.h"
14 #define HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_SHIFT 13
15 #define HINIC_SQ_CTXT_CEQ_ATTR_EN_SHIFT 23
17 #define HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK 0x3FF
18 #define HINIC_SQ_CTXT_CEQ_ATTR_EN_MASK 0x1
20 #define HINIC_SQ_CTXT_CEQ_ATTR_SET(val, member) \
21 (((u32)(val) & HINIC_SQ_CTXT_CEQ_ATTR_##member##_MASK) \
22 << HINIC_SQ_CTXT_CEQ_ATTR_##member##_SHIFT)
24 #define HINIC_SQ_CTXT_CI_IDX_SHIFT 11
25 #define HINIC_SQ_CTXT_CI_WRAPPED_SHIFT 23
27 #define HINIC_SQ_CTXT_CI_IDX_MASK 0xFFF
28 #define HINIC_SQ_CTXT_CI_WRAPPED_MASK 0x1
30 #define HINIC_SQ_CTXT_CI_SET(val, member) \
31 (((u32)(val) & HINIC_SQ_CTXT_CI_##member##_MASK) \
32 << HINIC_SQ_CTXT_CI_##member##_SHIFT)
34 #define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
35 #define HINIC_SQ_CTXT_WQ_PAGE_PI_SHIFT 20
37 #define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFF
38 #define HINIC_SQ_CTXT_WQ_PAGE_PI_MASK 0xFFF
40 #define HINIC_SQ_CTXT_WQ_PAGE_SET(val, member) \
41 (((u32)(val) & HINIC_SQ_CTXT_WQ_PAGE_##member##_MASK) \
42 << HINIC_SQ_CTXT_WQ_PAGE_##member##_SHIFT)
44 #define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
45 #define HINIC_SQ_CTXT_PREF_CACHE_MAX_SHIFT 14
46 #define HINIC_SQ_CTXT_PREF_CACHE_MIN_SHIFT 25
48 #define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFF
49 #define HINIC_SQ_CTXT_PREF_CACHE_MAX_MASK 0x7FF
50 #define HINIC_SQ_CTXT_PREF_CACHE_MIN_MASK 0x7F
52 #define HINIC_SQ_CTXT_PREF_WQ_HI_PFN_SHIFT 0
53 #define HINIC_SQ_CTXT_PREF_CI_SHIFT 20
55 #define HINIC_SQ_CTXT_PREF_WQ_HI_PFN_MASK 0xFFFFF
56 #define HINIC_SQ_CTXT_PREF_CI_MASK 0xFFF
58 #define HINIC_SQ_CTXT_PREF_SET(val, member) \
59 (((u32)(val) & HINIC_SQ_CTXT_PREF_##member##_MASK) \
60 << HINIC_SQ_CTXT_PREF_##member##_SHIFT)
62 #define HINIC_SQ_CTXT_WQ_BLOCK_HI_PFN_SHIFT 0
64 #define HINIC_SQ_CTXT_WQ_BLOCK_HI_PFN_MASK 0x7FFFFF
66 #define HINIC_SQ_CTXT_WQ_BLOCK_SET(val, member) \
67 (((u32)(val) & HINIC_SQ_CTXT_WQ_BLOCK_##member##_MASK) \
68 << HINIC_SQ_CTXT_WQ_BLOCK_##member##_SHIFT)
70 #define HINIC_RQ_CTXT_CEQ_ATTR_EN_SHIFT 0
71 #define HINIC_RQ_CTXT_CEQ_ATTR_WRAPPED_SHIFT 1
73 #define HINIC_RQ_CTXT_CEQ_ATTR_EN_MASK 0x1
74 #define HINIC_RQ_CTXT_CEQ_ATTR_WRAPPED_MASK 0x1
76 #define HINIC_RQ_CTXT_CEQ_ATTR_SET(val, member) \
77 (((u32)(val) & HINIC_RQ_CTXT_CEQ_ATTR_##member##_MASK) \
78 << HINIC_RQ_CTXT_CEQ_ATTR_##member##_SHIFT)
80 #define HINIC_RQ_CTXT_PI_IDX_SHIFT 0
81 #define HINIC_RQ_CTXT_PI_INTR_SHIFT 22
83 #define HINIC_RQ_CTXT_PI_IDX_MASK 0xFFF
84 #define HINIC_RQ_CTXT_PI_INTR_MASK 0x3FF
86 #define HINIC_RQ_CTXT_PI_SET(val, member) \
87 (((u32)(val) & HINIC_RQ_CTXT_PI_##member##_MASK) << \
88 HINIC_RQ_CTXT_PI_##member##_SHIFT)
90 #define HINIC_RQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
91 #define HINIC_RQ_CTXT_WQ_PAGE_CI_SHIFT 20
93 #define HINIC_RQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFF
94 #define HINIC_RQ_CTXT_WQ_PAGE_CI_MASK 0xFFF
96 #define HINIC_RQ_CTXT_WQ_PAGE_SET(val, member) \
97 (((u32)(val) & HINIC_RQ_CTXT_WQ_PAGE_##member##_MASK) << \
98 HINIC_RQ_CTXT_WQ_PAGE_##member##_SHIFT)
100 #define HINIC_RQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
101 #define HINIC_RQ_CTXT_PREF_CACHE_MAX_SHIFT 14
102 #define HINIC_RQ_CTXT_PREF_CACHE_MIN_SHIFT 25
104 #define HINIC_RQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFF
105 #define HINIC_RQ_CTXT_PREF_CACHE_MAX_MASK 0x7FF
106 #define HINIC_RQ_CTXT_PREF_CACHE_MIN_MASK 0x7F
108 #define HINIC_RQ_CTXT_PREF_WQ_HI_PFN_SHIFT 0
109 #define HINIC_RQ_CTXT_PREF_CI_SHIFT 20
111 #define HINIC_RQ_CTXT_PREF_WQ_HI_PFN_MASK 0xFFFFF
112 #define HINIC_RQ_CTXT_PREF_CI_MASK 0xFFF
114 #define HINIC_RQ_CTXT_PREF_SET(val, member) \
115 (((u32)(val) & HINIC_RQ_CTXT_PREF_##member##_MASK) << \
116 HINIC_RQ_CTXT_PREF_##member##_SHIFT)
118 #define HINIC_RQ_CTXT_WQ_BLOCK_HI_PFN_SHIFT 0
120 #define HINIC_RQ_CTXT_WQ_BLOCK_HI_PFN_MASK 0x7FFFFF
122 #define HINIC_RQ_CTXT_WQ_BLOCK_SET(val, member) \
123 (((u32)(val) & HINIC_RQ_CTXT_WQ_BLOCK_##member##_MASK) << \
124 HINIC_RQ_CTXT_WQ_BLOCK_##member##_SHIFT)
126 #define HINIC_SQ_CTXT_SIZE(num_sqs) (sizeof(struct hinic_qp_ctxt_header) \
127 + (num_sqs) * sizeof(struct hinic_sq_ctxt))
129 #define HINIC_RQ_CTXT_SIZE(num_rqs) (sizeof(struct hinic_qp_ctxt_header) \
130 + (num_rqs) * sizeof(struct hinic_rq_ctxt))
132 #define HINIC_WQ_PAGE_PFN_SHIFT 12
133 #define HINIC_WQ_BLOCK_PFN_SHIFT 9
135 #define HINIC_WQ_PAGE_PFN(page_addr) ((page_addr) >> HINIC_WQ_PAGE_PFN_SHIFT)
136 #define HINIC_WQ_BLOCK_PFN(page_addr) ((page_addr) >> \
137 HINIC_WQ_BLOCK_PFN_SHIFT)
139 #define HINIC_Q_CTXT_MAX \
140 ((HINIC_CMDQ_BUF_SIZE - sizeof(struct hinic_qp_ctxt_header)) \
141 / sizeof(struct hinic_sq_ctxt))
143 enum hinic_qp_ctxt_type {
144 HINIC_QP_CTXT_TYPE_SQ,
145 HINIC_QP_CTXT_TYPE_RQ
148 struct hinic_qp_ctxt_header {
154 struct hinic_sq_ctxt {
164 u32 pref_wq_hi_pfn_ci;
174 struct hinic_rq_ctxt {
185 u32 pref_wq_hi_pfn_ci;
195 struct hinic_clean_queue_ctxt {
196 struct hinic_qp_ctxt_header cmdq_hdr;
200 struct hinic_sq_ctxt_block {
201 struct hinic_qp_ctxt_header hdr;
202 struct hinic_sq_ctxt sq_ctxt[HINIC_Q_CTXT_MAX];
205 struct hinic_rq_ctxt_block {
206 struct hinic_qp_ctxt_header hdr;
207 struct hinic_rq_ctxt rq_ctxt[HINIC_Q_CTXT_MAX];