1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Huawei HiNIC PCI Express Linux driver
4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
10 #include <linux/pci.h>
11 #include <linux/types.h>
12 #include <linux/bitops.h>
13 #include <net/devlink.h>
15 #include "hinic_hw_if.h"
16 #include "hinic_hw_eqs.h"
17 #include "hinic_hw_mgmt.h"
18 #include "hinic_hw_qp.h"
19 #include "hinic_hw_io.h"
20 #include "hinic_hw_mbox.h"
22 #define HINIC_MAX_QPS 32
24 #define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \
25 HINIC_MGMT_MSG_CMD_BASE)
27 #define HINIC_PF_SET_VF_ALREADY 0x4
28 #define HINIC_MGMT_STATUS_EXIST 0x6
29 #define HINIC_MGMT_CMD_UNSUPPORTED 0xFF
31 #define HINIC_CMD_VER_FUNC_ID 2
40 enum hw_ioctxt_set_cmdq_depth {
41 HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT,
42 HW_IOCTXT_SET_CMDQ_DEPTH_ENABLE,
46 HINIC_PORT_CMD_VF_REGISTER = 0x0,
47 HINIC_PORT_CMD_VF_UNREGISTER = 0x1,
49 HINIC_PORT_CMD_CHANGE_MTU = 0x2,
51 HINIC_PORT_CMD_ADD_VLAN = 0x3,
52 HINIC_PORT_CMD_DEL_VLAN = 0x4,
54 HINIC_PORT_CMD_SET_ETS = 0x7,
55 HINIC_PORT_CMD_GET_ETS = 0x8,
57 HINIC_PORT_CMD_SET_PFC = 0x5,
59 HINIC_PORT_CMD_SET_MAC = 0x9,
60 HINIC_PORT_CMD_GET_MAC = 0xA,
61 HINIC_PORT_CMD_DEL_MAC = 0xB,
63 HINIC_PORT_CMD_SET_RX_MODE = 0xC,
65 HINIC_PORT_CMD_SET_ANTI_ATTACK_RATE = 0xD,
67 HINIC_PORT_CMD_GET_PAUSE_INFO = 0x14,
68 HINIC_PORT_CMD_SET_PAUSE_INFO = 0x15,
70 HINIC_PORT_CMD_GET_LINK_STATE = 0x18,
72 HINIC_PORT_CMD_SET_LRO = 0x19,
74 HINIC_PORT_CMD_SET_RX_CSUM = 0x1A,
76 HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 0x1B,
78 HINIC_PORT_CMD_GET_PORT_STATISTICS = 0x1C,
80 HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 0x1D,
82 HINIC_PORT_CMD_GET_VPORT_STAT = 0x1E,
84 HINIC_PORT_CMD_CLEAN_VPORT_STAT = 0x1F,
86 HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 0x25,
88 HINIC_PORT_CMD_SET_PORT_STATE = 0x29,
89 HINIC_PORT_CMD_GET_PORT_STATE = 0x30,
91 HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 0x2B,
93 HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 0x2C,
95 HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 0x2D,
97 HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 0x2E,
99 HINIC_PORT_CMD_GET_RSS_CTX_TBL = 0x2F,
101 HINIC_PORT_CMD_SET_RSS_CTX_TBL = 0x30,
103 HINIC_PORT_CMD_RSS_TEMP_MGR = 0x31,
105 HINIC_PORT_CMD_RD_LINE_TBL = 0x39,
107 HINIC_PORT_CMD_RSS_CFG = 0x42,
109 HINIC_PORT_CMD_GET_PHY_TYPE = 0x44,
111 HINIC_PORT_CMD_FWCTXT_INIT = 0x45,
113 HINIC_PORT_CMD_GET_LOOPBACK_MODE = 0x48,
114 HINIC_PORT_CMD_SET_LOOPBACK_MODE = 0x49,
116 HINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE = 0x4A,
117 HINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE = 0x4B,
119 HINIC_PORT_CMD_ENABLE_SPOOFCHK = 0x4E,
121 HINIC_PORT_CMD_GET_MGMT_VERSION = 0x58,
123 HINIC_PORT_CMD_GET_PORT_TYPE = 0x5B,
125 HINIC_PORT_CMD_SET_FUNC_STATE = 0x5D,
127 HINIC_PORT_CMD_GET_PORT_ID_BY_FUNC_ID = 0x5E,
129 HINIC_PORT_CMD_GET_DMA_CS = 0x64,
130 HINIC_PORT_CMD_SET_DMA_CS = 0x65,
132 HINIC_PORT_CMD_GET_GLOBAL_QPN = 0x66,
134 HINIC_PORT_CMD_SET_VF_RATE = 0x69,
136 HINIC_PORT_CMD_SET_VF_VLAN = 0x6A,
138 HINIC_PORT_CMD_CLR_VF_VLAN = 0x6B,
140 HINIC_PORT_CMD_SET_TSO = 0x70,
142 HINIC_PORT_CMD_UPDATE_FW = 0x72,
144 HINIC_PORT_CMD_SET_RQ_IQ_MAP = 0x73,
146 HINIC_PORT_CMD_SET_PFC_THD = 0x75,
148 HINIC_PORT_CMD_LINK_STATUS_REPORT = 0xA0,
150 HINIC_PORT_CMD_SET_LOSSLESS_ETH = 0xA3,
152 HINIC_PORT_CMD_UPDATE_MAC = 0xA4,
154 HINIC_PORT_CMD_GET_CAP = 0xAA,
156 HINIC_PORT_CMD_UP_TC_ADD_FLOW = 0xAF,
157 HINIC_PORT_CMD_UP_TC_DEL_FLOW = 0xB0,
158 HINIC_PORT_CMD_UP_TC_GET_FLOW = 0xB1,
160 HINIC_PORT_CMD_UP_TC_FLUSH_TCAM = 0xB2,
162 HINIC_PORT_CMD_UP_TC_CTRL_TCAM_BLOCK = 0xB3,
164 HINIC_PORT_CMD_UP_TC_ENABLE = 0xB4,
166 HINIC_PORT_CMD_UP_TC_GET_TCAM_BLOCK = 0xB5,
168 HINIC_PORT_CMD_SET_IPSU_MAC = 0xCB,
169 HINIC_PORT_CMD_GET_IPSU_MAC = 0xCC,
171 HINIC_PORT_CMD_SET_XSFP_STATUS = 0xD4,
173 HINIC_PORT_CMD_GET_LINK_MODE = 0xD9,
175 HINIC_PORT_CMD_SET_SPEED = 0xDA,
177 HINIC_PORT_CMD_SET_AUTONEG = 0xDB,
179 HINIC_PORT_CMD_CLEAR_QP_RES = 0xDD,
181 HINIC_PORT_CMD_SET_SUPER_CQE = 0xDE,
183 HINIC_PORT_CMD_SET_VF_COS = 0xDF,
184 HINIC_PORT_CMD_GET_VF_COS = 0xE1,
186 HINIC_PORT_CMD_CABLE_PLUG_EVENT = 0xE5,
188 HINIC_PORT_CMD_LINK_ERR_EVENT = 0xE6,
190 HINIC_PORT_CMD_SET_COS_UP_MAP = 0xE8,
192 HINIC_PORT_CMD_RESET_LINK_CFG = 0xEB,
194 HINIC_PORT_CMD_GET_STD_SFP_INFO = 0xF0,
196 HINIC_PORT_CMD_FORCE_PKT_DROP = 0xF3,
198 HINIC_PORT_CMD_SET_LRO_TIMER = 0xF4,
200 HINIC_PORT_CMD_SET_VHD_CFG = 0xF7,
202 HINIC_PORT_CMD_SET_LINK_FOLLOW = 0xF8,
204 HINIC_PORT_CMD_SET_VF_MAX_MIN_RATE = 0xF9,
206 HINIC_PORT_CMD_GET_SFP_ABS = 0xFB,
208 HINIC_PORT_CMD_Q_FILTER = 0xFC,
210 HINIC_PORT_CMD_TCAM_FILTER = 0xFE,
212 HINIC_PORT_CMD_SET_VLAN_FILTER = 0xFF,
215 /* cmd of mgmt CPU message for HILINK module */
216 enum hinic_hilink_cmd {
217 HINIC_HILINK_CMD_GET_LINK_INFO = 0x3,
218 HINIC_HILINK_CMD_SET_LINK_SETTINGS = 0x8,
221 enum hinic_ucode_cmd {
222 HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT = 0,
223 HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,
224 HINIC_UCODE_CMD_ARM_SQ,
225 HINIC_UCODE_CMD_ARM_RQ,
226 HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,
227 HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE,
228 HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE,
229 HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE,
230 HINIC_UCODE_CMD_SET_IQ_ENABLE,
231 HINIC_UCODE_CMD_SET_RQ_FLUSH = 10
234 #define NIC_RSS_CMD_TEMP_ALLOC 0x01
235 #define NIC_RSS_CMD_TEMP_FREE 0x02
237 enum hinic_mgmt_msg_cmd {
238 HINIC_MGMT_MSG_CMD_BASE = 0xA0,
240 HINIC_MGMT_MSG_CMD_LINK_STATUS = 0xA0,
242 HINIC_MGMT_MSG_CMD_CABLE_PLUG_EVENT = 0xE5,
243 HINIC_MGMT_MSG_CMD_LINK_ERR_EVENT = 0xE6,
245 HINIC_MGMT_MSG_CMD_MAX,
248 enum hinic_cb_state {
249 HINIC_CB_ENABLED = BIT(0),
250 HINIC_CB_RUNNING = BIT(1),
253 enum hinic_res_state {
255 HINIC_RES_ACTIVE = 1,
258 struct hinic_cmd_fw_ctxt {
269 struct hinic_cmd_hw_ioctxt {
291 struct hinic_cmd_io_status {
302 struct hinic_cmd_clear_io_res {
312 struct hinic_cmd_set_res_state {
323 struct hinic_ceq_ctrl_reg {
334 struct hinic_cmd_base_qpn {
343 struct hinic_cmd_hw_ci {
362 struct hinic_cmd_l2nic_reset {
371 struct hinic_msix_config {
379 u8 coalesce_timer_cnt;
386 struct hinic_set_random_id {
397 struct hinic_board_info {
416 struct hinic_comm_board_info {
421 struct hinic_board_info info;
427 struct hinic_hwif *hwif;
428 struct msix_entry *msix_entries;
430 struct hinic_aeqs aeqs;
431 struct hinic_func_to_io func_to_io;
432 struct hinic_mbox_func_to_func *func_to_func;
434 struct hinic_cap nic_cap;
436 struct hinic_devlink_priv *devlink_dev;
439 struct hinic_nic_cb {
440 void (*handler)(void *handle, void *buf_in,
441 u16 in_size, void *buf_out,
445 unsigned long cb_state;
448 #define HINIC_COMM_SELF_CMD_MAX 4
450 typedef void (*comm_mgmt_self_msg_proc)(void *handle, void *buf_in, u16 in_size,
451 void *buf_out, u16 *out_size);
453 struct comm_mgmt_self_msg_sub_info {
455 comm_mgmt_self_msg_proc proc;
458 struct comm_mgmt_self_msg_info {
460 struct comm_mgmt_self_msg_sub_info info[HINIC_COMM_SELF_CMD_MAX];
463 struct hinic_pfhwdev {
464 struct hinic_hwdev hwdev;
466 struct hinic_pf_to_mgmt pf_to_mgmt;
468 struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD];
470 struct comm_mgmt_self_msg_info proc;
473 struct hinic_dev_cap {
492 union hinic_fault_hw_mgmt {
494 /* valid only type == FAULT_TYPE_CHIP */
501 /* func_id valid only if err_level == FAULT_LEVEL_SERIOUS_FLR */
506 /* valid only if type == FAULT_TYPE_UCODE */
517 /* valid only if type == FAULT_TYPE_MEM_RD_TIMEOUT ||
518 * FAULT_TYPE_MEM_WR_TIMEOUT
527 /* valid only if type == FAULT_TYPE_REG_RD_TIMEOUT ||
528 * FAULT_TYPE_REG_WR_TIMEOUT
538 /* 0: read; 1: write */
549 struct hinic_fault_event {
553 union hinic_fault_hw_mgmt event;
556 struct hinic_cmd_fault_event {
561 struct hinic_fault_event event;
564 enum hinic_fault_type {
567 FAULT_TYPE_MEM_RD_TIMEOUT,
568 FAULT_TYPE_MEM_WR_TIMEOUT,
569 FAULT_TYPE_REG_RD_TIMEOUT,
570 FAULT_TYPE_REG_WR_TIMEOUT,
571 FAULT_TYPE_PHY_FAULT,
575 enum hinic_fault_err_level {
577 FAULT_LEVEL_SERIOUS_RESET,
578 FAULT_LEVEL_SERIOUS_FLR,
580 FAULT_LEVEL_SUGGESTION,
584 struct hinic_mgmt_watchdog_info {
610 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev,
611 enum hinic_mgmt_msg_cmd cmd, void *handle,
612 void (*handler)(void *handle, void *buf_in,
613 u16 in_size, void *buf_out,
616 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev,
617 enum hinic_mgmt_msg_cmd cmd);
619 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd,
620 void *buf_in, u16 in_size, void *buf_out,
623 int hinic_hilink_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_hilink_cmd cmd,
624 void *buf_in, u16 in_size, void *buf_out,
627 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev, u16 sq_depth, u16 rq_depth);
629 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev);
631 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev, struct devlink *devlink);
633 void hinic_free_hwdev(struct hinic_hwdev *hwdev);
635 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev);
637 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i);
639 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i);
641 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index);
643 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index,
644 u8 pending_limit, u8 coalesc_timer,
645 u8 lli_timer_cfg, u8 lli_credit_limit,
648 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq,
649 u8 pending_limit, u8 coalesc_timer);
651 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index,
652 enum hinic_msix_state flag);
654 int hinic_set_interrupt_cfg(struct hinic_hwdev *hwdev,
655 struct hinic_msix_config *interrupt_info);
657 int hinic_get_board_info(struct hinic_hwdev *hwdev,
658 struct hinic_comm_board_info *board_info);