1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Huawei HiNIC PCI Express Linux driver
4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
7 #ifndef HINIC_HW_API_CMD_H
8 #define HINIC_HW_API_CMD_H
10 #include <linux/types.h>
11 #include <linux/semaphore.h>
13 #include "hinic_hw_if.h"
15 #define HINIC_API_CMD_PI_IDX_SHIFT 0
17 #define HINIC_API_CMD_PI_IDX_MASK 0xFFFFFF
19 #define HINIC_API_CMD_PI_SET(val, member) \
20 (((u32)(val) & HINIC_API_CMD_PI_##member##_MASK) << \
21 HINIC_API_CMD_PI_##member##_SHIFT)
23 #define HINIC_API_CMD_PI_CLEAR(val, member) \
24 ((val) & (~(HINIC_API_CMD_PI_##member##_MASK \
25 << HINIC_API_CMD_PI_##member##_SHIFT)))
27 #define HINIC_API_CMD_CHAIN_REQ_RESTART_SHIFT 1
29 #define HINIC_API_CMD_CHAIN_REQ_RESTART_MASK 0x1
31 #define HINIC_API_CMD_CHAIN_REQ_SET(val, member) \
32 (((u32)(val) & HINIC_API_CMD_CHAIN_REQ_##member##_MASK) << \
33 HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT)
35 #define HINIC_API_CMD_CHAIN_REQ_GET(val, member) \
36 (((val) >> HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT) & \
37 HINIC_API_CMD_CHAIN_REQ_##member##_MASK)
39 #define HINIC_API_CMD_CHAIN_REQ_CLEAR(val, member) \
40 ((val) & (~(HINIC_API_CMD_CHAIN_REQ_##member##_MASK \
41 << HINIC_API_CMD_CHAIN_REQ_##member##_SHIFT)))
43 #define HINIC_API_CMD_CHAIN_CTRL_RESTART_WB_STAT_SHIFT 1
44 #define HINIC_API_CMD_CHAIN_CTRL_XOR_ERR_SHIFT 2
45 #define HINIC_API_CMD_CHAIN_CTRL_AEQE_EN_SHIFT 4
46 #define HINIC_API_CMD_CHAIN_CTRL_AEQ_ID_SHIFT 8
47 #define HINIC_API_CMD_CHAIN_CTRL_XOR_CHK_EN_SHIFT 28
48 #define HINIC_API_CMD_CHAIN_CTRL_CELL_SIZE_SHIFT 30
50 #define HINIC_API_CMD_CHAIN_CTRL_RESTART_WB_STAT_MASK 0x1
51 #define HINIC_API_CMD_CHAIN_CTRL_XOR_ERR_MASK 0x1
52 #define HINIC_API_CMD_CHAIN_CTRL_AEQE_EN_MASK 0x1
53 #define HINIC_API_CMD_CHAIN_CTRL_AEQ_ID_MASK 0x3
54 #define HINIC_API_CMD_CHAIN_CTRL_XOR_CHK_EN_MASK 0x3
55 #define HINIC_API_CMD_CHAIN_CTRL_CELL_SIZE_MASK 0x3
57 #define HINIC_API_CMD_CHAIN_CTRL_SET(val, member) \
58 (((u32)(val) & HINIC_API_CMD_CHAIN_CTRL_##member##_MASK) << \
59 HINIC_API_CMD_CHAIN_CTRL_##member##_SHIFT)
61 #define HINIC_API_CMD_CHAIN_CTRL_CLEAR(val, member) \
62 ((val) & (~(HINIC_API_CMD_CHAIN_CTRL_##member##_MASK \
63 << HINIC_API_CMD_CHAIN_CTRL_##member##_SHIFT)))
65 #define HINIC_API_CMD_CELL_CTRL_DATA_SZ_SHIFT 0
66 #define HINIC_API_CMD_CELL_CTRL_RD_DMA_ATTR_SHIFT 16
67 #define HINIC_API_CMD_CELL_CTRL_WR_DMA_ATTR_SHIFT 24
68 #define HINIC_API_CMD_CELL_CTRL_XOR_CHKSUM_SHIFT 56
70 #define HINIC_API_CMD_CELL_CTRL_DATA_SZ_MASK 0x3F
71 #define HINIC_API_CMD_CELL_CTRL_RD_DMA_ATTR_MASK 0x3F
72 #define HINIC_API_CMD_CELL_CTRL_WR_DMA_ATTR_MASK 0x3F
73 #define HINIC_API_CMD_CELL_CTRL_XOR_CHKSUM_MASK 0xFF
75 #define HINIC_API_CMD_CELL_CTRL_SET(val, member) \
76 ((((u64)val) & HINIC_API_CMD_CELL_CTRL_##member##_MASK) << \
77 HINIC_API_CMD_CELL_CTRL_##member##_SHIFT)
79 #define HINIC_API_CMD_DESC_API_TYPE_SHIFT 0
80 #define HINIC_API_CMD_DESC_RD_WR_SHIFT 1
81 #define HINIC_API_CMD_DESC_MGMT_BYPASS_SHIFT 2
82 #define HINIC_API_CMD_DESC_DEST_SHIFT 32
83 #define HINIC_API_CMD_DESC_SIZE_SHIFT 40
84 #define HINIC_API_CMD_DESC_XOR_CHKSUM_SHIFT 56
86 #define HINIC_API_CMD_DESC_API_TYPE_MASK 0x1
87 #define HINIC_API_CMD_DESC_RD_WR_MASK 0x1
88 #define HINIC_API_CMD_DESC_MGMT_BYPASS_MASK 0x1
89 #define HINIC_API_CMD_DESC_DEST_MASK 0x1F
90 #define HINIC_API_CMD_DESC_SIZE_MASK 0x7FF
91 #define HINIC_API_CMD_DESC_XOR_CHKSUM_MASK 0xFF
93 #define HINIC_API_CMD_DESC_SET(val, member) \
94 ((((u64)val) & HINIC_API_CMD_DESC_##member##_MASK) << \
95 HINIC_API_CMD_DESC_##member##_SHIFT)
97 #define HINIC_API_CMD_STATUS_HEADER_CHAIN_ID_SHIFT 16
99 #define HINIC_API_CMD_STATUS_HEADER_CHAIN_ID_MASK 0xFF
101 #define HINIC_API_CMD_STATUS_HEADER_GET(val, member) \
102 (((val) >> HINIC_API_CMD_STATUS_HEADER_##member##_SHIFT) & \
103 HINIC_API_CMD_STATUS_HEADER_##member##_MASK)
105 #define HINIC_API_CMD_STATUS_CONS_IDX_SHIFT 0
106 #define HINIC_API_CMD_STATUS_FSM_SHIFT 24
107 #define HINIC_API_CMD_STATUS_CHKSUM_ERR_SHIFT 28
108 #define HINIC_API_CMD_STATUS_CPLD_ERR_SHIFT 30
110 #define HINIC_API_CMD_STATUS_CONS_IDX_MASK 0xFFFFFF
111 #define HINIC_API_CMD_STATUS_FSM_MASK 0xFU
112 #define HINIC_API_CMD_STATUS_CHKSUM_ERR_MASK 0x3
113 #define HINIC_API_CMD_STATUS_CPLD_ERR_MASK 0x1U
115 #define HINIC_API_CMD_STATUS_GET(val, member) \
116 (((val) >> HINIC_API_CMD_STATUS_##member##_SHIFT) & \
117 HINIC_API_CMD_STATUS_##member##_MASK)
119 enum hinic_api_cmd_chain_type {
120 HINIC_API_CMD_WRITE_TO_MGMT_CPU = 2,
125 struct hinic_api_cmd_chain_attr {
126 struct hinic_hwif *hwif;
127 enum hinic_api_cmd_chain_type chain_type;
133 struct hinic_api_cmd_status {
143 struct hinic_api_cmd_cell {
146 /* address is 64 bit in HW struct */
158 u64 hw_wb_resp_paddr;
164 struct hinic_api_cmd_cell_ctxt {
165 dma_addr_t cell_paddr;
166 struct hinic_api_cmd_cell *cell_vaddr;
168 dma_addr_t api_cmd_paddr;
172 struct hinic_api_cmd_chain {
173 struct hinic_hwif *hwif;
174 enum hinic_api_cmd_chain_type chain_type;
179 /* HW members in 24 bit format */
183 struct semaphore sem;
185 struct hinic_api_cmd_cell_ctxt *cell_ctxt;
187 dma_addr_t wb_status_paddr;
188 struct hinic_api_cmd_status *wb_status;
190 dma_addr_t head_cell_paddr;
191 struct hinic_api_cmd_cell *head_node;
192 struct hinic_api_cmd_cell *curr_node;
195 int hinic_api_cmd_write(struct hinic_api_cmd_chain *chain,
196 enum hinic_node_id dest, u8 *cmd, u16 size);
198 int hinic_api_cmd_init(struct hinic_api_cmd_chain **chain,
199 struct hinic_hwif *hwif);
201 void hinic_api_cmd_free(struct hinic_api_cmd_chain **chain);