2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
21 #include "hclge_cmd.h"
22 #include "hclge_main.h"
23 #include "hclge_mdio.h"
27 #define HCLGE_NAME "hclge"
28 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
29 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
30 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
31 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
33 static int hclge_rss_init_hw(struct hclge_dev *hdev);
34 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
35 enum hclge_mta_dmac_sel_type mta_mac_sel,
37 static int hclge_init_vlan_config(struct hclge_dev *hdev);
39 static struct hnae3_ae_algo ae_algo;
41 static const struct pci_device_id ae_algo_pci_tbl[] = {
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
49 /* required last entry */
53 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
55 "Serdes Loopback test",
59 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
60 {"igu_rx_oversize_pkt",
61 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
62 {"igu_rx_undersize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
64 {"igu_rx_out_all_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
72 {"egu_tx_out_all_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
80 {"ssu_ppp_mac_key_num",
81 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
82 {"ssu_ppp_host_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
84 {"ppp_ssu_mac_rlt_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
86 {"ppp_ssu_host_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
98 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
100 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
101 {"igu_rx_no_eof_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
103 {"igu_rx_no_sof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
106 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
107 {"ssu_full_drop_num",
108 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
109 {"ssu_part_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
112 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
118 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
120 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
123 {"qcn_fb_invaild_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
125 {"rx_packet_tc0_in_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
127 {"rx_packet_tc1_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
129 {"rx_packet_tc2_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
131 {"rx_packet_tc3_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
133 {"rx_packet_tc4_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
135 {"rx_packet_tc5_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
137 {"rx_packet_tc6_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
139 {"rx_packet_tc7_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
141 {"rx_packet_tc0_out_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
143 {"rx_packet_tc1_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
145 {"rx_packet_tc2_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
147 {"rx_packet_tc3_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
149 {"rx_packet_tc4_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
151 {"rx_packet_tc5_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
153 {"rx_packet_tc6_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
155 {"rx_packet_tc7_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
157 {"tx_packet_tc0_in_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
159 {"tx_packet_tc1_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
161 {"tx_packet_tc2_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
163 {"tx_packet_tc3_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
165 {"tx_packet_tc4_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
167 {"tx_packet_tc5_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
169 {"tx_packet_tc6_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
171 {"tx_packet_tc7_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
173 {"tx_packet_tc0_out_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
175 {"tx_packet_tc1_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
177 {"tx_packet_tc2_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
179 {"tx_packet_tc3_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
181 {"tx_packet_tc4_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
183 {"tx_packet_tc5_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
185 {"tx_packet_tc6_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
187 {"tx_packet_tc7_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
189 {"pkt_curr_buf_tc0_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
191 {"pkt_curr_buf_tc1_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
193 {"pkt_curr_buf_tc2_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
195 {"pkt_curr_buf_tc3_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
197 {"pkt_curr_buf_tc4_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
199 {"pkt_curr_buf_tc5_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
201 {"pkt_curr_buf_tc6_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
203 {"pkt_curr_buf_tc7_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
206 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
207 {"lo_pri_unicast_rlt_drop_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
209 {"hi_pri_multicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
211 {"lo_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
213 {"rx_oq_drop_pkt_cnt",
214 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
215 {"tx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
217 {"nic_l2_err_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
219 {"roc_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
223 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
224 {"mac_tx_mac_pause_num",
225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
226 {"mac_rx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
228 {"mac_tx_pfc_pri0_pkt_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
230 {"mac_tx_pfc_pri1_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
232 {"mac_tx_pfc_pri2_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
234 {"mac_tx_pfc_pri3_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
236 {"mac_tx_pfc_pri4_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
238 {"mac_tx_pfc_pri5_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
240 {"mac_tx_pfc_pri6_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
242 {"mac_tx_pfc_pri7_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
244 {"mac_rx_pfc_pri0_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
246 {"mac_rx_pfc_pri1_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
248 {"mac_rx_pfc_pri2_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
250 {"mac_rx_pfc_pri3_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
252 {"mac_rx_pfc_pri4_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
254 {"mac_rx_pfc_pri5_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
256 {"mac_rx_pfc_pri6_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
258 {"mac_rx_pfc_pri7_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
260 {"mac_tx_total_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
262 {"mac_tx_total_oct_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
264 {"mac_tx_good_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
266 {"mac_tx_bad_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
268 {"mac_tx_good_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
270 {"mac_tx_bad_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
272 {"mac_tx_uni_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
274 {"mac_tx_multi_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
276 {"mac_tx_broad_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
278 {"mac_tx_undersize_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
280 {"mac_tx_overrsize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
282 {"mac_tx_64_oct_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
284 {"mac_tx_65_127_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
286 {"mac_tx_128_255_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
288 {"mac_tx_256_511_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
290 {"mac_tx_512_1023_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
292 {"mac_tx_1024_1518_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
294 {"mac_tx_1519_max_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
296 {"mac_rx_total_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
298 {"mac_rx_total_oct_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
300 {"mac_rx_good_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
302 {"mac_rx_bad_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
304 {"mac_rx_good_oct_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
306 {"mac_rx_bad_oct_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
308 {"mac_rx_uni_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
310 {"mac_rx_multi_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
312 {"mac_rx_broad_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
314 {"mac_rx_undersize_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
316 {"mac_rx_overrsize_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
318 {"mac_rx_64_oct_pkt_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
320 {"mac_rx_65_127_oct_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
322 {"mac_rx_128_255_oct_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
324 {"mac_rx_256_511_oct_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
326 {"mac_rx_512_1023_oct_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
328 {"mac_rx_1024_1518_oct_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
330 {"mac_rx_1519_max_oct_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
333 {"mac_trans_fragment_pkt_num",
334 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
335 {"mac_trans_undermin_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
337 {"mac_trans_jabber_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
339 {"mac_trans_err_all_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
341 {"mac_trans_from_app_good_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
343 {"mac_trans_from_app_bad_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
345 {"mac_rcv_fragment_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
347 {"mac_rcv_undermin_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
349 {"mac_rcv_jabber_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
351 {"mac_rcv_fcs_err_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
353 {"mac_rcv_send_app_good_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
355 {"mac_rcv_send_app_bad_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
359 static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
361 #define HCLGE_64_BIT_CMD_NUM 5
362 #define HCLGE_64_BIT_RTN_DATANUM 4
363 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
364 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
369 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
370 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
372 dev_err(&hdev->pdev->dev,
373 "Get 64 bit pkt stats fail, status = %d.\n", ret);
377 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
378 if (unlikely(i == 0)) {
379 desc_data = (u64 *)(&desc[i].data[0]);
380 n = HCLGE_64_BIT_RTN_DATANUM - 1;
382 desc_data = (u64 *)(&desc[i]);
383 n = HCLGE_64_BIT_RTN_DATANUM;
385 for (k = 0; k < n; k++) {
386 *data++ += cpu_to_le64(*desc_data);
394 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
396 stats->pkt_curr_buf_cnt = 0;
397 stats->pkt_curr_buf_tc0_cnt = 0;
398 stats->pkt_curr_buf_tc1_cnt = 0;
399 stats->pkt_curr_buf_tc2_cnt = 0;
400 stats->pkt_curr_buf_tc3_cnt = 0;
401 stats->pkt_curr_buf_tc4_cnt = 0;
402 stats->pkt_curr_buf_tc5_cnt = 0;
403 stats->pkt_curr_buf_tc6_cnt = 0;
404 stats->pkt_curr_buf_tc7_cnt = 0;
407 static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
409 #define HCLGE_32_BIT_CMD_NUM 8
410 #define HCLGE_32_BIT_RTN_DATANUM 8
412 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
413 struct hclge_32_bit_stats *all_32_bit_stats;
419 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
420 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
422 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
423 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
425 dev_err(&hdev->pdev->dev,
426 "Get 32 bit pkt stats fail, status = %d.\n", ret);
431 hclge_reset_partial_32bit_counter(all_32_bit_stats);
432 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
433 if (unlikely(i == 0)) {
434 all_32_bit_stats->igu_rx_err_pkt +=
435 cpu_to_le32(desc[i].data[0]);
436 all_32_bit_stats->igu_rx_no_eof_pkt +=
437 cpu_to_le32(desc[i].data[1] & 0xffff);
438 all_32_bit_stats->igu_rx_no_sof_pkt +=
439 cpu_to_le32((desc[i].data[1] >> 16) & 0xffff);
441 desc_data = (u32 *)(&desc[i].data[2]);
442 n = HCLGE_32_BIT_RTN_DATANUM - 4;
444 desc_data = (u32 *)(&desc[i]);
445 n = HCLGE_32_BIT_RTN_DATANUM;
447 for (k = 0; k < n; k++) {
448 *data++ += cpu_to_le32(*desc_data);
456 static int hclge_mac_update_stats(struct hclge_dev *hdev)
458 #define HCLGE_MAC_CMD_NUM 17
459 #define HCLGE_RTN_DATA_NUM 4
461 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
462 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
467 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
468 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
470 dev_err(&hdev->pdev->dev,
471 "Get MAC pkt stats fail, status = %d.\n", ret);
476 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
477 if (unlikely(i == 0)) {
478 desc_data = (u64 *)(&desc[i].data[0]);
479 n = HCLGE_RTN_DATA_NUM - 2;
481 desc_data = (u64 *)(&desc[i]);
482 n = HCLGE_RTN_DATA_NUM;
484 for (k = 0; k < n; k++) {
485 *data++ += cpu_to_le64(*desc_data);
493 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
495 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
496 struct hclge_vport *vport = hclge_get_vport(handle);
497 struct hclge_dev *hdev = vport->back;
498 struct hnae3_queue *queue;
499 struct hclge_desc desc[1];
500 struct hclge_tqp *tqp;
503 for (i = 0; i < kinfo->num_tqps; i++) {
504 queue = handle->kinfo.tqp[i];
505 tqp = container_of(queue, struct hclge_tqp, q);
506 /* command : HCLGE_OPC_QUERY_IGU_STAT */
507 hclge_cmd_setup_basic_desc(&desc[0],
508 HCLGE_OPC_QUERY_RX_STATUS,
511 desc[0].data[0] = (tqp->index & 0x1ff);
512 ret = hclge_cmd_send(&hdev->hw, desc, 1);
514 dev_err(&hdev->pdev->dev,
515 "Query tqp stat fail, status = %d,queue = %d\n",
519 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
520 cpu_to_le32(desc[0].data[4]);
523 for (i = 0; i < kinfo->num_tqps; i++) {
524 queue = handle->kinfo.tqp[i];
525 tqp = container_of(queue, struct hclge_tqp, q);
526 /* command : HCLGE_OPC_QUERY_IGU_STAT */
527 hclge_cmd_setup_basic_desc(&desc[0],
528 HCLGE_OPC_QUERY_TX_STATUS,
531 desc[0].data[0] = (tqp->index & 0x1ff);
532 ret = hclge_cmd_send(&hdev->hw, desc, 1);
534 dev_err(&hdev->pdev->dev,
535 "Query tqp stat fail, status = %d,queue = %d\n",
539 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
540 cpu_to_le32(desc[0].data[4]);
546 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
548 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
549 struct hclge_tqp *tqp;
553 for (i = 0; i < kinfo->num_tqps; i++) {
554 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
555 *buff++ = cpu_to_le64(tqp->tqp_stats.rcb_tx_ring_pktnum_rcd);
558 for (i = 0; i < kinfo->num_tqps; i++) {
559 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
560 *buff++ = cpu_to_le64(tqp->tqp_stats.rcb_rx_ring_pktnum_rcd);
566 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
568 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
570 return kinfo->num_tqps * (2);
573 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
575 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
579 for (i = 0; i < kinfo->num_tqps; i++) {
580 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
581 struct hclge_tqp, q);
582 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
584 buff = buff + ETH_GSTRING_LEN;
587 for (i = 0; i < kinfo->num_tqps; i++) {
588 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
589 struct hclge_tqp, q);
590 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
592 buff = buff + ETH_GSTRING_LEN;
598 static u64 *hclge_comm_get_stats(void *comm_stats,
599 const struct hclge_comm_stats_str strs[],
605 for (i = 0; i < size; i++)
606 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
611 static u8 *hclge_comm_get_strings(u32 stringset,
612 const struct hclge_comm_stats_str strs[],
615 char *buff = (char *)data;
618 if (stringset != ETH_SS_STATS)
621 for (i = 0; i < size; i++) {
622 snprintf(buff, ETH_GSTRING_LEN, "%s", strs[i].desc);
623 buff = buff + ETH_GSTRING_LEN;
629 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
630 struct net_device_stats *net_stats)
632 net_stats->tx_dropped = 0;
633 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
634 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
635 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
637 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
638 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
639 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
640 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
641 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
642 net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
644 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
645 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
647 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
648 net_stats->rx_length_errors =
649 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
650 net_stats->rx_length_errors +=
651 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
652 net_stats->rx_over_errors =
653 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
656 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
658 struct hnae3_handle *handle;
661 handle = &hdev->vport[0].nic;
662 if (handle->client) {
663 status = hclge_tqps_update_stats(handle);
665 dev_err(&hdev->pdev->dev,
666 "Update TQPS stats fail, status = %d.\n",
671 status = hclge_mac_update_stats(hdev);
673 dev_err(&hdev->pdev->dev,
674 "Update MAC stats fail, status = %d.\n", status);
676 status = hclge_32_bit_update_stats(hdev);
678 dev_err(&hdev->pdev->dev,
679 "Update 32 bit stats fail, status = %d.\n",
682 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
685 static void hclge_update_stats(struct hnae3_handle *handle,
686 struct net_device_stats *net_stats)
688 struct hclge_vport *vport = hclge_get_vport(handle);
689 struct hclge_dev *hdev = vport->back;
690 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
693 status = hclge_mac_update_stats(hdev);
695 dev_err(&hdev->pdev->dev,
696 "Update MAC stats fail, status = %d.\n",
699 status = hclge_32_bit_update_stats(hdev);
701 dev_err(&hdev->pdev->dev,
702 "Update 32 bit stats fail, status = %d.\n",
705 status = hclge_64_bit_update_stats(hdev);
707 dev_err(&hdev->pdev->dev,
708 "Update 64 bit stats fail, status = %d.\n",
711 status = hclge_tqps_update_stats(handle);
713 dev_err(&hdev->pdev->dev,
714 "Update TQPS stats fail, status = %d.\n",
717 hclge_update_netstat(hw_stats, net_stats);
720 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
722 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
724 struct hclge_vport *vport = hclge_get_vport(handle);
725 struct hclge_dev *hdev = vport->back;
728 /* Loopback test support rules:
729 * mac: only GE mode support
730 * serdes: all mac mode will support include GE/XGE/LGE/CGE
731 * phy: only support when phy device exist on board
733 if (stringset == ETH_SS_TEST) {
734 /* clear loopback bit flags at first */
735 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
736 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
737 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
738 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
740 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
744 } else if (stringset == ETH_SS_STATS) {
745 count = ARRAY_SIZE(g_mac_stats_string) +
746 ARRAY_SIZE(g_all_32bit_stats_string) +
747 ARRAY_SIZE(g_all_64bit_stats_string) +
748 hclge_tqps_get_sset_count(handle, stringset);
754 static void hclge_get_strings(struct hnae3_handle *handle,
758 u8 *p = (char *)data;
761 if (stringset == ETH_SS_STATS) {
762 size = ARRAY_SIZE(g_mac_stats_string);
763 p = hclge_comm_get_strings(stringset,
767 size = ARRAY_SIZE(g_all_32bit_stats_string);
768 p = hclge_comm_get_strings(stringset,
769 g_all_32bit_stats_string,
772 size = ARRAY_SIZE(g_all_64bit_stats_string);
773 p = hclge_comm_get_strings(stringset,
774 g_all_64bit_stats_string,
777 p = hclge_tqps_get_strings(handle, p);
778 } else if (stringset == ETH_SS_TEST) {
779 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
781 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
783 p += ETH_GSTRING_LEN;
785 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
787 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
789 p += ETH_GSTRING_LEN;
791 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
793 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
795 p += ETH_GSTRING_LEN;
800 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
802 struct hclge_vport *vport = hclge_get_vport(handle);
803 struct hclge_dev *hdev = vport->back;
806 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
808 ARRAY_SIZE(g_mac_stats_string),
810 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
811 g_all_32bit_stats_string,
812 ARRAY_SIZE(g_all_32bit_stats_string),
814 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
815 g_all_64bit_stats_string,
816 ARRAY_SIZE(g_all_64bit_stats_string),
818 p = hclge_tqps_get_stats(handle, p);
821 static int hclge_parse_func_status(struct hclge_dev *hdev,
822 struct hclge_func_status *status)
824 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
827 /* Set the pf to main pf */
828 if (status->pf_state & HCLGE_PF_STATE_MAIN)
829 hdev->flag |= HCLGE_FLAG_MAIN;
831 hdev->flag &= ~HCLGE_FLAG_MAIN;
833 hdev->num_req_vfs = status->vf_num / status->pf_num;
837 static int hclge_query_function_status(struct hclge_dev *hdev)
839 struct hclge_func_status *req;
840 struct hclge_desc desc;
844 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
845 req = (struct hclge_func_status *)desc.data;
848 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
850 dev_err(&hdev->pdev->dev,
851 "query function status failed %d.\n",
857 /* Check pf reset is done */
860 usleep_range(1000, 2000);
861 } while (timeout++ < 5);
863 ret = hclge_parse_func_status(hdev, req);
868 static int hclge_query_pf_resource(struct hclge_dev *hdev)
870 struct hclge_pf_res *req;
871 struct hclge_desc desc;
874 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
875 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
877 dev_err(&hdev->pdev->dev,
878 "query pf resource failed %d.\n", ret);
882 req = (struct hclge_pf_res *)desc.data;
883 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
884 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
886 if (hnae3_dev_roce_supported(hdev)) {
887 hdev->num_roce_msix =
888 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
889 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
891 /* PF should have NIC vectors and Roce vectors,
892 * NIC vectors are queued before Roce vectors.
894 hdev->num_msi = hdev->num_roce_msix + HCLGE_ROCE_VECTOR_OFFSET;
897 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
898 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
904 static int hclge_parse_speed(int speed_cmd, int *speed)
908 *speed = HCLGE_MAC_SPEED_10M;
911 *speed = HCLGE_MAC_SPEED_100M;
914 *speed = HCLGE_MAC_SPEED_1G;
917 *speed = HCLGE_MAC_SPEED_10G;
920 *speed = HCLGE_MAC_SPEED_25G;
923 *speed = HCLGE_MAC_SPEED_40G;
926 *speed = HCLGE_MAC_SPEED_50G;
929 *speed = HCLGE_MAC_SPEED_100G;
938 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
940 struct hclge_cfg_param *req;
941 u64 mac_addr_tmp_high;
945 req = (struct hclge_cfg_param *)desc[0].data;
947 /* get the configuration */
948 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
951 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
952 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
953 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
954 HCLGE_CFG_TQP_DESC_N_M,
955 HCLGE_CFG_TQP_DESC_N_S);
957 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
958 HCLGE_CFG_PHY_ADDR_M,
959 HCLGE_CFG_PHY_ADDR_S);
960 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
961 HCLGE_CFG_MEDIA_TP_M,
962 HCLGE_CFG_MEDIA_TP_S);
963 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
964 HCLGE_CFG_RX_BUF_LEN_M,
965 HCLGE_CFG_RX_BUF_LEN_S);
966 /* get mac_address */
967 mac_addr_tmp = __le32_to_cpu(req->param[2]);
968 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
969 HCLGE_CFG_MAC_ADDR_H_M,
970 HCLGE_CFG_MAC_ADDR_H_S);
972 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
974 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
975 HCLGE_CFG_DEFAULT_SPEED_M,
976 HCLGE_CFG_DEFAULT_SPEED_S);
977 for (i = 0; i < ETH_ALEN; i++)
978 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
980 req = (struct hclge_cfg_param *)desc[1].data;
981 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
984 /* hclge_get_cfg: query the static parameter from flash
985 * @hdev: pointer to struct hclge_dev
986 * @hcfg: the config structure to be getted
988 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
990 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
991 struct hclge_cfg_param *req;
994 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
995 req = (struct hclge_cfg_param *)desc[i].data;
996 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
998 hnae_set_field(req->offset, HCLGE_CFG_OFFSET_M,
999 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1000 /* Len should be united by 4 bytes when send to hardware */
1001 hnae_set_field(req->offset, HCLGE_CFG_RD_LEN_M,
1003 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1004 req->offset = cpu_to_le32(req->offset);
1007 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1009 dev_err(&hdev->pdev->dev,
1010 "get config failed %d.\n", ret);
1014 hclge_parse_cfg(hcfg, desc);
1018 static int hclge_get_cap(struct hclge_dev *hdev)
1022 ret = hclge_query_function_status(hdev);
1024 dev_err(&hdev->pdev->dev,
1025 "query function status error %d.\n", ret);
1029 /* get pf resource */
1030 ret = hclge_query_pf_resource(hdev);
1032 dev_err(&hdev->pdev->dev,
1033 "query pf resource error %d.\n", ret);
1040 static int hclge_configure(struct hclge_dev *hdev)
1042 struct hclge_cfg cfg;
1045 ret = hclge_get_cfg(hdev, &cfg);
1047 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1051 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1052 hdev->base_tqp_pid = 0;
1053 hdev->rss_size_max = 1;
1054 hdev->rx_buf_len = cfg.rx_buf_len;
1055 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1056 hdev->hw.mac.media_type = cfg.media_type;
1057 hdev->hw.mac.phy_addr = cfg.phy_addr;
1058 hdev->num_desc = cfg.tqp_desc_num;
1059 hdev->tm_info.num_pg = 1;
1060 hdev->tm_info.num_tc = cfg.tc_num;
1061 hdev->tm_info.hw_pfc_map = 0;
1063 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1065 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1069 if ((hdev->tm_info.num_tc > HNAE3_MAX_TC) ||
1070 (hdev->tm_info.num_tc < 1)) {
1071 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1072 hdev->tm_info.num_tc);
1073 hdev->tm_info.num_tc = 1;
1076 /* Currently not support uncontiuous tc */
1077 for (i = 0; i < cfg.tc_num; i++)
1078 hnae_set_bit(hdev->hw_tc_map, i, 1);
1080 if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
1081 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1083 hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
1088 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1091 struct hclge_cfg_tso_status *req;
1092 struct hclge_desc desc;
1094 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1096 req = (struct hclge_cfg_tso_status *)desc.data;
1097 hnae_set_field(req->tso_mss_min, HCLGE_TSO_MSS_MIN_M,
1098 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1099 hnae_set_field(req->tso_mss_max, HCLGE_TSO_MSS_MIN_M,
1100 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1102 return hclge_cmd_send(&hdev->hw, &desc, 1);
1105 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1107 struct hclge_tqp *tqp;
1110 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1111 sizeof(struct hclge_tqp), GFP_KERNEL);
1117 for (i = 0; i < hdev->num_tqps; i++) {
1118 tqp->dev = &hdev->pdev->dev;
1121 tqp->q.ae_algo = &ae_algo;
1122 tqp->q.buf_size = hdev->rx_buf_len;
1123 tqp->q.desc_num = hdev->num_desc;
1124 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1125 i * HCLGE_TQP_REG_SIZE;
1133 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1134 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1136 struct hclge_tqp_map *req;
1137 struct hclge_desc desc;
1140 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1142 req = (struct hclge_tqp_map *)desc.data;
1143 req->tqp_id = cpu_to_le16(tqp_pid);
1144 req->tqp_vf = cpu_to_le16(func_id);
1145 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1146 1 << HCLGE_TQP_MAP_EN_B;
1147 req->tqp_vid = cpu_to_le16(tqp_vid);
1149 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1151 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1159 static int hclge_assign_tqp(struct hclge_vport *vport,
1160 struct hnae3_queue **tqp, u16 num_tqps)
1162 struct hclge_dev *hdev = vport->back;
1163 int i, alloced, func_id, ret;
1166 func_id = vport->vport_id;
1167 is_pf = (vport->vport_id == 0) ? true : false;
1169 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1170 alloced < num_tqps; i++) {
1171 if (!hdev->htqp[i].alloced) {
1172 hdev->htqp[i].q.handle = &vport->nic;
1173 hdev->htqp[i].q.tqp_index = alloced;
1174 tqp[alloced] = &hdev->htqp[i].q;
1175 hdev->htqp[i].alloced = true;
1176 ret = hclge_map_tqps_to_func(hdev, func_id,
1177 hdev->htqp[i].index,
1185 vport->alloc_tqps = num_tqps;
1190 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1192 struct hnae3_handle *nic = &vport->nic;
1193 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1194 struct hclge_dev *hdev = vport->back;
1197 kinfo->num_desc = hdev->num_desc;
1198 kinfo->rx_buf_len = hdev->rx_buf_len;
1199 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1201 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1202 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1204 for (i = 0; i < HNAE3_MAX_TC; i++) {
1205 if (hdev->hw_tc_map & BIT(i)) {
1206 kinfo->tc_info[i].enable = true;
1207 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1208 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1209 kinfo->tc_info[i].tc = i;
1211 /* Set to default queue if TC is disable */
1212 kinfo->tc_info[i].enable = false;
1213 kinfo->tc_info[i].tqp_offset = 0;
1214 kinfo->tc_info[i].tqp_count = 1;
1215 kinfo->tc_info[i].tc = 0;
1219 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1220 sizeof(struct hnae3_queue *), GFP_KERNEL);
1224 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1226 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1233 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1235 /* this would be initialized later */
1238 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1240 struct hnae3_handle *nic = &vport->nic;
1241 struct hclge_dev *hdev = vport->back;
1244 nic->pdev = hdev->pdev;
1245 nic->ae_algo = &ae_algo;
1246 nic->numa_node_mask = hdev->numa_node_mask;
1248 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1249 ret = hclge_knic_setup(vport, num_tqps);
1251 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1256 hclge_unic_setup(vport, num_tqps);
1262 static int hclge_alloc_vport(struct hclge_dev *hdev)
1264 struct pci_dev *pdev = hdev->pdev;
1265 struct hclge_vport *vport;
1271 /* We need to alloc a vport for main NIC of PF */
1272 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1274 if (hdev->num_tqps < num_vport) {
1275 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1276 hdev->num_tqps, num_vport);
1280 /* Alloc the same number of TQPs for every vport */
1281 tqp_per_vport = hdev->num_tqps / num_vport;
1282 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1284 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1289 hdev->vport = vport;
1290 hdev->num_alloc_vport = num_vport;
1292 #ifdef CONFIG_PCI_IOV
1294 if (hdev->num_req_vfs) {
1295 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1297 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1299 hdev->num_alloc_vfs = 0;
1300 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1305 hdev->num_alloc_vfs = hdev->num_req_vfs;
1308 for (i = 0; i < num_vport; i++) {
1310 vport->vport_id = i;
1313 ret = hclge_vport_setup(vport, tqp_main_vport);
1315 ret = hclge_vport_setup(vport, tqp_per_vport);
1318 "vport setup failed for vport %d, %d\n",
1329 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, u16 buf_size)
1331 /* TX buffer size is unit by 128 byte */
1332 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1333 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1334 struct hclge_tx_buff_alloc *req;
1335 struct hclge_desc desc;
1339 req = (struct hclge_tx_buff_alloc *)desc.data;
1341 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1342 for (i = 0; i < HCLGE_TC_NUM; i++)
1343 req->tx_pkt_buff[i] =
1344 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1345 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1347 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1349 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1357 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, u32 buf_size)
1359 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_size);
1362 dev_err(&hdev->pdev->dev,
1363 "tx buffer alloc failed %d\n", ret);
1370 static int hclge_get_tc_num(struct hclge_dev *hdev)
1374 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1375 if (hdev->hw_tc_map & BIT(i))
1380 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1384 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1385 if (hdev->hw_tc_map & BIT(i) &&
1386 hdev->tm_info.hw_pfc_map & BIT(i))
1391 /* Get the number of pfc enabled TCs, which have private buffer */
1392 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev)
1394 struct hclge_priv_buf *priv;
1397 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1398 priv = &hdev->priv_buf[i];
1399 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1407 /* Get the number of pfc disabled TCs, which have private buffer */
1408 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev)
1410 struct hclge_priv_buf *priv;
1413 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1414 priv = &hdev->priv_buf[i];
1415 if (hdev->hw_tc_map & BIT(i) &&
1416 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1424 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_dev *hdev)
1426 struct hclge_priv_buf *priv;
1430 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1431 priv = &hdev->priv_buf[i];
1433 rx_priv += priv->buf_size;
1438 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, u32 rx_all)
1440 u32 shared_buf_min, shared_buf_tc, shared_std;
1441 int tc_num, pfc_enable_num;
1446 tc_num = hclge_get_tc_num(hdev);
1447 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1449 if (hnae3_dev_dcb_supported(hdev))
1450 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1452 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1454 shared_buf_tc = pfc_enable_num * hdev->mps +
1455 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1457 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1459 rx_priv = hclge_get_rx_priv_buff_alloced(hdev);
1460 if (rx_all <= rx_priv + shared_std)
1463 shared_buf = rx_all - rx_priv;
1464 hdev->s_buf.buf_size = shared_buf;
1465 hdev->s_buf.self.high = shared_buf;
1466 hdev->s_buf.self.low = 2 * hdev->mps;
1468 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1469 if ((hdev->hw_tc_map & BIT(i)) &&
1470 (hdev->tm_info.hw_pfc_map & BIT(i))) {
1471 hdev->s_buf.tc_thrd[i].low = hdev->mps;
1472 hdev->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1474 hdev->s_buf.tc_thrd[i].low = 0;
1475 hdev->s_buf.tc_thrd[i].high = hdev->mps;
1482 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1483 * @hdev: pointer to struct hclge_dev
1484 * @tx_size: the allocated tx buffer for all TCs
1485 * @return: 0: calculate sucessful, negative: fail
1487 int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size)
1489 u32 rx_all = hdev->pkt_buf_size - tx_size;
1490 int no_pfc_priv_num, pfc_priv_num;
1491 struct hclge_priv_buf *priv;
1494 /* When DCB is not supported, rx private
1495 * buffer is not allocated.
1497 if (!hnae3_dev_dcb_supported(hdev)) {
1498 if (!hclge_is_rx_buf_ok(hdev, rx_all))
1504 /* step 1, try to alloc private buffer for all enabled tc */
1505 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1506 priv = &hdev->priv_buf[i];
1507 if (hdev->hw_tc_map & BIT(i)) {
1509 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1510 priv->wl.low = hdev->mps;
1511 priv->wl.high = priv->wl.low + hdev->mps;
1512 priv->buf_size = priv->wl.high +
1516 priv->wl.high = 2 * hdev->mps;
1517 priv->buf_size = priv->wl.high;
1527 if (hclge_is_rx_buf_ok(hdev, rx_all))
1530 /* step 2, try to decrease the buffer size of
1531 * no pfc TC's private buffer
1533 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1534 priv = &hdev->priv_buf[i];
1541 if (!(hdev->hw_tc_map & BIT(i)))
1546 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1548 priv->wl.high = priv->wl.low + hdev->mps;
1549 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1552 priv->wl.high = hdev->mps;
1553 priv->buf_size = priv->wl.high;
1557 if (hclge_is_rx_buf_ok(hdev, rx_all))
1560 /* step 3, try to reduce the number of pfc disabled TCs,
1561 * which have private buffer
1563 /* get the total no pfc enable TC number, which have private buffer */
1564 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev);
1566 /* let the last to be cleared first */
1567 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1568 priv = &hdev->priv_buf[i];
1570 if (hdev->hw_tc_map & BIT(i) &&
1571 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1572 /* Clear the no pfc TC private buffer */
1580 if (hclge_is_rx_buf_ok(hdev, rx_all) ||
1581 no_pfc_priv_num == 0)
1585 if (hclge_is_rx_buf_ok(hdev, rx_all))
1588 /* step 4, try to reduce the number of pfc enabled TCs
1589 * which have private buffer.
1591 pfc_priv_num = hclge_get_pfc_priv_num(hdev);
1593 /* let the last to be cleared first */
1594 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1595 priv = &hdev->priv_buf[i];
1597 if (hdev->hw_tc_map & BIT(i) &&
1598 hdev->tm_info.hw_pfc_map & BIT(i)) {
1599 /* Reduce the number of pfc TC with private buffer */
1607 if (hclge_is_rx_buf_ok(hdev, rx_all) ||
1611 if (hclge_is_rx_buf_ok(hdev, rx_all))
1617 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev)
1619 struct hclge_rx_priv_buff *req;
1620 struct hclge_desc desc;
1624 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1625 req = (struct hclge_rx_priv_buff *)desc.data;
1627 /* Alloc private buffer TCs */
1628 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1629 struct hclge_priv_buf *priv = &hdev->priv_buf[i];
1632 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1634 cpu_to_le16(true << HCLGE_TC0_PRI_BUF_EN_B);
1638 cpu_to_le16((hdev->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1639 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1641 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1643 dev_err(&hdev->pdev->dev,
1644 "rx private buffer alloc cmd failed %d\n", ret);
1651 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1653 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev)
1655 struct hclge_rx_priv_wl_buf *req;
1656 struct hclge_priv_buf *priv;
1657 struct hclge_desc desc[2];
1661 for (i = 0; i < 2; i++) {
1662 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1664 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1666 /* The first descriptor set the NEXT bit to 1 */
1668 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1670 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1672 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1673 priv = &hdev->priv_buf[i * HCLGE_TC_NUM_ONE_DESC + j];
1674 req->tc_wl[j].high =
1675 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1676 req->tc_wl[j].high |=
1677 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1678 HCLGE_RX_PRIV_EN_B);
1680 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1681 req->tc_wl[j].low |=
1682 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1683 HCLGE_RX_PRIV_EN_B);
1687 /* Send 2 descriptor at one time */
1688 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1690 dev_err(&hdev->pdev->dev,
1691 "rx private waterline config cmd failed %d\n",
1698 static int hclge_common_thrd_config(struct hclge_dev *hdev)
1700 struct hclge_shared_buf *s_buf = &hdev->s_buf;
1701 struct hclge_rx_com_thrd *req;
1702 struct hclge_desc desc[2];
1703 struct hclge_tc_thrd *tc;
1707 for (i = 0; i < 2; i++) {
1708 hclge_cmd_setup_basic_desc(&desc[i],
1709 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1710 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1712 /* The first descriptor set the NEXT bit to 1 */
1714 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1716 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1718 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1719 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1721 req->com_thrd[j].high =
1722 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1723 req->com_thrd[j].high |=
1724 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1725 HCLGE_RX_PRIV_EN_B);
1726 req->com_thrd[j].low =
1727 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1728 req->com_thrd[j].low |=
1729 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1730 HCLGE_RX_PRIV_EN_B);
1734 /* Send 2 descriptors at one time */
1735 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1737 dev_err(&hdev->pdev->dev,
1738 "common threshold config cmd failed %d\n", ret);
1744 static int hclge_common_wl_config(struct hclge_dev *hdev)
1746 struct hclge_shared_buf *buf = &hdev->s_buf;
1747 struct hclge_rx_com_wl *req;
1748 struct hclge_desc desc;
1751 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1753 req = (struct hclge_rx_com_wl *)desc.data;
1754 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1756 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1757 HCLGE_RX_PRIV_EN_B);
1759 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1761 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1762 HCLGE_RX_PRIV_EN_B);
1764 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1766 dev_err(&hdev->pdev->dev,
1767 "common waterline config cmd failed %d\n", ret);
1774 int hclge_buffer_alloc(struct hclge_dev *hdev)
1776 u32 tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1779 hdev->priv_buf = devm_kmalloc_array(&hdev->pdev->dev, HCLGE_MAX_TC_NUM,
1780 sizeof(struct hclge_priv_buf),
1781 GFP_KERNEL | __GFP_ZERO);
1782 if (!hdev->priv_buf)
1785 ret = hclge_tx_buffer_alloc(hdev, tx_buf_size);
1787 dev_err(&hdev->pdev->dev,
1788 "could not alloc tx buffers %d\n", ret);
1792 ret = hclge_rx_buffer_calc(hdev, tx_buf_size);
1794 dev_err(&hdev->pdev->dev,
1795 "could not calc rx priv buffer size for all TCs %d\n",
1800 ret = hclge_rx_priv_buf_alloc(hdev);
1802 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1807 if (hnae3_dev_dcb_supported(hdev)) {
1808 ret = hclge_rx_priv_wl_config(hdev);
1810 dev_err(&hdev->pdev->dev,
1811 "could not configure rx private waterline %d\n",
1816 ret = hclge_common_thrd_config(hdev);
1818 dev_err(&hdev->pdev->dev,
1819 "could not configure common threshold %d\n",
1825 ret = hclge_common_wl_config(hdev);
1827 dev_err(&hdev->pdev->dev,
1828 "could not configure common waterline %d\n", ret);
1835 static int hclge_init_roce_base_info(struct hclge_vport *vport)
1837 struct hnae3_handle *roce = &vport->roce;
1838 struct hnae3_handle *nic = &vport->nic;
1840 roce->rinfo.num_vectors = vport->back->num_roce_msix;
1842 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1843 vport->back->num_msi_left == 0)
1846 roce->rinfo.base_vector = vport->back->roce_base_vector;
1848 roce->rinfo.netdev = nic->kinfo.netdev;
1849 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1851 roce->pdev = nic->pdev;
1852 roce->ae_algo = nic->ae_algo;
1853 roce->numa_node_mask = nic->numa_node_mask;
1858 static int hclge_init_msix(struct hclge_dev *hdev)
1860 struct pci_dev *pdev = hdev->pdev;
1863 hdev->msix_entries = devm_kcalloc(&pdev->dev, hdev->num_msi,
1864 sizeof(struct msix_entry),
1866 if (!hdev->msix_entries)
1869 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1870 sizeof(u16), GFP_KERNEL);
1871 if (!hdev->vector_status)
1874 for (i = 0; i < hdev->num_msi; i++) {
1875 hdev->msix_entries[i].entry = i;
1876 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1879 hdev->num_msi_left = hdev->num_msi;
1880 hdev->base_msi_vector = hdev->pdev->irq;
1881 hdev->roce_base_vector = hdev->base_msi_vector +
1882 HCLGE_ROCE_VECTOR_OFFSET;
1884 ret = pci_enable_msix_range(hdev->pdev, hdev->msix_entries,
1885 hdev->num_msi, hdev->num_msi);
1887 dev_info(&hdev->pdev->dev,
1888 "MSI-X vector alloc failed: %d\n", ret);
1895 static int hclge_init_msi(struct hclge_dev *hdev)
1897 struct pci_dev *pdev = hdev->pdev;
1901 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1902 sizeof(u16), GFP_KERNEL);
1903 if (!hdev->vector_status)
1906 for (i = 0; i < hdev->num_msi; i++)
1907 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1909 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, PCI_IRQ_MSI);
1911 dev_err(&pdev->dev, "MSI vectors enable failed %d\n", vectors);
1914 hdev->num_msi = vectors;
1915 hdev->num_msi_left = vectors;
1916 hdev->base_msi_vector = pdev->irq;
1917 hdev->roce_base_vector = hdev->base_msi_vector +
1918 HCLGE_ROCE_VECTOR_OFFSET;
1923 static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
1925 struct hclge_mac *mac = &hdev->hw.mac;
1927 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
1928 mac->duplex = (u8)duplex;
1930 mac->duplex = HCLGE_MAC_FULL;
1935 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1937 struct hclge_config_mac_speed_dup *req;
1938 struct hclge_desc desc;
1941 req = (struct hclge_config_mac_speed_dup *)desc.data;
1943 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1945 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
1948 case HCLGE_MAC_SPEED_10M:
1949 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1950 HCLGE_CFG_SPEED_S, 6);
1952 case HCLGE_MAC_SPEED_100M:
1953 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1954 HCLGE_CFG_SPEED_S, 7);
1956 case HCLGE_MAC_SPEED_1G:
1957 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1958 HCLGE_CFG_SPEED_S, 0);
1960 case HCLGE_MAC_SPEED_10G:
1961 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1962 HCLGE_CFG_SPEED_S, 1);
1964 case HCLGE_MAC_SPEED_25G:
1965 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1966 HCLGE_CFG_SPEED_S, 2);
1968 case HCLGE_MAC_SPEED_40G:
1969 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1970 HCLGE_CFG_SPEED_S, 3);
1972 case HCLGE_MAC_SPEED_50G:
1973 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1974 HCLGE_CFG_SPEED_S, 4);
1976 case HCLGE_MAC_SPEED_100G:
1977 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1978 HCLGE_CFG_SPEED_S, 5);
1981 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
1985 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1988 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1990 dev_err(&hdev->pdev->dev,
1991 "mac speed/duplex config cmd failed %d.\n", ret);
1995 hclge_check_speed_dup(hdev, duplex, speed);
2000 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2003 struct hclge_vport *vport = hclge_get_vport(handle);
2004 struct hclge_dev *hdev = vport->back;
2006 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2009 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2012 struct hclge_query_an_speed_dup *req;
2013 struct hclge_desc desc;
2017 req = (struct hclge_query_an_speed_dup *)desc.data;
2019 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2020 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2022 dev_err(&hdev->pdev->dev,
2023 "mac speed/autoneg/duplex query cmd failed %d\n",
2028 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2029 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2030 HCLGE_QUERY_SPEED_S);
2032 ret = hclge_parse_speed(speed_tmp, speed);
2034 dev_err(&hdev->pdev->dev,
2035 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2042 static int hclge_query_autoneg_result(struct hclge_dev *hdev)
2044 struct hclge_mac *mac = &hdev->hw.mac;
2045 struct hclge_query_an_speed_dup *req;
2046 struct hclge_desc desc;
2049 req = (struct hclge_query_an_speed_dup *)desc.data;
2051 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2052 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2054 dev_err(&hdev->pdev->dev,
2055 "autoneg result query cmd failed %d.\n", ret);
2059 mac->autoneg = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_AN_B);
2064 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2066 struct hclge_config_auto_neg *req;
2067 struct hclge_desc desc;
2070 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2072 req = (struct hclge_config_auto_neg *)desc.data;
2073 hnae_set_bit(req->cfg_an_cmd_flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2075 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2077 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2085 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2087 struct hclge_vport *vport = hclge_get_vport(handle);
2088 struct hclge_dev *hdev = vport->back;
2090 return hclge_set_autoneg_en(hdev, enable);
2093 static int hclge_get_autoneg(struct hnae3_handle *handle)
2095 struct hclge_vport *vport = hclge_get_vport(handle);
2096 struct hclge_dev *hdev = vport->back;
2097 struct phy_device *phydev = hdev->hw.mac.phydev;
2100 return phydev->autoneg;
2102 hclge_query_autoneg_result(hdev);
2104 return hdev->hw.mac.autoneg;
2107 static int hclge_mac_init(struct hclge_dev *hdev)
2109 struct hclge_mac *mac = &hdev->hw.mac;
2112 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2114 dev_err(&hdev->pdev->dev,
2115 "Config mac speed dup fail ret=%d\n", ret);
2121 ret = hclge_mac_mdio_config(hdev);
2123 dev_warn(&hdev->pdev->dev,
2124 "mdio config fail ret=%d\n", ret);
2128 /* Initialize the MTA table work mode */
2129 hdev->accept_mta_mc = true;
2130 hdev->enable_mta = true;
2131 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2133 ret = hclge_set_mta_filter_mode(hdev,
2134 hdev->mta_mac_sel_type,
2137 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2142 return hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2145 static void hclge_task_schedule(struct hclge_dev *hdev)
2147 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2148 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2149 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2150 (void)schedule_work(&hdev->service_task);
2153 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2155 struct hclge_link_status *req;
2156 struct hclge_desc desc;
2160 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2161 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2163 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2168 req = (struct hclge_link_status *)desc.data;
2169 link_status = req->status & HCLGE_LINK_STATUS;
2171 return !!link_status;
2174 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2179 mac_state = hclge_get_mac_link_status(hdev);
2181 if (hdev->hw.mac.phydev) {
2182 if (hdev->hw.mac.phydev->state == PHY_RUNNING)
2183 link_stat = mac_state &
2184 hdev->hw.mac.phydev->link;
2189 link_stat = mac_state;
2195 static void hclge_update_link_status(struct hclge_dev *hdev)
2197 struct hnae3_client *client = hdev->nic_client;
2198 struct hnae3_handle *handle;
2204 state = hclge_get_mac_phy_link(hdev);
2205 if (state != hdev->hw.mac.link) {
2206 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2207 handle = &hdev->vport[i].nic;
2208 client->ops->link_status_change(handle, state);
2210 hdev->hw.mac.link = state;
2214 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2216 struct hclge_mac mac = hdev->hw.mac;
2221 /* get the speed and duplex as autoneg'result from mac cmd when phy
2227 /* update mac->antoneg. */
2228 ret = hclge_query_autoneg_result(hdev);
2230 dev_err(&hdev->pdev->dev,
2231 "autoneg result query failed %d\n", ret);
2238 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2240 dev_err(&hdev->pdev->dev,
2241 "mac autoneg/speed/duplex query failed %d\n", ret);
2245 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2246 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2248 dev_err(&hdev->pdev->dev,
2249 "mac speed/duplex config failed %d\n", ret);
2257 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2259 struct hclge_vport *vport = hclge_get_vport(handle);
2260 struct hclge_dev *hdev = vport->back;
2262 return hclge_update_speed_duplex(hdev);
2265 static int hclge_get_status(struct hnae3_handle *handle)
2267 struct hclge_vport *vport = hclge_get_vport(handle);
2268 struct hclge_dev *hdev = vport->back;
2270 hclge_update_link_status(hdev);
2272 return hdev->hw.mac.link;
2275 static void hclge_service_timer(unsigned long data)
2277 struct hclge_dev *hdev = (struct hclge_dev *)data;
2278 (void)mod_timer(&hdev->service_timer, jiffies + HZ);
2280 hclge_task_schedule(hdev);
2283 static void hclge_service_complete(struct hclge_dev *hdev)
2285 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2287 /* Flush memory before next watchdog */
2288 smp_mb__before_atomic();
2289 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2292 static void hclge_service_task(struct work_struct *work)
2294 struct hclge_dev *hdev =
2295 container_of(work, struct hclge_dev, service_task);
2297 hclge_update_speed_duplex(hdev);
2298 hclge_update_link_status(hdev);
2299 hclge_update_stats_for_all(hdev);
2300 hclge_service_complete(hdev);
2303 static void hclge_disable_sriov(struct hclge_dev *hdev)
2305 /* If our VFs are assigned we cannot shut down SR-IOV
2306 * without causing issues, so just leave the hardware
2307 * available but disabled
2309 if (pci_vfs_assigned(hdev->pdev)) {
2310 dev_warn(&hdev->pdev->dev,
2311 "disabling driver while VFs are assigned\n");
2315 pci_disable_sriov(hdev->pdev);
2318 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2320 /* VF handle has no client */
2321 if (!handle->client)
2322 return container_of(handle, struct hclge_vport, nic);
2323 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2324 return container_of(handle, struct hclge_vport, roce);
2326 return container_of(handle, struct hclge_vport, nic);
2329 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2330 struct hnae3_vector_info *vector_info)
2332 struct hclge_vport *vport = hclge_get_vport(handle);
2333 struct hnae3_vector_info *vector = vector_info;
2334 struct hclge_dev *hdev = vport->back;
2338 vector_num = min(hdev->num_msi_left, vector_num);
2340 for (j = 0; j < vector_num; j++) {
2341 for (i = 1; i < hdev->num_msi; i++) {
2342 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2343 vector->vector = pci_irq_vector(hdev->pdev, i);
2344 vector->io_addr = hdev->hw.io_base +
2345 HCLGE_VECTOR_REG_BASE +
2346 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2348 HCLGE_VECTOR_VF_OFFSET;
2349 hdev->vector_status[i] = vport->vport_id;
2358 hdev->num_msi_left -= alloc;
2359 hdev->num_msi_used += alloc;
2364 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2368 for (i = 0; i < hdev->num_msi; i++) {
2369 if (hdev->msix_entries) {
2370 if (vector == hdev->msix_entries[i].vector)
2373 if (vector == (hdev->base_msi_vector + i))
2380 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2382 return HCLGE_RSS_KEY_SIZE;
2385 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2387 return HCLGE_RSS_IND_TBL_SIZE;
2390 static int hclge_get_rss_algo(struct hclge_dev *hdev)
2392 struct hclge_rss_config *req;
2393 struct hclge_desc desc;
2397 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2399 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2401 dev_err(&hdev->pdev->dev,
2402 "Get link status error, status =%d\n", ret);
2406 req = (struct hclge_rss_config *)desc.data;
2407 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2409 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2410 return ETH_RSS_HASH_TOP;
2415 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2416 const u8 hfunc, const u8 *key)
2418 struct hclge_rss_config *req;
2419 struct hclge_desc desc;
2424 req = (struct hclge_rss_config *)desc.data;
2426 for (key_offset = 0; key_offset < 3; key_offset++) {
2427 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2430 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2431 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2433 if (key_offset == 2)
2435 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2437 key_size = HCLGE_RSS_HASH_KEY_NUM;
2439 memcpy(req->hash_key,
2440 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2442 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2444 dev_err(&hdev->pdev->dev,
2445 "Configure RSS config fail, status = %d\n",
2453 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2455 struct hclge_rss_indirection_table *req;
2456 struct hclge_desc desc;
2460 req = (struct hclge_rss_indirection_table *)desc.data;
2462 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2463 hclge_cmd_setup_basic_desc
2464 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2466 req->start_table_index = i * HCLGE_RSS_CFG_TBL_SIZE;
2467 req->rss_set_bitmap = HCLGE_RSS_SET_BITMAP_MSK;
2469 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2470 req->rss_result[j] =
2471 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2473 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2475 dev_err(&hdev->pdev->dev,
2476 "Configure rss indir table fail,status = %d\n",
2484 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2485 u16 *tc_size, u16 *tc_offset)
2487 struct hclge_rss_tc_mode *req;
2488 struct hclge_desc desc;
2492 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
2493 req = (struct hclge_rss_tc_mode *)desc.data;
2495 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2496 hnae_set_bit(req->rss_tc_mode[i], HCLGE_RSS_TC_VALID_B,
2497 (tc_valid[i] & 0x1));
2498 hnae_set_field(req->rss_tc_mode[i], HCLGE_RSS_TC_SIZE_M,
2499 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
2500 hnae_set_field(req->rss_tc_mode[i], HCLGE_RSS_TC_OFFSET_M,
2501 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
2504 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2506 dev_err(&hdev->pdev->dev,
2507 "Configure rss tc mode fail, status = %d\n", ret);
2514 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2516 #define HCLGE_RSS_INPUT_TUPLE_OTHER 0xf
2517 #define HCLGE_RSS_INPUT_TUPLE_SCTP 0x1f
2518 struct hclge_rss_input_tuple *req;
2519 struct hclge_desc desc;
2522 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2524 req = (struct hclge_rss_input_tuple *)desc.data;
2525 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2526 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2527 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2528 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2529 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2530 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2531 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2532 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2533 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2535 dev_err(&hdev->pdev->dev,
2536 "Configure rss input fail, status = %d\n", ret);
2543 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2546 struct hclge_vport *vport = hclge_get_vport(handle);
2547 struct hclge_dev *hdev = vport->back;
2550 /* Get hash algorithm */
2552 *hfunc = hclge_get_rss_algo(hdev);
2554 /* Get the RSS Key required by the user */
2556 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2558 /* Get indirect table */
2560 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2561 indir[i] = vport->rss_indirection_tbl[i];
2566 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2567 const u8 *key, const u8 hfunc)
2569 struct hclge_vport *vport = hclge_get_vport(handle);
2570 struct hclge_dev *hdev = vport->back;
2574 /* Set the RSS Hash Key if specififed by the user */
2576 /* Update the shadow RSS key with user specified qids */
2577 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2579 if (hfunc == ETH_RSS_HASH_TOP ||
2580 hfunc == ETH_RSS_HASH_NO_CHANGE)
2581 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2584 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2589 /* Update the shadow RSS table with user specified qids */
2590 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2591 vport->rss_indirection_tbl[i] = indir[i];
2593 /* Update the hardware */
2594 ret = hclge_set_rss_indir_table(hdev, indir);
2598 static int hclge_get_tc_size(struct hnae3_handle *handle)
2600 struct hclge_vport *vport = hclge_get_vport(handle);
2601 struct hclge_dev *hdev = vport->back;
2603 return hdev->rss_size_max;
2606 static int hclge_rss_init_hw(struct hclge_dev *hdev)
2608 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2609 struct hclge_vport *vport = hdev->vport;
2610 u16 tc_offset[HCLGE_MAX_TC_NUM];
2611 u8 rss_key[HCLGE_RSS_KEY_SIZE];
2612 u16 tc_valid[HCLGE_MAX_TC_NUM];
2613 u16 tc_size[HCLGE_MAX_TC_NUM];
2614 u32 *rss_indir = NULL;
2615 u16 rss_size = 0, roundup_size;
2619 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
2623 /* Get default RSS key */
2624 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
2626 /* Initialize RSS indirect table for each vport */
2627 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
2628 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
2629 vport[j].rss_indirection_tbl[i] =
2630 i % vport[j].alloc_rss_size;
2632 /* vport 0 is for PF */
2636 rss_size = vport[j].alloc_rss_size;
2637 rss_indir[i] = vport[j].rss_indirection_tbl[i];
2640 ret = hclge_set_rss_indir_table(hdev, rss_indir);
2645 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
2649 ret = hclge_set_rss_input_tuple(hdev);
2653 /* Each TC have the same queue size, and tc_size set to hardware is
2654 * the log2 of roundup power of two of rss_size, the acutal queue
2655 * size is limited by indirection table.
2657 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
2658 dev_err(&hdev->pdev->dev,
2659 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
2665 roundup_size = roundup_pow_of_two(rss_size);
2666 roundup_size = ilog2(roundup_size);
2668 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2671 if (!(hdev->hw_tc_map & BIT(i)))
2675 tc_size[i] = roundup_size;
2676 tc_offset[i] = rss_size * i;
2679 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
2687 int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,
2688 struct hnae3_ring_chain_node *ring_chain)
2690 struct hclge_dev *hdev = vport->back;
2691 struct hclge_ctrl_vector_chain *req;
2692 struct hnae3_ring_chain_node *node;
2693 struct hclge_desc desc;
2697 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ADD_RING_TO_VECTOR, false);
2699 req = (struct hclge_ctrl_vector_chain *)desc.data;
2700 req->int_vector_id = vector_id;
2703 for (node = ring_chain; node; node = node->next) {
2704 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_TYPE_M,
2706 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2707 hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,
2708 HCLGE_TQP_ID_S, node->tqp_index);
2709 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,
2711 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2712 req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);
2713 req->vfid = vport->vport_id;
2715 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
2716 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
2718 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2720 dev_err(&hdev->pdev->dev,
2721 "Map TQP fail, status is %d.\n",
2727 hclge_cmd_setup_basic_desc(&desc,
2728 HCLGE_OPC_ADD_RING_TO_VECTOR,
2730 req->int_vector_id = vector_id;
2735 req->int_cause_num = i;
2737 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2739 dev_err(&hdev->pdev->dev,
2740 "Map TQP fail, status is %d.\n", ret);
2748 int hclge_map_handle_ring_to_vector(struct hnae3_handle *handle,
2750 struct hnae3_ring_chain_node *ring_chain)
2752 struct hclge_vport *vport = hclge_get_vport(handle);
2753 struct hclge_dev *hdev = vport->back;
2756 vector_id = hclge_get_vector_index(hdev, vector);
2757 if (vector_id < 0) {
2758 dev_err(&hdev->pdev->dev,
2759 "Get vector index fail. ret =%d\n", vector_id);
2763 return hclge_map_vport_ring_to_vector(vport, vector_id, ring_chain);
2766 static int hclge_unmap_ring_from_vector(
2767 struct hnae3_handle *handle, int vector,
2768 struct hnae3_ring_chain_node *ring_chain)
2770 struct hclge_vport *vport = hclge_get_vport(handle);
2771 struct hclge_dev *hdev = vport->back;
2772 struct hclge_ctrl_vector_chain *req;
2773 struct hnae3_ring_chain_node *node;
2774 struct hclge_desc desc;
2778 vector_id = hclge_get_vector_index(hdev, vector);
2779 if (vector_id < 0) {
2780 dev_err(&handle->pdev->dev,
2781 "Get vector index fail. ret =%d\n", vector_id);
2785 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_DEL_RING_TO_VECTOR, false);
2787 req = (struct hclge_ctrl_vector_chain *)desc.data;
2788 req->int_vector_id = vector_id;
2791 for (node = ring_chain; node; node = node->next) {
2792 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_TYPE_M,
2794 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2795 hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,
2796 HCLGE_TQP_ID_S, node->tqp_index);
2797 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,
2799 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2801 req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);
2802 req->vfid = vport->vport_id;
2804 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
2805 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
2807 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2809 dev_err(&hdev->pdev->dev,
2810 "Unmap TQP fail, status is %d.\n",
2815 hclge_cmd_setup_basic_desc(&desc,
2816 HCLGE_OPC_DEL_RING_TO_VECTOR,
2818 req->int_vector_id = vector_id;
2823 req->int_cause_num = i;
2825 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2827 dev_err(&hdev->pdev->dev,
2828 "Unmap TQP fail, status is %d.\n", ret);
2836 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
2837 struct hclge_promisc_param *param)
2839 struct hclge_promisc_cfg *req;
2840 struct hclge_desc desc;
2843 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
2845 req = (struct hclge_promisc_cfg *)desc.data;
2846 req->vf_id = param->vf_id;
2847 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
2849 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2851 dev_err(&hdev->pdev->dev,
2852 "Set promisc mode fail, status is %d.\n", ret);
2858 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
2859 bool en_mc, bool en_bc, int vport_id)
2864 memset(param, 0, sizeof(struct hclge_promisc_param));
2866 param->enable = HCLGE_PROMISC_EN_UC;
2868 param->enable |= HCLGE_PROMISC_EN_MC;
2870 param->enable |= HCLGE_PROMISC_EN_BC;
2871 param->vf_id = vport_id;
2874 static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
2876 struct hclge_vport *vport = hclge_get_vport(handle);
2877 struct hclge_dev *hdev = vport->back;
2878 struct hclge_promisc_param param;
2880 hclge_promisc_param_init(¶m, en, en, true, vport->vport_id);
2881 hclge_cmd_set_promisc_mode(hdev, ¶m);
2884 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
2886 struct hclge_desc desc;
2887 struct hclge_config_mac_mode *req =
2888 (struct hclge_config_mac_mode *)desc.data;
2891 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
2892 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_TX_EN_B, enable);
2893 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_RX_EN_B, enable);
2894 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_PAD_TX_B, enable);
2895 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_PAD_RX_B, enable);
2896 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_1588_TX_B, 0);
2897 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_1588_RX_B, 0);
2898 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_APP_LP_B, 0);
2899 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_LINE_LP_B, 0);
2900 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_FCS_TX_B, enable);
2901 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_RX_FCS_B, enable);
2902 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2903 HCLGE_MAC_RX_FCS_STRIP_B, enable);
2904 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2905 HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
2906 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2907 HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
2908 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2909 HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
2911 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2913 dev_err(&hdev->pdev->dev,
2914 "mac enable fail, ret =%d.\n", ret);
2917 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
2918 int stream_id, bool enable)
2920 struct hclge_desc desc;
2921 struct hclge_cfg_com_tqp_queue *req =
2922 (struct hclge_cfg_com_tqp_queue *)desc.data;
2925 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
2926 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
2927 req->stream_id = cpu_to_le16(stream_id);
2928 req->enable |= enable << HCLGE_TQP_ENABLE_B;
2930 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2932 dev_err(&hdev->pdev->dev,
2933 "Tqp enable fail, status =%d.\n", ret);
2937 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
2939 struct hclge_vport *vport = hclge_get_vport(handle);
2940 struct hnae3_queue *queue;
2941 struct hclge_tqp *tqp;
2944 for (i = 0; i < vport->alloc_tqps; i++) {
2945 queue = handle->kinfo.tqp[i];
2946 tqp = container_of(queue, struct hclge_tqp, q);
2947 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
2951 static int hclge_ae_start(struct hnae3_handle *handle)
2953 struct hclge_vport *vport = hclge_get_vport(handle);
2954 struct hclge_dev *hdev = vport->back;
2955 int i, queue_id, ret;
2957 for (i = 0; i < vport->alloc_tqps; i++) {
2958 /* todo clear interrupt */
2960 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
2962 dev_warn(&hdev->pdev->dev,
2963 "Get invalid queue id, ignore it\n");
2967 hclge_tqp_enable(hdev, queue_id, 0, true);
2970 hclge_cfg_mac_mode(hdev, true);
2971 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
2972 (void)mod_timer(&hdev->service_timer, jiffies + HZ);
2974 ret = hclge_mac_start_phy(hdev);
2978 /* reset tqp stats */
2979 hclge_reset_tqp_stats(handle);
2984 static void hclge_ae_stop(struct hnae3_handle *handle)
2986 struct hclge_vport *vport = hclge_get_vport(handle);
2987 struct hclge_dev *hdev = vport->back;
2990 for (i = 0; i < vport->alloc_tqps; i++) {
2992 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
2994 dev_warn(&hdev->pdev->dev,
2995 "Get invalid queue id, ignore it\n");
2999 hclge_tqp_enable(hdev, queue_id, 0, false);
3002 hclge_cfg_mac_mode(hdev, false);
3004 hclge_mac_stop_phy(hdev);
3006 /* reset tqp stats */
3007 hclge_reset_tqp_stats(handle);
3010 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3011 u16 cmdq_resp, u8 resp_code,
3012 enum hclge_mac_vlan_tbl_opcode op)
3014 struct hclge_dev *hdev = vport->back;
3015 int return_status = -EIO;
3018 dev_err(&hdev->pdev->dev,
3019 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3024 if (op == HCLGE_MAC_VLAN_ADD) {
3025 if ((!resp_code) || (resp_code == 1)) {
3027 } else if (resp_code == 2) {
3028 return_status = -EIO;
3029 dev_err(&hdev->pdev->dev,
3030 "add mac addr failed for uc_overflow.\n");
3031 } else if (resp_code == 3) {
3032 return_status = -EIO;
3033 dev_err(&hdev->pdev->dev,
3034 "add mac addr failed for mc_overflow.\n");
3036 dev_err(&hdev->pdev->dev,
3037 "add mac addr failed for undefined, code=%d.\n",
3040 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3043 } else if (resp_code == 1) {
3044 return_status = -EIO;
3045 dev_dbg(&hdev->pdev->dev,
3046 "remove mac addr failed for miss.\n");
3048 dev_err(&hdev->pdev->dev,
3049 "remove mac addr failed for undefined, code=%d.\n",
3052 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3055 } else if (resp_code == 1) {
3056 return_status = -EIO;
3057 dev_dbg(&hdev->pdev->dev,
3058 "lookup mac addr failed for miss.\n");
3060 dev_err(&hdev->pdev->dev,
3061 "lookup mac addr failed for undefined, code=%d.\n",
3065 return_status = -EIO;
3066 dev_err(&hdev->pdev->dev,
3067 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3071 return return_status;
3074 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3079 if (vfid > 255 || vfid < 0)
3082 if (vfid >= 0 && vfid <= 191) {
3083 word_num = vfid / 32;
3084 bit_num = vfid % 32;
3086 desc[1].data[word_num] &= ~(1 << bit_num);
3088 desc[1].data[word_num] |= (1 << bit_num);
3090 word_num = (vfid - 192) / 32;
3091 bit_num = vfid % 32;
3093 desc[2].data[word_num] &= ~(1 << bit_num);
3095 desc[2].data[word_num] |= (1 << bit_num);
3101 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3103 #define HCLGE_DESC_NUMBER 3
3104 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3107 for (i = 1; i < HCLGE_DESC_NUMBER; i++)
3108 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3109 if (desc[i].data[j])
3115 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry *new_req,
3118 const unsigned char *mac_addr = addr;
3119 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3120 (mac_addr[0]) | (mac_addr[1] << 8);
3121 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3123 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3124 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3127 u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3130 u16 high_val = addr[1] | (addr[0] << 8);
3131 struct hclge_dev *hdev = vport->back;
3132 u32 rsh = 4 - hdev->mta_mac_sel_type;
3133 u16 ret_val = (high_val >> rsh) & 0xfff;
3138 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3139 enum hclge_mta_dmac_sel_type mta_mac_sel,
3142 struct hclge_mta_filter_mode *req;
3143 struct hclge_desc desc;
3146 req = (struct hclge_mta_filter_mode *)desc.data;
3147 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3149 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3151 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3152 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3154 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3156 dev_err(&hdev->pdev->dev,
3157 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3165 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3169 struct hclge_cfg_func_mta_filter *req;
3170 struct hclge_desc desc;
3173 req = (struct hclge_cfg_func_mta_filter *)desc.data;
3174 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3176 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3178 req->function_id = func_id;
3180 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3182 dev_err(&hdev->pdev->dev,
3183 "Config func_id enable failed for cmd_send, ret =%d.\n",
3191 static int hclge_set_mta_table_item(struct hclge_vport *vport,
3195 struct hclge_dev *hdev = vport->back;
3196 struct hclge_cfg_func_mta_item *req;
3197 struct hclge_desc desc;
3200 req = (struct hclge_cfg_func_mta_item *)desc.data;
3201 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3202 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3204 hnae_set_field(req->item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
3205 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
3206 req->item_idx = cpu_to_le16(req->item_idx);
3208 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3210 dev_err(&hdev->pdev->dev,
3211 "Config mta table item failed for cmd_send, ret =%d.\n",
3219 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
3220 struct hclge_mac_vlan_tbl_entry *req)
3222 struct hclge_dev *hdev = vport->back;
3223 struct hclge_desc desc;
3227 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3229 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry));
3231 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3233 dev_err(&hdev->pdev->dev,
3234 "del mac addr failed for cmd_send, ret =%d.\n",
3238 resp_code = (desc.data[0] >> 8) & 0xff;
3240 return hclge_get_mac_vlan_cmd_status(vport, desc.retval, resp_code,
3241 HCLGE_MAC_VLAN_REMOVE);
3244 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
3245 struct hclge_mac_vlan_tbl_entry *req,
3246 struct hclge_desc *desc,
3249 struct hclge_dev *hdev = vport->back;
3253 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3255 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3256 memcpy(desc[0].data,
3258 sizeof(struct hclge_mac_vlan_tbl_entry));
3259 hclge_cmd_setup_basic_desc(&desc[1],
3260 HCLGE_OPC_MAC_VLAN_ADD,
3262 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3263 hclge_cmd_setup_basic_desc(&desc[2],
3264 HCLGE_OPC_MAC_VLAN_ADD,
3266 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3268 memcpy(desc[0].data,
3270 sizeof(struct hclge_mac_vlan_tbl_entry));
3271 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3274 dev_err(&hdev->pdev->dev,
3275 "lookup mac addr failed for cmd_send, ret =%d.\n",
3279 resp_code = (desc[0].data[0] >> 8) & 0xff;
3281 return hclge_get_mac_vlan_cmd_status(vport, desc[0].retval, resp_code,
3282 HCLGE_MAC_VLAN_LKUP);
3285 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
3286 struct hclge_mac_vlan_tbl_entry *req,
3287 struct hclge_desc *mc_desc)
3289 struct hclge_dev *hdev = vport->back;
3295 struct hclge_desc desc;
3297 hclge_cmd_setup_basic_desc(&desc,
3298 HCLGE_OPC_MAC_VLAN_ADD,
3300 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry));
3301 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3302 resp_code = (desc.data[0] >> 8) & 0xff;
3303 cfg_status = hclge_get_mac_vlan_cmd_status(vport, desc.retval,
3305 HCLGE_MAC_VLAN_ADD);
3307 mc_desc[0].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3308 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3309 mc_desc[1].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3310 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3311 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3312 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3313 memcpy(mc_desc[0].data, req,
3314 sizeof(struct hclge_mac_vlan_tbl_entry));
3315 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
3316 resp_code = (mc_desc[0].data[0] >> 8) & 0xff;
3317 cfg_status = hclge_get_mac_vlan_cmd_status(vport,
3320 HCLGE_MAC_VLAN_ADD);
3324 dev_err(&hdev->pdev->dev,
3325 "add mac addr failed for cmd_send, ret =%d.\n",
3333 static int hclge_add_uc_addr(struct hnae3_handle *handle,
3334 const unsigned char *addr)
3336 struct hclge_vport *vport = hclge_get_vport(handle);
3338 return hclge_add_uc_addr_common(vport, addr);
3341 int hclge_add_uc_addr_common(struct hclge_vport *vport,
3342 const unsigned char *addr)
3344 struct hclge_dev *hdev = vport->back;
3345 struct hclge_mac_vlan_tbl_entry req;
3346 enum hclge_cmd_status status;
3348 /* mac addr check */
3349 if (is_zero_ether_addr(addr) ||
3350 is_broadcast_ether_addr(addr) ||
3351 is_multicast_ether_addr(addr)) {
3352 dev_err(&hdev->pdev->dev,
3353 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3355 is_zero_ether_addr(addr),
3356 is_broadcast_ether_addr(addr),
3357 is_multicast_ether_addr(addr));
3361 memset(&req, 0, sizeof(req));
3362 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3363 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3364 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
3365 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3366 hnae_set_bit(req.egress_port,
3367 HCLGE_MAC_EPORT_SW_EN_B, 0);
3368 hnae_set_bit(req.egress_port,
3369 HCLGE_MAC_EPORT_TYPE_B, 0);
3370 hnae_set_field(req.egress_port, HCLGE_MAC_EPORT_VFID_M,
3371 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
3372 hnae_set_field(req.egress_port, HCLGE_MAC_EPORT_PFID_M,
3373 HCLGE_MAC_EPORT_PFID_S, 0);
3374 req.egress_port = cpu_to_le16(req.egress_port);
3376 hclge_prepare_mac_addr(&req, addr);
3378 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
3383 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
3384 const unsigned char *addr)
3386 struct hclge_vport *vport = hclge_get_vport(handle);
3388 return hclge_rm_uc_addr_common(vport, addr);
3391 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
3392 const unsigned char *addr)
3394 struct hclge_dev *hdev = vport->back;
3395 struct hclge_mac_vlan_tbl_entry req;
3396 enum hclge_cmd_status status;
3398 /* mac addr check */
3399 if (is_zero_ether_addr(addr) ||
3400 is_broadcast_ether_addr(addr) ||
3401 is_multicast_ether_addr(addr)) {
3402 dev_dbg(&hdev->pdev->dev,
3403 "Remove mac err! invalid mac:%pM.\n",
3408 memset(&req, 0, sizeof(req));
3409 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3410 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3411 hclge_prepare_mac_addr(&req, addr);
3412 status = hclge_remove_mac_vlan_tbl(vport, &req);
3417 static int hclge_add_mc_addr(struct hnae3_handle *handle,
3418 const unsigned char *addr)
3420 struct hclge_vport *vport = hclge_get_vport(handle);
3422 return hclge_add_mc_addr_common(vport, addr);
3425 int hclge_add_mc_addr_common(struct hclge_vport *vport,
3426 const unsigned char *addr)
3428 struct hclge_dev *hdev = vport->back;
3429 struct hclge_mac_vlan_tbl_entry req;
3430 struct hclge_desc desc[3];
3434 /* mac addr check */
3435 if (!is_multicast_ether_addr(addr)) {
3436 dev_err(&hdev->pdev->dev,
3437 "Add mc mac err! invalid mac:%pM.\n",
3441 memset(&req, 0, sizeof(req));
3442 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3443 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3444 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
3445 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3446 hclge_prepare_mac_addr(&req, addr);
3447 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
3449 /* This mac addr exist, update VFID for it */
3450 hclge_update_desc_vfid(desc, vport->vport_id, false);
3451 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3453 /* This mac addr do not exist, add new entry for it */
3454 memset(desc[0].data, 0, sizeof(desc[0].data));
3455 memset(desc[1].data, 0, sizeof(desc[0].data));
3456 memset(desc[2].data, 0, sizeof(desc[0].data));
3457 hclge_update_desc_vfid(desc, vport->vport_id, false);
3458 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3461 /* Set MTA table for this MAC address */
3462 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
3463 status = hclge_set_mta_table_item(vport, tbl_idx, true);
3468 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
3469 const unsigned char *addr)
3471 struct hclge_vport *vport = hclge_get_vport(handle);
3473 return hclge_rm_mc_addr_common(vport, addr);
3476 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
3477 const unsigned char *addr)
3479 struct hclge_dev *hdev = vport->back;
3480 struct hclge_mac_vlan_tbl_entry req;
3481 enum hclge_cmd_status status;
3482 struct hclge_desc desc[3];
3485 /* mac addr check */
3486 if (!is_multicast_ether_addr(addr)) {
3487 dev_dbg(&hdev->pdev->dev,
3488 "Remove mc mac err! invalid mac:%pM.\n",
3493 memset(&req, 0, sizeof(req));
3494 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3495 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3496 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
3497 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3498 hclge_prepare_mac_addr(&req, addr);
3499 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
3501 /* This mac addr exist, remove this handle's VFID for it */
3502 hclge_update_desc_vfid(desc, vport->vport_id, true);
3504 if (hclge_is_all_function_id_zero(desc))
3505 /* All the vfid is zero, so need to delete this entry */
3506 status = hclge_remove_mac_vlan_tbl(vport, &req);
3508 /* Not all the vfid is zero, update the vfid */
3509 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3512 /* This mac addr do not exist, can't delete it */
3513 dev_err(&hdev->pdev->dev,
3514 "Rm multicast mac addr failed, ret = %d.\n",
3519 /* Set MTB table for this MAC address */
3520 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
3521 status = hclge_set_mta_table_item(vport, tbl_idx, false);
3526 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
3528 struct hclge_vport *vport = hclge_get_vport(handle);
3529 struct hclge_dev *hdev = vport->back;
3531 ether_addr_copy(p, hdev->hw.mac.mac_addr);
3534 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
3536 const unsigned char *new_addr = (const unsigned char *)p;
3537 struct hclge_vport *vport = hclge_get_vport(handle);
3538 struct hclge_dev *hdev = vport->back;
3540 /* mac addr check */
3541 if (is_zero_ether_addr(new_addr) ||
3542 is_broadcast_ether_addr(new_addr) ||
3543 is_multicast_ether_addr(new_addr)) {
3544 dev_err(&hdev->pdev->dev,
3545 "Change uc mac err! invalid mac:%p.\n",
3550 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
3552 if (!hclge_add_uc_addr(handle, new_addr)) {
3553 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
3560 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
3563 struct hclge_vlan_filter_ctrl *req;
3564 struct hclge_desc desc;
3567 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
3569 req = (struct hclge_vlan_filter_ctrl *)desc.data;
3570 req->vlan_type = vlan_type;
3571 req->vlan_fe = filter_en;
3573 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3575 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
3583 int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
3584 bool is_kill, u16 vlan, u8 qos, __be16 proto)
3586 #define HCLGE_MAX_VF_BYTES 16
3587 struct hclge_vlan_filter_vf_cfg *req0;
3588 struct hclge_vlan_filter_vf_cfg *req1;
3589 struct hclge_desc desc[2];
3594 hclge_cmd_setup_basic_desc(&desc[0],
3595 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
3596 hclge_cmd_setup_basic_desc(&desc[1],
3597 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
3599 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3601 vf_byte_off = vfid / 8;
3602 vf_byte_val = 1 << (vfid % 8);
3604 req0 = (struct hclge_vlan_filter_vf_cfg *)desc[0].data;
3605 req1 = (struct hclge_vlan_filter_vf_cfg *)desc[1].data;
3607 req0->vlan_id = vlan;
3608 req0->vlan_cfg = is_kill;
3610 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
3611 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
3613 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
3615 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3617 dev_err(&hdev->pdev->dev,
3618 "Send vf vlan command fail, ret =%d.\n",
3624 if (!req0->resp_code || req0->resp_code == 1)
3627 dev_err(&hdev->pdev->dev,
3628 "Add vf vlan filter fail, ret =%d.\n",
3631 if (!req0->resp_code)
3634 dev_err(&hdev->pdev->dev,
3635 "Kill vf vlan filter fail, ret =%d.\n",
3642 static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
3643 __be16 proto, u16 vlan_id,
3646 struct hclge_vport *vport = hclge_get_vport(handle);
3647 struct hclge_dev *hdev = vport->back;
3648 struct hclge_vlan_filter_pf_cfg *req;
3649 struct hclge_desc desc;
3650 u8 vlan_offset_byte_val;
3651 u8 vlan_offset_byte;
3655 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
3657 vlan_offset_160 = vlan_id / 160;
3658 vlan_offset_byte = (vlan_id % 160) / 8;
3659 vlan_offset_byte_val = 1 << (vlan_id % 8);
3661 req = (struct hclge_vlan_filter_pf_cfg *)desc.data;
3662 req->vlan_offset = vlan_offset_160;
3663 req->vlan_cfg = is_kill;
3664 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
3666 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3668 dev_err(&hdev->pdev->dev,
3669 "port vlan command, send fail, ret =%d.\n",
3674 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
3676 dev_err(&hdev->pdev->dev,
3677 "Set pf vlan filter config fail, ret =%d.\n",
3685 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
3686 u16 vlan, u8 qos, __be16 proto)
3688 struct hclge_vport *vport = hclge_get_vport(handle);
3689 struct hclge_dev *hdev = vport->back;
3691 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
3693 if (proto != htons(ETH_P_8021Q))
3694 return -EPROTONOSUPPORT;
3696 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
3699 static int hclge_init_vlan_config(struct hclge_dev *hdev)
3701 #define HCLGE_VLAN_TYPE_VF_TABLE 0
3702 #define HCLGE_VLAN_TYPE_PORT_TABLE 1
3703 struct hnae3_handle *handle;
3706 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_VF_TABLE,
3711 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_PORT_TABLE,
3716 handle = &hdev->vport[0].nic;
3717 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
3720 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
3722 struct hclge_vport *vport = hclge_get_vport(handle);
3723 struct hclge_config_max_frm_size *req;
3724 struct hclge_dev *hdev = vport->back;
3725 struct hclge_desc desc;
3728 if ((new_mtu < HCLGE_MAC_MIN_MTU) || (new_mtu > HCLGE_MAC_MAX_MTU))
3731 hdev->mps = new_mtu;
3732 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
3734 req = (struct hclge_config_max_frm_size *)desc.data;
3735 req->max_frm_size = cpu_to_le16(new_mtu);
3737 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3739 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
3746 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
3749 struct hclge_reset_tqp_queue *req;
3750 struct hclge_desc desc;
3753 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
3755 req = (struct hclge_reset_tqp_queue *)desc.data;
3756 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
3757 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
3759 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3761 dev_err(&hdev->pdev->dev,
3762 "Send tqp reset cmd error, status =%d\n", ret);
3769 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
3771 struct hclge_reset_tqp_queue *req;
3772 struct hclge_desc desc;
3775 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
3777 req = (struct hclge_reset_tqp_queue *)desc.data;
3778 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
3780 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3782 dev_err(&hdev->pdev->dev,
3783 "Get reset status error, status =%d\n", ret);
3787 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
3790 static void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
3792 struct hclge_vport *vport = hclge_get_vport(handle);
3793 struct hclge_dev *hdev = vport->back;
3794 int reset_try_times = 0;
3798 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
3800 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
3804 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
3806 dev_warn(&hdev->pdev->dev,
3807 "Send reset tqp cmd fail, ret = %d\n", ret);
3811 reset_try_times = 0;
3812 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
3813 /* Wait for tqp hw reset */
3815 reset_status = hclge_get_reset_status(hdev, queue_id);
3820 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
3821 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
3825 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
3827 dev_warn(&hdev->pdev->dev,
3828 "Deassert the soft reset fail, ret = %d\n", ret);
3833 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
3835 struct hclge_vport *vport = hclge_get_vport(handle);
3836 struct hclge_dev *hdev = vport->back;
3838 return hdev->fw_version;
3841 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
3842 u32 *rx_en, u32 *tx_en)
3844 struct hclge_vport *vport = hclge_get_vport(handle);
3845 struct hclge_dev *hdev = vport->back;
3847 *auto_neg = hclge_get_autoneg(handle);
3849 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
3855 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
3858 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
3861 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
3870 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
3871 u8 *auto_neg, u32 *speed, u8 *duplex)
3873 struct hclge_vport *vport = hclge_get_vport(handle);
3874 struct hclge_dev *hdev = vport->back;
3877 *speed = hdev->hw.mac.speed;
3879 *duplex = hdev->hw.mac.duplex;
3881 *auto_neg = hdev->hw.mac.autoneg;
3884 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
3886 struct hclge_vport *vport = hclge_get_vport(handle);
3887 struct hclge_dev *hdev = vport->back;
3890 *media_type = hdev->hw.mac.media_type;
3893 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
3894 u8 *tp_mdix_ctrl, u8 *tp_mdix)
3896 struct hclge_vport *vport = hclge_get_vport(handle);
3897 struct hclge_dev *hdev = vport->back;
3898 struct phy_device *phydev = hdev->hw.mac.phydev;
3899 int mdix_ctrl, mdix, retval, is_resolved;
3902 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
3903 *tp_mdix = ETH_TP_MDI_INVALID;
3907 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
3909 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
3910 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
3911 HCLGE_PHY_MDIX_CTRL_S);
3913 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
3914 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
3915 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
3917 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
3919 switch (mdix_ctrl) {
3921 *tp_mdix_ctrl = ETH_TP_MDI;
3924 *tp_mdix_ctrl = ETH_TP_MDI_X;
3927 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
3930 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
3935 *tp_mdix = ETH_TP_MDI_INVALID;
3937 *tp_mdix = ETH_TP_MDI_X;
3939 *tp_mdix = ETH_TP_MDI;
3942 static int hclge_init_client_instance(struct hnae3_client *client,
3943 struct hnae3_ae_dev *ae_dev)
3945 struct hclge_dev *hdev = ae_dev->priv;
3946 struct hclge_vport *vport;
3949 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3950 vport = &hdev->vport[i];
3952 switch (client->type) {
3953 case HNAE3_CLIENT_KNIC:
3955 hdev->nic_client = client;
3956 vport->nic.client = client;
3957 ret = client->ops->init_instance(&vport->nic);
3961 if (hdev->roce_client &&
3962 hnae3_dev_roce_supported(hdev)) {
3963 struct hnae3_client *rc = hdev->roce_client;
3965 ret = hclge_init_roce_base_info(vport);
3969 ret = rc->ops->init_instance(&vport->roce);
3975 case HNAE3_CLIENT_UNIC:
3976 hdev->nic_client = client;
3977 vport->nic.client = client;
3979 ret = client->ops->init_instance(&vport->nic);
3984 case HNAE3_CLIENT_ROCE:
3985 if (hnae3_dev_roce_supported(hdev)) {
3986 hdev->roce_client = client;
3987 vport->roce.client = client;
3990 if (hdev->roce_client && hdev->nic_client) {
3991 ret = hclge_init_roce_base_info(vport);
3995 ret = client->ops->init_instance(&vport->roce);
4007 static void hclge_uninit_client_instance(struct hnae3_client *client,
4008 struct hnae3_ae_dev *ae_dev)
4010 struct hclge_dev *hdev = ae_dev->priv;
4011 struct hclge_vport *vport;
4014 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4015 vport = &hdev->vport[i];
4016 if (hdev->roce_client) {
4017 hdev->roce_client->ops->uninit_instance(&vport->roce,
4019 hdev->roce_client = NULL;
4020 vport->roce.client = NULL;
4022 if (client->type == HNAE3_CLIENT_ROCE)
4024 if (client->ops->uninit_instance) {
4025 client->ops->uninit_instance(&vport->nic, 0);
4026 hdev->nic_client = NULL;
4027 vport->nic.client = NULL;
4032 static int hclge_pci_init(struct hclge_dev *hdev)
4034 struct pci_dev *pdev = hdev->pdev;
4035 struct hclge_hw *hw;
4038 ret = pci_enable_device(pdev);
4040 dev_err(&pdev->dev, "failed to enable PCI device\n");
4041 goto err_no_drvdata;
4044 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4046 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4049 "can't set consistent PCI DMA");
4050 goto err_disable_device;
4052 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
4055 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
4057 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
4058 goto err_disable_device;
4061 pci_set_master(pdev);
4064 hw->io_base = pcim_iomap(pdev, 2, 0);
4066 dev_err(&pdev->dev, "Can't map configuration register space\n");
4068 goto err_clr_master;
4073 pci_clear_master(pdev);
4074 pci_release_regions(pdev);
4076 pci_disable_device(pdev);
4078 pci_set_drvdata(pdev, NULL);
4083 static void hclge_pci_uninit(struct hclge_dev *hdev)
4085 struct pci_dev *pdev = hdev->pdev;
4087 if (hdev->flag & HCLGE_FLAG_USE_MSIX) {
4088 pci_disable_msix(pdev);
4089 devm_kfree(&pdev->dev, hdev->msix_entries);
4090 hdev->msix_entries = NULL;
4092 pci_disable_msi(pdev);
4095 pci_clear_master(pdev);
4096 pci_release_mem_regions(pdev);
4097 pci_disable_device(pdev);
4100 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
4102 struct pci_dev *pdev = ae_dev->pdev;
4103 struct hclge_dev *hdev;
4106 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
4112 hdev->flag |= HCLGE_FLAG_USE_MSIX;
4114 hdev->ae_dev = ae_dev;
4115 ae_dev->priv = hdev;
4117 ret = hclge_pci_init(hdev);
4119 dev_err(&pdev->dev, "PCI init failed\n");
4123 /* Command queue initialize */
4124 ret = hclge_cmd_init(hdev);
4128 ret = hclge_get_cap(hdev);
4130 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4135 ret = hclge_configure(hdev);
4137 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4141 if (hdev->flag & HCLGE_FLAG_USE_MSIX)
4142 ret = hclge_init_msix(hdev);
4144 ret = hclge_init_msi(hdev);
4146 dev_err(&pdev->dev, "Init msix/msi error, ret = %d.\n", ret);
4150 ret = hclge_alloc_tqps(hdev);
4152 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
4156 ret = hclge_alloc_vport(hdev);
4158 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
4162 ret = hclge_mac_init(hdev);
4164 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4167 ret = hclge_buffer_alloc(hdev);
4169 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4173 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4175 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4179 ret = hclge_init_vlan_config(hdev);
4181 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4185 ret = hclge_tm_schd_init(hdev);
4187 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4191 ret = hclge_rss_init_hw(hdev);
4193 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4197 setup_timer(&hdev->service_timer, hclge_service_timer,
4198 (unsigned long)hdev);
4199 INIT_WORK(&hdev->service_task, hclge_service_task);
4201 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
4202 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4204 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
4208 pci_release_regions(pdev);
4210 pci_set_drvdata(pdev, NULL);
4215 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
4217 struct hclge_dev *hdev = ae_dev->priv;
4218 struct hclge_mac *mac = &hdev->hw.mac;
4220 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4222 if (IS_ENABLED(CONFIG_PCI_IOV))
4223 hclge_disable_sriov(hdev);
4225 if (hdev->service_timer.data)
4226 del_timer_sync(&hdev->service_timer);
4227 if (hdev->service_task.func)
4228 cancel_work_sync(&hdev->service_task);
4231 mdiobus_unregister(mac->mdio_bus);
4233 hclge_destroy_cmd_queue(&hdev->hw);
4234 hclge_pci_uninit(hdev);
4235 ae_dev->priv = NULL;
4238 static const struct hnae3_ae_ops hclge_ops = {
4239 .init_ae_dev = hclge_init_ae_dev,
4240 .uninit_ae_dev = hclge_uninit_ae_dev,
4241 .init_client_instance = hclge_init_client_instance,
4242 .uninit_client_instance = hclge_uninit_client_instance,
4243 .map_ring_to_vector = hclge_map_handle_ring_to_vector,
4244 .unmap_ring_from_vector = hclge_unmap_ring_from_vector,
4245 .get_vector = hclge_get_vector,
4246 .set_promisc_mode = hclge_set_promisc_mode,
4247 .start = hclge_ae_start,
4248 .stop = hclge_ae_stop,
4249 .get_status = hclge_get_status,
4250 .get_ksettings_an_result = hclge_get_ksettings_an_result,
4251 .update_speed_duplex_h = hclge_update_speed_duplex_h,
4252 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
4253 .get_media_type = hclge_get_media_type,
4254 .get_rss_key_size = hclge_get_rss_key_size,
4255 .get_rss_indir_size = hclge_get_rss_indir_size,
4256 .get_rss = hclge_get_rss,
4257 .set_rss = hclge_set_rss,
4258 .get_tc_size = hclge_get_tc_size,
4259 .get_mac_addr = hclge_get_mac_addr,
4260 .set_mac_addr = hclge_set_mac_addr,
4261 .add_uc_addr = hclge_add_uc_addr,
4262 .rm_uc_addr = hclge_rm_uc_addr,
4263 .add_mc_addr = hclge_add_mc_addr,
4264 .rm_mc_addr = hclge_rm_mc_addr,
4265 .set_autoneg = hclge_set_autoneg,
4266 .get_autoneg = hclge_get_autoneg,
4267 .get_pauseparam = hclge_get_pauseparam,
4268 .set_mtu = hclge_set_mtu,
4269 .reset_queue = hclge_reset_tqp,
4270 .get_stats = hclge_get_stats,
4271 .update_stats = hclge_update_stats,
4272 .get_strings = hclge_get_strings,
4273 .get_sset_count = hclge_get_sset_count,
4274 .get_fw_version = hclge_get_fw_version,
4275 .get_mdix_mode = hclge_get_mdix_mode,
4276 .set_vlan_filter = hclge_set_port_vlan_filter,
4277 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
4280 static struct hnae3_ae_algo ae_algo = {
4283 .pdev_id_table = ae_algo_pci_tbl,
4286 static int hclge_init(void)
4288 pr_info("%s is initializing\n", HCLGE_NAME);
4290 return hnae3_register_ae_algo(&ae_algo);
4293 static void hclge_exit(void)
4295 hnae3_unregister_ae_algo(&ae_algo);
4297 module_init(hclge_init);
4298 module_exit(hclge_exit);
4300 MODULE_LICENSE("GPL");
4301 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4302 MODULE_DESCRIPTION("HCLGE Driver");
4303 MODULE_VERSION(HCLGE_MOD_VERSION);