1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
8 #include <linux/if_vlan.h>
9 #include <net/page_pool/types.h>
10 #include <asm/barrier.h>
18 HNS3_NIC_STATE_TESTING,
19 HNS3_NIC_STATE_RESETTING,
20 HNS3_NIC_STATE_INITED,
22 HNS3_NIC_STATE_DISABLED,
23 HNS3_NIC_STATE_REMOVING,
24 HNS3_NIC_STATE_SERVICE_INITED,
25 HNS3_NIC_STATE_SERVICE_SCHED,
26 HNS3_NIC_STATE2_RESET_REQUESTED,
27 HNS3_NIC_STATE_HW_TX_CSUM_ENABLE,
28 HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE,
29 HNS3_NIC_STATE_TX_PUSH_ENABLE,
33 #define HNS3_MAX_PUSH_BD_NUM 2
35 #define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
36 #define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
37 #define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
38 #define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
39 #define HNS3_RING_RX_RING_TAIL_REG 0x00018
40 #define HNS3_RING_RX_RING_HEAD_REG 0x0001C
41 #define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
42 #define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
44 #define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
45 #define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
46 #define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
47 #define HNS3_RING_TX_RING_TC_REG 0x00050
48 #define HNS3_RING_TX_RING_TAIL_REG 0x00058
49 #define HNS3_RING_TX_RING_HEAD_REG 0x0005C
50 #define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
51 #define HNS3_RING_TX_RING_OFFSET_REG 0x00064
52 #define HNS3_RING_TX_RING_EBDNUM_REG 0x00068
53 #define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
54 #define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070
55 #define HNS3_RING_TX_RING_BD_ERR_REG 0x00074
56 #define HNS3_RING_EN_REG 0x00090
57 #define HNS3_RING_RX_EN_REG 0x00098
58 #define HNS3_RING_TX_EN_REG 0x000D4
60 #define HNS3_RX_HEAD_SIZE 256
62 #define HNS3_TX_TIMEOUT (5 * HZ)
63 #define HNS3_RING_NAME_LEN 16
64 #define HNS3_BUFFER_SIZE_2048 2048
65 #define HNS3_RING_MAX_PENDING 32760
66 #define HNS3_RING_MIN_PENDING 72
67 #define HNS3_RING_BD_MULTIPLE 8
68 /* max frame size of mac */
69 #define HNS3_MAX_MTU(max_frm_size) \
70 ((max_frm_size) - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))
72 #define HNS3_BD_SIZE_512_TYPE 0
73 #define HNS3_BD_SIZE_1024_TYPE 1
74 #define HNS3_BD_SIZE_2048_TYPE 2
75 #define HNS3_BD_SIZE_4096_TYPE 3
77 #define HNS3_RX_FLAG_VLAN_PRESENT 0x1
78 #define HNS3_RX_FLAG_L3ID_IPV4 0x0
79 #define HNS3_RX_FLAG_L3ID_IPV6 0x1
80 #define HNS3_RX_FLAG_L4ID_UDP 0x0
81 #define HNS3_RX_FLAG_L4ID_TCP 0x1
83 #define HNS3_RXD_DMAC_S 0
84 #define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
85 #define HNS3_RXD_VLAN_S 2
86 #define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
87 #define HNS3_RXD_L3ID_S 4
88 #define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
89 #define HNS3_RXD_L4ID_S 8
90 #define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
91 #define HNS3_RXD_FRAG_B 12
92 #define HNS3_RXD_STRP_TAGP_S 13
93 #define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
95 #define HNS3_RXD_L2E_B 16
96 #define HNS3_RXD_L3E_B 17
97 #define HNS3_RXD_L4E_B 18
98 #define HNS3_RXD_TRUNCAT_B 19
99 #define HNS3_RXD_HOI_B 20
100 #define HNS3_RXD_DOI_B 21
101 #define HNS3_RXD_OL3E_B 22
102 #define HNS3_RXD_OL4E_B 23
103 #define HNS3_RXD_GRO_COUNT_S 24
104 #define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
105 #define HNS3_RXD_GRO_FIXID_B 30
106 #define HNS3_RXD_GRO_ECN_B 31
108 #define HNS3_RXD_ODMAC_S 0
109 #define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
110 #define HNS3_RXD_OVLAN_S 2
111 #define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
112 #define HNS3_RXD_OL3ID_S 4
113 #define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
114 #define HNS3_RXD_OL4ID_S 8
115 #define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
116 #define HNS3_RXD_FBHI_S 12
117 #define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
118 #define HNS3_RXD_FBLI_S 14
119 #define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
121 #define HNS3_RXD_PTYPE_S 4
122 #define HNS3_RXD_PTYPE_M GENMASK(11, 4)
124 #define HNS3_RXD_BDTYPE_S 0
125 #define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
126 #define HNS3_RXD_VLD_B 4
127 #define HNS3_RXD_UDP0_B 5
128 #define HNS3_RXD_EXTEND_B 7
129 #define HNS3_RXD_FE_B 8
130 #define HNS3_RXD_LUM_B 9
131 #define HNS3_RXD_CRCP_B 10
132 #define HNS3_RXD_L3L4P_B 11
133 #define HNS3_RXD_TSIDX_S 12
134 #define HNS3_RXD_TSIDX_M (0x3 << HNS3_RXD_TSIDX_S)
135 #define HNS3_RXD_TS_VLD_B 14
136 #define HNS3_RXD_LKBK_B 15
137 #define HNS3_RXD_GRO_SIZE_S 16
138 #define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
140 #define HNS3_TXD_L3T_S 0
141 #define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
142 #define HNS3_TXD_L4T_S 2
143 #define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
144 #define HNS3_TXD_L3CS_B 4
145 #define HNS3_TXD_L4CS_B 5
146 #define HNS3_TXD_VLAN_B 6
147 #define HNS3_TXD_TSO_B 7
149 #define HNS3_TXD_L2LEN_S 8
150 #define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
151 #define HNS3_TXD_L3LEN_S 16
152 #define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
153 #define HNS3_TXD_L4LEN_S 24
154 #define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
156 #define HNS3_TXD_CSUM_START_S 8
157 #define HNS3_TXD_CSUM_START_M (0xffff << HNS3_TXD_CSUM_START_S)
159 #define HNS3_TXD_OL3T_S 0
160 #define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
161 #define HNS3_TXD_OVLAN_B 2
162 #define HNS3_TXD_MACSEC_B 3
163 #define HNS3_TXD_TUNTYPE_S 4
164 #define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
166 #define HNS3_TXD_CSUM_OFFSET_S 8
167 #define HNS3_TXD_CSUM_OFFSET_M (0xffff << HNS3_TXD_CSUM_OFFSET_S)
169 #define HNS3_TXD_BDTYPE_S 0
170 #define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
171 #define HNS3_TXD_FE_B 4
172 #define HNS3_TXD_SC_S 5
173 #define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
174 #define HNS3_TXD_EXTEND_B 7
175 #define HNS3_TXD_VLD_B 8
176 #define HNS3_TXD_RI_B 9
177 #define HNS3_TXD_RA_B 10
178 #define HNS3_TXD_TSYN_B 11
179 #define HNS3_TXD_DECTTL_S 12
180 #define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
182 #define HNS3_TXD_OL4CS_B 22
184 #define HNS3_TXD_MSS_S 0
185 #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
186 #define HNS3_TXD_HW_CS_B 14
188 #define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
189 #define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
191 #define HNS3_VECTOR_NOT_INITED 0
192 #define HNS3_VECTOR_INITED 1
194 #define HNS3_MAX_BD_SIZE 65535
195 #define HNS3_MAX_TSO_BD_NUM 63U
196 #define HNS3_MAX_TSO_SIZE 1048576U
197 #define HNS3_MAX_NON_TSO_SIZE 9728U
199 #define HNS3_VECTOR_GL_MASK GENMASK(11, 0)
200 #define HNS3_VECTOR_GL0_OFFSET 0x100
201 #define HNS3_VECTOR_GL1_OFFSET 0x200
202 #define HNS3_VECTOR_GL2_OFFSET 0x300
203 #define HNS3_VECTOR_RL_OFFSET 0x900
204 #define HNS3_VECTOR_RL_EN_B 6
205 #define HNS3_VECTOR_QL_MASK GENMASK(9, 0)
206 #define HNS3_VECTOR_TX_QL_OFFSET 0xe00
207 #define HNS3_VECTOR_RX_QL_OFFSET 0xf00
209 #define HNS3_RING_EN_B 0
211 #define HNS3_GL0_CQ_MODE_REG 0x20d00
212 #define HNS3_GL1_CQ_MODE_REG 0x20d04
213 #define HNS3_GL2_CQ_MODE_REG 0x20d08
214 #define HNS3_CQ_MODE_EQE 1U
215 #define HNS3_CQ_MODE_CQE 0U
217 enum hns3_pkt_l2t_type {
218 HNS3_L2_TYPE_UNICAST,
219 HNS3_L2_TYPE_MULTICAST,
220 HNS3_L2_TYPE_BROADCAST,
221 HNS3_L2_TYPE_INVALID,
224 enum hns3_pkt_l3t_type {
231 enum hns3_pkt_l4t_type {
238 enum hns3_pkt_ol3t_type {
241 HNS3_OL3T_IPV4_NO_CSUM,
245 enum hns3_pkt_tun_type {
252 /* hardware spec ring buffer format */
253 struct __packed hns3_desc {
267 __le32 type_cs_vlan_tso_len;
269 __u8 type_cs_vlan_tso;
275 __le16 outer_vlan_tag;
279 __le32 ol_type_vlan_len_msec;
281 __u8 ol_type_vlan_msec;
289 __le16 bdtp_fe_sc_vld_ra_ri;
305 __le16 o_dm_vlan_id_fb;
315 enum hns3_desc_type {
316 DESC_TYPE_UNKNOWN = 0,
317 DESC_TYPE_SKB = 1 << 0,
318 DESC_TYPE_FRAGLIST_SKB = 1 << 1,
319 DESC_TYPE_PAGE = 1 << 2,
320 DESC_TYPE_BOUNCE_ALL = 1 << 3,
321 DESC_TYPE_BOUNCE_HEAD = 1 << 4,
322 DESC_TYPE_SGL_SKB = 1 << 5,
323 DESC_TYPE_PP_FRAG = 1 << 6,
326 struct hns3_desc_cb {
327 dma_addr_t dma; /* dma address of this desc */
328 void *buf; /* cpu addr for a desc */
330 /* priv data for the desc, e.g. skb when use with ip stack */
334 u32 page_offset; /* for rx */
335 u32 send_bytes; /* for tx */
338 u32 length; /* length of the buffer */
343 /* desc type, used by the ring user to mark the type of the priv data */
348 enum hns3_pkt_l3type {
353 HNS3_L3_TYPE_IPV4_OPT,
354 HNS3_L3_TYPE_IPV6_EXT,
357 HNS3_L3_TYPE_MAC_PAUSE,
358 HNS3_L3_TYPE_PFC_PAUSE, /* 0x9 */
360 /* reserved for 0xA~0xB */
362 HNS3_L3_TYPE_CNM = 0xc,
364 /* reserved for 0xD~0xE */
366 HNS3_L3_TYPE_PARSE_FAIL = 0xf /* must be last */
369 enum hns3_pkt_l4type {
377 /* reserved for 0x6~0xE */
379 HNS3_L4_TYPE_PARSE_FAIL = 0xf /* must be last */
382 enum hns3_pkt_ol3type {
383 HNS3_OL3_TYPE_IPV4 = 0,
385 /* reserved for 0x2~0x3 */
386 HNS3_OL3_TYPE_IPV4_OPT = 4,
387 HNS3_OL3_TYPE_IPV6_EXT,
389 /* reserved for 0x6~0xE */
391 HNS3_OL3_TYPE_PARSE_FAIL = 0xf /* must be last */
394 enum hns3_pkt_ol4type {
395 HNS3_OL4_TYPE_NO_TUN,
396 HNS3_OL4_TYPE_MAC_IN_UDP,
398 HNS3_OL4_TYPE_UNKNOWN
401 struct hns3_rx_ptype {
427 u64 over_max_recursion;
455 struct hns3_tx_spare {
464 struct hns3_enet_ring {
465 struct hns3_desc *desc; /* dma map address space */
466 struct hns3_desc_cb *desc_cb;
467 struct hns3_enet_ring *next;
468 struct hns3_enet_tqp_vector *tqp_vector;
469 struct hnae3_queue *tqp;
471 struct device *dev; /* will be used for DMA mapping of descriptors */
472 struct page_pool *page_pool;
475 struct ring_stats stats;
476 struct u64_stats_sync syncp;
478 dma_addr_t desc_dma_addr;
479 u32 buf_size; /* size for hnae_desc->addr, preset by AE */
480 u16 desc_num; /* total number of desc */
481 int next_to_use; /* idx of next spare desc */
483 /* idx of lastest sent desc, the ring is empty when equal to
487 u32 flag; /* ring attribute */
494 int last_to_use; /* last idx used by xmit */
496 struct hns3_tx_spare *tx_spare;
501 u32 pull_len; /* memcpy len for current rx packet */
504 /* first buffer address for current packet */
507 struct sk_buff *tail_skb;
510 } ____cacheline_internodealigned_in_smp;
512 enum hns3_flow_level_range {
519 #define HNS3_INT_GL_50K 0x0014
520 #define HNS3_INT_GL_20K 0x0032
521 #define HNS3_INT_GL_18K 0x0036
522 #define HNS3_INT_GL_8K 0x007C
524 #define HNS3_INT_GL_1US BIT(31)
526 #define HNS3_INT_RL_MAX 0x00EC
527 #define HNS3_INT_RL_ENABLE_MASK 0x40
529 #define HNS3_INT_QL_DEFAULT_CFG 0x20
531 struct hns3_enet_coalesce {
538 enum hns3_flow_level_range flow_level;
541 struct hns3_enet_ring_group {
542 /* array of pointers to rings */
543 struct hns3_enet_ring *ring;
544 u64 total_bytes; /* total bytes processed this group */
545 u64 total_packets; /* total packets processed this group */
547 struct hns3_enet_coalesce coal;
551 struct hns3_enet_tqp_vector {
552 struct hnae3_handle *handle;
553 u8 __iomem *mask_addr;
557 u16 idx; /* index in the TQP vector array per handle. */
559 struct napi_struct napi;
561 struct hns3_enet_ring_group rx_group;
562 struct hns3_enet_ring_group tx_group;
564 cpumask_t affinity_mask;
565 u16 num_tqps; /* total number of tqps in TQP vector */
566 struct irq_affinity_notify affinity_notify;
568 char name[HNAE3_INT_NAME_LEN];
571 } ____cacheline_internodealigned_in_smp;
573 struct hns3_nic_priv {
574 struct hnae3_handle *ae_handle;
575 struct net_device *netdev;
579 * the cb for nic to manage the ring buffer, the first half of the
580 * array is for tx_ring and vice versa for the second half
582 struct hns3_enet_ring *ring;
583 struct hns3_enet_tqp_vector *tqp_vector;
585 u8 max_non_tso_bd_num;
587 u64 tx_timeout_count;
591 enum dim_cq_period_mode tx_cqe_mode;
592 enum dim_cq_period_mode rx_cqe_mode;
593 struct hns3_enet_coalesce tx_coal;
594 struct hns3_enet_coalesce rx_coal;
608 struct gre_base_hdr *gre;
612 struct hns3_hw_error_info {
613 enum hnae3_hw_error_type type;
617 struct hns3_reset_type_map {
618 enum ethtool_reset_flags rst_flags;
619 enum hnae3_reset_type rst_type;
622 static inline int ring_space(struct hns3_enet_ring *ring)
624 /* This smp_load_acquire() pairs with smp_store_release() in
625 * hns3_nic_reclaim_one_desc called by hns3_clean_tx_ring.
627 int begin = smp_load_acquire(&ring->next_to_clean);
628 int end = READ_ONCE(ring->next_to_use);
630 return ((end >= begin) ? (ring->desc_num - end + begin) :
634 static inline u32 hns3_tqp_read_reg(struct hns3_enet_ring *ring, u32 reg)
636 return readl_relaxed(ring->tqp->io_base + reg);
639 static inline u32 hns3_read_reg(void __iomem *base, u32 reg)
641 return readl(base + reg);
644 static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
646 u8 __iomem *reg_addr = READ_ONCE(base);
648 writel(value, reg_addr + reg);
651 #define hns3_read_dev(a, reg) \
652 hns3_read_reg((a)->io_base, reg)
654 static inline bool hns3_nic_resetting(struct net_device *netdev)
656 struct hns3_nic_priv *priv = netdev_priv(netdev);
658 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
661 #define hns3_write_dev(a, reg, value) \
662 hns3_write_reg((a)->io_base, reg, value)
664 #define ring_to_dev(ring) ((ring)->dev)
666 #define ring_to_netdev(ring) ((ring)->tqp_vector->napi.dev)
668 #define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
669 DMA_TO_DEVICE : DMA_FROM_DEVICE)
671 #define hns3_buf_size(_ring) ((_ring)->buf_size)
673 #define hns3_ring_stats_update(ring, cnt) do { \
674 typeof(ring) (tmp) = (ring); \
675 u64_stats_update_begin(&(tmp)->syncp); \
676 ((tmp)->stats.cnt)++; \
677 u64_stats_update_end(&(tmp)->syncp); \
680 static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring)
682 #if (PAGE_SIZE < 8192)
683 if (ring->buf_size > (PAGE_SIZE / 2))
689 #define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring))
691 /* iterator for handling rings in ring group */
692 #define hns3_for_each_ring(pos, head) \
693 for (pos = (head).ring; (pos); pos = (pos)->next)
695 #define hns3_get_handle(ndev) \
696 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
698 #define hns3_get_ae_dev(handle) \
699 (pci_get_drvdata((handle)->pdev))
701 #define hns3_get_ops(handle) \
702 ((handle)->ae_algo->ops)
704 #define hns3_gl_usec_to_reg(int_gl) ((int_gl) >> 1)
705 #define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
707 #define hns3_rl_usec_to_reg(int_rl) ((int_rl) >> 2)
708 #define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
710 void hns3_ethtool_set_ops(struct net_device *netdev);
711 int hns3_set_channels(struct net_device *netdev,
712 struct ethtool_channels *ch);
714 void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget);
715 int hns3_init_all_ring(struct hns3_nic_priv *priv);
716 int hns3_nic_reset_all_ring(struct hnae3_handle *h);
717 void hns3_fini_ring(struct hns3_enet_ring *ring);
718 netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
719 bool hns3_is_phys_func(struct pci_dev *pdev);
720 int hns3_clean_rx_ring(
721 struct hns3_enet_ring *ring, int budget,
722 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *));
724 void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
726 void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
728 void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
730 void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
732 void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
735 void hns3_request_update_promisc_mode(struct hnae3_handle *handle);
736 int hns3_reset_notify(struct hnae3_handle *handle,
737 enum hnae3_reset_notify_type type);
739 #ifdef CONFIG_HNS3_DCB
740 void hns3_dcbnl_setup(struct hnae3_handle *handle);
742 static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
745 int hns3_dbg_init(struct hnae3_handle *handle);
746 void hns3_dbg_uninit(struct hnae3_handle *handle);
747 void hns3_dbg_register_debugfs(const char *debugfs_dir_name);
748 void hns3_dbg_unregister_debugfs(void);
749 void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size);
750 u16 hns3_get_max_available_channels(struct hnae3_handle *h);
751 void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
752 enum dim_cq_period_mode tx_mode,
753 enum dim_cq_period_mode rx_mode);
755 void hns3_external_lb_prepare(struct net_device *ndev, bool if_running);
756 void hns3_external_lb_restore(struct net_device *ndev, bool if_running);