2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include "hns_dsaf_mac.h"
11 #include "hns_dsaf_misc.h"
12 #include "hns_dsaf_ppe.h"
13 #include "hns_dsaf_reg.h"
16 HNS_OP_RESET_FUNC = 0x1,
17 HNS_OP_SERDES_LP_FUNC = 0x2,
18 HNS_OP_LED_SET_FUNC = 0x3,
19 HNS_OP_GET_PORT_TYPE_FUNC = 0x4,
20 HNS_OP_GET_SFP_STAT_FUNC = 0x5,
24 HNS_DSAF_RESET_FUNC = 0x1,
25 HNS_PPE_RESET_FUNC = 0x2,
26 HNS_XGE_CORE_RESET_FUNC = 0x3,
27 HNS_XGE_RESET_FUNC = 0x4,
28 HNS_GE_RESET_FUNC = 0x5,
29 HNS_DSAF_CHN_RESET_FUNC = 0x6,
30 HNS_ROCE_RESET_FUNC = 0x7,
33 const u8 hns_dsaf_acpi_dsm_uuid[] = {
34 0x1A, 0xAA, 0x85, 0x1A, 0x93, 0xE2, 0x5E, 0x41,
35 0x8E, 0x28, 0x8D, 0x69, 0x0A, 0x0F, 0x82, 0x0A
38 static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
40 if (dsaf_dev->sub_ctrl)
41 dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
43 dsaf_write_reg(dsaf_dev->sc_base, reg, val);
46 static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
50 if (dsaf_dev->sub_ctrl)
51 ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
53 ret = dsaf_read_reg(dsaf_dev->sc_base, reg);
58 static void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
65 pr_err("sfp_led_opt mac_dev is null!\n");
68 if (!mac_cb->cpld_ctrl) {
69 dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
74 if (speed == MAC_SPEED_10000)
77 value = mac_cb->cpld_led_value;
80 dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
81 dsaf_set_field(value, DSAF_LED_SPEED_M,
82 DSAF_LED_SPEED_S, speed_reg);
83 dsaf_set_bit(value, DSAF_LED_DATA_B, data);
85 if (value != mac_cb->cpld_led_value) {
86 dsaf_write_syscon(mac_cb->cpld_ctrl,
87 mac_cb->cpld_ctrl_reg, value);
88 mac_cb->cpld_led_value = value;
91 value = (mac_cb->cpld_led_value) & (0x1 << DSAF_LED_ANCHOR_B);
92 dsaf_write_syscon(mac_cb->cpld_ctrl,
93 mac_cb->cpld_ctrl_reg, value);
94 mac_cb->cpld_led_value = value;
98 static void cpld_led_reset(struct hns_mac_cb *mac_cb)
100 if (!mac_cb || !mac_cb->cpld_ctrl)
103 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
104 CPLD_LED_DEFAULT_VALUE);
105 mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
108 static int cpld_set_led_id(struct hns_mac_cb *mac_cb,
109 enum hnae_led_state status)
112 case HNAE_LED_ACTIVE:
113 mac_cb->cpld_led_value =
114 dsaf_read_syscon(mac_cb->cpld_ctrl,
115 mac_cb->cpld_ctrl_reg);
116 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
118 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
119 mac_cb->cpld_led_value);
121 case HNAE_LED_INACTIVE:
122 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
123 CPLD_LED_DEFAULT_VALUE);
124 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
125 mac_cb->cpld_led_value);
128 dev_err(mac_cb->dev, "invalid led state: %d!", status);
135 #define RESET_REQ_OR_DREQ 1
137 static void hns_dsaf_acpi_srst_by_port(struct dsaf_device *dsaf_dev, u8 op_type,
138 u32 port_type, u32 port, u32 val)
140 union acpi_object *obj;
141 union acpi_object obj_args[3], argv4;
143 obj_args[0].integer.type = ACPI_TYPE_INTEGER;
144 obj_args[0].integer.value = port_type;
145 obj_args[1].integer.type = ACPI_TYPE_INTEGER;
146 obj_args[1].integer.value = port;
147 obj_args[2].integer.type = ACPI_TYPE_INTEGER;
148 obj_args[2].integer.value = val;
150 argv4.type = ACPI_TYPE_PACKAGE;
151 argv4.package.count = 3;
152 argv4.package.elements = obj_args;
154 obj = acpi_evaluate_dsm(ACPI_HANDLE(dsaf_dev->dev),
155 hns_dsaf_acpi_dsm_uuid, 0, op_type, &argv4);
157 dev_warn(dsaf_dev->dev, "reset port_type%d port%d fail!",
165 static void hns_dsaf_rst(struct dsaf_device *dsaf_dev, bool dereset)
171 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
172 nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
174 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
175 nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
178 dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
179 dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
182 static void hns_dsaf_rst_acpi(struct dsaf_device *dsaf_dev, bool dereset)
184 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
189 static void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
195 if (port >= DSAF_XGE_NUM)
198 reg_val |= RESET_REQ_OR_DREQ;
199 reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;
202 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
204 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
206 dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
209 static void hns_dsaf_xge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
210 u32 port, bool dereset)
212 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
213 HNS_XGE_RESET_FUNC, port, dereset);
216 static void hns_dsaf_xge_core_srst_by_port(struct dsaf_device *dsaf_dev,
217 u32 port, bool dereset)
222 if (port >= DSAF_XGE_NUM)
225 reg_val |= XGMAC_TRX_CORE_SRST_M
226 << dsaf_dev->mac_cb[port]->port_rst_off;
229 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
231 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
233 dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
237 * hns_dsaf_srst_chns - reset dsaf channels
238 * @dsaf_dev: dsaf device struct pointer
239 * @msk: xbar channels mask value:
242 * bit12-17 for roce0-5
243 * bit18-19 for com/dfx
244 * @enable: false - request reset , true - drop reset
246 void hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32 msk, bool dereset)
251 reg_addr = DSAF_SUB_SC_DSAF_RESET_REQ_REG;
253 reg_addr = DSAF_SUB_SC_DSAF_RESET_DREQ_REG;
255 dsaf_write_sub(dsaf_dev, reg_addr, msk);
259 * hns_dsaf_srst_chns - reset dsaf channels
260 * @dsaf_dev: dsaf device struct pointer
261 * @msk: xbar channels mask value:
264 * bit12-17 for roce0-5
265 * bit18-19 for com/dfx
266 * @enable: false - request reset , true - drop reset
269 hns_dsaf_srst_chns_acpi(struct dsaf_device *dsaf_dev, u32 msk, bool dereset)
271 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
272 HNS_DSAF_CHN_RESET_FUNC,
276 void hns_dsaf_roce_srst(struct dsaf_device *dsaf_dev, bool dereset)
279 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_RESET_REQ_REG, 1);
281 dsaf_write_sub(dsaf_dev,
282 DSAF_SUB_SC_ROCEE_CLK_DIS_REG, 1);
283 dsaf_write_sub(dsaf_dev,
284 DSAF_SUB_SC_ROCEE_RESET_DREQ_REG, 1);
286 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_CLK_EN_REG, 1);
290 void hns_dsaf_roce_srst_acpi(struct dsaf_device *dsaf_dev, bool dereset)
292 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
293 HNS_ROCE_RESET_FUNC, 0, dereset);
297 hns_dsaf_xge_core_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
298 u32 port, bool dereset)
300 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
301 HNS_XGE_CORE_RESET_FUNC, port, dereset);
304 static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
311 if (port >= DSAF_GE_NUM)
314 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
315 reg_val_1 = 0x1 << port;
316 port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
317 /* there is difference between V1 and V2 in register.*/
318 reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ?
319 0x1041041 : 0x2082082;
320 reg_val_2 <<= port_rst_off;
323 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
326 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
329 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
332 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
337 reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 0x100 : 0x40;
339 reg_val_1 <<= dsaf_dev->reset_offset;
340 reg_val_2 <<= dsaf_dev->reset_offset;
343 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
346 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
349 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
352 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
358 static void hns_dsaf_ge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
359 u32 port, bool dereset)
361 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
362 HNS_GE_RESET_FUNC, port, dereset);
365 static void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
371 reg_val |= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off;
374 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
376 reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
378 dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
382 hns_ppe_srst_by_port_acpi(struct dsaf_device *dsaf_dev, u32 port, bool dereset)
384 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
385 HNS_PPE_RESET_FUNC, port, dereset);
388 static void hns_ppe_com_srst(struct dsaf_device *dsaf_dev, bool dereset)
393 if (!(dev_of_node(dsaf_dev->dev)))
396 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
397 reg_val = RESET_REQ_OR_DREQ;
399 reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
401 reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
404 reg_val = 0x100 << dsaf_dev->reset_offset;
407 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
409 reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
412 dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
416 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
417 * @mac_cb: mac control block
418 * retuen phy interface
420 static phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
424 bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
425 int mac_id = mac_cb->mac_id;
426 phy_interface_t phy_if;
429 if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev))
430 return PHY_INTERFACE_MODE_SGMII;
432 if (mac_id >= 0 && mac_id <= 3)
433 reg = HNS_MAC_HILINK4_REG;
435 reg = HNS_MAC_HILINK3_REG;
437 if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3)
438 reg = HNS_MAC_HILINK4V2_REG;
440 reg = HNS_MAC_HILINK3V2_REG;
443 mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
444 if (dsaf_get_bit(mode, mac_cb->port_mode_off))
445 phy_if = PHY_INTERFACE_MODE_XGMII;
447 phy_if = PHY_INTERFACE_MODE_SGMII;
452 static phy_interface_t hns_mac_get_phy_if_acpi(struct hns_mac_cb *mac_cb)
454 phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
455 union acpi_object *obj;
456 union acpi_object obj_args, argv4;
458 obj_args.integer.type = ACPI_TYPE_INTEGER;
459 obj_args.integer.value = mac_cb->mac_id;
461 argv4.type = ACPI_TYPE_PACKAGE,
462 argv4.package.count = 1,
463 argv4.package.elements = &obj_args,
465 obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev),
466 hns_dsaf_acpi_dsm_uuid, 0,
467 HNS_OP_GET_PORT_TYPE_FUNC, &argv4);
469 if (!obj || obj->type != ACPI_TYPE_INTEGER)
472 phy_if = obj->integer.value ?
473 PHY_INTERFACE_MODE_XGMII : PHY_INTERFACE_MODE_SGMII;
475 dev_dbg(mac_cb->dev, "mac_id=%d, phy_if=%d\n", mac_cb->mac_id, phy_if);
482 int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt)
484 if (!mac_cb->cpld_ctrl)
487 *sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
488 + MAC_SFP_PORT_OFFSET);
494 * hns_mac_config_sds_loopback - set loop back for serdes
495 * @mac_cb: mac control block
496 * retuen 0 == success
498 static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
500 const u8 lane_id[] = {
501 0, /* mac 0 -> lane 0 */
502 1, /* mac 1 -> lane 1 */
503 2, /* mac 2 -> lane 2 */
504 3, /* mac 3 -> lane 3 */
505 2, /* mac 4 -> lane 2 */
506 3, /* mac 5 -> lane 3 */
507 0, /* mac 6 -> lane 0 */
508 1 /* mac 7 -> lane 1 */
510 #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
511 u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
514 int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
516 if (!mac_cb->phy_dev) {
518 pr_info("please confirm sfp is present or not\n");
521 pr_info("no sfp in this eth\n");
524 if (mac_cb->serdes_ctrl) {
527 if (!AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver)) {
528 #define HILINK_ACCESS_SEL_CFG 0x40008
529 /* hilink4 & hilink3 use the same xge training and
530 * xge u adaptor. There is a hilink access sel cfg
531 * register to select which one to be configed
533 if ((!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) &&
534 (mac_cb->mac_id <= 3))
535 dsaf_write_syscon(mac_cb->serdes_ctrl,
536 HILINK_ACCESS_SEL_CFG, 0);
538 dsaf_write_syscon(mac_cb->serdes_ctrl,
539 HILINK_ACCESS_SEL_CFG, 3);
542 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
544 dsaf_set_field(origin, 1ull << 10, 10, en);
545 dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
547 u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
548 (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
549 dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en);
556 hns_mac_config_sds_loopback_acpi(struct hns_mac_cb *mac_cb, bool en)
558 union acpi_object *obj;
559 union acpi_object obj_args[3], argv4;
561 obj_args[0].integer.type = ACPI_TYPE_INTEGER;
562 obj_args[0].integer.value = mac_cb->mac_id;
563 obj_args[1].integer.type = ACPI_TYPE_INTEGER;
564 obj_args[1].integer.value = !!en;
566 argv4.type = ACPI_TYPE_PACKAGE;
567 argv4.package.count = 2;
568 argv4.package.elements = obj_args;
570 obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dsaf_dev->dev),
571 hns_dsaf_acpi_dsm_uuid, 0,
572 HNS_OP_SERDES_LP_FUNC, &argv4);
574 dev_warn(mac_cb->dsaf_dev->dev, "set port%d serdes lp fail!",
585 struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev)
587 struct dsaf_misc_op *misc_op;
589 misc_op = devm_kzalloc(dsaf_dev->dev, sizeof(*misc_op), GFP_KERNEL);
593 if (dev_of_node(dsaf_dev->dev)) {
594 misc_op->cpld_set_led = hns_cpld_set_led;
595 misc_op->cpld_reset_led = cpld_led_reset;
596 misc_op->cpld_set_led_id = cpld_set_led_id;
598 misc_op->dsaf_reset = hns_dsaf_rst;
599 misc_op->xge_srst = hns_dsaf_xge_srst_by_port;
600 misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port;
601 misc_op->ge_srst = hns_dsaf_ge_srst_by_port;
602 misc_op->ppe_srst = hns_ppe_srst_by_port;
603 misc_op->ppe_comm_srst = hns_ppe_com_srst;
604 misc_op->hns_dsaf_srst_chns = hns_dsaf_srst_chns;
605 misc_op->hns_dsaf_roce_srst = hns_dsaf_roce_srst;
607 misc_op->get_phy_if = hns_mac_get_phy_if;
608 misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
610 misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback;
611 } else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
612 misc_op->cpld_set_led = hns_cpld_set_led;
613 misc_op->cpld_reset_led = cpld_led_reset;
614 misc_op->cpld_set_led_id = cpld_set_led_id;
616 misc_op->dsaf_reset = hns_dsaf_rst_acpi;
617 misc_op->xge_srst = hns_dsaf_xge_srst_by_port_acpi;
618 misc_op->xge_core_srst = hns_dsaf_xge_core_srst_by_port_acpi;
619 misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi;
620 misc_op->ppe_srst = hns_ppe_srst_by_port_acpi;
621 misc_op->ppe_comm_srst = hns_ppe_com_srst;
622 misc_op->hns_dsaf_srst_chns = hns_dsaf_srst_chns_acpi;
623 misc_op->hns_dsaf_roce_srst = hns_dsaf_roce_srst_acpi;
625 misc_op->get_phy_if = hns_mac_get_phy_if_acpi;
626 misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
628 misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback_acpi;
630 devm_kfree(dsaf_dev->dev, (void *)misc_op);
634 return (void *)misc_op;
637 static int hns_dsaf_dev_match(struct device *dev, void *fwnode)
639 return dev->fwnode == fwnode;
643 platform_device *hns_dsaf_find_platform_device(struct fwnode_handle *fwnode)
647 dev = bus_find_device(&platform_bus_type, NULL,
648 fwnode, hns_dsaf_dev_match);
649 return dev ? to_platform_device(dev) : NULL;