drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/acpi.h>
  11 #include <linux/device.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/netdevice.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/vmalloc.h>
  24
  25 #include "hns_dsaf_mac.h"
  26 #include "hns_dsaf_main.h"
  27 #include "hns_dsaf_ppe.h"
  28 #include "hns_dsaf_rcb.h"
  29 #include "hns_dsaf_misc.h"
  30
  31 const char *g_dsaf_mode_match[DSAF_MODE_MAX] = {
  32         [DSAF_MODE_DISABLE_2PORT_64VM] = "2port-64vf",
  33         [DSAF_MODE_DISABLE_6PORT_0VM] = "6port-16rss",
  34         [DSAF_MODE_DISABLE_6PORT_16VM] = "6port-16vf",
  35         [DSAF_MODE_DISABLE_SP] = "single-port",
  36 };
  37
  38 static const struct acpi_device_id hns_dsaf_acpi_match[] = {
  39         { "HISI00B1", 0 },
  40         { "HISI00B2", 0 },
  41         { },
  42 };
  43 MODULE_DEVICE_TABLE(acpi, hns_dsaf_acpi_match);
  44
  45 int hns_dsaf_get_cfg(struct dsaf_device *dsaf_dev)
  46 {
  47         int ret, i;
  48         u32 desc_num;
  49         u32 buf_size;
  50         u32 reset_offset = 0;
  51         u32 res_idx = 0;
  52         const char *mode_str;
  53         struct regmap *syscon;
  54         struct resource *res;
  55         struct device_node *np = dsaf_dev->dev->of_node, *np_temp;
  56         struct platform_device *pdev = to_platform_device(dsaf_dev->dev);
  57
  58         if (dev_of_node(dsaf_dev->dev)) {
  59                 if (of_device_is_compatible(np, "hisilicon,hns-dsaf-v1"))
  60                         dsaf_dev->dsaf_ver = AE_VERSION_1;
  61                 else
  62                         dsaf_dev->dsaf_ver = AE_VERSION_2;
  63         } else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
  64                 if (acpi_dev_found(hns_dsaf_acpi_match[0].id))
  65                         dsaf_dev->dsaf_ver = AE_VERSION_1;
  66                 else if (acpi_dev_found(hns_dsaf_acpi_match[1].id))
  67                         dsaf_dev->dsaf_ver = AE_VERSION_2;
  68                 else
  69                         return -ENXIO;
  70         } else {
  71                 dev_err(dsaf_dev->dev, "cannot get cfg data from of or acpi\n");
  72                 return -ENXIO;
  73         }
  74
  75         ret = device_property_read_string(dsaf_dev->dev, "mode", &mode_str);
  76         if (ret) {
  77                 dev_err(dsaf_dev->dev, "get dsaf mode fail, ret=%d!\n", ret);
  78                 return ret;
  79         }
  80         for (i = 0; i < DSAF_MODE_MAX; i++) {
  81                 if (g_dsaf_mode_match[i] &&
  82                     !strcmp(mode_str, g_dsaf_mode_match[i]))
  83                         break;
  84         }
  85         if (i >= DSAF_MODE_MAX ||
  86             i == DSAF_MODE_INVALID || i == DSAF_MODE_ENABLE) {
  87                 dev_err(dsaf_dev->dev,
  88                         "%s prs mode str fail!\n", dsaf_dev->ae_dev.name);
  89                 return -EINVAL;
  90         }
  91         dsaf_dev->dsaf_mode = (enum dsaf_mode)i;
  92
  93         if (dsaf_dev->dsaf_mode > DSAF_MODE_ENABLE)
  94                 dsaf_dev->dsaf_en = HRD_DSAF_NO_DSAF_MODE;
  95         else
  96                 dsaf_dev->dsaf_en = HRD_DSAF_MODE;
  97
  98         if ((i == DSAF_MODE_ENABLE_16VM) ||
  99             (i == DSAF_MODE_DISABLE_2PORT_8VM) ||
 100             (i == DSAF_MODE_DISABLE_6PORT_2VM))
 101                 dsaf_dev->dsaf_tc_mode = HRD_DSAF_8TC_MODE;
 102         else
 103                 dsaf_dev->dsaf_tc_mode = HRD_DSAF_4TC_MODE;
 104
 105         if (dev_of_node(dsaf_dev->dev)) {
 106                 np_temp = of_parse_phandle(np, "subctrl-syscon", 0);
 107                 syscon = syscon_node_to_regmap(np_temp);
 108                 of_node_put(np_temp);
 109                 if (IS_ERR_OR_NULL(syscon)) {
 110                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 111                                                     res_idx++);
 112                         if (!res) {
 113                                 dev_err(dsaf_dev->dev, "subctrl info is needed!\n");
 114                                 return -ENOMEM;
 115                         }
 116
 117                         dsaf_dev->sc_base = devm_ioremap_resource(&pdev->dev,
 118                                                                   res);
 119                         if (IS_ERR(dsaf_dev->sc_base))
 120                                 return PTR_ERR(dsaf_dev->sc_base);
 121
 122                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 123                                                     res_idx++);
 124                         if (!res) {
 125                                 dev_err(dsaf_dev->dev, "serdes-ctrl info is needed!\n");
 126                                 return -ENOMEM;
 127                         }
 128
 129                         dsaf_dev->sds_base = devm_ioremap_resource(&pdev->dev,
 130                                                                    res);
 131                         if (IS_ERR(dsaf_dev->sds_base))
 132                                 return PTR_ERR(dsaf_dev->sds_base);
 133                 } else {
 134                         dsaf_dev->sub_ctrl = syscon;
 135                 }
 136         }
 137
 138         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ppe-base");
 139         if (!res) {
 140                 res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx++);
 141                 if (!res) {
 142                         dev_err(dsaf_dev->dev, "ppe-base info is needed!\n");
 143                         return -ENOMEM;
 144                 }
 145         }
 146         dsaf_dev->ppe_base = devm_ioremap_resource(&pdev->dev, res);
 147         if (IS_ERR(dsaf_dev->ppe_base))
 148                 return PTR_ERR(dsaf_dev->ppe_base);
 149         dsaf_dev->ppe_paddr = res->start;
 150
 151         if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
 152                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 153                                                    "dsaf-base");
 154                 if (!res) {
 155                         res = platform_get_resource(pdev, IORESOURCE_MEM,
 156                                                     res_idx);
 157                         if (!res) {
 158                                 dev_err(dsaf_dev->dev,
 159                                         "dsaf-base info is needed!\n");
 160                                 return -ENOMEM;
 161                         }
 162                 }
 163                 dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res);
 164                 if (IS_ERR(dsaf_dev->io_base))
 165                         return PTR_ERR(dsaf_dev->io_base);
 166         }
 167
 168         ret = device_property_read_u32(dsaf_dev->dev, "desc-num", &desc_num);
 169         if (ret < 0 || desc_num < HNS_DSAF_MIN_DESC_CNT ||
 170             desc_num > HNS_DSAF_MAX_DESC_CNT) {
 171                 dev_err(dsaf_dev->dev, "get desc-num(%d) fail, ret=%d!\n",
 172                         desc_num, ret);
 173                 return -EINVAL;
 174         }
 175         dsaf_dev->desc_num = desc_num;
 176
 177         ret = device_property_read_u32(dsaf_dev->dev, "reset-field-offset",
 178                                        &reset_offset);
 179         if (ret < 0) {
 180                 dev_dbg(dsaf_dev->dev,
 181                         "get reset-field-offset fail, ret=%d!\r\n", ret);
 182         }
 183         dsaf_dev->reset_offset = reset_offset;
 184
 185         ret = device_property_read_u32(dsaf_dev->dev, "buf-size", &buf_size);
 186         if (ret < 0) {
 187                 dev_err(dsaf_dev->dev,
 188                         "get buf-size fail, ret=%d!\r\n", ret);
 189                 return ret;
 190         }
 191         dsaf_dev->buf_size = buf_size;
 192
 193         dsaf_dev->buf_size_type = hns_rcb_buf_size2type(buf_size);
 194         if (dsaf_dev->buf_size_type < 0) {
 195                 dev_err(dsaf_dev->dev,
 196                         "buf_size(%d) is wrong!\n", buf_size);
 197                 return -EINVAL;
 198         }
 199
 200         dsaf_dev->misc_op = hns_misc_op_get(dsaf_dev);
 201         if (!dsaf_dev->misc_op)
 202                 return -ENOMEM;
 203
 204         if (!dma_set_mask_and_coherent(dsaf_dev->dev, DMA_BIT_MASK(64ULL)))
 205                 dev_dbg(dsaf_dev->dev, "set mask to 64bit\n");
 206         else
 207                 dev_err(dsaf_dev->dev, "set mask to 64bit fail!\n");
 208
 209         return 0;
 210 }
 211
 212 /**
 213  * hns_dsaf_sbm_link_sram_init_en - config dsaf_sbm_init_en
 214  * @dsaf_id: dsa fabric id
 215  */
 216 static void hns_dsaf_sbm_link_sram_init_en(struct dsaf_device *dsaf_dev)
 217 {
 218         dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG, DSAF_CFG_SBM_INIT_S, 1);
 219 }
 220
 221 /**
 222  * hns_dsaf_reg_cnt_clr_ce - config hns_dsaf_reg_cnt_clr_ce
 223  * @dsaf_id: dsa fabric id
 224  * @hns_dsaf_reg_cnt_clr_ce: config value
 225  */
 226 static void
 227 hns_dsaf_reg_cnt_clr_ce(struct dsaf_device *dsaf_dev, u32 reg_cnt_clr_ce)
 228 {
 229         dsaf_set_dev_bit(dsaf_dev, DSAF_DSA_REG_CNT_CLR_CE_REG,
 230                          DSAF_CNT_CLR_CE_S, reg_cnt_clr_ce);
 231 }
 232
 233 /**
 234  * hns_ppe_qid_cfg - config ppe qid
 235  * @dsaf_id: dsa fabric id
 236  * @pppe_qid_cfg: value array
 237  */
 238 static void
 239 hns_dsaf_ppe_qid_cfg(struct dsaf_device *dsaf_dev, u32 qid_cfg)
 240 {
 241         u32 i;
 242
 243         for (i = 0; i < DSAF_COMM_CHN; i++) {
 244                 dsaf_set_dev_field(dsaf_dev,
 245                                    DSAF_PPE_QID_CFG_0_REG + 0x0004 * i,
 246                                    DSAF_PPE_QID_CFG_M, DSAF_PPE_QID_CFG_S,
 247                                    qid_cfg);
 248         }
 249 }
 250
 251 static void hns_dsaf_mix_def_qid_cfg(struct dsaf_device *dsaf_dev)
 252 {
 253         u16 max_q_per_vf, max_vfn;
 254         u32 q_id, q_num_per_port;
 255         u32 i;
 256
 257         hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
 258         q_num_per_port = max_vfn * max_q_per_vf;
 259
 260         for (i = 0, q_id = 0; i < DSAF_SERVICE_NW_NUM; i++) {
 261                 dsaf_set_dev_field(dsaf_dev,
 262                                    DSAF_MIX_DEF_QID_0_REG + 0x0004 * i,
 263                                    0xff, 0, q_id);
 264                 q_id += q_num_per_port;
 265         }
 266 }
 267
 268 static void hns_dsaf_inner_qid_cfg(struct dsaf_device *dsaf_dev)
 269 {
 270         u16 max_q_per_vf, max_vfn;
 271         u32 q_id, q_num_per_port;
 272         u32 mac_id;
 273
 274         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
 275                 return;
 276
 277         hns_rcb_get_queue_mode(dsaf_dev->dsaf_mode, &max_vfn, &max_q_per_vf);
 278         q_num_per_port = max_vfn * max_q_per_vf;
 279
 280         for (mac_id = 0, q_id = 0; mac_id < DSAF_SERVICE_NW_NUM; mac_id++) {
 281                 dsaf_set_dev_field(dsaf_dev,
 282                                    DSAFV2_SERDES_LBK_0_REG + 4 * mac_id,
 283                                    DSAFV2_SERDES_LBK_QID_M,
 284                                    DSAFV2_SERDES_LBK_QID_S,
 285                                    q_id);
 286                 q_id += q_num_per_port;
 287         }
 288 }
 289
 290 /**
 291  * hns_dsaf_sw_port_type_cfg - cfg sw type
 292  * @dsaf_id: dsa fabric id
 293  * @psw_port_type: array
 294  */
 295 static void hns_dsaf_sw_port_type_cfg(struct dsaf_device *dsaf_dev,
 296                                       enum dsaf_sw_port_type port_type)
 297 {
 298         u32 i;
 299
 300         for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
 301                 dsaf_set_dev_field(dsaf_dev,
 302                                    DSAF_SW_PORT_TYPE_0_REG + 0x0004 * i,
 303                                    DSAF_SW_PORT_TYPE_M, DSAF_SW_PORT_TYPE_S,
 304                                    port_type);
 305         }
 306 }
 307
 308 /**
 309  * hns_dsaf_stp_port_type_cfg - cfg stp type
 310  * @dsaf_id: dsa fabric id
 311  * @pstp_port_type: array
 312  */
 313 static void hns_dsaf_stp_port_type_cfg(struct dsaf_device *dsaf_dev,
 314                                        enum dsaf_stp_port_type port_type)
 315 {
 316         u32 i;
 317
 318         for (i = 0; i < DSAF_COMM_CHN; i++) {
 319                 dsaf_set_dev_field(dsaf_dev,
 320                                    DSAF_STP_PORT_TYPE_0_REG + 0x0004 * i,
 321                                    DSAF_STP_PORT_TYPE_M, DSAF_STP_PORT_TYPE_S,
 322                                    port_type);
 323         }
 324 }
 325
 326 #define HNS_DSAF_SBM_NUM(dev) \
 327         (AE_IS_VER1((dev)->dsaf_ver) ? DSAF_SBM_NUM : DSAFV2_SBM_NUM)
 328 /**
 329  * hns_dsaf_sbm_cfg - config sbm
 330  * @dsaf_id: dsa fabric id
 331  */
 332 static void hns_dsaf_sbm_cfg(struct dsaf_device *dsaf_dev)
 333 {
 334         u32 o_sbm_cfg;
 335         u32 i;
 336
 337         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 338                 o_sbm_cfg = dsaf_read_dev(dsaf_dev,
 339                                           DSAF_SBM_CFG_REG_0_REG + 0x80 * i);
 340                 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_EN_S, 1);
 341                 dsaf_set_bit(o_sbm_cfg, DSAF_SBM_CFG_SHCUT_EN_S, 0);
 342                 dsaf_write_dev(dsaf_dev,
 343                                DSAF_SBM_CFG_REG_0_REG + 0x80 * i, o_sbm_cfg);
 344         }
 345 }
 346
 347 /**
 348  * hns_dsaf_sbm_cfg_mib_en - config sbm
 349  * @dsaf_id: dsa fabric id
 350  */
 351 static int hns_dsaf_sbm_cfg_mib_en(struct dsaf_device *dsaf_dev)
 352 {
 353         u32 sbm_cfg_mib_en;
 354         u32 i;
 355         u32 reg;
 356         u32 read_cnt;
 357
 358         /* validate configure by setting SBM_CFG_MIB_EN bit from 0 to 1. */
 359         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 360                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 361                 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 0);
 362         }
 363
 364         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 365                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 366                 dsaf_set_dev_bit(dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S, 1);
 367         }
 368
 369         /* waitint for all sbm enable finished */
 370         for (i = 0; i < HNS_DSAF_SBM_NUM(dsaf_dev); i++) {
 371                 read_cnt = 0;
 372                 reg = DSAF_SBM_CFG_REG_0_REG + 0x80 * i;
 373                 do {
 374                         udelay(1);
 375                         sbm_cfg_mib_en = dsaf_get_dev_bit(
 376                                         dsaf_dev, reg, DSAF_SBM_CFG_MIB_EN_S);
 377                         read_cnt++;
 378                 } while (sbm_cfg_mib_en == 0 &&
 379                         read_cnt < DSAF_CFG_READ_CNT);
 380
 381                 if (sbm_cfg_mib_en == 0) {
 382                         dev_err(dsaf_dev->dev,
 383                                 "sbm_cfg_mib_en fail,%s,sbm_num=%d\n",
 384                                 dsaf_dev->ae_dev.name, i);
 385                         return -ENODEV;
 386                 }
 387         }
 388
 389         return 0;
 390 }
 391
 392 /**
 393  * hns_dsaf_sbm_bp_wl_cfg - config sbm
 394  * @dsaf_id: dsa fabric id
 395  */
 396 static void hns_dsaf_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
 397 {
 398         u32 o_sbm_bp_cfg;
 399         u32 reg;
 400         u32 i;
 401
 402         /* XGE */
 403         for (i = 0; i < DSAF_XGE_NUM; i++) {
 404                 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
 405                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 406                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M,
 407                                DSAF_SBM_CFG0_COM_MAX_BUF_NUM_S, 512);
 408                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M,
 409                                DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
 410                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M,
 411                                DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
 412                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 413
 414                 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
 415                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 416                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M,
 417                                DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
 418                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M,
 419                                DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
 420                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 421
 422                 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
 423                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 424                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 425                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 104);
 426                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 427                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 128);
 428                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 429
 430                 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
 431                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 432                 dsaf_set_field(o_sbm_bp_cfg,
 433                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 434                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 110);
 435                 dsaf_set_field(o_sbm_bp_cfg,
 436                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 437                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 160);
 438                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 439
 440                 /* for no enable pfc mode */
 441                 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
 442                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 443                 dsaf_set_field(o_sbm_bp_cfg,
 444                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 445                                DSAF_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 128);
 446                 dsaf_set_field(o_sbm_bp_cfg,
 447                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 448                                DSAF_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 192);
 449                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 450         }
 451
 452         /* PPE */
 453         for (i = 0; i < DSAF_COMM_CHN; i++) {
 454                 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
 455                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 456                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 457                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 10);
 458                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 459                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 12);
 460                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 461         }
 462
 463         /* RoCEE */
 464         for (i = 0; i < DSAF_COMM_CHN; i++) {
 465                 reg = DSAF_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
 466                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 467                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
 468                                DSAF_SBM_CFG2_SET_BUF_NUM_S, 2);
 469                 dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
 470                                DSAF_SBM_CFG2_RESET_BUF_NUM_S, 4);
 471                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 472         }
 473 }
 474
 475 static void hns_dsafv2_sbm_bp_wl_cfg(struct dsaf_device *dsaf_dev)
 476 {
 477         u32 o_sbm_bp_cfg;
 478         u32 reg;
 479         u32 i;
 480
 481         /* XGE */
 482         for (i = 0; i < DSAFV2_SBM_XGE_CHN; i++) {
 483                 reg = DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + 0x80 * i;
 484                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 485                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M,
 486                                DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_S, 256);
 487                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M,
 488                                DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_S, 0);
 489                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M,
 490                                DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_S, 0);
 491                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 492
 493                 reg = DSAF_SBM_BP_CFG_1_REG_0_REG + 0x80 * i;
 494                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 495                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M,
 496                                DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_S, 0);
 497                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M,
 498                                DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_S, 0);
 499                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 500
 501                 reg = DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + 0x80 * i;
 502                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 503                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M,
 504                                DSAFV2_SBM_CFG2_SET_BUF_NUM_S, 104);
 505                 dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M,
 506                                DSAFV2_SBM_CFG2_RESET_BUF_NUM_S, 128);
 507                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 508
 509                 reg = DSAF_SBM_BP_CFG_3_REG_0_REG + 0x80 * i;
 510                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 511                 dsaf_set_field(o_sbm_bp_cfg,
 512                                DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_M,
 513                                DSAFV2_SBM_CFG3_SET_BUF_NUM_NO_PFC_S, 55);
 514                 dsaf_set_field(o_sbm_bp_cfg,
 515                                DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_M,
 516                                DSAFV2_SBM_CFG3_RESET_BUF_NUM_NO_PFC_S, 110);
 517                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 518
 519                 /* for no enable pfc mode */
 520                 reg = DSAF_SBM_BP_CFG_4_REG_0_REG + 0x80 * i;
 521                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 522                 dsaf_set_field(o_sbm_bp_cfg,
 523                                DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_M,
 524                                DSAFV2_SBM_CFG4_SET_BUF_NUM_NO_PFC_S, 128);
 525                 dsaf_set_field(o_sbm_bp_cfg,
 526                                DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_M,
 527                                DSAFV2_SBM_CFG4_RESET_BUF_NUM_NO_PFC_S, 192);
 528                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 529         }
 530
 531         /* PPE */
 532         for (i = 0; i < DSAFV2_SBM_PPE_CHN; i++) {
 533                 reg = DSAF_SBM_BP_CFG_2_PPE_REG_0_REG + 0x80 * i;
 534                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 535                 dsaf_set_field(o_sbm_bp_cfg,
 536                                DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_M,
 537                                DSAFV2_SBM_CFG2_PPE_SET_BUF_NUM_S, 2);
 538                 dsaf_set_field(o_sbm_bp_cfg,
 539                                DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_M,
 540                                DSAFV2_SBM_CFG2_PPE_RESET_BUF_NUM_S, 3);
 541                 dsaf_set_field(o_sbm_bp_cfg,
 542                                DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_M,
 543                                DSAFV2_SBM_CFG2_PPE_CFG_USEFUL_NUM_S, 52);
 544                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 545         }
 546
 547         /* RoCEE */
 548         for (i = 0; i < DASFV2_ROCEE_CRD_NUM; i++) {
 549                 reg = DSAFV2_SBM_BP_CFG_2_ROCEE_REG_0_REG + 0x80 * i;
 550                 o_sbm_bp_cfg = dsaf_read_dev(dsaf_dev, reg);
 551                 dsaf_set_field(o_sbm_bp_cfg,
 552                                DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_M,
 553                                DSAFV2_SBM_CFG2_ROCEE_SET_BUF_NUM_S, 2);
 554                 dsaf_set_field(o_sbm_bp_cfg,
 555                                DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_M,
 556                                DSAFV2_SBM_CFG2_ROCEE_RESET_BUF_NUM_S, 4);
 557                 dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
 558         }
 559 }
 560
 561 /**
 562  * hns_dsaf_voq_bp_all_thrd_cfg -  voq
 563  * @dsaf_id: dsa fabric id
 564  */
 565 static void hns_dsaf_voq_bp_all_thrd_cfg(struct dsaf_device *dsaf_dev)
 566 {
 567         u32 voq_bp_all_thrd;
 568         u32 i;
 569
 570         for (i = 0; i < DSAF_VOQ_NUM; i++) {
 571                 voq_bp_all_thrd = dsaf_read_dev(
 572                         dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i);
 573                 if (i < DSAF_XGE_NUM) {
 574                         dsaf_set_field(voq_bp_all_thrd,
 575                                        DSAF_VOQ_BP_ALL_DOWNTHRD_M,
 576                                        DSAF_VOQ_BP_ALL_DOWNTHRD_S, 930);
 577                         dsaf_set_field(voq_bp_all_thrd,
 578                                        DSAF_VOQ_BP_ALL_UPTHRD_M,
 579                                        DSAF_VOQ_BP_ALL_UPTHRD_S, 950);
 580                 } else {
 581                         dsaf_set_field(voq_bp_all_thrd,
 582                                        DSAF_VOQ_BP_ALL_DOWNTHRD_M,
 583                                        DSAF_VOQ_BP_ALL_DOWNTHRD_S, 220);
 584                         dsaf_set_field(voq_bp_all_thrd,
 585                                        DSAF_VOQ_BP_ALL_UPTHRD_M,
 586                                        DSAF_VOQ_BP_ALL_UPTHRD_S, 230);
 587                 }
 588                 dsaf_write_dev(
 589                         dsaf_dev, DSAF_VOQ_BP_ALL_THRD_0_REG + 0x40 * i,
 590                         voq_bp_all_thrd);
 591         }
 592 }
 593
 594 static void hns_dsaf_tbl_tcam_match_cfg(
 595         struct dsaf_device *dsaf_dev,
 596         struct dsaf_tbl_tcam_data *ptbl_tcam_data)
 597 {
 598         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_L_REG,
 599                        ptbl_tcam_data->tbl_tcam_data_low);
 600         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_H_REG,
 601                        ptbl_tcam_data->tbl_tcam_data_high);
 602 }
 603
 604 /**
 605  * hns_dsaf_tbl_tcam_data_cfg - tbl
 606  * @dsaf_id: dsa fabric id
 607  * @ptbl_tcam_data: addr
 608  */
 609 static void hns_dsaf_tbl_tcam_data_cfg(
 610         struct dsaf_device *dsaf_dev,
 611         struct dsaf_tbl_tcam_data *ptbl_tcam_data)
 612 {
 613         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG,
 614                        ptbl_tcam_data->tbl_tcam_data_low);
 615         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG,
 616                        ptbl_tcam_data->tbl_tcam_data_high);
 617 }
 618
 619 /**
 620  * dsaf_tbl_tcam_mcast_cfg - tbl
 621  * @dsaf_id: dsa fabric id
 622  * @ptbl_tcam_mcast: addr
 623  */
 624 static void hns_dsaf_tbl_tcam_mcast_cfg(
 625         struct dsaf_device *dsaf_dev,
 626         struct dsaf_tbl_tcam_mcast_cfg *mcast)
 627 {
 628         u32 mcast_cfg4;
 629
 630         mcast_cfg4 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
 631         dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S,
 632                      mcast->tbl_mcast_item_vld);
 633         dsaf_set_bit(mcast_cfg4, DSAF_TBL_MCAST_CFG4_OLD_EN_S,
 634                      mcast->tbl_mcast_old_en);
 635         dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M,
 636                        DSAF_TBL_MCAST_CFG4_VM128_112_S,
 637                        mcast->tbl_mcast_port_msk[4]);
 638         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4);
 639
 640         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG,
 641                        mcast->tbl_mcast_port_msk[3]);
 642
 643         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG,
 644                        mcast->tbl_mcast_port_msk[2]);
 645
 646         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG,
 647                        mcast->tbl_mcast_port_msk[1]);
 648
 649         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG,
 650                        mcast->tbl_mcast_port_msk[0]);
 651 }
 652
 653 /**
 654  * hns_dsaf_tbl_tcam_ucast_cfg - tbl
 655  * @dsaf_id: dsa fabric id
 656  * @ptbl_tcam_ucast: addr
 657  */
 658 static void hns_dsaf_tbl_tcam_ucast_cfg(
 659         struct dsaf_device *dsaf_dev,
 660         struct dsaf_tbl_tcam_ucast_cfg *tbl_tcam_ucast)
 661 {
 662         u32 ucast_cfg1;
 663
 664         ucast_cfg1 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
 665         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S,
 666                      tbl_tcam_ucast->tbl_ucast_mac_discard);
 667         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_ITEM_VLD_S,
 668                      tbl_tcam_ucast->tbl_ucast_item_vld);
 669         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OLD_EN_S,
 670                      tbl_tcam_ucast->tbl_ucast_old_en);
 671         dsaf_set_bit(ucast_cfg1, DSAF_TBL_UCAST_CFG1_DVC_S,
 672                      tbl_tcam_ucast->tbl_ucast_dvc);
 673         dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
 674                        DSAF_TBL_UCAST_CFG1_OUT_PORT_S,
 675                        tbl_tcam_ucast->tbl_ucast_out_port);
 676         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1);
 677 }
 678
 679 /**
 680  * hns_dsaf_tbl_line_cfg - tbl
 681  * @dsaf_id: dsa fabric id
 682  * @ptbl_lin: addr
 683  */
 684 static void hns_dsaf_tbl_line_cfg(struct dsaf_device *dsaf_dev,
 685                                   struct dsaf_tbl_line_cfg *tbl_lin)
 686 {
 687         u32 tbl_line;
 688
 689         tbl_line = dsaf_read_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG);
 690         dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_MAC_DISCARD_S,
 691                      tbl_lin->tbl_line_mac_discard);
 692         dsaf_set_bit(tbl_line, DSAF_TBL_LINE_CFG_DVC_S,
 693                      tbl_lin->tbl_line_dvc);
 694         dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M,
 695                        DSAF_TBL_LINE_CFG_OUT_PORT_S,
 696                        tbl_lin->tbl_line_out_port);
 697         dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line);
 698 }
 699
 700 /**
 701  * hns_dsaf_tbl_tcam_mcast_pul - tbl
 702  * @dsaf_id: dsa fabric id
 703  */
 704 static void hns_dsaf_tbl_tcam_mcast_pul(struct dsaf_device *dsaf_dev)
 705 {
 706         u32 o_tbl_pul;
 707
 708         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 709         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
 710         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 711         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
 712         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 713 }
 714
 715 /**
 716  * hns_dsaf_tbl_line_pul - tbl
 717  * @dsaf_id: dsa fabric id
 718  */
 719 static void hns_dsaf_tbl_line_pul(struct dsaf_device *dsaf_dev)
 720 {
 721         u32 tbl_pul;
 722
 723         tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 724         dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 1);
 725         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
 726         dsaf_set_bit(tbl_pul, DSAF_TBL_PUL_LINE_VLD_S, 0);
 727         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
 728 }
 729
 730 /**
 731  * hns_dsaf_tbl_tcam_data_mcast_pul - tbl
 732  * @dsaf_id: dsa fabric id
 733  */
 734 static void hns_dsaf_tbl_tcam_data_mcast_pul(
 735         struct dsaf_device *dsaf_dev)
 736 {
 737         u32 o_tbl_pul;
 738
 739         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 740         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
 741         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 1);
 742         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 743         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
 744         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_MCAST_VLD_S, 0);
 745         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 746 }
 747
 748 /**
 749  * hns_dsaf_tbl_tcam_data_ucast_pul - tbl
 750  * @dsaf_id: dsa fabric id
 751  */
 752 static void hns_dsaf_tbl_tcam_data_ucast_pul(
 753         struct dsaf_device *dsaf_dev)
 754 {
 755         u32 o_tbl_pul;
 756
 757         o_tbl_pul = dsaf_read_dev(dsaf_dev, DSAF_TBL_PUL_0_REG);
 758         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 1);
 759         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 1);
 760         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 761         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_TCAM_DATA_VLD_S, 0);
 762         dsaf_set_bit(o_tbl_pul, DSAF_TBL_PUL_UCAST_VLD_S, 0);
 763         dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
 764 }
 765
 766 void hns_dsaf_set_promisc_mode(struct dsaf_device *dsaf_dev, u32 en)
 767 {
 768         if (AE_IS_VER1(dsaf_dev->dsaf_ver) && !HNS_DSAF_IS_DEBUG(dsaf_dev))
 769                 dsaf_set_dev_bit(dsaf_dev, DSAF_CFG_0_REG,
 770                                  DSAF_CFG_MIX_MODE_S, !!en);
 771 }
 772
 773 /**
 774  * hns_dsaf_tbl_stat_en - tbl
 775  * @dsaf_id: dsa fabric id
 776  * @ptbl_stat_en: addr
 777  */
 778 static void hns_dsaf_tbl_stat_en(struct dsaf_device *dsaf_dev)
 779 {
 780         u32 o_tbl_ctrl;
 781
 782         o_tbl_ctrl = dsaf_read_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG);
 783         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_LINE_LKUP_NUM_EN_S, 1);
 784         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_UC_LKUP_NUM_EN_S, 1);
 785         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_MC_LKUP_NUM_EN_S, 1);
 786         dsaf_set_bit(o_tbl_ctrl, DSAF_TBL_DFX_BC_LKUP_NUM_EN_S, 1);
 787         dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl);
 788 }
 789
 790 /**
 791  * hns_dsaf_rocee_bp_en - rocee back press enable
 792  * @dsaf_id: dsa fabric id
 793  */
 794 static void hns_dsaf_rocee_bp_en(struct dsaf_device *dsaf_dev)
 795 {
 796         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
 797                 dsaf_set_dev_bit(dsaf_dev, DSAF_XGE_CTRL_SIG_CFG_0_REG,
 798                                  DSAF_FC_XGE_TX_PAUSE_S, 1);
 799 }
 800
 801 /* set msk for dsaf exception irq*/
 802 static void hns_dsaf_int_xge_msk_set(struct dsaf_device *dsaf_dev,
 803                                      u32 chnn_num, u32 mask_set)
 804 {
 805         dsaf_write_dev(dsaf_dev,
 806                        DSAF_XGE_INT_MSK_0_REG + 0x4 * chnn_num, mask_set);
 807 }
 808
 809 static void hns_dsaf_int_ppe_msk_set(struct dsaf_device *dsaf_dev,
 810                                      u32 chnn_num, u32 msk_set)
 811 {
 812         dsaf_write_dev(dsaf_dev,
 813                        DSAF_PPE_INT_MSK_0_REG + 0x4 * chnn_num, msk_set);
 814 }
 815
 816 static void hns_dsaf_int_rocee_msk_set(struct dsaf_device *dsaf_dev,
 817                                        u32 chnn, u32 msk_set)
 818 {
 819         dsaf_write_dev(dsaf_dev,
 820                        DSAF_ROCEE_INT_MSK_0_REG + 0x4 * chnn, msk_set);
 821 }
 822
 823 static void
 824 hns_dsaf_int_tbl_msk_set(struct dsaf_device *dsaf_dev, u32 msk_set)
 825 {
 826         dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set);
 827 }
 828
 829 /* clr dsaf exception irq*/
 830 static void hns_dsaf_int_xge_src_clr(struct dsaf_device *dsaf_dev,
 831                                      u32 chnn_num, u32 int_src)
 832 {
 833         dsaf_write_dev(dsaf_dev,
 834                        DSAF_XGE_INT_SRC_0_REG + 0x4 * chnn_num, int_src);
 835 }
 836
 837 static void hns_dsaf_int_ppe_src_clr(struct dsaf_device *dsaf_dev,
 838                                      u32 chnn, u32 int_src)
 839 {
 840         dsaf_write_dev(dsaf_dev,
 841                        DSAF_PPE_INT_SRC_0_REG + 0x4 * chnn, int_src);
 842 }
 843
 844 static void hns_dsaf_int_rocee_src_clr(struct dsaf_device *dsaf_dev,
 845                                        u32 chnn, u32 int_src)
 846 {
 847         dsaf_write_dev(dsaf_dev,
 848                        DSAF_ROCEE_INT_SRC_0_REG + 0x4 * chnn, int_src);
 849 }
 850
 851 static void hns_dsaf_int_tbl_src_clr(struct dsaf_device *dsaf_dev,
 852                                      u32 int_src)
 853 {
 854         dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src);
 855 }
 856
 857 /**
 858  * hns_dsaf_single_line_tbl_cfg - INT
 859  * @dsaf_id: dsa fabric id
 860  * @address:
 861  * @ptbl_line:
 862  */
 863 static void hns_dsaf_single_line_tbl_cfg(
 864         struct dsaf_device *dsaf_dev,
 865         u32 address, struct dsaf_tbl_line_cfg *ptbl_line)
 866 {
 867         spin_lock_bh(&dsaf_dev->tcam_lock);
 868
 869         /*Write Addr*/
 870         hns_dsaf_tbl_line_addr_cfg(dsaf_dev, address);
 871
 872         /*Write Line*/
 873         hns_dsaf_tbl_line_cfg(dsaf_dev, ptbl_line);
 874
 875         /*Write Plus*/
 876         hns_dsaf_tbl_line_pul(dsaf_dev);
 877
 878         spin_unlock_bh(&dsaf_dev->tcam_lock);
 879 }
 880
 881 /**
 882  * hns_dsaf_tcam_uc_cfg - INT
 883  * @dsaf_id: dsa fabric id
 884  * @address,
 885  * @ptbl_tcam_data,
 886  */
 887 static void hns_dsaf_tcam_uc_cfg(
 888         struct dsaf_device *dsaf_dev, u32 address,
 889         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 890         struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
 891 {
 892         spin_lock_bh(&dsaf_dev->tcam_lock);
 893
 894         /*Write Addr*/
 895         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 896         /*Write Tcam Data*/
 897         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
 898         /*Write Tcam Ucast*/
 899         hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, ptbl_tcam_ucast);
 900         /*Write Plus*/
 901         hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
 902
 903         spin_unlock_bh(&dsaf_dev->tcam_lock);
 904 }
 905
 906 /**
 907  * hns_dsaf_tcam_mc_cfg - cfg the tcam for mc
 908  * @dsaf_dev: dsa fabric device struct pointer
 909  * @address: tcam index
 910  * @ptbl_tcam_data: tcam data struct pointer
 911  * @ptbl_tcam_mcast: tcam mask struct pointer, it must be null for HNSv1
 912  */
 913 static void hns_dsaf_tcam_mc_cfg(
 914         struct dsaf_device *dsaf_dev, u32 address,
 915         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
 916         struct dsaf_tbl_tcam_data *ptbl_tcam_mask,
 917         struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
 918 {
 919         spin_lock_bh(&dsaf_dev->tcam_lock);
 920
 921         /*Write Addr*/
 922         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 923         /*Write Tcam Data*/
 924         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, ptbl_tcam_data);
 925         /*Write Tcam Mcast*/
 926         hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, ptbl_tcam_mcast);
 927         /* Write Match Data */
 928         if (ptbl_tcam_mask)
 929                 hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, ptbl_tcam_mask);
 930
 931         /* Write Puls */
 932         hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
 933
 934         spin_unlock_bh(&dsaf_dev->tcam_lock);
 935 }
 936
 937 /**
 938  * hns_dsaf_tcam_uc_cfg_vague - INT
 939  * @dsaf_dev: dsa fabric device struct pointer
 940  * @address,
 941  * @ptbl_tcam_data,
 942  */
 943 static void hns_dsaf_tcam_uc_cfg_vague(struct dsaf_device *dsaf_dev,
 944                                        u32 address,
 945                                        struct dsaf_tbl_tcam_data *tcam_data,
 946                                        struct dsaf_tbl_tcam_data *tcam_mask,
 947                                        struct dsaf_tbl_tcam_ucast_cfg *tcam_uc)
 948 {
 949         spin_lock_bh(&dsaf_dev->tcam_lock);
 950         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 951         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, tcam_data);
 952         hns_dsaf_tbl_tcam_ucast_cfg(dsaf_dev, tcam_uc);
 953         hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
 954         hns_dsaf_tbl_tcam_data_ucast_pul(dsaf_dev);
 955
 956         /*Restore Match Data*/
 957         tcam_mask->tbl_tcam_data_high = 0xffffffff;
 958         tcam_mask->tbl_tcam_data_low = 0xffffffff;
 959         hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
 960
 961         spin_unlock_bh(&dsaf_dev->tcam_lock);
 962 }
 963
 964 /**
 965  * hns_dsaf_tcam_mc_cfg_vague - INT
 966  * @dsaf_dev: dsa fabric device struct pointer
 967  * @address,
 968  * @ptbl_tcam_data,
 969  * @ptbl_tcam_mask
 970  * @ptbl_tcam_mcast
 971  */
 972 static void hns_dsaf_tcam_mc_cfg_vague(struct dsaf_device *dsaf_dev,
 973                                        u32 address,
 974                                        struct dsaf_tbl_tcam_data *tcam_data,
 975                                        struct dsaf_tbl_tcam_data *tcam_mask,
 976                                        struct dsaf_tbl_tcam_mcast_cfg *tcam_mc)
 977 {
 978         spin_lock_bh(&dsaf_dev->tcam_lock);
 979         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
 980         hns_dsaf_tbl_tcam_data_cfg(dsaf_dev, tcam_data);
 981         hns_dsaf_tbl_tcam_mcast_cfg(dsaf_dev, tcam_mc);
 982         hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
 983         hns_dsaf_tbl_tcam_data_mcast_pul(dsaf_dev);
 984
 985         /*Restore Match Data*/
 986         tcam_mask->tbl_tcam_data_high = 0xffffffff;
 987         tcam_mask->tbl_tcam_data_low = 0xffffffff;
 988         hns_dsaf_tbl_tcam_match_cfg(dsaf_dev, tcam_mask);
 989
 990         spin_unlock_bh(&dsaf_dev->tcam_lock);
 991 }
 992
 993 /**
 994  * hns_dsaf_tcam_mc_invld - INT
 995  * @dsaf_id: dsa fabric id
 996  * @address
 997  */
 998 static void hns_dsaf_tcam_mc_invld(struct dsaf_device *dsaf_dev, u32 address)
 999 {
1000         spin_lock_bh(&dsaf_dev->tcam_lock);
1001
1002         /*Write Addr*/
1003         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1004
1005         /*write tcam mcast*/
1006         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0);
1007         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0);
1008         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0);
1009         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0);
1010         dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0);
1011
1012         /*Write Plus*/
1013         hns_dsaf_tbl_tcam_mcast_pul(dsaf_dev);
1014
1015         spin_unlock_bh(&dsaf_dev->tcam_lock);
1016 }
1017
1018 void hns_dsaf_tcam_addr_get(struct dsaf_drv_tbl_tcam_key *mac_key, u8 *addr)
1019 {
1020         addr[0] = mac_key->high.bits.mac_0;
1021         addr[1] = mac_key->high.bits.mac_1;
1022         addr[2] = mac_key->high.bits.mac_2;
1023         addr[3] = mac_key->high.bits.mac_3;
1024         addr[4] = mac_key->low.bits.mac_4;
1025         addr[5] = mac_key->low.bits.mac_5;
1026 }
1027
1028 /**
1029  * hns_dsaf_tcam_uc_get - INT
1030  * @dsaf_id: dsa fabric id
1031  * @address
1032  * @ptbl_tcam_data
1033  * @ptbl_tcam_ucast
1034  */
1035 static void hns_dsaf_tcam_uc_get(
1036         struct dsaf_device *dsaf_dev, u32 address,
1037         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
1038         struct dsaf_tbl_tcam_ucast_cfg *ptbl_tcam_ucast)
1039 {
1040         u32 tcam_read_data0;
1041         u32 tcam_read_data4;
1042
1043         spin_lock_bh(&dsaf_dev->tcam_lock);
1044
1045         /*Write Addr*/
1046         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1047
1048         /*read tcam item puls*/
1049         hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
1050
1051         /*read tcam data*/
1052         ptbl_tcam_data->tbl_tcam_data_high
1053                 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
1054         ptbl_tcam_data->tbl_tcam_data_low
1055                 = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1056
1057         /*read tcam mcast*/
1058         tcam_read_data0 = dsaf_read_dev(dsaf_dev,
1059                                         DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1060         tcam_read_data4 = dsaf_read_dev(dsaf_dev,
1061                                         DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1062
1063         ptbl_tcam_ucast->tbl_ucast_item_vld
1064                 = dsaf_get_bit(tcam_read_data4,
1065                                DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1066         ptbl_tcam_ucast->tbl_ucast_old_en
1067                 = dsaf_get_bit(tcam_read_data4, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1068         ptbl_tcam_ucast->tbl_ucast_mac_discard
1069                 = dsaf_get_bit(tcam_read_data0,
1070                                DSAF_TBL_UCAST_CFG1_MAC_DISCARD_S);
1071         ptbl_tcam_ucast->tbl_ucast_out_port
1072                 = dsaf_get_field(tcam_read_data0,
1073                                  DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
1074                                  DSAF_TBL_UCAST_CFG1_OUT_PORT_S);
1075         ptbl_tcam_ucast->tbl_ucast_dvc
1076                 = dsaf_get_bit(tcam_read_data0, DSAF_TBL_UCAST_CFG1_DVC_S);
1077
1078         spin_unlock_bh(&dsaf_dev->tcam_lock);
1079 }
1080
1081 /**
1082  * hns_dsaf_tcam_mc_get - INT
1083  * @dsaf_id: dsa fabric id
1084  * @address
1085  * @ptbl_tcam_data
1086  * @ptbl_tcam_ucast
1087  */
1088 static void hns_dsaf_tcam_mc_get(
1089         struct dsaf_device *dsaf_dev, u32 address,
1090         struct dsaf_tbl_tcam_data *ptbl_tcam_data,
1091         struct dsaf_tbl_tcam_mcast_cfg *ptbl_tcam_mcast)
1092 {
1093         u32 data_tmp;
1094
1095         spin_lock_bh(&dsaf_dev->tcam_lock);
1096
1097         /*Write Addr*/
1098         hns_dsaf_tbl_tcam_addr_cfg(dsaf_dev, address);
1099
1100         /*read tcam item puls*/
1101         hns_dsaf_tbl_tcam_load_pul(dsaf_dev);
1102
1103         /*read tcam data*/
1104         ptbl_tcam_data->tbl_tcam_data_high =
1105                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
1106         ptbl_tcam_data->tbl_tcam_data_low =
1107                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
1108
1109         /*read tcam mcast*/
1110         ptbl_tcam_mcast->tbl_mcast_port_msk[0] =
1111                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
1112         ptbl_tcam_mcast->tbl_mcast_port_msk[1] =
1113                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
1114         ptbl_tcam_mcast->tbl_mcast_port_msk[2] =
1115                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
1116         ptbl_tcam_mcast->tbl_mcast_port_msk[3] =
1117                 dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
1118
1119         data_tmp = dsaf_read_dev(dsaf_dev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
1120         ptbl_tcam_mcast->tbl_mcast_item_vld =
1121                 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_ITEM_VLD_S);
1122         ptbl_tcam_mcast->tbl_mcast_old_en =
1123                 dsaf_get_bit(data_tmp, DSAF_TBL_MCAST_CFG4_OLD_EN_S);
1124         ptbl_tcam_mcast->tbl_mcast_port_msk[4] =
1125                 dsaf_get_field(data_tmp, DSAF_TBL_MCAST_CFG4_VM128_112_M,
1126                                DSAF_TBL_MCAST_CFG4_VM128_112_S);
1127
1128         spin_unlock_bh(&dsaf_dev->tcam_lock);
1129 }
1130
1131 /**
1132  * hns_dsaf_tbl_line_init - INT
1133  * @dsaf_id: dsa fabric id
1134  */
1135 static void hns_dsaf_tbl_line_init(struct dsaf_device *dsaf_dev)
1136 {
1137         u32 i;
1138         /* defaultly set all lineal mac table entry resulting discard */
1139         struct dsaf_tbl_line_cfg tbl_line[] = {{1, 0, 0} };
1140
1141         for (i = 0; i < DSAF_LINE_SUM; i++)
1142                 hns_dsaf_single_line_tbl_cfg(dsaf_dev, i, tbl_line);
1143 }
1144
1145 /**
1146  * hns_dsaf_tbl_tcam_init - INT
1147  * @dsaf_id: dsa fabric id
1148  */
1149 static void hns_dsaf_tbl_tcam_init(struct dsaf_device *dsaf_dev)
1150 {
1151         u32 i;
1152         struct dsaf_tbl_tcam_data tcam_data[] = {{0, 0} };
1153         struct dsaf_tbl_tcam_ucast_cfg tcam_ucast[] = {{0, 0, 0, 0, 0} };
1154
1155         /*tcam tbl*/
1156         for (i = 0; i < DSAF_TCAM_SUM; i++)
1157                 hns_dsaf_tcam_uc_cfg(dsaf_dev, i, tcam_data, tcam_ucast);
1158 }
1159
1160 /**
1161  * hns_dsaf_pfc_en_cfg - dsaf pfc pause cfg
1162  * @mac_cb: mac contrl block
1163  */
1164 static void hns_dsaf_pfc_en_cfg(struct dsaf_device *dsaf_dev,
1165                                 int mac_id, int tc_en)
1166 {
1167         dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en);
1168 }
1169
1170 static void hns_dsaf_set_pfc_pause(struct dsaf_device *dsaf_dev,
1171                                    int mac_id, int tx_en, int rx_en)
1172 {
1173         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1174                 if (!tx_en || !rx_en)
1175                         dev_err(dsaf_dev->dev, "dsaf v1 can not close pfc!\n");
1176
1177                 return;
1178         }
1179
1180         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1181                          DSAF_PFC_PAUSE_RX_EN_B, !!rx_en);
1182         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1183                          DSAF_PFC_PAUSE_TX_EN_B, !!tx_en);
1184 }
1185
1186 int hns_dsaf_set_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1187                                  u32 en)
1188 {
1189         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1190                 if (!en) {
1191                         dev_err(dsaf_dev->dev, "dsafv1 can't close rx_pause!\n");
1192                         return -EINVAL;
1193                 }
1194         }
1195
1196         dsaf_set_dev_bit(dsaf_dev, DSAF_PAUSE_CFG_REG + mac_id * 4,
1197                          DSAF_MAC_PAUSE_RX_EN_B, !!en);
1198
1199         return 0;
1200 }
1201
1202 void hns_dsaf_get_rx_mac_pause_en(struct dsaf_device *dsaf_dev, int mac_id,
1203                                   u32 *en)
1204 {
1205         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1206                 *en = 1;
1207         else
1208                 *en = dsaf_get_dev_bit(dsaf_dev,
1209                                        DSAF_PAUSE_CFG_REG + mac_id * 4,
1210                                        DSAF_MAC_PAUSE_RX_EN_B);
1211 }
1212
1213 /**
1214  * hns_dsaf_tbl_tcam_init - INT
1215  * @dsaf_id: dsa fabric id
1216  * @dsaf_mode
1217  */
1218 static void hns_dsaf_comm_init(struct dsaf_device *dsaf_dev)
1219 {
1220         u32 i;
1221         u32 o_dsaf_cfg;
1222         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
1223
1224         o_dsaf_cfg = dsaf_read_dev(dsaf_dev, DSAF_CFG_0_REG);
1225         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_EN_S, dsaf_dev->dsaf_en);
1226         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_TC_MODE_S, dsaf_dev->dsaf_tc_mode);
1227         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_CRC_EN_S, 0);
1228         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_MIX_MODE_S, 0);
1229         dsaf_set_bit(o_dsaf_cfg, DSAF_CFG_LOCA_ADDR_EN_S, 0);
1230         dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg);
1231
1232         hns_dsaf_reg_cnt_clr_ce(dsaf_dev, 1);
1233         hns_dsaf_stp_port_type_cfg(dsaf_dev, DSAF_STP_PORT_TYPE_FORWARD);
1234
1235         /* set 22 queue per tx ppe engine, only used in switch mode */
1236         hns_dsaf_ppe_qid_cfg(dsaf_dev, DSAF_DEFAUTL_QUEUE_NUM_PER_PPE);
1237
1238         /* set promisc def queue id */
1239         hns_dsaf_mix_def_qid_cfg(dsaf_dev);
1240
1241         /* set inner loopback queue id */
1242         hns_dsaf_inner_qid_cfg(dsaf_dev);
1243
1244         /* in non switch mode, set all port to access mode */
1245         hns_dsaf_sw_port_type_cfg(dsaf_dev, DSAF_SW_PORT_TYPE_NON_VLAN);
1246
1247         /*set dsaf pfc  to 0 for parseing rx pause*/
1248         for (i = 0; i < DSAF_COMM_CHN; i++) {
1249                 hns_dsaf_pfc_en_cfg(dsaf_dev, i, 0);
1250                 hns_dsaf_set_pfc_pause(dsaf_dev, i, is_ver1, is_ver1);
1251         }
1252
1253         /*msk and  clr exception irqs */
1254         for (i = 0; i < DSAF_COMM_CHN; i++) {
1255                 hns_dsaf_int_xge_src_clr(dsaf_dev, i, 0xfffffffful);
1256                 hns_dsaf_int_ppe_src_clr(dsaf_dev, i, 0xfffffffful);
1257                 hns_dsaf_int_rocee_src_clr(dsaf_dev, i, 0xfffffffful);
1258
1259                 hns_dsaf_int_xge_msk_set(dsaf_dev, i, 0xfffffffful);
1260                 hns_dsaf_int_ppe_msk_set(dsaf_dev, i, 0xfffffffful);
1261                 hns_dsaf_int_rocee_msk_set(dsaf_dev, i, 0xfffffffful);
1262         }
1263         hns_dsaf_int_tbl_src_clr(dsaf_dev, 0xfffffffful);
1264         hns_dsaf_int_tbl_msk_set(dsaf_dev, 0xfffffffful);
1265 }
1266
1267 /**
1268  * hns_dsaf_inode_init - INT
1269  * @dsaf_id: dsa fabric id
1270  */
1271 static void hns_dsaf_inode_init(struct dsaf_device *dsaf_dev)
1272 {
1273         u32 reg;
1274         u32 tc_cfg;
1275         u32 i;
1276
1277         if (dsaf_dev->dsaf_tc_mode == HRD_DSAF_4TC_MODE)
1278                 tc_cfg = HNS_DSAF_I4TC_CFG;
1279         else
1280                 tc_cfg = HNS_DSAF_I8TC_CFG;
1281
1282         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1283                 for (i = 0; i < DSAF_INODE_NUM; i++) {
1284                         reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1285                         dsaf_set_dev_field(dsaf_dev, reg,
1286                                            DSAF_INODE_IN_PORT_NUM_M,
1287                                            DSAF_INODE_IN_PORT_NUM_S,
1288                                            i % DSAF_XGE_NUM);
1289                 }
1290         } else {
1291                 for (i = 0; i < DSAF_PORT_TYPE_NUM; i++) {
1292                         reg = DSAF_INODE_IN_PORT_NUM_0_REG + 0x80 * i;
1293                         dsaf_set_dev_field(dsaf_dev, reg,
1294                                            DSAF_INODE_IN_PORT_NUM_M,
1295                                            DSAF_INODE_IN_PORT_NUM_S, 0);
1296                         dsaf_set_dev_field(dsaf_dev, reg,
1297                                            DSAFV2_INODE_IN_PORT1_NUM_M,
1298                                            DSAFV2_INODE_IN_PORT1_NUM_S, 1);
1299                         dsaf_set_dev_field(dsaf_dev, reg,
1300                                            DSAFV2_INODE_IN_PORT2_NUM_M,
1301                                            DSAFV2_INODE_IN_PORT2_NUM_S, 2);
1302                         dsaf_set_dev_field(dsaf_dev, reg,
1303                                            DSAFV2_INODE_IN_PORT3_NUM_M,
1304                                            DSAFV2_INODE_IN_PORT3_NUM_S, 3);
1305                         dsaf_set_dev_field(dsaf_dev, reg,
1306                                            DSAFV2_INODE_IN_PORT4_NUM_M,
1307                                            DSAFV2_INODE_IN_PORT4_NUM_S, 4);
1308                         dsaf_set_dev_field(dsaf_dev, reg,
1309                                            DSAFV2_INODE_IN_PORT5_NUM_M,
1310                                            DSAFV2_INODE_IN_PORT5_NUM_S, 5);
1311                 }
1312         }
1313         for (i = 0; i < DSAF_INODE_NUM; i++) {
1314                 reg = DSAF_INODE_PRI_TC_CFG_0_REG + 0x80 * i;
1315                 dsaf_write_dev(dsaf_dev, reg, tc_cfg);
1316         }
1317 }
1318
1319 /**
1320  * hns_dsaf_sbm_init - INT
1321  * @dsaf_id: dsa fabric id
1322  */
1323 static int hns_dsaf_sbm_init(struct dsaf_device *dsaf_dev)
1324 {
1325         u32 flag;
1326         u32 finish_msk;
1327         u32 cnt = 0;
1328         int ret;
1329
1330         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1331                 hns_dsaf_sbm_bp_wl_cfg(dsaf_dev);
1332                 finish_msk = DSAF_SRAM_INIT_OVER_M;
1333         } else {
1334                 hns_dsafv2_sbm_bp_wl_cfg(dsaf_dev);
1335                 finish_msk = DSAFV2_SRAM_INIT_OVER_M;
1336         }
1337
1338         /* enable sbm chanel, disable sbm chanel shcut function*/
1339         hns_dsaf_sbm_cfg(dsaf_dev);
1340
1341         /* enable sbm mib */
1342         ret = hns_dsaf_sbm_cfg_mib_en(dsaf_dev);
1343         if (ret) {
1344                 dev_err(dsaf_dev->dev,
1345                         "hns_dsaf_sbm_cfg_mib_en fail,%s, ret=%d\n",
1346                         dsaf_dev->ae_dev.name, ret);
1347                 return ret;
1348         }
1349
1350         /* enable sbm initial link sram */
1351         hns_dsaf_sbm_link_sram_init_en(dsaf_dev);
1352
1353         do {
1354                 usleep_range(200, 210);/*udelay(200);*/
1355                 flag = dsaf_get_dev_field(dsaf_dev, DSAF_SRAM_INIT_OVER_0_REG,
1356                                           finish_msk, DSAF_SRAM_INIT_OVER_S);
1357                 cnt++;
1358         } while (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S) &&
1359                  cnt < DSAF_CFG_READ_CNT);
1360
1361         if (flag != (finish_msk >> DSAF_SRAM_INIT_OVER_S)) {
1362                 dev_err(dsaf_dev->dev,
1363                         "hns_dsaf_sbm_init fail %s, flag=%d, cnt=%d\n",
1364                         dsaf_dev->ae_dev.name, flag, cnt);
1365                 return -ENODEV;
1366         }
1367
1368         hns_dsaf_rocee_bp_en(dsaf_dev);
1369
1370         return 0;
1371 }
1372
1373 /**
1374  * hns_dsaf_tbl_init - INT
1375  * @dsaf_id: dsa fabric id
1376  */
1377 static void hns_dsaf_tbl_init(struct dsaf_device *dsaf_dev)
1378 {
1379         hns_dsaf_tbl_stat_en(dsaf_dev);
1380
1381         hns_dsaf_tbl_tcam_init(dsaf_dev);
1382         hns_dsaf_tbl_line_init(dsaf_dev);
1383 }
1384
1385 /**
1386  * hns_dsaf_voq_init - INT
1387  * @dsaf_id: dsa fabric id
1388  */
1389 static void hns_dsaf_voq_init(struct dsaf_device *dsaf_dev)
1390 {
1391         hns_dsaf_voq_bp_all_thrd_cfg(dsaf_dev);
1392 }
1393
1394 /**
1395  * hns_dsaf_init_hw - init dsa fabric hardware
1396  * @dsaf_dev: dsa fabric device struct pointer
1397  */
1398 static int hns_dsaf_init_hw(struct dsaf_device *dsaf_dev)
1399 {
1400         int ret;
1401
1402         dev_dbg(dsaf_dev->dev,
1403                 "hns_dsaf_init_hw begin %s !\n", dsaf_dev->ae_dev.name);
1404
1405         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1406         mdelay(10);
1407         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 1);
1408
1409         hns_dsaf_comm_init(dsaf_dev);
1410
1411         /*init XBAR_INODE*/
1412         hns_dsaf_inode_init(dsaf_dev);
1413
1414         /*init SBM*/
1415         ret = hns_dsaf_sbm_init(dsaf_dev);
1416         if (ret)
1417                 return ret;
1418
1419         /*init TBL*/
1420         hns_dsaf_tbl_init(dsaf_dev);
1421
1422         /*init VOQ*/
1423         hns_dsaf_voq_init(dsaf_dev);
1424
1425         return 0;
1426 }
1427
1428 /**
1429  * hns_dsaf_remove_hw - uninit dsa fabric hardware
1430  * @dsaf_dev: dsa fabric device struct pointer
1431  */
1432 static void hns_dsaf_remove_hw(struct dsaf_device *dsaf_dev)
1433 {
1434         /*reset*/
1435         dsaf_dev->misc_op->dsaf_reset(dsaf_dev, 0);
1436 }
1437
1438 /**
1439  * hns_dsaf_init - init dsa fabric
1440  * @dsaf_dev: dsa fabric device struct pointer
1441  * retuen 0 - success , negative --fail
1442  */
1443 static int hns_dsaf_init(struct dsaf_device *dsaf_dev)
1444 {
1445         struct dsaf_drv_priv *priv =
1446             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1447         u32 i;
1448         int ret;
1449
1450         if (HNS_DSAF_IS_DEBUG(dsaf_dev))
1451                 return 0;
1452
1453         if (AE_IS_VER1(dsaf_dev->dsaf_ver))
1454                 dsaf_dev->tcam_max_num = DSAF_TCAM_SUM;
1455         else
1456                 dsaf_dev->tcam_max_num =
1457                         DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM;
1458
1459         spin_lock_init(&dsaf_dev->tcam_lock);
1460         ret = hns_dsaf_init_hw(dsaf_dev);
1461         if (ret)
1462                 return ret;
1463
1464         /* malloc mem for tcam mac key(vlan+mac) */
1465         priv->soft_mac_tbl = vzalloc(sizeof(*priv->soft_mac_tbl)
1466                   * DSAF_TCAM_SUM);
1467         if (!priv->soft_mac_tbl) {
1468                 ret = -ENOMEM;
1469                 goto remove_hw;
1470         }
1471
1472         /*all entry invall */
1473         for (i = 0; i < DSAF_TCAM_SUM; i++)
1474                 (priv->soft_mac_tbl + i)->index = DSAF_INVALID_ENTRY_IDX;
1475
1476         return 0;
1477
1478 remove_hw:
1479         hns_dsaf_remove_hw(dsaf_dev);
1480         return ret;
1481 }
1482
1483 /**
1484  * hns_dsaf_free - free dsa fabric
1485  * @dsaf_dev: dsa fabric device struct pointer
1486  */
1487 static void hns_dsaf_free(struct dsaf_device *dsaf_dev)
1488 {
1489         struct dsaf_drv_priv *priv =
1490             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1491
1492         hns_dsaf_remove_hw(dsaf_dev);
1493
1494         /* free all mac mem */
1495         vfree(priv->soft_mac_tbl);
1496         priv->soft_mac_tbl = NULL;
1497 }
1498
1499 /**
1500  * hns_dsaf_find_soft_mac_entry - find dsa fabric soft entry
1501  * @dsaf_dev: dsa fabric device struct pointer
1502  * @mac_key: mac entry struct pointer
1503  */
1504 static u16 hns_dsaf_find_soft_mac_entry(
1505         struct dsaf_device *dsaf_dev,
1506         struct dsaf_drv_tbl_tcam_key *mac_key)
1507 {
1508         struct dsaf_drv_priv *priv =
1509             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1510         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1511         u32 i;
1512
1513         soft_mac_entry = priv->soft_mac_tbl;
1514         for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
1515                 /* invall tab entry */
1516                 if ((soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX) &&
1517                     (soft_mac_entry->tcam_key.high.val == mac_key->high.val) &&
1518                     (soft_mac_entry->tcam_key.low.val == mac_key->low.val))
1519                         /* return find result --soft index */
1520                         return soft_mac_entry->index;
1521
1522                 soft_mac_entry++;
1523         }
1524         return DSAF_INVALID_ENTRY_IDX;
1525 }
1526
1527 /**
1528  * hns_dsaf_find_empty_mac_entry - search dsa fabric soft empty-entry
1529  * @dsaf_dev: dsa fabric device struct pointer
1530  */
1531 static u16 hns_dsaf_find_empty_mac_entry(struct dsaf_device *dsaf_dev)
1532 {
1533         struct dsaf_drv_priv *priv =
1534             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1535         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1536         u32 i;
1537
1538         soft_mac_entry = priv->soft_mac_tbl;
1539         for (i = 0; i < dsaf_dev->tcam_max_num; i++) {
1540                 /* inv all entry */
1541                 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
1542                         /* return find result --soft index */
1543                         return i;
1544
1545                 soft_mac_entry++;
1546         }
1547         return DSAF_INVALID_ENTRY_IDX;
1548 }
1549
1550 /**
1551  * hns_dsaf_find_empty_mac_entry_reverse
1552  * search dsa fabric soft empty-entry from the end
1553  * @dsaf_dev: dsa fabric device struct pointer
1554  */
1555 static u16 hns_dsaf_find_empty_mac_entry_reverse(struct dsaf_device *dsaf_dev)
1556 {
1557         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1558         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
1559         int i;
1560
1561         soft_mac_entry = priv->soft_mac_tbl + (DSAF_TCAM_SUM - 1);
1562         for (i = (DSAF_TCAM_SUM - 1); i > 0; i--) {
1563                 /* search all entry from end to start.*/
1564                 if (soft_mac_entry->index == DSAF_INVALID_ENTRY_IDX)
1565                         return i;
1566                 soft_mac_entry--;
1567         }
1568         return DSAF_INVALID_ENTRY_IDX;
1569 }
1570
1571 /**
1572  * hns_dsaf_set_mac_key - set mac key
1573  * @dsaf_dev: dsa fabric device struct pointer
1574  * @mac_key: tcam key pointer
1575  * @vlan_id: vlan id
1576  * @in_port_num: input port num
1577  * @addr: mac addr
1578  */
1579 static void hns_dsaf_set_mac_key(
1580         struct dsaf_device *dsaf_dev,
1581         struct dsaf_drv_tbl_tcam_key *mac_key, u16 vlan_id, u8 in_port_num,
1582         u8 *addr)
1583 {
1584         u8 port;
1585
1586         if (dsaf_dev->dsaf_mode <= DSAF_MODE_ENABLE)
1587                 /*DSAF mode : in port id fixed 0*/
1588                 port = 0;
1589         else
1590                 /*non-dsaf mode*/
1591                 port = in_port_num;
1592
1593         mac_key->high.bits.mac_0 = addr[0];
1594         mac_key->high.bits.mac_1 = addr[1];
1595         mac_key->high.bits.mac_2 = addr[2];
1596         mac_key->high.bits.mac_3 = addr[3];
1597         mac_key->low.bits.mac_4 = addr[4];
1598         mac_key->low.bits.mac_5 = addr[5];
1599         mac_key->low.bits.port_vlan = 0;
1600         dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_VLAN_M,
1601                        DSAF_TBL_TCAM_KEY_VLAN_S, vlan_id);
1602         dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_PORT_M,
1603                        DSAF_TBL_TCAM_KEY_PORT_S, port);
1604
1605         mac_key->low.bits.port_vlan = le16_to_cpu(mac_key->low.bits.port_vlan);
1606 }
1607
1608 /**
1609  * hns_dsaf_set_mac_uc_entry - set mac uc-entry
1610  * @dsaf_dev: dsa fabric device struct pointer
1611  * @mac_entry: uc-mac entry
1612  */
1613 int hns_dsaf_set_mac_uc_entry(
1614         struct dsaf_device *dsaf_dev,
1615         struct dsaf_drv_mac_single_dest_entry *mac_entry)
1616 {
1617         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1618         struct dsaf_drv_tbl_tcam_key mac_key;
1619         struct dsaf_tbl_tcam_ucast_cfg mac_data;
1620         struct dsaf_drv_priv *priv =
1621             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1622         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1623         struct dsaf_tbl_tcam_data tcam_data;
1624
1625         /* mac addr check */
1626         if (MAC_IS_ALL_ZEROS(mac_entry->addr) ||
1627             MAC_IS_BROADCAST(mac_entry->addr) ||
1628             MAC_IS_MULTICAST(mac_entry->addr)) {
1629                 dev_err(dsaf_dev->dev, "set_uc %s Mac %pM err!\n",
1630                         dsaf_dev->ae_dev.name, mac_entry->addr);
1631                 return -EINVAL;
1632         }
1633
1634         /* config key */
1635         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1636                              mac_entry->in_port_num, mac_entry->addr);
1637
1638         /* entry ie exist? */
1639         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1640         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1641                 /*if has not inv entry,find a empty entry */
1642                 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1643                 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1644                         /* has not empty,return error */
1645                         dev_err(dsaf_dev->dev,
1646                                 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1647                                 dsaf_dev->ae_dev.name,
1648                                 mac_key.high.val, mac_key.low.val);
1649                         return -EINVAL;
1650                 }
1651         }
1652
1653         dev_dbg(dsaf_dev->dev,
1654                 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1655                 dsaf_dev->ae_dev.name, mac_key.high.val,
1656                 mac_key.low.val, entry_index);
1657
1658         /* config hardware entry */
1659         mac_data.tbl_ucast_item_vld = 1;
1660         mac_data.tbl_ucast_mac_discard = 0;
1661         mac_data.tbl_ucast_old_en = 0;
1662         /* default config dvc to 0 */
1663         mac_data.tbl_ucast_dvc = 0;
1664         mac_data.tbl_ucast_out_port = mac_entry->port_num;
1665         tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val);
1666         tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val);
1667
1668         hns_dsaf_tcam_uc_cfg(dsaf_dev, entry_index, &tcam_data, &mac_data);
1669
1670         /* config software entry */
1671         soft_mac_entry += entry_index;
1672         soft_mac_entry->index = entry_index;
1673         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1674         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1675
1676         return 0;
1677 }
1678
1679 int hns_dsaf_rm_mac_addr(
1680         struct dsaf_device *dsaf_dev,
1681         struct dsaf_drv_mac_single_dest_entry *mac_entry)
1682 {
1683         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1684         struct dsaf_tbl_tcam_ucast_cfg mac_data;
1685         struct dsaf_drv_tbl_tcam_key mac_key;
1686
1687         /* mac addr check */
1688         if (!is_valid_ether_addr(mac_entry->addr)) {
1689                 dev_err(dsaf_dev->dev, "rm_uc_addr %s Mac %pM err!\n",
1690                         dsaf_dev->ae_dev.name, mac_entry->addr);
1691                 return -EINVAL;
1692         }
1693
1694         /* config key */
1695         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1696                              mac_entry->in_port_num, mac_entry->addr);
1697
1698         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1699         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1700                 /* can not find the tcam entry, return 0 */
1701                 dev_info(dsaf_dev->dev,
1702                          "rm_uc_addr no tcam, %s Mac key(%#x:%#x)\n",
1703                          dsaf_dev->ae_dev.name,
1704                          mac_key.high.val, mac_key.low.val);
1705                 return 0;
1706         }
1707
1708         dev_dbg(dsaf_dev->dev,
1709                 "rm_uc_addr, %s Mac key(%#x:%#x) entry_index%d\n",
1710                 dsaf_dev->ae_dev.name, mac_key.high.val,
1711                 mac_key.low.val, entry_index);
1712
1713         hns_dsaf_tcam_uc_get(
1714                         dsaf_dev, entry_index,
1715                         (struct dsaf_tbl_tcam_data *)&mac_key,
1716                         &mac_data);
1717
1718         /* unicast entry not used locally should not clear */
1719         if (mac_entry->port_num != mac_data.tbl_ucast_out_port)
1720                 return -EFAULT;
1721
1722         return hns_dsaf_del_mac_entry(dsaf_dev,
1723                                       mac_entry->in_vlan_id,
1724                                       mac_entry->in_port_num,
1725                                       mac_entry->addr);
1726 }
1727
1728 static void hns_dsaf_mc_mask_bit_clear(char *dst, const char *src)
1729 {
1730         u16 *a = (u16 *)dst;
1731         const u16 *b = (const u16 *)src;
1732
1733         a[0] &= b[0];
1734         a[1] &= b[1];
1735         a[2] &= b[2];
1736 }
1737
1738 /**
1739  * hns_dsaf_add_mac_mc_port - add mac mc-port
1740  * @dsaf_dev: dsa fabric device struct pointer
1741  * @mac_entry: mc-mac entry
1742  */
1743 int hns_dsaf_add_mac_mc_port(struct dsaf_device *dsaf_dev,
1744                              struct dsaf_drv_mac_single_dest_entry *mac_entry)
1745 {
1746         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1747         struct dsaf_drv_tbl_tcam_key mac_key;
1748         struct dsaf_drv_tbl_tcam_key mask_key;
1749         struct dsaf_tbl_tcam_data *pmask_key = NULL;
1750         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1751         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1752         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1753         struct dsaf_drv_tbl_tcam_key tmp_mac_key;
1754         struct dsaf_tbl_tcam_data tcam_data;
1755         u8 mc_addr[ETH_ALEN];
1756         u8 *mc_mask;
1757         int mskid;
1758
1759         /*chechk mac addr */
1760         if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1761                 dev_err(dsaf_dev->dev, "set_entry failed,addr %pM!\n",
1762                         mac_entry->addr);
1763                 return -EINVAL;
1764         }
1765
1766         ether_addr_copy(mc_addr, mac_entry->addr);
1767         mc_mask = dsaf_dev->mac_cb[mac_entry->in_port_num]->mc_mask;
1768         if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1769                 /* prepare for key data setting */
1770                 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1771
1772                 /* config key mask */
1773                 hns_dsaf_set_mac_key(dsaf_dev, &mask_key,
1774                                      0x0,
1775                                      0xff,
1776                                      mc_mask);
1777
1778                 mask_key.high.val = le32_to_cpu(mask_key.high.val);
1779                 mask_key.low.val = le32_to_cpu(mask_key.low.val);
1780
1781                 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1782         }
1783
1784         /*config key */
1785         hns_dsaf_set_mac_key(
1786                 dsaf_dev, &mac_key, mac_entry->in_vlan_id,
1787                 mac_entry->in_port_num, mc_addr);
1788
1789         memset(&mac_data, 0, sizeof(struct dsaf_tbl_tcam_mcast_cfg));
1790
1791         /* check if the tcam is exist */
1792         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1793         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1794                 /*if hasnot , find a empty*/
1795                 entry_index = hns_dsaf_find_empty_mac_entry(dsaf_dev);
1796                 if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1797                         /*if hasnot empty, error*/
1798                         dev_err(dsaf_dev->dev,
1799                                 "set_uc_entry failed, %s Mac key(%#x:%#x)\n",
1800                                 dsaf_dev->ae_dev.name, mac_key.high.val,
1801                                 mac_key.low.val);
1802                         return -EINVAL;
1803                 }
1804         } else {
1805                 /* if exist, add in */
1806                 hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data,
1807                                      &mac_data);
1808
1809                 tmp_mac_key.high.val =
1810                         le32_to_cpu(tcam_data.tbl_tcam_data_high);
1811                 tmp_mac_key.low.val = le32_to_cpu(tcam_data.tbl_tcam_data_low);
1812         }
1813
1814         /* config hardware entry */
1815         if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1816                 mskid = mac_entry->port_num;
1817         } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1818                 mskid = mac_entry->port_num -
1819                         DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1820         } else {
1821                 dev_err(dsaf_dev->dev,
1822                         "%s,pnum(%d)error,key(%#x:%#x)\n",
1823                         dsaf_dev->ae_dev.name, mac_entry->port_num,
1824                         mac_key.high.val, mac_key.low.val);
1825                 return -EINVAL;
1826         }
1827         dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 1);
1828         mac_data.tbl_mcast_old_en = 0;
1829         mac_data.tbl_mcast_item_vld = 1;
1830
1831         dev_dbg(dsaf_dev->dev,
1832                 "set_uc_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1833                 dsaf_dev->ae_dev.name, mac_key.high.val,
1834                 mac_key.low.val, entry_index);
1835
1836         tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val);
1837         tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val);
1838
1839         /* config mc entry with mask */
1840         hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index, &tcam_data,
1841                              pmask_key, &mac_data);
1842
1843         /*config software entry */
1844         soft_mac_entry += entry_index;
1845         soft_mac_entry->index = entry_index;
1846         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
1847         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
1848
1849         return 0;
1850 }
1851
1852 /**
1853  * hns_dsaf_del_mac_entry - del mac mc-port
1854  * @dsaf_dev: dsa fabric device struct pointer
1855  * @vlan_id: vlian id
1856  * @in_port_num: input port num
1857  * @addr : mac addr
1858  */
1859 int hns_dsaf_del_mac_entry(struct dsaf_device *dsaf_dev, u16 vlan_id,
1860                            u8 in_port_num, u8 *addr)
1861 {
1862         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1863         struct dsaf_drv_tbl_tcam_key mac_key;
1864         struct dsaf_drv_priv *priv =
1865             (struct dsaf_drv_priv *)hns_dsaf_dev_priv(dsaf_dev);
1866         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1867
1868         /*check mac addr */
1869         if (MAC_IS_ALL_ZEROS(addr) || MAC_IS_BROADCAST(addr)) {
1870                 dev_err(dsaf_dev->dev, "del_entry failed,addr %pM!\n",
1871                         addr);
1872                 return -EINVAL;
1873         }
1874
1875         /*config key */
1876         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, addr);
1877
1878         /*exist ?*/
1879         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1880         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1881                 /*not exist, error */
1882                 dev_err(dsaf_dev->dev,
1883                         "del_mac_entry failed, %s Mac key(%#x:%#x)\n",
1884                         dsaf_dev->ae_dev.name,
1885                         mac_key.high.val, mac_key.low.val);
1886                 return -EINVAL;
1887         }
1888         dev_dbg(dsaf_dev->dev,
1889                 "del_mac_entry, %s Mac key(%#x:%#x) entry_index%d\n",
1890                 dsaf_dev->ae_dev.name, mac_key.high.val,
1891                 mac_key.low.val, entry_index);
1892
1893         /*do del opt*/
1894         hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
1895
1896         /*del soft emtry */
1897         soft_mac_entry += entry_index;
1898         soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
1899
1900         return 0;
1901 }
1902
1903 /**
1904  * hns_dsaf_del_mac_mc_port - del mac mc- port
1905  * @dsaf_dev: dsa fabric device struct pointer
1906  * @mac_entry: mac entry
1907  */
1908 int hns_dsaf_del_mac_mc_port(struct dsaf_device *dsaf_dev,
1909                              struct dsaf_drv_mac_single_dest_entry *mac_entry)
1910 {
1911         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
1912         struct dsaf_drv_tbl_tcam_key mac_key;
1913         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
1914         struct dsaf_drv_soft_mac_tbl *soft_mac_entry = priv->soft_mac_tbl;
1915         u16 vlan_id;
1916         u8 in_port_num;
1917         struct dsaf_tbl_tcam_mcast_cfg mac_data;
1918         struct dsaf_tbl_tcam_data tcam_data;
1919         int mskid;
1920         const u8 empty_msk[sizeof(mac_data.tbl_mcast_port_msk)] = {0};
1921         struct dsaf_drv_tbl_tcam_key mask_key, tmp_mac_key;
1922         struct dsaf_tbl_tcam_data *pmask_key = NULL;
1923         u8 mc_addr[ETH_ALEN];
1924         u8 *mc_mask;
1925
1926         if (!(void *)mac_entry) {
1927                 dev_err(dsaf_dev->dev,
1928                         "hns_dsaf_del_mac_mc_port mac_entry is NULL\n");
1929                 return -EINVAL;
1930         }
1931
1932         /*check mac addr */
1933         if (MAC_IS_ALL_ZEROS(mac_entry->addr)) {
1934                 dev_err(dsaf_dev->dev, "del_port failed, addr %pM!\n",
1935                         mac_entry->addr);
1936                 return -EINVAL;
1937         }
1938
1939         /* always mask vlan_id field */
1940         ether_addr_copy(mc_addr, mac_entry->addr);
1941         mc_mask = dsaf_dev->mac_cb[mac_entry->in_port_num]->mc_mask;
1942
1943         if (!AE_IS_VER1(dsaf_dev->dsaf_ver)) {
1944                 /* prepare for key data setting */
1945                 hns_dsaf_mc_mask_bit_clear(mc_addr, mc_mask);
1946
1947                 /* config key mask */
1948                 hns_dsaf_set_mac_key(dsaf_dev, &mask_key, 0x00, 0xff, mc_addr);
1949
1950                 mask_key.high.val = le32_to_cpu(mask_key.high.val);
1951                 mask_key.low.val = le32_to_cpu(mask_key.low.val);
1952
1953                 pmask_key = (struct dsaf_tbl_tcam_data *)(&mask_key);
1954         }
1955
1956         /* get key info */
1957         vlan_id = mac_entry->in_vlan_id;
1958         in_port_num = mac_entry->in_port_num;
1959
1960         /* config key */
1961         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, vlan_id, in_port_num, mc_addr);
1962
1963         /* check if the tcam entry is exist */
1964         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
1965         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
1966                 /*find none */
1967                 dev_err(dsaf_dev->dev,
1968                         "find_soft_mac_entry failed, %s Mac key(%#x:%#x)\n",
1969                         dsaf_dev->ae_dev.name,
1970                         mac_key.high.val, mac_key.low.val);
1971                 return -EINVAL;
1972         }
1973
1974         dev_dbg(dsaf_dev->dev,
1975                 "del_mac_mc_port, %s key(%#x:%#x) index%d\n",
1976                 dsaf_dev->ae_dev.name, mac_key.high.val,
1977                 mac_key.low.val, entry_index);
1978
1979         /* read entry */
1980         hns_dsaf_tcam_mc_get(dsaf_dev, entry_index, &tcam_data, &mac_data);
1981
1982         tmp_mac_key.high.val = le32_to_cpu(tcam_data.tbl_tcam_data_high);
1983         tmp_mac_key.low.val = le32_to_cpu(tcam_data.tbl_tcam_data_low);
1984
1985         /*del the port*/
1986         if (mac_entry->port_num < DSAF_SERVICE_NW_NUM) {
1987                 mskid = mac_entry->port_num;
1988         } else if (mac_entry->port_num >= DSAF_BASE_INNER_PORT_NUM) {
1989                 mskid = mac_entry->port_num -
1990                         DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
1991         } else {
1992                 dev_err(dsaf_dev->dev,
1993                         "%s,pnum(%d)error,key(%#x:%#x)\n",
1994                         dsaf_dev->ae_dev.name, mac_entry->port_num,
1995                         mac_key.high.val, mac_key.low.val);
1996                 return -EINVAL;
1997         }
1998         dsaf_set_bit(mac_data.tbl_mcast_port_msk[mskid / 32], mskid % 32, 0);
1999
2000         /*check non port, do del entry */
2001         if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
2002                     sizeof(mac_data.tbl_mcast_port_msk))) {
2003                 hns_dsaf_tcam_mc_invld(dsaf_dev, entry_index);
2004
2005                 /* del soft entry */
2006                 soft_mac_entry += entry_index;
2007                 soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
2008         } else { /* not zero, just del port, update */
2009                 tcam_data.tbl_tcam_data_high = cpu_to_le32(mac_key.high.val);
2010                 tcam_data.tbl_tcam_data_low = cpu_to_le32(mac_key.low.val);
2011
2012                 hns_dsaf_tcam_mc_cfg(dsaf_dev, entry_index,
2013                                      &tcam_data,
2014                                      pmask_key, &mac_data);
2015         }
2016
2017         return 0;
2018 }
2019
2020 int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev, u8 mac_id,
2021                              u8 port_num)
2022 {
2023         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2024         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
2025         struct dsaf_tbl_tcam_mcast_cfg mac_data;
2026         int ret = 0, i;
2027
2028         if (HNS_DSAF_IS_DEBUG(dsaf_dev))
2029                 return 0;
2030
2031         for (i = 0; i < DSAF_TCAM_SUM - DSAFV2_MAC_FUZZY_TCAM_NUM; i++) {
2032                 u8 addr[ETH_ALEN];
2033                 u8 port;
2034
2035                 soft_mac_entry = priv->soft_mac_tbl + i;
2036
2037                 hns_dsaf_tcam_addr_get(&soft_mac_entry->tcam_key, addr);
2038                 port = dsaf_get_field(
2039                                 soft_mac_entry->tcam_key.low.bits.port_vlan,
2040                                 DSAF_TBL_TCAM_KEY_PORT_M,
2041                                 DSAF_TBL_TCAM_KEY_PORT_S);
2042                 /* check valid tcam mc entry */
2043                 if (soft_mac_entry->index != DSAF_INVALID_ENTRY_IDX &&
2044                     port == mac_id &&
2045                     is_multicast_ether_addr(addr) &&
2046                     !is_broadcast_ether_addr(addr)) {
2047                         const u32 empty_msk[DSAF_PORT_MSK_NUM] = {0};
2048                         struct dsaf_drv_mac_single_dest_entry mac_entry;
2049
2050                         /* disable receiving of this multicast address for
2051                          * the VF.
2052                          */
2053                         ether_addr_copy(mac_entry.addr, addr);
2054                         mac_entry.in_vlan_id = dsaf_get_field(
2055                                 soft_mac_entry->tcam_key.low.bits.port_vlan,
2056                                 DSAF_TBL_TCAM_KEY_VLAN_M,
2057                                 DSAF_TBL_TCAM_KEY_VLAN_S);
2058                         mac_entry.in_port_num = mac_id;
2059                         mac_entry.port_num = port_num;
2060                         if (hns_dsaf_del_mac_mc_port(dsaf_dev, &mac_entry)) {
2061                                 ret = -EINVAL;
2062                                 continue;
2063                         }
2064
2065                         /* disable receiving of this multicast address for
2066                          * the mac port if all VF are disable
2067                          */
2068                         hns_dsaf_tcam_mc_get(dsaf_dev, i,
2069                                              (struct dsaf_tbl_tcam_data *)
2070                                              (&soft_mac_entry->tcam_key),
2071                                              &mac_data);
2072                         dsaf_set_bit(mac_data.tbl_mcast_port_msk[mac_id / 32],
2073                                      mac_id % 32, 0);
2074                         if (!memcmp(mac_data.tbl_mcast_port_msk, empty_msk,
2075                                     sizeof(u32) * DSAF_PORT_MSK_NUM)) {
2076                                 mac_entry.port_num = mac_id;
2077                                 if (hns_dsaf_del_mac_mc_port(dsaf_dev,
2078                                                              &mac_entry)) {
2079                                         ret = -EINVAL;
2080                                         continue;
2081                                 }
2082                         }
2083                 }
2084         }
2085
2086         return ret;
2087 }
2088
2089 static struct dsaf_device *hns_dsaf_alloc_dev(struct device *dev,
2090                                               size_t sizeof_priv)
2091 {
2092         struct dsaf_device *dsaf_dev;
2093
2094         dsaf_dev = devm_kzalloc(dev,
2095                                 sizeof(*dsaf_dev) + sizeof_priv, GFP_KERNEL);
2096         if (unlikely(!dsaf_dev)) {
2097                 dsaf_dev = ERR_PTR(-ENOMEM);
2098         } else {
2099                 dsaf_dev->dev = dev;
2100                 dev_set_drvdata(dev, dsaf_dev);
2101         }
2102
2103         return dsaf_dev;
2104 }
2105
2106 /**
2107  * hns_dsaf_free_dev - free dev mem
2108  * @dev: struct device pointer
2109  */
2110 static void hns_dsaf_free_dev(struct dsaf_device *dsaf_dev)
2111 {
2112         (void)dev_set_drvdata(dsaf_dev->dev, NULL);
2113 }
2114
2115 /**
2116  * dsaf_pfc_unit_cnt - set pfc unit count
2117  * @dsaf_id: dsa fabric id
2118  * @pport_rate:  value array
2119  * @pdsaf_pfc_unit_cnt:  value array
2120  */
2121 static void hns_dsaf_pfc_unit_cnt(struct dsaf_device *dsaf_dev, int  mac_id,
2122                                   enum dsaf_port_rate_mode rate)
2123 {
2124         u32 unit_cnt;
2125
2126         switch (rate) {
2127         case DSAF_PORT_RATE_10000:
2128                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2129                 break;
2130         case DSAF_PORT_RATE_1000:
2131                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2132                 break;
2133         case DSAF_PORT_RATE_2500:
2134                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_GE_1000;
2135                 break;
2136         default:
2137                 unit_cnt = HNS_DSAF_PFC_UNIT_CNT_FOR_XGE;
2138         }
2139
2140         dsaf_set_dev_field(dsaf_dev,
2141                            (DSAF_PFC_UNIT_CNT_0_REG + 0x4 * (u64)mac_id),
2142                            DSAF_PFC_UNINT_CNT_M, DSAF_PFC_UNINT_CNT_S,
2143                            unit_cnt);
2144 }
2145
2146 /**
2147  * dsaf_port_work_rate_cfg - fifo
2148  * @dsaf_id: dsa fabric id
2149  * @xge_ge_work_mode
2150  */
2151 void hns_dsaf_port_work_rate_cfg(struct dsaf_device *dsaf_dev, int mac_id,
2152                                  enum dsaf_port_rate_mode rate_mode)
2153 {
2154         u32 port_work_mode;
2155
2156         port_work_mode = dsaf_read_dev(
2157                 dsaf_dev, DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id);
2158
2159         if (rate_mode == DSAF_PORT_RATE_10000)
2160                 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 1);
2161         else
2162                 dsaf_set_bit(port_work_mode, DSAF_XGE_GE_WORK_MODE_S, 0);
2163
2164         dsaf_write_dev(dsaf_dev,
2165                        DSAF_XGE_GE_WORK_MODE_0_REG + 0x4 * (u64)mac_id,
2166                        port_work_mode);
2167
2168         hns_dsaf_pfc_unit_cnt(dsaf_dev, mac_id, rate_mode);
2169 }
2170
2171 /**
2172  * hns_dsaf_fix_mac_mode - dsaf modify mac mode
2173  * @mac_cb: mac contrl block
2174  */
2175 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb)
2176 {
2177         enum dsaf_port_rate_mode mode;
2178         struct dsaf_device *dsaf_dev = mac_cb->dsaf_dev;
2179         int mac_id = mac_cb->mac_id;
2180
2181         if (mac_cb->mac_type != HNAE_PORT_SERVICE)
2182                 return;
2183         if (mac_cb->phy_if == PHY_INTERFACE_MODE_XGMII)
2184                 mode = DSAF_PORT_RATE_10000;
2185         else
2186                 mode = DSAF_PORT_RATE_1000;
2187
2188         hns_dsaf_port_work_rate_cfg(dsaf_dev, mac_id, mode);
2189 }
2190
2191 static u32 hns_dsaf_get_inode_prio_reg(int index)
2192 {
2193         int base_index, offset;
2194         u32 base_addr = DSAF_INODE_IN_PRIO_PAUSE_BASE_REG;
2195
2196         base_index = (index + 1) / DSAF_REG_PER_ZONE;
2197         offset = (index + 1) % DSAF_REG_PER_ZONE;
2198
2199         return base_addr + DSAF_INODE_IN_PRIO_PAUSE_BASE_OFFSET * base_index +
2200                 DSAF_INODE_IN_PRIO_PAUSE_OFFSET * offset;
2201 }
2202
2203 void hns_dsaf_update_stats(struct dsaf_device *dsaf_dev, u32 node_num)
2204 {
2205         struct dsaf_hw_stats *hw_stats
2206                 = &dsaf_dev->hw_stats[node_num];
2207         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2208         int i;
2209         u32 reg_tmp;
2210
2211         hw_stats->pad_drop += dsaf_read_dev(dsaf_dev,
2212                 DSAF_INODE_PAD_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2213         hw_stats->man_pkts += dsaf_read_dev(dsaf_dev,
2214                 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + 0x80 * (u64)node_num);
2215         hw_stats->rx_pkts += dsaf_read_dev(dsaf_dev,
2216                 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + 0x80 * (u64)node_num);
2217         hw_stats->rx_pkt_id += dsaf_read_dev(dsaf_dev,
2218                 DSAF_INODE_SBM_PID_NUM_0_REG + 0x80 * (u64)node_num);
2219
2220         reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2221                             DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2222         hw_stats->rx_pause_frame +=
2223                 dsaf_read_dev(dsaf_dev, reg_tmp + 0x80 * (u64)node_num);
2224
2225         hw_stats->release_buf_num += dsaf_read_dev(dsaf_dev,
2226                 DSAF_INODE_SBM_RELS_NUM_0_REG + 0x80 * (u64)node_num);
2227         hw_stats->sbm_drop += dsaf_read_dev(dsaf_dev,
2228                 DSAF_INODE_SBM_DROP_NUM_0_REG + 0x80 * (u64)node_num);
2229         hw_stats->crc_false += dsaf_read_dev(dsaf_dev,
2230                 DSAF_INODE_CRC_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2231         hw_stats->bp_drop += dsaf_read_dev(dsaf_dev,
2232                 DSAF_INODE_BP_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2233         hw_stats->rslt_drop += dsaf_read_dev(dsaf_dev,
2234                 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + 0x80 * (u64)node_num);
2235         hw_stats->local_addr_false += dsaf_read_dev(dsaf_dev,
2236                 DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + 0x80 * (u64)node_num);
2237
2238         hw_stats->vlan_drop += dsaf_read_dev(dsaf_dev,
2239                 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + 4 * (u64)node_num);
2240         hw_stats->stp_drop += dsaf_read_dev(dsaf_dev,
2241                 DSAF_INODE_IN_DATA_STP_DISC_0_REG + 4 * (u64)node_num);
2242
2243         /* pfc pause frame statistics stored in dsaf inode*/
2244         if ((node_num < DSAF_SERVICE_NW_NUM) && !is_ver1) {
2245                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2246                         reg_tmp = hns_dsaf_get_inode_prio_reg(i);
2247                         hw_stats->rx_pfc[i] += dsaf_read_dev(dsaf_dev,
2248                                 reg_tmp + 0x4 * (u64)node_num);
2249                         hw_stats->tx_pfc[i] += dsaf_read_dev(dsaf_dev,
2250                                 DSAF_XOD_XGE_PFC_PRIO_CNT_BASE_REG +
2251                                 DSAF_XOD_XGE_PFC_PRIO_CNT_OFFSET * i +
2252                                 0xF0 * (u64)node_num);
2253                 }
2254         }
2255         hw_stats->tx_pkts += dsaf_read_dev(dsaf_dev,
2256                 DSAF_XOD_RCVPKT_CNT_0_REG + 0x90 * (u64)node_num);
2257 }
2258
2259 /**
2260  *hns_dsaf_get_regs - dump dsaf regs
2261  *@dsaf_dev: dsaf device
2262  *@data:data for value of regs
2263  */
2264 void hns_dsaf_get_regs(struct dsaf_device *ddev, u32 port, void *data)
2265 {
2266         u32 i = 0;
2267         u32 j;
2268         u32 *p = data;
2269         u32 reg_tmp;
2270         bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2271
2272         /* dsaf common registers */
2273         p[0] = dsaf_read_dev(ddev, DSAF_SRAM_INIT_OVER_0_REG);
2274         p[1] = dsaf_read_dev(ddev, DSAF_CFG_0_REG);
2275         p[2] = dsaf_read_dev(ddev, DSAF_ECC_ERR_INVERT_0_REG);
2276         p[3] = dsaf_read_dev(ddev, DSAF_ABNORMAL_TIMEOUT_0_REG);
2277         p[4] = dsaf_read_dev(ddev, DSAF_FSM_TIMEOUT_0_REG);
2278         p[5] = dsaf_read_dev(ddev, DSAF_DSA_REG_CNT_CLR_CE_REG);
2279         p[6] = dsaf_read_dev(ddev, DSAF_DSA_SBM_INF_FIFO_THRD_REG);
2280         p[7] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_SEL_REG);
2281         p[8] = dsaf_read_dev(ddev, DSAF_DSA_SRAM_1BIT_ECC_CNT_REG);
2282
2283         p[9] = dsaf_read_dev(ddev, DSAF_PFC_EN_0_REG + port * 4);
2284         p[10] = dsaf_read_dev(ddev, DSAF_PFC_UNIT_CNT_0_REG + port * 4);
2285         p[11] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2286         p[12] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2287         p[13] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2288         p[14] = dsaf_read_dev(ddev, DSAF_XGE_INT_MSK_0_REG + port * 4);
2289         p[15] = dsaf_read_dev(ddev, DSAF_PPE_INT_MSK_0_REG + port * 4);
2290         p[16] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_MSK_0_REG + port * 4);
2291         p[17] = dsaf_read_dev(ddev, DSAF_XGE_INT_SRC_0_REG + port * 4);
2292         p[18] = dsaf_read_dev(ddev, DSAF_PPE_INT_SRC_0_REG + port * 4);
2293         p[19] =  dsaf_read_dev(ddev, DSAF_ROCEE_INT_SRC_0_REG + port * 4);
2294         p[20] = dsaf_read_dev(ddev, DSAF_XGE_INT_STS_0_REG + port * 4);
2295         p[21] = dsaf_read_dev(ddev, DSAF_PPE_INT_STS_0_REG + port * 4);
2296         p[22] = dsaf_read_dev(ddev, DSAF_ROCEE_INT_STS_0_REG + port * 4);
2297         p[23] = dsaf_read_dev(ddev, DSAF_PPE_QID_CFG_0_REG + port * 4);
2298
2299         for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2300                 p[24 + i] = dsaf_read_dev(ddev,
2301                                 DSAF_SW_PORT_TYPE_0_REG + i * 4);
2302
2303         p[32] = dsaf_read_dev(ddev, DSAF_MIX_DEF_QID_0_REG + port * 4);
2304
2305         for (i = 0; i < DSAF_SW_PORT_NUM; i++)
2306                 p[33 + i] = dsaf_read_dev(ddev,
2307                                 DSAF_PORT_DEF_VLAN_0_REG + i * 4);
2308
2309         for (i = 0; i < DSAF_TOTAL_QUEUE_NUM; i++)
2310                 p[41 + i] = dsaf_read_dev(ddev,
2311                                 DSAF_VM_DEF_VLAN_0_REG + i * 4);
2312
2313         /* dsaf inode registers */
2314         p[170] = dsaf_read_dev(ddev, DSAF_INODE_CUT_THROUGH_CFG_0_REG);
2315
2316         p[171] = dsaf_read_dev(ddev,
2317                         DSAF_INODE_ECC_ERR_ADDR_0_REG + port * 0x80);
2318
2319         for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2320                 j = i * DSAF_COMM_CHN + port;
2321                 p[172 + i] = dsaf_read_dev(ddev,
2322                                 DSAF_INODE_IN_PORT_NUM_0_REG + j * 0x80);
2323                 p[175 + i] = dsaf_read_dev(ddev,
2324                                 DSAF_INODE_PRI_TC_CFG_0_REG + j * 0x80);
2325                 p[178 + i] = dsaf_read_dev(ddev,
2326                                 DSAF_INODE_BP_STATUS_0_REG + j * 0x80);
2327                 p[181 + i] = dsaf_read_dev(ddev,
2328                                 DSAF_INODE_PAD_DISCARD_NUM_0_REG + j * 0x80);
2329                 p[184 + i] = dsaf_read_dev(ddev,
2330                                 DSAF_INODE_FINAL_IN_MAN_NUM_0_REG + j * 0x80);
2331                 p[187 + i] = dsaf_read_dev(ddev,
2332                                 DSAF_INODE_FINAL_IN_PKT_NUM_0_REG + j * 0x80);
2333                 p[190 + i] = dsaf_read_dev(ddev,
2334                                 DSAF_INODE_SBM_PID_NUM_0_REG + j * 0x80);
2335                 reg_tmp = is_ver1 ? DSAF_INODE_FINAL_IN_PAUSE_NUM_0_REG :
2336                                     DSAFV2_INODE_FINAL_IN_PAUSE_NUM_0_REG;
2337                 p[193 + i] = dsaf_read_dev(ddev, reg_tmp + j * 0x80);
2338                 p[196 + i] = dsaf_read_dev(ddev,
2339                                 DSAF_INODE_SBM_RELS_NUM_0_REG + j * 0x80);
2340                 p[199 + i] = dsaf_read_dev(ddev,
2341                                 DSAF_INODE_SBM_DROP_NUM_0_REG + j * 0x80);
2342                 p[202 + i] = dsaf_read_dev(ddev,
2343                                 DSAF_INODE_CRC_FALSE_NUM_0_REG + j * 0x80);
2344                 p[205 + i] = dsaf_read_dev(ddev,
2345                                 DSAF_INODE_BP_DISCARD_NUM_0_REG + j * 0x80);
2346                 p[208 + i] = dsaf_read_dev(ddev,
2347                                 DSAF_INODE_RSLT_DISCARD_NUM_0_REG + j * 0x80);
2348                 p[211 + i] = dsaf_read_dev(ddev,
2349                         DSAF_INODE_LOCAL_ADDR_FALSE_NUM_0_REG + j * 0x80);
2350                 p[214 + i] = dsaf_read_dev(ddev,
2351                                 DSAF_INODE_VOQ_OVER_NUM_0_REG + j * 0x80);
2352                 p[217 + i] = dsaf_read_dev(ddev,
2353                                 DSAF_INODE_BD_SAVE_STATUS_0_REG + j * 4);
2354                 p[220 + i] = dsaf_read_dev(ddev,
2355                                 DSAF_INODE_BD_ORDER_STATUS_0_REG + j * 4);
2356                 p[223 + i] = dsaf_read_dev(ddev,
2357                                 DSAF_INODE_SW_VLAN_TAG_DISC_0_REG + j * 4);
2358                 p[226 + i] = dsaf_read_dev(ddev,
2359                                 DSAF_INODE_IN_DATA_STP_DISC_0_REG + j * 4);
2360         }
2361
2362         p[229] = dsaf_read_dev(ddev, DSAF_INODE_GE_FC_EN_0_REG + port * 4);
2363
2364         for (i = 0; i < DSAF_INODE_NUM / DSAF_COMM_CHN; i++) {
2365                 j = i * DSAF_COMM_CHN + port;
2366                 p[230 + i] = dsaf_read_dev(ddev,
2367                                 DSAF_INODE_VC0_IN_PKT_NUM_0_REG + j * 4);
2368         }
2369
2370         p[233] = dsaf_read_dev(ddev,
2371                 DSAF_INODE_VC1_IN_PKT_NUM_0_REG + port * 0x80);
2372
2373         /* dsaf inode registers */
2374         for (i = 0; i < HNS_DSAF_SBM_NUM(ddev) / DSAF_COMM_CHN; i++) {
2375                 j = i * DSAF_COMM_CHN + port;
2376                 p[234 + i] = dsaf_read_dev(ddev,
2377                                 DSAF_SBM_CFG_REG_0_REG + j * 0x80);
2378                 p[237 + i] = dsaf_read_dev(ddev,
2379                                 DSAF_SBM_BP_CFG_0_XGE_REG_0_REG + j * 0x80);
2380                 p[240 + i] = dsaf_read_dev(ddev,
2381                                 DSAF_SBM_BP_CFG_1_REG_0_REG + j * 0x80);
2382                 p[243 + i] = dsaf_read_dev(ddev,
2383                                 DSAF_SBM_BP_CFG_2_XGE_REG_0_REG + j * 0x80);
2384                 p[246 + i] = dsaf_read_dev(ddev,
2385                                 DSAF_SBM_FREE_CNT_0_0_REG + j * 0x80);
2386                 p[249 + i] = dsaf_read_dev(ddev,
2387                                 DSAF_SBM_FREE_CNT_1_0_REG + j * 0x80);
2388                 p[252 + i] = dsaf_read_dev(ddev,
2389                                 DSAF_SBM_BP_CNT_0_0_REG + j * 0x80);
2390                 p[255 + i] = dsaf_read_dev(ddev,
2391                                 DSAF_SBM_BP_CNT_1_0_REG + j * 0x80);
2392                 p[258 + i] = dsaf_read_dev(ddev,
2393                                 DSAF_SBM_BP_CNT_2_0_REG + j * 0x80);
2394                 p[261 + i] = dsaf_read_dev(ddev,
2395                                 DSAF_SBM_BP_CNT_3_0_REG + j * 0x80);
2396                 p[264 + i] = dsaf_read_dev(ddev,
2397                                 DSAF_SBM_INER_ST_0_REG + j * 0x80);
2398                 p[267 + i] = dsaf_read_dev(ddev,
2399                                 DSAF_SBM_MIB_REQ_FAILED_TC_0_REG + j * 0x80);
2400                 p[270 + i] = dsaf_read_dev(ddev,
2401                                 DSAF_SBM_LNK_INPORT_CNT_0_REG + j * 0x80);
2402                 p[273 + i] = dsaf_read_dev(ddev,
2403                                 DSAF_SBM_LNK_DROP_CNT_0_REG + j * 0x80);
2404                 p[276 + i] = dsaf_read_dev(ddev,
2405                                 DSAF_SBM_INF_OUTPORT_CNT_0_REG + j * 0x80);
2406                 p[279 + i] = dsaf_read_dev(ddev,
2407                                 DSAF_SBM_LNK_INPORT_TC0_CNT_0_REG + j * 0x80);
2408                 p[282 + i] = dsaf_read_dev(ddev,
2409                                 DSAF_SBM_LNK_INPORT_TC1_CNT_0_REG + j * 0x80);
2410                 p[285 + i] = dsaf_read_dev(ddev,
2411                                 DSAF_SBM_LNK_INPORT_TC2_CNT_0_REG + j * 0x80);
2412                 p[288 + i] = dsaf_read_dev(ddev,
2413                                 DSAF_SBM_LNK_INPORT_TC3_CNT_0_REG + j * 0x80);
2414                 p[291 + i] = dsaf_read_dev(ddev,
2415                                 DSAF_SBM_LNK_INPORT_TC4_CNT_0_REG + j * 0x80);
2416                 p[294 + i] = dsaf_read_dev(ddev,
2417                                 DSAF_SBM_LNK_INPORT_TC5_CNT_0_REG + j * 0x80);
2418                 p[297 + i] = dsaf_read_dev(ddev,
2419                                 DSAF_SBM_LNK_INPORT_TC6_CNT_0_REG + j * 0x80);
2420                 p[300 + i] = dsaf_read_dev(ddev,
2421                                 DSAF_SBM_LNK_INPORT_TC7_CNT_0_REG + j * 0x80);
2422                 p[303 + i] = dsaf_read_dev(ddev,
2423                                 DSAF_SBM_LNK_REQ_CNT_0_REG + j * 0x80);
2424                 p[306 + i] = dsaf_read_dev(ddev,
2425                                 DSAF_SBM_LNK_RELS_CNT_0_REG + j * 0x80);
2426                 p[309 + i] = dsaf_read_dev(ddev,
2427                                 DSAF_SBM_BP_CFG_3_REG_0_REG + j * 0x80);
2428                 p[312 + i] = dsaf_read_dev(ddev,
2429                                 DSAF_SBM_BP_CFG_4_REG_0_REG + j * 0x80);
2430         }
2431
2432         /* dsaf onode registers */
2433         for (i = 0; i < DSAF_XOD_NUM; i++) {
2434                 p[315 + i] = dsaf_read_dev(ddev,
2435                                 DSAF_XOD_ETS_TSA_TC0_TC3_CFG_0_REG + i * 0x90);
2436                 p[323 + i] = dsaf_read_dev(ddev,
2437                                 DSAF_XOD_ETS_TSA_TC4_TC7_CFG_0_REG + i * 0x90);
2438                 p[331 + i] = dsaf_read_dev(ddev,
2439                                 DSAF_XOD_ETS_BW_TC0_TC3_CFG_0_REG + i * 0x90);
2440                 p[339 + i] = dsaf_read_dev(ddev,
2441                                 DSAF_XOD_ETS_BW_TC4_TC7_CFG_0_REG + i * 0x90);
2442                 p[347 + i] = dsaf_read_dev(ddev,
2443                                 DSAF_XOD_ETS_BW_OFFSET_CFG_0_REG + i * 0x90);
2444                 p[355 + i] = dsaf_read_dev(ddev,
2445                                 DSAF_XOD_ETS_TOKEN_CFG_0_REG + i * 0x90);
2446         }
2447
2448         p[363] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_0_0_REG + port * 0x90);
2449         p[364] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_1_0_REG + port * 0x90);
2450         p[365] = dsaf_read_dev(ddev, DSAF_XOD_PFS_CFG_2_0_REG + port * 0x90);
2451
2452         for (i = 0; i < DSAF_XOD_BIG_NUM / DSAF_COMM_CHN; i++) {
2453                 j = i * DSAF_COMM_CHN + port;
2454                 p[366 + i] = dsaf_read_dev(ddev,
2455                                 DSAF_XOD_GNT_L_0_REG + j * 0x90);
2456                 p[369 + i] = dsaf_read_dev(ddev,
2457                                 DSAF_XOD_GNT_H_0_REG + j * 0x90);
2458                 p[372 + i] = dsaf_read_dev(ddev,
2459                                 DSAF_XOD_CONNECT_STATE_0_REG + j * 0x90);
2460                 p[375 + i] = dsaf_read_dev(ddev,
2461                                 DSAF_XOD_RCVPKT_CNT_0_REG + j * 0x90);
2462                 p[378 + i] = dsaf_read_dev(ddev,
2463                                 DSAF_XOD_RCVTC0_CNT_0_REG + j * 0x90);
2464                 p[381 + i] = dsaf_read_dev(ddev,
2465                                 DSAF_XOD_RCVTC1_CNT_0_REG + j * 0x90);
2466                 p[384 + i] = dsaf_read_dev(ddev,
2467                                 DSAF_XOD_RCVTC2_CNT_0_REG + j * 0x90);
2468                 p[387 + i] = dsaf_read_dev(ddev,
2469                                 DSAF_XOD_RCVTC3_CNT_0_REG + j * 0x90);
2470                 p[390 + i] = dsaf_read_dev(ddev,
2471                                 DSAF_XOD_RCVVC0_CNT_0_REG + j * 0x90);
2472                 p[393 + i] = dsaf_read_dev(ddev,
2473                                 DSAF_XOD_RCVVC1_CNT_0_REG + j * 0x90);
2474         }
2475
2476         p[396] = dsaf_read_dev(ddev,
2477                 DSAF_XOD_XGE_RCVIN0_CNT_0_REG + port * 0x90);
2478         p[397] = dsaf_read_dev(ddev,
2479                 DSAF_XOD_XGE_RCVIN1_CNT_0_REG + port * 0x90);
2480         p[398] = dsaf_read_dev(ddev,
2481                 DSAF_XOD_XGE_RCVIN2_CNT_0_REG + port * 0x90);
2482         p[399] = dsaf_read_dev(ddev,
2483                 DSAF_XOD_XGE_RCVIN3_CNT_0_REG + port * 0x90);
2484         p[400] = dsaf_read_dev(ddev,
2485                 DSAF_XOD_XGE_RCVIN4_CNT_0_REG + port * 0x90);
2486         p[401] = dsaf_read_dev(ddev,
2487                 DSAF_XOD_XGE_RCVIN5_CNT_0_REG + port * 0x90);
2488         p[402] = dsaf_read_dev(ddev,
2489                 DSAF_XOD_XGE_RCVIN6_CNT_0_REG + port * 0x90);
2490         p[403] = dsaf_read_dev(ddev,
2491                 DSAF_XOD_XGE_RCVIN7_CNT_0_REG + port * 0x90);
2492         p[404] = dsaf_read_dev(ddev,
2493                 DSAF_XOD_PPE_RCVIN0_CNT_0_REG + port * 0x90);
2494         p[405] = dsaf_read_dev(ddev,
2495                 DSAF_XOD_PPE_RCVIN1_CNT_0_REG + port * 0x90);
2496         p[406] = dsaf_read_dev(ddev,
2497                 DSAF_XOD_ROCEE_RCVIN0_CNT_0_REG + port * 0x90);
2498         p[407] = dsaf_read_dev(ddev,
2499                 DSAF_XOD_ROCEE_RCVIN1_CNT_0_REG + port * 0x90);
2500         p[408] = dsaf_read_dev(ddev,
2501                 DSAF_XOD_FIFO_STATUS_0_REG + port * 0x90);
2502
2503         /* dsaf voq registers */
2504         for (i = 0; i < DSAF_VOQ_NUM / DSAF_COMM_CHN; i++) {
2505                 j = (i * DSAF_COMM_CHN + port) * 0x90;
2506                 p[409 + i] = dsaf_read_dev(ddev,
2507                         DSAF_VOQ_ECC_INVERT_EN_0_REG + j);
2508                 p[412 + i] = dsaf_read_dev(ddev,
2509                         DSAF_VOQ_SRAM_PKT_NUM_0_REG + j);
2510                 p[415 + i] = dsaf_read_dev(ddev, DSAF_VOQ_IN_PKT_NUM_0_REG + j);
2511                 p[418 + i] = dsaf_read_dev(ddev,
2512                         DSAF_VOQ_OUT_PKT_NUM_0_REG + j);
2513                 p[421 + i] = dsaf_read_dev(ddev,
2514                         DSAF_VOQ_ECC_ERR_ADDR_0_REG + j);
2515                 p[424 + i] = dsaf_read_dev(ddev, DSAF_VOQ_BP_STATUS_0_REG + j);
2516                 p[427 + i] = dsaf_read_dev(ddev, DSAF_VOQ_SPUP_IDLE_0_REG + j);
2517                 p[430 + i] = dsaf_read_dev(ddev,
2518                         DSAF_VOQ_XGE_XOD_REQ_0_0_REG + j);
2519                 p[433 + i] = dsaf_read_dev(ddev,
2520                         DSAF_VOQ_XGE_XOD_REQ_1_0_REG + j);
2521                 p[436 + i] = dsaf_read_dev(ddev,
2522                         DSAF_VOQ_PPE_XOD_REQ_0_REG + j);
2523                 p[439 + i] = dsaf_read_dev(ddev,
2524                         DSAF_VOQ_ROCEE_XOD_REQ_0_REG + j);
2525                 p[442 + i] = dsaf_read_dev(ddev,
2526                         DSAF_VOQ_BP_ALL_THRD_0_REG + j);
2527         }
2528
2529         /* dsaf tbl registers */
2530         p[445] = dsaf_read_dev(ddev, DSAF_TBL_CTRL_0_REG);
2531         p[446] = dsaf_read_dev(ddev, DSAF_TBL_INT_MSK_0_REG);
2532         p[447] = dsaf_read_dev(ddev, DSAF_TBL_INT_SRC_0_REG);
2533         p[448] = dsaf_read_dev(ddev, DSAF_TBL_INT_STS_0_REG);
2534         p[449] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_ADDR_0_REG);
2535         p[450] = dsaf_read_dev(ddev, DSAF_TBL_LINE_ADDR_0_REG);
2536         p[451] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_HIGH_0_REG);
2537         p[452] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_LOW_0_REG);
2538         p[453] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG);
2539         p[454] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG);
2540         p[455] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG);
2541         p[456] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG);
2542         p[457] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG);
2543         p[458] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_UCAST_CFG_0_REG);
2544         p[459] = dsaf_read_dev(ddev, DSAF_TBL_LIN_CFG_0_REG);
2545         p[460] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_HIGH_0_REG);
2546         p[461] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RDATA_LOW_0_REG);
2547         p[462] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA4_0_REG);
2548         p[463] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA3_0_REG);
2549         p[464] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA2_0_REG);
2550         p[465] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA1_0_REG);
2551         p[466] = dsaf_read_dev(ddev, DSAF_TBL_TCAM_RAM_RDATA0_0_REG);
2552         p[467] = dsaf_read_dev(ddev, DSAF_TBL_LIN_RDATA_0_REG);
2553
2554         for (i = 0; i < DSAF_SW_PORT_NUM; i++) {
2555                 j = i * 0x8;
2556                 p[468 + 2 * i] = dsaf_read_dev(ddev,
2557                         DSAF_TBL_DA0_MIS_INFO1_0_REG + j);
2558                 p[469 + 2 * i] = dsaf_read_dev(ddev,
2559                         DSAF_TBL_DA0_MIS_INFO0_0_REG + j);
2560         }
2561
2562         p[484] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO2_0_REG);
2563         p[485] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO1_0_REG);
2564         p[486] = dsaf_read_dev(ddev, DSAF_TBL_SA_MIS_INFO0_0_REG);
2565         p[487] = dsaf_read_dev(ddev, DSAF_TBL_PUL_0_REG);
2566         p[488] = dsaf_read_dev(ddev, DSAF_TBL_OLD_RSLT_0_REG);
2567         p[489] = dsaf_read_dev(ddev, DSAF_TBL_OLD_SCAN_VAL_0_REG);
2568         p[490] = dsaf_read_dev(ddev, DSAF_TBL_DFX_CTRL_0_REG);
2569         p[491] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_0_REG);
2570         p[492] = dsaf_read_dev(ddev, DSAF_TBL_DFX_STAT_2_0_REG);
2571         p[493] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_I_0_REG);
2572         p[494] = dsaf_read_dev(ddev, DSAF_TBL_LKUP_NUM_O_0_REG);
2573         p[495] = dsaf_read_dev(ddev, DSAF_TBL_UCAST_BCAST_MIS_INFO_0_0_REG);
2574
2575         /* dsaf other registers */
2576         p[496] = dsaf_read_dev(ddev, DSAF_INODE_FIFO_WL_0_REG + port * 0x4);
2577         p[497] = dsaf_read_dev(ddev, DSAF_ONODE_FIFO_WL_0_REG + port * 0x4);
2578         p[498] = dsaf_read_dev(ddev, DSAF_XGE_GE_WORK_MODE_0_REG + port * 0x4);
2579         p[499] = dsaf_read_dev(ddev,
2580                 DSAF_XGE_APP_RX_LINK_UP_0_REG + port * 0x4);
2581         p[500] = dsaf_read_dev(ddev, DSAF_NETPORT_CTRL_SIG_0_REG + port * 0x4);
2582         p[501] = dsaf_read_dev(ddev, DSAF_XGE_CTRL_SIG_CFG_0_REG + port * 0x4);
2583
2584         if (!is_ver1)
2585                 p[502] = dsaf_read_dev(ddev, DSAF_PAUSE_CFG_REG + port * 0x4);
2586
2587         /* mark end of dsaf regs */
2588         for (i = 503; i < 504; i++)
2589                 p[i] = 0xdddddddd;
2590 }
2591
2592 static char *hns_dsaf_get_node_stats_strings(char *data, int node,
2593                                              struct dsaf_device *dsaf_dev)
2594 {
2595         char *buff = data;
2596         int i;
2597         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2598
2599         snprintf(buff, ETH_GSTRING_LEN, "innod%d_pad_drop_pkts", node);
2600         buff += ETH_GSTRING_LEN;
2601         snprintf(buff, ETH_GSTRING_LEN, "innod%d_manage_pkts", node);
2602         buff += ETH_GSTRING_LEN;
2603         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkts", node);
2604         buff += ETH_GSTRING_LEN;
2605         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pkt_id", node);
2606         buff += ETH_GSTRING_LEN;
2607         snprintf(buff, ETH_GSTRING_LEN, "innod%d_rx_pause_frame", node);
2608         buff += ETH_GSTRING_LEN;
2609         snprintf(buff, ETH_GSTRING_LEN, "innod%d_release_buf_num", node);
2610         buff += ETH_GSTRING_LEN;
2611         snprintf(buff, ETH_GSTRING_LEN, "innod%d_sbm_drop_pkts", node);
2612         buff += ETH_GSTRING_LEN;
2613         snprintf(buff, ETH_GSTRING_LEN, "innod%d_crc_false_pkts", node);
2614         buff += ETH_GSTRING_LEN;
2615         snprintf(buff, ETH_GSTRING_LEN, "innod%d_bp_drop_pkts", node);
2616         buff += ETH_GSTRING_LEN;
2617         snprintf(buff, ETH_GSTRING_LEN, "innod%d_lookup_rslt_drop_pkts", node);
2618         buff += ETH_GSTRING_LEN;
2619         snprintf(buff, ETH_GSTRING_LEN, "innod%d_local_rslt_fail_pkts", node);
2620         buff += ETH_GSTRING_LEN;
2621         snprintf(buff, ETH_GSTRING_LEN, "innod%d_vlan_drop_pkts", node);
2622         buff += ETH_GSTRING_LEN;
2623         snprintf(buff, ETH_GSTRING_LEN, "innod%d_stp_drop_pkts", node);
2624         buff += ETH_GSTRING_LEN;
2625         if (node < DSAF_SERVICE_NW_NUM && !is_ver1) {
2626                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2627                         snprintf(buff + 0 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2628                                  ETH_GSTRING_LEN, "inod%d_pfc_prio%d_pkts",
2629                                  node, i);
2630                         snprintf(buff + 1 * ETH_GSTRING_LEN * DSAF_PRIO_NR,
2631                                  ETH_GSTRING_LEN, "onod%d_pfc_prio%d_pkts",
2632                                  node, i);
2633                         buff += ETH_GSTRING_LEN;
2634                 }
2635                 buff += 1 * DSAF_PRIO_NR * ETH_GSTRING_LEN;
2636         }
2637         snprintf(buff, ETH_GSTRING_LEN, "onnod%d_tx_pkts", node);
2638         buff += ETH_GSTRING_LEN;
2639
2640         return buff;
2641 }
2642
2643 static u64 *hns_dsaf_get_node_stats(struct dsaf_device *ddev, u64 *data,
2644                                     int node_num)
2645 {
2646         u64 *p = data;
2647         int i;
2648         struct dsaf_hw_stats *hw_stats = &ddev->hw_stats[node_num];
2649         bool is_ver1 = AE_IS_VER1(ddev->dsaf_ver);
2650
2651         p[0] = hw_stats->pad_drop;
2652         p[1] = hw_stats->man_pkts;
2653         p[2] = hw_stats->rx_pkts;
2654         p[3] = hw_stats->rx_pkt_id;
2655         p[4] = hw_stats->rx_pause_frame;
2656         p[5] = hw_stats->release_buf_num;
2657         p[6] = hw_stats->sbm_drop;
2658         p[7] = hw_stats->crc_false;
2659         p[8] = hw_stats->bp_drop;
2660         p[9] = hw_stats->rslt_drop;
2661         p[10] = hw_stats->local_addr_false;
2662         p[11] = hw_stats->vlan_drop;
2663         p[12] = hw_stats->stp_drop;
2664         if (node_num < DSAF_SERVICE_NW_NUM && !is_ver1) {
2665                 for (i = 0; i < DSAF_PRIO_NR; i++) {
2666                         p[13 + i + 0 * DSAF_PRIO_NR] = hw_stats->rx_pfc[i];
2667                         p[13 + i + 1 * DSAF_PRIO_NR] = hw_stats->tx_pfc[i];
2668                 }
2669                 p[29] = hw_stats->tx_pkts;
2670                 return &p[30];
2671         }
2672
2673         p[13] = hw_stats->tx_pkts;
2674         return &p[14];
2675 }
2676
2677 /**
2678  *hns_dsaf_get_stats - get dsaf statistic
2679  *@ddev: dsaf device
2680  *@data:statistic value
2681  *@port: port num
2682  */
2683 void hns_dsaf_get_stats(struct dsaf_device *ddev, u64 *data, int port)
2684 {
2685         u64 *p = data;
2686         int node_num = port;
2687
2688         /* for ge/xge node info */
2689         p = hns_dsaf_get_node_stats(ddev, p, node_num);
2690
2691         /* for ppe node info */
2692         node_num = port + DSAF_PPE_INODE_BASE;
2693         (void)hns_dsaf_get_node_stats(ddev, p, node_num);
2694 }
2695
2696 /**
2697  *hns_dsaf_get_sset_count - get dsaf string set count
2698  *@stringset: type of values in data
2699  *return dsaf string name count
2700  */
2701 int hns_dsaf_get_sset_count(struct dsaf_device *dsaf_dev, int stringset)
2702 {
2703         bool is_ver1 = AE_IS_VER1(dsaf_dev->dsaf_ver);
2704
2705         if (stringset == ETH_SS_STATS) {
2706                 if (is_ver1)
2707                         return DSAF_STATIC_NUM;
2708                 else
2709                         return DSAF_V2_STATIC_NUM;
2710         }
2711         return 0;
2712 }
2713
2714 /**
2715  *hns_dsaf_get_strings - get dsaf string set
2716  *@stringset:srting set index
2717  *@data:strings name value
2718  *@port:port index
2719  */
2720 void hns_dsaf_get_strings(int stringset, u8 *data, int port,
2721                           struct dsaf_device *dsaf_dev)
2722 {
2723         char *buff = (char *)data;
2724         int node = port;
2725
2726         if (stringset != ETH_SS_STATS)
2727                 return;
2728
2729         /* for ge/xge node info */
2730         buff = hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2731
2732         /* for ppe node info */
2733         node = port + DSAF_PPE_INODE_BASE;
2734         (void)hns_dsaf_get_node_stats_strings(buff, node, dsaf_dev);
2735 }
2736
2737 /**
2738  *hns_dsaf_get_sset_count - get dsaf regs count
2739  *return dsaf regs count
2740  */
2741 int hns_dsaf_get_regs_count(void)
2742 {
2743         return DSAF_DUMP_REGS_NUM;
2744 }
2745
2746 static int hns_dsaf_get_port_id(u8 port)
2747 {
2748         if (port < DSAF_SERVICE_NW_NUM)
2749                 return port;
2750
2751         if (port >= DSAF_BASE_INNER_PORT_NUM)
2752                 return port - DSAF_BASE_INNER_PORT_NUM + DSAF_SERVICE_NW_NUM;
2753
2754         return -EINVAL;
2755 }
2756
2757 static void set_promisc_tcam_enable(struct dsaf_device *dsaf_dev, u32 port)
2758 {
2759         struct dsaf_tbl_tcam_ucast_cfg tbl_tcam_ucast = {0, 1, 0, 0, 0x80};
2760         struct dsaf_tbl_tcam_data tbl_tcam_data_mc = {0x01000000, port};
2761         struct dsaf_tbl_tcam_data tbl_tcam_mask_uc = {0x01000000, 0xf};
2762         struct dsaf_tbl_tcam_mcast_cfg tbl_tcam_mcast = {0, 0, {0} };
2763         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2764         struct dsaf_tbl_tcam_data tbl_tcam_data_uc = {0, port};
2765         struct dsaf_drv_mac_single_dest_entry mask_entry;
2766         struct dsaf_drv_tbl_tcam_key temp_key, mask_key;
2767         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
2768         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
2769         struct dsaf_drv_tbl_tcam_key mac_key;
2770         struct hns_mac_cb *mac_cb;
2771         u8 addr[ETH_ALEN] = {0};
2772         u8 port_num;
2773         int mskid;
2774
2775         /* promisc use vague table match with vlanid = 0 & macaddr = 0 */
2776         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr);
2777         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
2778         if (entry_index != DSAF_INVALID_ENTRY_IDX)
2779                 return;
2780
2781         /* put promisc tcam entry in the end. */
2782         /* 1. set promisc unicast vague tcam entry. */
2783         entry_index = hns_dsaf_find_empty_mac_entry_reverse(dsaf_dev);
2784         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
2785                 dev_err(dsaf_dev->dev,
2786                         "enable uc promisc failed (port:%#x)\n",
2787                         port);
2788                 return;
2789         }
2790
2791         mac_cb = dsaf_dev->mac_cb[port];
2792         (void)hns_mac_get_inner_port_num(mac_cb, 0, &port_num);
2793         tbl_tcam_ucast.tbl_ucast_out_port = port_num;
2794
2795         /* config uc vague table */
2796         hns_dsaf_tcam_uc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_uc,
2797                                    &tbl_tcam_mask_uc, &tbl_tcam_ucast);
2798
2799         /* update software entry */
2800         soft_mac_entry = priv->soft_mac_tbl;
2801         soft_mac_entry += entry_index;
2802         soft_mac_entry->index = entry_index;
2803         soft_mac_entry->tcam_key.high.val = mac_key.high.val;
2804         soft_mac_entry->tcam_key.low.val = mac_key.low.val;
2805         /* step back to the START for mc. */
2806         soft_mac_entry = priv->soft_mac_tbl;
2807
2808         /* 2. set promisc multicast vague tcam entry. */
2809         entry_index = hns_dsaf_find_empty_mac_entry_reverse(dsaf_dev);
2810         if (entry_index == DSAF_INVALID_ENTRY_IDX) {
2811                 dev_err(dsaf_dev->dev,
2812                         "enable mc promisc failed (port:%#x)\n",
2813                         port);
2814                 return;
2815         }
2816
2817         memset(&mask_entry, 0x0, sizeof(mask_entry));
2818         memset(&mask_key, 0x0, sizeof(mask_key));
2819         memset(&temp_key, 0x0, sizeof(temp_key));
2820         mask_entry.addr[0] = 0x01;
2821         hns_dsaf_set_mac_key(dsaf_dev, &mask_key, mask_entry.in_vlan_id,
2822                              0xf, mask_entry.addr);
2823         tbl_tcam_mcast.tbl_mcast_item_vld = 1;
2824         tbl_tcam_mcast.tbl_mcast_old_en = 0;
2825
2826         /* set MAC port to handle multicast */
2827         mskid = hns_dsaf_get_port_id(port);
2828         if (mskid == -EINVAL) {
2829                 dev_err(dsaf_dev->dev, "%s,pnum(%d)error,key(%#x:%#x)\n",
2830                         dsaf_dev->ae_dev.name, port,
2831                         mask_key.high.val, mask_key.low.val);
2832                 return;
2833         }
2834         dsaf_set_bit(tbl_tcam_mcast.tbl_mcast_port_msk[mskid / 32],
2835                      mskid % 32, 1);
2836
2837         /* set pool bit map to handle multicast */
2838         mskid = hns_dsaf_get_port_id(port_num);
2839         if (mskid == -EINVAL) {
2840                 dev_err(dsaf_dev->dev,
2841                         "%s, pool bit map pnum(%d)error,key(%#x:%#x)\n",
2842                         dsaf_dev->ae_dev.name, port_num,
2843                         mask_key.high.val, mask_key.low.val);
2844                 return;
2845         }
2846         dsaf_set_bit(tbl_tcam_mcast.tbl_mcast_port_msk[mskid / 32],
2847                      mskid % 32, 1);
2848
2849         memcpy(&temp_key, &mask_key, sizeof(mask_key));
2850         hns_dsaf_tcam_mc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_mc,
2851                                    (struct dsaf_tbl_tcam_data *)(&mask_key),
2852                                    &tbl_tcam_mcast);
2853
2854         /* update software entry */
2855         soft_mac_entry += entry_index;
2856         soft_mac_entry->index = entry_index;
2857         soft_mac_entry->tcam_key.high.val = temp_key.high.val;
2858         soft_mac_entry->tcam_key.low.val = temp_key.low.val;
2859 }
2860
2861 static void set_promisc_tcam_disable(struct dsaf_device *dsaf_dev, u32 port)
2862 {
2863         struct dsaf_tbl_tcam_data tbl_tcam_data_mc = {0x01000000, port};
2864         struct dsaf_tbl_tcam_ucast_cfg tbl_tcam_ucast = {0, 0, 0, 0, 0};
2865         struct dsaf_tbl_tcam_mcast_cfg tbl_tcam_mcast = {0, 0, {0} };
2866         struct dsaf_drv_priv *priv = hns_dsaf_dev_priv(dsaf_dev);
2867         struct dsaf_tbl_tcam_data tbl_tcam_data_uc = {0, 0};
2868         struct dsaf_tbl_tcam_data tbl_tcam_mask = {0, 0};
2869         struct dsaf_drv_soft_mac_tbl *soft_mac_entry;
2870         u16 entry_index = DSAF_INVALID_ENTRY_IDX;
2871         struct dsaf_drv_tbl_tcam_key mac_key;
2872         u8 addr[ETH_ALEN] = {0};
2873
2874         /* 1. delete uc vague tcam entry. */
2875         /* promisc use vague table match with vlanid = 0 & macaddr = 0 */
2876         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr);
2877         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
2878
2879         if (entry_index == DSAF_INVALID_ENTRY_IDX)
2880                 return;
2881
2882         /* config uc vague table */
2883         hns_dsaf_tcam_uc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_uc,
2884                                    &tbl_tcam_mask, &tbl_tcam_ucast);
2885         /* update soft management table. */
2886         soft_mac_entry = priv->soft_mac_tbl;
2887         soft_mac_entry += entry_index;
2888         soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
2889         /* step back to the START for mc. */
2890         soft_mac_entry = priv->soft_mac_tbl;
2891
2892         /* 2. delete mc vague tcam entry. */
2893         addr[0] = 0x01;
2894         memset(&mac_key, 0x0, sizeof(mac_key));
2895         hns_dsaf_set_mac_key(dsaf_dev, &mac_key, 0x00, port, addr);
2896         entry_index = hns_dsaf_find_soft_mac_entry(dsaf_dev, &mac_key);
2897
2898         if (entry_index == DSAF_INVALID_ENTRY_IDX)
2899                 return;
2900
2901         /* config mc vague table */
2902         hns_dsaf_tcam_mc_cfg_vague(dsaf_dev, entry_index, &tbl_tcam_data_mc,
2903                                    &tbl_tcam_mask, &tbl_tcam_mcast);
2904         /* update soft management table. */
2905         soft_mac_entry += entry_index;
2906         soft_mac_entry->index = DSAF_INVALID_ENTRY_IDX;
2907 }
2908
2909 /* Reserve the last TCAM entry for promisc support */
2910 void hns_dsaf_set_promisc_tcam(struct dsaf_device *dsaf_dev,
2911                                u32 port, bool enable)
2912 {
2913         if (enable)
2914                 set_promisc_tcam_enable(dsaf_dev, port);
2915         else
2916                 set_promisc_tcam_disable(dsaf_dev, port);
2917 }
2918
2919 int hns_dsaf_wait_pkt_clean(struct dsaf_device *dsaf_dev, int port)
2920 {
2921         u32 val, val_tmp;
2922         int wait_cnt;
2923
2924         if (port >= DSAF_SERVICE_NW_NUM)
2925                 return 0;
2926
2927         wait_cnt = 0;
2928         while (wait_cnt++ < HNS_MAX_WAIT_CNT) {
2929                 val = dsaf_read_dev(dsaf_dev, DSAF_VOQ_IN_PKT_NUM_0_REG +
2930                         (port + DSAF_XGE_NUM) * 0x40);
2931                 val_tmp = dsaf_read_dev(dsaf_dev, DSAF_VOQ_OUT_PKT_NUM_0_REG +
2932                         (port + DSAF_XGE_NUM) * 0x40);
2933                 if (val == val_tmp)
2934                         break;
2935
2936                 usleep_range(100, 200);
2937         }
2938
2939         if (wait_cnt >= HNS_MAX_WAIT_CNT) {
2940                 dev_err(dsaf_dev->dev, "hns dsaf clean wait timeout(%u - %u).\n",
2941                         val, val_tmp);
2942                 return -EBUSY;
2943         }
2944
2945         return 0;
2946 }
2947
2948 /**
2949  * dsaf_probe - probo dsaf dev
2950  * @pdev: dasf platform device
2951  * retuen 0 - success , negative --fail
2952  */
2953 static int hns_dsaf_probe(struct platform_device *pdev)
2954 {
2955         struct dsaf_device *dsaf_dev;
2956         int ret;
2957
2958         dsaf_dev = hns_dsaf_alloc_dev(&pdev->dev, sizeof(struct dsaf_drv_priv));
2959         if (IS_ERR(dsaf_dev)) {
2960                 ret = PTR_ERR(dsaf_dev);
2961                 dev_err(&pdev->dev,
2962                         "dsaf_probe dsaf_alloc_dev failed, ret = %#x!\n", ret);
2963                 return ret;
2964         }
2965
2966         ret = hns_dsaf_get_cfg(dsaf_dev);
2967         if (ret)
2968                 goto free_dev;
2969
2970         ret = hns_dsaf_init(dsaf_dev);
2971         if (ret)
2972                 goto free_dev;
2973
2974         ret = hns_mac_init(dsaf_dev);
2975         if (ret)
2976                 goto uninit_dsaf;
2977
2978         ret = hns_ppe_init(dsaf_dev);
2979         if (ret)
2980                 goto uninit_mac;
2981
2982         ret = hns_dsaf_ae_init(dsaf_dev);
2983         if (ret)
2984                 goto uninit_ppe;
2985
2986         return 0;
2987
2988 uninit_ppe:
2989         hns_ppe_uninit(dsaf_dev);
2990
2991 uninit_mac:
2992         hns_mac_uninit(dsaf_dev);
2993
2994 uninit_dsaf:
2995         hns_dsaf_free(dsaf_dev);
2996
2997 free_dev:
2998         hns_dsaf_free_dev(dsaf_dev);
2999
3000         return ret;
3001 }
3002
3003 /**
3004  * dsaf_remove - remove dsaf dev
3005  * @pdev: dasf platform device
3006  */
3007 static int hns_dsaf_remove(struct platform_device *pdev)
3008 {
3009         struct dsaf_device *dsaf_dev = dev_get_drvdata(&pdev->dev);
3010
3011         hns_dsaf_ae_uninit(dsaf_dev);
3012
3013         hns_ppe_uninit(dsaf_dev);
3014
3015         hns_mac_uninit(dsaf_dev);
3016
3017         hns_dsaf_free(dsaf_dev);
3018
3019         hns_dsaf_free_dev(dsaf_dev);
3020
3021         return 0;
3022 }
3023
3024 static const struct of_device_id g_dsaf_match[] = {
3025         {.compatible = "hisilicon,hns-dsaf-v1"},
3026         {.compatible = "hisilicon,hns-dsaf-v2"},
3027         {}
3028 };
3029 MODULE_DEVICE_TABLE(of, g_dsaf_match);
3030
3031 static struct platform_driver g_dsaf_driver = {
3032         .probe = hns_dsaf_probe,
3033         .remove = hns_dsaf_remove,
3034         .driver = {
3035                 .name = DSAF_DRV_NAME,
3036                 .of_match_table = g_dsaf_match,
3037                 .acpi_match_table = hns_dsaf_acpi_match,
3038         },
3039 };
3040
3041 module_platform_driver(g_dsaf_driver);
3042
3043 /**
3044  * hns_dsaf_roce_reset - reset dsaf and roce
3045  * @dsaf_fwnode: Pointer to framework node for the dasf
3046  * @enable: false - request reset , true - drop reset
3047  * retuen 0 - success , negative -fail
3048  */
3049 int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset)
3050 {
3051         struct dsaf_device *dsaf_dev;
3052         struct platform_device *pdev;
3053         u32 mp;
3054         u32 sl;
3055         u32 credit;
3056         int i;
3057         const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
3058                 {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
3059                 {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0},
3060                 {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
3061                 {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0},
3062                 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
3063                 {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1},
3064                 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
3065                 {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1},
3066         };
3067         const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = {
3068                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
3069                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
3070                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
3071                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
3072                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0},
3073                 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1},
3074                 {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2},
3075                 {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3},
3076         };
3077
3078         /* find the platform device corresponding to fwnode */
3079         if (is_of_node(dsaf_fwnode)) {
3080                 pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
3081         } else if (is_acpi_device_node(dsaf_fwnode)) {
3082                 pdev = hns_dsaf_find_platform_device(dsaf_fwnode);
3083         } else {
3084                 pr_err("fwnode is neither OF or ACPI type\n");
3085                 return -EINVAL;
3086         }
3087
3088         /* check if we were a success in fetching pdev */
3089         if (!pdev) {
3090                 pr_err("couldn't find platform device for node\n");
3091                 return -ENODEV;
3092         }
3093
3094         /* retrieve the dsaf_device from the driver data */
3095         dsaf_dev = dev_get_drvdata(&pdev->dev);
3096         if (!dsaf_dev) {
3097                 dev_err(&pdev->dev, "dsaf_dev is NULL\n");
3098                 put_device(&pdev->dev);
3099                 return -ENODEV;
3100         }
3101
3102         /* now, make sure we are running on compatible SoC */
3103         if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
3104                 dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n",
3105                         dsaf_dev->ae_dev.name);
3106                 put_device(&pdev->dev);
3107                 return -ENODEV;
3108         }
3109
3110         /* do reset or de-reset according to the flag */
3111         if (!dereset) {
3112                 /* reset rocee-channels in dsaf and rocee */
3113                 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
3114                                                       false);
3115                 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false);
3116         } else {
3117                 /* configure dsaf tx roce correspond to port map and sl map */
3118                 mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
3119                 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
3120                         dsaf_set_field(mp, 7 << i * 3, i * 3,
3121                                        port_map[i][DSAF_ROCE_6PORT_MODE]);
3122                 dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
3123                 dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
3124
3125                 sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
3126                 for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
3127                         dsaf_set_field(sl, 3 << i * 2, i * 2,
3128                                        sl_map[i][DSAF_ROCE_6PORT_MODE]);
3129                 dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
3130
3131                 /* de-reset rocee-channels in dsaf and rocee */
3132                 dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK,
3133                                                       true);
3134                 msleep(SRST_TIME_INTERVAL);
3135                 dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true);
3136
3137                 /* enable dsaf channel rocee credit */
3138                 credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
3139                 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);
3140                 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
3141
3142                 dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);
3143                 dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
3144         }
3145
3146         put_device(&pdev->dev);
3147
3148         return 0;
3149 }
3150 EXPORT_SYMBOL(hns_dsaf_roce_reset);
3151
3152 MODULE_LICENSE("GPL");
3153 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
3154 MODULE_DESCRIPTION("HNS DSAF driver");
3155 MODULE_VERSION(DSAF_MOD_VERSION);