drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/delay.h>
  11 #include <linux/of_mdio.h>
  12 #include "hns_dsaf_main.h"
  13 #include "hns_dsaf_mac.h"
  14 #include "hns_dsaf_gmac.h"
  15
  16 static const struct mac_stats_string g_gmac_stats_string[] = {
  17         {"gmac_rx_octets_total_ok", MAC_STATS_FIELD_OFF(rx_good_bytes)},
  18         {"gmac_rx_octets_bad", MAC_STATS_FIELD_OFF(rx_bad_bytes)},
  19         {"gmac_rx_uc_pkts", MAC_STATS_FIELD_OFF(rx_uc_pkts)},
  20         {"gmac_rx_mc_pkts", MAC_STATS_FIELD_OFF(rx_mc_pkts)},
  21         {"gmac_rx_bc_pkts", MAC_STATS_FIELD_OFF(rx_bc_pkts)},
  22         {"gmac_rx_pkts_64octets", MAC_STATS_FIELD_OFF(rx_64bytes)},
  23         {"gmac_rx_pkts_65to127", MAC_STATS_FIELD_OFF(rx_65to127)},
  24         {"gmac_rx_pkts_128to255", MAC_STATS_FIELD_OFF(rx_128to255)},
  25         {"gmac_rx_pkts_256to511", MAC_STATS_FIELD_OFF(rx_256to511)},
  26         {"gmac_rx_pkts_512to1023", MAC_STATS_FIELD_OFF(rx_512to1023)},
  27         {"gmac_rx_pkts_1024to1518", MAC_STATS_FIELD_OFF(rx_1024to1518)},
  28         {"gmac_rx_pkts_1519tomax", MAC_STATS_FIELD_OFF(rx_1519tomax)},
  29         {"gmac_rx_fcs_errors", MAC_STATS_FIELD_OFF(rx_fcs_err)},
  30         {"gmac_rx_tagged", MAC_STATS_FIELD_OFF(rx_vlan_pkts)},
  31         {"gmac_rx_data_err", MAC_STATS_FIELD_OFF(rx_data_err)},
  32         {"gmac_rx_align_errors", MAC_STATS_FIELD_OFF(rx_align_err)},
  33         {"gmac_rx_long_errors", MAC_STATS_FIELD_OFF(rx_oversize)},
  34         {"gmac_rx_jabber_errors", MAC_STATS_FIELD_OFF(rx_jabber_err)},
  35         {"gmac_rx_pause_maccontrol", MAC_STATS_FIELD_OFF(rx_pfc_tc0)},
  36         {"gmac_rx_unknown_maccontrol", MAC_STATS_FIELD_OFF(rx_unknown_ctrl)},
  37         {"gmac_rx_very_long_err", MAC_STATS_FIELD_OFF(rx_long_err)},
  38         {"gmac_rx_runt_err", MAC_STATS_FIELD_OFF(rx_minto64)},
  39         {"gmac_rx_short_err", MAC_STATS_FIELD_OFF(rx_under_min)},
  40         {"gmac_rx_filt_pkt", MAC_STATS_FIELD_OFF(rx_filter_bytes)},
  41         {"gmac_rx_octets_total_filt", MAC_STATS_FIELD_OFF(rx_filter_pkts)},
  42         {"gmac_rx_overrun_cnt", MAC_STATS_FIELD_OFF(rx_fifo_overrun_err)},
  43         {"gmac_rx_length_err", MAC_STATS_FIELD_OFF(rx_len_err)},
  44         {"gmac_rx_fail_comma", MAC_STATS_FIELD_OFF(rx_comma_err)},
  45
  46         {"gmac_tx_octets_ok", MAC_STATS_FIELD_OFF(tx_good_bytes)},
  47         {"gmac_tx_octets_bad", MAC_STATS_FIELD_OFF(tx_bad_bytes)},
  48         {"gmac_tx_uc_pkts", MAC_STATS_FIELD_OFF(tx_uc_pkts)},
  49         {"gmac_tx_mc_pkts", MAC_STATS_FIELD_OFF(tx_mc_pkts)},
  50         {"gmac_tx_bc_pkts", MAC_STATS_FIELD_OFF(tx_bc_pkts)},
  51         {"gmac_tx_pkts_64octets", MAC_STATS_FIELD_OFF(tx_64bytes)},
  52         {"gmac_tx_pkts_65to127", MAC_STATS_FIELD_OFF(tx_65to127)},
  53         {"gmac_tx_pkts_128to255", MAC_STATS_FIELD_OFF(tx_128to255)},
  54         {"gmac_tx_pkts_256to511", MAC_STATS_FIELD_OFF(tx_256to511)},
  55         {"gmac_tx_pkts_512to1023", MAC_STATS_FIELD_OFF(tx_512to1023)},
  56         {"gmac_tx_pkts_1024to1518", MAC_STATS_FIELD_OFF(tx_1024to1518)},
  57         {"gmac_tx_pkts_1519tomax", MAC_STATS_FIELD_OFF(tx_1519tomax)},
  58         {"gmac_tx_excessive_length_drop", MAC_STATS_FIELD_OFF(tx_jabber_err)},
  59         {"gmac_tx_underrun", MAC_STATS_FIELD_OFF(tx_underrun_err)},
  60         {"gmac_tx_tagged", MAC_STATS_FIELD_OFF(tx_vlan)},
  61         {"gmac_tx_crc_error", MAC_STATS_FIELD_OFF(tx_crc_err)},
  62         {"gmac_tx_pause_frames", MAC_STATS_FIELD_OFF(tx_pfc_tc0)}
  63 };
  64
  65 static void hns_gmac_enable(void *mac_drv, enum mac_commom_mode mode)
  66 {
  67         struct mac_driver *drv = (struct mac_driver *)mac_drv;
  68
  69         /*enable GE rX/tX */
  70         if (mode == MAC_COMM_MODE_TX || mode == MAC_COMM_MODE_RX_AND_TX)
  71                 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 1);
  72
  73         if (mode == MAC_COMM_MODE_RX || mode == MAC_COMM_MODE_RX_AND_TX) {
  74                 /* enable rx pcs */
  75                 dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 0);
  76                 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 1);
  77         }
  78 }
  79
  80 static void hns_gmac_disable(void *mac_drv, enum mac_commom_mode mode)
  81 {
  82         struct mac_driver *drv = (struct mac_driver *)mac_drv;
  83
  84         /*disable GE rX/tX */
  85         if (mode == MAC_COMM_MODE_TX || mode == MAC_COMM_MODE_RX_AND_TX)
  86                 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 0);
  87
  88         if (mode == MAC_COMM_MODE_RX || mode == MAC_COMM_MODE_RX_AND_TX) {
  89                 /* disable rx pcs */
  90                 dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 1);
  91                 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 0);
  92         }
  93 }
  94
  95 /* hns_gmac_get_en - get port enable
  96  * @mac_drv:mac device
  97  * @rx:rx enable
  98  * @tx:tx enable
  99  */
 100 static void hns_gmac_get_en(void *mac_drv, u32 *rx, u32 *tx)
 101 {
 102         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 103         u32 porten;
 104
 105         porten = dsaf_read_dev(drv, GMAC_PORT_EN_REG);
 106         *tx = dsaf_get_bit(porten, GMAC_PORT_TX_EN_B);
 107         *rx = dsaf_get_bit(porten, GMAC_PORT_RX_EN_B);
 108 }
 109
 110 static void hns_gmac_free(void *mac_drv)
 111 {
 112         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 113         struct dsaf_device *dsaf_dev
 114                 = (struct dsaf_device *)dev_get_drvdata(drv->dev);
 115
 116         u32 mac_id = drv->mac_id;
 117
 118         dsaf_dev->misc_op->ge_srst(dsaf_dev, mac_id, 0);
 119 }
 120
 121 static void hns_gmac_set_tx_auto_pause_frames(void *mac_drv, u16 newval)
 122 {
 123         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 124
 125         dsaf_set_dev_field(drv, GMAC_FC_TX_TIMER_REG, GMAC_FC_TX_TIMER_M,
 126                            GMAC_FC_TX_TIMER_S, newval);
 127 }
 128
 129 static void hns_gmac_get_tx_auto_pause_frames(void *mac_drv, u16 *newval)
 130 {
 131         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 132
 133         *newval = dsaf_get_dev_field(drv, GMAC_FC_TX_TIMER_REG,
 134                                      GMAC_FC_TX_TIMER_M, GMAC_FC_TX_TIMER_S);
 135 }
 136
 137 static void hns_gmac_set_rx_auto_pause_frames(void *mac_drv, u32 newval)
 138 {
 139         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 140
 141         dsaf_set_dev_bit(drv, GMAC_PAUSE_EN_REG,
 142                          GMAC_PAUSE_EN_RX_FDFC_B, !!newval);
 143 }
 144
 145 static void hns_gmac_config_max_frame_length(void *mac_drv, u16 newval)
 146 {
 147         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 148
 149         dsaf_set_dev_field(drv, GMAC_MAX_FRM_SIZE_REG, GMAC_MAX_FRM_SIZE_M,
 150                            GMAC_MAX_FRM_SIZE_S, newval);
 151
 152         dsaf_set_dev_field(drv, GAMC_RX_MAX_FRAME, GMAC_MAX_FRM_SIZE_M,
 153                            GMAC_MAX_FRM_SIZE_S, newval);
 154 }
 155
 156 static void hns_gmac_config_an_mode(void *mac_drv, u8 newval)
 157 {
 158         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 159
 160         dsaf_set_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG,
 161                          GMAC_TX_AN_EN_B, !!newval);
 162 }
 163
 164 static void hns_gmac_tx_loop_pkt_dis(void *mac_drv)
 165 {
 166         u32 tx_loop_pkt_pri;
 167         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 168
 169         tx_loop_pkt_pri = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG);
 170         dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_EN_B, 1);
 171         dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_HIG_PRI_B, 0);
 172         dsaf_write_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG, tx_loop_pkt_pri);
 173 }
 174
 175 static void hns_gmac_set_duplex_type(void *mac_drv, u8 newval)
 176 {
 177         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 178
 179         dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG,
 180                          GMAC_DUPLEX_TYPE_B, !!newval);
 181 }
 182
 183 static void hns_gmac_get_duplex_type(void *mac_drv,
 184                                      enum hns_gmac_duplex_mdoe *duplex_mode)
 185 {
 186         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 187
 188         *duplex_mode = (enum hns_gmac_duplex_mdoe)dsaf_get_dev_bit(
 189                 drv, GMAC_DUPLEX_TYPE_REG, GMAC_DUPLEX_TYPE_B);
 190 }
 191
 192 static void hns_gmac_get_port_mode(void *mac_drv, enum hns_port_mode *port_mode)
 193 {
 194         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 195
 196         *port_mode = (enum hns_port_mode)dsaf_get_dev_field(
 197                 drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S);
 198 }
 199
 200 static void hns_gmac_port_mode_get(void *mac_drv,
 201                                    struct hns_gmac_port_mode_cfg *port_mode)
 202 {
 203         u32 tx_ctrl;
 204         u32 recv_ctrl;
 205         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 206
 207         port_mode->port_mode = (enum hns_port_mode)dsaf_get_dev_field(
 208                 drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S);
 209
 210         tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
 211         recv_ctrl = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG);
 212
 213         port_mode->max_frm_size =
 214                 dsaf_get_dev_field(drv, GMAC_MAX_FRM_SIZE_REG,
 215                                    GMAC_MAX_FRM_SIZE_M, GMAC_MAX_FRM_SIZE_S);
 216         port_mode->short_runts_thr =
 217                 dsaf_get_dev_field(drv, GMAC_SHORT_RUNTS_THR_REG,
 218                                    GMAC_SHORT_RUNTS_THR_M,
 219                                    GMAC_SHORT_RUNTS_THR_S);
 220
 221         port_mode->pad_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_PAD_EN_B);
 222         port_mode->crc_add = dsaf_get_bit(tx_ctrl, GMAC_TX_CRC_ADD_B);
 223         port_mode->an_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_AN_EN_B);
 224
 225         port_mode->runt_pkt_en =
 226                 dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_RUNT_PKT_EN_B);
 227         port_mode->strip_pad_en =
 228                 dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_STRIP_PAD_EN_B);
 229 }
 230
 231 static void hns_gmac_pause_frm_cfg(void *mac_drv, u32 rx_pause_en,
 232                                    u32 tx_pause_en)
 233 {
 234         u32 pause_en;
 235         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 236
 237         pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
 238         dsaf_set_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B, !!rx_pause_en);
 239         dsaf_set_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B, !!tx_pause_en);
 240         dsaf_write_dev(drv, GMAC_PAUSE_EN_REG, pause_en);
 241 }
 242
 243 static void hns_gmac_get_pausefrm_cfg(void *mac_drv, u32 *rx_pause_en,
 244                                       u32 *tx_pause_en)
 245 {
 246         u32 pause_en;
 247         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 248
 249         pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
 250
 251         *rx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B);
 252         *tx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B);
 253 }
 254
 255 static int hns_gmac_adjust_link(void *mac_drv, enum mac_speed speed,
 256                                 u32 full_duplex)
 257 {
 258         u32 tx_ctrl;
 259         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 260
 261         dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG,
 262                          GMAC_DUPLEX_TYPE_B, !!full_duplex);
 263
 264         switch (speed) {
 265         case MAC_SPEED_10:
 266                 dsaf_set_dev_field(
 267                         drv, GMAC_PORT_MODE_REG,
 268                         GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x6);
 269                 break;
 270         case MAC_SPEED_100:
 271                 dsaf_set_dev_field(
 272                         drv, GMAC_PORT_MODE_REG,
 273                         GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x7);
 274                 break;
 275         case MAC_SPEED_1000:
 276                 dsaf_set_dev_field(
 277                         drv, GMAC_PORT_MODE_REG,
 278                         GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x8);
 279                 break;
 280         default:
 281                 dev_err(drv->dev,
 282                         "hns_gmac_adjust_link fail, speed%d mac%d\n",
 283                         speed, drv->mac_id);
 284                 return -EINVAL;
 285         }
 286
 287         tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
 288         dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, 1);
 289         dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, 1);
 290         dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl);
 291
 292         dsaf_set_dev_bit(drv, GMAC_MODE_CHANGE_EN_REG,
 293                          GMAC_MODE_CHANGE_EB_B, 1);
 294
 295         return 0;
 296 }
 297
 298 static void hns_gmac_set_uc_match(void *mac_drv, u16 en)
 299 {
 300         struct mac_driver *drv = mac_drv;
 301
 302         dsaf_set_dev_bit(drv, GMAC_REC_FILT_CONTROL_REG,
 303                          GMAC_UC_MATCH_EN_B, !en);
 304         dsaf_set_dev_bit(drv, GMAC_STATION_ADDR_HIGH_2_REG,
 305                          GMAC_ADDR_EN_B, !en);
 306 }
 307
 308 static void hns_gmac_set_promisc(void *mac_drv, u8 en)
 309 {
 310         struct mac_driver *drv = mac_drv;
 311
 312         if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG)
 313                 hns_gmac_set_uc_match(mac_drv, en);
 314 }
 315
 316 static void hns_gmac_init(void *mac_drv)
 317 {
 318         u32 port;
 319         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 320         struct dsaf_device *dsaf_dev
 321                 = (struct dsaf_device *)dev_get_drvdata(drv->dev);
 322
 323         port = drv->mac_id;
 324
 325         dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 0);
 326         mdelay(10);
 327         dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 1);
 328         mdelay(10);
 329         hns_gmac_disable(mac_drv, MAC_COMM_MODE_RX_AND_TX);
 330         hns_gmac_tx_loop_pkt_dis(mac_drv);
 331         if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG)
 332                 hns_gmac_set_uc_match(mac_drv, 0);
 333 }
 334
 335 void hns_gmac_update_stats(void *mac_drv)
 336 {
 337         struct mac_hw_stats *hw_stats = NULL;
 338         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 339
 340         hw_stats = &drv->mac_cb->hw_stats;
 341
 342         /* RX */
 343         hw_stats->rx_good_bytes
 344                 += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG);
 345         hw_stats->rx_bad_bytes
 346                 += dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG);
 347         hw_stats->rx_uc_pkts += dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG);
 348         hw_stats->rx_mc_pkts += dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG);
 349         hw_stats->rx_bc_pkts += dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG);
 350         hw_stats->rx_64bytes
 351                 += dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG);
 352         hw_stats->rx_65to127
 353                 += dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG);
 354         hw_stats->rx_128to255
 355                 += dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG);
 356         hw_stats->rx_256to511
 357                 += dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG);
 358         hw_stats->rx_512to1023
 359                 += dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG);
 360         hw_stats->rx_1024to1518
 361                 += dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG);
 362         hw_stats->rx_1519tomax
 363                 += dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG);
 364         hw_stats->rx_fcs_err += dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG);
 365         hw_stats->rx_vlan_pkts += dsaf_read_dev(drv, GMAC_RX_TAGGED_REG);
 366         hw_stats->rx_data_err += dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG);
 367         hw_stats->rx_align_err
 368                 += dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG);
 369         hw_stats->rx_oversize
 370                 += dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG);
 371         hw_stats->rx_jabber_err
 372                 += dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG);
 373         hw_stats->rx_pfc_tc0
 374                 += dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG);
 375         hw_stats->rx_unknown_ctrl
 376                 += dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG);
 377         hw_stats->rx_long_err
 378                 += dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG);
 379         hw_stats->rx_minto64
 380                 += dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG);
 381         hw_stats->rx_under_min
 382                 += dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG);
 383         hw_stats->rx_filter_pkts
 384                 += dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG);
 385         hw_stats->rx_filter_bytes
 386                 += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG);
 387         hw_stats->rx_fifo_overrun_err
 388                 += dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG);
 389         hw_stats->rx_len_err
 390                 += dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG);
 391         hw_stats->rx_comma_err
 392                 += dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG);
 393
 394         /* TX */
 395         hw_stats->tx_good_bytes
 396                 += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG);
 397         hw_stats->tx_bad_bytes
 398                 += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG);
 399         hw_stats->tx_uc_pkts += dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG);
 400         hw_stats->tx_mc_pkts += dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG);
 401         hw_stats->tx_bc_pkts += dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG);
 402         hw_stats->tx_64bytes
 403                 += dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG);
 404         hw_stats->tx_65to127
 405                 += dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG);
 406         hw_stats->tx_128to255
 407                 += dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG);
 408         hw_stats->tx_256to511
 409                 += dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG);
 410         hw_stats->tx_512to1023
 411                 += dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG);
 412         hw_stats->tx_1024to1518
 413                 += dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG);
 414         hw_stats->tx_1519tomax
 415                 += dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG);
 416         hw_stats->tx_jabber_err
 417                 += dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG);
 418         hw_stats->tx_underrun_err
 419                 += dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG);
 420         hw_stats->tx_vlan += dsaf_read_dev(drv, GMAC_TX_TAGGED_REG);
 421         hw_stats->tx_crc_err += dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG);
 422         hw_stats->tx_pfc_tc0
 423                 += dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG);
 424 }
 425
 426 static void hns_gmac_set_mac_addr(void *mac_drv, char *mac_addr)
 427 {
 428         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 429
 430         u32 high_val = mac_addr[1] | (mac_addr[0] << 8);
 431
 432         u32 low_val = mac_addr[5] | (mac_addr[4] << 8)
 433                 | (mac_addr[3] << 16) | (mac_addr[2] << 24);
 434
 435         u32 val = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG);
 436         u32 sta_addr_en = dsaf_get_bit(val, GMAC_ADDR_EN_B);
 437
 438         dsaf_write_dev(drv, GMAC_STATION_ADDR_LOW_2_REG, low_val);
 439         dsaf_write_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG,
 440                        high_val | (sta_addr_en << GMAC_ADDR_EN_B));
 441 }
 442
 443 static int hns_gmac_config_loopback(void *mac_drv, enum hnae_loop loop_mode,
 444                                     u8 enable)
 445 {
 446         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 447
 448         switch (loop_mode) {
 449         case MAC_INTERNALLOOP_MAC:
 450                 dsaf_set_dev_bit(drv, GMAC_LOOP_REG, GMAC_LP_REG_CF2MI_LP_EN_B,
 451                                  !!enable);
 452                 break;
 453         default:
 454                 dev_err(drv->dev, "loop_mode error\n");
 455                 return -EINVAL;
 456         }
 457
 458         return 0;
 459 }
 460
 461 static void hns_gmac_config_pad_and_crc(void *mac_drv, u8 newval)
 462 {
 463         u32 tx_ctrl;
 464         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 465
 466         tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
 467         dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, !!newval);
 468         dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, !!newval);
 469         dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl);
 470 }
 471
 472 static void hns_gmac_get_id(void *mac_drv, u8 *mac_id)
 473 {
 474         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 475
 476         *mac_id = drv->mac_id;
 477 }
 478
 479 static void hns_gmac_get_info(void *mac_drv, struct mac_info *mac_info)
 480 {
 481         enum hns_gmac_duplex_mdoe duplex;
 482         enum hns_port_mode speed;
 483         u32 rx_pause;
 484         u32 tx_pause;
 485         u32 rx;
 486         u32 tx;
 487         u16 fc_tx_timer;
 488         struct hns_gmac_port_mode_cfg port_mode = { GMAC_10M_MII, 0 };
 489
 490         hns_gmac_port_mode_get(mac_drv, &port_mode);
 491         mac_info->pad_and_crc_en = port_mode.crc_add && port_mode.pad_enable;
 492         mac_info->auto_neg = port_mode.an_enable;
 493
 494         hns_gmac_get_tx_auto_pause_frames(mac_drv, &fc_tx_timer);
 495         mac_info->tx_pause_time = fc_tx_timer;
 496
 497         hns_gmac_get_en(mac_drv, &rx, &tx);
 498         mac_info->port_en = rx && tx;
 499
 500         hns_gmac_get_duplex_type(mac_drv, &duplex);
 501         mac_info->duplex = duplex;
 502
 503         hns_gmac_get_port_mode(mac_drv, &speed);
 504         switch (speed) {
 505         case GMAC_10M_SGMII:
 506                 mac_info->speed = MAC_SPEED_10;
 507                 break;
 508         case GMAC_100M_SGMII:
 509                 mac_info->speed = MAC_SPEED_100;
 510                 break;
 511         case GMAC_1000M_SGMII:
 512                 mac_info->speed = MAC_SPEED_1000;
 513                 break;
 514         default:
 515                 mac_info->speed = 0;
 516                 break;
 517         }
 518
 519         hns_gmac_get_pausefrm_cfg(mac_drv, &rx_pause, &tx_pause);
 520         mac_info->rx_pause_en = rx_pause;
 521         mac_info->tx_pause_en = tx_pause;
 522 }
 523
 524 static void hns_gmac_autoneg_stat(void *mac_drv, u32 *enable)
 525 {
 526         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 527
 528         *enable = dsaf_get_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG,
 529                                    GMAC_TX_AN_EN_B);
 530 }
 531
 532 static void hns_gmac_get_link_status(void *mac_drv, u32 *link_stat)
 533 {
 534         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 535
 536         *link_stat = dsaf_get_dev_bit(drv, GMAC_AN_NEG_STATE_REG,
 537                                       GMAC_AN_NEG_STAT_RX_SYNC_OK_B);
 538 }
 539
 540 static void hns_gmac_get_regs(void *mac_drv, void *data)
 541 {
 542         u32 *regs = data;
 543         int i;
 544         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 545
 546         /* base config registers */
 547         regs[0] = dsaf_read_dev(drv, GMAC_DUPLEX_TYPE_REG);
 548         regs[1] = dsaf_read_dev(drv, GMAC_FD_FC_TYPE_REG);
 549         regs[2] = dsaf_read_dev(drv, GMAC_FC_TX_TIMER_REG);
 550         regs[3] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_LOW_REG);
 551         regs[4] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_HIGH_REG);
 552         regs[5] = dsaf_read_dev(drv, GMAC_IPG_TX_TIMER_REG);
 553         regs[6] = dsaf_read_dev(drv, GMAC_PAUSE_THR_REG);
 554         regs[7] = dsaf_read_dev(drv, GMAC_MAX_FRM_SIZE_REG);
 555         regs[8] = dsaf_read_dev(drv, GMAC_PORT_MODE_REG);
 556         regs[9] = dsaf_read_dev(drv, GMAC_PORT_EN_REG);
 557         regs[10] = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
 558         regs[11] = dsaf_read_dev(drv, GMAC_SHORT_RUNTS_THR_REG);
 559         regs[12] = dsaf_read_dev(drv, GMAC_AN_NEG_STATE_REG);
 560         regs[13] = dsaf_read_dev(drv, GMAC_TX_LOCAL_PAGE_REG);
 561         regs[14] = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
 562         regs[15] = dsaf_read_dev(drv, GMAC_REC_FILT_CONTROL_REG);
 563         regs[16] = dsaf_read_dev(drv, GMAC_PTP_CONFIG_REG);
 564
 565         /* rx static registers */
 566         regs[17] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG);
 567         regs[18] = dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG);
 568         regs[19] = dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG);
 569         regs[20] = dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG);
 570         regs[21] = dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG);
 571         regs[22] = dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG);
 572         regs[23] = dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG);
 573         regs[24] = dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG);
 574         regs[25] = dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG);
 575         regs[26] = dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG);
 576         regs[27] = dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG);
 577         regs[28] = dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG);
 578         regs[29] = dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG);
 579         regs[30] = dsaf_read_dev(drv, GMAC_RX_TAGGED_REG);
 580         regs[31] = dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG);
 581         regs[32] = dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG);
 582         regs[33] = dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG);
 583         regs[34] = dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG);
 584         regs[35] = dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG);
 585         regs[36] = dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG);
 586         regs[37] = dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG);
 587         regs[38] = dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG);
 588         regs[39] = dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG);
 589         regs[40] = dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG);
 590         regs[41] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG);
 591
 592         /* tx static registers */
 593         regs[42] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG);
 594         regs[43] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG);
 595         regs[44] = dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG);
 596         regs[45] = dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG);
 597         regs[46] = dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG);
 598         regs[47] = dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG);
 599         regs[48] = dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG);
 600         regs[49] = dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG);
 601         regs[50] = dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG);
 602         regs[51] = dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG);
 603         regs[52] = dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG);
 604         regs[53] = dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG);
 605         regs[54] = dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG);
 606         regs[55] = dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG);
 607         regs[56] = dsaf_read_dev(drv, GMAC_TX_TAGGED_REG);
 608         regs[57] = dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG);
 609         regs[58] = dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG);
 610
 611         regs[59] = dsaf_read_dev(drv, GAMC_RX_MAX_FRAME);
 612         regs[60] = dsaf_read_dev(drv, GMAC_LINE_LOOP_BACK_REG);
 613         regs[61] = dsaf_read_dev(drv, GMAC_CF_CRC_STRIP_REG);
 614         regs[62] = dsaf_read_dev(drv, GMAC_MODE_CHANGE_EN_REG);
 615         regs[63] = dsaf_read_dev(drv, GMAC_SIXTEEN_BIT_CNTR_REG);
 616         regs[64] = dsaf_read_dev(drv, GMAC_LD_LINK_COUNTER_REG);
 617         regs[65] = dsaf_read_dev(drv, GMAC_LOOP_REG);
 618         regs[66] = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG);
 619         regs[67] = dsaf_read_dev(drv, GMAC_VLAN_CODE_REG);
 620         regs[68] = dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG);
 621         regs[69] = dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG);
 622         regs[70] = dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG);
 623
 624         regs[71] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_0_REG);
 625         regs[72] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_0_REG);
 626         regs[73] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_1_REG);
 627         regs[74] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_1_REG);
 628         regs[75] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_2_REG);
 629         regs[76] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG);
 630         regs[77] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_3_REG);
 631         regs[78] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_3_REG);
 632         regs[79] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_4_REG);
 633         regs[80] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_4_REG);
 634         regs[81] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_5_REG);
 635         regs[82] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_5_REG);
 636         regs[83] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_0_REG);
 637         regs[84] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_0_REG);
 638         regs[85] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_1_REG);
 639         regs[86] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_1_REG);
 640         regs[87] = dsaf_read_dev(drv, GMAC_MAC_SKIP_LEN_REG);
 641         regs[88] = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG);
 642
 643         /* mark end of mac regs */
 644         for (i = 89; i < 96; i++)
 645                 regs[i] = 0xaaaaaaaa;
 646 }
 647
 648 static void hns_gmac_get_stats(void *mac_drv, u64 *data)
 649 {
 650         u32 i;
 651         u64 *buf = data;
 652         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 653         struct mac_hw_stats *hw_stats = NULL;
 654
 655         hw_stats = &drv->mac_cb->hw_stats;
 656
 657         for (i = 0; i < ARRAY_SIZE(g_gmac_stats_string); i++) {
 658                 buf[i] = DSAF_STATS_READ(hw_stats,
 659                         g_gmac_stats_string[i].offset);
 660         }
 661 }
 662
 663 static void hns_gmac_get_strings(u32 stringset, u8 *data)
 664 {
 665         char *buff = (char *)data;
 666         u32 i;
 667
 668         if (stringset != ETH_SS_STATS)
 669                 return;
 670
 671         for (i = 0; i < ARRAY_SIZE(g_gmac_stats_string); i++) {
 672                 snprintf(buff, ETH_GSTRING_LEN, "%s",
 673                          g_gmac_stats_string[i].desc);
 674                 buff = buff + ETH_GSTRING_LEN;
 675         }
 676 }
 677
 678 static int hns_gmac_get_sset_count(int stringset)
 679 {
 680         if (stringset == ETH_SS_STATS)
 681                 return ARRAY_SIZE(g_gmac_stats_string);
 682
 683         return 0;
 684 }
 685
 686 static int hns_gmac_get_regs_count(void)
 687 {
 688         return ETH_GMAC_DUMP_NUM;
 689 }
 690
 691 void *hns_gmac_config(struct hns_mac_cb *mac_cb, struct mac_params *mac_param)
 692 {
 693         struct mac_driver *mac_drv;
 694
 695         mac_drv = devm_kzalloc(mac_cb->dev, sizeof(*mac_drv), GFP_KERNEL);
 696         if (!mac_drv)
 697                 return NULL;
 698
 699         mac_drv->mac_init = hns_gmac_init;
 700         mac_drv->mac_enable = hns_gmac_enable;
 701         mac_drv->mac_disable = hns_gmac_disable;
 702         mac_drv->mac_free = hns_gmac_free;
 703         mac_drv->adjust_link = hns_gmac_adjust_link;
 704         mac_drv->set_tx_auto_pause_frames = hns_gmac_set_tx_auto_pause_frames;
 705         mac_drv->config_max_frame_length = hns_gmac_config_max_frame_length;
 706         mac_drv->mac_pausefrm_cfg = hns_gmac_pause_frm_cfg;
 707
 708         mac_drv->mac_id = mac_param->mac_id;
 709         mac_drv->mac_mode = mac_param->mac_mode;
 710         mac_drv->io_base = mac_param->vaddr;
 711         mac_drv->dev = mac_param->dev;
 712         mac_drv->mac_cb = mac_cb;
 713
 714         mac_drv->set_mac_addr = hns_gmac_set_mac_addr;
 715         mac_drv->set_an_mode = hns_gmac_config_an_mode;
 716         mac_drv->config_loopback = hns_gmac_config_loopback;
 717         mac_drv->config_pad_and_crc = hns_gmac_config_pad_and_crc;
 718         mac_drv->config_half_duplex = hns_gmac_set_duplex_type;
 719         mac_drv->set_rx_ignore_pause_frames = hns_gmac_set_rx_auto_pause_frames;
 720         mac_drv->mac_get_id = hns_gmac_get_id;
 721         mac_drv->get_info = hns_gmac_get_info;
 722         mac_drv->autoneg_stat = hns_gmac_autoneg_stat;
 723         mac_drv->get_pause_enable = hns_gmac_get_pausefrm_cfg;
 724         mac_drv->get_link_status = hns_gmac_get_link_status;
 725         mac_drv->get_regs = hns_gmac_get_regs;
 726         mac_drv->get_regs_count = hns_gmac_get_regs_count;
 727         mac_drv->get_ethtool_stats = hns_gmac_get_stats;
 728         mac_drv->get_sset_count = hns_gmac_get_sset_count;
 729         mac_drv->get_strings = hns_gmac_get_strings;
 730         mac_drv->update_stats = hns_gmac_update_stats;
 731         mac_drv->set_promiscuous = hns_gmac_set_promisc;
 732
 733         return (void *)mac_drv;
 734 }