drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c

   1 /*
   2  * Copyright (c) 2014-2015 Hisilicon Limited.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #include <linux/delay.h>
  11 #include <linux/of_mdio.h>
  12 #include "hns_dsaf_main.h"
  13 #include "hns_dsaf_mac.h"
  14 #include "hns_dsaf_gmac.h"
  15
  16 static const struct mac_stats_string g_gmac_stats_string[] = {
  17         {"gmac_rx_octets_total_ok", MAC_STATS_FIELD_OFF(rx_good_bytes)},
  18         {"gmac_rx_octets_bad", MAC_STATS_FIELD_OFF(rx_bad_bytes)},
  19         {"gmac_rx_uc_pkts", MAC_STATS_FIELD_OFF(rx_uc_pkts)},
  20         {"gmac_rx_mc_pkts", MAC_STATS_FIELD_OFF(rx_mc_pkts)},
  21         {"gmac_rx_bc_pkts", MAC_STATS_FIELD_OFF(rx_bc_pkts)},
  22         {"gmac_rx_pkts_64octets", MAC_STATS_FIELD_OFF(rx_64bytes)},
  23         {"gmac_rx_pkts_65to127", MAC_STATS_FIELD_OFF(rx_65to127)},
  24         {"gmac_rx_pkts_128to255", MAC_STATS_FIELD_OFF(rx_128to255)},
  25         {"gmac_rx_pkts_256to511", MAC_STATS_FIELD_OFF(rx_256to511)},
  26         {"gmac_rx_pkts_512to1023", MAC_STATS_FIELD_OFF(rx_512to1023)},
  27         {"gmac_rx_pkts_1024to1518", MAC_STATS_FIELD_OFF(rx_1024to1518)},
  28         {"gmac_rx_pkts_1519tomax", MAC_STATS_FIELD_OFF(rx_1519tomax)},
  29         {"gmac_rx_fcs_errors", MAC_STATS_FIELD_OFF(rx_fcs_err)},
  30         {"gmac_rx_tagged", MAC_STATS_FIELD_OFF(rx_vlan_pkts)},
  31         {"gmac_rx_data_err", MAC_STATS_FIELD_OFF(rx_data_err)},
  32         {"gmac_rx_align_errors", MAC_STATS_FIELD_OFF(rx_align_err)},
  33         {"gmac_rx_long_errors", MAC_STATS_FIELD_OFF(rx_oversize)},
  34         {"gmac_rx_jabber_errors", MAC_STATS_FIELD_OFF(rx_jabber_err)},
  35         {"gmac_rx_pause_maccontrol", MAC_STATS_FIELD_OFF(rx_pfc_tc0)},
  36         {"gmac_rx_unknown_maccontrol", MAC_STATS_FIELD_OFF(rx_unknown_ctrl)},
  37         {"gmac_rx_very_long_err", MAC_STATS_FIELD_OFF(rx_long_err)},
  38         {"gmac_rx_runt_err", MAC_STATS_FIELD_OFF(rx_minto64)},
  39         {"gmac_rx_short_err", MAC_STATS_FIELD_OFF(rx_under_min)},
  40         {"gmac_rx_filt_pkt", MAC_STATS_FIELD_OFF(rx_filter_pkts)},
  41         {"gmac_rx_octets_total_filt", MAC_STATS_FIELD_OFF(rx_filter_bytes)},
  42         {"gmac_rx_overrun_cnt", MAC_STATS_FIELD_OFF(rx_fifo_overrun_err)},
  43         {"gmac_rx_length_err", MAC_STATS_FIELD_OFF(rx_len_err)},
  44         {"gmac_rx_fail_comma", MAC_STATS_FIELD_OFF(rx_comma_err)},
  45
  46         {"gmac_tx_octets_ok", MAC_STATS_FIELD_OFF(tx_good_bytes)},
  47         {"gmac_tx_octets_bad", MAC_STATS_FIELD_OFF(tx_bad_bytes)},
  48         {"gmac_tx_uc_pkts", MAC_STATS_FIELD_OFF(tx_uc_pkts)},
  49         {"gmac_tx_mc_pkts", MAC_STATS_FIELD_OFF(tx_mc_pkts)},
  50         {"gmac_tx_bc_pkts", MAC_STATS_FIELD_OFF(tx_bc_pkts)},
  51         {"gmac_tx_pkts_64octets", MAC_STATS_FIELD_OFF(tx_64bytes)},
  52         {"gmac_tx_pkts_65to127", MAC_STATS_FIELD_OFF(tx_65to127)},
  53         {"gmac_tx_pkts_128to255", MAC_STATS_FIELD_OFF(tx_128to255)},
  54         {"gmac_tx_pkts_256to511", MAC_STATS_FIELD_OFF(tx_256to511)},
  55         {"gmac_tx_pkts_512to1023", MAC_STATS_FIELD_OFF(tx_512to1023)},
  56         {"gmac_tx_pkts_1024to1518", MAC_STATS_FIELD_OFF(tx_1024to1518)},
  57         {"gmac_tx_pkts_1519tomax", MAC_STATS_FIELD_OFF(tx_1519tomax)},
  58         {"gmac_tx_excessive_length_drop", MAC_STATS_FIELD_OFF(tx_jabber_err)},
  59         {"gmac_tx_underrun", MAC_STATS_FIELD_OFF(tx_underrun_err)},
  60         {"gmac_tx_tagged", MAC_STATS_FIELD_OFF(tx_vlan)},
  61         {"gmac_tx_crc_error", MAC_STATS_FIELD_OFF(tx_crc_err)},
  62         {"gmac_tx_pause_frames", MAC_STATS_FIELD_OFF(tx_pfc_tc0)}
  63 };
  64
  65 static void hns_gmac_enable(void *mac_drv, enum mac_commom_mode mode)
  66 {
  67         struct mac_driver *drv = (struct mac_driver *)mac_drv;
  68
  69         /*enable GE rX/tX */
  70         if (mode == MAC_COMM_MODE_TX || mode == MAC_COMM_MODE_RX_AND_TX)
  71                 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 1);
  72
  73         if (mode == MAC_COMM_MODE_RX || mode == MAC_COMM_MODE_RX_AND_TX) {
  74                 /* enable rx pcs */
  75                 dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 0);
  76                 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 1);
  77         }
  78 }
  79
  80 static void hns_gmac_disable(void *mac_drv, enum mac_commom_mode mode)
  81 {
  82         struct mac_driver *drv = (struct mac_driver *)mac_drv;
  83
  84         /*disable GE rX/tX */
  85         if (mode == MAC_COMM_MODE_TX || mode == MAC_COMM_MODE_RX_AND_TX)
  86                 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 0);
  87
  88         if (mode == MAC_COMM_MODE_RX || mode == MAC_COMM_MODE_RX_AND_TX) {
  89                 /* disable rx pcs */
  90                 dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 1);
  91                 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 0);
  92         }
  93 }
  94
  95 /* hns_gmac_get_en - get port enable
  96  * @mac_drv:mac device
  97  * @rx:rx enable
  98  * @tx:tx enable
  99  */
 100 static void hns_gmac_get_en(void *mac_drv, u32 *rx, u32 *tx)
 101 {
 102         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 103         u32 porten;
 104
 105         porten = dsaf_read_dev(drv, GMAC_PORT_EN_REG);
 106         *tx = dsaf_get_bit(porten, GMAC_PORT_TX_EN_B);
 107         *rx = dsaf_get_bit(porten, GMAC_PORT_RX_EN_B);
 108 }
 109
 110 static void hns_gmac_free(void *mac_drv)
 111 {
 112         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 113         struct dsaf_device *dsaf_dev
 114                 = (struct dsaf_device *)dev_get_drvdata(drv->dev);
 115
 116         u32 mac_id = drv->mac_id;
 117
 118         dsaf_dev->misc_op->ge_srst(dsaf_dev, mac_id, 0);
 119 }
 120
 121 static void hns_gmac_set_tx_auto_pause_frames(void *mac_drv, u16 newval)
 122 {
 123         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 124
 125         dsaf_set_dev_field(drv, GMAC_FC_TX_TIMER_REG, GMAC_FC_TX_TIMER_M,
 126                            GMAC_FC_TX_TIMER_S, newval);
 127 }
 128
 129 static void hns_gmac_get_tx_auto_pause_frames(void *mac_drv, u16 *newval)
 130 {
 131         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 132
 133         *newval = dsaf_get_dev_field(drv, GMAC_FC_TX_TIMER_REG,
 134                                      GMAC_FC_TX_TIMER_M, GMAC_FC_TX_TIMER_S);
 135 }
 136
 137 static void hns_gmac_set_rx_auto_pause_frames(void *mac_drv, u32 newval)
 138 {
 139         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 140
 141         dsaf_set_dev_bit(drv, GMAC_PAUSE_EN_REG,
 142                          GMAC_PAUSE_EN_RX_FDFC_B, !!newval);
 143 }
 144
 145 static void hns_gmac_config_max_frame_length(void *mac_drv, u16 newval)
 146 {
 147         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 148
 149         dsaf_set_dev_field(drv, GMAC_MAX_FRM_SIZE_REG, GMAC_MAX_FRM_SIZE_M,
 150                            GMAC_MAX_FRM_SIZE_S, newval);
 151
 152         dsaf_set_dev_field(drv, GAMC_RX_MAX_FRAME, GMAC_MAX_FRM_SIZE_M,
 153                            GMAC_MAX_FRM_SIZE_S, newval);
 154 }
 155
 156 static void hns_gmac_config_pad_and_crc(void *mac_drv, u8 newval)
 157 {
 158         u32 tx_ctrl;
 159         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 160
 161         tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
 162         dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, !!newval);
 163         dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, !!newval);
 164         dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl);
 165 }
 166
 167 static void hns_gmac_config_an_mode(void *mac_drv, u8 newval)
 168 {
 169         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 170
 171         dsaf_set_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG,
 172                          GMAC_TX_AN_EN_B, !!newval);
 173 }
 174
 175 static void hns_gmac_tx_loop_pkt_dis(void *mac_drv)
 176 {
 177         u32 tx_loop_pkt_pri;
 178         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 179
 180         tx_loop_pkt_pri = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG);
 181         dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_EN_B, 1);
 182         dsaf_set_bit(tx_loop_pkt_pri, GMAC_TX_LOOP_PKT_HIG_PRI_B, 0);
 183         dsaf_write_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG, tx_loop_pkt_pri);
 184 }
 185
 186 static void hns_gmac_set_duplex_type(void *mac_drv, u8 newval)
 187 {
 188         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 189
 190         dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG,
 191                          GMAC_DUPLEX_TYPE_B, !!newval);
 192 }
 193
 194 static void hns_gmac_get_duplex_type(void *mac_drv,
 195                                      enum hns_gmac_duplex_mdoe *duplex_mode)
 196 {
 197         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 198
 199         *duplex_mode = (enum hns_gmac_duplex_mdoe)dsaf_get_dev_bit(
 200                 drv, GMAC_DUPLEX_TYPE_REG, GMAC_DUPLEX_TYPE_B);
 201 }
 202
 203 static void hns_gmac_get_port_mode(void *mac_drv, enum hns_port_mode *port_mode)
 204 {
 205         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 206
 207         *port_mode = (enum hns_port_mode)dsaf_get_dev_field(
 208                 drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S);
 209 }
 210
 211 static void hns_gmac_port_mode_get(void *mac_drv,
 212                                    struct hns_gmac_port_mode_cfg *port_mode)
 213 {
 214         u32 tx_ctrl;
 215         u32 recv_ctrl;
 216         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 217
 218         port_mode->port_mode = (enum hns_port_mode)dsaf_get_dev_field(
 219                 drv, GMAC_PORT_MODE_REG, GMAC_PORT_MODE_M, GMAC_PORT_MODE_S);
 220
 221         tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
 222         recv_ctrl = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG);
 223
 224         port_mode->max_frm_size =
 225                 dsaf_get_dev_field(drv, GMAC_MAX_FRM_SIZE_REG,
 226                                    GMAC_MAX_FRM_SIZE_M, GMAC_MAX_FRM_SIZE_S);
 227         port_mode->short_runts_thr =
 228                 dsaf_get_dev_field(drv, GMAC_SHORT_RUNTS_THR_REG,
 229                                    GMAC_SHORT_RUNTS_THR_M,
 230                                    GMAC_SHORT_RUNTS_THR_S);
 231
 232         port_mode->pad_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_PAD_EN_B);
 233         port_mode->crc_add = dsaf_get_bit(tx_ctrl, GMAC_TX_CRC_ADD_B);
 234         port_mode->an_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_AN_EN_B);
 235
 236         port_mode->runt_pkt_en =
 237                 dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_RUNT_PKT_EN_B);
 238         port_mode->strip_pad_en =
 239                 dsaf_get_bit(recv_ctrl, GMAC_RECV_CTRL_STRIP_PAD_EN_B);
 240 }
 241
 242 static void hns_gmac_pause_frm_cfg(void *mac_drv, u32 rx_pause_en,
 243                                    u32 tx_pause_en)
 244 {
 245         u32 pause_en;
 246         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 247
 248         pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
 249         dsaf_set_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B, !!rx_pause_en);
 250         dsaf_set_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B, !!tx_pause_en);
 251         dsaf_write_dev(drv, GMAC_PAUSE_EN_REG, pause_en);
 252 }
 253
 254 static void hns_gmac_get_pausefrm_cfg(void *mac_drv, u32 *rx_pause_en,
 255                                       u32 *tx_pause_en)
 256 {
 257         u32 pause_en;
 258         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 259
 260         pause_en = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
 261
 262         *rx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_RX_FDFC_B);
 263         *tx_pause_en = dsaf_get_bit(pause_en, GMAC_PAUSE_EN_TX_FDFC_B);
 264 }
 265
 266 static bool hns_gmac_need_adjust_link(void *mac_drv, enum mac_speed speed,
 267                                       int duplex)
 268 {
 269         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 270         struct hns_mac_cb *mac_cb = drv->mac_cb;
 271
 272         return (mac_cb->speed != speed) ||
 273                 (mac_cb->half_duplex == duplex);
 274 }
 275
 276 static int hns_gmac_adjust_link(void *mac_drv, enum mac_speed speed,
 277                                 u32 full_duplex)
 278 {
 279         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 280
 281         dsaf_set_dev_bit(drv, GMAC_DUPLEX_TYPE_REG,
 282                          GMAC_DUPLEX_TYPE_B, !!full_duplex);
 283
 284         switch (speed) {
 285         case MAC_SPEED_10:
 286                 dsaf_set_dev_field(
 287                         drv, GMAC_PORT_MODE_REG,
 288                         GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x6);
 289                 break;
 290         case MAC_SPEED_100:
 291                 dsaf_set_dev_field(
 292                         drv, GMAC_PORT_MODE_REG,
 293                         GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x7);
 294                 break;
 295         case MAC_SPEED_1000:
 296                 dsaf_set_dev_field(
 297                         drv, GMAC_PORT_MODE_REG,
 298                         GMAC_PORT_MODE_M, GMAC_PORT_MODE_S, 0x8);
 299                 break;
 300         default:
 301                 dev_err(drv->dev,
 302                         "hns_gmac_adjust_link fail, speed%d mac%d\n",
 303                         speed, drv->mac_id);
 304                 return -EINVAL;
 305         }
 306
 307         return 0;
 308 }
 309
 310 static void hns_gmac_set_uc_match(void *mac_drv, u16 en)
 311 {
 312         struct mac_driver *drv = mac_drv;
 313
 314         dsaf_set_dev_bit(drv, GMAC_REC_FILT_CONTROL_REG,
 315                          GMAC_UC_MATCH_EN_B, !en);
 316         dsaf_set_dev_bit(drv, GMAC_STATION_ADDR_HIGH_2_REG,
 317                          GMAC_ADDR_EN_B, !en);
 318 }
 319
 320 static void hns_gmac_set_promisc(void *mac_drv, u8 en)
 321 {
 322         struct mac_driver *drv = mac_drv;
 323
 324         if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG)
 325                 hns_gmac_set_uc_match(mac_drv, en);
 326 }
 327
 328 int hns_gmac_wait_fifo_clean(void *mac_drv)
 329 {
 330         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 331         int wait_cnt;
 332         u32 val;
 333
 334         wait_cnt = 0;
 335         while (wait_cnt++ < HNS_MAX_WAIT_CNT) {
 336                 val = dsaf_read_dev(drv, GMAC_FIFO_STATE_REG);
 337                 /* bit5~bit0 is not send complete pkts */
 338                 if ((val & 0x3f) == 0)
 339                         break;
 340                 usleep_range(100, 200);
 341         }
 342
 343         if (wait_cnt >= HNS_MAX_WAIT_CNT) {
 344                 dev_err(drv->dev,
 345                         "hns ge %d fifo was not idle.\n", drv->mac_id);
 346                 return -EBUSY;
 347         }
 348
 349         return 0;
 350 }
 351
 352 static void hns_gmac_init(void *mac_drv)
 353 {
 354         u32 port;
 355         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 356         struct dsaf_device *dsaf_dev
 357                 = (struct dsaf_device *)dev_get_drvdata(drv->dev);
 358
 359         port = drv->mac_id;
 360
 361         dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 0);
 362         mdelay(10);
 363         dsaf_dev->misc_op->ge_srst(dsaf_dev, port, 1);
 364         mdelay(10);
 365         hns_gmac_disable(mac_drv, MAC_COMM_MODE_RX_AND_TX);
 366         hns_gmac_tx_loop_pkt_dis(mac_drv);
 367         if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG)
 368                 hns_gmac_set_uc_match(mac_drv, 0);
 369
 370         hns_gmac_config_pad_and_crc(mac_drv, 1);
 371
 372         dsaf_set_dev_bit(drv, GMAC_MODE_CHANGE_EN_REG,
 373                          GMAC_MODE_CHANGE_EB_B, 1);
 374
 375         /* reduce gmac tx water line to avoid gmac hang-up
 376          * in speed 100M and duplex half.
 377          */
 378         dsaf_set_dev_field(drv, GMAC_TX_WATER_LINE_REG, GMAC_TX_WATER_LINE_MASK,
 379                            GMAC_TX_WATER_LINE_SHIFT, 8);
 380 }
 381
 382 void hns_gmac_update_stats(void *mac_drv)
 383 {
 384         struct mac_hw_stats *hw_stats = NULL;
 385         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 386
 387         hw_stats = &drv->mac_cb->hw_stats;
 388
 389         /* RX */
 390         hw_stats->rx_good_bytes
 391                 += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG);
 392         hw_stats->rx_bad_bytes
 393                 += dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG);
 394         hw_stats->rx_uc_pkts += dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG);
 395         hw_stats->rx_mc_pkts += dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG);
 396         hw_stats->rx_bc_pkts += dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG);
 397         hw_stats->rx_64bytes
 398                 += dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG);
 399         hw_stats->rx_65to127
 400                 += dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG);
 401         hw_stats->rx_128to255
 402                 += dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG);
 403         hw_stats->rx_256to511
 404                 += dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG);
 405         hw_stats->rx_512to1023
 406                 += dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG);
 407         hw_stats->rx_1024to1518
 408                 += dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG);
 409         hw_stats->rx_1519tomax
 410                 += dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG);
 411         hw_stats->rx_fcs_err += dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG);
 412         hw_stats->rx_vlan_pkts += dsaf_read_dev(drv, GMAC_RX_TAGGED_REG);
 413         hw_stats->rx_data_err += dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG);
 414         hw_stats->rx_align_err
 415                 += dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG);
 416         hw_stats->rx_oversize
 417                 += dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG);
 418         hw_stats->rx_jabber_err
 419                 += dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG);
 420         hw_stats->rx_pfc_tc0
 421                 += dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG);
 422         hw_stats->rx_unknown_ctrl
 423                 += dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG);
 424         hw_stats->rx_long_err
 425                 += dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG);
 426         hw_stats->rx_minto64
 427                 += dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG);
 428         hw_stats->rx_under_min
 429                 += dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG);
 430         hw_stats->rx_filter_pkts
 431                 += dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG);
 432         hw_stats->rx_filter_bytes
 433                 += dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG);
 434         hw_stats->rx_fifo_overrun_err
 435                 += dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG);
 436         hw_stats->rx_len_err
 437                 += dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG);
 438         hw_stats->rx_comma_err
 439                 += dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG);
 440
 441         /* TX */
 442         hw_stats->tx_good_bytes
 443                 += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG);
 444         hw_stats->tx_bad_bytes
 445                 += dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG);
 446         hw_stats->tx_uc_pkts += dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG);
 447         hw_stats->tx_mc_pkts += dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG);
 448         hw_stats->tx_bc_pkts += dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG);
 449         hw_stats->tx_64bytes
 450                 += dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG);
 451         hw_stats->tx_65to127
 452                 += dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG);
 453         hw_stats->tx_128to255
 454                 += dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG);
 455         hw_stats->tx_256to511
 456                 += dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG);
 457         hw_stats->tx_512to1023
 458                 += dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG);
 459         hw_stats->tx_1024to1518
 460                 += dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG);
 461         hw_stats->tx_1519tomax
 462                 += dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG);
 463         hw_stats->tx_jabber_err
 464                 += dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG);
 465         hw_stats->tx_underrun_err
 466                 += dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG);
 467         hw_stats->tx_vlan += dsaf_read_dev(drv, GMAC_TX_TAGGED_REG);
 468         hw_stats->tx_crc_err += dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG);
 469         hw_stats->tx_pfc_tc0
 470                 += dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG);
 471 }
 472
 473 static void hns_gmac_set_mac_addr(void *mac_drv, char *mac_addr)
 474 {
 475         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 476
 477         u32 high_val = mac_addr[1] | (mac_addr[0] << 8);
 478
 479         u32 low_val = mac_addr[5] | (mac_addr[4] << 8)
 480                 | (mac_addr[3] << 16) | (mac_addr[2] << 24);
 481
 482         u32 val = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG);
 483         u32 sta_addr_en = dsaf_get_bit(val, GMAC_ADDR_EN_B);
 484
 485         dsaf_write_dev(drv, GMAC_STATION_ADDR_LOW_2_REG, low_val);
 486         dsaf_write_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG,
 487                        high_val | (sta_addr_en << GMAC_ADDR_EN_B));
 488 }
 489
 490 static int hns_gmac_config_loopback(void *mac_drv, enum hnae_loop loop_mode,
 491                                     u8 enable)
 492 {
 493         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 494
 495         switch (loop_mode) {
 496         case MAC_INTERNALLOOP_MAC:
 497                 dsaf_set_dev_bit(drv, GMAC_LOOP_REG, GMAC_LP_REG_CF2MI_LP_EN_B,
 498                                  !!enable);
 499                 break;
 500         default:
 501                 dev_err(drv->dev, "loop_mode error\n");
 502                 return -EINVAL;
 503         }
 504
 505         return 0;
 506 }
 507
 508 static void hns_gmac_get_info(void *mac_drv, struct mac_info *mac_info)
 509 {
 510         enum hns_gmac_duplex_mdoe duplex;
 511         enum hns_port_mode speed;
 512         u32 rx_pause;
 513         u32 tx_pause;
 514         u32 rx;
 515         u32 tx;
 516         u16 fc_tx_timer;
 517         struct hns_gmac_port_mode_cfg port_mode = { GMAC_10M_MII, 0 };
 518
 519         hns_gmac_port_mode_get(mac_drv, &port_mode);
 520         mac_info->pad_and_crc_en = port_mode.crc_add && port_mode.pad_enable;
 521         mac_info->auto_neg = port_mode.an_enable;
 522
 523         hns_gmac_get_tx_auto_pause_frames(mac_drv, &fc_tx_timer);
 524         mac_info->tx_pause_time = fc_tx_timer;
 525
 526         hns_gmac_get_en(mac_drv, &rx, &tx);
 527         mac_info->port_en = rx && tx;
 528
 529         hns_gmac_get_duplex_type(mac_drv, &duplex);
 530         mac_info->duplex = duplex;
 531
 532         hns_gmac_get_port_mode(mac_drv, &speed);
 533         switch (speed) {
 534         case GMAC_10M_SGMII:
 535                 mac_info->speed = MAC_SPEED_10;
 536                 break;
 537         case GMAC_100M_SGMII:
 538                 mac_info->speed = MAC_SPEED_100;
 539                 break;
 540         case GMAC_1000M_SGMII:
 541                 mac_info->speed = MAC_SPEED_1000;
 542                 break;
 543         default:
 544                 mac_info->speed = 0;
 545                 break;
 546         }
 547
 548         hns_gmac_get_pausefrm_cfg(mac_drv, &rx_pause, &tx_pause);
 549         mac_info->rx_pause_en = rx_pause;
 550         mac_info->tx_pause_en = tx_pause;
 551 }
 552
 553 static void hns_gmac_autoneg_stat(void *mac_drv, u32 *enable)
 554 {
 555         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 556
 557         *enable = dsaf_get_dev_bit(drv, GMAC_TRANSMIT_CONTROL_REG,
 558                                    GMAC_TX_AN_EN_B);
 559 }
 560
 561 static void hns_gmac_get_link_status(void *mac_drv, u32 *link_stat)
 562 {
 563         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 564
 565         *link_stat = dsaf_get_dev_bit(drv, GMAC_AN_NEG_STATE_REG,
 566                                       GMAC_AN_NEG_STAT_RX_SYNC_OK_B);
 567 }
 568
 569 static void hns_gmac_get_regs(void *mac_drv, void *data)
 570 {
 571         u32 *regs = data;
 572         int i;
 573         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 574
 575         /* base config registers */
 576         regs[0] = dsaf_read_dev(drv, GMAC_DUPLEX_TYPE_REG);
 577         regs[1] = dsaf_read_dev(drv, GMAC_FD_FC_TYPE_REG);
 578         regs[2] = dsaf_read_dev(drv, GMAC_FC_TX_TIMER_REG);
 579         regs[3] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_LOW_REG);
 580         regs[4] = dsaf_read_dev(drv, GMAC_FD_FC_ADDR_HIGH_REG);
 581         regs[5] = dsaf_read_dev(drv, GMAC_IPG_TX_TIMER_REG);
 582         regs[6] = dsaf_read_dev(drv, GMAC_PAUSE_THR_REG);
 583         regs[7] = dsaf_read_dev(drv, GMAC_MAX_FRM_SIZE_REG);
 584         regs[8] = dsaf_read_dev(drv, GMAC_PORT_MODE_REG);
 585         regs[9] = dsaf_read_dev(drv, GMAC_PORT_EN_REG);
 586         regs[10] = dsaf_read_dev(drv, GMAC_PAUSE_EN_REG);
 587         regs[11] = dsaf_read_dev(drv, GMAC_SHORT_RUNTS_THR_REG);
 588         regs[12] = dsaf_read_dev(drv, GMAC_AN_NEG_STATE_REG);
 589         regs[13] = dsaf_read_dev(drv, GMAC_TX_LOCAL_PAGE_REG);
 590         regs[14] = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG);
 591         regs[15] = dsaf_read_dev(drv, GMAC_REC_FILT_CONTROL_REG);
 592         regs[16] = dsaf_read_dev(drv, GMAC_PTP_CONFIG_REG);
 593
 594         /* rx static registers */
 595         regs[17] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_OK_REG);
 596         regs[18] = dsaf_read_dev(drv, GMAC_RX_OCTETS_BAD_REG);
 597         regs[19] = dsaf_read_dev(drv, GMAC_RX_UC_PKTS_REG);
 598         regs[20] = dsaf_read_dev(drv, GMAC_RX_MC_PKTS_REG);
 599         regs[21] = dsaf_read_dev(drv, GMAC_RX_BC_PKTS_REG);
 600         regs[22] = dsaf_read_dev(drv, GMAC_RX_PKTS_64OCTETS_REG);
 601         regs[23] = dsaf_read_dev(drv, GMAC_RX_PKTS_65TO127OCTETS_REG);
 602         regs[24] = dsaf_read_dev(drv, GMAC_RX_PKTS_128TO255OCTETS_REG);
 603         regs[25] = dsaf_read_dev(drv, GMAC_RX_PKTS_255TO511OCTETS_REG);
 604         regs[26] = dsaf_read_dev(drv, GMAC_RX_PKTS_512TO1023OCTETS_REG);
 605         regs[27] = dsaf_read_dev(drv, GMAC_RX_PKTS_1024TO1518OCTETS_REG);
 606         regs[28] = dsaf_read_dev(drv, GMAC_RX_PKTS_1519TOMAXOCTETS_REG);
 607         regs[29] = dsaf_read_dev(drv, GMAC_RX_FCS_ERRORS_REG);
 608         regs[30] = dsaf_read_dev(drv, GMAC_RX_TAGGED_REG);
 609         regs[31] = dsaf_read_dev(drv, GMAC_RX_DATA_ERR_REG);
 610         regs[32] = dsaf_read_dev(drv, GMAC_RX_ALIGN_ERRORS_REG);
 611         regs[33] = dsaf_read_dev(drv, GMAC_RX_LONG_ERRORS_REG);
 612         regs[34] = dsaf_read_dev(drv, GMAC_RX_JABBER_ERRORS_REG);
 613         regs[35] = dsaf_read_dev(drv, GMAC_RX_PAUSE_MACCTRL_FRAM_REG);
 614         regs[36] = dsaf_read_dev(drv, GMAC_RX_UNKNOWN_MACCTRL_FRAM_REG);
 615         regs[37] = dsaf_read_dev(drv, GMAC_RX_VERY_LONG_ERR_CNT_REG);
 616         regs[38] = dsaf_read_dev(drv, GMAC_RX_RUNT_ERR_CNT_REG);
 617         regs[39] = dsaf_read_dev(drv, GMAC_RX_SHORT_ERR_CNT_REG);
 618         regs[40] = dsaf_read_dev(drv, GMAC_RX_FILT_PKT_CNT_REG);
 619         regs[41] = dsaf_read_dev(drv, GMAC_RX_OCTETS_TOTAL_FILT_REG);
 620
 621         /* tx static registers */
 622         regs[42] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_OK_REG);
 623         regs[43] = dsaf_read_dev(drv, GMAC_OCTETS_TRANSMITTED_BAD_REG);
 624         regs[44] = dsaf_read_dev(drv, GMAC_TX_UC_PKTS_REG);
 625         regs[45] = dsaf_read_dev(drv, GMAC_TX_MC_PKTS_REG);
 626         regs[46] = dsaf_read_dev(drv, GMAC_TX_BC_PKTS_REG);
 627         regs[47] = dsaf_read_dev(drv, GMAC_TX_PKTS_64OCTETS_REG);
 628         regs[48] = dsaf_read_dev(drv, GMAC_TX_PKTS_65TO127OCTETS_REG);
 629         regs[49] = dsaf_read_dev(drv, GMAC_TX_PKTS_128TO255OCTETS_REG);
 630         regs[50] = dsaf_read_dev(drv, GMAC_TX_PKTS_255TO511OCTETS_REG);
 631         regs[51] = dsaf_read_dev(drv, GMAC_TX_PKTS_512TO1023OCTETS_REG);
 632         regs[52] = dsaf_read_dev(drv, GMAC_TX_PKTS_1024TO1518OCTETS_REG);
 633         regs[53] = dsaf_read_dev(drv, GMAC_TX_PKTS_1519TOMAXOCTETS_REG);
 634         regs[54] = dsaf_read_dev(drv, GMAC_TX_EXCESSIVE_LENGTH_DROP_REG);
 635         regs[55] = dsaf_read_dev(drv, GMAC_TX_UNDERRUN_REG);
 636         regs[56] = dsaf_read_dev(drv, GMAC_TX_TAGGED_REG);
 637         regs[57] = dsaf_read_dev(drv, GMAC_TX_CRC_ERROR_REG);
 638         regs[58] = dsaf_read_dev(drv, GMAC_TX_PAUSE_FRAMES_REG);
 639
 640         regs[59] = dsaf_read_dev(drv, GAMC_RX_MAX_FRAME);
 641         regs[60] = dsaf_read_dev(drv, GMAC_LINE_LOOP_BACK_REG);
 642         regs[61] = dsaf_read_dev(drv, GMAC_CF_CRC_STRIP_REG);
 643         regs[62] = dsaf_read_dev(drv, GMAC_MODE_CHANGE_EN_REG);
 644         regs[63] = dsaf_read_dev(drv, GMAC_SIXTEEN_BIT_CNTR_REG);
 645         regs[64] = dsaf_read_dev(drv, GMAC_LD_LINK_COUNTER_REG);
 646         regs[65] = dsaf_read_dev(drv, GMAC_LOOP_REG);
 647         regs[66] = dsaf_read_dev(drv, GMAC_RECV_CONTROL_REG);
 648         regs[67] = dsaf_read_dev(drv, GMAC_VLAN_CODE_REG);
 649         regs[68] = dsaf_read_dev(drv, GMAC_RX_OVERRUN_CNT_REG);
 650         regs[69] = dsaf_read_dev(drv, GMAC_RX_LENGTHFIELD_ERR_CNT_REG);
 651         regs[70] = dsaf_read_dev(drv, GMAC_RX_FAIL_COMMA_CNT_REG);
 652
 653         regs[71] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_0_REG);
 654         regs[72] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_0_REG);
 655         regs[73] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_1_REG);
 656         regs[74] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_1_REG);
 657         regs[75] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_2_REG);
 658         regs[76] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG);
 659         regs[77] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_3_REG);
 660         regs[78] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_3_REG);
 661         regs[79] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_4_REG);
 662         regs[80] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_4_REG);
 663         regs[81] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_5_REG);
 664         regs[82] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_5_REG);
 665         regs[83] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_0_REG);
 666         regs[84] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_0_REG);
 667         regs[85] = dsaf_read_dev(drv, GMAC_STATION_ADDR_LOW_MSK_1_REG);
 668         regs[86] = dsaf_read_dev(drv, GMAC_STATION_ADDR_HIGH_MSK_1_REG);
 669         regs[87] = dsaf_read_dev(drv, GMAC_MAC_SKIP_LEN_REG);
 670         regs[88] = dsaf_read_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG);
 671
 672         /* mark end of mac regs */
 673         for (i = 89; i < 96; i++)
 674                 regs[i] = 0xaaaaaaaa;
 675 }
 676
 677 static void hns_gmac_get_stats(void *mac_drv, u64 *data)
 678 {
 679         u32 i;
 680         u64 *buf = data;
 681         struct mac_driver *drv = (struct mac_driver *)mac_drv;
 682         struct mac_hw_stats *hw_stats = NULL;
 683
 684         hw_stats = &drv->mac_cb->hw_stats;
 685
 686         for (i = 0; i < ARRAY_SIZE(g_gmac_stats_string); i++) {
 687                 buf[i] = DSAF_STATS_READ(hw_stats,
 688                         g_gmac_stats_string[i].offset);
 689         }
 690 }
 691
 692 static void hns_gmac_get_strings(u32 stringset, u8 *data)
 693 {
 694         char *buff = (char *)data;
 695         u32 i;
 696
 697         if (stringset != ETH_SS_STATS)
 698                 return;
 699
 700         for (i = 0; i < ARRAY_SIZE(g_gmac_stats_string); i++) {
 701                 snprintf(buff, ETH_GSTRING_LEN, "%s",
 702                          g_gmac_stats_string[i].desc);
 703                 buff = buff + ETH_GSTRING_LEN;
 704         }
 705 }
 706
 707 static int hns_gmac_get_sset_count(int stringset)
 708 {
 709         if (stringset == ETH_SS_STATS)
 710                 return ARRAY_SIZE(g_gmac_stats_string);
 711
 712         return 0;
 713 }
 714
 715 static int hns_gmac_get_regs_count(void)
 716 {
 717         return ETH_GMAC_DUMP_NUM;
 718 }
 719
 720 void *hns_gmac_config(struct hns_mac_cb *mac_cb, struct mac_params *mac_param)
 721 {
 722         struct mac_driver *mac_drv;
 723
 724         mac_drv = devm_kzalloc(mac_cb->dev, sizeof(*mac_drv), GFP_KERNEL);
 725         if (!mac_drv)
 726                 return NULL;
 727
 728         mac_drv->mac_init = hns_gmac_init;
 729         mac_drv->mac_enable = hns_gmac_enable;
 730         mac_drv->mac_disable = hns_gmac_disable;
 731         mac_drv->mac_free = hns_gmac_free;
 732         mac_drv->adjust_link = hns_gmac_adjust_link;
 733         mac_drv->need_adjust_link = hns_gmac_need_adjust_link;
 734         mac_drv->set_tx_auto_pause_frames = hns_gmac_set_tx_auto_pause_frames;
 735         mac_drv->config_max_frame_length = hns_gmac_config_max_frame_length;
 736         mac_drv->mac_pausefrm_cfg = hns_gmac_pause_frm_cfg;
 737
 738         mac_drv->mac_id = mac_param->mac_id;
 739         mac_drv->mac_mode = mac_param->mac_mode;
 740         mac_drv->io_base = mac_param->vaddr;
 741         mac_drv->dev = mac_param->dev;
 742         mac_drv->mac_cb = mac_cb;
 743
 744         mac_drv->set_mac_addr = hns_gmac_set_mac_addr;
 745         mac_drv->set_an_mode = hns_gmac_config_an_mode;
 746         mac_drv->config_loopback = hns_gmac_config_loopback;
 747         mac_drv->config_pad_and_crc = hns_gmac_config_pad_and_crc;
 748         mac_drv->config_half_duplex = hns_gmac_set_duplex_type;
 749         mac_drv->set_rx_ignore_pause_frames = hns_gmac_set_rx_auto_pause_frames;
 750         mac_drv->get_info = hns_gmac_get_info;
 751         mac_drv->autoneg_stat = hns_gmac_autoneg_stat;
 752         mac_drv->get_pause_enable = hns_gmac_get_pausefrm_cfg;
 753         mac_drv->get_link_status = hns_gmac_get_link_status;
 754         mac_drv->get_regs = hns_gmac_get_regs;
 755         mac_drv->get_regs_count = hns_gmac_get_regs_count;
 756         mac_drv->get_ethtool_stats = hns_gmac_get_stats;
 757         mac_drv->get_sset_count = hns_gmac_get_sset_count;
 758         mac_drv->get_strings = hns_gmac_get_strings;
 759         mac_drv->update_stats = hns_gmac_update_stats;
 760         mac_drv->set_promiscuous = hns_gmac_set_promisc;
 761         mac_drv->wait_fifo_clean = hns_gmac_wait_fifo_clean;
 762
 763         return (void *)mac_drv;
 764 }