2 * QorIQ 10G MDIO Controller
4 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Authors: Andy Fleming <afleming@freescale.com>
7 * Timur Tabi <timur@freescale.com>
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/phy.h>
19 #include <linux/mdio.h>
20 #include <linux/of_address.h>
21 #include <linux/of_platform.h>
22 #include <linux/of_mdio.h>
24 /* Number of microseconds to wait for a register to respond */
27 struct tgec_mdio_controller {
29 __be32 mdio_stat; /* MDIO configuration and status */
30 __be32 mdio_ctl; /* MDIO control */
31 __be32 mdio_data; /* MDIO data */
32 __be32 mdio_addr; /* MDIO address */
35 #define MDIO_STAT_ENC BIT(6)
36 #define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
37 #define MDIO_STAT_BSY BIT(0)
38 #define MDIO_STAT_RD_ER BIT(1)
39 #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
40 #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
41 #define MDIO_CTL_PRE_DIS BIT(10)
42 #define MDIO_CTL_SCAN_EN BIT(11)
43 #define MDIO_CTL_POST_INC BIT(14)
44 #define MDIO_CTL_READ BIT(15)
46 #define MDIO_DATA(x) (x & 0xffff)
47 #define MDIO_DATA_BSY BIT(31)
49 struct mdio_fsl_priv {
50 struct tgec_mdio_controller __iomem *mdio_base;
51 bool is_little_endian;
55 static u32 xgmac_read32(void __iomem *regs,
56 bool is_little_endian)
59 return ioread32(regs);
61 return ioread32be(regs);
64 static void xgmac_write32(u32 value,
66 bool is_little_endian)
69 iowrite32(value, regs);
71 iowrite32be(value, regs);
75 * Wait until the MDIO bus is free
77 static int xgmac_wait_until_free(struct device *dev,
78 struct tgec_mdio_controller __iomem *regs,
79 bool is_little_endian)
83 /* Wait till the bus is free */
85 while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
86 MDIO_STAT_BSY) && timeout) {
92 dev_err(dev, "timeout waiting for bus to be free\n");
100 * Wait till the MDIO read or write operation is complete
102 static int xgmac_wait_until_done(struct device *dev,
103 struct tgec_mdio_controller __iomem *regs,
104 bool is_little_endian)
106 unsigned int timeout;
108 /* Wait till the MDIO write is complete */
110 while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
111 MDIO_STAT_BSY) && timeout) {
117 dev_err(dev, "timeout waiting for operation to complete\n");
125 * Write value to the PHY for this device to the register at regnum,waiting
126 * until the write is done before it returns. All PHY configuration has to be
127 * done through the TSEC1 MIIM regs.
129 static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
131 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
132 struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
134 u32 mdio_ctl, mdio_stat;
136 bool endian = priv->is_little_endian;
138 mdio_stat = xgmac_read32(®s->mdio_stat, endian);
139 if (regnum & MII_ADDR_C45) {
140 /* Clause 45 (ie 10G) */
141 dev_addr = (regnum >> 16) & 0x1f;
142 mdio_stat |= MDIO_STAT_ENC;
144 /* Clause 22 (ie 1G) */
145 dev_addr = regnum & 0x1f;
146 mdio_stat &= ~MDIO_STAT_ENC;
149 xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
151 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
155 /* Set the port and dev addr */
156 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
157 xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
159 /* Set the register address */
160 if (regnum & MII_ADDR_C45) {
161 xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
163 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
168 /* Write the value to the register */
169 xgmac_write32(MDIO_DATA(value), ®s->mdio_data, endian);
171 ret = xgmac_wait_until_done(&bus->dev, regs, endian);
179 * Reads from register regnum in the PHY for device dev, returning the value.
180 * Clears miimcom first. All PHY configuration has to be done through the
183 static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
185 struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
186 struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
192 bool endian = priv->is_little_endian;
194 mdio_stat = xgmac_read32(®s->mdio_stat, endian);
195 if (regnum & MII_ADDR_C45) {
196 dev_addr = (regnum >> 16) & 0x1f;
197 mdio_stat |= MDIO_STAT_ENC;
199 dev_addr = regnum & 0x1f;
200 mdio_stat &= ~MDIO_STAT_ENC;
203 xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
205 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
209 /* Set the Port and Device Addrs */
210 mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
211 xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
213 /* Set the register address */
214 if (regnum & MII_ADDR_C45) {
215 xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
217 ret = xgmac_wait_until_free(&bus->dev, regs, endian);
222 /* Initiate the read */
223 xgmac_write32(mdio_ctl | MDIO_CTL_READ, ®s->mdio_ctl, endian);
225 ret = xgmac_wait_until_done(&bus->dev, regs, endian);
229 /* Return all Fs if nothing was there */
230 if ((xgmac_read32(®s->mdio_stat, endian) & MDIO_STAT_RD_ER) &&
231 !priv->has_a011043) {
233 "Error while reading PHY%d reg at %d.%hhu\n",
234 phy_id, dev_addr, regnum);
238 value = xgmac_read32(®s->mdio_data, endian) & 0xffff;
239 dev_dbg(&bus->dev, "read %04x\n", value);
244 static int xgmac_mdio_probe(struct platform_device *pdev)
246 struct device_node *np = pdev->dev.of_node;
249 struct mdio_fsl_priv *priv;
252 ret = of_address_to_resource(np, 0, &res);
254 dev_err(&pdev->dev, "could not obtain address\n");
258 bus = mdiobus_alloc_size(sizeof(struct mdio_fsl_priv));
262 bus->name = "Freescale XGMAC MDIO Bus";
263 bus->read = xgmac_mdio_read;
264 bus->write = xgmac_mdio_write;
265 bus->parent = &pdev->dev;
266 snprintf(bus->id, MII_BUS_ID_SIZE, "%llx", (unsigned long long)res.start);
268 /* Set the PHY base address */
270 priv->mdio_base = of_iomap(np, 0);
271 if (!priv->mdio_base) {
276 priv->is_little_endian = of_property_read_bool(pdev->dev.of_node,
279 priv->has_a011043 = of_property_read_bool(pdev->dev.of_node,
280 "fsl,erratum-a011043");
282 ret = of_mdiobus_register(bus, np);
284 dev_err(&pdev->dev, "cannot register MDIO bus\n");
285 goto err_registration;
288 platform_set_drvdata(pdev, bus);
293 iounmap(priv->mdio_base);
301 static int xgmac_mdio_remove(struct platform_device *pdev)
303 struct mii_bus *bus = platform_get_drvdata(pdev);
305 mdiobus_unregister(bus);
312 static const struct of_device_id xgmac_mdio_match[] = {
314 .compatible = "fsl,fman-xmdio",
317 .compatible = "fsl,fman-memac-mdio",
321 MODULE_DEVICE_TABLE(of, xgmac_mdio_match);
323 static struct platform_driver xgmac_mdio_driver = {
325 .name = "fsl-fman_xmdio",
326 .of_match_table = xgmac_mdio_match,
328 .probe = xgmac_mdio_probe,
329 .remove = xgmac_mdio_remove,
332 module_platform_driver(xgmac_mdio_driver);
334 MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller");
335 MODULE_LICENSE("GPL v2");