1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/delay.h>
74 #include <linux/netdevice.h>
75 #include <linux/etherdevice.h>
76 #include <linux/skbuff.h>
77 #include <linux/if_vlan.h>
78 #include <linux/spinlock.h>
80 #include <linux/of_address.h>
81 #include <linux/of_irq.h>
82 #include <linux/of_mdio.h>
83 #include <linux/of_platform.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
88 #include <linux/net_tstamp.h>
93 #include <asm/mpc85xx.h>
96 #include <asm/uaccess.h>
97 #include <linux/module.h>
98 #include <linux/dma-mapping.h>
99 #include <linux/crc32.h>
100 #include <linux/mii.h>
101 #include <linux/phy.h>
102 #include <linux/phy_fixed.h>
103 #include <linux/of.h>
104 #include <linux/of_net.h>
105 #include <linux/of_address.h>
106 #include <linux/of_irq.h>
110 #define TX_TIMEOUT (5*HZ)
112 const char gfar_driver_version[] = "2.0";
114 static int gfar_enet_open(struct net_device *dev);
115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
116 static void gfar_reset_task(struct work_struct *work);
117 static void gfar_timeout(struct net_device *dev);
118 static int gfar_close(struct net_device *dev);
119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
121 static int gfar_set_mac_address(struct net_device *dev);
122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
123 static irqreturn_t gfar_error(int irq, void *dev_id);
124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
126 static void adjust_link(struct net_device *dev);
127 static noinline void gfar_update_link_state(struct gfar_private *priv);
128 static int init_phy(struct net_device *dev);
129 static int gfar_probe(struct platform_device *ofdev);
130 static int gfar_remove(struct platform_device *ofdev);
131 static void free_skb_resources(struct gfar_private *priv);
132 static void gfar_set_multi(struct net_device *dev);
133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
134 static void gfar_configure_serdes(struct net_device *dev);
135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
139 #ifdef CONFIG_NET_POLL_CONTROLLER
140 static void gfar_netpoll(struct net_device *dev);
142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
145 static void gfar_halt_nodisable(struct gfar_private *priv);
146 static void gfar_clear_exact_match(struct net_device *dev);
147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
153 MODULE_LICENSE("GPL");
155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
160 bdp->bufPtr = cpu_to_be32(buf);
162 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
163 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
164 lstatus |= BD_LFLAG(RXBD_WRAP);
168 bdp->lstatus = cpu_to_be32(lstatus);
171 static void gfar_init_bds(struct net_device *ndev)
173 struct gfar_private *priv = netdev_priv(ndev);
174 struct gfar __iomem *regs = priv->gfargrp[0].regs;
175 struct gfar_priv_tx_q *tx_queue = NULL;
176 struct gfar_priv_rx_q *rx_queue = NULL;
181 for (i = 0; i < priv->num_tx_queues; i++) {
182 tx_queue = priv->tx_queue[i];
183 /* Initialize some variables in our dev structure */
184 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
185 tx_queue->dirty_tx = tx_queue->tx_bd_base;
186 tx_queue->cur_tx = tx_queue->tx_bd_base;
187 tx_queue->skb_curtx = 0;
188 tx_queue->skb_dirtytx = 0;
190 /* Initialize Transmit Descriptor Ring */
191 txbdp = tx_queue->tx_bd_base;
192 for (j = 0; j < tx_queue->tx_ring_size; j++) {
198 /* Set the last descriptor in the ring to indicate wrap */
200 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
204 rfbptr = ®s->rfbptr0;
205 for (i = 0; i < priv->num_rx_queues; i++) {
206 rx_queue = priv->rx_queue[i];
208 rx_queue->next_to_clean = 0;
209 rx_queue->next_to_use = 0;
210 rx_queue->next_to_alloc = 0;
212 /* make sure next_to_clean != next_to_use after this
213 * by leaving at least 1 unused descriptor
215 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
217 rx_queue->rfbptr = rfbptr;
222 static int gfar_alloc_skb_resources(struct net_device *ndev)
227 struct gfar_private *priv = netdev_priv(ndev);
228 struct device *dev = priv->dev;
229 struct gfar_priv_tx_q *tx_queue = NULL;
230 struct gfar_priv_rx_q *rx_queue = NULL;
232 priv->total_tx_ring_size = 0;
233 for (i = 0; i < priv->num_tx_queues; i++)
234 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
236 priv->total_rx_ring_size = 0;
237 for (i = 0; i < priv->num_rx_queues; i++)
238 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
240 /* Allocate memory for the buffer descriptors */
241 vaddr = dma_alloc_coherent(dev,
242 (priv->total_tx_ring_size *
243 sizeof(struct txbd8)) +
244 (priv->total_rx_ring_size *
245 sizeof(struct rxbd8)),
250 for (i = 0; i < priv->num_tx_queues; i++) {
251 tx_queue = priv->tx_queue[i];
252 tx_queue->tx_bd_base = vaddr;
253 tx_queue->tx_bd_dma_base = addr;
254 tx_queue->dev = ndev;
255 /* enet DMA only understands physical addresses */
256 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
257 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
260 /* Start the rx descriptor ring where the tx ring leaves off */
261 for (i = 0; i < priv->num_rx_queues; i++) {
262 rx_queue = priv->rx_queue[i];
263 rx_queue->rx_bd_base = vaddr;
264 rx_queue->rx_bd_dma_base = addr;
265 rx_queue->ndev = ndev;
267 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
268 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
271 /* Setup the skbuff rings */
272 for (i = 0; i < priv->num_tx_queues; i++) {
273 tx_queue = priv->tx_queue[i];
274 tx_queue->tx_skbuff =
275 kmalloc_array(tx_queue->tx_ring_size,
276 sizeof(*tx_queue->tx_skbuff),
278 if (!tx_queue->tx_skbuff)
281 for (j = 0; j < tx_queue->tx_ring_size; j++)
282 tx_queue->tx_skbuff[j] = NULL;
285 for (i = 0; i < priv->num_rx_queues; i++) {
286 rx_queue = priv->rx_queue[i];
287 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
288 sizeof(*rx_queue->rx_buff),
290 if (!rx_queue->rx_buff)
299 free_skb_resources(priv);
303 static void gfar_init_tx_rx_base(struct gfar_private *priv)
305 struct gfar __iomem *regs = priv->gfargrp[0].regs;
309 baddr = ®s->tbase0;
310 for (i = 0; i < priv->num_tx_queues; i++) {
311 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
315 baddr = ®s->rbase0;
316 for (i = 0; i < priv->num_rx_queues; i++) {
317 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
322 static void gfar_init_rqprm(struct gfar_private *priv)
324 struct gfar __iomem *regs = priv->gfargrp[0].regs;
328 baddr = ®s->rqprm0;
329 for (i = 0; i < priv->num_rx_queues; i++) {
330 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
331 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
336 static void gfar_rx_offload_en(struct gfar_private *priv)
338 /* set this when rx hw offload (TOE) functions are being used */
339 priv->uses_rxfcb = 0;
341 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
342 priv->uses_rxfcb = 1;
344 if (priv->hwts_rx_en || priv->rx_filer_enable)
345 priv->uses_rxfcb = 1;
348 static void gfar_mac_rx_config(struct gfar_private *priv)
350 struct gfar __iomem *regs = priv->gfargrp[0].regs;
353 if (priv->rx_filer_enable) {
354 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
355 /* Program the RIR0 reg with the required distribution */
356 if (priv->poll_mode == GFAR_SQ_POLLING)
357 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0);
358 else /* GFAR_MQ_POLLING */
359 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0);
362 /* Restore PROMISC mode */
363 if (priv->ndev->flags & IFF_PROMISC)
366 if (priv->ndev->features & NETIF_F_RXCSUM)
367 rctrl |= RCTRL_CHECKSUMMING;
369 if (priv->extended_hash)
370 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
373 rctrl &= ~RCTRL_PAL_MASK;
374 rctrl |= RCTRL_PADDING(priv->padding);
377 /* Enable HW time stamping if requested from user space */
378 if (priv->hwts_rx_en)
379 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
381 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
382 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
384 /* Clear the LFC bit */
385 gfar_write(®s->rctrl, rctrl);
386 /* Init flow control threshold values */
387 gfar_init_rqprm(priv);
388 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL);
391 /* Init rctrl based on our settings */
392 gfar_write(®s->rctrl, rctrl);
395 static void gfar_mac_tx_config(struct gfar_private *priv)
397 struct gfar __iomem *regs = priv->gfargrp[0].regs;
400 if (priv->ndev->features & NETIF_F_IP_CSUM)
401 tctrl |= TCTRL_INIT_CSUM;
403 if (priv->prio_sched_en)
404 tctrl |= TCTRL_TXSCHED_PRIO;
406 tctrl |= TCTRL_TXSCHED_WRRS;
407 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
408 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
411 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
412 tctrl |= TCTRL_VLINS;
414 gfar_write(®s->tctrl, tctrl);
417 static void gfar_configure_coalescing(struct gfar_private *priv,
418 unsigned long tx_mask, unsigned long rx_mask)
420 struct gfar __iomem *regs = priv->gfargrp[0].regs;
423 if (priv->mode == MQ_MG_MODE) {
426 baddr = ®s->txic0;
427 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
428 gfar_write(baddr + i, 0);
429 if (likely(priv->tx_queue[i]->txcoalescing))
430 gfar_write(baddr + i, priv->tx_queue[i]->txic);
433 baddr = ®s->rxic0;
434 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
435 gfar_write(baddr + i, 0);
436 if (likely(priv->rx_queue[i]->rxcoalescing))
437 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
440 /* Backward compatible case -- even if we enable
441 * multiple queues, there's only single reg to program
443 gfar_write(®s->txic, 0);
444 if (likely(priv->tx_queue[0]->txcoalescing))
445 gfar_write(®s->txic, priv->tx_queue[0]->txic);
447 gfar_write(®s->rxic, 0);
448 if (unlikely(priv->rx_queue[0]->rxcoalescing))
449 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
453 void gfar_configure_coalescing_all(struct gfar_private *priv)
455 gfar_configure_coalescing(priv, 0xFF, 0xFF);
458 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
460 struct gfar_private *priv = netdev_priv(dev);
461 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
462 unsigned long tx_packets = 0, tx_bytes = 0;
465 for (i = 0; i < priv->num_rx_queues; i++) {
466 rx_packets += priv->rx_queue[i]->stats.rx_packets;
467 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
468 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
471 dev->stats.rx_packets = rx_packets;
472 dev->stats.rx_bytes = rx_bytes;
473 dev->stats.rx_dropped = rx_dropped;
475 for (i = 0; i < priv->num_tx_queues; i++) {
476 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
477 tx_packets += priv->tx_queue[i]->stats.tx_packets;
480 dev->stats.tx_bytes = tx_bytes;
481 dev->stats.tx_packets = tx_packets;
486 static int gfar_set_mac_addr(struct net_device *dev, void *p)
490 ret = eth_mac_addr(dev, p);
494 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
499 static const struct net_device_ops gfar_netdev_ops = {
500 .ndo_open = gfar_enet_open,
501 .ndo_start_xmit = gfar_start_xmit,
502 .ndo_stop = gfar_close,
503 .ndo_change_mtu = gfar_change_mtu,
504 .ndo_set_features = gfar_set_features,
505 .ndo_set_rx_mode = gfar_set_multi,
506 .ndo_tx_timeout = gfar_timeout,
507 .ndo_do_ioctl = gfar_ioctl,
508 .ndo_get_stats = gfar_get_stats,
509 .ndo_set_mac_address = gfar_set_mac_addr,
510 .ndo_validate_addr = eth_validate_addr,
511 #ifdef CONFIG_NET_POLL_CONTROLLER
512 .ndo_poll_controller = gfar_netpoll,
516 static void gfar_ints_disable(struct gfar_private *priv)
519 for (i = 0; i < priv->num_grps; i++) {
520 struct gfar __iomem *regs = priv->gfargrp[i].regs;
522 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
524 /* Initialize IMASK */
525 gfar_write(®s->imask, IMASK_INIT_CLEAR);
529 static void gfar_ints_enable(struct gfar_private *priv)
532 for (i = 0; i < priv->num_grps; i++) {
533 struct gfar __iomem *regs = priv->gfargrp[i].regs;
534 /* Unmask the interrupts we look for */
535 gfar_write(®s->imask, IMASK_DEFAULT);
539 static int gfar_alloc_tx_queues(struct gfar_private *priv)
543 for (i = 0; i < priv->num_tx_queues; i++) {
544 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
546 if (!priv->tx_queue[i])
549 priv->tx_queue[i]->tx_skbuff = NULL;
550 priv->tx_queue[i]->qindex = i;
551 priv->tx_queue[i]->dev = priv->ndev;
552 spin_lock_init(&(priv->tx_queue[i]->txlock));
557 static int gfar_alloc_rx_queues(struct gfar_private *priv)
561 for (i = 0; i < priv->num_rx_queues; i++) {
562 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
564 if (!priv->rx_queue[i])
567 priv->rx_queue[i]->qindex = i;
568 priv->rx_queue[i]->ndev = priv->ndev;
573 static void gfar_free_tx_queues(struct gfar_private *priv)
577 for (i = 0; i < priv->num_tx_queues; i++)
578 kfree(priv->tx_queue[i]);
581 static void gfar_free_rx_queues(struct gfar_private *priv)
585 for (i = 0; i < priv->num_rx_queues; i++)
586 kfree(priv->rx_queue[i]);
589 static void unmap_group_regs(struct gfar_private *priv)
593 for (i = 0; i < MAXGROUPS; i++)
594 if (priv->gfargrp[i].regs)
595 iounmap(priv->gfargrp[i].regs);
598 static void free_gfar_dev(struct gfar_private *priv)
602 for (i = 0; i < priv->num_grps; i++)
603 for (j = 0; j < GFAR_NUM_IRQS; j++) {
604 kfree(priv->gfargrp[i].irqinfo[j]);
605 priv->gfargrp[i].irqinfo[j] = NULL;
608 free_netdev(priv->ndev);
611 static void disable_napi(struct gfar_private *priv)
615 for (i = 0; i < priv->num_grps; i++) {
616 napi_disable(&priv->gfargrp[i].napi_rx);
617 napi_disable(&priv->gfargrp[i].napi_tx);
621 static void enable_napi(struct gfar_private *priv)
625 for (i = 0; i < priv->num_grps; i++) {
626 napi_enable(&priv->gfargrp[i].napi_rx);
627 napi_enable(&priv->gfargrp[i].napi_tx);
631 static int gfar_parse_group(struct device_node *np,
632 struct gfar_private *priv, const char *model)
634 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
637 for (i = 0; i < GFAR_NUM_IRQS; i++) {
638 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
640 if (!grp->irqinfo[i])
644 grp->regs = of_iomap(np, 0);
648 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
650 /* If we aren't the FEC we have multiple interrupts */
651 if (model && strcasecmp(model, "FEC")) {
652 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
653 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
654 if (!gfar_irq(grp, TX)->irq ||
655 !gfar_irq(grp, RX)->irq ||
656 !gfar_irq(grp, ER)->irq)
661 spin_lock_init(&grp->grplock);
662 if (priv->mode == MQ_MG_MODE) {
663 u32 rxq_mask, txq_mask;
666 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
667 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
669 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
671 grp->rx_bit_map = rxq_mask ?
672 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
675 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
677 grp->tx_bit_map = txq_mask ?
678 txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
681 if (priv->poll_mode == GFAR_SQ_POLLING) {
682 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
683 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
684 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
687 grp->rx_bit_map = 0xFF;
688 grp->tx_bit_map = 0xFF;
691 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
692 * right to left, so we need to revert the 8 bits to get the q index
694 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
695 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
697 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
698 * also assign queues to groups
700 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
702 grp->rx_queue = priv->rx_queue[i];
703 grp->num_rx_queues++;
704 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
705 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
706 priv->rx_queue[i]->grp = grp;
709 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
711 grp->tx_queue = priv->tx_queue[i];
712 grp->num_tx_queues++;
713 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
714 priv->tqueue |= (TQUEUE_EN0 >> i);
715 priv->tx_queue[i]->grp = grp;
723 static int gfar_of_group_count(struct device_node *np)
725 struct device_node *child;
728 for_each_available_child_of_node(np, child)
729 if (!of_node_cmp(child->name, "queue-group"))
735 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
739 const void *mac_addr;
741 struct net_device *dev = NULL;
742 struct gfar_private *priv = NULL;
743 struct device_node *np = ofdev->dev.of_node;
744 struct device_node *child = NULL;
747 unsigned int num_tx_qs, num_rx_qs;
748 unsigned short mode, poll_mode;
753 if (of_device_is_compatible(np, "fsl,etsec2")) {
755 poll_mode = GFAR_SQ_POLLING;
758 poll_mode = GFAR_SQ_POLLING;
761 if (mode == SQ_SG_MODE) {
764 } else { /* MQ_MG_MODE */
765 /* get the actual number of supported groups */
766 unsigned int num_grps = gfar_of_group_count(np);
768 if (num_grps == 0 || num_grps > MAXGROUPS) {
769 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
771 pr_err("Cannot do alloc_etherdev, aborting\n");
775 if (poll_mode == GFAR_SQ_POLLING) {
776 num_tx_qs = num_grps; /* one txq per int group */
777 num_rx_qs = num_grps; /* one rxq per int group */
778 } else { /* GFAR_MQ_POLLING */
779 u32 tx_queues, rx_queues;
782 /* parse the num of HW tx and rx queues */
783 ret = of_property_read_u32(np, "fsl,num_tx_queues",
785 num_tx_qs = ret ? 1 : tx_queues;
787 ret = of_property_read_u32(np, "fsl,num_rx_queues",
789 num_rx_qs = ret ? 1 : rx_queues;
793 if (num_tx_qs > MAX_TX_QS) {
794 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
795 num_tx_qs, MAX_TX_QS);
796 pr_err("Cannot do alloc_etherdev, aborting\n");
800 if (num_rx_qs > MAX_RX_QS) {
801 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
802 num_rx_qs, MAX_RX_QS);
803 pr_err("Cannot do alloc_etherdev, aborting\n");
807 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
812 priv = netdev_priv(dev);
816 priv->poll_mode = poll_mode;
818 priv->num_tx_queues = num_tx_qs;
819 netif_set_real_num_rx_queues(dev, num_rx_qs);
820 priv->num_rx_queues = num_rx_qs;
822 err = gfar_alloc_tx_queues(priv);
824 goto tx_alloc_failed;
826 err = gfar_alloc_rx_queues(priv);
828 goto rx_alloc_failed;
830 err = of_property_read_string(np, "model", &model);
832 pr_err("Device model property missing, aborting\n");
833 goto rx_alloc_failed;
836 /* Init Rx queue filer rule set linked list */
837 INIT_LIST_HEAD(&priv->rx_list.list);
838 priv->rx_list.count = 0;
839 mutex_init(&priv->rx_queue_access);
841 for (i = 0; i < MAXGROUPS; i++)
842 priv->gfargrp[i].regs = NULL;
844 /* Parse and initialize group specific information */
845 if (priv->mode == MQ_MG_MODE) {
846 for_each_available_child_of_node(np, child) {
847 if (of_node_cmp(child->name, "queue-group"))
850 err = gfar_parse_group(child, priv, model);
856 } else { /* SQ_SG_MODE */
857 err = gfar_parse_group(np, priv, model);
862 if (of_property_read_bool(np, "bd-stash")) {
863 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
864 priv->bd_stash_en = 1;
867 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
870 priv->rx_stash_size = stash_len;
872 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
875 priv->rx_stash_index = stash_idx;
877 if (stash_len || stash_idx)
878 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
880 mac_addr = of_get_mac_address(np);
883 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
885 if (model && !strcasecmp(model, "TSEC"))
886 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
887 FSL_GIANFAR_DEV_HAS_COALESCE |
888 FSL_GIANFAR_DEV_HAS_RMON |
889 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
891 if (model && !strcasecmp(model, "eTSEC"))
892 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
893 FSL_GIANFAR_DEV_HAS_COALESCE |
894 FSL_GIANFAR_DEV_HAS_RMON |
895 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
896 FSL_GIANFAR_DEV_HAS_CSUM |
897 FSL_GIANFAR_DEV_HAS_VLAN |
898 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
899 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
900 FSL_GIANFAR_DEV_HAS_TIMER |
901 FSL_GIANFAR_DEV_HAS_RX_FILER;
903 err = of_property_read_string(np, "phy-connection-type", &ctype);
905 /* We only care about rgmii-id. The rest are autodetected */
906 if (err == 0 && !strcmp(ctype, "rgmii-id"))
907 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
909 priv->interface = PHY_INTERFACE_MODE_MII;
911 if (of_find_property(np, "fsl,magic-packet", NULL))
912 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
914 if (of_get_property(np, "fsl,wake-on-filer", NULL))
915 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
917 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
919 /* In the case of a fixed PHY, the DT node associated
920 * to the PHY is the Ethernet MAC DT node.
922 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
923 err = of_phy_register_fixed_link(np);
927 priv->phy_node = of_node_get(np);
930 /* Find the TBI PHY. If it's not there, we don't support SGMII */
931 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
936 unmap_group_regs(priv);
938 gfar_free_rx_queues(priv);
940 gfar_free_tx_queues(priv);
945 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
947 struct hwtstamp_config config;
948 struct gfar_private *priv = netdev_priv(netdev);
950 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
953 /* reserved for future extensions */
957 switch (config.tx_type) {
958 case HWTSTAMP_TX_OFF:
959 priv->hwts_tx_en = 0;
962 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
964 priv->hwts_tx_en = 1;
970 switch (config.rx_filter) {
971 case HWTSTAMP_FILTER_NONE:
972 if (priv->hwts_rx_en) {
973 priv->hwts_rx_en = 0;
978 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
980 if (!priv->hwts_rx_en) {
981 priv->hwts_rx_en = 1;
984 config.rx_filter = HWTSTAMP_FILTER_ALL;
988 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
992 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
994 struct hwtstamp_config config;
995 struct gfar_private *priv = netdev_priv(netdev);
998 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
999 config.rx_filter = (priv->hwts_rx_en ?
1000 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
1002 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1006 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1008 struct phy_device *phydev = dev->phydev;
1010 if (!netif_running(dev))
1013 if (cmd == SIOCSHWTSTAMP)
1014 return gfar_hwtstamp_set(dev, rq);
1015 if (cmd == SIOCGHWTSTAMP)
1016 return gfar_hwtstamp_get(dev, rq);
1021 return phy_mii_ioctl(phydev, rq, cmd);
1024 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1027 u32 rqfpr = FPR_FILER_MASK;
1031 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1032 priv->ftp_rqfpr[rqfar] = rqfpr;
1033 priv->ftp_rqfcr[rqfar] = rqfcr;
1034 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1037 rqfcr = RQFCR_CMP_NOMATCH;
1038 priv->ftp_rqfpr[rqfar] = rqfpr;
1039 priv->ftp_rqfcr[rqfar] = rqfcr;
1040 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1043 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1045 priv->ftp_rqfcr[rqfar] = rqfcr;
1046 priv->ftp_rqfpr[rqfar] = rqfpr;
1047 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1050 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1052 priv->ftp_rqfcr[rqfar] = rqfcr;
1053 priv->ftp_rqfpr[rqfar] = rqfpr;
1054 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1059 static void gfar_init_filer_table(struct gfar_private *priv)
1062 u32 rqfar = MAX_FILER_IDX;
1064 u32 rqfpr = FPR_FILER_MASK;
1067 rqfcr = RQFCR_CMP_MATCH;
1068 priv->ftp_rqfcr[rqfar] = rqfcr;
1069 priv->ftp_rqfpr[rqfar] = rqfpr;
1070 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1072 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1073 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1074 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1075 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1076 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1077 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1079 /* cur_filer_idx indicated the first non-masked rule */
1080 priv->cur_filer_idx = rqfar;
1082 /* Rest are masked rules */
1083 rqfcr = RQFCR_CMP_NOMATCH;
1084 for (i = 0; i < rqfar; i++) {
1085 priv->ftp_rqfcr[i] = rqfcr;
1086 priv->ftp_rqfpr[i] = rqfpr;
1087 gfar_write_filer(priv, i, rqfcr, rqfpr);
1092 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1094 unsigned int pvr = mfspr(SPRN_PVR);
1095 unsigned int svr = mfspr(SPRN_SVR);
1096 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1097 unsigned int rev = svr & 0xffff;
1099 /* MPC8313 Rev 2.0 and higher; All MPC837x */
1100 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1101 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1102 priv->errata |= GFAR_ERRATA_74;
1104 /* MPC8313 and MPC837x all rev */
1105 if ((pvr == 0x80850010 && mod == 0x80b0) ||
1106 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1107 priv->errata |= GFAR_ERRATA_76;
1109 /* MPC8313 Rev < 2.0 */
1110 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1111 priv->errata |= GFAR_ERRATA_12;
1114 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1116 unsigned int svr = mfspr(SPRN_SVR);
1118 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1119 priv->errata |= GFAR_ERRATA_12;
1120 /* P2020/P1010 Rev 1; MPC8548 Rev 2 */
1121 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1122 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
1123 ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
1124 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1128 static void gfar_detect_errata(struct gfar_private *priv)
1130 struct device *dev = &priv->ofdev->dev;
1132 /* no plans to fix */
1133 priv->errata |= GFAR_ERRATA_A002;
1136 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1137 __gfar_detect_errata_85xx(priv);
1138 else /* non-mpc85xx parts, i.e. e300 core based */
1139 __gfar_detect_errata_83xx(priv);
1143 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1147 void gfar_mac_reset(struct gfar_private *priv)
1149 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1152 /* Reset MAC layer */
1153 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1155 /* We need to delay at least 3 TX clocks */
1158 /* the soft reset bit is not self-resetting, so we need to
1159 * clear it before resuming normal operation
1161 gfar_write(®s->maccfg1, 0);
1165 gfar_rx_offload_en(priv);
1167 /* Initialize the max receive frame/buffer lengths */
1168 gfar_write(®s->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1169 gfar_write(®s->mrblr, GFAR_RXB_SIZE);
1171 /* Initialize the Minimum Frame Length Register */
1172 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1174 /* Initialize MACCFG2. */
1175 tempval = MACCFG2_INIT_SETTINGS;
1177 /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1178 * are marked as truncated. Avoid this by MACCFG2[Huge Frame]=1,
1179 * and by checking RxBD[LG] and discarding larger than MAXFRM.
1181 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1182 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1184 gfar_write(®s->maccfg2, tempval);
1186 /* Clear mac addr hash registers */
1187 gfar_write(®s->igaddr0, 0);
1188 gfar_write(®s->igaddr1, 0);
1189 gfar_write(®s->igaddr2, 0);
1190 gfar_write(®s->igaddr3, 0);
1191 gfar_write(®s->igaddr4, 0);
1192 gfar_write(®s->igaddr5, 0);
1193 gfar_write(®s->igaddr6, 0);
1194 gfar_write(®s->igaddr7, 0);
1196 gfar_write(®s->gaddr0, 0);
1197 gfar_write(®s->gaddr1, 0);
1198 gfar_write(®s->gaddr2, 0);
1199 gfar_write(®s->gaddr3, 0);
1200 gfar_write(®s->gaddr4, 0);
1201 gfar_write(®s->gaddr5, 0);
1202 gfar_write(®s->gaddr6, 0);
1203 gfar_write(®s->gaddr7, 0);
1205 if (priv->extended_hash)
1206 gfar_clear_exact_match(priv->ndev);
1208 gfar_mac_rx_config(priv);
1210 gfar_mac_tx_config(priv);
1212 gfar_set_mac_address(priv->ndev);
1214 gfar_set_multi(priv->ndev);
1216 /* clear ievent and imask before configuring coalescing */
1217 gfar_ints_disable(priv);
1219 /* Configure the coalescing support */
1220 gfar_configure_coalescing_all(priv);
1223 static void gfar_hw_init(struct gfar_private *priv)
1225 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1228 /* Stop the DMA engine now, in case it was running before
1229 * (The firmware could have used it, and left it running).
1233 gfar_mac_reset(priv);
1235 /* Zero out the rmon mib registers if it has them */
1236 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1237 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1239 /* Mask off the CAM interrupts */
1240 gfar_write(®s->rmon.cam1, 0xffffffff);
1241 gfar_write(®s->rmon.cam2, 0xffffffff);
1244 /* Initialize ECNTRL */
1245 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1247 /* Set the extraction length and index */
1248 attrs = ATTRELI_EL(priv->rx_stash_size) |
1249 ATTRELI_EI(priv->rx_stash_index);
1251 gfar_write(®s->attreli, attrs);
1253 /* Start with defaults, and add stashing
1254 * depending on driver parameters
1256 attrs = ATTR_INIT_SETTINGS;
1258 if (priv->bd_stash_en)
1259 attrs |= ATTR_BDSTASH;
1261 if (priv->rx_stash_size != 0)
1262 attrs |= ATTR_BUFSTASH;
1264 gfar_write(®s->attr, attrs);
1267 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1268 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1269 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1271 /* Program the interrupt steering regs, only for MG devices */
1272 if (priv->num_grps > 1)
1273 gfar_write_isrg(priv);
1276 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1278 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1280 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1281 priv->extended_hash = 1;
1282 priv->hash_width = 9;
1284 priv->hash_regs[0] = ®s->igaddr0;
1285 priv->hash_regs[1] = ®s->igaddr1;
1286 priv->hash_regs[2] = ®s->igaddr2;
1287 priv->hash_regs[3] = ®s->igaddr3;
1288 priv->hash_regs[4] = ®s->igaddr4;
1289 priv->hash_regs[5] = ®s->igaddr5;
1290 priv->hash_regs[6] = ®s->igaddr6;
1291 priv->hash_regs[7] = ®s->igaddr7;
1292 priv->hash_regs[8] = ®s->gaddr0;
1293 priv->hash_regs[9] = ®s->gaddr1;
1294 priv->hash_regs[10] = ®s->gaddr2;
1295 priv->hash_regs[11] = ®s->gaddr3;
1296 priv->hash_regs[12] = ®s->gaddr4;
1297 priv->hash_regs[13] = ®s->gaddr5;
1298 priv->hash_regs[14] = ®s->gaddr6;
1299 priv->hash_regs[15] = ®s->gaddr7;
1302 priv->extended_hash = 0;
1303 priv->hash_width = 8;
1305 priv->hash_regs[0] = ®s->gaddr0;
1306 priv->hash_regs[1] = ®s->gaddr1;
1307 priv->hash_regs[2] = ®s->gaddr2;
1308 priv->hash_regs[3] = ®s->gaddr3;
1309 priv->hash_regs[4] = ®s->gaddr4;
1310 priv->hash_regs[5] = ®s->gaddr5;
1311 priv->hash_regs[6] = ®s->gaddr6;
1312 priv->hash_regs[7] = ®s->gaddr7;
1316 /* Set up the ethernet device structure, private data,
1317 * and anything else we need before we start
1319 static int gfar_probe(struct platform_device *ofdev)
1321 struct device_node *np = ofdev->dev.of_node;
1322 struct net_device *dev = NULL;
1323 struct gfar_private *priv = NULL;
1326 err = gfar_of_init(ofdev, &dev);
1331 priv = netdev_priv(dev);
1333 priv->ofdev = ofdev;
1334 priv->dev = &ofdev->dev;
1335 SET_NETDEV_DEV(dev, &ofdev->dev);
1337 INIT_WORK(&priv->reset_task, gfar_reset_task);
1339 platform_set_drvdata(ofdev, priv);
1341 gfar_detect_errata(priv);
1343 /* Set the dev->base_addr to the gfar reg region */
1344 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1346 /* Fill in the dev structure */
1347 dev->watchdog_timeo = TX_TIMEOUT;
1349 dev->netdev_ops = &gfar_netdev_ops;
1350 dev->ethtool_ops = &gfar_ethtool_ops;
1352 /* Register for napi ...We are registering NAPI for each grp */
1353 for (i = 0; i < priv->num_grps; i++) {
1354 if (priv->poll_mode == GFAR_SQ_POLLING) {
1355 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1356 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1357 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1358 gfar_poll_tx_sq, 2);
1360 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1361 gfar_poll_rx, GFAR_DEV_WEIGHT);
1362 netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1367 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1368 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1370 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1371 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1374 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1375 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1376 NETIF_F_HW_VLAN_CTAG_RX;
1377 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1380 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1382 gfar_init_addr_hash_table(priv);
1384 /* Insert receive time stamps into padding alignment bytes, and
1385 * plus 2 bytes padding to ensure the cpu alignment.
1387 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1388 priv->padding = 8 + DEFAULT_PADDING;
1390 if (dev->features & NETIF_F_IP_CSUM ||
1391 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1392 dev->needed_headroom = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
1394 /* Initializing some of the rx/tx queue level parameters */
1395 for (i = 0; i < priv->num_tx_queues; i++) {
1396 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1397 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1398 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1399 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1402 for (i = 0; i < priv->num_rx_queues; i++) {
1403 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1404 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1405 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1408 /* Always enable rx filer if available */
1409 priv->rx_filer_enable =
1410 (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
1411 /* Enable most messages by default */
1412 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1413 /* use pritority h/w tx queue scheduling for single queue devices */
1414 if (priv->num_tx_queues == 1)
1415 priv->prio_sched_en = 1;
1417 set_bit(GFAR_DOWN, &priv->state);
1421 /* Carrier starts down, phylib will bring it up */
1422 netif_carrier_off(dev);
1424 err = register_netdev(dev);
1427 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1431 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
1432 priv->wol_supported |= GFAR_WOL_MAGIC;
1434 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
1435 priv->rx_filer_enable)
1436 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
1438 device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
1440 /* fill out IRQ number and name fields */
1441 for (i = 0; i < priv->num_grps; i++) {
1442 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1443 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1444 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1445 dev->name, "_g", '0' + i, "_tx");
1446 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1447 dev->name, "_g", '0' + i, "_rx");
1448 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1449 dev->name, "_g", '0' + i, "_er");
1451 strcpy(gfar_irq(grp, TX)->name, dev->name);
1454 /* Initialize the filer table */
1455 gfar_init_filer_table(priv);
1457 /* Print out the device info */
1458 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1460 /* Even more device info helps when determining which kernel
1461 * provided which set of benchmarks.
1463 netdev_info(dev, "Running with NAPI enabled\n");
1464 for (i = 0; i < priv->num_rx_queues; i++)
1465 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1466 i, priv->rx_queue[i]->rx_ring_size);
1467 for (i = 0; i < priv->num_tx_queues; i++)
1468 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1469 i, priv->tx_queue[i]->tx_ring_size);
1474 if (of_phy_is_fixed_link(np))
1475 of_phy_deregister_fixed_link(np);
1476 unmap_group_regs(priv);
1477 gfar_free_rx_queues(priv);
1478 gfar_free_tx_queues(priv);
1479 of_node_put(priv->phy_node);
1480 of_node_put(priv->tbi_node);
1481 free_gfar_dev(priv);
1485 static int gfar_remove(struct platform_device *ofdev)
1487 struct gfar_private *priv = platform_get_drvdata(ofdev);
1488 struct device_node *np = ofdev->dev.of_node;
1490 of_node_put(priv->phy_node);
1491 of_node_put(priv->tbi_node);
1493 unregister_netdev(priv->ndev);
1495 if (of_phy_is_fixed_link(np))
1496 of_phy_deregister_fixed_link(np);
1498 unmap_group_regs(priv);
1499 gfar_free_rx_queues(priv);
1500 gfar_free_tx_queues(priv);
1501 free_gfar_dev(priv);
1508 static void __gfar_filer_disable(struct gfar_private *priv)
1510 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1513 temp = gfar_read(®s->rctrl);
1514 temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
1515 gfar_write(®s->rctrl, temp);
1518 static void __gfar_filer_enable(struct gfar_private *priv)
1520 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1523 temp = gfar_read(®s->rctrl);
1524 temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1525 gfar_write(®s->rctrl, temp);
1528 /* Filer rules implementing wol capabilities */
1529 static void gfar_filer_config_wol(struct gfar_private *priv)
1534 __gfar_filer_disable(priv);
1536 /* clear the filer table, reject any packet by default */
1537 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
1538 for (i = 0; i <= MAX_FILER_IDX; i++)
1539 gfar_write_filer(priv, i, rqfcr, 0);
1542 if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
1543 /* unicast packet, accept it */
1544 struct net_device *ndev = priv->ndev;
1545 /* get the default rx queue index */
1546 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
1547 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
1548 (ndev->dev_addr[1] << 8) |
1551 rqfcr = (qindex << 10) | RQFCR_AND |
1552 RQFCR_CMP_EXACT | RQFCR_PID_DAH;
1554 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1556 dest_mac_addr = (ndev->dev_addr[3] << 16) |
1557 (ndev->dev_addr[4] << 8) |
1559 rqfcr = (qindex << 10) | RQFCR_GPI |
1560 RQFCR_CMP_EXACT | RQFCR_PID_DAL;
1561 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1564 __gfar_filer_enable(priv);
1567 static void gfar_filer_restore_table(struct gfar_private *priv)
1572 __gfar_filer_disable(priv);
1574 for (i = 0; i <= MAX_FILER_IDX; i++) {
1575 rqfcr = priv->ftp_rqfcr[i];
1576 rqfpr = priv->ftp_rqfpr[i];
1577 gfar_write_filer(priv, i, rqfcr, rqfpr);
1580 __gfar_filer_enable(priv);
1583 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
1584 static void gfar_start_wol_filer(struct gfar_private *priv)
1586 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1590 /* Enable Rx hw queues */
1591 gfar_write(®s->rqueue, priv->rqueue);
1593 /* Initialize DMACTRL to have WWR and WOP */
1594 tempval = gfar_read(®s->dmactrl);
1595 tempval |= DMACTRL_INIT_SETTINGS;
1596 gfar_write(®s->dmactrl, tempval);
1598 /* Make sure we aren't stopped */
1599 tempval = gfar_read(®s->dmactrl);
1600 tempval &= ~DMACTRL_GRS;
1601 gfar_write(®s->dmactrl, tempval);
1603 for (i = 0; i < priv->num_grps; i++) {
1604 regs = priv->gfargrp[i].regs;
1605 /* Clear RHLT, so that the DMA starts polling now */
1606 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1607 /* enable the Filer General Purpose Interrupt */
1608 gfar_write(®s->imask, IMASK_FGPI);
1612 tempval = gfar_read(®s->maccfg1);
1613 tempval |= MACCFG1_RX_EN;
1614 gfar_write(®s->maccfg1, tempval);
1617 static int gfar_suspend(struct device *dev)
1619 struct gfar_private *priv = dev_get_drvdata(dev);
1620 struct net_device *ndev = priv->ndev;
1621 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1623 u16 wol = priv->wol_opts;
1625 if (!netif_running(ndev))
1629 netif_tx_lock(ndev);
1630 netif_device_detach(ndev);
1631 netif_tx_unlock(ndev);
1635 if (wol & GFAR_WOL_MAGIC) {
1636 /* Enable interrupt on Magic Packet */
1637 gfar_write(®s->imask, IMASK_MAG);
1639 /* Enable Magic Packet mode */
1640 tempval = gfar_read(®s->maccfg2);
1641 tempval |= MACCFG2_MPEN;
1642 gfar_write(®s->maccfg2, tempval);
1644 /* re-enable the Rx block */
1645 tempval = gfar_read(®s->maccfg1);
1646 tempval |= MACCFG1_RX_EN;
1647 gfar_write(®s->maccfg1, tempval);
1649 } else if (wol & GFAR_WOL_FILER_UCAST) {
1650 gfar_filer_config_wol(priv);
1651 gfar_start_wol_filer(priv);
1654 phy_stop(ndev->phydev);
1660 static int gfar_resume(struct device *dev)
1662 struct gfar_private *priv = dev_get_drvdata(dev);
1663 struct net_device *ndev = priv->ndev;
1664 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1666 u16 wol = priv->wol_opts;
1668 if (!netif_running(ndev))
1671 if (wol & GFAR_WOL_MAGIC) {
1672 /* Disable Magic Packet mode */
1673 tempval = gfar_read(®s->maccfg2);
1674 tempval &= ~MACCFG2_MPEN;
1675 gfar_write(®s->maccfg2, tempval);
1677 } else if (wol & GFAR_WOL_FILER_UCAST) {
1678 /* need to stop rx only, tx is already down */
1680 gfar_filer_restore_table(priv);
1683 phy_start(ndev->phydev);
1688 netif_device_attach(ndev);
1694 static int gfar_restore(struct device *dev)
1696 struct gfar_private *priv = dev_get_drvdata(dev);
1697 struct net_device *ndev = priv->ndev;
1699 if (!netif_running(ndev)) {
1700 netif_device_attach(ndev);
1705 gfar_init_bds(ndev);
1707 gfar_mac_reset(priv);
1709 gfar_init_tx_rx_base(priv);
1715 priv->oldduplex = -1;
1718 phy_start(ndev->phydev);
1720 netif_device_attach(ndev);
1726 static struct dev_pm_ops gfar_pm_ops = {
1727 .suspend = gfar_suspend,
1728 .resume = gfar_resume,
1729 .freeze = gfar_suspend,
1730 .thaw = gfar_resume,
1731 .restore = gfar_restore,
1734 #define GFAR_PM_OPS (&gfar_pm_ops)
1738 #define GFAR_PM_OPS NULL
1742 /* Reads the controller's registers to determine what interface
1743 * connects it to the PHY.
1745 static phy_interface_t gfar_get_interface(struct net_device *dev)
1747 struct gfar_private *priv = netdev_priv(dev);
1748 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1751 ecntrl = gfar_read(®s->ecntrl);
1753 if (ecntrl & ECNTRL_SGMII_MODE)
1754 return PHY_INTERFACE_MODE_SGMII;
1756 if (ecntrl & ECNTRL_TBI_MODE) {
1757 if (ecntrl & ECNTRL_REDUCED_MODE)
1758 return PHY_INTERFACE_MODE_RTBI;
1760 return PHY_INTERFACE_MODE_TBI;
1763 if (ecntrl & ECNTRL_REDUCED_MODE) {
1764 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1765 return PHY_INTERFACE_MODE_RMII;
1768 phy_interface_t interface = priv->interface;
1770 /* This isn't autodetected right now, so it must
1771 * be set by the device tree or platform code.
1773 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1774 return PHY_INTERFACE_MODE_RGMII_ID;
1776 return PHY_INTERFACE_MODE_RGMII;
1780 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1781 return PHY_INTERFACE_MODE_GMII;
1783 return PHY_INTERFACE_MODE_MII;
1787 /* Initializes driver's PHY state, and attaches to the PHY.
1788 * Returns 0 on success.
1790 static int init_phy(struct net_device *dev)
1792 struct gfar_private *priv = netdev_priv(dev);
1793 uint gigabit_support =
1794 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1795 GFAR_SUPPORTED_GBIT : 0;
1796 phy_interface_t interface;
1797 struct phy_device *phydev;
1798 struct ethtool_eee edata;
1802 priv->oldduplex = -1;
1804 interface = gfar_get_interface(dev);
1806 phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1809 dev_err(&dev->dev, "could not attach to PHY\n");
1813 if (interface == PHY_INTERFACE_MODE_SGMII)
1814 gfar_configure_serdes(dev);
1816 /* Remove any features not supported by the controller */
1817 phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1818 phydev->advertising = phydev->supported;
1820 /* Add support for flow control, but don't advertise it by default */
1821 phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1823 /* disable EEE autoneg, EEE not supported by eTSEC */
1824 memset(&edata, 0, sizeof(struct ethtool_eee));
1825 phy_ethtool_set_eee(phydev, &edata);
1830 /* Initialize TBI PHY interface for communicating with the
1831 * SERDES lynx PHY on the chip. We communicate with this PHY
1832 * through the MDIO bus on each controller, treating it as a
1833 * "normal" PHY at the address found in the TBIPA register. We assume
1834 * that the TBIPA register is valid. Either the MDIO bus code will set
1835 * it to a value that doesn't conflict with other PHYs on the bus, or the
1836 * value doesn't matter, as there are no other PHYs on the bus.
1838 static void gfar_configure_serdes(struct net_device *dev)
1840 struct gfar_private *priv = netdev_priv(dev);
1841 struct phy_device *tbiphy;
1843 if (!priv->tbi_node) {
1844 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1845 "device tree specify a tbi-handle\n");
1849 tbiphy = of_phy_find_device(priv->tbi_node);
1851 dev_err(&dev->dev, "error: Could not get TBI device\n");
1855 /* If the link is already up, we must already be ok, and don't need to
1856 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1857 * everything for us? Resetting it takes the link down and requires
1858 * several seconds for it to come back.
1860 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1861 put_device(&tbiphy->mdio.dev);
1865 /* Single clk mode, mii mode off(for serdes communication) */
1866 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1868 phy_write(tbiphy, MII_ADVERTISE,
1869 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1870 ADVERTISE_1000XPSE_ASYM);
1872 phy_write(tbiphy, MII_BMCR,
1873 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1876 put_device(&tbiphy->mdio.dev);
1879 static int __gfar_is_rx_idle(struct gfar_private *priv)
1883 /* Normaly TSEC should not hang on GRS commands, so we should
1884 * actually wait for IEVENT_GRSC flag.
1886 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1889 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1890 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1891 * and the Rx can be safely reset.
1893 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1895 if ((res & 0xffff) == (res >> 16))
1901 /* Halt the receive and transmit queues */
1902 static void gfar_halt_nodisable(struct gfar_private *priv)
1904 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1906 unsigned int timeout;
1909 gfar_ints_disable(priv);
1911 if (gfar_is_dma_stopped(priv))
1914 /* Stop the DMA, and wait for it to stop */
1915 tempval = gfar_read(®s->dmactrl);
1916 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1917 gfar_write(®s->dmactrl, tempval);
1921 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1927 stopped = gfar_is_dma_stopped(priv);
1929 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1930 !__gfar_is_rx_idle(priv))
1934 /* Halt the receive and transmit queues */
1935 void gfar_halt(struct gfar_private *priv)
1937 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1940 /* Dissable the Rx/Tx hw queues */
1941 gfar_write(®s->rqueue, 0);
1942 gfar_write(®s->tqueue, 0);
1946 gfar_halt_nodisable(priv);
1948 /* Disable Rx/Tx DMA */
1949 tempval = gfar_read(®s->maccfg1);
1950 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1951 gfar_write(®s->maccfg1, tempval);
1954 void stop_gfar(struct net_device *dev)
1956 struct gfar_private *priv = netdev_priv(dev);
1958 netif_tx_stop_all_queues(dev);
1960 smp_mb__before_atomic();
1961 set_bit(GFAR_DOWN, &priv->state);
1962 smp_mb__after_atomic();
1966 /* disable ints and gracefully shut down Rx/Tx DMA */
1969 phy_stop(dev->phydev);
1971 free_skb_resources(priv);
1974 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1976 struct txbd8 *txbdp;
1977 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1980 txbdp = tx_queue->tx_bd_base;
1982 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1983 if (!tx_queue->tx_skbuff[i])
1986 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1987 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1989 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1992 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1993 be16_to_cpu(txbdp->length),
1997 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1998 tx_queue->tx_skbuff[i] = NULL;
2000 kfree(tx_queue->tx_skbuff);
2001 tx_queue->tx_skbuff = NULL;
2004 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
2008 struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
2011 dev_kfree_skb(rx_queue->skb);
2013 for (i = 0; i < rx_queue->rx_ring_size; i++) {
2014 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
2023 dma_unmap_page(rx_queue->dev, rxb->dma,
2024 PAGE_SIZE, DMA_FROM_DEVICE);
2025 __free_page(rxb->page);
2030 kfree(rx_queue->rx_buff);
2031 rx_queue->rx_buff = NULL;
2034 /* If there are any tx skbs or rx skbs still around, free them.
2035 * Then free tx_skbuff and rx_skbuff
2037 static void free_skb_resources(struct gfar_private *priv)
2039 struct gfar_priv_tx_q *tx_queue = NULL;
2040 struct gfar_priv_rx_q *rx_queue = NULL;
2043 /* Go through all the buffer descriptors and free their data buffers */
2044 for (i = 0; i < priv->num_tx_queues; i++) {
2045 struct netdev_queue *txq;
2047 tx_queue = priv->tx_queue[i];
2048 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
2049 if (tx_queue->tx_skbuff)
2050 free_skb_tx_queue(tx_queue);
2051 netdev_tx_reset_queue(txq);
2054 for (i = 0; i < priv->num_rx_queues; i++) {
2055 rx_queue = priv->rx_queue[i];
2056 if (rx_queue->rx_buff)
2057 free_skb_rx_queue(rx_queue);
2060 dma_free_coherent(priv->dev,
2061 sizeof(struct txbd8) * priv->total_tx_ring_size +
2062 sizeof(struct rxbd8) * priv->total_rx_ring_size,
2063 priv->tx_queue[0]->tx_bd_base,
2064 priv->tx_queue[0]->tx_bd_dma_base);
2067 void gfar_start(struct gfar_private *priv)
2069 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2073 /* Enable Rx/Tx hw queues */
2074 gfar_write(®s->rqueue, priv->rqueue);
2075 gfar_write(®s->tqueue, priv->tqueue);
2077 /* Initialize DMACTRL to have WWR and WOP */
2078 tempval = gfar_read(®s->dmactrl);
2079 tempval |= DMACTRL_INIT_SETTINGS;
2080 gfar_write(®s->dmactrl, tempval);
2082 /* Make sure we aren't stopped */
2083 tempval = gfar_read(®s->dmactrl);
2084 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
2085 gfar_write(®s->dmactrl, tempval);
2087 for (i = 0; i < priv->num_grps; i++) {
2088 regs = priv->gfargrp[i].regs;
2089 /* Clear THLT/RHLT, so that the DMA starts polling now */
2090 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
2091 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
2094 /* Enable Rx/Tx DMA */
2095 tempval = gfar_read(®s->maccfg1);
2096 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2097 gfar_write(®s->maccfg1, tempval);
2099 gfar_ints_enable(priv);
2101 netif_trans_update(priv->ndev); /* prevent tx timeout */
2104 static void free_grp_irqs(struct gfar_priv_grp *grp)
2106 free_irq(gfar_irq(grp, TX)->irq, grp);
2107 free_irq(gfar_irq(grp, RX)->irq, grp);
2108 free_irq(gfar_irq(grp, ER)->irq, grp);
2111 static int register_grp_irqs(struct gfar_priv_grp *grp)
2113 struct gfar_private *priv = grp->priv;
2114 struct net_device *dev = priv->ndev;
2117 /* If the device has multiple interrupts, register for
2118 * them. Otherwise, only register for the one
2120 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2121 /* Install our interrupt handlers for Error,
2122 * Transmit, and Receive
2124 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2125 gfar_irq(grp, ER)->name, grp);
2127 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2128 gfar_irq(grp, ER)->irq);
2132 enable_irq_wake(gfar_irq(grp, ER)->irq);
2134 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2135 gfar_irq(grp, TX)->name, grp);
2137 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2138 gfar_irq(grp, TX)->irq);
2141 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2142 gfar_irq(grp, RX)->name, grp);
2144 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2145 gfar_irq(grp, RX)->irq);
2148 enable_irq_wake(gfar_irq(grp, RX)->irq);
2151 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2152 gfar_irq(grp, TX)->name, grp);
2154 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2155 gfar_irq(grp, TX)->irq);
2158 enable_irq_wake(gfar_irq(grp, TX)->irq);
2164 free_irq(gfar_irq(grp, TX)->irq, grp);
2166 free_irq(gfar_irq(grp, ER)->irq, grp);
2172 static void gfar_free_irq(struct gfar_private *priv)
2177 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2178 for (i = 0; i < priv->num_grps; i++)
2179 free_grp_irqs(&priv->gfargrp[i]);
2181 for (i = 0; i < priv->num_grps; i++)
2182 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2187 static int gfar_request_irq(struct gfar_private *priv)
2191 for (i = 0; i < priv->num_grps; i++) {
2192 err = register_grp_irqs(&priv->gfargrp[i]);
2194 for (j = 0; j < i; j++)
2195 free_grp_irqs(&priv->gfargrp[j]);
2203 /* Bring the controller up and running */
2204 int startup_gfar(struct net_device *ndev)
2206 struct gfar_private *priv = netdev_priv(ndev);
2209 gfar_mac_reset(priv);
2211 err = gfar_alloc_skb_resources(ndev);
2215 gfar_init_tx_rx_base(priv);
2217 smp_mb__before_atomic();
2218 clear_bit(GFAR_DOWN, &priv->state);
2219 smp_mb__after_atomic();
2221 /* Start Rx/Tx DMA and enable the interrupts */
2224 /* force link state update after mac reset */
2227 priv->oldduplex = -1;
2229 phy_start(ndev->phydev);
2233 netif_tx_wake_all_queues(ndev);
2238 /* Called when something needs to use the ethernet device
2239 * Returns 0 for success.
2241 static int gfar_enet_open(struct net_device *dev)
2243 struct gfar_private *priv = netdev_priv(dev);
2246 err = init_phy(dev);
2250 err = gfar_request_irq(priv);
2254 err = startup_gfar(dev);
2261 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2263 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2265 memset(fcb, 0, GMAC_FCB_LEN);
2270 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2273 /* If we're here, it's a IP packet with a TCP or UDP
2274 * payload. We set it to checksum, using a pseudo-header
2277 u8 flags = TXFCB_DEFAULT;
2279 /* Tell the controller what the protocol is
2280 * And provide the already calculated phcs
2282 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2284 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2286 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2288 /* l3os is the distance between the start of the
2289 * frame (skb->data) and the start of the IP hdr.
2290 * l4os is the distance between the start of the
2291 * l3 hdr and the l4 hdr
2293 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2294 fcb->l4os = skb_network_header_len(skb);
2299 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2301 fcb->flags |= TXFCB_VLN;
2302 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2305 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2306 struct txbd8 *base, int ring_size)
2308 struct txbd8 *new_bd = bdp + stride;
2310 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2313 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2316 return skip_txbd(bdp, 1, base, ring_size);
2319 /* eTSEC12: csum generation not supported for some fcb offsets */
2320 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2321 unsigned long fcb_addr)
2323 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2324 (fcb_addr % 0x20) > 0x18);
2327 /* eTSEC76: csum generation for frames larger than 2500 may
2328 * cause excess delays before start of transmission
2330 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2333 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2337 /* This is called by the kernel when a frame is ready for transmission.
2338 * It is pointed to by the dev->hard_start_xmit function pointer
2340 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2342 struct gfar_private *priv = netdev_priv(dev);
2343 struct gfar_priv_tx_q *tx_queue = NULL;
2344 struct netdev_queue *txq;
2345 struct gfar __iomem *regs = NULL;
2346 struct txfcb *fcb = NULL;
2347 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2351 int do_tstamp, do_csum, do_vlan;
2353 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2355 rq = skb->queue_mapping;
2356 tx_queue = priv->tx_queue[rq];
2357 txq = netdev_get_tx_queue(dev, rq);
2358 base = tx_queue->tx_bd_base;
2359 regs = tx_queue->grp->regs;
2361 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2362 do_vlan = skb_vlan_tag_present(skb);
2363 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2366 if (do_csum || do_vlan)
2367 fcb_len = GMAC_FCB_LEN;
2369 /* check if time stamp should be generated */
2370 if (unlikely(do_tstamp))
2371 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2373 /* make space for additional header when fcb is needed */
2375 if (unlikely(skb_cow_head(skb, fcb_len))) {
2376 dev->stats.tx_errors++;
2377 dev_kfree_skb_any(skb);
2378 return NETDEV_TX_OK;
2382 /* total number of fragments in the SKB */
2383 nr_frags = skb_shinfo(skb)->nr_frags;
2385 /* calculate the required number of TxBDs for this skb */
2386 if (unlikely(do_tstamp))
2387 nr_txbds = nr_frags + 2;
2389 nr_txbds = nr_frags + 1;
2391 /* check if there is space to queue this packet */
2392 if (nr_txbds > tx_queue->num_txbdfree) {
2393 /* no space, stop the queue */
2394 netif_tx_stop_queue(txq);
2395 dev->stats.tx_fifo_errors++;
2396 return NETDEV_TX_BUSY;
2399 /* Update transmit stats */
2400 bytes_sent = skb->len;
2401 tx_queue->stats.tx_bytes += bytes_sent;
2402 /* keep Tx bytes on wire for BQL accounting */
2403 GFAR_CB(skb)->bytes_sent = bytes_sent;
2404 tx_queue->stats.tx_packets++;
2406 txbdp = txbdp_start = tx_queue->cur_tx;
2407 lstatus = be32_to_cpu(txbdp->lstatus);
2409 /* Add TxPAL between FCB and frame if required */
2410 if (unlikely(do_tstamp)) {
2411 skb_push(skb, GMAC_TXPAL_LEN);
2412 memset(skb->data, 0, GMAC_TXPAL_LEN);
2415 /* Add TxFCB if required */
2417 fcb = gfar_add_fcb(skb);
2418 lstatus |= BD_LFLAG(TXBD_TOE);
2421 /* Set up checksumming */
2423 gfar_tx_checksum(skb, fcb, fcb_len);
2425 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2426 unlikely(gfar_csum_errata_76(priv, skb->len))) {
2427 __skb_pull(skb, GMAC_FCB_LEN);
2428 skb_checksum_help(skb);
2429 if (do_vlan || do_tstamp) {
2430 /* put back a new fcb for vlan/tstamp TOE */
2431 fcb = gfar_add_fcb(skb);
2433 /* Tx TOE not used */
2434 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2441 gfar_tx_vlan(skb, fcb);
2443 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2445 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2448 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2450 /* Time stamp insertion requires one additional TxBD */
2451 if (unlikely(do_tstamp))
2452 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2453 tx_queue->tx_ring_size);
2455 if (likely(!nr_frags)) {
2456 if (likely(!do_tstamp))
2457 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2459 u32 lstatus_start = lstatus;
2461 /* Place the fragment addresses and lengths into the TxBDs */
2462 frag = &skb_shinfo(skb)->frags[0];
2463 for (i = 0; i < nr_frags; i++, frag++) {
2466 /* Point at the next BD, wrapping as needed */
2467 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2469 size = skb_frag_size(frag);
2471 lstatus = be32_to_cpu(txbdp->lstatus) | size |
2472 BD_LFLAG(TXBD_READY);
2474 /* Handle the last BD specially */
2475 if (i == nr_frags - 1)
2476 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2478 bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
2479 size, DMA_TO_DEVICE);
2480 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2483 /* set the TxBD length and buffer pointer */
2484 txbdp->bufPtr = cpu_to_be32(bufaddr);
2485 txbdp->lstatus = cpu_to_be32(lstatus);
2488 lstatus = lstatus_start;
2491 /* If time stamping is requested one additional TxBD must be set up. The
2492 * first TxBD points to the FCB and must have a data length of
2493 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2494 * the full frame length.
2496 if (unlikely(do_tstamp)) {
2497 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2499 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2502 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2503 (skb_headlen(skb) - fcb_len);
2505 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2507 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2508 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2509 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2511 /* Setup tx hardware time stamping */
2512 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2515 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2518 netdev_tx_sent_queue(txq, bytes_sent);
2522 txbdp_start->lstatus = cpu_to_be32(lstatus);
2524 gfar_wmb(); /* force lstatus write before tx_skbuff */
2526 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2528 /* Update the current skb pointer to the next entry we will use
2529 * (wrapping if necessary)
2531 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2532 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2534 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2536 /* We can work in parallel with gfar_clean_tx_ring(), except
2537 * when modifying num_txbdfree. Note that we didn't grab the lock
2538 * when we were reading the num_txbdfree and checking for available
2539 * space, that's because outside of this function it can only grow.
2541 spin_lock_bh(&tx_queue->txlock);
2542 /* reduce TxBD free count */
2543 tx_queue->num_txbdfree -= (nr_txbds);
2544 spin_unlock_bh(&tx_queue->txlock);
2546 /* If the next BD still needs to be cleaned up, then the bds
2547 * are full. We need to tell the kernel to stop sending us stuff.
2549 if (!tx_queue->num_txbdfree) {
2550 netif_tx_stop_queue(txq);
2552 dev->stats.tx_fifo_errors++;
2555 /* Tell the DMA to go go go */
2556 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2558 return NETDEV_TX_OK;
2561 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2563 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2564 for (i = 0; i < nr_frags; i++) {
2565 lstatus = be32_to_cpu(txbdp->lstatus);
2566 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2569 lstatus &= ~BD_LFLAG(TXBD_READY);
2570 txbdp->lstatus = cpu_to_be32(lstatus);
2571 bufaddr = be32_to_cpu(txbdp->bufPtr);
2572 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2574 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2577 dev_kfree_skb_any(skb);
2578 return NETDEV_TX_OK;
2581 /* Stops the kernel queue, and halts the controller */
2582 static int gfar_close(struct net_device *dev)
2584 struct gfar_private *priv = netdev_priv(dev);
2586 cancel_work_sync(&priv->reset_task);
2589 /* Disconnect from the PHY */
2590 phy_disconnect(dev->phydev);
2592 gfar_free_irq(priv);
2597 /* Changes the mac address if the controller is not running. */
2598 static int gfar_set_mac_address(struct net_device *dev)
2600 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2605 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2607 struct gfar_private *priv = netdev_priv(dev);
2608 int frame_size = new_mtu + ETH_HLEN;
2610 if ((frame_size < 64) || (frame_size > GFAR_JUMBO_FRAME_SIZE)) {
2611 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2615 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2618 if (dev->flags & IFF_UP)
2623 if (dev->flags & IFF_UP)
2626 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2631 void reset_gfar(struct net_device *ndev)
2633 struct gfar_private *priv = netdev_priv(ndev);
2635 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2641 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2644 /* gfar_reset_task gets scheduled when a packet has not been
2645 * transmitted after a set amount of time.
2646 * For now, assume that clearing out all the structures, and
2647 * starting over will fix the problem.
2649 static void gfar_reset_task(struct work_struct *work)
2651 struct gfar_private *priv = container_of(work, struct gfar_private,
2653 reset_gfar(priv->ndev);
2656 static void gfar_timeout(struct net_device *dev)
2658 struct gfar_private *priv = netdev_priv(dev);
2660 dev->stats.tx_errors++;
2661 schedule_work(&priv->reset_task);
2664 /* Interrupt Handler for Transmit complete */
2665 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2667 struct net_device *dev = tx_queue->dev;
2668 struct netdev_queue *txq;
2669 struct gfar_private *priv = netdev_priv(dev);
2670 struct txbd8 *bdp, *next = NULL;
2671 struct txbd8 *lbdp = NULL;
2672 struct txbd8 *base = tx_queue->tx_bd_base;
2673 struct sk_buff *skb;
2675 int tx_ring_size = tx_queue->tx_ring_size;
2676 int frags = 0, nr_txbds = 0;
2679 int tqi = tx_queue->qindex;
2680 unsigned int bytes_sent = 0;
2684 txq = netdev_get_tx_queue(dev, tqi);
2685 bdp = tx_queue->dirty_tx;
2686 skb_dirtytx = tx_queue->skb_dirtytx;
2688 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2691 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2694 frags = skb_shinfo(skb)->nr_frags;
2696 /* When time stamping, one additional TxBD must be freed.
2697 * Also, we need to dma_unmap_single() the TxPAL.
2699 if (unlikely(do_tstamp))
2700 nr_txbds = frags + 2;
2702 nr_txbds = frags + 1;
2704 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2706 lstatus = be32_to_cpu(lbdp->lstatus);
2708 /* Only clean completed frames */
2709 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2710 (lstatus & BD_LENGTH_MASK))
2713 if (unlikely(do_tstamp)) {
2714 next = next_txbd(bdp, base, tx_ring_size);
2715 buflen = be16_to_cpu(next->length) +
2716 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2718 buflen = be16_to_cpu(bdp->length);
2720 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2721 buflen, DMA_TO_DEVICE);
2723 if (unlikely(do_tstamp)) {
2724 struct skb_shared_hwtstamps shhwtstamps;
2725 u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2728 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2729 shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2730 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2731 skb_tstamp_tx(skb, &shhwtstamps);
2732 gfar_clear_txbd_status(bdp);
2736 gfar_clear_txbd_status(bdp);
2737 bdp = next_txbd(bdp, base, tx_ring_size);
2739 for (i = 0; i < frags; i++) {
2740 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2741 be16_to_cpu(bdp->length),
2743 gfar_clear_txbd_status(bdp);
2744 bdp = next_txbd(bdp, base, tx_ring_size);
2747 bytes_sent += GFAR_CB(skb)->bytes_sent;
2749 dev_kfree_skb_any(skb);
2751 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2753 skb_dirtytx = (skb_dirtytx + 1) &
2754 TX_RING_MOD_MASK(tx_ring_size);
2757 spin_lock(&tx_queue->txlock);
2758 tx_queue->num_txbdfree += nr_txbds;
2759 spin_unlock(&tx_queue->txlock);
2762 /* If we freed a buffer, we can restart transmission, if necessary */
2763 if (tx_queue->num_txbdfree &&
2764 netif_tx_queue_stopped(txq) &&
2765 !(test_bit(GFAR_DOWN, &priv->state)))
2766 netif_wake_subqueue(priv->ndev, tqi);
2768 /* Update dirty indicators */
2769 tx_queue->skb_dirtytx = skb_dirtytx;
2770 tx_queue->dirty_tx = bdp;
2772 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2775 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2780 page = dev_alloc_page();
2781 if (unlikely(!page))
2784 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2785 if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2793 rxb->page_offset = 0;
2798 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2800 struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2801 struct gfar_extra_stats *estats = &priv->extra_stats;
2803 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2804 atomic64_inc(&estats->rx_alloc_err);
2807 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2811 struct gfar_rx_buff *rxb;
2814 i = rx_queue->next_to_use;
2815 bdp = &rx_queue->rx_bd_base[i];
2816 rxb = &rx_queue->rx_buff[i];
2818 while (alloc_cnt--) {
2819 /* try reuse page */
2820 if (unlikely(!rxb->page)) {
2821 if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2822 gfar_rx_alloc_err(rx_queue);
2827 /* Setup the new RxBD */
2828 gfar_init_rxbdp(rx_queue, bdp,
2829 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2831 /* Update to the next pointer */
2835 if (unlikely(++i == rx_queue->rx_ring_size)) {
2837 bdp = rx_queue->rx_bd_base;
2838 rxb = rx_queue->rx_buff;
2842 rx_queue->next_to_use = i;
2843 rx_queue->next_to_alloc = i;
2846 static void count_errors(u32 lstatus, struct net_device *ndev)
2848 struct gfar_private *priv = netdev_priv(ndev);
2849 struct net_device_stats *stats = &ndev->stats;
2850 struct gfar_extra_stats *estats = &priv->extra_stats;
2852 /* If the packet was truncated, none of the other errors matter */
2853 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2854 stats->rx_length_errors++;
2856 atomic64_inc(&estats->rx_trunc);
2860 /* Count the errors, if there were any */
2861 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2862 stats->rx_length_errors++;
2864 if (lstatus & BD_LFLAG(RXBD_LARGE))
2865 atomic64_inc(&estats->rx_large);
2867 atomic64_inc(&estats->rx_short);
2869 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2870 stats->rx_frame_errors++;
2871 atomic64_inc(&estats->rx_nonoctet);
2873 if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2874 atomic64_inc(&estats->rx_crcerr);
2875 stats->rx_crc_errors++;
2877 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2878 atomic64_inc(&estats->rx_overrun);
2879 stats->rx_over_errors++;
2883 irqreturn_t gfar_receive(int irq, void *grp_id)
2885 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2886 unsigned long flags;
2889 ievent = gfar_read(&grp->regs->ievent);
2891 if (unlikely(ievent & IEVENT_FGPI)) {
2892 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2896 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2897 spin_lock_irqsave(&grp->grplock, flags);
2898 imask = gfar_read(&grp->regs->imask);
2899 imask &= IMASK_RX_DISABLED;
2900 gfar_write(&grp->regs->imask, imask);
2901 spin_unlock_irqrestore(&grp->grplock, flags);
2902 __napi_schedule(&grp->napi_rx);
2904 /* Clear IEVENT, so interrupts aren't called again
2905 * because of the packets that have already arrived.
2907 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2913 /* Interrupt Handler for Transmit complete */
2914 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2916 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2917 unsigned long flags;
2920 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2921 spin_lock_irqsave(&grp->grplock, flags);
2922 imask = gfar_read(&grp->regs->imask);
2923 imask &= IMASK_TX_DISABLED;
2924 gfar_write(&grp->regs->imask, imask);
2925 spin_unlock_irqrestore(&grp->grplock, flags);
2926 __napi_schedule(&grp->napi_tx);
2928 /* Clear IEVENT, so interrupts aren't called again
2929 * because of the packets that have already arrived.
2931 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2937 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2938 struct sk_buff *skb, bool first)
2940 int size = lstatus & BD_LENGTH_MASK;
2941 struct page *page = rxb->page;
2943 if (likely(first)) {
2946 /* the last fragments' length contains the full frame length */
2947 if (lstatus & BD_LFLAG(RXBD_LAST))
2950 WARN(size < 0, "gianfar: rx fragment size underflow");
2954 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2955 rxb->page_offset + RXBUF_ALIGNMENT,
2956 size, GFAR_RXB_TRUESIZE);
2959 /* try reuse page */
2960 if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page)))
2963 /* change offset to the other half */
2964 rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2971 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2972 struct gfar_rx_buff *old_rxb)
2974 struct gfar_rx_buff *new_rxb;
2975 u16 nta = rxq->next_to_alloc;
2977 new_rxb = &rxq->rx_buff[nta];
2979 /* find next buf that can reuse a page */
2981 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2983 /* copy page reference */
2984 *new_rxb = *old_rxb;
2986 /* sync for use by the device */
2987 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2988 old_rxb->page_offset,
2989 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2992 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2993 u32 lstatus, struct sk_buff *skb)
2995 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2996 struct page *page = rxb->page;
3000 void *buff_addr = page_address(page) + rxb->page_offset;
3002 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
3003 if (unlikely(!skb)) {
3004 gfar_rx_alloc_err(rx_queue);
3007 skb_reserve(skb, RXBUF_ALIGNMENT);
3011 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
3012 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
3014 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
3015 /* reuse the free half of the page */
3016 gfar_reuse_rx_page(rx_queue, rxb);
3018 /* page cannot be reused, unmap it */
3019 dma_unmap_page(rx_queue->dev, rxb->dma,
3020 PAGE_SIZE, DMA_FROM_DEVICE);
3023 /* clear rxb content */
3029 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
3031 /* If valid headers were found, and valid sums
3032 * were verified, then we tell the kernel that no
3033 * checksumming is necessary. Otherwise, it is [FIXME]
3035 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
3036 (RXFCB_CIP | RXFCB_CTU))
3037 skb->ip_summed = CHECKSUM_UNNECESSARY;
3039 skb_checksum_none_assert(skb);
3042 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
3043 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
3045 struct gfar_private *priv = netdev_priv(ndev);
3046 struct rxfcb *fcb = NULL;
3048 /* fcb is at the beginning if exists */
3049 fcb = (struct rxfcb *)skb->data;
3051 /* Remove the FCB from the skb
3052 * Remove the padded bytes, if there are any
3054 if (priv->uses_rxfcb)
3055 skb_pull(skb, GMAC_FCB_LEN);
3057 /* Get receive timestamp from the skb */
3058 if (priv->hwts_rx_en) {
3059 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
3060 u64 *ns = (u64 *) skb->data;
3062 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3063 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
3067 skb_pull(skb, priv->padding);
3069 /* Trim off the FCS */
3070 pskb_trim(skb, skb->len - ETH_FCS_LEN);
3072 if (ndev->features & NETIF_F_RXCSUM)
3073 gfar_rx_checksum(skb, fcb);
3075 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
3076 * Even if vlan rx accel is disabled, on some chips
3077 * RXFCB_VLN is pseudo randomly set.
3079 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3080 be16_to_cpu(fcb->flags) & RXFCB_VLN)
3081 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3082 be16_to_cpu(fcb->vlctl));
3085 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
3086 * until the budget/quota has been reached. Returns the number
3089 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
3091 struct net_device *ndev = rx_queue->ndev;
3092 struct gfar_private *priv = netdev_priv(ndev);
3095 struct sk_buff *skb = rx_queue->skb;
3096 int cleaned_cnt = gfar_rxbd_unused(rx_queue);
3097 unsigned int total_bytes = 0, total_pkts = 0;
3099 /* Get the first full descriptor */
3100 i = rx_queue->next_to_clean;
3102 while (rx_work_limit--) {
3105 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
3106 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3110 bdp = &rx_queue->rx_bd_base[i];
3111 lstatus = be32_to_cpu(bdp->lstatus);
3112 if (lstatus & BD_LFLAG(RXBD_EMPTY))
3115 /* lost RXBD_LAST descriptor due to overrun */
3117 (lstatus & BD_LFLAG(RXBD_FIRST))) {
3118 /* discard faulty buffer */
3121 rx_queue->stats.rx_dropped++;
3123 /* can continue normally */
3126 /* order rx buffer descriptor reads */
3129 /* fetch next to clean buffer from the ring */
3130 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
3137 if (unlikely(++i == rx_queue->rx_ring_size))
3140 rx_queue->next_to_clean = i;
3142 /* fetch next buffer if not the last in frame */
3143 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
3146 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
3147 count_errors(lstatus, ndev);
3149 /* discard faulty buffer */
3152 rx_queue->stats.rx_dropped++;
3156 gfar_process_frame(ndev, skb);
3158 /* Increment the number of packets */
3160 total_bytes += skb->len;
3162 skb_record_rx_queue(skb, rx_queue->qindex);
3164 skb->protocol = eth_type_trans(skb, ndev);
3166 /* Send the packet up the stack */
3167 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3172 /* Store incomplete frames for completion */
3173 rx_queue->skb = skb;
3175 rx_queue->stats.rx_packets += total_pkts;
3176 rx_queue->stats.rx_bytes += total_bytes;
3179 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3181 /* Update Last Free RxBD pointer for LFC */
3182 if (unlikely(priv->tx_actual_en)) {
3183 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3185 gfar_write(rx_queue->rfbptr, bdp_dma);
3191 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3193 struct gfar_priv_grp *gfargrp =
3194 container_of(napi, struct gfar_priv_grp, napi_rx);
3195 struct gfar __iomem *regs = gfargrp->regs;
3196 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3199 /* Clear IEVENT, so interrupts aren't called again
3200 * because of the packets that have already arrived
3202 gfar_write(®s->ievent, IEVENT_RX_MASK);
3204 work_done = gfar_clean_rx_ring(rx_queue, budget);
3206 if (work_done < budget) {
3208 napi_complete(napi);
3209 /* Clear the halt bit in RSTAT */
3210 gfar_write(®s->rstat, gfargrp->rstat);
3212 spin_lock_irq(&gfargrp->grplock);
3213 imask = gfar_read(®s->imask);
3214 imask |= IMASK_RX_DEFAULT;
3215 gfar_write(®s->imask, imask);
3216 spin_unlock_irq(&gfargrp->grplock);
3222 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3224 struct gfar_priv_grp *gfargrp =
3225 container_of(napi, struct gfar_priv_grp, napi_tx);
3226 struct gfar __iomem *regs = gfargrp->regs;
3227 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3230 /* Clear IEVENT, so interrupts aren't called again
3231 * because of the packets that have already arrived
3233 gfar_write(®s->ievent, IEVENT_TX_MASK);
3235 /* run Tx cleanup to completion */
3236 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3237 gfar_clean_tx_ring(tx_queue);
3239 napi_complete(napi);
3241 spin_lock_irq(&gfargrp->grplock);
3242 imask = gfar_read(®s->imask);
3243 imask |= IMASK_TX_DEFAULT;
3244 gfar_write(®s->imask, imask);
3245 spin_unlock_irq(&gfargrp->grplock);
3250 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3252 struct gfar_priv_grp *gfargrp =
3253 container_of(napi, struct gfar_priv_grp, napi_rx);
3254 struct gfar_private *priv = gfargrp->priv;
3255 struct gfar __iomem *regs = gfargrp->regs;
3256 struct gfar_priv_rx_q *rx_queue = NULL;
3257 int work_done = 0, work_done_per_q = 0;
3258 int i, budget_per_q = 0;
3259 unsigned long rstat_rxf;
3262 /* Clear IEVENT, so interrupts aren't called again
3263 * because of the packets that have already arrived
3265 gfar_write(®s->ievent, IEVENT_RX_MASK);
3267 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
3269 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3271 budget_per_q = budget/num_act_queues;
3273 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3274 /* skip queue if not active */
3275 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3278 rx_queue = priv->rx_queue[i];
3280 gfar_clean_rx_ring(rx_queue, budget_per_q);
3281 work_done += work_done_per_q;
3283 /* finished processing this queue */
3284 if (work_done_per_q < budget_per_q) {
3285 /* clear active queue hw indication */
3286 gfar_write(®s->rstat,
3287 RSTAT_CLEAR_RXF0 >> i);
3290 if (!num_act_queues)
3295 if (!num_act_queues) {
3297 napi_complete(napi);
3299 /* Clear the halt bit in RSTAT */
3300 gfar_write(®s->rstat, gfargrp->rstat);
3302 spin_lock_irq(&gfargrp->grplock);
3303 imask = gfar_read(®s->imask);
3304 imask |= IMASK_RX_DEFAULT;
3305 gfar_write(®s->imask, imask);
3306 spin_unlock_irq(&gfargrp->grplock);
3312 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3314 struct gfar_priv_grp *gfargrp =
3315 container_of(napi, struct gfar_priv_grp, napi_tx);
3316 struct gfar_private *priv = gfargrp->priv;
3317 struct gfar __iomem *regs = gfargrp->regs;
3318 struct gfar_priv_tx_q *tx_queue = NULL;
3319 int has_tx_work = 0;
3322 /* Clear IEVENT, so interrupts aren't called again
3323 * because of the packets that have already arrived
3325 gfar_write(®s->ievent, IEVENT_TX_MASK);
3327 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3328 tx_queue = priv->tx_queue[i];
3329 /* run Tx cleanup to completion */
3330 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3331 gfar_clean_tx_ring(tx_queue);
3338 napi_complete(napi);
3340 spin_lock_irq(&gfargrp->grplock);
3341 imask = gfar_read(®s->imask);
3342 imask |= IMASK_TX_DEFAULT;
3343 gfar_write(®s->imask, imask);
3344 spin_unlock_irq(&gfargrp->grplock);
3351 #ifdef CONFIG_NET_POLL_CONTROLLER
3352 /* Polling 'interrupt' - used by things like netconsole to send skbs
3353 * without having to re-enable interrupts. It's not called while
3354 * the interrupt routine is executing.
3356 static void gfar_netpoll(struct net_device *dev)
3358 struct gfar_private *priv = netdev_priv(dev);
3361 /* If the device has multiple interrupts, run tx/rx */
3362 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3363 for (i = 0; i < priv->num_grps; i++) {
3364 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3366 disable_irq(gfar_irq(grp, TX)->irq);
3367 disable_irq(gfar_irq(grp, RX)->irq);
3368 disable_irq(gfar_irq(grp, ER)->irq);
3369 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3370 enable_irq(gfar_irq(grp, ER)->irq);
3371 enable_irq(gfar_irq(grp, RX)->irq);
3372 enable_irq(gfar_irq(grp, TX)->irq);
3375 for (i = 0; i < priv->num_grps; i++) {
3376 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3378 disable_irq(gfar_irq(grp, TX)->irq);
3379 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3380 enable_irq(gfar_irq(grp, TX)->irq);
3386 /* The interrupt handler for devices with one interrupt */
3387 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3389 struct gfar_priv_grp *gfargrp = grp_id;
3391 /* Save ievent for future reference */
3392 u32 events = gfar_read(&gfargrp->regs->ievent);
3394 /* Check for reception */
3395 if (events & IEVENT_RX_MASK)
3396 gfar_receive(irq, grp_id);
3398 /* Check for transmit completion */
3399 if (events & IEVENT_TX_MASK)
3400 gfar_transmit(irq, grp_id);
3402 /* Check for errors */
3403 if (events & IEVENT_ERR_MASK)
3404 gfar_error(irq, grp_id);
3409 /* Called every time the controller might need to be made
3410 * aware of new link state. The PHY code conveys this
3411 * information through variables in the phydev structure, and this
3412 * function converts those variables into the appropriate
3413 * register values, and can bring down the device if needed.
3415 static void adjust_link(struct net_device *dev)
3417 struct gfar_private *priv = netdev_priv(dev);
3418 struct phy_device *phydev = dev->phydev;
3420 if (unlikely(phydev->link != priv->oldlink ||
3421 (phydev->link && (phydev->duplex != priv->oldduplex ||
3422 phydev->speed != priv->oldspeed))))
3423 gfar_update_link_state(priv);
3426 /* Update the hash table based on the current list of multicast
3427 * addresses we subscribe to. Also, change the promiscuity of
3428 * the device based on the flags (this function is called
3429 * whenever dev->flags is changed
3431 static void gfar_set_multi(struct net_device *dev)
3433 struct netdev_hw_addr *ha;
3434 struct gfar_private *priv = netdev_priv(dev);
3435 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3438 if (dev->flags & IFF_PROMISC) {
3439 /* Set RCTRL to PROM */
3440 tempval = gfar_read(®s->rctrl);
3441 tempval |= RCTRL_PROM;
3442 gfar_write(®s->rctrl, tempval);
3444 /* Set RCTRL to not PROM */
3445 tempval = gfar_read(®s->rctrl);
3446 tempval &= ~(RCTRL_PROM);
3447 gfar_write(®s->rctrl, tempval);
3450 if (dev->flags & IFF_ALLMULTI) {
3451 /* Set the hash to rx all multicast frames */
3452 gfar_write(®s->igaddr0, 0xffffffff);
3453 gfar_write(®s->igaddr1, 0xffffffff);
3454 gfar_write(®s->igaddr2, 0xffffffff);
3455 gfar_write(®s->igaddr3, 0xffffffff);
3456 gfar_write(®s->igaddr4, 0xffffffff);
3457 gfar_write(®s->igaddr5, 0xffffffff);
3458 gfar_write(®s->igaddr6, 0xffffffff);
3459 gfar_write(®s->igaddr7, 0xffffffff);
3460 gfar_write(®s->gaddr0, 0xffffffff);
3461 gfar_write(®s->gaddr1, 0xffffffff);
3462 gfar_write(®s->gaddr2, 0xffffffff);
3463 gfar_write(®s->gaddr3, 0xffffffff);
3464 gfar_write(®s->gaddr4, 0xffffffff);
3465 gfar_write(®s->gaddr5, 0xffffffff);
3466 gfar_write(®s->gaddr6, 0xffffffff);
3467 gfar_write(®s->gaddr7, 0xffffffff);
3472 /* zero out the hash */
3473 gfar_write(®s->igaddr0, 0x0);
3474 gfar_write(®s->igaddr1, 0x0);
3475 gfar_write(®s->igaddr2, 0x0);
3476 gfar_write(®s->igaddr3, 0x0);
3477 gfar_write(®s->igaddr4, 0x0);
3478 gfar_write(®s->igaddr5, 0x0);
3479 gfar_write(®s->igaddr6, 0x0);
3480 gfar_write(®s->igaddr7, 0x0);
3481 gfar_write(®s->gaddr0, 0x0);
3482 gfar_write(®s->gaddr1, 0x0);
3483 gfar_write(®s->gaddr2, 0x0);
3484 gfar_write(®s->gaddr3, 0x0);
3485 gfar_write(®s->gaddr4, 0x0);
3486 gfar_write(®s->gaddr5, 0x0);
3487 gfar_write(®s->gaddr6, 0x0);
3488 gfar_write(®s->gaddr7, 0x0);
3490 /* If we have extended hash tables, we need to
3491 * clear the exact match registers to prepare for
3494 if (priv->extended_hash) {
3495 em_num = GFAR_EM_NUM + 1;
3496 gfar_clear_exact_match(dev);
3503 if (netdev_mc_empty(dev))
3506 /* Parse the list, and set the appropriate bits */
3507 netdev_for_each_mc_addr(ha, dev) {
3509 gfar_set_mac_for_addr(dev, idx, ha->addr);
3512 gfar_set_hash_for_addr(dev, ha->addr);
3518 /* Clears each of the exact match registers to zero, so they
3519 * don't interfere with normal reception
3521 static void gfar_clear_exact_match(struct net_device *dev)
3524 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3526 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3527 gfar_set_mac_for_addr(dev, idx, zero_arr);
3530 /* Set the appropriate hash bit for the given addr */
3531 /* The algorithm works like so:
3532 * 1) Take the Destination Address (ie the multicast address), and
3533 * do a CRC on it (little endian), and reverse the bits of the
3535 * 2) Use the 8 most significant bits as a hash into a 256-entry
3536 * table. The table is controlled through 8 32-bit registers:
3537 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3538 * gaddr7. This means that the 3 most significant bits in the
3539 * hash index which gaddr register to use, and the 5 other bits
3540 * indicate which bit (assuming an IBM numbering scheme, which
3541 * for PowerPC (tm) is usually the case) in the register holds
3544 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3547 struct gfar_private *priv = netdev_priv(dev);
3548 u32 result = ether_crc(ETH_ALEN, addr);
3549 int width = priv->hash_width;
3550 u8 whichbit = (result >> (32 - width)) & 0x1f;
3551 u8 whichreg = result >> (32 - width + 5);
3552 u32 value = (1 << (31-whichbit));
3554 tempval = gfar_read(priv->hash_regs[whichreg]);
3556 gfar_write(priv->hash_regs[whichreg], tempval);
3560 /* There are multiple MAC Address register pairs on some controllers
3561 * This function sets the numth pair to a given address
3563 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3566 struct gfar_private *priv = netdev_priv(dev);
3567 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3569 u32 __iomem *macptr = ®s->macstnaddr1;
3573 /* For a station address of 0x12345678ABCD in transmission
3574 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3575 * MACnADDR2 is set to 0x34120000.
3577 tempval = (addr[5] << 24) | (addr[4] << 16) |
3578 (addr[3] << 8) | addr[2];
3580 gfar_write(macptr, tempval);
3582 tempval = (addr[1] << 24) | (addr[0] << 16);
3584 gfar_write(macptr+1, tempval);
3587 /* GFAR error interrupt handler */
3588 static irqreturn_t gfar_error(int irq, void *grp_id)
3590 struct gfar_priv_grp *gfargrp = grp_id;
3591 struct gfar __iomem *regs = gfargrp->regs;
3592 struct gfar_private *priv= gfargrp->priv;
3593 struct net_device *dev = priv->ndev;
3595 /* Save ievent for future reference */
3596 u32 events = gfar_read(®s->ievent);
3599 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3601 /* Magic Packet is not an error. */
3602 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3603 (events & IEVENT_MAG))
3604 events &= ~IEVENT_MAG;
3607 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3609 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3610 events, gfar_read(®s->imask));
3612 /* Update the error counters */
3613 if (events & IEVENT_TXE) {
3614 dev->stats.tx_errors++;
3616 if (events & IEVENT_LC)
3617 dev->stats.tx_window_errors++;
3618 if (events & IEVENT_CRL)
3619 dev->stats.tx_aborted_errors++;
3620 if (events & IEVENT_XFUN) {
3621 netif_dbg(priv, tx_err, dev,
3622 "TX FIFO underrun, packet dropped\n");
3623 dev->stats.tx_dropped++;
3624 atomic64_inc(&priv->extra_stats.tx_underrun);
3626 schedule_work(&priv->reset_task);
3628 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3630 if (events & IEVENT_BSY) {
3631 dev->stats.rx_over_errors++;
3632 atomic64_inc(&priv->extra_stats.rx_bsy);
3634 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3635 gfar_read(®s->rstat));
3637 if (events & IEVENT_BABR) {
3638 dev->stats.rx_errors++;
3639 atomic64_inc(&priv->extra_stats.rx_babr);
3641 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3643 if (events & IEVENT_EBERR) {
3644 atomic64_inc(&priv->extra_stats.eberr);
3645 netif_dbg(priv, rx_err, dev, "bus error\n");
3647 if (events & IEVENT_RXC)
3648 netif_dbg(priv, rx_status, dev, "control frame\n");
3650 if (events & IEVENT_BABT) {
3651 atomic64_inc(&priv->extra_stats.tx_babt);
3652 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3657 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3659 struct net_device *ndev = priv->ndev;
3660 struct phy_device *phydev = ndev->phydev;
3663 if (!phydev->duplex)
3666 if (!priv->pause_aneg_en) {
3667 if (priv->tx_pause_en)
3668 val |= MACCFG1_TX_FLOW;
3669 if (priv->rx_pause_en)
3670 val |= MACCFG1_RX_FLOW;
3672 u16 lcl_adv, rmt_adv;
3674 /* get link partner capabilities */
3677 rmt_adv = LPA_PAUSE_CAP;
3678 if (phydev->asym_pause)
3679 rmt_adv |= LPA_PAUSE_ASYM;
3682 if (phydev->advertising & ADVERTISED_Pause)
3683 lcl_adv |= ADVERTISE_PAUSE_CAP;
3684 if (phydev->advertising & ADVERTISED_Asym_Pause)
3685 lcl_adv |= ADVERTISE_PAUSE_ASYM;
3687 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3688 if (flowctrl & FLOW_CTRL_TX)
3689 val |= MACCFG1_TX_FLOW;
3690 if (flowctrl & FLOW_CTRL_RX)
3691 val |= MACCFG1_RX_FLOW;
3697 static noinline void gfar_update_link_state(struct gfar_private *priv)
3699 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3700 struct net_device *ndev = priv->ndev;
3701 struct phy_device *phydev = ndev->phydev;
3702 struct gfar_priv_rx_q *rx_queue = NULL;
3705 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3709 u32 tempval1 = gfar_read(®s->maccfg1);
3710 u32 tempval = gfar_read(®s->maccfg2);
3711 u32 ecntrl = gfar_read(®s->ecntrl);
3712 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW);
3714 if (phydev->duplex != priv->oldduplex) {
3715 if (!(phydev->duplex))
3716 tempval &= ~(MACCFG2_FULL_DUPLEX);
3718 tempval |= MACCFG2_FULL_DUPLEX;
3720 priv->oldduplex = phydev->duplex;
3723 if (phydev->speed != priv->oldspeed) {
3724 switch (phydev->speed) {
3727 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3729 ecntrl &= ~(ECNTRL_R100);
3734 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3736 /* Reduced mode distinguishes
3737 * between 10 and 100
3739 if (phydev->speed == SPEED_100)
3740 ecntrl |= ECNTRL_R100;
3742 ecntrl &= ~(ECNTRL_R100);
3745 netif_warn(priv, link, priv->ndev,
3746 "Ack! Speed (%d) is not 10/100/1000!\n",
3751 priv->oldspeed = phydev->speed;
3754 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3755 tempval1 |= gfar_get_flowctrl_cfg(priv);
3757 /* Turn last free buffer recording on */
3758 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3759 for (i = 0; i < priv->num_rx_queues; i++) {
3762 rx_queue = priv->rx_queue[i];
3763 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3764 gfar_write(rx_queue->rfbptr, bdp_dma);
3767 priv->tx_actual_en = 1;
3770 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3771 priv->tx_actual_en = 0;
3773 gfar_write(®s->maccfg1, tempval1);
3774 gfar_write(®s->maccfg2, tempval);
3775 gfar_write(®s->ecntrl, ecntrl);
3780 } else if (priv->oldlink) {
3783 priv->oldduplex = -1;
3786 if (netif_msg_link(priv))
3787 phy_print_status(phydev);
3790 static const struct of_device_id gfar_match[] =
3794 .compatible = "gianfar",
3797 .compatible = "fsl,etsec2",
3801 MODULE_DEVICE_TABLE(of, gfar_match);
3803 /* Structure for a device driver */
3804 static struct platform_driver gfar_driver = {
3806 .name = "fsl-gianfar",
3808 .of_match_table = gfar_match,
3810 .probe = gfar_probe,
3811 .remove = gfar_remove,
3814 module_platform_driver(gfar_driver);