1 /* drivers/net/ethernet/freescale/gianfar.c
3 * Gianfar Ethernet Driver
4 * This driver is designed for the non-CPM ethernet controllers
5 * on the 85xx and 83xx family of integrated processors
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/delay.h>
74 #include <linux/netdevice.h>
75 #include <linux/etherdevice.h>
76 #include <linux/skbuff.h>
77 #include <linux/if_vlan.h>
78 #include <linux/spinlock.h>
80 #include <linux/of_address.h>
81 #include <linux/of_irq.h>
82 #include <linux/of_mdio.h>
83 #include <linux/of_platform.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
88 #include <linux/net_tstamp.h>
93 #include <asm/mpc85xx.h>
96 #include <asm/uaccess.h>
97 #include <linux/module.h>
98 #include <linux/dma-mapping.h>
99 #include <linux/crc32.h>
100 #include <linux/mii.h>
101 #include <linux/phy.h>
102 #include <linux/phy_fixed.h>
103 #include <linux/of.h>
104 #include <linux/of_net.h>
105 #include <linux/of_address.h>
106 #include <linux/of_irq.h>
110 #define TX_TIMEOUT (5*HZ)
112 const char gfar_driver_version[] = "2.0";
114 static int gfar_enet_open(struct net_device *dev);
115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
116 static void gfar_reset_task(struct work_struct *work);
117 static void gfar_timeout(struct net_device *dev);
118 static int gfar_close(struct net_device *dev);
119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
121 static int gfar_set_mac_address(struct net_device *dev);
122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
123 static irqreturn_t gfar_error(int irq, void *dev_id);
124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
126 static void adjust_link(struct net_device *dev);
127 static noinline void gfar_update_link_state(struct gfar_private *priv);
128 static int init_phy(struct net_device *dev);
129 static int gfar_probe(struct platform_device *ofdev);
130 static int gfar_remove(struct platform_device *ofdev);
131 static void free_skb_resources(struct gfar_private *priv);
132 static void gfar_set_multi(struct net_device *dev);
133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
134 static void gfar_configure_serdes(struct net_device *dev);
135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
139 #ifdef CONFIG_NET_POLL_CONTROLLER
140 static void gfar_netpoll(struct net_device *dev);
142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
145 static void gfar_halt_nodisable(struct gfar_private *priv);
146 static void gfar_clear_exact_match(struct net_device *dev);
147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
153 MODULE_LICENSE("GPL");
155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
160 bdp->bufPtr = cpu_to_be32(buf);
162 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
163 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
164 lstatus |= BD_LFLAG(RXBD_WRAP);
168 bdp->lstatus = cpu_to_be32(lstatus);
171 static void gfar_init_bds(struct net_device *ndev)
173 struct gfar_private *priv = netdev_priv(ndev);
174 struct gfar __iomem *regs = priv->gfargrp[0].regs;
175 struct gfar_priv_tx_q *tx_queue = NULL;
176 struct gfar_priv_rx_q *rx_queue = NULL;
181 for (i = 0; i < priv->num_tx_queues; i++) {
182 tx_queue = priv->tx_queue[i];
183 /* Initialize some variables in our dev structure */
184 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
185 tx_queue->dirty_tx = tx_queue->tx_bd_base;
186 tx_queue->cur_tx = tx_queue->tx_bd_base;
187 tx_queue->skb_curtx = 0;
188 tx_queue->skb_dirtytx = 0;
190 /* Initialize Transmit Descriptor Ring */
191 txbdp = tx_queue->tx_bd_base;
192 for (j = 0; j < tx_queue->tx_ring_size; j++) {
198 /* Set the last descriptor in the ring to indicate wrap */
200 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
204 rfbptr = ®s->rfbptr0;
205 for (i = 0; i < priv->num_rx_queues; i++) {
206 rx_queue = priv->rx_queue[i];
208 rx_queue->next_to_clean = 0;
209 rx_queue->next_to_use = 0;
210 rx_queue->next_to_alloc = 0;
212 /* make sure next_to_clean != next_to_use after this
213 * by leaving at least 1 unused descriptor
215 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
217 rx_queue->rfbptr = rfbptr;
222 static int gfar_alloc_skb_resources(struct net_device *ndev)
227 struct gfar_private *priv = netdev_priv(ndev);
228 struct device *dev = priv->dev;
229 struct gfar_priv_tx_q *tx_queue = NULL;
230 struct gfar_priv_rx_q *rx_queue = NULL;
232 priv->total_tx_ring_size = 0;
233 for (i = 0; i < priv->num_tx_queues; i++)
234 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
236 priv->total_rx_ring_size = 0;
237 for (i = 0; i < priv->num_rx_queues; i++)
238 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
240 /* Allocate memory for the buffer descriptors */
241 vaddr = dma_alloc_coherent(dev,
242 (priv->total_tx_ring_size *
243 sizeof(struct txbd8)) +
244 (priv->total_rx_ring_size *
245 sizeof(struct rxbd8)),
250 for (i = 0; i < priv->num_tx_queues; i++) {
251 tx_queue = priv->tx_queue[i];
252 tx_queue->tx_bd_base = vaddr;
253 tx_queue->tx_bd_dma_base = addr;
254 tx_queue->dev = ndev;
255 /* enet DMA only understands physical addresses */
256 addr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
257 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
260 /* Start the rx descriptor ring where the tx ring leaves off */
261 for (i = 0; i < priv->num_rx_queues; i++) {
262 rx_queue = priv->rx_queue[i];
263 rx_queue->rx_bd_base = vaddr;
264 rx_queue->rx_bd_dma_base = addr;
265 rx_queue->ndev = ndev;
267 addr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
268 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
271 /* Setup the skbuff rings */
272 for (i = 0; i < priv->num_tx_queues; i++) {
273 tx_queue = priv->tx_queue[i];
274 tx_queue->tx_skbuff =
275 kmalloc_array(tx_queue->tx_ring_size,
276 sizeof(*tx_queue->tx_skbuff),
278 if (!tx_queue->tx_skbuff)
281 for (j = 0; j < tx_queue->tx_ring_size; j++)
282 tx_queue->tx_skbuff[j] = NULL;
285 for (i = 0; i < priv->num_rx_queues; i++) {
286 rx_queue = priv->rx_queue[i];
287 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
288 sizeof(*rx_queue->rx_buff),
290 if (!rx_queue->rx_buff)
299 free_skb_resources(priv);
303 static void gfar_init_tx_rx_base(struct gfar_private *priv)
305 struct gfar __iomem *regs = priv->gfargrp[0].regs;
309 baddr = ®s->tbase0;
310 for (i = 0; i < priv->num_tx_queues; i++) {
311 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
315 baddr = ®s->rbase0;
316 for (i = 0; i < priv->num_rx_queues; i++) {
317 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
322 static void gfar_init_rqprm(struct gfar_private *priv)
324 struct gfar __iomem *regs = priv->gfargrp[0].regs;
328 baddr = ®s->rqprm0;
329 for (i = 0; i < priv->num_rx_queues; i++) {
330 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
331 (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
336 static void gfar_rx_offload_en(struct gfar_private *priv)
338 /* set this when rx hw offload (TOE) functions are being used */
339 priv->uses_rxfcb = 0;
341 if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
342 priv->uses_rxfcb = 1;
344 if (priv->hwts_rx_en || priv->rx_filer_enable)
345 priv->uses_rxfcb = 1;
348 static void gfar_mac_rx_config(struct gfar_private *priv)
350 struct gfar __iomem *regs = priv->gfargrp[0].regs;
353 if (priv->rx_filer_enable) {
354 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
355 /* Program the RIR0 reg with the required distribution */
356 if (priv->poll_mode == GFAR_SQ_POLLING)
357 gfar_write(®s->rir0, DEFAULT_2RXQ_RIR0);
358 else /* GFAR_MQ_POLLING */
359 gfar_write(®s->rir0, DEFAULT_8RXQ_RIR0);
362 /* Restore PROMISC mode */
363 if (priv->ndev->flags & IFF_PROMISC)
366 if (priv->ndev->features & NETIF_F_RXCSUM)
367 rctrl |= RCTRL_CHECKSUMMING;
369 if (priv->extended_hash)
370 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
373 rctrl &= ~RCTRL_PAL_MASK;
374 rctrl |= RCTRL_PADDING(priv->padding);
377 /* Enable HW time stamping if requested from user space */
378 if (priv->hwts_rx_en)
379 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
381 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
382 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
384 /* Clear the LFC bit */
385 gfar_write(®s->rctrl, rctrl);
386 /* Init flow control threshold values */
387 gfar_init_rqprm(priv);
388 gfar_write(®s->ptv, DEFAULT_LFC_PTVVAL);
391 /* Init rctrl based on our settings */
392 gfar_write(®s->rctrl, rctrl);
395 static void gfar_mac_tx_config(struct gfar_private *priv)
397 struct gfar __iomem *regs = priv->gfargrp[0].regs;
400 if (priv->ndev->features & NETIF_F_IP_CSUM)
401 tctrl |= TCTRL_INIT_CSUM;
403 if (priv->prio_sched_en)
404 tctrl |= TCTRL_TXSCHED_PRIO;
406 tctrl |= TCTRL_TXSCHED_WRRS;
407 gfar_write(®s->tr03wt, DEFAULT_WRRS_WEIGHT);
408 gfar_write(®s->tr47wt, DEFAULT_WRRS_WEIGHT);
411 if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
412 tctrl |= TCTRL_VLINS;
414 gfar_write(®s->tctrl, tctrl);
417 static void gfar_configure_coalescing(struct gfar_private *priv,
418 unsigned long tx_mask, unsigned long rx_mask)
420 struct gfar __iomem *regs = priv->gfargrp[0].regs;
423 if (priv->mode == MQ_MG_MODE) {
426 baddr = ®s->txic0;
427 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
428 gfar_write(baddr + i, 0);
429 if (likely(priv->tx_queue[i]->txcoalescing))
430 gfar_write(baddr + i, priv->tx_queue[i]->txic);
433 baddr = ®s->rxic0;
434 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
435 gfar_write(baddr + i, 0);
436 if (likely(priv->rx_queue[i]->rxcoalescing))
437 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
440 /* Backward compatible case -- even if we enable
441 * multiple queues, there's only single reg to program
443 gfar_write(®s->txic, 0);
444 if (likely(priv->tx_queue[0]->txcoalescing))
445 gfar_write(®s->txic, priv->tx_queue[0]->txic);
447 gfar_write(®s->rxic, 0);
448 if (unlikely(priv->rx_queue[0]->rxcoalescing))
449 gfar_write(®s->rxic, priv->rx_queue[0]->rxic);
453 void gfar_configure_coalescing_all(struct gfar_private *priv)
455 gfar_configure_coalescing(priv, 0xFF, 0xFF);
458 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
460 struct gfar_private *priv = netdev_priv(dev);
461 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
462 unsigned long tx_packets = 0, tx_bytes = 0;
465 for (i = 0; i < priv->num_rx_queues; i++) {
466 rx_packets += priv->rx_queue[i]->stats.rx_packets;
467 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
468 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
471 dev->stats.rx_packets = rx_packets;
472 dev->stats.rx_bytes = rx_bytes;
473 dev->stats.rx_dropped = rx_dropped;
475 for (i = 0; i < priv->num_tx_queues; i++) {
476 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
477 tx_packets += priv->tx_queue[i]->stats.tx_packets;
480 dev->stats.tx_bytes = tx_bytes;
481 dev->stats.tx_packets = tx_packets;
486 static int gfar_set_mac_addr(struct net_device *dev, void *p)
490 ret = eth_mac_addr(dev, p);
494 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
499 static const struct net_device_ops gfar_netdev_ops = {
500 .ndo_open = gfar_enet_open,
501 .ndo_start_xmit = gfar_start_xmit,
502 .ndo_stop = gfar_close,
503 .ndo_change_mtu = gfar_change_mtu,
504 .ndo_set_features = gfar_set_features,
505 .ndo_set_rx_mode = gfar_set_multi,
506 .ndo_tx_timeout = gfar_timeout,
507 .ndo_do_ioctl = gfar_ioctl,
508 .ndo_get_stats = gfar_get_stats,
509 .ndo_set_mac_address = gfar_set_mac_addr,
510 .ndo_validate_addr = eth_validate_addr,
511 #ifdef CONFIG_NET_POLL_CONTROLLER
512 .ndo_poll_controller = gfar_netpoll,
516 static void gfar_ints_disable(struct gfar_private *priv)
519 for (i = 0; i < priv->num_grps; i++) {
520 struct gfar __iomem *regs = priv->gfargrp[i].regs;
522 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
524 /* Initialize IMASK */
525 gfar_write(®s->imask, IMASK_INIT_CLEAR);
529 static void gfar_ints_enable(struct gfar_private *priv)
532 for (i = 0; i < priv->num_grps; i++) {
533 struct gfar __iomem *regs = priv->gfargrp[i].regs;
534 /* Unmask the interrupts we look for */
535 gfar_write(®s->imask, IMASK_DEFAULT);
539 static int gfar_alloc_tx_queues(struct gfar_private *priv)
543 for (i = 0; i < priv->num_tx_queues; i++) {
544 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
546 if (!priv->tx_queue[i])
549 priv->tx_queue[i]->tx_skbuff = NULL;
550 priv->tx_queue[i]->qindex = i;
551 priv->tx_queue[i]->dev = priv->ndev;
552 spin_lock_init(&(priv->tx_queue[i]->txlock));
557 static int gfar_alloc_rx_queues(struct gfar_private *priv)
561 for (i = 0; i < priv->num_rx_queues; i++) {
562 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
564 if (!priv->rx_queue[i])
567 priv->rx_queue[i]->qindex = i;
568 priv->rx_queue[i]->ndev = priv->ndev;
573 static void gfar_free_tx_queues(struct gfar_private *priv)
577 for (i = 0; i < priv->num_tx_queues; i++)
578 kfree(priv->tx_queue[i]);
581 static void gfar_free_rx_queues(struct gfar_private *priv)
585 for (i = 0; i < priv->num_rx_queues; i++)
586 kfree(priv->rx_queue[i]);
589 static void unmap_group_regs(struct gfar_private *priv)
593 for (i = 0; i < MAXGROUPS; i++)
594 if (priv->gfargrp[i].regs)
595 iounmap(priv->gfargrp[i].regs);
598 static void free_gfar_dev(struct gfar_private *priv)
602 for (i = 0; i < priv->num_grps; i++)
603 for (j = 0; j < GFAR_NUM_IRQS; j++) {
604 kfree(priv->gfargrp[i].irqinfo[j]);
605 priv->gfargrp[i].irqinfo[j] = NULL;
608 free_netdev(priv->ndev);
611 static void disable_napi(struct gfar_private *priv)
615 for (i = 0; i < priv->num_grps; i++) {
616 napi_disable(&priv->gfargrp[i].napi_rx);
617 napi_disable(&priv->gfargrp[i].napi_tx);
621 static void enable_napi(struct gfar_private *priv)
625 for (i = 0; i < priv->num_grps; i++) {
626 napi_enable(&priv->gfargrp[i].napi_rx);
627 napi_enable(&priv->gfargrp[i].napi_tx);
631 static int gfar_parse_group(struct device_node *np,
632 struct gfar_private *priv, const char *model)
634 struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
637 for (i = 0; i < GFAR_NUM_IRQS; i++) {
638 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
640 if (!grp->irqinfo[i])
644 grp->regs = of_iomap(np, 0);
648 gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
650 /* If we aren't the FEC we have multiple interrupts */
651 if (model && strcasecmp(model, "FEC")) {
652 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
653 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
654 if (!gfar_irq(grp, TX)->irq ||
655 !gfar_irq(grp, RX)->irq ||
656 !gfar_irq(grp, ER)->irq)
661 spin_lock_init(&grp->grplock);
662 if (priv->mode == MQ_MG_MODE) {
663 u32 rxq_mask, txq_mask;
666 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
667 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
669 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
671 grp->rx_bit_map = rxq_mask ?
672 rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
675 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
677 grp->tx_bit_map = txq_mask ?
678 txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
681 if (priv->poll_mode == GFAR_SQ_POLLING) {
682 /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
683 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
684 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
687 grp->rx_bit_map = 0xFF;
688 grp->tx_bit_map = 0xFF;
691 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
692 * right to left, so we need to revert the 8 bits to get the q index
694 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
695 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
697 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
698 * also assign queues to groups
700 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
702 grp->rx_queue = priv->rx_queue[i];
703 grp->num_rx_queues++;
704 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
705 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
706 priv->rx_queue[i]->grp = grp;
709 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
711 grp->tx_queue = priv->tx_queue[i];
712 grp->num_tx_queues++;
713 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
714 priv->tqueue |= (TQUEUE_EN0 >> i);
715 priv->tx_queue[i]->grp = grp;
723 static int gfar_of_group_count(struct device_node *np)
725 struct device_node *child;
728 for_each_available_child_of_node(np, child)
729 if (!of_node_cmp(child->name, "queue-group"))
735 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
739 const void *mac_addr;
741 struct net_device *dev = NULL;
742 struct gfar_private *priv = NULL;
743 struct device_node *np = ofdev->dev.of_node;
744 struct device_node *child = NULL;
745 struct property *stash;
748 unsigned int num_tx_qs, num_rx_qs;
749 unsigned short mode, poll_mode;
754 if (of_device_is_compatible(np, "fsl,etsec2")) {
756 poll_mode = GFAR_SQ_POLLING;
759 poll_mode = GFAR_SQ_POLLING;
762 if (mode == SQ_SG_MODE) {
765 } else { /* MQ_MG_MODE */
766 /* get the actual number of supported groups */
767 unsigned int num_grps = gfar_of_group_count(np);
769 if (num_grps == 0 || num_grps > MAXGROUPS) {
770 dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
772 pr_err("Cannot do alloc_etherdev, aborting\n");
776 if (poll_mode == GFAR_SQ_POLLING) {
777 num_tx_qs = num_grps; /* one txq per int group */
778 num_rx_qs = num_grps; /* one rxq per int group */
779 } else { /* GFAR_MQ_POLLING */
780 u32 tx_queues, rx_queues;
783 /* parse the num of HW tx and rx queues */
784 ret = of_property_read_u32(np, "fsl,num_tx_queues",
786 num_tx_qs = ret ? 1 : tx_queues;
788 ret = of_property_read_u32(np, "fsl,num_rx_queues",
790 num_rx_qs = ret ? 1 : rx_queues;
794 if (num_tx_qs > MAX_TX_QS) {
795 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
796 num_tx_qs, MAX_TX_QS);
797 pr_err("Cannot do alloc_etherdev, aborting\n");
801 if (num_rx_qs > MAX_RX_QS) {
802 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
803 num_rx_qs, MAX_RX_QS);
804 pr_err("Cannot do alloc_etherdev, aborting\n");
808 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
813 priv = netdev_priv(dev);
817 priv->poll_mode = poll_mode;
819 priv->num_tx_queues = num_tx_qs;
820 netif_set_real_num_rx_queues(dev, num_rx_qs);
821 priv->num_rx_queues = num_rx_qs;
823 err = gfar_alloc_tx_queues(priv);
825 goto tx_alloc_failed;
827 err = gfar_alloc_rx_queues(priv);
829 goto rx_alloc_failed;
831 err = of_property_read_string(np, "model", &model);
833 pr_err("Device model property missing, aborting\n");
834 goto rx_alloc_failed;
837 /* Init Rx queue filer rule set linked list */
838 INIT_LIST_HEAD(&priv->rx_list.list);
839 priv->rx_list.count = 0;
840 mutex_init(&priv->rx_queue_access);
842 for (i = 0; i < MAXGROUPS; i++)
843 priv->gfargrp[i].regs = NULL;
845 /* Parse and initialize group specific information */
846 if (priv->mode == MQ_MG_MODE) {
847 for_each_available_child_of_node(np, child) {
848 if (of_node_cmp(child->name, "queue-group"))
851 err = gfar_parse_group(child, priv, model);
857 } else { /* SQ_SG_MODE */
858 err = gfar_parse_group(np, priv, model);
863 stash = of_find_property(np, "bd-stash", NULL);
866 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
867 priv->bd_stash_en = 1;
870 err = of_property_read_u32(np, "rx-stash-len", &stash_len);
873 priv->rx_stash_size = stash_len;
875 err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
878 priv->rx_stash_index = stash_idx;
880 if (stash_len || stash_idx)
881 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
883 mac_addr = of_get_mac_address(np);
886 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
888 if (model && !strcasecmp(model, "TSEC"))
889 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
890 FSL_GIANFAR_DEV_HAS_COALESCE |
891 FSL_GIANFAR_DEV_HAS_RMON |
892 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
894 if (model && !strcasecmp(model, "eTSEC"))
895 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
896 FSL_GIANFAR_DEV_HAS_COALESCE |
897 FSL_GIANFAR_DEV_HAS_RMON |
898 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
899 FSL_GIANFAR_DEV_HAS_CSUM |
900 FSL_GIANFAR_DEV_HAS_VLAN |
901 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
902 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
903 FSL_GIANFAR_DEV_HAS_TIMER |
904 FSL_GIANFAR_DEV_HAS_RX_FILER;
906 err = of_property_read_string(np, "phy-connection-type", &ctype);
908 /* We only care about rgmii-id. The rest are autodetected */
909 if (err == 0 && !strcmp(ctype, "rgmii-id"))
910 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
912 priv->interface = PHY_INTERFACE_MODE_MII;
914 if (of_find_property(np, "fsl,magic-packet", NULL))
915 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
917 if (of_get_property(np, "fsl,wake-on-filer", NULL))
918 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
920 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
922 /* In the case of a fixed PHY, the DT node associated
923 * to the PHY is the Ethernet MAC DT node.
925 if (!priv->phy_node && of_phy_is_fixed_link(np)) {
926 err = of_phy_register_fixed_link(np);
930 priv->phy_node = of_node_get(np);
933 /* Find the TBI PHY. If it's not there, we don't support SGMII */
934 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
939 unmap_group_regs(priv);
941 gfar_free_rx_queues(priv);
943 gfar_free_tx_queues(priv);
948 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
950 struct hwtstamp_config config;
951 struct gfar_private *priv = netdev_priv(netdev);
953 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
956 /* reserved for future extensions */
960 switch (config.tx_type) {
961 case HWTSTAMP_TX_OFF:
962 priv->hwts_tx_en = 0;
965 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
967 priv->hwts_tx_en = 1;
973 switch (config.rx_filter) {
974 case HWTSTAMP_FILTER_NONE:
975 if (priv->hwts_rx_en) {
976 priv->hwts_rx_en = 0;
981 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
983 if (!priv->hwts_rx_en) {
984 priv->hwts_rx_en = 1;
987 config.rx_filter = HWTSTAMP_FILTER_ALL;
991 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
995 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
997 struct hwtstamp_config config;
998 struct gfar_private *priv = netdev_priv(netdev);
1001 config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1002 config.rx_filter = (priv->hwts_rx_en ?
1003 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
1005 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1009 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1011 struct gfar_private *priv = netdev_priv(dev);
1013 if (!netif_running(dev))
1016 if (cmd == SIOCSHWTSTAMP)
1017 return gfar_hwtstamp_set(dev, rq);
1018 if (cmd == SIOCGHWTSTAMP)
1019 return gfar_hwtstamp_get(dev, rq);
1024 return phy_mii_ioctl(priv->phydev, rq, cmd);
1027 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1030 u32 rqfpr = FPR_FILER_MASK;
1034 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1035 priv->ftp_rqfpr[rqfar] = rqfpr;
1036 priv->ftp_rqfcr[rqfar] = rqfcr;
1037 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1040 rqfcr = RQFCR_CMP_NOMATCH;
1041 priv->ftp_rqfpr[rqfar] = rqfpr;
1042 priv->ftp_rqfcr[rqfar] = rqfcr;
1043 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1046 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1048 priv->ftp_rqfcr[rqfar] = rqfcr;
1049 priv->ftp_rqfpr[rqfar] = rqfpr;
1050 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1053 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1055 priv->ftp_rqfcr[rqfar] = rqfcr;
1056 priv->ftp_rqfpr[rqfar] = rqfpr;
1057 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1062 static void gfar_init_filer_table(struct gfar_private *priv)
1065 u32 rqfar = MAX_FILER_IDX;
1067 u32 rqfpr = FPR_FILER_MASK;
1070 rqfcr = RQFCR_CMP_MATCH;
1071 priv->ftp_rqfcr[rqfar] = rqfcr;
1072 priv->ftp_rqfpr[rqfar] = rqfpr;
1073 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1075 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1076 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1077 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1078 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1079 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1080 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1082 /* cur_filer_idx indicated the first non-masked rule */
1083 priv->cur_filer_idx = rqfar;
1085 /* Rest are masked rules */
1086 rqfcr = RQFCR_CMP_NOMATCH;
1087 for (i = 0; i < rqfar; i++) {
1088 priv->ftp_rqfcr[i] = rqfcr;
1089 priv->ftp_rqfpr[i] = rqfpr;
1090 gfar_write_filer(priv, i, rqfcr, rqfpr);
1095 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1097 unsigned int pvr = mfspr(SPRN_PVR);
1098 unsigned int svr = mfspr(SPRN_SVR);
1099 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1100 unsigned int rev = svr & 0xffff;
1102 /* MPC8313 Rev 2.0 and higher; All MPC837x */
1103 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1104 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1105 priv->errata |= GFAR_ERRATA_74;
1107 /* MPC8313 and MPC837x all rev */
1108 if ((pvr == 0x80850010 && mod == 0x80b0) ||
1109 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1110 priv->errata |= GFAR_ERRATA_76;
1112 /* MPC8313 Rev < 2.0 */
1113 if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1114 priv->errata |= GFAR_ERRATA_12;
1117 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1119 unsigned int svr = mfspr(SPRN_SVR);
1121 if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1122 priv->errata |= GFAR_ERRATA_12;
1123 if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1124 ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
1125 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1129 static void gfar_detect_errata(struct gfar_private *priv)
1131 struct device *dev = &priv->ofdev->dev;
1133 /* no plans to fix */
1134 priv->errata |= GFAR_ERRATA_A002;
1137 if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1138 __gfar_detect_errata_85xx(priv);
1139 else /* non-mpc85xx parts, i.e. e300 core based */
1140 __gfar_detect_errata_83xx(priv);
1144 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1148 void gfar_mac_reset(struct gfar_private *priv)
1150 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1153 /* Reset MAC layer */
1154 gfar_write(®s->maccfg1, MACCFG1_SOFT_RESET);
1156 /* We need to delay at least 3 TX clocks */
1159 /* the soft reset bit is not self-resetting, so we need to
1160 * clear it before resuming normal operation
1162 gfar_write(®s->maccfg1, 0);
1166 gfar_rx_offload_en(priv);
1168 /* Initialize the max receive frame/buffer lengths */
1169 gfar_write(®s->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1170 gfar_write(®s->mrblr, GFAR_RXB_SIZE);
1172 /* Initialize the Minimum Frame Length Register */
1173 gfar_write(®s->minflr, MINFLR_INIT_SETTINGS);
1175 /* Initialize MACCFG2. */
1176 tempval = MACCFG2_INIT_SETTINGS;
1178 /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1179 * are marked as truncated. Avoid this by MACCFG2[Huge Frame]=1,
1180 * and by checking RxBD[LG] and discarding larger than MAXFRM.
1182 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1183 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1185 gfar_write(®s->maccfg2, tempval);
1187 /* Clear mac addr hash registers */
1188 gfar_write(®s->igaddr0, 0);
1189 gfar_write(®s->igaddr1, 0);
1190 gfar_write(®s->igaddr2, 0);
1191 gfar_write(®s->igaddr3, 0);
1192 gfar_write(®s->igaddr4, 0);
1193 gfar_write(®s->igaddr5, 0);
1194 gfar_write(®s->igaddr6, 0);
1195 gfar_write(®s->igaddr7, 0);
1197 gfar_write(®s->gaddr0, 0);
1198 gfar_write(®s->gaddr1, 0);
1199 gfar_write(®s->gaddr2, 0);
1200 gfar_write(®s->gaddr3, 0);
1201 gfar_write(®s->gaddr4, 0);
1202 gfar_write(®s->gaddr5, 0);
1203 gfar_write(®s->gaddr6, 0);
1204 gfar_write(®s->gaddr7, 0);
1206 if (priv->extended_hash)
1207 gfar_clear_exact_match(priv->ndev);
1209 gfar_mac_rx_config(priv);
1211 gfar_mac_tx_config(priv);
1213 gfar_set_mac_address(priv->ndev);
1215 gfar_set_multi(priv->ndev);
1217 /* clear ievent and imask before configuring coalescing */
1218 gfar_ints_disable(priv);
1220 /* Configure the coalescing support */
1221 gfar_configure_coalescing_all(priv);
1224 static void gfar_hw_init(struct gfar_private *priv)
1226 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1229 /* Stop the DMA engine now, in case it was running before
1230 * (The firmware could have used it, and left it running).
1234 gfar_mac_reset(priv);
1236 /* Zero out the rmon mib registers if it has them */
1237 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1238 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1240 /* Mask off the CAM interrupts */
1241 gfar_write(®s->rmon.cam1, 0xffffffff);
1242 gfar_write(®s->rmon.cam2, 0xffffffff);
1245 /* Initialize ECNTRL */
1246 gfar_write(®s->ecntrl, ECNTRL_INIT_SETTINGS);
1248 /* Set the extraction length and index */
1249 attrs = ATTRELI_EL(priv->rx_stash_size) |
1250 ATTRELI_EI(priv->rx_stash_index);
1252 gfar_write(®s->attreli, attrs);
1254 /* Start with defaults, and add stashing
1255 * depending on driver parameters
1257 attrs = ATTR_INIT_SETTINGS;
1259 if (priv->bd_stash_en)
1260 attrs |= ATTR_BDSTASH;
1262 if (priv->rx_stash_size != 0)
1263 attrs |= ATTR_BUFSTASH;
1265 gfar_write(®s->attr, attrs);
1268 gfar_write(®s->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1269 gfar_write(®s->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1270 gfar_write(®s->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1272 /* Program the interrupt steering regs, only for MG devices */
1273 if (priv->num_grps > 1)
1274 gfar_write_isrg(priv);
1277 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1279 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1281 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1282 priv->extended_hash = 1;
1283 priv->hash_width = 9;
1285 priv->hash_regs[0] = ®s->igaddr0;
1286 priv->hash_regs[1] = ®s->igaddr1;
1287 priv->hash_regs[2] = ®s->igaddr2;
1288 priv->hash_regs[3] = ®s->igaddr3;
1289 priv->hash_regs[4] = ®s->igaddr4;
1290 priv->hash_regs[5] = ®s->igaddr5;
1291 priv->hash_regs[6] = ®s->igaddr6;
1292 priv->hash_regs[7] = ®s->igaddr7;
1293 priv->hash_regs[8] = ®s->gaddr0;
1294 priv->hash_regs[9] = ®s->gaddr1;
1295 priv->hash_regs[10] = ®s->gaddr2;
1296 priv->hash_regs[11] = ®s->gaddr3;
1297 priv->hash_regs[12] = ®s->gaddr4;
1298 priv->hash_regs[13] = ®s->gaddr5;
1299 priv->hash_regs[14] = ®s->gaddr6;
1300 priv->hash_regs[15] = ®s->gaddr7;
1303 priv->extended_hash = 0;
1304 priv->hash_width = 8;
1306 priv->hash_regs[0] = ®s->gaddr0;
1307 priv->hash_regs[1] = ®s->gaddr1;
1308 priv->hash_regs[2] = ®s->gaddr2;
1309 priv->hash_regs[3] = ®s->gaddr3;
1310 priv->hash_regs[4] = ®s->gaddr4;
1311 priv->hash_regs[5] = ®s->gaddr5;
1312 priv->hash_regs[6] = ®s->gaddr6;
1313 priv->hash_regs[7] = ®s->gaddr7;
1317 /* Set up the ethernet device structure, private data,
1318 * and anything else we need before we start
1320 static int gfar_probe(struct platform_device *ofdev)
1322 struct net_device *dev = NULL;
1323 struct gfar_private *priv = NULL;
1326 err = gfar_of_init(ofdev, &dev);
1331 priv = netdev_priv(dev);
1333 priv->ofdev = ofdev;
1334 priv->dev = &ofdev->dev;
1335 SET_NETDEV_DEV(dev, &ofdev->dev);
1337 INIT_WORK(&priv->reset_task, gfar_reset_task);
1339 platform_set_drvdata(ofdev, priv);
1341 gfar_detect_errata(priv);
1343 /* Set the dev->base_addr to the gfar reg region */
1344 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1346 /* Fill in the dev structure */
1347 dev->watchdog_timeo = TX_TIMEOUT;
1349 dev->netdev_ops = &gfar_netdev_ops;
1350 dev->ethtool_ops = &gfar_ethtool_ops;
1352 /* Register for napi ...We are registering NAPI for each grp */
1353 for (i = 0; i < priv->num_grps; i++) {
1354 if (priv->poll_mode == GFAR_SQ_POLLING) {
1355 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1356 gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1357 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1358 gfar_poll_tx_sq, 2);
1360 netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1361 gfar_poll_rx, GFAR_DEV_WEIGHT);
1362 netif_napi_add(dev, &priv->gfargrp[i].napi_tx,
1367 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1368 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1370 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1371 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1374 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1375 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1376 NETIF_F_HW_VLAN_CTAG_RX;
1377 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1380 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1382 gfar_init_addr_hash_table(priv);
1384 /* Insert receive time stamps into padding alignment bytes, and
1385 * plus 2 bytes padding to ensure the cpu alignment.
1387 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1388 priv->padding = 8 + DEFAULT_PADDING;
1390 if (dev->features & NETIF_F_IP_CSUM ||
1391 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1392 dev->needed_headroom = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
1394 /* Initializing some of the rx/tx queue level parameters */
1395 for (i = 0; i < priv->num_tx_queues; i++) {
1396 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1397 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1398 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1399 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1402 for (i = 0; i < priv->num_rx_queues; i++) {
1403 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1404 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1405 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1408 /* Always enable rx filer if available */
1409 priv->rx_filer_enable =
1410 (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
1411 /* Enable most messages by default */
1412 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1413 /* use pritority h/w tx queue scheduling for single queue devices */
1414 if (priv->num_tx_queues == 1)
1415 priv->prio_sched_en = 1;
1417 set_bit(GFAR_DOWN, &priv->state);
1421 /* Carrier starts down, phylib will bring it up */
1422 netif_carrier_off(dev);
1424 err = register_netdev(dev);
1427 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1431 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
1432 priv->wol_supported |= GFAR_WOL_MAGIC;
1434 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
1435 priv->rx_filer_enable)
1436 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
1438 device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
1440 /* fill out IRQ number and name fields */
1441 for (i = 0; i < priv->num_grps; i++) {
1442 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1443 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1444 sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1445 dev->name, "_g", '0' + i, "_tx");
1446 sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1447 dev->name, "_g", '0' + i, "_rx");
1448 sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1449 dev->name, "_g", '0' + i, "_er");
1451 strcpy(gfar_irq(grp, TX)->name, dev->name);
1454 /* Initialize the filer table */
1455 gfar_init_filer_table(priv);
1457 /* Print out the device info */
1458 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1460 /* Even more device info helps when determining which kernel
1461 * provided which set of benchmarks.
1463 netdev_info(dev, "Running with NAPI enabled\n");
1464 for (i = 0; i < priv->num_rx_queues; i++)
1465 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1466 i, priv->rx_queue[i]->rx_ring_size);
1467 for (i = 0; i < priv->num_tx_queues; i++)
1468 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1469 i, priv->tx_queue[i]->tx_ring_size);
1474 unmap_group_regs(priv);
1475 gfar_free_rx_queues(priv);
1476 gfar_free_tx_queues(priv);
1477 of_node_put(priv->phy_node);
1478 of_node_put(priv->tbi_node);
1479 free_gfar_dev(priv);
1483 static int gfar_remove(struct platform_device *ofdev)
1485 struct gfar_private *priv = platform_get_drvdata(ofdev);
1487 of_node_put(priv->phy_node);
1488 of_node_put(priv->tbi_node);
1490 unregister_netdev(priv->ndev);
1491 unmap_group_regs(priv);
1492 gfar_free_rx_queues(priv);
1493 gfar_free_tx_queues(priv);
1494 free_gfar_dev(priv);
1501 static void __gfar_filer_disable(struct gfar_private *priv)
1503 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1506 temp = gfar_read(®s->rctrl);
1507 temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
1508 gfar_write(®s->rctrl, temp);
1511 static void __gfar_filer_enable(struct gfar_private *priv)
1513 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1516 temp = gfar_read(®s->rctrl);
1517 temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1518 gfar_write(®s->rctrl, temp);
1521 /* Filer rules implementing wol capabilities */
1522 static void gfar_filer_config_wol(struct gfar_private *priv)
1527 __gfar_filer_disable(priv);
1529 /* clear the filer table, reject any packet by default */
1530 rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
1531 for (i = 0; i <= MAX_FILER_IDX; i++)
1532 gfar_write_filer(priv, i, rqfcr, 0);
1535 if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
1536 /* unicast packet, accept it */
1537 struct net_device *ndev = priv->ndev;
1538 /* get the default rx queue index */
1539 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
1540 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
1541 (ndev->dev_addr[1] << 8) |
1544 rqfcr = (qindex << 10) | RQFCR_AND |
1545 RQFCR_CMP_EXACT | RQFCR_PID_DAH;
1547 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1549 dest_mac_addr = (ndev->dev_addr[3] << 16) |
1550 (ndev->dev_addr[4] << 8) |
1552 rqfcr = (qindex << 10) | RQFCR_GPI |
1553 RQFCR_CMP_EXACT | RQFCR_PID_DAL;
1554 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1557 __gfar_filer_enable(priv);
1560 static void gfar_filer_restore_table(struct gfar_private *priv)
1565 __gfar_filer_disable(priv);
1567 for (i = 0; i <= MAX_FILER_IDX; i++) {
1568 rqfcr = priv->ftp_rqfcr[i];
1569 rqfpr = priv->ftp_rqfpr[i];
1570 gfar_write_filer(priv, i, rqfcr, rqfpr);
1573 __gfar_filer_enable(priv);
1576 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
1577 static void gfar_start_wol_filer(struct gfar_private *priv)
1579 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1583 /* Enable Rx hw queues */
1584 gfar_write(®s->rqueue, priv->rqueue);
1586 /* Initialize DMACTRL to have WWR and WOP */
1587 tempval = gfar_read(®s->dmactrl);
1588 tempval |= DMACTRL_INIT_SETTINGS;
1589 gfar_write(®s->dmactrl, tempval);
1591 /* Make sure we aren't stopped */
1592 tempval = gfar_read(®s->dmactrl);
1593 tempval &= ~DMACTRL_GRS;
1594 gfar_write(®s->dmactrl, tempval);
1596 for (i = 0; i < priv->num_grps; i++) {
1597 regs = priv->gfargrp[i].regs;
1598 /* Clear RHLT, so that the DMA starts polling now */
1599 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
1600 /* enable the Filer General Purpose Interrupt */
1601 gfar_write(®s->imask, IMASK_FGPI);
1605 tempval = gfar_read(®s->maccfg1);
1606 tempval |= MACCFG1_RX_EN;
1607 gfar_write(®s->maccfg1, tempval);
1610 static int gfar_suspend(struct device *dev)
1612 struct gfar_private *priv = dev_get_drvdata(dev);
1613 struct net_device *ndev = priv->ndev;
1614 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1616 u16 wol = priv->wol_opts;
1618 if (!netif_running(ndev))
1622 netif_tx_lock(ndev);
1623 netif_device_detach(ndev);
1624 netif_tx_unlock(ndev);
1628 if (wol & GFAR_WOL_MAGIC) {
1629 /* Enable interrupt on Magic Packet */
1630 gfar_write(®s->imask, IMASK_MAG);
1632 /* Enable Magic Packet mode */
1633 tempval = gfar_read(®s->maccfg2);
1634 tempval |= MACCFG2_MPEN;
1635 gfar_write(®s->maccfg2, tempval);
1637 /* re-enable the Rx block */
1638 tempval = gfar_read(®s->maccfg1);
1639 tempval |= MACCFG1_RX_EN;
1640 gfar_write(®s->maccfg1, tempval);
1642 } else if (wol & GFAR_WOL_FILER_UCAST) {
1643 gfar_filer_config_wol(priv);
1644 gfar_start_wol_filer(priv);
1647 phy_stop(priv->phydev);
1653 static int gfar_resume(struct device *dev)
1655 struct gfar_private *priv = dev_get_drvdata(dev);
1656 struct net_device *ndev = priv->ndev;
1657 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1659 u16 wol = priv->wol_opts;
1661 if (!netif_running(ndev))
1664 if (wol & GFAR_WOL_MAGIC) {
1665 /* Disable Magic Packet mode */
1666 tempval = gfar_read(®s->maccfg2);
1667 tempval &= ~MACCFG2_MPEN;
1668 gfar_write(®s->maccfg2, tempval);
1670 } else if (wol & GFAR_WOL_FILER_UCAST) {
1671 /* need to stop rx only, tx is already down */
1673 gfar_filer_restore_table(priv);
1676 phy_start(priv->phydev);
1681 netif_device_attach(ndev);
1687 static int gfar_restore(struct device *dev)
1689 struct gfar_private *priv = dev_get_drvdata(dev);
1690 struct net_device *ndev = priv->ndev;
1692 if (!netif_running(ndev)) {
1693 netif_device_attach(ndev);
1698 gfar_init_bds(ndev);
1700 gfar_mac_reset(priv);
1702 gfar_init_tx_rx_base(priv);
1708 priv->oldduplex = -1;
1711 phy_start(priv->phydev);
1713 netif_device_attach(ndev);
1719 static struct dev_pm_ops gfar_pm_ops = {
1720 .suspend = gfar_suspend,
1721 .resume = gfar_resume,
1722 .freeze = gfar_suspend,
1723 .thaw = gfar_resume,
1724 .restore = gfar_restore,
1727 #define GFAR_PM_OPS (&gfar_pm_ops)
1731 #define GFAR_PM_OPS NULL
1735 /* Reads the controller's registers to determine what interface
1736 * connects it to the PHY.
1738 static phy_interface_t gfar_get_interface(struct net_device *dev)
1740 struct gfar_private *priv = netdev_priv(dev);
1741 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1744 ecntrl = gfar_read(®s->ecntrl);
1746 if (ecntrl & ECNTRL_SGMII_MODE)
1747 return PHY_INTERFACE_MODE_SGMII;
1749 if (ecntrl & ECNTRL_TBI_MODE) {
1750 if (ecntrl & ECNTRL_REDUCED_MODE)
1751 return PHY_INTERFACE_MODE_RTBI;
1753 return PHY_INTERFACE_MODE_TBI;
1756 if (ecntrl & ECNTRL_REDUCED_MODE) {
1757 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1758 return PHY_INTERFACE_MODE_RMII;
1761 phy_interface_t interface = priv->interface;
1763 /* This isn't autodetected right now, so it must
1764 * be set by the device tree or platform code.
1766 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1767 return PHY_INTERFACE_MODE_RGMII_ID;
1769 return PHY_INTERFACE_MODE_RGMII;
1773 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1774 return PHY_INTERFACE_MODE_GMII;
1776 return PHY_INTERFACE_MODE_MII;
1780 /* Initializes driver's PHY state, and attaches to the PHY.
1781 * Returns 0 on success.
1783 static int init_phy(struct net_device *dev)
1785 struct gfar_private *priv = netdev_priv(dev);
1786 uint gigabit_support =
1787 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1788 GFAR_SUPPORTED_GBIT : 0;
1789 phy_interface_t interface;
1793 priv->oldduplex = -1;
1795 interface = gfar_get_interface(dev);
1797 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1799 if (!priv->phydev) {
1800 dev_err(&dev->dev, "could not attach to PHY\n");
1804 if (interface == PHY_INTERFACE_MODE_SGMII)
1805 gfar_configure_serdes(dev);
1807 /* Remove any features not supported by the controller */
1808 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1809 priv->phydev->advertising = priv->phydev->supported;
1811 /* Add support for flow control, but don't advertise it by default */
1812 priv->phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1817 /* Initialize TBI PHY interface for communicating with the
1818 * SERDES lynx PHY on the chip. We communicate with this PHY
1819 * through the MDIO bus on each controller, treating it as a
1820 * "normal" PHY at the address found in the TBIPA register. We assume
1821 * that the TBIPA register is valid. Either the MDIO bus code will set
1822 * it to a value that doesn't conflict with other PHYs on the bus, or the
1823 * value doesn't matter, as there are no other PHYs on the bus.
1825 static void gfar_configure_serdes(struct net_device *dev)
1827 struct gfar_private *priv = netdev_priv(dev);
1828 struct phy_device *tbiphy;
1830 if (!priv->tbi_node) {
1831 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1832 "device tree specify a tbi-handle\n");
1836 tbiphy = of_phy_find_device(priv->tbi_node);
1838 dev_err(&dev->dev, "error: Could not get TBI device\n");
1842 /* If the link is already up, we must already be ok, and don't need to
1843 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1844 * everything for us? Resetting it takes the link down and requires
1845 * several seconds for it to come back.
1847 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1848 put_device(&tbiphy->dev);
1852 /* Single clk mode, mii mode off(for serdes communication) */
1853 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1855 phy_write(tbiphy, MII_ADVERTISE,
1856 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1857 ADVERTISE_1000XPSE_ASYM);
1859 phy_write(tbiphy, MII_BMCR,
1860 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1863 put_device(&tbiphy->dev);
1866 static int __gfar_is_rx_idle(struct gfar_private *priv)
1870 /* Normaly TSEC should not hang on GRS commands, so we should
1871 * actually wait for IEVENT_GRSC flag.
1873 if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1876 /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1877 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1878 * and the Rx can be safely reset.
1880 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1882 if ((res & 0xffff) == (res >> 16))
1888 /* Halt the receive and transmit queues */
1889 static void gfar_halt_nodisable(struct gfar_private *priv)
1891 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1893 unsigned int timeout;
1896 gfar_ints_disable(priv);
1898 if (gfar_is_dma_stopped(priv))
1901 /* Stop the DMA, and wait for it to stop */
1902 tempval = gfar_read(®s->dmactrl);
1903 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1904 gfar_write(®s->dmactrl, tempval);
1908 while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1914 stopped = gfar_is_dma_stopped(priv);
1916 if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1917 !__gfar_is_rx_idle(priv))
1921 /* Halt the receive and transmit queues */
1922 void gfar_halt(struct gfar_private *priv)
1924 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1927 /* Dissable the Rx/Tx hw queues */
1928 gfar_write(®s->rqueue, 0);
1929 gfar_write(®s->tqueue, 0);
1933 gfar_halt_nodisable(priv);
1935 /* Disable Rx/Tx DMA */
1936 tempval = gfar_read(®s->maccfg1);
1937 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1938 gfar_write(®s->maccfg1, tempval);
1941 void stop_gfar(struct net_device *dev)
1943 struct gfar_private *priv = netdev_priv(dev);
1945 netif_tx_stop_all_queues(dev);
1947 smp_mb__before_atomic();
1948 set_bit(GFAR_DOWN, &priv->state);
1949 smp_mb__after_atomic();
1953 /* disable ints and gracefully shut down Rx/Tx DMA */
1956 phy_stop(priv->phydev);
1958 free_skb_resources(priv);
1961 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1963 struct txbd8 *txbdp;
1964 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1967 txbdp = tx_queue->tx_bd_base;
1969 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1970 if (!tx_queue->tx_skbuff[i])
1973 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1974 be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1976 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1979 dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1980 be16_to_cpu(txbdp->length),
1984 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1985 tx_queue->tx_skbuff[i] = NULL;
1987 kfree(tx_queue->tx_skbuff);
1988 tx_queue->tx_skbuff = NULL;
1991 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1995 struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1998 dev_kfree_skb(rx_queue->skb);
2000 for (i = 0; i < rx_queue->rx_ring_size; i++) {
2001 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
2010 dma_unmap_page(rx_queue->dev, rxb->dma,
2011 PAGE_SIZE, DMA_FROM_DEVICE);
2012 __free_page(rxb->page);
2017 kfree(rx_queue->rx_buff);
2018 rx_queue->rx_buff = NULL;
2021 /* If there are any tx skbs or rx skbs still around, free them.
2022 * Then free tx_skbuff and rx_skbuff
2024 static void free_skb_resources(struct gfar_private *priv)
2026 struct gfar_priv_tx_q *tx_queue = NULL;
2027 struct gfar_priv_rx_q *rx_queue = NULL;
2030 /* Go through all the buffer descriptors and free their data buffers */
2031 for (i = 0; i < priv->num_tx_queues; i++) {
2032 struct netdev_queue *txq;
2034 tx_queue = priv->tx_queue[i];
2035 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
2036 if (tx_queue->tx_skbuff)
2037 free_skb_tx_queue(tx_queue);
2038 netdev_tx_reset_queue(txq);
2041 for (i = 0; i < priv->num_rx_queues; i++) {
2042 rx_queue = priv->rx_queue[i];
2043 if (rx_queue->rx_buff)
2044 free_skb_rx_queue(rx_queue);
2047 dma_free_coherent(priv->dev,
2048 sizeof(struct txbd8) * priv->total_tx_ring_size +
2049 sizeof(struct rxbd8) * priv->total_rx_ring_size,
2050 priv->tx_queue[0]->tx_bd_base,
2051 priv->tx_queue[0]->tx_bd_dma_base);
2054 void gfar_start(struct gfar_private *priv)
2056 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2060 /* Enable Rx/Tx hw queues */
2061 gfar_write(®s->rqueue, priv->rqueue);
2062 gfar_write(®s->tqueue, priv->tqueue);
2064 /* Initialize DMACTRL to have WWR and WOP */
2065 tempval = gfar_read(®s->dmactrl);
2066 tempval |= DMACTRL_INIT_SETTINGS;
2067 gfar_write(®s->dmactrl, tempval);
2069 /* Make sure we aren't stopped */
2070 tempval = gfar_read(®s->dmactrl);
2071 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
2072 gfar_write(®s->dmactrl, tempval);
2074 for (i = 0; i < priv->num_grps; i++) {
2075 regs = priv->gfargrp[i].regs;
2076 /* Clear THLT/RHLT, so that the DMA starts polling now */
2077 gfar_write(®s->tstat, priv->gfargrp[i].tstat);
2078 gfar_write(®s->rstat, priv->gfargrp[i].rstat);
2081 /* Enable Rx/Tx DMA */
2082 tempval = gfar_read(®s->maccfg1);
2083 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2084 gfar_write(®s->maccfg1, tempval);
2086 gfar_ints_enable(priv);
2088 priv->ndev->trans_start = jiffies; /* prevent tx timeout */
2091 static void free_grp_irqs(struct gfar_priv_grp *grp)
2093 free_irq(gfar_irq(grp, TX)->irq, grp);
2094 free_irq(gfar_irq(grp, RX)->irq, grp);
2095 free_irq(gfar_irq(grp, ER)->irq, grp);
2098 static int register_grp_irqs(struct gfar_priv_grp *grp)
2100 struct gfar_private *priv = grp->priv;
2101 struct net_device *dev = priv->ndev;
2104 /* If the device has multiple interrupts, register for
2105 * them. Otherwise, only register for the one
2107 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2108 /* Install our interrupt handlers for Error,
2109 * Transmit, and Receive
2111 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2112 gfar_irq(grp, ER)->name, grp);
2114 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2115 gfar_irq(grp, ER)->irq);
2119 enable_irq_wake(gfar_irq(grp, ER)->irq);
2121 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2122 gfar_irq(grp, TX)->name, grp);
2124 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2125 gfar_irq(grp, TX)->irq);
2128 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2129 gfar_irq(grp, RX)->name, grp);
2131 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2132 gfar_irq(grp, RX)->irq);
2135 enable_irq_wake(gfar_irq(grp, RX)->irq);
2138 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2139 gfar_irq(grp, TX)->name, grp);
2141 netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2142 gfar_irq(grp, TX)->irq);
2145 enable_irq_wake(gfar_irq(grp, TX)->irq);
2151 free_irq(gfar_irq(grp, TX)->irq, grp);
2153 free_irq(gfar_irq(grp, ER)->irq, grp);
2159 static void gfar_free_irq(struct gfar_private *priv)
2164 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2165 for (i = 0; i < priv->num_grps; i++)
2166 free_grp_irqs(&priv->gfargrp[i]);
2168 for (i = 0; i < priv->num_grps; i++)
2169 free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2174 static int gfar_request_irq(struct gfar_private *priv)
2178 for (i = 0; i < priv->num_grps; i++) {
2179 err = register_grp_irqs(&priv->gfargrp[i]);
2181 for (j = 0; j < i; j++)
2182 free_grp_irqs(&priv->gfargrp[j]);
2190 /* Bring the controller up and running */
2191 int startup_gfar(struct net_device *ndev)
2193 struct gfar_private *priv = netdev_priv(ndev);
2196 gfar_mac_reset(priv);
2198 err = gfar_alloc_skb_resources(ndev);
2202 gfar_init_tx_rx_base(priv);
2204 smp_mb__before_atomic();
2205 clear_bit(GFAR_DOWN, &priv->state);
2206 smp_mb__after_atomic();
2208 /* Start Rx/Tx DMA and enable the interrupts */
2211 /* force link state update after mac reset */
2214 priv->oldduplex = -1;
2216 phy_start(priv->phydev);
2220 netif_tx_wake_all_queues(ndev);
2225 /* Called when something needs to use the ethernet device
2226 * Returns 0 for success.
2228 static int gfar_enet_open(struct net_device *dev)
2230 struct gfar_private *priv = netdev_priv(dev);
2233 err = init_phy(dev);
2237 err = gfar_request_irq(priv);
2241 err = startup_gfar(dev);
2248 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2250 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2252 memset(fcb, 0, GMAC_FCB_LEN);
2257 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2260 /* If we're here, it's a IP packet with a TCP or UDP
2261 * payload. We set it to checksum, using a pseudo-header
2264 u8 flags = TXFCB_DEFAULT;
2266 /* Tell the controller what the protocol is
2267 * And provide the already calculated phcs
2269 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2271 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2273 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2275 /* l3os is the distance between the start of the
2276 * frame (skb->data) and the start of the IP hdr.
2277 * l4os is the distance between the start of the
2278 * l3 hdr and the l4 hdr
2280 fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2281 fcb->l4os = skb_network_header_len(skb);
2286 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2288 fcb->flags |= TXFCB_VLN;
2289 fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2292 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2293 struct txbd8 *base, int ring_size)
2295 struct txbd8 *new_bd = bdp + stride;
2297 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2300 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2303 return skip_txbd(bdp, 1, base, ring_size);
2306 /* eTSEC12: csum generation not supported for some fcb offsets */
2307 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2308 unsigned long fcb_addr)
2310 return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2311 (fcb_addr % 0x20) > 0x18);
2314 /* eTSEC76: csum generation for frames larger than 2500 may
2315 * cause excess delays before start of transmission
2317 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2320 return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2324 /* This is called by the kernel when a frame is ready for transmission.
2325 * It is pointed to by the dev->hard_start_xmit function pointer
2327 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2329 struct gfar_private *priv = netdev_priv(dev);
2330 struct gfar_priv_tx_q *tx_queue = NULL;
2331 struct netdev_queue *txq;
2332 struct gfar __iomem *regs = NULL;
2333 struct txfcb *fcb = NULL;
2334 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2337 int do_tstamp, do_csum, do_vlan;
2339 unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2341 rq = skb->queue_mapping;
2342 tx_queue = priv->tx_queue[rq];
2343 txq = netdev_get_tx_queue(dev, rq);
2344 base = tx_queue->tx_bd_base;
2345 regs = tx_queue->grp->regs;
2347 do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2348 do_vlan = skb_vlan_tag_present(skb);
2349 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2352 if (do_csum || do_vlan)
2353 fcb_len = GMAC_FCB_LEN;
2355 /* check if time stamp should be generated */
2356 if (unlikely(do_tstamp))
2357 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2359 /* make space for additional header when fcb is needed */
2361 if (unlikely(skb_cow_head(skb, fcb_len))) {
2362 dev->stats.tx_errors++;
2363 dev_kfree_skb_any(skb);
2364 return NETDEV_TX_OK;
2368 /* total number of fragments in the SKB */
2369 nr_frags = skb_shinfo(skb)->nr_frags;
2371 /* calculate the required number of TxBDs for this skb */
2372 if (unlikely(do_tstamp))
2373 nr_txbds = nr_frags + 2;
2375 nr_txbds = nr_frags + 1;
2377 /* check if there is space to queue this packet */
2378 if (nr_txbds > tx_queue->num_txbdfree) {
2379 /* no space, stop the queue */
2380 netif_tx_stop_queue(txq);
2381 dev->stats.tx_fifo_errors++;
2382 return NETDEV_TX_BUSY;
2385 /* Update transmit stats */
2386 bytes_sent = skb->len;
2387 tx_queue->stats.tx_bytes += bytes_sent;
2388 /* keep Tx bytes on wire for BQL accounting */
2389 GFAR_CB(skb)->bytes_sent = bytes_sent;
2390 tx_queue->stats.tx_packets++;
2392 txbdp = txbdp_start = tx_queue->cur_tx;
2393 lstatus = be32_to_cpu(txbdp->lstatus);
2395 /* Time stamp insertion requires one additional TxBD */
2396 if (unlikely(do_tstamp))
2397 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2398 tx_queue->tx_ring_size);
2400 if (nr_frags == 0) {
2401 if (unlikely(do_tstamp)) {
2402 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2404 lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2405 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2407 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2410 /* Place the fragment addresses and lengths into the TxBDs */
2411 for (i = 0; i < nr_frags; i++) {
2412 unsigned int frag_len;
2413 /* Point at the next BD, wrapping as needed */
2414 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2416 frag_len = skb_shinfo(skb)->frags[i].size;
2418 lstatus = be32_to_cpu(txbdp->lstatus) | frag_len |
2419 BD_LFLAG(TXBD_READY);
2421 /* Handle the last BD specially */
2422 if (i == nr_frags - 1)
2423 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2425 bufaddr = skb_frag_dma_map(priv->dev,
2426 &skb_shinfo(skb)->frags[i],
2430 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2433 /* set the TxBD length and buffer pointer */
2434 txbdp->bufPtr = cpu_to_be32(bufaddr);
2435 txbdp->lstatus = cpu_to_be32(lstatus);
2438 lstatus = be32_to_cpu(txbdp_start->lstatus);
2441 /* Add TxPAL between FCB and frame if required */
2442 if (unlikely(do_tstamp)) {
2443 skb_push(skb, GMAC_TXPAL_LEN);
2444 memset(skb->data, 0, GMAC_TXPAL_LEN);
2447 /* Add TxFCB if required */
2449 fcb = gfar_add_fcb(skb);
2450 lstatus |= BD_LFLAG(TXBD_TOE);
2453 /* Set up checksumming */
2455 gfar_tx_checksum(skb, fcb, fcb_len);
2457 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2458 unlikely(gfar_csum_errata_76(priv, skb->len))) {
2459 __skb_pull(skb, GMAC_FCB_LEN);
2460 skb_checksum_help(skb);
2461 if (do_vlan || do_tstamp) {
2462 /* put back a new fcb for vlan/tstamp TOE */
2463 fcb = gfar_add_fcb(skb);
2465 /* Tx TOE not used */
2466 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2473 gfar_tx_vlan(skb, fcb);
2475 /* Setup tx hardware time stamping if requested */
2476 if (unlikely(do_tstamp)) {
2477 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2481 bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2483 if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2486 txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2488 /* If time stamping is requested one additional TxBD must be set up. The
2489 * first TxBD points to the FCB and must have a data length of
2490 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2491 * the full frame length.
2493 if (unlikely(do_tstamp)) {
2494 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2496 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2498 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2499 (skb_headlen(skb) - fcb_len);
2501 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2502 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2503 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2505 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2508 netdev_tx_sent_queue(txq, bytes_sent);
2512 txbdp_start->lstatus = cpu_to_be32(lstatus);
2514 gfar_wmb(); /* force lstatus write before tx_skbuff */
2516 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2518 /* Update the current skb pointer to the next entry we will use
2519 * (wrapping if necessary)
2521 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2522 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2524 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2526 /* We can work in parallel with gfar_clean_tx_ring(), except
2527 * when modifying num_txbdfree. Note that we didn't grab the lock
2528 * when we were reading the num_txbdfree and checking for available
2529 * space, that's because outside of this function it can only grow.
2531 spin_lock_bh(&tx_queue->txlock);
2532 /* reduce TxBD free count */
2533 tx_queue->num_txbdfree -= (nr_txbds);
2534 spin_unlock_bh(&tx_queue->txlock);
2536 /* If the next BD still needs to be cleaned up, then the bds
2537 * are full. We need to tell the kernel to stop sending us stuff.
2539 if (!tx_queue->num_txbdfree) {
2540 netif_tx_stop_queue(txq);
2542 dev->stats.tx_fifo_errors++;
2545 /* Tell the DMA to go go go */
2546 gfar_write(®s->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2548 return NETDEV_TX_OK;
2551 txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2553 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2554 for (i = 0; i < nr_frags; i++) {
2555 lstatus = be32_to_cpu(txbdp->lstatus);
2556 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2559 lstatus &= ~BD_LFLAG(TXBD_READY);
2560 txbdp->lstatus = cpu_to_be32(lstatus);
2561 bufaddr = be32_to_cpu(txbdp->bufPtr);
2562 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2564 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2567 dev_kfree_skb_any(skb);
2568 return NETDEV_TX_OK;
2571 /* Stops the kernel queue, and halts the controller */
2572 static int gfar_close(struct net_device *dev)
2574 struct gfar_private *priv = netdev_priv(dev);
2576 cancel_work_sync(&priv->reset_task);
2579 /* Disconnect from the PHY */
2580 phy_disconnect(priv->phydev);
2581 priv->phydev = NULL;
2583 gfar_free_irq(priv);
2588 /* Changes the mac address if the controller is not running. */
2589 static int gfar_set_mac_address(struct net_device *dev)
2591 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2596 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2598 struct gfar_private *priv = netdev_priv(dev);
2599 int frame_size = new_mtu + ETH_HLEN;
2601 if ((frame_size < 64) || (frame_size > GFAR_JUMBO_FRAME_SIZE)) {
2602 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2606 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2609 if (dev->flags & IFF_UP)
2614 if (dev->flags & IFF_UP)
2617 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2622 void reset_gfar(struct net_device *ndev)
2624 struct gfar_private *priv = netdev_priv(ndev);
2626 while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2632 clear_bit_unlock(GFAR_RESETTING, &priv->state);
2635 /* gfar_reset_task gets scheduled when a packet has not been
2636 * transmitted after a set amount of time.
2637 * For now, assume that clearing out all the structures, and
2638 * starting over will fix the problem.
2640 static void gfar_reset_task(struct work_struct *work)
2642 struct gfar_private *priv = container_of(work, struct gfar_private,
2644 reset_gfar(priv->ndev);
2647 static void gfar_timeout(struct net_device *dev)
2649 struct gfar_private *priv = netdev_priv(dev);
2651 dev->stats.tx_errors++;
2652 schedule_work(&priv->reset_task);
2655 /* Interrupt Handler for Transmit complete */
2656 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2658 struct net_device *dev = tx_queue->dev;
2659 struct netdev_queue *txq;
2660 struct gfar_private *priv = netdev_priv(dev);
2661 struct txbd8 *bdp, *next = NULL;
2662 struct txbd8 *lbdp = NULL;
2663 struct txbd8 *base = tx_queue->tx_bd_base;
2664 struct sk_buff *skb;
2666 int tx_ring_size = tx_queue->tx_ring_size;
2667 int frags = 0, nr_txbds = 0;
2670 int tqi = tx_queue->qindex;
2671 unsigned int bytes_sent = 0;
2675 txq = netdev_get_tx_queue(dev, tqi);
2676 bdp = tx_queue->dirty_tx;
2677 skb_dirtytx = tx_queue->skb_dirtytx;
2679 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2682 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2685 frags = skb_shinfo(skb)->nr_frags;
2687 /* When time stamping, one additional TxBD must be freed.
2688 * Also, we need to dma_unmap_single() the TxPAL.
2690 if (unlikely(do_tstamp))
2691 nr_txbds = frags + 2;
2693 nr_txbds = frags + 1;
2695 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2697 lstatus = be32_to_cpu(lbdp->lstatus);
2699 /* Only clean completed frames */
2700 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2701 (lstatus & BD_LENGTH_MASK))
2704 if (unlikely(do_tstamp)) {
2705 next = next_txbd(bdp, base, tx_ring_size);
2706 buflen = be16_to_cpu(next->length) +
2707 GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2709 buflen = be16_to_cpu(bdp->length);
2711 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2712 buflen, DMA_TO_DEVICE);
2714 if (unlikely(do_tstamp)) {
2715 struct skb_shared_hwtstamps shhwtstamps;
2716 u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2719 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2720 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2721 skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2722 skb_tstamp_tx(skb, &shhwtstamps);
2723 gfar_clear_txbd_status(bdp);
2727 gfar_clear_txbd_status(bdp);
2728 bdp = next_txbd(bdp, base, tx_ring_size);
2730 for (i = 0; i < frags; i++) {
2731 dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2732 be16_to_cpu(bdp->length),
2734 gfar_clear_txbd_status(bdp);
2735 bdp = next_txbd(bdp, base, tx_ring_size);
2738 bytes_sent += GFAR_CB(skb)->bytes_sent;
2740 dev_kfree_skb_any(skb);
2742 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2744 skb_dirtytx = (skb_dirtytx + 1) &
2745 TX_RING_MOD_MASK(tx_ring_size);
2748 spin_lock(&tx_queue->txlock);
2749 tx_queue->num_txbdfree += nr_txbds;
2750 spin_unlock(&tx_queue->txlock);
2753 /* If we freed a buffer, we can restart transmission, if necessary */
2754 if (tx_queue->num_txbdfree &&
2755 netif_tx_queue_stopped(txq) &&
2756 !(test_bit(GFAR_DOWN, &priv->state)))
2757 netif_wake_subqueue(priv->ndev, tqi);
2759 /* Update dirty indicators */
2760 tx_queue->skb_dirtytx = skb_dirtytx;
2761 tx_queue->dirty_tx = bdp;
2763 netdev_tx_completed_queue(txq, howmany, bytes_sent);
2766 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2771 page = dev_alloc_page();
2772 if (unlikely(!page))
2775 addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2776 if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2784 rxb->page_offset = 0;
2789 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2791 struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2792 struct gfar_extra_stats *estats = &priv->extra_stats;
2794 netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2795 atomic64_inc(&estats->rx_alloc_err);
2798 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2802 struct gfar_rx_buff *rxb;
2805 i = rx_queue->next_to_use;
2806 bdp = &rx_queue->rx_bd_base[i];
2807 rxb = &rx_queue->rx_buff[i];
2809 while (alloc_cnt--) {
2810 /* try reuse page */
2811 if (unlikely(!rxb->page)) {
2812 if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2813 gfar_rx_alloc_err(rx_queue);
2818 /* Setup the new RxBD */
2819 gfar_init_rxbdp(rx_queue, bdp,
2820 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2822 /* Update to the next pointer */
2826 if (unlikely(++i == rx_queue->rx_ring_size)) {
2828 bdp = rx_queue->rx_bd_base;
2829 rxb = rx_queue->rx_buff;
2833 rx_queue->next_to_use = i;
2834 rx_queue->next_to_alloc = i;
2837 static void count_errors(u32 lstatus, struct net_device *ndev)
2839 struct gfar_private *priv = netdev_priv(ndev);
2840 struct net_device_stats *stats = &ndev->stats;
2841 struct gfar_extra_stats *estats = &priv->extra_stats;
2843 /* If the packet was truncated, none of the other errors matter */
2844 if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2845 stats->rx_length_errors++;
2847 atomic64_inc(&estats->rx_trunc);
2851 /* Count the errors, if there were any */
2852 if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2853 stats->rx_length_errors++;
2855 if (lstatus & BD_LFLAG(RXBD_LARGE))
2856 atomic64_inc(&estats->rx_large);
2858 atomic64_inc(&estats->rx_short);
2860 if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2861 stats->rx_frame_errors++;
2862 atomic64_inc(&estats->rx_nonoctet);
2864 if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2865 atomic64_inc(&estats->rx_crcerr);
2866 stats->rx_crc_errors++;
2868 if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2869 atomic64_inc(&estats->rx_overrun);
2870 stats->rx_over_errors++;
2874 irqreturn_t gfar_receive(int irq, void *grp_id)
2876 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2877 unsigned long flags;
2880 ievent = gfar_read(&grp->regs->ievent);
2882 if (unlikely(ievent & IEVENT_FGPI)) {
2883 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2887 if (likely(napi_schedule_prep(&grp->napi_rx))) {
2888 spin_lock_irqsave(&grp->grplock, flags);
2889 imask = gfar_read(&grp->regs->imask);
2890 imask &= IMASK_RX_DISABLED;
2891 gfar_write(&grp->regs->imask, imask);
2892 spin_unlock_irqrestore(&grp->grplock, flags);
2893 __napi_schedule(&grp->napi_rx);
2895 /* Clear IEVENT, so interrupts aren't called again
2896 * because of the packets that have already arrived.
2898 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2904 /* Interrupt Handler for Transmit complete */
2905 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2907 struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2908 unsigned long flags;
2911 if (likely(napi_schedule_prep(&grp->napi_tx))) {
2912 spin_lock_irqsave(&grp->grplock, flags);
2913 imask = gfar_read(&grp->regs->imask);
2914 imask &= IMASK_TX_DISABLED;
2915 gfar_write(&grp->regs->imask, imask);
2916 spin_unlock_irqrestore(&grp->grplock, flags);
2917 __napi_schedule(&grp->napi_tx);
2919 /* Clear IEVENT, so interrupts aren't called again
2920 * because of the packets that have already arrived.
2922 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2928 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2929 struct sk_buff *skb, bool first)
2931 unsigned int size = lstatus & BD_LENGTH_MASK;
2932 struct page *page = rxb->page;
2934 /* Remove the FCS from the packet length */
2935 if (likely(lstatus & BD_LFLAG(RXBD_LAST)))
2936 size -= ETH_FCS_LEN;
2941 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2942 rxb->page_offset + RXBUF_ALIGNMENT,
2943 size, GFAR_RXB_TRUESIZE);
2945 /* try reuse page */
2946 if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page)))
2949 /* change offset to the other half */
2950 rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2952 atomic_inc(&page->_count);
2957 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2958 struct gfar_rx_buff *old_rxb)
2960 struct gfar_rx_buff *new_rxb;
2961 u16 nta = rxq->next_to_alloc;
2963 new_rxb = &rxq->rx_buff[nta];
2965 /* find next buf that can reuse a page */
2967 rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2969 /* copy page reference */
2970 *new_rxb = *old_rxb;
2972 /* sync for use by the device */
2973 dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2974 old_rxb->page_offset,
2975 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2978 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2979 u32 lstatus, struct sk_buff *skb)
2981 struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2982 struct page *page = rxb->page;
2986 void *buff_addr = page_address(page) + rxb->page_offset;
2988 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2989 if (unlikely(!skb)) {
2990 gfar_rx_alloc_err(rx_queue);
2993 skb_reserve(skb, RXBUF_ALIGNMENT);
2997 dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2998 GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
3000 if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
3001 /* reuse the free half of the page */
3002 gfar_reuse_rx_page(rx_queue, rxb);
3004 /* page cannot be reused, unmap it */
3005 dma_unmap_page(rx_queue->dev, rxb->dma,
3006 PAGE_SIZE, DMA_FROM_DEVICE);
3009 /* clear rxb content */
3015 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
3017 /* If valid headers were found, and valid sums
3018 * were verified, then we tell the kernel that no
3019 * checksumming is necessary. Otherwise, it is [FIXME]
3021 if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
3022 (RXFCB_CIP | RXFCB_CTU))
3023 skb->ip_summed = CHECKSUM_UNNECESSARY;
3025 skb_checksum_none_assert(skb);
3028 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
3029 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
3031 struct gfar_private *priv = netdev_priv(ndev);
3032 struct rxfcb *fcb = NULL;
3034 /* fcb is at the beginning if exists */
3035 fcb = (struct rxfcb *)skb->data;
3037 /* Remove the FCB from the skb
3038 * Remove the padded bytes, if there are any
3040 if (priv->uses_rxfcb)
3041 skb_pull(skb, GMAC_FCB_LEN);
3043 /* Get receive timestamp from the skb */
3044 if (priv->hwts_rx_en) {
3045 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
3046 u64 *ns = (u64 *) skb->data;
3048 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3049 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
3053 skb_pull(skb, priv->padding);
3055 if (ndev->features & NETIF_F_RXCSUM)
3056 gfar_rx_checksum(skb, fcb);
3058 /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
3059 * Even if vlan rx accel is disabled, on some chips
3060 * RXFCB_VLN is pseudo randomly set.
3062 if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3063 be16_to_cpu(fcb->flags) & RXFCB_VLN)
3064 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3065 be16_to_cpu(fcb->vlctl));
3068 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
3069 * until the budget/quota has been reached. Returns the number
3072 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
3074 struct net_device *ndev = rx_queue->ndev;
3075 struct gfar_private *priv = netdev_priv(ndev);
3078 struct sk_buff *skb = rx_queue->skb;
3079 int cleaned_cnt = gfar_rxbd_unused(rx_queue);
3080 unsigned int total_bytes = 0, total_pkts = 0;
3082 /* Get the first full descriptor */
3083 i = rx_queue->next_to_clean;
3085 while (rx_work_limit--) {
3088 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
3089 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3093 bdp = &rx_queue->rx_bd_base[i];
3094 lstatus = be32_to_cpu(bdp->lstatus);
3095 if (lstatus & BD_LFLAG(RXBD_EMPTY))
3098 /* order rx buffer descriptor reads */
3101 /* fetch next to clean buffer from the ring */
3102 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
3109 if (unlikely(++i == rx_queue->rx_ring_size))
3112 rx_queue->next_to_clean = i;
3114 /* fetch next buffer if not the last in frame */
3115 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
3118 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
3119 count_errors(lstatus, ndev);
3121 /* discard faulty buffer */
3124 rx_queue->stats.rx_dropped++;
3128 gfar_process_frame(ndev, skb);
3130 /* Increment the number of packets */
3132 total_bytes += skb->len;
3134 skb_record_rx_queue(skb, rx_queue->qindex);
3136 skb->protocol = eth_type_trans(skb, ndev);
3138 /* Send the packet up the stack */
3139 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3144 /* Store incomplete frames for completion */
3145 rx_queue->skb = skb;
3147 rx_queue->stats.rx_packets += total_pkts;
3148 rx_queue->stats.rx_bytes += total_bytes;
3151 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3153 /* Update Last Free RxBD pointer for LFC */
3154 if (unlikely(priv->tx_actual_en)) {
3155 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3157 gfar_write(rx_queue->rfbptr, bdp_dma);
3163 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3165 struct gfar_priv_grp *gfargrp =
3166 container_of(napi, struct gfar_priv_grp, napi_rx);
3167 struct gfar __iomem *regs = gfargrp->regs;
3168 struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3171 /* Clear IEVENT, so interrupts aren't called again
3172 * because of the packets that have already arrived
3174 gfar_write(®s->ievent, IEVENT_RX_MASK);
3176 work_done = gfar_clean_rx_ring(rx_queue, budget);
3178 if (work_done < budget) {
3180 napi_complete(napi);
3181 /* Clear the halt bit in RSTAT */
3182 gfar_write(®s->rstat, gfargrp->rstat);
3184 spin_lock_irq(&gfargrp->grplock);
3185 imask = gfar_read(®s->imask);
3186 imask |= IMASK_RX_DEFAULT;
3187 gfar_write(®s->imask, imask);
3188 spin_unlock_irq(&gfargrp->grplock);
3194 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3196 struct gfar_priv_grp *gfargrp =
3197 container_of(napi, struct gfar_priv_grp, napi_tx);
3198 struct gfar __iomem *regs = gfargrp->regs;
3199 struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3202 /* Clear IEVENT, so interrupts aren't called again
3203 * because of the packets that have already arrived
3205 gfar_write(®s->ievent, IEVENT_TX_MASK);
3207 /* run Tx cleanup to completion */
3208 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3209 gfar_clean_tx_ring(tx_queue);
3211 napi_complete(napi);
3213 spin_lock_irq(&gfargrp->grplock);
3214 imask = gfar_read(®s->imask);
3215 imask |= IMASK_TX_DEFAULT;
3216 gfar_write(®s->imask, imask);
3217 spin_unlock_irq(&gfargrp->grplock);
3222 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3224 struct gfar_priv_grp *gfargrp =
3225 container_of(napi, struct gfar_priv_grp, napi_rx);
3226 struct gfar_private *priv = gfargrp->priv;
3227 struct gfar __iomem *regs = gfargrp->regs;
3228 struct gfar_priv_rx_q *rx_queue = NULL;
3229 int work_done = 0, work_done_per_q = 0;
3230 int i, budget_per_q = 0;
3231 unsigned long rstat_rxf;
3234 /* Clear IEVENT, so interrupts aren't called again
3235 * because of the packets that have already arrived
3237 gfar_write(®s->ievent, IEVENT_RX_MASK);
3239 rstat_rxf = gfar_read(®s->rstat) & RSTAT_RXF_MASK;
3241 num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3243 budget_per_q = budget/num_act_queues;
3245 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3246 /* skip queue if not active */
3247 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3250 rx_queue = priv->rx_queue[i];
3252 gfar_clean_rx_ring(rx_queue, budget_per_q);
3253 work_done += work_done_per_q;
3255 /* finished processing this queue */
3256 if (work_done_per_q < budget_per_q) {
3257 /* clear active queue hw indication */
3258 gfar_write(®s->rstat,
3259 RSTAT_CLEAR_RXF0 >> i);
3262 if (!num_act_queues)
3267 if (!num_act_queues) {
3269 napi_complete(napi);
3271 /* Clear the halt bit in RSTAT */
3272 gfar_write(®s->rstat, gfargrp->rstat);
3274 spin_lock_irq(&gfargrp->grplock);
3275 imask = gfar_read(®s->imask);
3276 imask |= IMASK_RX_DEFAULT;
3277 gfar_write(®s->imask, imask);
3278 spin_unlock_irq(&gfargrp->grplock);
3284 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3286 struct gfar_priv_grp *gfargrp =
3287 container_of(napi, struct gfar_priv_grp, napi_tx);
3288 struct gfar_private *priv = gfargrp->priv;
3289 struct gfar __iomem *regs = gfargrp->regs;
3290 struct gfar_priv_tx_q *tx_queue = NULL;
3291 int has_tx_work = 0;
3294 /* Clear IEVENT, so interrupts aren't called again
3295 * because of the packets that have already arrived
3297 gfar_write(®s->ievent, IEVENT_TX_MASK);
3299 for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3300 tx_queue = priv->tx_queue[i];
3301 /* run Tx cleanup to completion */
3302 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3303 gfar_clean_tx_ring(tx_queue);
3310 napi_complete(napi);
3312 spin_lock_irq(&gfargrp->grplock);
3313 imask = gfar_read(®s->imask);
3314 imask |= IMASK_TX_DEFAULT;
3315 gfar_write(®s->imask, imask);
3316 spin_unlock_irq(&gfargrp->grplock);
3323 #ifdef CONFIG_NET_POLL_CONTROLLER
3324 /* Polling 'interrupt' - used by things like netconsole to send skbs
3325 * without having to re-enable interrupts. It's not called while
3326 * the interrupt routine is executing.
3328 static void gfar_netpoll(struct net_device *dev)
3330 struct gfar_private *priv = netdev_priv(dev);
3333 /* If the device has multiple interrupts, run tx/rx */
3334 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3335 for (i = 0; i < priv->num_grps; i++) {
3336 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3338 disable_irq(gfar_irq(grp, TX)->irq);
3339 disable_irq(gfar_irq(grp, RX)->irq);
3340 disable_irq(gfar_irq(grp, ER)->irq);
3341 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3342 enable_irq(gfar_irq(grp, ER)->irq);
3343 enable_irq(gfar_irq(grp, RX)->irq);
3344 enable_irq(gfar_irq(grp, TX)->irq);
3347 for (i = 0; i < priv->num_grps; i++) {
3348 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3350 disable_irq(gfar_irq(grp, TX)->irq);
3351 gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3352 enable_irq(gfar_irq(grp, TX)->irq);
3358 /* The interrupt handler for devices with one interrupt */
3359 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3361 struct gfar_priv_grp *gfargrp = grp_id;
3363 /* Save ievent for future reference */
3364 u32 events = gfar_read(&gfargrp->regs->ievent);
3366 /* Check for reception */
3367 if (events & IEVENT_RX_MASK)
3368 gfar_receive(irq, grp_id);
3370 /* Check for transmit completion */
3371 if (events & IEVENT_TX_MASK)
3372 gfar_transmit(irq, grp_id);
3374 /* Check for errors */
3375 if (events & IEVENT_ERR_MASK)
3376 gfar_error(irq, grp_id);
3381 /* Called every time the controller might need to be made
3382 * aware of new link state. The PHY code conveys this
3383 * information through variables in the phydev structure, and this
3384 * function converts those variables into the appropriate
3385 * register values, and can bring down the device if needed.
3387 static void adjust_link(struct net_device *dev)
3389 struct gfar_private *priv = netdev_priv(dev);
3390 struct phy_device *phydev = priv->phydev;
3392 if (unlikely(phydev->link != priv->oldlink ||
3393 (phydev->link && (phydev->duplex != priv->oldduplex ||
3394 phydev->speed != priv->oldspeed))))
3395 gfar_update_link_state(priv);
3398 /* Update the hash table based on the current list of multicast
3399 * addresses we subscribe to. Also, change the promiscuity of
3400 * the device based on the flags (this function is called
3401 * whenever dev->flags is changed
3403 static void gfar_set_multi(struct net_device *dev)
3405 struct netdev_hw_addr *ha;
3406 struct gfar_private *priv = netdev_priv(dev);
3407 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3410 if (dev->flags & IFF_PROMISC) {
3411 /* Set RCTRL to PROM */
3412 tempval = gfar_read(®s->rctrl);
3413 tempval |= RCTRL_PROM;
3414 gfar_write(®s->rctrl, tempval);
3416 /* Set RCTRL to not PROM */
3417 tempval = gfar_read(®s->rctrl);
3418 tempval &= ~(RCTRL_PROM);
3419 gfar_write(®s->rctrl, tempval);
3422 if (dev->flags & IFF_ALLMULTI) {
3423 /* Set the hash to rx all multicast frames */
3424 gfar_write(®s->igaddr0, 0xffffffff);
3425 gfar_write(®s->igaddr1, 0xffffffff);
3426 gfar_write(®s->igaddr2, 0xffffffff);
3427 gfar_write(®s->igaddr3, 0xffffffff);
3428 gfar_write(®s->igaddr4, 0xffffffff);
3429 gfar_write(®s->igaddr5, 0xffffffff);
3430 gfar_write(®s->igaddr6, 0xffffffff);
3431 gfar_write(®s->igaddr7, 0xffffffff);
3432 gfar_write(®s->gaddr0, 0xffffffff);
3433 gfar_write(®s->gaddr1, 0xffffffff);
3434 gfar_write(®s->gaddr2, 0xffffffff);
3435 gfar_write(®s->gaddr3, 0xffffffff);
3436 gfar_write(®s->gaddr4, 0xffffffff);
3437 gfar_write(®s->gaddr5, 0xffffffff);
3438 gfar_write(®s->gaddr6, 0xffffffff);
3439 gfar_write(®s->gaddr7, 0xffffffff);
3444 /* zero out the hash */
3445 gfar_write(®s->igaddr0, 0x0);
3446 gfar_write(®s->igaddr1, 0x0);
3447 gfar_write(®s->igaddr2, 0x0);
3448 gfar_write(®s->igaddr3, 0x0);
3449 gfar_write(®s->igaddr4, 0x0);
3450 gfar_write(®s->igaddr5, 0x0);
3451 gfar_write(®s->igaddr6, 0x0);
3452 gfar_write(®s->igaddr7, 0x0);
3453 gfar_write(®s->gaddr0, 0x0);
3454 gfar_write(®s->gaddr1, 0x0);
3455 gfar_write(®s->gaddr2, 0x0);
3456 gfar_write(®s->gaddr3, 0x0);
3457 gfar_write(®s->gaddr4, 0x0);
3458 gfar_write(®s->gaddr5, 0x0);
3459 gfar_write(®s->gaddr6, 0x0);
3460 gfar_write(®s->gaddr7, 0x0);
3462 /* If we have extended hash tables, we need to
3463 * clear the exact match registers to prepare for
3466 if (priv->extended_hash) {
3467 em_num = GFAR_EM_NUM + 1;
3468 gfar_clear_exact_match(dev);
3475 if (netdev_mc_empty(dev))
3478 /* Parse the list, and set the appropriate bits */
3479 netdev_for_each_mc_addr(ha, dev) {
3481 gfar_set_mac_for_addr(dev, idx, ha->addr);
3484 gfar_set_hash_for_addr(dev, ha->addr);
3490 /* Clears each of the exact match registers to zero, so they
3491 * don't interfere with normal reception
3493 static void gfar_clear_exact_match(struct net_device *dev)
3496 static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3498 for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3499 gfar_set_mac_for_addr(dev, idx, zero_arr);
3502 /* Set the appropriate hash bit for the given addr */
3503 /* The algorithm works like so:
3504 * 1) Take the Destination Address (ie the multicast address), and
3505 * do a CRC on it (little endian), and reverse the bits of the
3507 * 2) Use the 8 most significant bits as a hash into a 256-entry
3508 * table. The table is controlled through 8 32-bit registers:
3509 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3510 * gaddr7. This means that the 3 most significant bits in the
3511 * hash index which gaddr register to use, and the 5 other bits
3512 * indicate which bit (assuming an IBM numbering scheme, which
3513 * for PowerPC (tm) is usually the case) in the register holds
3516 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3519 struct gfar_private *priv = netdev_priv(dev);
3520 u32 result = ether_crc(ETH_ALEN, addr);
3521 int width = priv->hash_width;
3522 u8 whichbit = (result >> (32 - width)) & 0x1f;
3523 u8 whichreg = result >> (32 - width + 5);
3524 u32 value = (1 << (31-whichbit));
3526 tempval = gfar_read(priv->hash_regs[whichreg]);
3528 gfar_write(priv->hash_regs[whichreg], tempval);
3532 /* There are multiple MAC Address register pairs on some controllers
3533 * This function sets the numth pair to a given address
3535 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3538 struct gfar_private *priv = netdev_priv(dev);
3539 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3541 u32 __iomem *macptr = ®s->macstnaddr1;
3545 /* For a station address of 0x12345678ABCD in transmission
3546 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3547 * MACnADDR2 is set to 0x34120000.
3549 tempval = (addr[5] << 24) | (addr[4] << 16) |
3550 (addr[3] << 8) | addr[2];
3552 gfar_write(macptr, tempval);
3554 tempval = (addr[1] << 24) | (addr[0] << 16);
3556 gfar_write(macptr+1, tempval);
3559 /* GFAR error interrupt handler */
3560 static irqreturn_t gfar_error(int irq, void *grp_id)
3562 struct gfar_priv_grp *gfargrp = grp_id;
3563 struct gfar __iomem *regs = gfargrp->regs;
3564 struct gfar_private *priv= gfargrp->priv;
3565 struct net_device *dev = priv->ndev;
3567 /* Save ievent for future reference */
3568 u32 events = gfar_read(®s->ievent);
3571 gfar_write(®s->ievent, events & IEVENT_ERR_MASK);
3573 /* Magic Packet is not an error. */
3574 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3575 (events & IEVENT_MAG))
3576 events &= ~IEVENT_MAG;
3579 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3581 "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3582 events, gfar_read(®s->imask));
3584 /* Update the error counters */
3585 if (events & IEVENT_TXE) {
3586 dev->stats.tx_errors++;
3588 if (events & IEVENT_LC)
3589 dev->stats.tx_window_errors++;
3590 if (events & IEVENT_CRL)
3591 dev->stats.tx_aborted_errors++;
3592 if (events & IEVENT_XFUN) {
3593 netif_dbg(priv, tx_err, dev,
3594 "TX FIFO underrun, packet dropped\n");
3595 dev->stats.tx_dropped++;
3596 atomic64_inc(&priv->extra_stats.tx_underrun);
3598 schedule_work(&priv->reset_task);
3600 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3602 if (events & IEVENT_BSY) {
3603 dev->stats.rx_over_errors++;
3604 atomic64_inc(&priv->extra_stats.rx_bsy);
3606 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3607 gfar_read(®s->rstat));
3609 if (events & IEVENT_BABR) {
3610 dev->stats.rx_errors++;
3611 atomic64_inc(&priv->extra_stats.rx_babr);
3613 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3615 if (events & IEVENT_EBERR) {
3616 atomic64_inc(&priv->extra_stats.eberr);
3617 netif_dbg(priv, rx_err, dev, "bus error\n");
3619 if (events & IEVENT_RXC)
3620 netif_dbg(priv, rx_status, dev, "control frame\n");
3622 if (events & IEVENT_BABT) {
3623 atomic64_inc(&priv->extra_stats.tx_babt);
3624 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3629 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3631 struct phy_device *phydev = priv->phydev;
3634 if (!phydev->duplex)
3637 if (!priv->pause_aneg_en) {
3638 if (priv->tx_pause_en)
3639 val |= MACCFG1_TX_FLOW;
3640 if (priv->rx_pause_en)
3641 val |= MACCFG1_RX_FLOW;
3643 u16 lcl_adv, rmt_adv;
3645 /* get link partner capabilities */
3648 rmt_adv = LPA_PAUSE_CAP;
3649 if (phydev->asym_pause)
3650 rmt_adv |= LPA_PAUSE_ASYM;
3653 if (phydev->advertising & ADVERTISED_Pause)
3654 lcl_adv |= ADVERTISE_PAUSE_CAP;
3655 if (phydev->advertising & ADVERTISED_Asym_Pause)
3656 lcl_adv |= ADVERTISE_PAUSE_ASYM;
3658 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3659 if (flowctrl & FLOW_CTRL_TX)
3660 val |= MACCFG1_TX_FLOW;
3661 if (flowctrl & FLOW_CTRL_RX)
3662 val |= MACCFG1_RX_FLOW;
3668 static noinline void gfar_update_link_state(struct gfar_private *priv)
3670 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3671 struct phy_device *phydev = priv->phydev;
3672 struct gfar_priv_rx_q *rx_queue = NULL;
3675 if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3679 u32 tempval1 = gfar_read(®s->maccfg1);
3680 u32 tempval = gfar_read(®s->maccfg2);
3681 u32 ecntrl = gfar_read(®s->ecntrl);
3682 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW);
3684 if (phydev->duplex != priv->oldduplex) {
3685 if (!(phydev->duplex))
3686 tempval &= ~(MACCFG2_FULL_DUPLEX);
3688 tempval |= MACCFG2_FULL_DUPLEX;
3690 priv->oldduplex = phydev->duplex;
3693 if (phydev->speed != priv->oldspeed) {
3694 switch (phydev->speed) {
3697 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3699 ecntrl &= ~(ECNTRL_R100);
3704 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3706 /* Reduced mode distinguishes
3707 * between 10 and 100
3709 if (phydev->speed == SPEED_100)
3710 ecntrl |= ECNTRL_R100;
3712 ecntrl &= ~(ECNTRL_R100);
3715 netif_warn(priv, link, priv->ndev,
3716 "Ack! Speed (%d) is not 10/100/1000!\n",
3721 priv->oldspeed = phydev->speed;
3724 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3725 tempval1 |= gfar_get_flowctrl_cfg(priv);
3727 /* Turn last free buffer recording on */
3728 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3729 for (i = 0; i < priv->num_rx_queues; i++) {
3732 rx_queue = priv->rx_queue[i];
3733 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3734 gfar_write(rx_queue->rfbptr, bdp_dma);
3737 priv->tx_actual_en = 1;
3740 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3741 priv->tx_actual_en = 0;
3743 gfar_write(®s->maccfg1, tempval1);
3744 gfar_write(®s->maccfg2, tempval);
3745 gfar_write(®s->ecntrl, ecntrl);
3750 } else if (priv->oldlink) {
3753 priv->oldduplex = -1;
3756 if (netif_msg_link(priv))
3757 phy_print_status(phydev);
3760 static const struct of_device_id gfar_match[] =
3764 .compatible = "gianfar",
3767 .compatible = "fsl,etsec2",
3771 MODULE_DEVICE_TABLE(of, gfar_match);
3773 /* Structure for a device driver */
3774 static struct platform_driver gfar_driver = {
3776 .name = "fsl-gianfar",
3778 .of_match_table = gfar_match,
3780 .probe = gfar_probe,
3781 .remove = gfar_remove,
3784 module_platform_driver(gfar_driver);