drivers/net/ethernet/freescale/gianfar.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* drivers/net/ethernet/freescale/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  12  *
  13  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  14  * Copyright 2007 MontaVista Software, Inc.
  15  *
  16  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  17  *  RA 11 31 24.2
  18  *  Dec +69 19 52
  19  *  V 3.84
  20  *  B-V +1.62
  21  *
  22  *  Theory of operation
  23  *
  24  *  The driver is initialized through of_device. Configuration information
  25  *  is therefore conveyed through an OF-style device tree.
  26  *
  27  *  The Gianfar Ethernet Controller uses a ring of buffer
  28  *  descriptors.  The beginning is indicated by a register
  29  *  pointing to the physical address of the start of the ring.
  30  *  The end is determined by a "wrap" bit being set in the
  31  *  last descriptor of the ring.
  32  *
  33  *  When a packet is received, the RXF bit in the
  34  *  IEVENT register is set, triggering an interrupt when the
  35  *  corresponding bit in the IMASK register is also set (if
  36  *  interrupt coalescing is active, then the interrupt may not
  37  *  happen immediately, but will wait until either a set number
  38  *  of frames or amount of time have passed).  In NAPI, the
  39  *  interrupt handler will signal there is work to be done, and
  40  *  exit. This method will start at the last known empty
  41  *  descriptor, and process every subsequent descriptor until there
  42  *  are none left with data (NAPI will stop after a set number of
  43  *  packets to give time to other tasks, but will eventually
  44  *  process all the packets).  The data arrives inside a
  45  *  pre-allocated skb, and so after the skb is passed up to the
  46  *  stack, a new skb must be allocated, and the address field in
  47  *  the buffer descriptor must be updated to indicate this new
  48  *  skb.
  49  *
  50  *  When the kernel requests that a packet be transmitted, the
  51  *  driver starts where it left off last time, and points the
  52  *  descriptor at the buffer which was passed in.  The driver
  53  *  then informs the DMA engine that there are packets ready to
  54  *  be transmitted.  Once the controller is finished transmitting
  55  *  the packet, an interrupt may be triggered (under the same
  56  *  conditions as for reception, but depending on the TXF bit).
  57  *  The driver then cleans up the buffer.
  58  */
  59
  60 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  61 #define DEBUG
  62
  63 #include <linux/kernel.h>
  64 #include <linux/string.h>
  65 #include <linux/errno.h>
  66 #include <linux/unistd.h>
  67 #include <linux/slab.h>
  68 #include <linux/interrupt.h>
  69 #include <linux/delay.h>
  70 #include <linux/netdevice.h>
  71 #include <linux/etherdevice.h>
  72 #include <linux/skbuff.h>
  73 #include <linux/if_vlan.h>
  74 #include <linux/spinlock.h>
  75 #include <linux/mm.h>
  76 #include <linux/of_address.h>
  77 #include <linux/of_irq.h>
  78 #include <linux/of_mdio.h>
  79 #include <linux/of_platform.h>
  80 #include <linux/ip.h>
  81 #include <linux/tcp.h>
  82 #include <linux/udp.h>
  83 #include <linux/in.h>
  84 #include <linux/net_tstamp.h>
  85
  86 #include <asm/io.h>
  87 #ifdef CONFIG_PPC
  88 #include <asm/reg.h>
  89 #include <asm/mpc85xx.h>
  90 #endif
  91 #include <asm/irq.h>
  92 #include <linux/uaccess.h>
  93 #include <linux/module.h>
  94 #include <linux/dma-mapping.h>
  95 #include <linux/crc32.h>
  96 #include <linux/mii.h>
  97 #include <linux/phy.h>
  98 #include <linux/phy_fixed.h>
  99 #include <linux/of.h>
 100 #include <linux/of_net.h>
 101
 102 #include "gianfar.h"
 103
 104 #define TX_TIMEOUT      (5*HZ)
 105
 106 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 107 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 108 MODULE_LICENSE("GPL");
 109
 110 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 111                             dma_addr_t buf)
 112 {
 113         u32 lstatus;
 114
 115         bdp->bufPtr = cpu_to_be32(buf);
 116
 117         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 118         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 119                 lstatus |= BD_LFLAG(RXBD_WRAP);
 120
 121         gfar_wmb();
 122
 123         bdp->lstatus = cpu_to_be32(lstatus);
 124 }
 125
 126 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 127 {
 128         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 129         u32 __iomem *baddr;
 130         int i;
 131
 132         baddr = &regs->tbase0;
 133         for (i = 0; i < priv->num_tx_queues; i++) {
 134                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 135                 baddr += 2;
 136         }
 137
 138         baddr = &regs->rbase0;
 139         for (i = 0; i < priv->num_rx_queues; i++) {
 140                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 141                 baddr += 2;
 142         }
 143 }
 144
 145 static void gfar_init_rqprm(struct gfar_private *priv)
 146 {
 147         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 148         u32 __iomem *baddr;
 149         int i;
 150
 151         baddr = &regs->rqprm0;
 152         for (i = 0; i < priv->num_rx_queues; i++) {
 153                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 154                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 155                 baddr++;
 156         }
 157 }
 158
 159 static void gfar_rx_offload_en(struct gfar_private *priv)
 160 {
 161         /* set this when rx hw offload (TOE) functions are being used */
 162         priv->uses_rxfcb = 0;
 163
 164         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 165                 priv->uses_rxfcb = 1;
 166
 167         if (priv->hwts_rx_en || priv->rx_filer_enable)
 168                 priv->uses_rxfcb = 1;
 169 }
 170
 171 static void gfar_mac_rx_config(struct gfar_private *priv)
 172 {
 173         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 174         u32 rctrl = 0;
 175
 176         if (priv->rx_filer_enable) {
 177                 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
 178                 /* Program the RIR0 reg with the required distribution */
 179                 if (priv->poll_mode == GFAR_SQ_POLLING)
 180                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 181                 else /* GFAR_MQ_POLLING */
 182                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 183         }
 184
 185         /* Restore PROMISC mode */
 186         if (priv->ndev->flags & IFF_PROMISC)
 187                 rctrl |= RCTRL_PROM;
 188
 189         if (priv->ndev->features & NETIF_F_RXCSUM)
 190                 rctrl |= RCTRL_CHECKSUMMING;
 191
 192         if (priv->extended_hash)
 193                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 194
 195         if (priv->padding) {
 196                 rctrl &= ~RCTRL_PAL_MASK;
 197                 rctrl |= RCTRL_PADDING(priv->padding);
 198         }
 199
 200         /* Enable HW time stamping if requested from user space */
 201         if (priv->hwts_rx_en)
 202                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 203
 204         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 205                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 206
 207         /* Clear the LFC bit */
 208         gfar_write(&regs->rctrl, rctrl);
 209         /* Init flow control threshold values */
 210         gfar_init_rqprm(priv);
 211         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 212         rctrl |= RCTRL_LFC;
 213
 214         /* Init rctrl based on our settings */
 215         gfar_write(&regs->rctrl, rctrl);
 216 }
 217
 218 static void gfar_mac_tx_config(struct gfar_private *priv)
 219 {
 220         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 221         u32 tctrl = 0;
 222
 223         if (priv->ndev->features & NETIF_F_IP_CSUM)
 224                 tctrl |= TCTRL_INIT_CSUM;
 225
 226         if (priv->prio_sched_en)
 227                 tctrl |= TCTRL_TXSCHED_PRIO;
 228         else {
 229                 tctrl |= TCTRL_TXSCHED_WRRS;
 230                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 231                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 232         }
 233
 234         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 235                 tctrl |= TCTRL_VLINS;
 236
 237         gfar_write(&regs->tctrl, tctrl);
 238 }
 239
 240 static void gfar_configure_coalescing(struct gfar_private *priv,
 241                                unsigned long tx_mask, unsigned long rx_mask)
 242 {
 243         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 244         u32 __iomem *baddr;
 245
 246         if (priv->mode == MQ_MG_MODE) {
 247                 int i = 0;
 248
 249                 baddr = &regs->txic0;
 250                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 251                         gfar_write(baddr + i, 0);
 252                         if (likely(priv->tx_queue[i]->txcoalescing))
 253                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 254                 }
 255
 256                 baddr = &regs->rxic0;
 257                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 258                         gfar_write(baddr + i, 0);
 259                         if (likely(priv->rx_queue[i]->rxcoalescing))
 260                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 261                 }
 262         } else {
 263                 /* Backward compatible case -- even if we enable
 264                  * multiple queues, there's only single reg to program
 265                  */
 266                 gfar_write(&regs->txic, 0);
 267                 if (likely(priv->tx_queue[0]->txcoalescing))
 268                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 269
 270                 gfar_write(&regs->rxic, 0);
 271                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 272                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 273         }
 274 }
 275
 276 static void gfar_configure_coalescing_all(struct gfar_private *priv)
 277 {
 278         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 279 }
 280
 281 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 282 {
 283         struct gfar_private *priv = netdev_priv(dev);
 284         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 285         unsigned long tx_packets = 0, tx_bytes = 0;
 286         int i;
 287
 288         for (i = 0; i < priv->num_rx_queues; i++) {
 289                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 290                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 291                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 292         }
 293
 294         dev->stats.rx_packets = rx_packets;
 295         dev->stats.rx_bytes   = rx_bytes;
 296         dev->stats.rx_dropped = rx_dropped;
 297
 298         for (i = 0; i < priv->num_tx_queues; i++) {
 299                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 300                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 301         }
 302
 303         dev->stats.tx_bytes   = tx_bytes;
 304         dev->stats.tx_packets = tx_packets;
 305
 306         return &dev->stats;
 307 }
 308
 309 /* Set the appropriate hash bit for the given addr */
 310 /* The algorithm works like so:
 311  * 1) Take the Destination Address (ie the multicast address), and
 312  * do a CRC on it (little endian), and reverse the bits of the
 313  * result.
 314  * 2) Use the 8 most significant bits as a hash into a 256-entry
 315  * table.  The table is controlled through 8 32-bit registers:
 316  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
 317  * gaddr7.  This means that the 3 most significant bits in the
 318  * hash index which gaddr register to use, and the 5 other bits
 319  * indicate which bit (assuming an IBM numbering scheme, which
 320  * for PowerPC (tm) is usually the case) in the register holds
 321  * the entry.
 322  */
 323 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
 324 {
 325         u32 tempval;
 326         struct gfar_private *priv = netdev_priv(dev);
 327         u32 result = ether_crc(ETH_ALEN, addr);
 328         int width = priv->hash_width;
 329         u8 whichbit = (result >> (32 - width)) & 0x1f;
 330         u8 whichreg = result >> (32 - width + 5);
 331         u32 value = (1 << (31-whichbit));
 332
 333         tempval = gfar_read(priv->hash_regs[whichreg]);
 334         tempval |= value;
 335         gfar_write(priv->hash_regs[whichreg], tempval);
 336 }
 337
 338 /* There are multiple MAC Address register pairs on some controllers
 339  * This function sets the numth pair to a given address
 340  */
 341 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 342                                   const u8 *addr)
 343 {
 344         struct gfar_private *priv = netdev_priv(dev);
 345         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 346         u32 tempval;
 347         u32 __iomem *macptr = &regs->macstnaddr1;
 348
 349         macptr += num*2;
 350
 351         /* For a station address of 0x12345678ABCD in transmission
 352          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
 353          * MACnADDR2 is set to 0x34120000.
 354          */
 355         tempval = (addr[5] << 24) | (addr[4] << 16) |
 356                   (addr[3] << 8)  |  addr[2];
 357
 358         gfar_write(macptr, tempval);
 359
 360         tempval = (addr[1] << 24) | (addr[0] << 16);
 361
 362         gfar_write(macptr+1, tempval);
 363 }
 364
 365 static int gfar_set_mac_addr(struct net_device *dev, void *p)
 366 {
 367         int ret;
 368
 369         ret = eth_mac_addr(dev, p);
 370         if (ret)
 371                 return ret;
 372
 373         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 374
 375         return 0;
 376 }
 377
 378 static void gfar_ints_disable(struct gfar_private *priv)
 379 {
 380         int i;
 381         for (i = 0; i < priv->num_grps; i++) {
 382                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 383                 /* Clear IEVENT */
 384                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 385
 386                 /* Initialize IMASK */
 387                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 388         }
 389 }
 390
 391 static void gfar_ints_enable(struct gfar_private *priv)
 392 {
 393         int i;
 394         for (i = 0; i < priv->num_grps; i++) {
 395                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 396                 /* Unmask the interrupts we look for */
 397                 gfar_write(&regs->imask, IMASK_DEFAULT);
 398         }
 399 }
 400
 401 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 402 {
 403         int i;
 404
 405         for (i = 0; i < priv->num_tx_queues; i++) {
 406                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 407                                             GFP_KERNEL);
 408                 if (!priv->tx_queue[i])
 409                         return -ENOMEM;
 410
 411                 priv->tx_queue[i]->tx_skbuff = NULL;
 412                 priv->tx_queue[i]->qindex = i;
 413                 priv->tx_queue[i]->dev = priv->ndev;
 414                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 415         }
 416         return 0;
 417 }
 418
 419 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 420 {
 421         int i;
 422
 423         for (i = 0; i < priv->num_rx_queues; i++) {
 424                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 425                                             GFP_KERNEL);
 426                 if (!priv->rx_queue[i])
 427                         return -ENOMEM;
 428
 429                 priv->rx_queue[i]->qindex = i;
 430                 priv->rx_queue[i]->ndev = priv->ndev;
 431         }
 432         return 0;
 433 }
 434
 435 static void gfar_free_tx_queues(struct gfar_private *priv)
 436 {
 437         int i;
 438
 439         for (i = 0; i < priv->num_tx_queues; i++)
 440                 kfree(priv->tx_queue[i]);
 441 }
 442
 443 static void gfar_free_rx_queues(struct gfar_private *priv)
 444 {
 445         int i;
 446
 447         for (i = 0; i < priv->num_rx_queues; i++)
 448                 kfree(priv->rx_queue[i]);
 449 }
 450
 451 static void unmap_group_regs(struct gfar_private *priv)
 452 {
 453         int i;
 454
 455         for (i = 0; i < MAXGROUPS; i++)
 456                 if (priv->gfargrp[i].regs)
 457                         iounmap(priv->gfargrp[i].regs);
 458 }
 459
 460 static void free_gfar_dev(struct gfar_private *priv)
 461 {
 462         int i, j;
 463
 464         for (i = 0; i < priv->num_grps; i++)
 465                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 466                         kfree(priv->gfargrp[i].irqinfo[j]);
 467                         priv->gfargrp[i].irqinfo[j] = NULL;
 468                 }
 469
 470         free_netdev(priv->ndev);
 471 }
 472
 473 static void disable_napi(struct gfar_private *priv)
 474 {
 475         int i;
 476
 477         for (i = 0; i < priv->num_grps; i++) {
 478                 napi_disable(&priv->gfargrp[i].napi_rx);
 479                 napi_disable(&priv->gfargrp[i].napi_tx);
 480         }
 481 }
 482
 483 static void enable_napi(struct gfar_private *priv)
 484 {
 485         int i;
 486
 487         for (i = 0; i < priv->num_grps; i++) {
 488                 napi_enable(&priv->gfargrp[i].napi_rx);
 489                 napi_enable(&priv->gfargrp[i].napi_tx);
 490         }
 491 }
 492
 493 static int gfar_parse_group(struct device_node *np,
 494                             struct gfar_private *priv, const char *model)
 495 {
 496         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 497         int i;
 498
 499         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 500                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 501                                           GFP_KERNEL);
 502                 if (!grp->irqinfo[i])
 503                         return -ENOMEM;
 504         }
 505
 506         grp->regs = of_iomap(np, 0);
 507         if (!grp->regs)
 508                 return -ENOMEM;
 509
 510         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 511
 512         /* If we aren't the FEC we have multiple interrupts */
 513         if (model && strcasecmp(model, "FEC")) {
 514                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 515                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 516                 if (!gfar_irq(grp, TX)->irq ||
 517                     !gfar_irq(grp, RX)->irq ||
 518                     !gfar_irq(grp, ER)->irq)
 519                         return -EINVAL;
 520         }
 521
 522         grp->priv = priv;
 523         spin_lock_init(&grp->grplock);
 524         if (priv->mode == MQ_MG_MODE) {
 525                 u32 rxq_mask, txq_mask;
 526                 int ret;
 527
 528                 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 529                 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 530
 531                 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
 532                 if (!ret) {
 533                         grp->rx_bit_map = rxq_mask ?
 534                         rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 535                 }
 536
 537                 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
 538                 if (!ret) {
 539                         grp->tx_bit_map = txq_mask ?
 540                         txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 541                 }
 542
 543                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 544                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 545                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 546                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 547                 }
 548         } else {
 549                 grp->rx_bit_map = 0xFF;
 550                 grp->tx_bit_map = 0xFF;
 551         }
 552
 553         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 554          * right to left, so we need to revert the 8 bits to get the q index
 555          */
 556         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 557         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 558
 559         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 560          * also assign queues to groups
 561          */
 562         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 563                 if (!grp->rx_queue)
 564                         grp->rx_queue = priv->rx_queue[i];
 565                 grp->num_rx_queues++;
 566                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 567                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 568                 priv->rx_queue[i]->grp = grp;
 569         }
 570
 571         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 572                 if (!grp->tx_queue)
 573                         grp->tx_queue = priv->tx_queue[i];
 574                 grp->num_tx_queues++;
 575                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 576                 priv->tqueue |= (TQUEUE_EN0 >> i);
 577                 priv->tx_queue[i]->grp = grp;
 578         }
 579
 580         priv->num_grps++;
 581
 582         return 0;
 583 }
 584
 585 static int gfar_of_group_count(struct device_node *np)
 586 {
 587         struct device_node *child;
 588         int num = 0;
 589
 590         for_each_available_child_of_node(np, child)
 591                 if (of_node_name_eq(child, "queue-group"))
 592                         num++;
 593
 594         return num;
 595 }
 596
 597 /* Reads the controller's registers to determine what interface
 598  * connects it to the PHY.
 599  */
 600 static phy_interface_t gfar_get_interface(struct net_device *dev)
 601 {
 602         struct gfar_private *priv = netdev_priv(dev);
 603         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 604         u32 ecntrl;
 605
 606         ecntrl = gfar_read(&regs->ecntrl);
 607
 608         if (ecntrl & ECNTRL_SGMII_MODE)
 609                 return PHY_INTERFACE_MODE_SGMII;
 610
 611         if (ecntrl & ECNTRL_TBI_MODE) {
 612                 if (ecntrl & ECNTRL_REDUCED_MODE)
 613                         return PHY_INTERFACE_MODE_RTBI;
 614                 else
 615                         return PHY_INTERFACE_MODE_TBI;
 616         }
 617
 618         if (ecntrl & ECNTRL_REDUCED_MODE) {
 619                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
 620                         return PHY_INTERFACE_MODE_RMII;
 621                 }
 622                 else {
 623                         phy_interface_t interface = priv->interface;
 624
 625                         /* This isn't autodetected right now, so it must
 626                          * be set by the device tree or platform code.
 627                          */
 628                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
 629                                 return PHY_INTERFACE_MODE_RGMII_ID;
 630
 631                         return PHY_INTERFACE_MODE_RGMII;
 632                 }
 633         }
 634
 635         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
 636                 return PHY_INTERFACE_MODE_GMII;
 637
 638         return PHY_INTERFACE_MODE_MII;
 639 }
 640
 641 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 642 {
 643         const char *model;
 644         const void *mac_addr;
 645         int err = 0, i;
 646         phy_interface_t interface;
 647         struct net_device *dev = NULL;
 648         struct gfar_private *priv = NULL;
 649         struct device_node *np = ofdev->dev.of_node;
 650         struct device_node *child = NULL;
 651         u32 stash_len = 0;
 652         u32 stash_idx = 0;
 653         unsigned int num_tx_qs, num_rx_qs;
 654         unsigned short mode, poll_mode;
 655
 656         if (!np)
 657                 return -ENODEV;
 658
 659         if (of_device_is_compatible(np, "fsl,etsec2")) {
 660                 mode = MQ_MG_MODE;
 661                 poll_mode = GFAR_SQ_POLLING;
 662         } else {
 663                 mode = SQ_SG_MODE;
 664                 poll_mode = GFAR_SQ_POLLING;
 665         }
 666
 667         if (mode == SQ_SG_MODE) {
 668                 num_tx_qs = 1;
 669                 num_rx_qs = 1;
 670         } else { /* MQ_MG_MODE */
 671                 /* get the actual number of supported groups */
 672                 unsigned int num_grps = gfar_of_group_count(np);
 673
 674                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 675                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 676                                 num_grps);
 677                         pr_err("Cannot do alloc_etherdev, aborting\n");
 678                         return -EINVAL;
 679                 }
 680
 681                 if (poll_mode == GFAR_SQ_POLLING) {
 682                         num_tx_qs = num_grps; /* one txq per int group */
 683                         num_rx_qs = num_grps; /* one rxq per int group */
 684                 } else { /* GFAR_MQ_POLLING */
 685                         u32 tx_queues, rx_queues;
 686                         int ret;
 687
 688                         /* parse the num of HW tx and rx queues */
 689                         ret = of_property_read_u32(np, "fsl,num_tx_queues",
 690                                                    &tx_queues);
 691                         num_tx_qs = ret ? 1 : tx_queues;
 692
 693                         ret = of_property_read_u32(np, "fsl,num_rx_queues",
 694                                                    &rx_queues);
 695                         num_rx_qs = ret ? 1 : rx_queues;
 696                 }
 697         }
 698
 699         if (num_tx_qs > MAX_TX_QS) {
 700                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 701                        num_tx_qs, MAX_TX_QS);
 702                 pr_err("Cannot do alloc_etherdev, aborting\n");
 703                 return -EINVAL;
 704         }
 705
 706         if (num_rx_qs > MAX_RX_QS) {
 707                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 708                        num_rx_qs, MAX_RX_QS);
 709                 pr_err("Cannot do alloc_etherdev, aborting\n");
 710                 return -EINVAL;
 711         }
 712
 713         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 714         dev = *pdev;
 715         if (NULL == dev)
 716                 return -ENOMEM;
 717
 718         priv = netdev_priv(dev);
 719         priv->ndev = dev;
 720
 721         priv->mode = mode;
 722         priv->poll_mode = poll_mode;
 723
 724         priv->num_tx_queues = num_tx_qs;
 725         netif_set_real_num_rx_queues(dev, num_rx_qs);
 726         priv->num_rx_queues = num_rx_qs;
 727
 728         err = gfar_alloc_tx_queues(priv);
 729         if (err)
 730                 goto tx_alloc_failed;
 731
 732         err = gfar_alloc_rx_queues(priv);
 733         if (err)
 734                 goto rx_alloc_failed;
 735
 736         err = of_property_read_string(np, "model", &model);
 737         if (err) {
 738                 pr_err("Device model property missing, aborting\n");
 739                 goto rx_alloc_failed;
 740         }
 741
 742         /* Init Rx queue filer rule set linked list */
 743         INIT_LIST_HEAD(&priv->rx_list.list);
 744         priv->rx_list.count = 0;
 745         mutex_init(&priv->rx_queue_access);
 746
 747         for (i = 0; i < MAXGROUPS; i++)
 748                 priv->gfargrp[i].regs = NULL;
 749
 750         /* Parse and initialize group specific information */
 751         if (priv->mode == MQ_MG_MODE) {
 752                 for_each_available_child_of_node(np, child) {
 753                         if (!of_node_name_eq(child, "queue-group"))
 754                                 continue;
 755
 756                         err = gfar_parse_group(child, priv, model);
 757                         if (err) {
 758                                 of_node_put(child);
 759                                 goto err_grp_init;
 760                         }
 761                 }
 762         } else { /* SQ_SG_MODE */
 763                 err = gfar_parse_group(np, priv, model);
 764                 if (err)
 765                         goto err_grp_init;
 766         }
 767
 768         if (of_property_read_bool(np, "bd-stash")) {
 769                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 770                 priv->bd_stash_en = 1;
 771         }
 772
 773         err = of_property_read_u32(np, "rx-stash-len", &stash_len);
 774
 775         if (err == 0)
 776                 priv->rx_stash_size = stash_len;
 777
 778         err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
 779
 780         if (err == 0)
 781                 priv->rx_stash_index = stash_idx;
 782
 783         if (stash_len || stash_idx)
 784                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 785
 786         mac_addr = of_get_mac_address(np);
 787
 788         if (!IS_ERR(mac_addr)) {
 789                 ether_addr_copy(dev->dev_addr, mac_addr);
 790         } else {
 791                 eth_hw_addr_random(dev);
 792                 dev_info(&ofdev->dev, "Using random MAC address: %pM\n", dev->dev_addr);
 793         }
 794
 795         if (model && !strcasecmp(model, "TSEC"))
 796                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 797                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 798                                      FSL_GIANFAR_DEV_HAS_RMON |
 799                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 800
 801         if (model && !strcasecmp(model, "eTSEC"))
 802                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 803                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 804                                      FSL_GIANFAR_DEV_HAS_RMON |
 805                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 806                                      FSL_GIANFAR_DEV_HAS_CSUM |
 807                                      FSL_GIANFAR_DEV_HAS_VLAN |
 808                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 809                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 810                                      FSL_GIANFAR_DEV_HAS_TIMER |
 811                                      FSL_GIANFAR_DEV_HAS_RX_FILER;
 812
 813         /* Use PHY connection type from the DT node if one is specified there.
 814          * rgmii-id really needs to be specified. Other types can be
 815          * detected by hardware
 816          */
 817         err = of_get_phy_mode(np, &interface);
 818         if (!err)
 819                 priv->interface = interface;
 820         else
 821                 priv->interface = gfar_get_interface(dev);
 822
 823         if (of_find_property(np, "fsl,magic-packet", NULL))
 824                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 825
 826         if (of_get_property(np, "fsl,wake-on-filer", NULL))
 827                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
 828
 829         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 830
 831         /* In the case of a fixed PHY, the DT node associated
 832          * to the PHY is the Ethernet MAC DT node.
 833          */
 834         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 835                 err = of_phy_register_fixed_link(np);
 836                 if (err)
 837                         goto err_grp_init;
 838
 839                 priv->phy_node = of_node_get(np);
 840         }
 841
 842         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 843         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 844
 845         return 0;
 846
 847 err_grp_init:
 848         unmap_group_regs(priv);
 849 rx_alloc_failed:
 850         gfar_free_rx_queues(priv);
 851 tx_alloc_failed:
 852         gfar_free_tx_queues(priv);
 853         free_gfar_dev(priv);
 854         return err;
 855 }
 856
 857 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 858                                    u32 class)
 859 {
 860         u32 rqfpr = FPR_FILER_MASK;
 861         u32 rqfcr = 0x0;
 862
 863         rqfar--;
 864         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 865         priv->ftp_rqfpr[rqfar] = rqfpr;
 866         priv->ftp_rqfcr[rqfar] = rqfcr;
 867         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 868
 869         rqfar--;
 870         rqfcr = RQFCR_CMP_NOMATCH;
 871         priv->ftp_rqfpr[rqfar] = rqfpr;
 872         priv->ftp_rqfcr[rqfar] = rqfcr;
 873         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 874
 875         rqfar--;
 876         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 877         rqfpr = class;
 878         priv->ftp_rqfcr[rqfar] = rqfcr;
 879         priv->ftp_rqfpr[rqfar] = rqfpr;
 880         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 881
 882         rqfar--;
 883         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 884         rqfpr = class;
 885         priv->ftp_rqfcr[rqfar] = rqfcr;
 886         priv->ftp_rqfpr[rqfar] = rqfpr;
 887         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 888
 889         return rqfar;
 890 }
 891
 892 static void gfar_init_filer_table(struct gfar_private *priv)
 893 {
 894         int i = 0x0;
 895         u32 rqfar = MAX_FILER_IDX;
 896         u32 rqfcr = 0x0;
 897         u32 rqfpr = FPR_FILER_MASK;
 898
 899         /* Default rule */
 900         rqfcr = RQFCR_CMP_MATCH;
 901         priv->ftp_rqfcr[rqfar] = rqfcr;
 902         priv->ftp_rqfpr[rqfar] = rqfpr;
 903         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 904
 905         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 906         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 907         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 908         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 909         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 910         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 911
 912         /* cur_filer_idx indicated the first non-masked rule */
 913         priv->cur_filer_idx = rqfar;
 914
 915         /* Rest are masked rules */
 916         rqfcr = RQFCR_CMP_NOMATCH;
 917         for (i = 0; i < rqfar; i++) {
 918                 priv->ftp_rqfcr[i] = rqfcr;
 919                 priv->ftp_rqfpr[i] = rqfpr;
 920                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 921         }
 922 }
 923
 924 #ifdef CONFIG_PPC
 925 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
 926 {
 927         unsigned int pvr = mfspr(SPRN_PVR);
 928         unsigned int svr = mfspr(SPRN_SVR);
 929         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 930         unsigned int rev = svr & 0xffff;
 931
 932         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 933         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 934             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 935                 priv->errata |= GFAR_ERRATA_74;
 936
 937         /* MPC8313 and MPC837x all rev */
 938         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 939             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 940                 priv->errata |= GFAR_ERRATA_76;
 941
 942         /* MPC8313 Rev < 2.0 */
 943         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
 944                 priv->errata |= GFAR_ERRATA_12;
 945 }
 946
 947 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
 948 {
 949         unsigned int svr = mfspr(SPRN_SVR);
 950
 951         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
 952                 priv->errata |= GFAR_ERRATA_12;
 953         /* P2020/P1010 Rev 1; MPC8548 Rev 2 */
 954         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
 955             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
 956             ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
 957                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
 958 }
 959 #endif
 960
 961 static void gfar_detect_errata(struct gfar_private *priv)
 962 {
 963         struct device *dev = &priv->ofdev->dev;
 964
 965         /* no plans to fix */
 966         priv->errata |= GFAR_ERRATA_A002;
 967
 968 #ifdef CONFIG_PPC
 969         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
 970                 __gfar_detect_errata_85xx(priv);
 971         else /* non-mpc85xx parts, i.e. e300 core based */
 972                 __gfar_detect_errata_83xx(priv);
 973 #endif
 974
 975         if (priv->errata)
 976                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 977                          priv->errata);
 978 }
 979
 980 static void gfar_init_addr_hash_table(struct gfar_private *priv)
 981 {
 982         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 983
 984         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 985                 priv->extended_hash = 1;
 986                 priv->hash_width = 9;
 987
 988                 priv->hash_regs[0] = &regs->igaddr0;
 989                 priv->hash_regs[1] = &regs->igaddr1;
 990                 priv->hash_regs[2] = &regs->igaddr2;
 991                 priv->hash_regs[3] = &regs->igaddr3;
 992                 priv->hash_regs[4] = &regs->igaddr4;
 993                 priv->hash_regs[5] = &regs->igaddr5;
 994                 priv->hash_regs[6] = &regs->igaddr6;
 995                 priv->hash_regs[7] = &regs->igaddr7;
 996                 priv->hash_regs[8] = &regs->gaddr0;
 997                 priv->hash_regs[9] = &regs->gaddr1;
 998                 priv->hash_regs[10] = &regs->gaddr2;
 999                 priv->hash_regs[11] = &regs->gaddr3;
1000                 priv->hash_regs[12] = &regs->gaddr4;
1001                 priv->hash_regs[13] = &regs->gaddr5;
1002                 priv->hash_regs[14] = &regs->gaddr6;
1003                 priv->hash_regs[15] = &regs->gaddr7;
1004
1005         } else {
1006                 priv->extended_hash = 0;
1007                 priv->hash_width = 8;
1008
1009                 priv->hash_regs[0] = &regs->gaddr0;
1010                 priv->hash_regs[1] = &regs->gaddr1;
1011                 priv->hash_regs[2] = &regs->gaddr2;
1012                 priv->hash_regs[3] = &regs->gaddr3;
1013                 priv->hash_regs[4] = &regs->gaddr4;
1014                 priv->hash_regs[5] = &regs->gaddr5;
1015                 priv->hash_regs[6] = &regs->gaddr6;
1016                 priv->hash_regs[7] = &regs->gaddr7;
1017         }
1018 }
1019
1020 static int __gfar_is_rx_idle(struct gfar_private *priv)
1021 {
1022         u32 res;
1023
1024         /* Normaly TSEC should not hang on GRS commands, so we should
1025          * actually wait for IEVENT_GRSC flag.
1026          */
1027         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1028                 return 0;
1029
1030         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1031          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1032          * and the Rx can be safely reset.
1033          */
1034         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1035         res &= 0x7f807f80;
1036         if ((res & 0xffff) == (res >> 16))
1037                 return 1;
1038
1039         return 0;
1040 }
1041
1042 /* Halt the receive and transmit queues */
1043 static void gfar_halt_nodisable(struct gfar_private *priv)
1044 {
1045         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1046         u32 tempval;
1047         unsigned int timeout;
1048         int stopped;
1049
1050         gfar_ints_disable(priv);
1051
1052         if (gfar_is_dma_stopped(priv))
1053                 return;
1054
1055         /* Stop the DMA, and wait for it to stop */
1056         tempval = gfar_read(&regs->dmactrl);
1057         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1058         gfar_write(&regs->dmactrl, tempval);
1059
1060 retry:
1061         timeout = 1000;
1062         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1063                 cpu_relax();
1064                 timeout--;
1065         }
1066
1067         if (!timeout)
1068                 stopped = gfar_is_dma_stopped(priv);
1069
1070         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1071             !__gfar_is_rx_idle(priv))
1072                 goto retry;
1073 }
1074
1075 /* Halt the receive and transmit queues */
1076 static void gfar_halt(struct gfar_private *priv)
1077 {
1078         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1079         u32 tempval;
1080
1081         /* Dissable the Rx/Tx hw queues */
1082         gfar_write(&regs->rqueue, 0);
1083         gfar_write(&regs->tqueue, 0);
1084
1085         mdelay(10);
1086
1087         gfar_halt_nodisable(priv);
1088
1089         /* Disable Rx/Tx DMA */
1090         tempval = gfar_read(&regs->maccfg1);
1091         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1092         gfar_write(&regs->maccfg1, tempval);
1093 }
1094
1095 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1096 {
1097         struct txbd8 *txbdp;
1098         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1099         int i, j;
1100
1101         txbdp = tx_queue->tx_bd_base;
1102
1103         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1104                 if (!tx_queue->tx_skbuff[i])
1105                         continue;
1106
1107                 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1108                                  be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1109                 txbdp->lstatus = 0;
1110                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1111                      j++) {
1112                         txbdp++;
1113                         dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1114                                        be16_to_cpu(txbdp->length),
1115                                        DMA_TO_DEVICE);
1116                 }
1117                 txbdp++;
1118                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1119                 tx_queue->tx_skbuff[i] = NULL;
1120         }
1121         kfree(tx_queue->tx_skbuff);
1122         tx_queue->tx_skbuff = NULL;
1123 }
1124
1125 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1126 {
1127         int i;
1128
1129         struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1130
1131         dev_kfree_skb(rx_queue->skb);
1132
1133         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1134                 struct  gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
1135
1136                 rxbdp->lstatus = 0;
1137                 rxbdp->bufPtr = 0;
1138                 rxbdp++;
1139
1140                 if (!rxb->page)
1141                         continue;
1142
1143                 dma_unmap_page(rx_queue->dev, rxb->dma,
1144                                PAGE_SIZE, DMA_FROM_DEVICE);
1145                 __free_page(rxb->page);
1146
1147                 rxb->page = NULL;
1148         }
1149
1150         kfree(rx_queue->rx_buff);
1151         rx_queue->rx_buff = NULL;
1152 }
1153
1154 /* If there are any tx skbs or rx skbs still around, free them.
1155  * Then free tx_skbuff and rx_skbuff
1156  */
1157 static void free_skb_resources(struct gfar_private *priv)
1158 {
1159         struct gfar_priv_tx_q *tx_queue = NULL;
1160         struct gfar_priv_rx_q *rx_queue = NULL;
1161         int i;
1162
1163         /* Go through all the buffer descriptors and free their data buffers */
1164         for (i = 0; i < priv->num_tx_queues; i++) {
1165                 struct netdev_queue *txq;
1166
1167                 tx_queue = priv->tx_queue[i];
1168                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1169                 if (tx_queue->tx_skbuff)
1170                         free_skb_tx_queue(tx_queue);
1171                 netdev_tx_reset_queue(txq);
1172         }
1173
1174         for (i = 0; i < priv->num_rx_queues; i++) {
1175                 rx_queue = priv->rx_queue[i];
1176                 if (rx_queue->rx_buff)
1177                         free_skb_rx_queue(rx_queue);
1178         }
1179
1180         dma_free_coherent(priv->dev,
1181                           sizeof(struct txbd8) * priv->total_tx_ring_size +
1182                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
1183                           priv->tx_queue[0]->tx_bd_base,
1184                           priv->tx_queue[0]->tx_bd_dma_base);
1185 }
1186
1187 void stop_gfar(struct net_device *dev)
1188 {
1189         struct gfar_private *priv = netdev_priv(dev);
1190
1191         netif_tx_stop_all_queues(dev);
1192
1193         smp_mb__before_atomic();
1194         set_bit(GFAR_DOWN, &priv->state);
1195         smp_mb__after_atomic();
1196
1197         disable_napi(priv);
1198
1199         /* disable ints and gracefully shut down Rx/Tx DMA */
1200         gfar_halt(priv);
1201
1202         phy_stop(dev->phydev);
1203
1204         free_skb_resources(priv);
1205 }
1206
1207 static void gfar_start(struct gfar_private *priv)
1208 {
1209         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1210         u32 tempval;
1211         int i = 0;
1212
1213         /* Enable Rx/Tx hw queues */
1214         gfar_write(&regs->rqueue, priv->rqueue);
1215         gfar_write(&regs->tqueue, priv->tqueue);
1216
1217         /* Initialize DMACTRL to have WWR and WOP */
1218         tempval = gfar_read(&regs->dmactrl);
1219         tempval |= DMACTRL_INIT_SETTINGS;
1220         gfar_write(&regs->dmactrl, tempval);
1221
1222         /* Make sure we aren't stopped */
1223         tempval = gfar_read(&regs->dmactrl);
1224         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1225         gfar_write(&regs->dmactrl, tempval);
1226
1227         for (i = 0; i < priv->num_grps; i++) {
1228                 regs = priv->gfargrp[i].regs;
1229                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1230                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1231                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1232         }
1233
1234         /* Enable Rx/Tx DMA */
1235         tempval = gfar_read(&regs->maccfg1);
1236         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1237         gfar_write(&regs->maccfg1, tempval);
1238
1239         gfar_ints_enable(priv);
1240
1241         netif_trans_update(priv->ndev); /* prevent tx timeout */
1242 }
1243
1244 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
1245 {
1246         struct page *page;
1247         dma_addr_t addr;
1248
1249         page = dev_alloc_page();
1250         if (unlikely(!page))
1251                 return false;
1252
1253         addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
1254         if (unlikely(dma_mapping_error(rxq->dev, addr))) {
1255                 __free_page(page);
1256
1257                 return false;
1258         }
1259
1260         rxb->dma = addr;
1261         rxb->page = page;
1262         rxb->page_offset = 0;
1263
1264         return true;
1265 }
1266
1267 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
1268 {
1269         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
1270         struct gfar_extra_stats *estats = &priv->extra_stats;
1271
1272         netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
1273         atomic64_inc(&estats->rx_alloc_err);
1274 }
1275
1276 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
1277                                 int alloc_cnt)
1278 {
1279         struct rxbd8 *bdp;
1280         struct gfar_rx_buff *rxb;
1281         int i;
1282
1283         i = rx_queue->next_to_use;
1284         bdp = &rx_queue->rx_bd_base[i];
1285         rxb = &rx_queue->rx_buff[i];
1286
1287         while (alloc_cnt--) {
1288                 /* try reuse page */
1289                 if (unlikely(!rxb->page)) {
1290                         if (unlikely(!gfar_new_page(rx_queue, rxb))) {
1291                                 gfar_rx_alloc_err(rx_queue);
1292                                 break;
1293                         }
1294                 }
1295
1296                 /* Setup the new RxBD */
1297                 gfar_init_rxbdp(rx_queue, bdp,
1298                                 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
1299
1300                 /* Update to the next pointer */
1301                 bdp++;
1302                 rxb++;
1303
1304                 if (unlikely(++i == rx_queue->rx_ring_size)) {
1305                         i = 0;
1306                         bdp = rx_queue->rx_bd_base;
1307                         rxb = rx_queue->rx_buff;
1308                 }
1309         }
1310
1311         rx_queue->next_to_use = i;
1312         rx_queue->next_to_alloc = i;
1313 }
1314
1315 static void gfar_init_bds(struct net_device *ndev)
1316 {
1317         struct gfar_private *priv = netdev_priv(ndev);
1318         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1319         struct gfar_priv_tx_q *tx_queue = NULL;
1320         struct gfar_priv_rx_q *rx_queue = NULL;
1321         struct txbd8 *txbdp;
1322         u32 __iomem *rfbptr;
1323         int i, j;
1324
1325         for (i = 0; i < priv->num_tx_queues; i++) {
1326                 tx_queue = priv->tx_queue[i];
1327                 /* Initialize some variables in our dev structure */
1328                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
1329                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
1330                 tx_queue->cur_tx = tx_queue->tx_bd_base;
1331                 tx_queue->skb_curtx = 0;
1332                 tx_queue->skb_dirtytx = 0;
1333
1334                 /* Initialize Transmit Descriptor Ring */
1335                 txbdp = tx_queue->tx_bd_base;
1336                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
1337                         txbdp->lstatus = 0;
1338                         txbdp->bufPtr = 0;
1339                         txbdp++;
1340                 }
1341
1342                 /* Set the last descriptor in the ring to indicate wrap */
1343                 txbdp--;
1344                 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
1345                                             TXBD_WRAP);
1346         }
1347
1348         rfbptr = &regs->rfbptr0;
1349         for (i = 0; i < priv->num_rx_queues; i++) {
1350                 rx_queue = priv->rx_queue[i];
1351
1352                 rx_queue->next_to_clean = 0;
1353                 rx_queue->next_to_use = 0;
1354                 rx_queue->next_to_alloc = 0;
1355
1356                 /* make sure next_to_clean != next_to_use after this
1357                  * by leaving at least 1 unused descriptor
1358                  */
1359                 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
1360
1361                 rx_queue->rfbptr = rfbptr;
1362                 rfbptr += 2;
1363         }
1364 }
1365
1366 static int gfar_alloc_skb_resources(struct net_device *ndev)
1367 {
1368         void *vaddr;
1369         dma_addr_t addr;
1370         int i, j;
1371         struct gfar_private *priv = netdev_priv(ndev);
1372         struct device *dev = priv->dev;
1373         struct gfar_priv_tx_q *tx_queue = NULL;
1374         struct gfar_priv_rx_q *rx_queue = NULL;
1375
1376         priv->total_tx_ring_size = 0;
1377         for (i = 0; i < priv->num_tx_queues; i++)
1378                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
1379
1380         priv->total_rx_ring_size = 0;
1381         for (i = 0; i < priv->num_rx_queues; i++)
1382                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
1383
1384         /* Allocate memory for the buffer descriptors */
1385         vaddr = dma_alloc_coherent(dev,
1386                                    (priv->total_tx_ring_size *
1387                                     sizeof(struct txbd8)) +
1388                                    (priv->total_rx_ring_size *
1389                                     sizeof(struct rxbd8)),
1390                                    &addr, GFP_KERNEL);
1391         if (!vaddr)
1392                 return -ENOMEM;
1393
1394         for (i = 0; i < priv->num_tx_queues; i++) {
1395                 tx_queue = priv->tx_queue[i];
1396                 tx_queue->tx_bd_base = vaddr;
1397                 tx_queue->tx_bd_dma_base = addr;
1398                 tx_queue->dev = ndev;
1399                 /* enet DMA only understands physical addresses */
1400                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1401                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
1402         }
1403
1404         /* Start the rx descriptor ring where the tx ring leaves off */
1405         for (i = 0; i < priv->num_rx_queues; i++) {
1406                 rx_queue = priv->rx_queue[i];
1407                 rx_queue->rx_bd_base = vaddr;
1408                 rx_queue->rx_bd_dma_base = addr;
1409                 rx_queue->ndev = ndev;
1410                 rx_queue->dev = dev;
1411                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1412                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
1413         }
1414
1415         /* Setup the skbuff rings */
1416         for (i = 0; i < priv->num_tx_queues; i++) {
1417                 tx_queue = priv->tx_queue[i];
1418                 tx_queue->tx_skbuff =
1419                         kmalloc_array(tx_queue->tx_ring_size,
1420                                       sizeof(*tx_queue->tx_skbuff),
1421                                       GFP_KERNEL);
1422                 if (!tx_queue->tx_skbuff)
1423                         goto cleanup;
1424
1425                 for (j = 0; j < tx_queue->tx_ring_size; j++)
1426                         tx_queue->tx_skbuff[j] = NULL;
1427         }
1428
1429         for (i = 0; i < priv->num_rx_queues; i++) {
1430                 rx_queue = priv->rx_queue[i];
1431                 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
1432                                             sizeof(*rx_queue->rx_buff),
1433                                             GFP_KERNEL);
1434                 if (!rx_queue->rx_buff)
1435                         goto cleanup;
1436         }
1437
1438         gfar_init_bds(ndev);
1439
1440         return 0;
1441
1442 cleanup:
1443         free_skb_resources(priv);
1444         return -ENOMEM;
1445 }
1446
1447 /* Bring the controller up and running */
1448 int startup_gfar(struct net_device *ndev)
1449 {
1450         struct gfar_private *priv = netdev_priv(ndev);
1451         int err;
1452
1453         gfar_mac_reset(priv);
1454
1455         err = gfar_alloc_skb_resources(ndev);
1456         if (err)
1457                 return err;
1458
1459         gfar_init_tx_rx_base(priv);
1460
1461         smp_mb__before_atomic();
1462         clear_bit(GFAR_DOWN, &priv->state);
1463         smp_mb__after_atomic();
1464
1465         /* Start Rx/Tx DMA and enable the interrupts */
1466         gfar_start(priv);
1467
1468         /* force link state update after mac reset */
1469         priv->oldlink = 0;
1470         priv->oldspeed = 0;
1471         priv->oldduplex = -1;
1472
1473         phy_start(ndev->phydev);
1474
1475         enable_napi(priv);
1476
1477         netif_tx_wake_all_queues(ndev);
1478
1479         return 0;
1480 }
1481
1482 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
1483 {
1484         struct net_device *ndev = priv->ndev;
1485         struct phy_device *phydev = ndev->phydev;
1486         u32 val = 0;
1487
1488         if (!phydev->duplex)
1489                 return val;
1490
1491         if (!priv->pause_aneg_en) {
1492                 if (priv->tx_pause_en)
1493                         val |= MACCFG1_TX_FLOW;
1494                 if (priv->rx_pause_en)
1495                         val |= MACCFG1_RX_FLOW;
1496         } else {
1497                 u16 lcl_adv, rmt_adv;
1498                 u8 flowctrl;
1499                 /* get link partner capabilities */
1500                 rmt_adv = 0;
1501                 if (phydev->pause)
1502                         rmt_adv = LPA_PAUSE_CAP;
1503                 if (phydev->asym_pause)
1504                         rmt_adv |= LPA_PAUSE_ASYM;
1505
1506                 lcl_adv = linkmode_adv_to_lcl_adv_t(phydev->advertising);
1507                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
1508                 if (flowctrl & FLOW_CTRL_TX)
1509                         val |= MACCFG1_TX_FLOW;
1510                 if (flowctrl & FLOW_CTRL_RX)
1511                         val |= MACCFG1_RX_FLOW;
1512         }
1513
1514         return val;
1515 }
1516
1517 static noinline void gfar_update_link_state(struct gfar_private *priv)
1518 {
1519         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1520         struct net_device *ndev = priv->ndev;
1521         struct phy_device *phydev = ndev->phydev;
1522         struct gfar_priv_rx_q *rx_queue = NULL;
1523         int i;
1524
1525         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
1526                 return;
1527
1528         if (phydev->link) {
1529                 u32 tempval1 = gfar_read(&regs->maccfg1);
1530                 u32 tempval = gfar_read(&regs->maccfg2);
1531                 u32 ecntrl = gfar_read(&regs->ecntrl);
1532                 u32 tx_flow_oldval = (tempval1 & MACCFG1_TX_FLOW);
1533
1534                 if (phydev->duplex != priv->oldduplex) {
1535                         if (!(phydev->duplex))
1536                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1537                         else
1538                                 tempval |= MACCFG2_FULL_DUPLEX;
1539
1540                         priv->oldduplex = phydev->duplex;
1541                 }
1542
1543                 if (phydev->speed != priv->oldspeed) {
1544                         switch (phydev->speed) {
1545                         case 1000:
1546                                 tempval =
1547                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1548
1549                                 ecntrl &= ~(ECNTRL_R100);
1550                                 break;
1551                         case 100:
1552                         case 10:
1553                                 tempval =
1554                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1555
1556                                 /* Reduced mode distinguishes
1557                                  * between 10 and 100
1558                                  */
1559                                 if (phydev->speed == SPEED_100)
1560                                         ecntrl |= ECNTRL_R100;
1561                                 else
1562                                         ecntrl &= ~(ECNTRL_R100);
1563                                 break;
1564                         default:
1565                                 netif_warn(priv, link, priv->ndev,
1566                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
1567                                            phydev->speed);
1568                                 break;
1569                         }
1570
1571                         priv->oldspeed = phydev->speed;
1572                 }
1573
1574                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1575                 tempval1 |= gfar_get_flowctrl_cfg(priv);
1576
1577                 /* Turn last free buffer recording on */
1578                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
1579                         for (i = 0; i < priv->num_rx_queues; i++) {
1580                                 u32 bdp_dma;
1581
1582                                 rx_queue = priv->rx_queue[i];
1583                                 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
1584                                 gfar_write(rx_queue->rfbptr, bdp_dma);
1585                         }
1586
1587                         priv->tx_actual_en = 1;
1588                 }
1589
1590                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
1591                         priv->tx_actual_en = 0;
1592
1593                 gfar_write(&regs->maccfg1, tempval1);
1594                 gfar_write(&regs->maccfg2, tempval);
1595                 gfar_write(&regs->ecntrl, ecntrl);
1596
1597                 if (!priv->oldlink)
1598                         priv->oldlink = 1;
1599
1600         } else if (priv->oldlink) {
1601                 priv->oldlink = 0;
1602                 priv->oldspeed = 0;
1603                 priv->oldduplex = -1;
1604         }
1605
1606         if (netif_msg_link(priv))
1607                 phy_print_status(phydev);
1608 }
1609
1610 /* Called every time the controller might need to be made
1611  * aware of new link state.  The PHY code conveys this
1612  * information through variables in the phydev structure, and this
1613  * function converts those variables into the appropriate
1614  * register values, and can bring down the device if needed.
1615  */
1616 static void adjust_link(struct net_device *dev)
1617 {
1618         struct gfar_private *priv = netdev_priv(dev);
1619         struct phy_device *phydev = dev->phydev;
1620
1621         if (unlikely(phydev->link != priv->oldlink ||
1622                      (phydev->link && (phydev->duplex != priv->oldduplex ||
1623                                        phydev->speed != priv->oldspeed))))
1624                 gfar_update_link_state(priv);
1625 }
1626
1627 /* Initialize TBI PHY interface for communicating with the
1628  * SERDES lynx PHY on the chip.  We communicate with this PHY
1629  * through the MDIO bus on each controller, treating it as a
1630  * "normal" PHY at the address found in the TBIPA register.  We assume
1631  * that the TBIPA register is valid.  Either the MDIO bus code will set
1632  * it to a value that doesn't conflict with other PHYs on the bus, or the
1633  * value doesn't matter, as there are no other PHYs on the bus.
1634  */
1635 static void gfar_configure_serdes(struct net_device *dev)
1636 {
1637         struct gfar_private *priv = netdev_priv(dev);
1638         struct phy_device *tbiphy;
1639
1640         if (!priv->tbi_node) {
1641                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1642                                     "device tree specify a tbi-handle\n");
1643                 return;
1644         }
1645
1646         tbiphy = of_phy_find_device(priv->tbi_node);
1647         if (!tbiphy) {
1648                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1649                 return;
1650         }
1651
1652         /* If the link is already up, we must already be ok, and don't need to
1653          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1654          * everything for us?  Resetting it takes the link down and requires
1655          * several seconds for it to come back.
1656          */
1657         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1658                 put_device(&tbiphy->mdio.dev);
1659                 return;
1660         }
1661
1662         /* Single clk mode, mii mode off(for serdes communication) */
1663         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1664
1665         phy_write(tbiphy, MII_ADVERTISE,
1666                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1667                   ADVERTISE_1000XPSE_ASYM);
1668
1669         phy_write(tbiphy, MII_BMCR,
1670                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1671                   BMCR_SPEED1000);
1672
1673         put_device(&tbiphy->mdio.dev);
1674 }
1675
1676 /* Initializes driver's PHY state, and attaches to the PHY.
1677  * Returns 0 on success.
1678  */
1679 static int init_phy(struct net_device *dev)
1680 {
1681         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1682         struct gfar_private *priv = netdev_priv(dev);
1683         phy_interface_t interface = priv->interface;
1684         struct phy_device *phydev;
1685         struct ethtool_eee edata;
1686
1687         linkmode_set_bit_array(phy_10_100_features_array,
1688                                ARRAY_SIZE(phy_10_100_features_array),
1689                                mask);
1690         linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask);
1691         linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask);
1692         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1693                 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, mask);
1694
1695         priv->oldlink = 0;
1696         priv->oldspeed = 0;
1697         priv->oldduplex = -1;
1698
1699         phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1700                                 interface);
1701         if (!phydev) {
1702                 dev_err(&dev->dev, "could not attach to PHY\n");
1703                 return -ENODEV;
1704         }
1705
1706         if (interface == PHY_INTERFACE_MODE_SGMII)
1707                 gfar_configure_serdes(dev);
1708
1709         /* Remove any features not supported by the controller */
1710         linkmode_and(phydev->supported, phydev->supported, mask);
1711         linkmode_copy(phydev->advertising, phydev->supported);
1712
1713         /* Add support for flow control */
1714         phy_support_asym_pause(phydev);
1715
1716         /* disable EEE autoneg, EEE not supported by eTSEC */
1717         memset(&edata, 0, sizeof(struct ethtool_eee));
1718         phy_ethtool_set_eee(phydev, &edata);
1719
1720         return 0;
1721 }
1722
1723 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1724 {
1725         struct txfcb *fcb = skb_push(skb, GMAC_FCB_LEN);
1726
1727         memset(fcb, 0, GMAC_FCB_LEN);
1728
1729         return fcb;
1730 }
1731
1732 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1733                                     int fcb_length)
1734 {
1735         /* If we're here, it's a IP packet with a TCP or UDP
1736          * payload.  We set it to checksum, using a pseudo-header
1737          * we provide
1738          */
1739         u8 flags = TXFCB_DEFAULT;
1740
1741         /* Tell the controller what the protocol is
1742          * And provide the already calculated phcs
1743          */
1744         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1745                 flags |= TXFCB_UDP;
1746                 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
1747         } else
1748                 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
1749
1750         /* l3os is the distance between the start of the
1751          * frame (skb->data) and the start of the IP hdr.
1752          * l4os is the distance between the start of the
1753          * l3 hdr and the l4 hdr
1754          */
1755         fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
1756         fcb->l4os = skb_network_header_len(skb);
1757
1758         fcb->flags = flags;
1759 }
1760
1761 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1762 {
1763         fcb->flags |= TXFCB_VLN;
1764         fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
1765 }
1766
1767 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1768                                       struct txbd8 *base, int ring_size)
1769 {
1770         struct txbd8 *new_bd = bdp + stride;
1771
1772         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1773 }
1774
1775 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1776                                       int ring_size)
1777 {
1778         return skip_txbd(bdp, 1, base, ring_size);
1779 }
1780
1781 /* eTSEC12: csum generation not supported for some fcb offsets */
1782 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
1783                                        unsigned long fcb_addr)
1784 {
1785         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
1786                (fcb_addr % 0x20) > 0x18);
1787 }
1788
1789 /* eTSEC76: csum generation for frames larger than 2500 may
1790  * cause excess delays before start of transmission
1791  */
1792 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
1793                                        unsigned int len)
1794 {
1795         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
1796                (len > 2500));
1797 }
1798
1799 /* This is called by the kernel when a frame is ready for transmission.
1800  * It is pointed to by the dev->hard_start_xmit function pointer
1801  */
1802 static netdev_tx_t gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1803 {
1804         struct gfar_private *priv = netdev_priv(dev);
1805         struct gfar_priv_tx_q *tx_queue = NULL;
1806         struct netdev_queue *txq;
1807         struct gfar __iomem *regs = NULL;
1808         struct txfcb *fcb = NULL;
1809         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
1810         u32 lstatus;
1811         skb_frag_t *frag;
1812         int i, rq = 0;
1813         int do_tstamp, do_csum, do_vlan;
1814         u32 bufaddr;
1815         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
1816
1817         rq = skb->queue_mapping;
1818         tx_queue = priv->tx_queue[rq];
1819         txq = netdev_get_tx_queue(dev, rq);
1820         base = tx_queue->tx_bd_base;
1821         regs = tx_queue->grp->regs;
1822
1823         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
1824         do_vlan = skb_vlan_tag_present(skb);
1825         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1826                     priv->hwts_tx_en;
1827
1828         if (do_csum || do_vlan)
1829                 fcb_len = GMAC_FCB_LEN;
1830
1831         /* check if time stamp should be generated */
1832         if (unlikely(do_tstamp))
1833                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
1834
1835         /* make space for additional header when fcb is needed */
1836         if (fcb_len) {
1837                 if (unlikely(skb_cow_head(skb, fcb_len))) {
1838                         dev->stats.tx_errors++;
1839                         dev_kfree_skb_any(skb);
1840                         return NETDEV_TX_OK;
1841                 }
1842         }
1843
1844         /* total number of fragments in the SKB */
1845         nr_frags = skb_shinfo(skb)->nr_frags;
1846
1847         /* calculate the required number of TxBDs for this skb */
1848         if (unlikely(do_tstamp))
1849                 nr_txbds = nr_frags + 2;
1850         else
1851                 nr_txbds = nr_frags + 1;
1852
1853         /* check if there is space to queue this packet */
1854         if (nr_txbds > tx_queue->num_txbdfree) {
1855                 /* no space, stop the queue */
1856                 netif_tx_stop_queue(txq);
1857                 dev->stats.tx_fifo_errors++;
1858                 return NETDEV_TX_BUSY;
1859         }
1860
1861         /* Update transmit stats */
1862         bytes_sent = skb->len;
1863         tx_queue->stats.tx_bytes += bytes_sent;
1864         /* keep Tx bytes on wire for BQL accounting */
1865         GFAR_CB(skb)->bytes_sent = bytes_sent;
1866         tx_queue->stats.tx_packets++;
1867
1868         txbdp = txbdp_start = tx_queue->cur_tx;
1869         lstatus = be32_to_cpu(txbdp->lstatus);
1870
1871         /* Add TxPAL between FCB and frame if required */
1872         if (unlikely(do_tstamp)) {
1873                 skb_push(skb, GMAC_TXPAL_LEN);
1874                 memset(skb->data, 0, GMAC_TXPAL_LEN);
1875         }
1876
1877         /* Add TxFCB if required */
1878         if (fcb_len) {
1879                 fcb = gfar_add_fcb(skb);
1880                 lstatus |= BD_LFLAG(TXBD_TOE);
1881         }
1882
1883         /* Set up checksumming */
1884         if (do_csum) {
1885                 gfar_tx_checksum(skb, fcb, fcb_len);
1886
1887                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
1888                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
1889                         __skb_pull(skb, GMAC_FCB_LEN);
1890                         skb_checksum_help(skb);
1891                         if (do_vlan || do_tstamp) {
1892                                 /* put back a new fcb for vlan/tstamp TOE */
1893                                 fcb = gfar_add_fcb(skb);
1894                         } else {
1895                                 /* Tx TOE not used */
1896                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
1897                                 fcb = NULL;
1898                         }
1899                 }
1900         }
1901
1902         if (do_vlan)
1903                 gfar_tx_vlan(skb, fcb);
1904
1905         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
1906                                  DMA_TO_DEVICE);
1907         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1908                 goto dma_map_err;
1909
1910         txbdp_start->bufPtr = cpu_to_be32(bufaddr);
1911
1912         /* Time stamp insertion requires one additional TxBD */
1913         if (unlikely(do_tstamp))
1914                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
1915                                                  tx_queue->tx_ring_size);
1916
1917         if (likely(!nr_frags)) {
1918                 if (likely(!do_tstamp))
1919                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1920         } else {
1921                 u32 lstatus_start = lstatus;
1922
1923                 /* Place the fragment addresses and lengths into the TxBDs */
1924                 frag = &skb_shinfo(skb)->frags[0];
1925                 for (i = 0; i < nr_frags; i++, frag++) {
1926                         unsigned int size;
1927
1928                         /* Point at the next BD, wrapping as needed */
1929                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1930
1931                         size = skb_frag_size(frag);
1932
1933                         lstatus = be32_to_cpu(txbdp->lstatus) | size |
1934                                   BD_LFLAG(TXBD_READY);
1935
1936                         /* Handle the last BD specially */
1937                         if (i == nr_frags - 1)
1938                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1939
1940                         bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
1941                                                    size, DMA_TO_DEVICE);
1942                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
1943                                 goto dma_map_err;
1944
1945                         /* set the TxBD length and buffer pointer */
1946                         txbdp->bufPtr = cpu_to_be32(bufaddr);
1947                         txbdp->lstatus = cpu_to_be32(lstatus);
1948                 }
1949
1950                 lstatus = lstatus_start;
1951         }
1952
1953         /* If time stamping is requested one additional TxBD must be set up. The
1954          * first TxBD points to the FCB and must have a data length of
1955          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
1956          * the full frame length.
1957          */
1958         if (unlikely(do_tstamp)) {
1959                 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
1960
1961                 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
1962                 bufaddr += fcb_len;
1963
1964                 lstatus_ts |= BD_LFLAG(TXBD_READY) |
1965                               (skb_headlen(skb) - fcb_len);
1966                 if (!nr_frags)
1967                         lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1968
1969                 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
1970                 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
1971                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
1972
1973                 /* Setup tx hardware time stamping */
1974                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1975                 fcb->ptp = 1;
1976         } else {
1977                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1978         }
1979
1980         netdev_tx_sent_queue(txq, bytes_sent);
1981
1982         gfar_wmb();
1983
1984         txbdp_start->lstatus = cpu_to_be32(lstatus);
1985
1986         gfar_wmb(); /* force lstatus write before tx_skbuff */
1987
1988         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
1989
1990         /* Update the current skb pointer to the next entry we will use
1991          * (wrapping if necessary)
1992          */
1993         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
1994                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
1995
1996         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
1997
1998         /* We can work in parallel with gfar_clean_tx_ring(), except
1999          * when modifying num_txbdfree. Note that we didn't grab the lock
2000          * when we were reading the num_txbdfree and checking for available
2001          * space, that's because outside of this function it can only grow.
2002          */
2003         spin_lock_bh(&tx_queue->txlock);
2004         /* reduce TxBD free count */
2005         tx_queue->num_txbdfree -= (nr_txbds);
2006         spin_unlock_bh(&tx_queue->txlock);
2007
2008         /* If the next BD still needs to be cleaned up, then the bds
2009          * are full.  We need to tell the kernel to stop sending us stuff.
2010          */
2011         if (!tx_queue->num_txbdfree) {
2012                 netif_tx_stop_queue(txq);
2013
2014                 dev->stats.tx_fifo_errors++;
2015         }
2016
2017         /* Tell the DMA to go go go */
2018         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2019
2020         return NETDEV_TX_OK;
2021
2022 dma_map_err:
2023         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2024         if (do_tstamp)
2025                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2026         for (i = 0; i < nr_frags; i++) {
2027                 lstatus = be32_to_cpu(txbdp->lstatus);
2028                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2029                         break;
2030
2031                 lstatus &= ~BD_LFLAG(TXBD_READY);
2032                 txbdp->lstatus = cpu_to_be32(lstatus);
2033                 bufaddr = be32_to_cpu(txbdp->bufPtr);
2034                 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2035                                DMA_TO_DEVICE);
2036                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2037         }
2038         gfar_wmb();
2039         dev_kfree_skb_any(skb);
2040         return NETDEV_TX_OK;
2041 }
2042
2043 /* Changes the mac address if the controller is not running. */
2044 static int gfar_set_mac_address(struct net_device *dev)
2045 {
2046         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2047
2048         return 0;
2049 }
2050
2051 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2052 {
2053         struct gfar_private *priv = netdev_priv(dev);
2054
2055         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2056                 cpu_relax();
2057
2058         if (dev->flags & IFF_UP)
2059                 stop_gfar(dev);
2060
2061         dev->mtu = new_mtu;
2062
2063         if (dev->flags & IFF_UP)
2064                 startup_gfar(dev);
2065
2066         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2067
2068         return 0;
2069 }
2070
2071 static void reset_gfar(struct net_device *ndev)
2072 {
2073         struct gfar_private *priv = netdev_priv(ndev);
2074
2075         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2076                 cpu_relax();
2077
2078         stop_gfar(ndev);
2079         startup_gfar(ndev);
2080
2081         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2082 }
2083
2084 /* gfar_reset_task gets scheduled when a packet has not been
2085  * transmitted after a set amount of time.
2086  * For now, assume that clearing out all the structures, and
2087  * starting over will fix the problem.
2088  */
2089 static void gfar_reset_task(struct work_struct *work)
2090 {
2091         struct gfar_private *priv = container_of(work, struct gfar_private,
2092                                                  reset_task);
2093         reset_gfar(priv->ndev);
2094 }
2095
2096 static void gfar_timeout(struct net_device *dev, unsigned int txqueue)
2097 {
2098         struct gfar_private *priv = netdev_priv(dev);
2099
2100         dev->stats.tx_errors++;
2101         schedule_work(&priv->reset_task);
2102 }
2103
2104 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
2105 {
2106         struct hwtstamp_config config;
2107         struct gfar_private *priv = netdev_priv(netdev);
2108
2109         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2110                 return -EFAULT;
2111
2112         /* reserved for future extensions */
2113         if (config.flags)
2114                 return -EINVAL;
2115
2116         switch (config.tx_type) {
2117         case HWTSTAMP_TX_OFF:
2118                 priv->hwts_tx_en = 0;
2119                 break;
2120         case HWTSTAMP_TX_ON:
2121                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2122                         return -ERANGE;
2123                 priv->hwts_tx_en = 1;
2124                 break;
2125         default:
2126                 return -ERANGE;
2127         }
2128
2129         switch (config.rx_filter) {
2130         case HWTSTAMP_FILTER_NONE:
2131                 if (priv->hwts_rx_en) {
2132                         priv->hwts_rx_en = 0;
2133                         reset_gfar(netdev);
2134                 }
2135                 break;
2136         default:
2137                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
2138                         return -ERANGE;
2139                 if (!priv->hwts_rx_en) {
2140                         priv->hwts_rx_en = 1;
2141                         reset_gfar(netdev);
2142                 }
2143                 config.rx_filter = HWTSTAMP_FILTER_ALL;
2144                 break;
2145         }
2146
2147         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2148                 -EFAULT : 0;
2149 }
2150
2151 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
2152 {
2153         struct hwtstamp_config config;
2154         struct gfar_private *priv = netdev_priv(netdev);
2155
2156         config.flags = 0;
2157         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
2158         config.rx_filter = (priv->hwts_rx_en ?
2159                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
2160
2161         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2162                 -EFAULT : 0;
2163 }
2164
2165 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2166 {
2167         struct phy_device *phydev = dev->phydev;
2168
2169         if (!netif_running(dev))
2170                 return -EINVAL;
2171
2172         if (cmd == SIOCSHWTSTAMP)
2173                 return gfar_hwtstamp_set(dev, rq);
2174         if (cmd == SIOCGHWTSTAMP)
2175                 return gfar_hwtstamp_get(dev, rq);
2176
2177         if (!phydev)
2178                 return -ENODEV;
2179
2180         return phy_mii_ioctl(phydev, rq, cmd);
2181 }
2182
2183 /* Interrupt Handler for Transmit complete */
2184 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2185 {
2186         struct net_device *dev = tx_queue->dev;
2187         struct netdev_queue *txq;
2188         struct gfar_private *priv = netdev_priv(dev);
2189         struct txbd8 *bdp, *next = NULL;
2190         struct txbd8 *lbdp = NULL;
2191         struct txbd8 *base = tx_queue->tx_bd_base;
2192         struct sk_buff *skb;
2193         int skb_dirtytx;
2194         int tx_ring_size = tx_queue->tx_ring_size;
2195         int frags = 0, nr_txbds = 0;
2196         int i;
2197         int howmany = 0;
2198         int tqi = tx_queue->qindex;
2199         unsigned int bytes_sent = 0;
2200         u32 lstatus;
2201         size_t buflen;
2202
2203         txq = netdev_get_tx_queue(dev, tqi);
2204         bdp = tx_queue->dirty_tx;
2205         skb_dirtytx = tx_queue->skb_dirtytx;
2206
2207         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2208                 bool do_tstamp;
2209
2210                 do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2211                             priv->hwts_tx_en;
2212
2213                 frags = skb_shinfo(skb)->nr_frags;
2214
2215                 /* When time stamping, one additional TxBD must be freed.
2216                  * Also, we need to dma_unmap_single() the TxPAL.
2217                  */
2218                 if (unlikely(do_tstamp))
2219                         nr_txbds = frags + 2;
2220                 else
2221                         nr_txbds = frags + 1;
2222
2223                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2224
2225                 lstatus = be32_to_cpu(lbdp->lstatus);
2226
2227                 /* Only clean completed frames */
2228                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2229                     (lstatus & BD_LENGTH_MASK))
2230                         break;
2231
2232                 if (unlikely(do_tstamp)) {
2233                         next = next_txbd(bdp, base, tx_ring_size);
2234                         buflen = be16_to_cpu(next->length) +
2235                                  GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2236                 } else
2237                         buflen = be16_to_cpu(bdp->length);
2238
2239                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2240                                  buflen, DMA_TO_DEVICE);
2241
2242                 if (unlikely(do_tstamp)) {
2243                         struct skb_shared_hwtstamps shhwtstamps;
2244                         u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2245                                           ~0x7UL);
2246
2247                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2248                         shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2249                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2250                         skb_tstamp_tx(skb, &shhwtstamps);
2251                         gfar_clear_txbd_status(bdp);
2252                         bdp = next;
2253                 }
2254
2255                 gfar_clear_txbd_status(bdp);
2256                 bdp = next_txbd(bdp, base, tx_ring_size);
2257
2258                 for (i = 0; i < frags; i++) {
2259                         dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2260                                        be16_to_cpu(bdp->length),
2261                                        DMA_TO_DEVICE);
2262                         gfar_clear_txbd_status(bdp);
2263                         bdp = next_txbd(bdp, base, tx_ring_size);
2264                 }
2265
2266                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2267
2268                 dev_kfree_skb_any(skb);
2269
2270                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2271
2272                 skb_dirtytx = (skb_dirtytx + 1) &
2273                               TX_RING_MOD_MASK(tx_ring_size);
2274
2275                 howmany++;
2276                 spin_lock(&tx_queue->txlock);
2277                 tx_queue->num_txbdfree += nr_txbds;
2278                 spin_unlock(&tx_queue->txlock);
2279         }
2280
2281         /* If we freed a buffer, we can restart transmission, if necessary */
2282         if (tx_queue->num_txbdfree &&
2283             netif_tx_queue_stopped(txq) &&
2284             !(test_bit(GFAR_DOWN, &priv->state)))
2285                 netif_wake_subqueue(priv->ndev, tqi);
2286
2287         /* Update dirty indicators */
2288         tx_queue->skb_dirtytx = skb_dirtytx;
2289         tx_queue->dirty_tx = bdp;
2290
2291         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2292 }
2293
2294 static void count_errors(u32 lstatus, struct net_device *ndev)
2295 {
2296         struct gfar_private *priv = netdev_priv(ndev);
2297         struct net_device_stats *stats = &ndev->stats;
2298         struct gfar_extra_stats *estats = &priv->extra_stats;
2299
2300         /* If the packet was truncated, none of the other errors matter */
2301         if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2302                 stats->rx_length_errors++;
2303
2304                 atomic64_inc(&estats->rx_trunc);
2305
2306                 return;
2307         }
2308         /* Count the errors, if there were any */
2309         if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2310                 stats->rx_length_errors++;
2311
2312                 if (lstatus & BD_LFLAG(RXBD_LARGE))
2313                         atomic64_inc(&estats->rx_large);
2314                 else
2315                         atomic64_inc(&estats->rx_short);
2316         }
2317         if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2318                 stats->rx_frame_errors++;
2319                 atomic64_inc(&estats->rx_nonoctet);
2320         }
2321         if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2322                 atomic64_inc(&estats->rx_crcerr);
2323                 stats->rx_crc_errors++;
2324         }
2325         if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2326                 atomic64_inc(&estats->rx_overrun);
2327                 stats->rx_over_errors++;
2328         }
2329 }
2330
2331 static irqreturn_t gfar_receive(int irq, void *grp_id)
2332 {
2333         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2334         unsigned long flags;
2335         u32 imask, ievent;
2336
2337         ievent = gfar_read(&grp->regs->ievent);
2338
2339         if (unlikely(ievent & IEVENT_FGPI)) {
2340                 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2341                 return IRQ_HANDLED;
2342         }
2343
2344         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2345                 spin_lock_irqsave(&grp->grplock, flags);
2346                 imask = gfar_read(&grp->regs->imask);
2347                 imask &= IMASK_RX_DISABLED;
2348                 gfar_write(&grp->regs->imask, imask);
2349                 spin_unlock_irqrestore(&grp->grplock, flags);
2350                 __napi_schedule(&grp->napi_rx);
2351         } else {
2352                 /* Clear IEVENT, so interrupts aren't called again
2353                  * because of the packets that have already arrived.
2354                  */
2355                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2356         }
2357
2358         return IRQ_HANDLED;
2359 }
2360
2361 /* Interrupt Handler for Transmit complete */
2362 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2363 {
2364         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2365         unsigned long flags;
2366         u32 imask;
2367
2368         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2369                 spin_lock_irqsave(&grp->grplock, flags);
2370                 imask = gfar_read(&grp->regs->imask);
2371                 imask &= IMASK_TX_DISABLED;
2372                 gfar_write(&grp->regs->imask, imask);
2373                 spin_unlock_irqrestore(&grp->grplock, flags);
2374                 __napi_schedule(&grp->napi_tx);
2375         } else {
2376                 /* Clear IEVENT, so interrupts aren't called again
2377                  * because of the packets that have already arrived.
2378                  */
2379                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2380         }
2381
2382         return IRQ_HANDLED;
2383 }
2384
2385 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2386                              struct sk_buff *skb, bool first)
2387 {
2388         int size = lstatus & BD_LENGTH_MASK;
2389         struct page *page = rxb->page;
2390
2391         if (likely(first)) {
2392                 skb_put(skb, size);
2393         } else {
2394                 /* the last fragments' length contains the full frame length */
2395                 if (lstatus & BD_LFLAG(RXBD_LAST))
2396                         size -= skb->len;
2397
2398                 WARN(size < 0, "gianfar: rx fragment size underflow");
2399                 if (size < 0)
2400                         return false;
2401
2402                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2403                                 rxb->page_offset + RXBUF_ALIGNMENT,
2404                                 size, GFAR_RXB_TRUESIZE);
2405         }
2406
2407         /* try reuse page */
2408         if (unlikely(page_count(page) != 1 || page_is_pfmemalloc(page)))
2409                 return false;
2410
2411         /* change offset to the other half */
2412         rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2413
2414         page_ref_inc(page);
2415
2416         return true;
2417 }
2418
2419 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2420                                struct gfar_rx_buff *old_rxb)
2421 {
2422         struct gfar_rx_buff *new_rxb;
2423         u16 nta = rxq->next_to_alloc;
2424
2425         new_rxb = &rxq->rx_buff[nta];
2426
2427         /* find next buf that can reuse a page */
2428         nta++;
2429         rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2430
2431         /* copy page reference */
2432         *new_rxb = *old_rxb;
2433
2434         /* sync for use by the device */
2435         dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2436                                          old_rxb->page_offset,
2437                                          GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2438 }
2439
2440 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2441                                             u32 lstatus, struct sk_buff *skb)
2442 {
2443         struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2444         struct page *page = rxb->page;
2445         bool first = false;
2446
2447         if (likely(!skb)) {
2448                 void *buff_addr = page_address(page) + rxb->page_offset;
2449
2450                 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2451                 if (unlikely(!skb)) {
2452                         gfar_rx_alloc_err(rx_queue);
2453                         return NULL;
2454                 }
2455                 skb_reserve(skb, RXBUF_ALIGNMENT);
2456                 first = true;
2457         }
2458
2459         dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
2460                                       GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2461
2462         if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
2463                 /* reuse the free half of the page */
2464                 gfar_reuse_rx_page(rx_queue, rxb);
2465         } else {
2466                 /* page cannot be reused, unmap it */
2467                 dma_unmap_page(rx_queue->dev, rxb->dma,
2468                                PAGE_SIZE, DMA_FROM_DEVICE);
2469         }
2470
2471         /* clear rxb content */
2472         rxb->page = NULL;
2473
2474         return skb;
2475 }
2476
2477 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2478 {
2479         /* If valid headers were found, and valid sums
2480          * were verified, then we tell the kernel that no
2481          * checksumming is necessary.  Otherwise, it is [FIXME]
2482          */
2483         if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
2484             (RXFCB_CIP | RXFCB_CTU))
2485                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2486         else
2487                 skb_checksum_none_assert(skb);
2488 }
2489
2490 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
2491 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
2492 {
2493         struct gfar_private *priv = netdev_priv(ndev);
2494         struct rxfcb *fcb = NULL;
2495
2496         /* fcb is at the beginning if exists */
2497         fcb = (struct rxfcb *)skb->data;
2498
2499         /* Remove the FCB from the skb
2500          * Remove the padded bytes, if there are any
2501          */
2502         if (priv->uses_rxfcb)
2503                 skb_pull(skb, GMAC_FCB_LEN);
2504
2505         /* Get receive timestamp from the skb */
2506         if (priv->hwts_rx_en) {
2507                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2508                 u64 *ns = (u64 *) skb->data;
2509
2510                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2511                 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2512         }
2513
2514         if (priv->padding)
2515                 skb_pull(skb, priv->padding);
2516
2517         /* Trim off the FCS */
2518         pskb_trim(skb, skb->len - ETH_FCS_LEN);
2519
2520         if (ndev->features & NETIF_F_RXCSUM)
2521                 gfar_rx_checksum(skb, fcb);
2522
2523         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
2524          * Even if vlan rx accel is disabled, on some chips
2525          * RXFCB_VLN is pseudo randomly set.
2526          */
2527         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2528             be16_to_cpu(fcb->flags) & RXFCB_VLN)
2529                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2530                                        be16_to_cpu(fcb->vlctl));
2531 }
2532
2533 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2534  * until the budget/quota has been reached. Returns the number
2535  * of frames handled
2536  */
2537 static int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue,
2538                               int rx_work_limit)
2539 {
2540         struct net_device *ndev = rx_queue->ndev;
2541         struct gfar_private *priv = netdev_priv(ndev);
2542         struct rxbd8 *bdp;
2543         int i, howmany = 0;
2544         struct sk_buff *skb = rx_queue->skb;
2545         int cleaned_cnt = gfar_rxbd_unused(rx_queue);
2546         unsigned int total_bytes = 0, total_pkts = 0;
2547
2548         /* Get the first full descriptor */
2549         i = rx_queue->next_to_clean;
2550
2551         while (rx_work_limit--) {
2552                 u32 lstatus;
2553
2554                 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
2555                         gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2556                         cleaned_cnt = 0;
2557                 }
2558
2559                 bdp = &rx_queue->rx_bd_base[i];
2560                 lstatus = be32_to_cpu(bdp->lstatus);
2561                 if (lstatus & BD_LFLAG(RXBD_EMPTY))
2562                         break;
2563
2564                 /* lost RXBD_LAST descriptor due to overrun */
2565                 if (skb &&
2566                     (lstatus & BD_LFLAG(RXBD_FIRST))) {
2567                         /* discard faulty buffer */
2568                         dev_kfree_skb(skb);
2569                         skb = NULL;
2570                         rx_queue->stats.rx_dropped++;
2571
2572                         /* can continue normally */
2573                 }
2574
2575                 /* order rx buffer descriptor reads */
2576                 rmb();
2577
2578                 /* fetch next to clean buffer from the ring */
2579                 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
2580                 if (unlikely(!skb))
2581                         break;
2582
2583                 cleaned_cnt++;
2584                 howmany++;
2585
2586                 if (unlikely(++i == rx_queue->rx_ring_size))
2587                         i = 0;
2588
2589                 rx_queue->next_to_clean = i;
2590
2591                 /* fetch next buffer if not the last in frame */
2592                 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
2593                         continue;
2594
2595                 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
2596                         count_errors(lstatus, ndev);
2597
2598                         /* discard faulty buffer */
2599                         dev_kfree_skb(skb);
2600                         skb = NULL;
2601                         rx_queue->stats.rx_dropped++;
2602                         continue;
2603                 }
2604
2605                 gfar_process_frame(ndev, skb);
2606
2607                 /* Increment the number of packets */
2608                 total_pkts++;
2609                 total_bytes += skb->len;
2610
2611                 skb_record_rx_queue(skb, rx_queue->qindex);
2612
2613                 skb->protocol = eth_type_trans(skb, ndev);
2614
2615                 /* Send the packet up the stack */
2616                 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
2617
2618                 skb = NULL;
2619         }
2620
2621         /* Store incomplete frames for completion */
2622         rx_queue->skb = skb;
2623
2624         rx_queue->stats.rx_packets += total_pkts;
2625         rx_queue->stats.rx_bytes += total_bytes;
2626
2627         if (cleaned_cnt)
2628                 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
2629
2630         /* Update Last Free RxBD pointer for LFC */
2631         if (unlikely(priv->tx_actual_en)) {
2632                 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
2633
2634                 gfar_write(rx_queue->rfbptr, bdp_dma);
2635         }
2636
2637         return howmany;
2638 }
2639
2640 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
2641 {
2642         struct gfar_priv_grp *gfargrp =
2643                 container_of(napi, struct gfar_priv_grp, napi_rx);
2644         struct gfar __iomem *regs = gfargrp->regs;
2645         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
2646         int work_done = 0;
2647
2648         /* Clear IEVENT, so interrupts aren't called again
2649          * because of the packets that have already arrived
2650          */
2651         gfar_write(&regs->ievent, IEVENT_RX_MASK);
2652
2653         work_done = gfar_clean_rx_ring(rx_queue, budget);
2654
2655         if (work_done < budget) {
2656                 u32 imask;
2657                 napi_complete_done(napi, work_done);
2658                 /* Clear the halt bit in RSTAT */
2659                 gfar_write(&regs->rstat, gfargrp->rstat);
2660
2661                 spin_lock_irq(&gfargrp->grplock);
2662                 imask = gfar_read(&regs->imask);
2663                 imask |= IMASK_RX_DEFAULT;
2664                 gfar_write(&regs->imask, imask);
2665                 spin_unlock_irq(&gfargrp->grplock);
2666         }
2667
2668         return work_done;
2669 }
2670
2671 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
2672 {
2673         struct gfar_priv_grp *gfargrp =
2674                 container_of(napi, struct gfar_priv_grp, napi_tx);
2675         struct gfar __iomem *regs = gfargrp->regs;
2676         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
2677         u32 imask;
2678
2679         /* Clear IEVENT, so interrupts aren't called again
2680          * because of the packets that have already arrived
2681          */
2682         gfar_write(&regs->ievent, IEVENT_TX_MASK);
2683
2684         /* run Tx cleanup to completion */
2685         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
2686                 gfar_clean_tx_ring(tx_queue);
2687
2688         napi_complete(napi);
2689
2690         spin_lock_irq(&gfargrp->grplock);
2691         imask = gfar_read(&regs->imask);
2692         imask |= IMASK_TX_DEFAULT;
2693         gfar_write(&regs->imask, imask);
2694         spin_unlock_irq(&gfargrp->grplock);
2695
2696         return 0;
2697 }
2698
2699 static int gfar_poll_rx(struct napi_struct *napi, int budget)
2700 {
2701         struct gfar_priv_grp *gfargrp =
2702                 container_of(napi, struct gfar_priv_grp, napi_rx);
2703         struct gfar_private *priv = gfargrp->priv;
2704         struct gfar __iomem *regs = gfargrp->regs;
2705         struct gfar_priv_rx_q *rx_queue = NULL;
2706         int work_done = 0, work_done_per_q = 0;
2707         int i, budget_per_q = 0;
2708         unsigned long rstat_rxf;
2709         int num_act_queues;
2710
2711         /* Clear IEVENT, so interrupts aren't called again
2712          * because of the packets that have already arrived
2713          */
2714         gfar_write(&regs->ievent, IEVENT_RX_MASK);
2715
2716         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
2717
2718         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
2719         if (num_act_queues)
2720                 budget_per_q = budget/num_act_queues;
2721
2722         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2723                 /* skip queue if not active */
2724                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
2725                         continue;
2726
2727                 rx_queue = priv->rx_queue[i];
2728                 work_done_per_q =
2729                         gfar_clean_rx_ring(rx_queue, budget_per_q);
2730                 work_done += work_done_per_q;
2731
2732                 /* finished processing this queue */
2733                 if (work_done_per_q < budget_per_q) {
2734                         /* clear active queue hw indication */
2735                         gfar_write(&regs->rstat,
2736                                    RSTAT_CLEAR_RXF0 >> i);
2737                         num_act_queues--;
2738
2739                         if (!num_act_queues)
2740                                 break;
2741                 }
2742         }
2743
2744         if (!num_act_queues) {
2745                 u32 imask;
2746                 napi_complete_done(napi, work_done);
2747
2748                 /* Clear the halt bit in RSTAT */
2749                 gfar_write(&regs->rstat, gfargrp->rstat);
2750
2751                 spin_lock_irq(&gfargrp->grplock);
2752                 imask = gfar_read(&regs->imask);
2753                 imask |= IMASK_RX_DEFAULT;
2754                 gfar_write(&regs->imask, imask);
2755                 spin_unlock_irq(&gfargrp->grplock);
2756         }
2757
2758         return work_done;
2759 }
2760
2761 static int gfar_poll_tx(struct napi_struct *napi, int budget)
2762 {
2763         struct gfar_priv_grp *gfargrp =
2764                 container_of(napi, struct gfar_priv_grp, napi_tx);
2765         struct gfar_private *priv = gfargrp->priv;
2766         struct gfar __iomem *regs = gfargrp->regs;
2767         struct gfar_priv_tx_q *tx_queue = NULL;
2768         int has_tx_work = 0;
2769         int i;
2770
2771         /* Clear IEVENT, so interrupts aren't called again
2772          * because of the packets that have already arrived
2773          */
2774         gfar_write(&regs->ievent, IEVENT_TX_MASK);
2775
2776         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
2777                 tx_queue = priv->tx_queue[i];
2778                 /* run Tx cleanup to completion */
2779                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
2780                         gfar_clean_tx_ring(tx_queue);
2781                         has_tx_work = 1;
2782                 }
2783         }
2784
2785         if (!has_tx_work) {
2786                 u32 imask;
2787                 napi_complete(napi);
2788
2789                 spin_lock_irq(&gfargrp->grplock);
2790                 imask = gfar_read(&regs->imask);
2791                 imask |= IMASK_TX_DEFAULT;
2792                 gfar_write(&regs->imask, imask);
2793                 spin_unlock_irq(&gfargrp->grplock);
2794         }
2795
2796         return 0;
2797 }
2798
2799 /* GFAR error interrupt handler */
2800 static irqreturn_t gfar_error(int irq, void *grp_id)
2801 {
2802         struct gfar_priv_grp *gfargrp = grp_id;
2803         struct gfar __iomem *regs = gfargrp->regs;
2804         struct gfar_private *priv= gfargrp->priv;
2805         struct net_device *dev = priv->ndev;
2806
2807         /* Save ievent for future reference */
2808         u32 events = gfar_read(&regs->ievent);
2809
2810         /* Clear IEVENT */
2811         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
2812
2813         /* Magic Packet is not an error. */
2814         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2815             (events & IEVENT_MAG))
2816                 events &= ~IEVENT_MAG;
2817
2818         /* Hmm... */
2819         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2820                 netdev_dbg(dev,
2821                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
2822                            events, gfar_read(&regs->imask));
2823
2824         /* Update the error counters */
2825         if (events & IEVENT_TXE) {
2826                 dev->stats.tx_errors++;
2827
2828                 if (events & IEVENT_LC)
2829                         dev->stats.tx_window_errors++;
2830                 if (events & IEVENT_CRL)
2831                         dev->stats.tx_aborted_errors++;
2832                 if (events & IEVENT_XFUN) {
2833                         netif_dbg(priv, tx_err, dev,
2834                                   "TX FIFO underrun, packet dropped\n");
2835                         dev->stats.tx_dropped++;
2836                         atomic64_inc(&priv->extra_stats.tx_underrun);
2837
2838                         schedule_work(&priv->reset_task);
2839                 }
2840                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
2841         }
2842         if (events & IEVENT_BSY) {
2843                 dev->stats.rx_over_errors++;
2844                 atomic64_inc(&priv->extra_stats.rx_bsy);
2845
2846                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
2847                           gfar_read(&regs->rstat));
2848         }
2849         if (events & IEVENT_BABR) {
2850                 dev->stats.rx_errors++;
2851                 atomic64_inc(&priv->extra_stats.rx_babr);
2852
2853                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
2854         }
2855         if (events & IEVENT_EBERR) {
2856                 atomic64_inc(&priv->extra_stats.eberr);
2857                 netif_dbg(priv, rx_err, dev, "bus error\n");
2858         }
2859         if (events & IEVENT_RXC)
2860                 netif_dbg(priv, rx_status, dev, "control frame\n");
2861
2862         if (events & IEVENT_BABT) {
2863                 atomic64_inc(&priv->extra_stats.tx_babt);
2864                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
2865         }
2866         return IRQ_HANDLED;
2867 }
2868
2869 /* The interrupt handler for devices with one interrupt */
2870 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2871 {
2872         struct gfar_priv_grp *gfargrp = grp_id;
2873
2874         /* Save ievent for future reference */
2875         u32 events = gfar_read(&gfargrp->regs->ievent);
2876
2877         /* Check for reception */
2878         if (events & IEVENT_RX_MASK)
2879                 gfar_receive(irq, grp_id);
2880
2881         /* Check for transmit completion */
2882         if (events & IEVENT_TX_MASK)
2883                 gfar_transmit(irq, grp_id);
2884
2885         /* Check for errors */
2886         if (events & IEVENT_ERR_MASK)
2887                 gfar_error(irq, grp_id);
2888
2889         return IRQ_HANDLED;
2890 }
2891
2892 #ifdef CONFIG_NET_POLL_CONTROLLER
2893 /* Polling 'interrupt' - used by things like netconsole to send skbs
2894  * without having to re-enable interrupts. It's not called while
2895  * the interrupt routine is executing.
2896  */
2897 static void gfar_netpoll(struct net_device *dev)
2898 {
2899         struct gfar_private *priv = netdev_priv(dev);
2900         int i;
2901
2902         /* If the device has multiple interrupts, run tx/rx */
2903         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2904                 for (i = 0; i < priv->num_grps; i++) {
2905                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
2906
2907                         disable_irq(gfar_irq(grp, TX)->irq);
2908                         disable_irq(gfar_irq(grp, RX)->irq);
2909                         disable_irq(gfar_irq(grp, ER)->irq);
2910                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2911                         enable_irq(gfar_irq(grp, ER)->irq);
2912                         enable_irq(gfar_irq(grp, RX)->irq);
2913                         enable_irq(gfar_irq(grp, TX)->irq);
2914                 }
2915         } else {
2916                 for (i = 0; i < priv->num_grps; i++) {
2917                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
2918
2919                         disable_irq(gfar_irq(grp, TX)->irq);
2920                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
2921                         enable_irq(gfar_irq(grp, TX)->irq);
2922                 }
2923         }
2924 }
2925 #endif
2926
2927 static void free_grp_irqs(struct gfar_priv_grp *grp)
2928 {
2929         free_irq(gfar_irq(grp, TX)->irq, grp);
2930         free_irq(gfar_irq(grp, RX)->irq, grp);
2931         free_irq(gfar_irq(grp, ER)->irq, grp);
2932 }
2933
2934 static int register_grp_irqs(struct gfar_priv_grp *grp)
2935 {
2936         struct gfar_private *priv = grp->priv;
2937         struct net_device *dev = priv->ndev;
2938         int err;
2939
2940         /* If the device has multiple interrupts, register for
2941          * them.  Otherwise, only register for the one
2942          */
2943         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2944                 /* Install our interrupt handlers for Error,
2945                  * Transmit, and Receive
2946                  */
2947                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2948                                   gfar_irq(grp, ER)->name, grp);
2949                 if (err < 0) {
2950                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2951                                   gfar_irq(grp, ER)->irq);
2952
2953                         goto err_irq_fail;
2954                 }
2955                 enable_irq_wake(gfar_irq(grp, ER)->irq);
2956
2957                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2958                                   gfar_irq(grp, TX)->name, grp);
2959                 if (err < 0) {
2960                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2961                                   gfar_irq(grp, TX)->irq);
2962                         goto tx_irq_fail;
2963                 }
2964                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2965                                   gfar_irq(grp, RX)->name, grp);
2966                 if (err < 0) {
2967                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2968                                   gfar_irq(grp, RX)->irq);
2969                         goto rx_irq_fail;
2970                 }
2971                 enable_irq_wake(gfar_irq(grp, RX)->irq);
2972
2973         } else {
2974                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2975                                   gfar_irq(grp, TX)->name, grp);
2976                 if (err < 0) {
2977                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2978                                   gfar_irq(grp, TX)->irq);
2979                         goto err_irq_fail;
2980                 }
2981                 enable_irq_wake(gfar_irq(grp, TX)->irq);
2982         }
2983
2984         return 0;
2985
2986 rx_irq_fail:
2987         free_irq(gfar_irq(grp, TX)->irq, grp);
2988 tx_irq_fail:
2989         free_irq(gfar_irq(grp, ER)->irq, grp);
2990 err_irq_fail:
2991         return err;
2992
2993 }
2994
2995 static void gfar_free_irq(struct gfar_private *priv)
2996 {
2997         int i;
2998
2999         /* Free the IRQs */
3000         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3001                 for (i = 0; i < priv->num_grps; i++)
3002                         free_grp_irqs(&priv->gfargrp[i]);
3003         } else {
3004                 for (i = 0; i < priv->num_grps; i++)
3005                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
3006                                  &priv->gfargrp[i]);
3007         }
3008 }
3009
3010 static int gfar_request_irq(struct gfar_private *priv)
3011 {
3012         int err, i, j;
3013
3014         for (i = 0; i < priv->num_grps; i++) {
3015                 err = register_grp_irqs(&priv->gfargrp[i]);
3016                 if (err) {
3017                         for (j = 0; j < i; j++)
3018                                 free_grp_irqs(&priv->gfargrp[j]);
3019                         return err;
3020                 }
3021         }
3022
3023         return 0;
3024 }
3025
3026 /* Called when something needs to use the ethernet device
3027  * Returns 0 for success.
3028  */
3029 static int gfar_enet_open(struct net_device *dev)
3030 {
3031         struct gfar_private *priv = netdev_priv(dev);
3032         int err;
3033
3034         err = init_phy(dev);
3035         if (err)
3036                 return err;
3037
3038         err = gfar_request_irq(priv);
3039         if (err)
3040                 return err;
3041
3042         err = startup_gfar(dev);
3043         if (err)
3044                 return err;
3045
3046         return err;
3047 }
3048
3049 /* Stops the kernel queue, and halts the controller */
3050 static int gfar_close(struct net_device *dev)
3051 {
3052         struct gfar_private *priv = netdev_priv(dev);
3053
3054         cancel_work_sync(&priv->reset_task);
3055         stop_gfar(dev);
3056
3057         /* Disconnect from the PHY */
3058         phy_disconnect(dev->phydev);
3059
3060         gfar_free_irq(priv);
3061
3062         return 0;
3063 }
3064
3065 /* Clears each of the exact match registers to zero, so they
3066  * don't interfere with normal reception
3067  */
3068 static void gfar_clear_exact_match(struct net_device *dev)
3069 {
3070         int idx;
3071         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3072
3073         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3074                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3075 }
3076
3077 /* Update the hash table based on the current list of multicast
3078  * addresses we subscribe to.  Also, change the promiscuity of
3079  * the device based on the flags (this function is called
3080  * whenever dev->flags is changed
3081  */
3082 static void gfar_set_multi(struct net_device *dev)
3083 {
3084         struct netdev_hw_addr *ha;
3085         struct gfar_private *priv = netdev_priv(dev);
3086         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3087         u32 tempval;
3088
3089         if (dev->flags & IFF_PROMISC) {
3090                 /* Set RCTRL to PROM */
3091                 tempval = gfar_read(&regs->rctrl);
3092                 tempval |= RCTRL_PROM;
3093                 gfar_write(&regs->rctrl, tempval);
3094         } else {
3095                 /* Set RCTRL to not PROM */
3096                 tempval = gfar_read(&regs->rctrl);
3097                 tempval &= ~(RCTRL_PROM);
3098                 gfar_write(&regs->rctrl, tempval);
3099         }
3100
3101         if (dev->flags & IFF_ALLMULTI) {
3102                 /* Set the hash to rx all multicast frames */
3103                 gfar_write(&regs->igaddr0, 0xffffffff);
3104                 gfar_write(&regs->igaddr1, 0xffffffff);
3105                 gfar_write(&regs->igaddr2, 0xffffffff);
3106                 gfar_write(&regs->igaddr3, 0xffffffff);
3107                 gfar_write(&regs->igaddr4, 0xffffffff);
3108                 gfar_write(&regs->igaddr5, 0xffffffff);
3109                 gfar_write(&regs->igaddr6, 0xffffffff);
3110                 gfar_write(&regs->igaddr7, 0xffffffff);
3111                 gfar_write(&regs->gaddr0, 0xffffffff);
3112                 gfar_write(&regs->gaddr1, 0xffffffff);
3113                 gfar_write(&regs->gaddr2, 0xffffffff);
3114                 gfar_write(&regs->gaddr3, 0xffffffff);
3115                 gfar_write(&regs->gaddr4, 0xffffffff);
3116                 gfar_write(&regs->gaddr5, 0xffffffff);
3117                 gfar_write(&regs->gaddr6, 0xffffffff);
3118                 gfar_write(&regs->gaddr7, 0xffffffff);
3119         } else {
3120                 int em_num;
3121                 int idx;
3122
3123                 /* zero out the hash */
3124                 gfar_write(&regs->igaddr0, 0x0);
3125                 gfar_write(&regs->igaddr1, 0x0);
3126                 gfar_write(&regs->igaddr2, 0x0);
3127                 gfar_write(&regs->igaddr3, 0x0);
3128                 gfar_write(&regs->igaddr4, 0x0);
3129                 gfar_write(&regs->igaddr5, 0x0);
3130                 gfar_write(&regs->igaddr6, 0x0);
3131                 gfar_write(&regs->igaddr7, 0x0);
3132                 gfar_write(&regs->gaddr0, 0x0);
3133                 gfar_write(&regs->gaddr1, 0x0);
3134                 gfar_write(&regs->gaddr2, 0x0);
3135                 gfar_write(&regs->gaddr3, 0x0);
3136                 gfar_write(&regs->gaddr4, 0x0);
3137                 gfar_write(&regs->gaddr5, 0x0);
3138                 gfar_write(&regs->gaddr6, 0x0);
3139                 gfar_write(&regs->gaddr7, 0x0);
3140
3141                 /* If we have extended hash tables, we need to
3142                  * clear the exact match registers to prepare for
3143                  * setting them
3144                  */
3145                 if (priv->extended_hash) {
3146                         em_num = GFAR_EM_NUM + 1;
3147                         gfar_clear_exact_match(dev);
3148                         idx = 1;
3149                 } else {
3150                         idx = 0;
3151                         em_num = 0;
3152                 }
3153
3154                 if (netdev_mc_empty(dev))
3155                         return;
3156
3157                 /* Parse the list, and set the appropriate bits */
3158                 netdev_for_each_mc_addr(ha, dev) {
3159                         if (idx < em_num) {
3160                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3161                                 idx++;
3162                         } else
3163                                 gfar_set_hash_for_addr(dev, ha->addr);
3164                 }
3165         }
3166 }
3167
3168 void gfar_mac_reset(struct gfar_private *priv)
3169 {
3170         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3171         u32 tempval;
3172
3173         /* Reset MAC layer */
3174         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
3175
3176         /* We need to delay at least 3 TX clocks */
3177         udelay(3);
3178
3179         /* the soft reset bit is not self-resetting, so we need to
3180          * clear it before resuming normal operation
3181          */
3182         gfar_write(&regs->maccfg1, 0);
3183
3184         udelay(3);
3185
3186         gfar_rx_offload_en(priv);
3187
3188         /* Initialize the max receive frame/buffer lengths */
3189         gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
3190         gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
3191
3192         /* Initialize the Minimum Frame Length Register */
3193         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
3194
3195         /* Initialize MACCFG2. */
3196         tempval = MACCFG2_INIT_SETTINGS;
3197
3198         /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
3199          * are marked as truncated.  Avoid this by MACCFG2[Huge Frame]=1,
3200          * and by checking RxBD[LG] and discarding larger than MAXFRM.
3201          */
3202         if (gfar_has_errata(priv, GFAR_ERRATA_74))
3203                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
3204
3205         gfar_write(&regs->maccfg2, tempval);
3206
3207         /* Clear mac addr hash registers */
3208         gfar_write(&regs->igaddr0, 0);
3209         gfar_write(&regs->igaddr1, 0);
3210         gfar_write(&regs->igaddr2, 0);
3211         gfar_write(&regs->igaddr3, 0);
3212         gfar_write(&regs->igaddr4, 0);
3213         gfar_write(&regs->igaddr5, 0);
3214         gfar_write(&regs->igaddr6, 0);
3215         gfar_write(&regs->igaddr7, 0);
3216
3217         gfar_write(&regs->gaddr0, 0);
3218         gfar_write(&regs->gaddr1, 0);
3219         gfar_write(&regs->gaddr2, 0);
3220         gfar_write(&regs->gaddr3, 0);
3221         gfar_write(&regs->gaddr4, 0);
3222         gfar_write(&regs->gaddr5, 0);
3223         gfar_write(&regs->gaddr6, 0);
3224         gfar_write(&regs->gaddr7, 0);
3225
3226         if (priv->extended_hash)
3227                 gfar_clear_exact_match(priv->ndev);
3228
3229         gfar_mac_rx_config(priv);
3230
3231         gfar_mac_tx_config(priv);
3232
3233         gfar_set_mac_address(priv->ndev);
3234
3235         gfar_set_multi(priv->ndev);
3236
3237         /* clear ievent and imask before configuring coalescing */
3238         gfar_ints_disable(priv);
3239
3240         /* Configure the coalescing support */
3241         gfar_configure_coalescing_all(priv);
3242 }
3243
3244 static void gfar_hw_init(struct gfar_private *priv)
3245 {
3246         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3247         u32 attrs;
3248
3249         /* Stop the DMA engine now, in case it was running before
3250          * (The firmware could have used it, and left it running).
3251          */
3252         gfar_halt(priv);
3253
3254         gfar_mac_reset(priv);
3255
3256         /* Zero out the rmon mib registers if it has them */
3257         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
3258                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
3259
3260                 /* Mask off the CAM interrupts */
3261                 gfar_write(&regs->rmon.cam1, 0xffffffff);
3262                 gfar_write(&regs->rmon.cam2, 0xffffffff);
3263         }
3264
3265         /* Initialize ECNTRL */
3266         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
3267
3268         /* Set the extraction length and index */
3269         attrs = ATTRELI_EL(priv->rx_stash_size) |
3270                 ATTRELI_EI(priv->rx_stash_index);
3271
3272         gfar_write(&regs->attreli, attrs);
3273
3274         /* Start with defaults, and add stashing
3275          * depending on driver parameters
3276          */
3277         attrs = ATTR_INIT_SETTINGS;
3278
3279         if (priv->bd_stash_en)
3280                 attrs |= ATTR_BDSTASH;
3281
3282         if (priv->rx_stash_size != 0)
3283                 attrs |= ATTR_BUFSTASH;
3284
3285         gfar_write(&regs->attr, attrs);
3286
3287         /* FIFO configs */
3288         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
3289         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
3290         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
3291
3292         /* Program the interrupt steering regs, only for MG devices */
3293         if (priv->num_grps > 1)
3294                 gfar_write_isrg(priv);
3295 }
3296
3297 static const struct net_device_ops gfar_netdev_ops = {
3298         .ndo_open = gfar_enet_open,
3299         .ndo_start_xmit = gfar_start_xmit,
3300         .ndo_stop = gfar_close,
3301         .ndo_change_mtu = gfar_change_mtu,
3302         .ndo_set_features = gfar_set_features,
3303         .ndo_set_rx_mode = gfar_set_multi,
3304         .ndo_tx_timeout = gfar_timeout,
3305         .ndo_do_ioctl = gfar_ioctl,
3306         .ndo_get_stats = gfar_get_stats,
3307         .ndo_change_carrier = fixed_phy_change_carrier,
3308         .ndo_set_mac_address = gfar_set_mac_addr,
3309         .ndo_validate_addr = eth_validate_addr,
3310 #ifdef CONFIG_NET_POLL_CONTROLLER
3311         .ndo_poll_controller = gfar_netpoll,
3312 #endif
3313 };
3314
3315 /* Set up the ethernet device structure, private data,
3316  * and anything else we need before we start
3317  */
3318 static int gfar_probe(struct platform_device *ofdev)
3319 {
3320         struct device_node *np = ofdev->dev.of_node;
3321         struct net_device *dev = NULL;
3322         struct gfar_private *priv = NULL;
3323         int err = 0, i;
3324
3325         err = gfar_of_init(ofdev, &dev);
3326
3327         if (err)
3328                 return err;
3329
3330         priv = netdev_priv(dev);
3331         priv->ndev = dev;
3332         priv->ofdev = ofdev;
3333         priv->dev = &ofdev->dev;
3334         SET_NETDEV_DEV(dev, &ofdev->dev);
3335
3336         INIT_WORK(&priv->reset_task, gfar_reset_task);
3337
3338         platform_set_drvdata(ofdev, priv);
3339
3340         gfar_detect_errata(priv);
3341
3342         /* Set the dev->base_addr to the gfar reg region */
3343         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
3344
3345         /* Fill in the dev structure */
3346         dev->watchdog_timeo = TX_TIMEOUT;
3347         /* MTU range: 50 - 9586 */
3348         dev->mtu = 1500;
3349         dev->min_mtu = 50;
3350         dev->max_mtu = GFAR_JUMBO_FRAME_SIZE - ETH_HLEN;
3351         dev->netdev_ops = &gfar_netdev_ops;
3352         dev->ethtool_ops = &gfar_ethtool_ops;
3353
3354         /* Register for napi ...We are registering NAPI for each grp */
3355         for (i = 0; i < priv->num_grps; i++) {
3356                 if (priv->poll_mode == GFAR_SQ_POLLING) {
3357                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3358                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
3359                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3360                                        gfar_poll_tx_sq, 2);
3361                 } else {
3362                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
3363                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
3364                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
3365                                        gfar_poll_tx, 2);
3366                 }
3367         }
3368
3369         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
3370                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3371                                    NETIF_F_RXCSUM;
3372                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
3373                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
3374         }
3375
3376         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
3377                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
3378                                     NETIF_F_HW_VLAN_CTAG_RX;
3379                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3380         }
3381
3382         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3383
3384         gfar_init_addr_hash_table(priv);
3385
3386         /* Insert receive time stamps into padding alignment bytes, and
3387          * plus 2 bytes padding to ensure the cpu alignment.
3388          */
3389         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3390                 priv->padding = 8 + DEFAULT_PADDING;
3391
3392         if (dev->features & NETIF_F_IP_CSUM ||
3393             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
3394                 dev->needed_headroom = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
3395
3396         /* Initializing some of the rx/tx queue level parameters */
3397         for (i = 0; i < priv->num_tx_queues; i++) {
3398                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
3399                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
3400                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
3401                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
3402         }
3403
3404         for (i = 0; i < priv->num_rx_queues; i++) {
3405                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
3406                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
3407                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
3408         }
3409
3410         /* Always enable rx filer if available */
3411         priv->rx_filer_enable =
3412             (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
3413         /* Enable most messages by default */
3414         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
3415         /* use pritority h/w tx queue scheduling for single queue devices */
3416         if (priv->num_tx_queues == 1)
3417                 priv->prio_sched_en = 1;
3418
3419         set_bit(GFAR_DOWN, &priv->state);
3420
3421         gfar_hw_init(priv);
3422
3423         /* Carrier starts down, phylib will bring it up */
3424         netif_carrier_off(dev);
3425
3426         err = register_netdev(dev);
3427
3428         if (err) {
3429                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
3430                 goto register_fail;
3431         }
3432
3433         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
3434                 priv->wol_supported |= GFAR_WOL_MAGIC;
3435
3436         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
3437             priv->rx_filer_enable)
3438                 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
3439
3440         device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
3441
3442         /* fill out IRQ number and name fields */
3443         for (i = 0; i < priv->num_grps; i++) {
3444                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
3445                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3446                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
3447                                 dev->name, "_g", '0' + i, "_tx");
3448                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
3449                                 dev->name, "_g", '0' + i, "_rx");
3450                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
3451                                 dev->name, "_g", '0' + i, "_er");
3452                 } else
3453                         strcpy(gfar_irq(grp, TX)->name, dev->name);
3454         }
3455
3456         /* Initialize the filer table */
3457         gfar_init_filer_table(priv);
3458
3459         /* Print out the device info */
3460         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
3461
3462         /* Even more device info helps when determining which kernel
3463          * provided which set of benchmarks.
3464          */
3465         netdev_info(dev, "Running with NAPI enabled\n");
3466         for (i = 0; i < priv->num_rx_queues; i++)
3467                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
3468                             i, priv->rx_queue[i]->rx_ring_size);
3469         for (i = 0; i < priv->num_tx_queues; i++)
3470                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
3471                             i, priv->tx_queue[i]->tx_ring_size);
3472
3473         return 0;
3474
3475 register_fail:
3476         if (of_phy_is_fixed_link(np))
3477                 of_phy_deregister_fixed_link(np);
3478         unmap_group_regs(priv);
3479         gfar_free_rx_queues(priv);
3480         gfar_free_tx_queues(priv);
3481         of_node_put(priv->phy_node);
3482         of_node_put(priv->tbi_node);
3483         free_gfar_dev(priv);
3484         return err;
3485 }
3486
3487 static int gfar_remove(struct platform_device *ofdev)
3488 {
3489         struct gfar_private *priv = platform_get_drvdata(ofdev);
3490         struct device_node *np = ofdev->dev.of_node;
3491
3492         of_node_put(priv->phy_node);
3493         of_node_put(priv->tbi_node);
3494
3495         unregister_netdev(priv->ndev);
3496
3497         if (of_phy_is_fixed_link(np))
3498                 of_phy_deregister_fixed_link(np);
3499
3500         unmap_group_regs(priv);
3501         gfar_free_rx_queues(priv);
3502         gfar_free_tx_queues(priv);
3503         free_gfar_dev(priv);
3504
3505         return 0;
3506 }
3507
3508 #ifdef CONFIG_PM
3509
3510 static void __gfar_filer_disable(struct gfar_private *priv)
3511 {
3512         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3513         u32 temp;
3514
3515         temp = gfar_read(&regs->rctrl);
3516         temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
3517         gfar_write(&regs->rctrl, temp);
3518 }
3519
3520 static void __gfar_filer_enable(struct gfar_private *priv)
3521 {
3522         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3523         u32 temp;
3524
3525         temp = gfar_read(&regs->rctrl);
3526         temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
3527         gfar_write(&regs->rctrl, temp);
3528 }
3529
3530 /* Filer rules implementing wol capabilities */
3531 static void gfar_filer_config_wol(struct gfar_private *priv)
3532 {
3533         unsigned int i;
3534         u32 rqfcr;
3535
3536         __gfar_filer_disable(priv);
3537
3538         /* clear the filer table, reject any packet by default */
3539         rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
3540         for (i = 0; i <= MAX_FILER_IDX; i++)
3541                 gfar_write_filer(priv, i, rqfcr, 0);
3542
3543         i = 0;
3544         if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
3545                 /* unicast packet, accept it */
3546                 struct net_device *ndev = priv->ndev;
3547                 /* get the default rx queue index */
3548                 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
3549                 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
3550                                     (ndev->dev_addr[1] << 8) |
3551                                      ndev->dev_addr[2];
3552
3553                 rqfcr = (qindex << 10) | RQFCR_AND |
3554                         RQFCR_CMP_EXACT | RQFCR_PID_DAH;
3555
3556                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3557
3558                 dest_mac_addr = (ndev->dev_addr[3] << 16) |
3559                                 (ndev->dev_addr[4] << 8) |
3560                                  ndev->dev_addr[5];
3561                 rqfcr = (qindex << 10) | RQFCR_GPI |
3562                         RQFCR_CMP_EXACT | RQFCR_PID_DAL;
3563                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
3564         }
3565
3566         __gfar_filer_enable(priv);
3567 }
3568
3569 static void gfar_filer_restore_table(struct gfar_private *priv)
3570 {
3571         u32 rqfcr, rqfpr;
3572         unsigned int i;
3573
3574         __gfar_filer_disable(priv);
3575
3576         for (i = 0; i <= MAX_FILER_IDX; i++) {
3577                 rqfcr = priv->ftp_rqfcr[i];
3578                 rqfpr = priv->ftp_rqfpr[i];
3579                 gfar_write_filer(priv, i, rqfcr, rqfpr);
3580         }
3581
3582         __gfar_filer_enable(priv);
3583 }
3584
3585 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
3586 static void gfar_start_wol_filer(struct gfar_private *priv)
3587 {
3588         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3589         u32 tempval;
3590         int i = 0;
3591
3592         /* Enable Rx hw queues */
3593         gfar_write(&regs->rqueue, priv->rqueue);
3594
3595         /* Initialize DMACTRL to have WWR and WOP */
3596         tempval = gfar_read(&regs->dmactrl);
3597         tempval |= DMACTRL_INIT_SETTINGS;
3598         gfar_write(&regs->dmactrl, tempval);
3599
3600         /* Make sure we aren't stopped */
3601         tempval = gfar_read(&regs->dmactrl);
3602         tempval &= ~DMACTRL_GRS;
3603         gfar_write(&regs->dmactrl, tempval);
3604
3605         for (i = 0; i < priv->num_grps; i++) {
3606                 regs = priv->gfargrp[i].regs;
3607                 /* Clear RHLT, so that the DMA starts polling now */
3608                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
3609                 /* enable the Filer General Purpose Interrupt */
3610                 gfar_write(&regs->imask, IMASK_FGPI);
3611         }
3612
3613         /* Enable Rx DMA */
3614         tempval = gfar_read(&regs->maccfg1);
3615         tempval |= MACCFG1_RX_EN;
3616         gfar_write(&regs->maccfg1, tempval);
3617 }
3618
3619 static int gfar_suspend(struct device *dev)
3620 {
3621         struct gfar_private *priv = dev_get_drvdata(dev);
3622         struct net_device *ndev = priv->ndev;
3623         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3624         u32 tempval;
3625         u16 wol = priv->wol_opts;
3626
3627         if (!netif_running(ndev))
3628                 return 0;
3629
3630         disable_napi(priv);
3631         netif_tx_lock(ndev);
3632         netif_device_detach(ndev);
3633         netif_tx_unlock(ndev);
3634
3635         gfar_halt(priv);
3636
3637         if (wol & GFAR_WOL_MAGIC) {
3638                 /* Enable interrupt on Magic Packet */
3639                 gfar_write(&regs->imask, IMASK_MAG);
3640
3641                 /* Enable Magic Packet mode */
3642                 tempval = gfar_read(&regs->maccfg2);
3643                 tempval |= MACCFG2_MPEN;
3644                 gfar_write(&regs->maccfg2, tempval);
3645
3646                 /* re-enable the Rx block */
3647                 tempval = gfar_read(&regs->maccfg1);
3648                 tempval |= MACCFG1_RX_EN;
3649                 gfar_write(&regs->maccfg1, tempval);
3650
3651         } else if (wol & GFAR_WOL_FILER_UCAST) {
3652                 gfar_filer_config_wol(priv);
3653                 gfar_start_wol_filer(priv);
3654
3655         } else {
3656                 phy_stop(ndev->phydev);
3657         }
3658
3659         return 0;
3660 }
3661
3662 static int gfar_resume(struct device *dev)
3663 {
3664         struct gfar_private *priv = dev_get_drvdata(dev);
3665         struct net_device *ndev = priv->ndev;
3666         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3667         u32 tempval;
3668         u16 wol = priv->wol_opts;
3669
3670         if (!netif_running(ndev))
3671                 return 0;
3672
3673         if (wol & GFAR_WOL_MAGIC) {
3674                 /* Disable Magic Packet mode */
3675                 tempval = gfar_read(&regs->maccfg2);
3676                 tempval &= ~MACCFG2_MPEN;
3677                 gfar_write(&regs->maccfg2, tempval);
3678
3679         } else if (wol & GFAR_WOL_FILER_UCAST) {
3680                 /* need to stop rx only, tx is already down */
3681                 gfar_halt(priv);
3682                 gfar_filer_restore_table(priv);
3683
3684         } else {
3685                 phy_start(ndev->phydev);
3686         }
3687
3688         gfar_start(priv);
3689
3690         netif_device_attach(ndev);
3691         enable_napi(priv);
3692
3693         return 0;
3694 }
3695
3696 static int gfar_restore(struct device *dev)
3697 {
3698         struct gfar_private *priv = dev_get_drvdata(dev);
3699         struct net_device *ndev = priv->ndev;
3700
3701         if (!netif_running(ndev)) {
3702                 netif_device_attach(ndev);
3703
3704                 return 0;
3705         }
3706
3707         gfar_init_bds(ndev);
3708
3709         gfar_mac_reset(priv);
3710
3711         gfar_init_tx_rx_base(priv);
3712
3713         gfar_start(priv);
3714
3715         priv->oldlink = 0;
3716         priv->oldspeed = 0;
3717         priv->oldduplex = -1;
3718
3719         if (ndev->phydev)
3720                 phy_start(ndev->phydev);
3721
3722         netif_device_attach(ndev);
3723         enable_napi(priv);
3724
3725         return 0;
3726 }
3727
3728 static const struct dev_pm_ops gfar_pm_ops = {
3729         .suspend = gfar_suspend,
3730         .resume = gfar_resume,
3731         .freeze = gfar_suspend,
3732         .thaw = gfar_resume,
3733         .restore = gfar_restore,
3734 };
3735
3736 #define GFAR_PM_OPS (&gfar_pm_ops)
3737
3738 #else
3739
3740 #define GFAR_PM_OPS NULL
3741
3742 #endif
3743
3744 static const struct of_device_id gfar_match[] =
3745 {
3746         {
3747                 .type = "network",
3748                 .compatible = "gianfar",
3749         },
3750         {
3751                 .compatible = "fsl,etsec2",
3752         },
3753         {},
3754 };
3755 MODULE_DEVICE_TABLE(of, gfar_match);
3756
3757 /* Structure for a device driver */
3758 static struct platform_driver gfar_driver = {
3759         .driver = {
3760                 .name = "fsl-gianfar",
3761                 .pm = GFAR_PM_OPS,
3762                 .of_match_table = gfar_match,
3763         },
3764         .probe = gfar_probe,
3765         .remove = gfar_remove,
3766 };
3767
3768 module_platform_driver(gfar_driver);