2 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
3 * Provides Bus interface for MIIM regs
5 * Author: Andy Fleming <afleming@freescale.com>
6 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
8 * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
10 * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/string.h>
21 #include <linux/errno.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/mii.h>
26 #include <linux/of_address.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_device.h>
31 #if IS_ENABLED(CONFIG_UCC_GETH)
32 #include <soc/fsl/qe/ucc.h>
37 #define MIIMIND_BUSY 0x00000001
38 #define MIIMIND_NOTVALID 0x00000004
39 #define MIIMCFG_INIT_VALUE 0x00000007
40 #define MIIMCFG_RESET 0x80000000
42 #define MII_READ_COMMAND 0x00000001
45 u32 miimcfg; /* MII management configuration reg */
46 u32 miimcom; /* MII management command reg */
47 u32 miimadd; /* MII management address reg */
48 u32 miimcon; /* MII management control reg */
49 u32 miimstat; /* MII management status reg */
50 u32 miimind; /* MII management indication reg */
55 u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/
56 u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/
58 u32 emapm; /* MDIO Event mapping register (for etsec2)*/
60 struct fsl_pq_mii mii;
62 u32 utbipar; /* TBI phy address reg (only on UCC) */
66 /* Number of microseconds to wait for an MII register to respond */
67 #define MII_TIMEOUT 1000
69 struct fsl_pq_mdio_priv {
71 struct fsl_pq_mii __iomem *regs;
75 * Per-device-type data. Each type of device tree node that we support gets
78 * @mii_offset: the offset of the MII registers within the memory map of the
79 * node. Some nodes define only the MII registers, and some define the whole
80 * MAC (which includes the MII registers).
82 * @get_tbipa: determines the address of the TBIPA register
84 * @ucc_configure: a special function for extra QE configuration
86 struct fsl_pq_mdio_data {
87 unsigned int mii_offset; /* offset of the MII registers */
88 uint32_t __iomem * (*get_tbipa)(void __iomem *p);
89 void (*ucc_configure)(phys_addr_t start, phys_addr_t end);
93 * Write value to the PHY at mii_id at register regnum, on the bus attached
94 * to the local interface, which may be different from the generic mdio bus
95 * (tied to a single interface), waiting until the write is done before
96 * returning. This is helpful in programming interfaces like the TBI which
97 * control interfaces like onchip SERDES and are always tied to the local
98 * mdio pins, which may not be the same as system mdio bus, used for
99 * controlling the external PHYs, for example.
101 static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
104 struct fsl_pq_mdio_priv *priv = bus->priv;
105 struct fsl_pq_mii __iomem *regs = priv->regs;
106 unsigned int timeout;
108 /* Set the PHY address and the register address we want to write */
109 iowrite32be((mii_id << 8) | regnum, ®s->miimadd);
111 /* Write out the value we want */
112 iowrite32be(value, ®s->miimcon);
114 /* Wait for the transaction to finish */
115 timeout = MII_TIMEOUT;
116 while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) {
121 return timeout ? 0 : -ETIMEDOUT;
125 * Read the bus for PHY at addr mii_id, register regnum, and return the value.
126 * Clears miimcom first.
128 * All PHY operation done on the bus attached to the local interface, which
129 * may be different from the generic mdio bus. This is helpful in programming
130 * interfaces like the TBI which, in turn, control interfaces like on-chip
131 * SERDES and are always tied to the local mdio pins, which may not be the
132 * same as system mdio bus, used for controlling the external PHYs, for eg.
134 static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
136 struct fsl_pq_mdio_priv *priv = bus->priv;
137 struct fsl_pq_mii __iomem *regs = priv->regs;
138 unsigned int timeout;
141 /* Set the PHY address and the register address we want to read */
142 iowrite32be((mii_id << 8) | regnum, ®s->miimadd);
144 /* Clear miimcom, and then initiate a read */
145 iowrite32be(0, ®s->miimcom);
146 iowrite32be(MII_READ_COMMAND, ®s->miimcom);
148 /* Wait for the transaction to finish, normally less than 100us */
149 timeout = MII_TIMEOUT;
150 while ((ioread32be(®s->miimind) &
151 (MIIMIND_NOTVALID | MIIMIND_BUSY)) && timeout) {
159 /* Grab the value of the register from miimstat */
160 value = ioread32be(®s->miimstat);
162 dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum);
166 /* Reset the MIIM registers, and wait for the bus to free */
167 static int fsl_pq_mdio_reset(struct mii_bus *bus)
169 struct fsl_pq_mdio_priv *priv = bus->priv;
170 struct fsl_pq_mii __iomem *regs = priv->regs;
171 unsigned int timeout;
173 mutex_lock(&bus->mdio_lock);
175 /* Reset the management interface */
176 iowrite32be(MIIMCFG_RESET, ®s->miimcfg);
178 /* Setup the MII Mgmt clock speed */
179 iowrite32be(MIIMCFG_INIT_VALUE, ®s->miimcfg);
181 /* Wait until the bus is free */
182 timeout = MII_TIMEOUT;
183 while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) {
188 mutex_unlock(&bus->mdio_lock);
191 dev_err(&bus->dev, "timeout waiting for MII bus\n");
198 #if IS_ENABLED(CONFIG_GIANFAR)
200 * Return the TBIPA address, starting from the address
201 * of the mapped GFAR MDIO registers (struct gfar)
202 * This is mildly evil, but so is our hardware for doing this.
203 * Also, we have to cast back to struct gfar because of
204 * definition weirdness done in gianfar.h.
206 static uint32_t __iomem *get_gfar_tbipa_from_mdio(void __iomem *p)
208 struct gfar __iomem *enet_regs = p;
210 return &enet_regs->tbipa;
214 * Return the TBIPA address, starting from the address
215 * of the mapped GFAR MII registers (gfar_mii_regs[] within struct gfar)
217 static uint32_t __iomem *get_gfar_tbipa_from_mii(void __iomem *p)
219 return get_gfar_tbipa_from_mdio(container_of(p, struct gfar, gfar_mii_regs));
223 * Return the TBIPAR address for an eTSEC2 node
225 static uint32_t __iomem *get_etsec_tbipa(void __iomem *p)
231 #if IS_ENABLED(CONFIG_UCC_GETH)
233 * Return the TBIPAR address for a QE MDIO node, starting from the address
234 * of the mapped MII registers (struct fsl_pq_mii)
236 static uint32_t __iomem *get_ucc_tbipa(void __iomem *p)
238 struct fsl_pq_mdio __iomem *mdio = container_of(p, struct fsl_pq_mdio, mii);
240 return &mdio->utbipar;
244 * Find the UCC node that controls the given MDIO node
246 * For some reason, the QE MDIO nodes are not children of the UCC devices
247 * that control them. Therefore, we need to scan all UCC nodes looking for
248 * the one that encompases the given MDIO node. We do this by comparing
249 * physical addresses. The 'start' and 'end' addresses of the MDIO node are
250 * passed, and the correct UCC node will cover the entire address range.
252 * This assumes that there is only one QE MDIO node in the entire device tree.
254 static void ucc_configure(phys_addr_t start, phys_addr_t end)
256 static bool found_mii_master;
257 struct device_node *np = NULL;
259 if (found_mii_master)
262 for_each_compatible_node(np, NULL, "ucc_geth") {
264 const uint32_t *iprop;
268 ret = of_address_to_resource(np, 0, &res);
270 pr_debug("fsl-pq-mdio: no address range in node %s\n",
275 /* if our mdio regs fall within this UCC regs range */
276 if ((start < res.start) || (end > res.end))
279 iprop = of_get_property(np, "cell-index", NULL);
281 iprop = of_get_property(np, "device-id", NULL);
283 pr_debug("fsl-pq-mdio: no UCC ID in node %s\n",
289 id = be32_to_cpup(iprop);
292 * cell-index and device-id for QE nodes are
293 * numbered from 1, not 0.
295 if (ucc_set_qe_mux_mii_mng(id - 1) < 0) {
296 pr_debug("fsl-pq-mdio: invalid UCC ID in node %s\n",
301 pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id);
302 found_mii_master = true;
308 static const struct of_device_id fsl_pq_mdio_match[] = {
309 #if IS_ENABLED(CONFIG_GIANFAR)
311 .compatible = "fsl,gianfar-tbi",
312 .data = &(struct fsl_pq_mdio_data) {
314 .get_tbipa = get_gfar_tbipa_from_mii,
318 .compatible = "fsl,gianfar-mdio",
319 .data = &(struct fsl_pq_mdio_data) {
321 .get_tbipa = get_gfar_tbipa_from_mii,
326 .compatible = "gianfar",
327 .data = &(struct fsl_pq_mdio_data) {
328 .mii_offset = offsetof(struct fsl_pq_mdio, mii),
329 .get_tbipa = get_gfar_tbipa_from_mdio,
333 .compatible = "fsl,etsec2-tbi",
334 .data = &(struct fsl_pq_mdio_data) {
335 .mii_offset = offsetof(struct fsl_pq_mdio, mii),
336 .get_tbipa = get_etsec_tbipa,
340 .compatible = "fsl,etsec2-mdio",
341 .data = &(struct fsl_pq_mdio_data) {
342 .mii_offset = offsetof(struct fsl_pq_mdio, mii),
343 .get_tbipa = get_etsec_tbipa,
347 #if IS_ENABLED(CONFIG_UCC_GETH)
349 .compatible = "fsl,ucc-mdio",
350 .data = &(struct fsl_pq_mdio_data) {
352 .get_tbipa = get_ucc_tbipa,
353 .ucc_configure = ucc_configure,
357 /* Legacy UCC MDIO node */
359 .compatible = "ucc_geth_phy",
360 .data = &(struct fsl_pq_mdio_data) {
362 .get_tbipa = get_ucc_tbipa,
363 .ucc_configure = ucc_configure,
367 /* No Kconfig option for Fman support yet */
369 .compatible = "fsl,fman-mdio",
370 .data = &(struct fsl_pq_mdio_data) {
372 /* Fman TBI operations are handled elsewhere */
378 MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
380 static int fsl_pq_mdio_probe(struct platform_device *pdev)
382 const struct of_device_id *id =
383 of_match_device(fsl_pq_mdio_match, &pdev->dev);
384 const struct fsl_pq_mdio_data *data;
385 struct device_node *np = pdev->dev.of_node;
387 struct device_node *tbi;
388 struct fsl_pq_mdio_priv *priv;
389 struct mii_bus *new_bus;
393 dev_err(&pdev->dev, "Failed to match device\n");
399 dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible);
401 new_bus = mdiobus_alloc_size(sizeof(*priv));
405 priv = new_bus->priv;
406 new_bus->name = "Freescale PowerQUICC MII Bus",
407 new_bus->read = &fsl_pq_mdio_read;
408 new_bus->write = &fsl_pq_mdio_write;
409 new_bus->reset = &fsl_pq_mdio_reset;
411 err = of_address_to_resource(np, 0, &res);
413 dev_err(&pdev->dev, "could not obtain address information\n");
417 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name,
418 (unsigned long long)res.start);
420 priv->map = of_iomap(np, 0);
427 * Some device tree nodes represent only the MII registers, and
428 * others represent the MAC and MII registers. The 'mii_offset' field
429 * contains the offset of the MII registers inside the mapped register
432 if (data->mii_offset > resource_size(&res)) {
433 dev_err(&pdev->dev, "invalid register map\n");
437 priv->regs = priv->map + data->mii_offset;
439 new_bus->parent = &pdev->dev;
440 platform_set_drvdata(pdev, new_bus);
442 if (data->get_tbipa) {
443 for_each_child_of_node(np, tbi) {
444 if (strcmp(tbi->type, "tbi-phy") == 0) {
445 dev_dbg(&pdev->dev, "found TBI PHY node %s\n",
446 strrchr(tbi->full_name, '/') + 1);
452 const u32 *prop = of_get_property(tbi, "reg", NULL);
453 uint32_t __iomem *tbipa;
457 "missing 'reg' property in node %s\n",
463 tbipa = data->get_tbipa(priv->map);
466 * Add consistency check to make sure TBI is contained
467 * within the mapped range (not because we would get a
468 * segfault, rather to catch bugs in computing TBI
469 * address). Print error message but continue anyway.
471 if ((void *)tbipa > priv->map + resource_size(&res) - 4)
472 dev_err(&pdev->dev, "invalid register map (should be at least 0x%04zx to contain TBI address)\n",
473 ((void *)tbipa - priv->map) + 4);
475 iowrite32be(be32_to_cpup(prop), tbipa);
479 if (data->ucc_configure)
480 data->ucc_configure(res.start, res.end);
482 err = of_mdiobus_register(new_bus, np);
484 dev_err(&pdev->dev, "cannot register %s as MDIO bus\n",
501 static int fsl_pq_mdio_remove(struct platform_device *pdev)
503 struct device *device = &pdev->dev;
504 struct mii_bus *bus = dev_get_drvdata(device);
505 struct fsl_pq_mdio_priv *priv = bus->priv;
507 mdiobus_unregister(bus);
515 static struct platform_driver fsl_pq_mdio_driver = {
517 .name = "fsl-pq_mdio",
518 .of_match_table = fsl_pq_mdio_match,
520 .probe = fsl_pq_mdio_probe,
521 .remove = fsl_pq_mdio_remove,
524 module_platform_driver(fsl_pq_mdio_driver);
526 MODULE_LICENSE("GPL");