drivers/net/ethernet/freescale/fman/fman_dtsec.c

   1 /*
   2  * Copyright 2008-2015 Freescale Semiconductor Inc.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are met:
   6  *     * Redistributions of source code must retain the above copyright
   7  *       notice, this list of conditions and the following disclaimer.
   8  *     * Redistributions in binary form must reproduce the above copyright
   9  *       notice, this list of conditions and the following disclaimer in the
  10  *       documentation and/or other materials provided with the distribution.
  11  *     * Neither the name of Freescale Semiconductor nor the
  12  *       names of its contributors may be used to endorse or promote products
  13  *       derived from this software without specific prior written permission.
  14  *
  15  *
  16  * ALTERNATIVELY, this software may be distributed under the terms of the
  17  * GNU General Public License ("GPL") as published by the Free Software
  18  * Foundation, either version 2 of that License or (at your option) any
  19  * later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  22  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  24  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  34
  35 #include "fman_dtsec.h"
  36 #include "fman.h"
  37
  38 #include <linux/slab.h>
  39 #include <linux/bitrev.h>
  40 #include <linux/io.h>
  41 #include <linux/delay.h>
  42 #include <linux/phy.h>
  43 #include <linux/crc32.h>
  44 #include <linux/of_mdio.h>
  45 #include <linux/mii.h>
  46
  47 /* TBI register addresses */
  48 #define MII_TBICON              0x11
  49
  50 /* TBICON register bit fields */
  51 #define TBICON_SOFT_RESET       0x8000  /* Soft reset */
  52 #define TBICON_DISABLE_RX_DIS   0x2000  /* Disable receive disparity */
  53 #define TBICON_DISABLE_TX_DIS   0x1000  /* Disable transmit disparity */
  54 #define TBICON_AN_SENSE         0x0100  /* Auto-negotiation sense enable */
  55 #define TBICON_CLK_SELECT       0x0020  /* Clock select */
  56 #define TBICON_MI_MODE          0x0010  /* GMII mode (TBI if not set) */
  57
  58 #define TBIANA_SGMII            0x4001
  59 #define TBIANA_1000X            0x01a0
  60
  61 /* Interrupt Mask Register (IMASK) */
  62 #define DTSEC_IMASK_BREN        0x80000000
  63 #define DTSEC_IMASK_RXCEN       0x40000000
  64 #define DTSEC_IMASK_MSROEN      0x04000000
  65 #define DTSEC_IMASK_GTSCEN      0x02000000
  66 #define DTSEC_IMASK_BTEN        0x01000000
  67 #define DTSEC_IMASK_TXCEN       0x00800000
  68 #define DTSEC_IMASK_TXEEN       0x00400000
  69 #define DTSEC_IMASK_LCEN        0x00040000
  70 #define DTSEC_IMASK_CRLEN       0x00020000
  71 #define DTSEC_IMASK_XFUNEN      0x00010000
  72 #define DTSEC_IMASK_ABRTEN      0x00008000
  73 #define DTSEC_IMASK_IFERREN     0x00004000
  74 #define DTSEC_IMASK_MAGEN       0x00000800
  75 #define DTSEC_IMASK_MMRDEN      0x00000400
  76 #define DTSEC_IMASK_MMWREN      0x00000200
  77 #define DTSEC_IMASK_GRSCEN      0x00000100
  78 #define DTSEC_IMASK_TDPEEN      0x00000002
  79 #define DTSEC_IMASK_RDPEEN      0x00000001
  80
  81 #define DTSEC_EVENTS_MASK               \
  82          ((u32)(DTSEC_IMASK_BREN    |   \
  83                 DTSEC_IMASK_RXCEN   |   \
  84                 DTSEC_IMASK_BTEN    |   \
  85                 DTSEC_IMASK_TXCEN   |   \
  86                 DTSEC_IMASK_TXEEN   |   \
  87                 DTSEC_IMASK_ABRTEN  |   \
  88                 DTSEC_IMASK_LCEN    |   \
  89                 DTSEC_IMASK_CRLEN   |   \
  90                 DTSEC_IMASK_XFUNEN  |   \
  91                 DTSEC_IMASK_IFERREN |   \
  92                 DTSEC_IMASK_MAGEN   |   \
  93                 DTSEC_IMASK_TDPEEN  |   \
  94                 DTSEC_IMASK_RDPEEN))
  95
  96 /* dtsec timestamp event bits */
  97 #define TMR_PEMASK_TSREEN       0x00010000
  98 #define TMR_PEVENT_TSRE         0x00010000
  99
 100 /* Group address bit indication */
 101 #define MAC_GROUP_ADDRESS       0x0000010000000000ULL
 102
 103 /* Defaults */
 104 #define DEFAULT_HALFDUP_RETRANSMIT              0xf
 105 #define DEFAULT_HALFDUP_COLL_WINDOW             0x37
 106 #define DEFAULT_TX_PAUSE_TIME                   0xf000
 107 #define DEFAULT_RX_PREPEND                      0
 108 #define DEFAULT_PREAMBLE_LEN                    7
 109 #define DEFAULT_TX_PAUSE_TIME_EXTD              0
 110 #define DEFAULT_NON_BACK_TO_BACK_IPG1           0x40
 111 #define DEFAULT_NON_BACK_TO_BACK_IPG2           0x60
 112 #define DEFAULT_MIN_IFG_ENFORCEMENT             0x50
 113 #define DEFAULT_BACK_TO_BACK_IPG                0x60
 114 #define DEFAULT_MAXIMUM_FRAME                   0x600
 115
 116 /* register related defines (bits, field offsets..) */
 117 #define DTSEC_ID2_INT_REDUCED_OFF       0x00010000
 118
 119 #define DTSEC_ECNTRL_GMIIM              0x00000040
 120 #define DTSEC_ECNTRL_TBIM               0x00000020
 121 #define DTSEC_ECNTRL_SGMIIM             0x00000002
 122 #define DTSEC_ECNTRL_RPM                0x00000010
 123 #define DTSEC_ECNTRL_R100M              0x00000008
 124 #define DTSEC_ECNTRL_QSGMIIM            0x00000001
 125
 126 #define DTSEC_TCTRL_GTS                 0x00000020
 127
 128 #define RCTRL_PAL_MASK                  0x001f0000
 129 #define RCTRL_PAL_SHIFT                 16
 130 #define RCTRL_GHTX                      0x00000400
 131 #define RCTRL_GRS                       0x00000020
 132 #define RCTRL_MPROM                     0x00000008
 133 #define RCTRL_RSF                       0x00000004
 134 #define RCTRL_UPROM                     0x00000001
 135
 136 #define MACCFG1_SOFT_RESET              0x80000000
 137 #define MACCFG1_RX_FLOW                 0x00000020
 138 #define MACCFG1_TX_FLOW                 0x00000010
 139 #define MACCFG1_TX_EN                   0x00000001
 140 #define MACCFG1_RX_EN                   0x00000004
 141
 142 #define MACCFG2_NIBBLE_MODE             0x00000100
 143 #define MACCFG2_BYTE_MODE               0x00000200
 144 #define MACCFG2_PAD_CRC_EN              0x00000004
 145 #define MACCFG2_FULL_DUPLEX             0x00000001
 146 #define MACCFG2_PREAMBLE_LENGTH_MASK    0x0000f000
 147 #define MACCFG2_PREAMBLE_LENGTH_SHIFT   12
 148
 149 #define IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT     24
 150 #define IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT     16
 151 #define IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT        8
 152
 153 #define IPGIFG_NON_BACK_TO_BACK_IPG_1   0x7F000000
 154 #define IPGIFG_NON_BACK_TO_BACK_IPG_2   0x007F0000
 155 #define IPGIFG_MIN_IFG_ENFORCEMENT      0x0000FF00
 156 #define IPGIFG_BACK_TO_BACK_IPG 0x0000007F
 157
 158 #define HAFDUP_EXCESS_DEFER                     0x00010000
 159 #define HAFDUP_COLLISION_WINDOW         0x000003ff
 160 #define HAFDUP_RETRANSMISSION_MAX_SHIFT 12
 161 #define HAFDUP_RETRANSMISSION_MAX               0x0000f000
 162
 163 #define NUM_OF_HASH_REGS        8       /* Number of hash table registers */
 164
 165 #define PTV_PTE_MASK            0xffff0000
 166 #define PTV_PT_MASK             0x0000ffff
 167 #define PTV_PTE_SHIFT           16
 168
 169 #define MAX_PACKET_ALIGNMENT            31
 170 #define MAX_INTER_PACKET_GAP            0x7f
 171 #define MAX_RETRANSMISSION              0x0f
 172 #define MAX_COLLISION_WINDOW            0x03ff
 173
 174 /* Hash table size (32 bits*8 regs) */
 175 #define DTSEC_HASH_TABLE_SIZE           256
 176 /* Extended Hash table size (32 bits*16 regs) */
 177 #define EXTENDED_HASH_TABLE_SIZE        512
 178
 179 /* dTSEC Memory Map registers */
 180 struct dtsec_regs {
 181         /* dTSEC General Control and Status Registers */
 182         u32 tsec_id;            /* 0x000 ETSEC_ID register */
 183         u32 tsec_id2;           /* 0x004 ETSEC_ID2 register */
 184         u32 ievent;             /* 0x008 Interrupt event register */
 185         u32 imask;              /* 0x00C Interrupt mask register */
 186         u32 reserved0010[1];
 187         u32 ecntrl;             /* 0x014 E control register */
 188         u32 ptv;                /* 0x018 Pause time value register */
 189         u32 tbipa;              /* 0x01C TBI PHY address register */
 190         u32 tmr_ctrl;           /* 0x020 Time-stamp Control register */
 191         u32 tmr_pevent;         /* 0x024 Time-stamp event register */
 192         u32 tmr_pemask;         /* 0x028 Timer event mask register */
 193         u32 reserved002c[5];
 194         u32 tctrl;              /* 0x040 Transmit control register */
 195         u32 reserved0044[3];
 196         u32 rctrl;              /* 0x050 Receive control register */
 197         u32 reserved0054[11];
 198         u32 igaddr[8];          /* 0x080-0x09C Individual/group address */
 199         u32 gaddr[8];           /* 0x0A0-0x0BC Group address registers 0-7 */
 200         u32 reserved00c0[16];
 201         u32 maccfg1;            /* 0x100 MAC configuration #1 */
 202         u32 maccfg2;            /* 0x104 MAC configuration #2 */
 203         u32 ipgifg;             /* 0x108 IPG/IFG */
 204         u32 hafdup;             /* 0x10C Half-duplex */
 205         u32 maxfrm;             /* 0x110 Maximum frame */
 206         u32 reserved0114[10];
 207         u32 ifstat;             /* 0x13C Interface status */
 208         u32 macstnaddr1;        /* 0x140 Station Address,part 1 */
 209         u32 macstnaddr2;        /* 0x144 Station Address,part 2 */
 210         struct {
 211                 u32 exact_match1;       /* octets 1-4 */
 212                 u32 exact_match2;       /* octets 5-6 */
 213         } macaddr[15];          /* 0x148-0x1BC mac exact match addresses 1-15 */
 214         u32 reserved01c0[16];
 215         u32 tr64;       /* 0x200 Tx and Rx 64 byte frame counter */
 216         u32 tr127;      /* 0x204 Tx and Rx 65 to 127 byte frame counter */
 217         u32 tr255;      /* 0x208 Tx and Rx 128 to 255 byte frame counter */
 218         u32 tr511;      /* 0x20C Tx and Rx 256 to 511 byte frame counter */
 219         u32 tr1k;       /* 0x210 Tx and Rx 512 to 1023 byte frame counter */
 220         u32 trmax;      /* 0x214 Tx and Rx 1024 to 1518 byte frame counter */
 221         u32 trmgv;
 222         /* 0x218 Tx and Rx 1519 to 1522 byte good VLAN frame count */
 223         u32 rbyt;       /* 0x21C receive byte counter */
 224         u32 rpkt;       /* 0x220 receive packet counter */
 225         u32 rfcs;       /* 0x224 receive FCS error counter */
 226         u32 rmca;       /* 0x228 RMCA Rx multicast packet counter */
 227         u32 rbca;       /* 0x22C Rx broadcast packet counter */
 228         u32 rxcf;       /* 0x230 Rx control frame packet counter */
 229         u32 rxpf;       /* 0x234 Rx pause frame packet counter */
 230         u32 rxuo;       /* 0x238 Rx unknown OP code counter */
 231         u32 raln;       /* 0x23C Rx alignment error counter */
 232         u32 rflr;       /* 0x240 Rx frame length error counter */
 233         u32 rcde;       /* 0x244 Rx code error counter */
 234         u32 rcse;       /* 0x248 Rx carrier sense error counter */
 235         u32 rund;       /* 0x24C Rx undersize packet counter */
 236         u32 rovr;       /* 0x250 Rx oversize packet counter */
 237         u32 rfrg;       /* 0x254 Rx fragments counter */
 238         u32 rjbr;       /* 0x258 Rx jabber counter */
 239         u32 rdrp;       /* 0x25C Rx drop */
 240         u32 tbyt;       /* 0x260 Tx byte counter */
 241         u32 tpkt;       /* 0x264 Tx packet counter */
 242         u32 tmca;       /* 0x268 Tx multicast packet counter */
 243         u32 tbca;       /* 0x26C Tx broadcast packet counter */
 244         u32 txpf;       /* 0x270 Tx pause control frame counter */
 245         u32 tdfr;       /* 0x274 Tx deferral packet counter */
 246         u32 tedf;       /* 0x278 Tx excessive deferral packet counter */
 247         u32 tscl;       /* 0x27C Tx single collision packet counter */
 248         u32 tmcl;       /* 0x280 Tx multiple collision packet counter */
 249         u32 tlcl;       /* 0x284 Tx late collision packet counter */
 250         u32 txcl;       /* 0x288 Tx excessive collision packet counter */
 251         u32 tncl;       /* 0x28C Tx total collision counter */
 252         u32 reserved0290[1];
 253         u32 tdrp;       /* 0x294 Tx drop frame counter */
 254         u32 tjbr;       /* 0x298 Tx jabber frame counter */
 255         u32 tfcs;       /* 0x29C Tx FCS error counter */
 256         u32 txcf;       /* 0x2A0 Tx control frame counter */
 257         u32 tovr;       /* 0x2A4 Tx oversize frame counter */
 258         u32 tund;       /* 0x2A8 Tx undersize frame counter */
 259         u32 tfrg;       /* 0x2AC Tx fragments frame counter */
 260         u32 car1;       /* 0x2B0 carry register one register* */
 261         u32 car2;       /* 0x2B4 carry register two register* */
 262         u32 cam1;       /* 0x2B8 carry register one mask register */
 263         u32 cam2;       /* 0x2BC carry register two mask register */
 264         u32 reserved02c0[848];
 265 };
 266
 267 /* struct dtsec_cfg - dTSEC configuration
 268  * Transmit half-duplex flow control, under software control for 10/100-Mbps
 269  * half-duplex media. If set, back pressure is applied to media by raising
 270  * carrier.
 271  * halfdup_retransmit:
 272  * Number of retransmission attempts following a collision.
 273  * If this is exceeded dTSEC aborts transmission due to excessive collisions.
 274  * The standard specifies the attempt limit to be 15.
 275  * halfdup_coll_window:
 276  * The number of bytes of the frame during which collisions may occur.
 277  * The default value of 55 corresponds to the frame byte at the end of the
 278  * standard 512-bit slot time window. If collisions are detected after this
 279  * byte, the late collision event is asserted and transmission of current
 280  * frame is aborted.
 281  * tx_pad_crc:
 282  * Pad and append CRC. If set, the MAC pads all ransmitted short frames and
 283  * appends a CRC to every frame regardless of padding requirement.
 284  * tx_pause_time:
 285  * Transmit pause time value. This pause value is used as part of the pause
 286  * frame to be sent when a transmit pause frame is initiated.
 287  * If set to 0 this disables transmission of pause frames.
 288  * preamble_len:
 289  * Length, in bytes, of the preamble field preceding each Ethernet
 290  * start-of-frame delimiter byte. The default value of 0x7 should be used in
 291  * order to guarantee reliable operation with IEEE 802.3 compliant hardware.
 292  * rx_prepend:
 293  * Packet alignment padding length. The specified number of bytes (1-31)
 294  * of zero padding are inserted before the start of each received frame.
 295  * For Ethernet, where optional preamble extraction is enabled, the padding
 296  * appears before the preamble, otherwise the padding precedes the
 297  * layer 2 header.
 298  *
 299  * This structure contains basic dTSEC configuration and must be passed to
 300  * init() function. A default set of configuration values can be
 301  * obtained by calling set_dflts().
 302  */
 303 struct dtsec_cfg {
 304         u16 halfdup_retransmit;
 305         u16 halfdup_coll_window;
 306         bool tx_pad_crc;
 307         u16 tx_pause_time;
 308         bool ptp_tsu_en;
 309         bool ptp_exception_en;
 310         u32 preamble_len;
 311         u32 rx_prepend;
 312         u16 tx_pause_time_extd;
 313         u16 maximum_frame;
 314         u32 non_back_to_back_ipg1;
 315         u32 non_back_to_back_ipg2;
 316         u32 min_ifg_enforcement;
 317         u32 back_to_back_ipg;
 318 };
 319
 320 struct fman_mac {
 321         /* pointer to dTSEC memory mapped registers */
 322         struct dtsec_regs __iomem *regs;
 323         /* MAC address of device */
 324         u64 addr;
 325         /* Ethernet physical interface */
 326         phy_interface_t phy_if;
 327         u16 max_speed;
 328         void *dev_id; /* device cookie used by the exception cbs */
 329         fman_mac_exception_cb *exception_cb;
 330         fman_mac_exception_cb *event_cb;
 331         /* Number of individual addresses in registers for this station */
 332         u8 num_of_ind_addr_in_regs;
 333         /* pointer to driver's global address hash table */
 334         struct eth_hash_t *multicast_addr_hash;
 335         /* pointer to driver's individual address hash table */
 336         struct eth_hash_t *unicast_addr_hash;
 337         u8 mac_id;
 338         u32 exceptions;
 339         bool ptp_tsu_enabled;
 340         bool en_tsu_err_exeption;
 341         struct dtsec_cfg *dtsec_drv_param;
 342         void *fm;
 343         struct fman_rev_info fm_rev_info;
 344         bool basex_if;
 345         struct phy_device *tbiphy;
 346 };
 347
 348 static void set_dflts(struct dtsec_cfg *cfg)
 349 {
 350         cfg->halfdup_retransmit = DEFAULT_HALFDUP_RETRANSMIT;
 351         cfg->halfdup_coll_window = DEFAULT_HALFDUP_COLL_WINDOW;
 352         cfg->tx_pad_crc = true;
 353         cfg->tx_pause_time = DEFAULT_TX_PAUSE_TIME;
 354         /* PHY address 0 is reserved (DPAA RM) */
 355         cfg->rx_prepend = DEFAULT_RX_PREPEND;
 356         cfg->ptp_tsu_en = true;
 357         cfg->ptp_exception_en = true;
 358         cfg->preamble_len = DEFAULT_PREAMBLE_LEN;
 359         cfg->tx_pause_time_extd = DEFAULT_TX_PAUSE_TIME_EXTD;
 360         cfg->non_back_to_back_ipg1 = DEFAULT_NON_BACK_TO_BACK_IPG1;
 361         cfg->non_back_to_back_ipg2 = DEFAULT_NON_BACK_TO_BACK_IPG2;
 362         cfg->min_ifg_enforcement = DEFAULT_MIN_IFG_ENFORCEMENT;
 363         cfg->back_to_back_ipg = DEFAULT_BACK_TO_BACK_IPG;
 364         cfg->maximum_frame = DEFAULT_MAXIMUM_FRAME;
 365 }
 366
 367 static int init(struct dtsec_regs __iomem *regs, struct dtsec_cfg *cfg,
 368                 phy_interface_t iface, u16 iface_speed, u8 *macaddr,
 369                 u32 exception_mask, u8 tbi_addr)
 370 {
 371         bool is_rgmii, is_sgmii, is_qsgmii;
 372         int i;
 373         u32 tmp;
 374
 375         /* Soft reset */
 376         iowrite32be(MACCFG1_SOFT_RESET, &regs->maccfg1);
 377         iowrite32be(0, &regs->maccfg1);
 378
 379         /* dtsec_id2 */
 380         tmp = ioread32be(&regs->tsec_id2);
 381
 382         /* check RGMII support */
 383         if (iface == PHY_INTERFACE_MODE_RGMII ||
 384             iface == PHY_INTERFACE_MODE_RMII)
 385                 if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
 386                         return -EINVAL;
 387
 388         if (iface == PHY_INTERFACE_MODE_SGMII ||
 389             iface == PHY_INTERFACE_MODE_MII)
 390                 if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
 391                         return -EINVAL;
 392
 393         is_rgmii = iface == PHY_INTERFACE_MODE_RGMII;
 394         is_sgmii = iface == PHY_INTERFACE_MODE_SGMII;
 395         is_qsgmii = iface == PHY_INTERFACE_MODE_QSGMII;
 396
 397         tmp = 0;
 398         if (is_rgmii || iface == PHY_INTERFACE_MODE_GMII)
 399                 tmp |= DTSEC_ECNTRL_GMIIM;
 400         if (is_sgmii)
 401                 tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM);
 402         if (is_qsgmii)
 403                 tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM |
 404                         DTSEC_ECNTRL_QSGMIIM);
 405         if (is_rgmii)
 406                 tmp |= DTSEC_ECNTRL_RPM;
 407         if (iface_speed == SPEED_100)
 408                 tmp |= DTSEC_ECNTRL_R100M;
 409
 410         iowrite32be(tmp, &regs->ecntrl);
 411
 412         tmp = 0;
 413
 414         if (cfg->tx_pause_time)
 415                 tmp |= cfg->tx_pause_time;
 416         if (cfg->tx_pause_time_extd)
 417                 tmp |= cfg->tx_pause_time_extd << PTV_PTE_SHIFT;
 418         iowrite32be(tmp, &regs->ptv);
 419
 420         tmp = 0;
 421         tmp |= (cfg->rx_prepend << RCTRL_PAL_SHIFT) & RCTRL_PAL_MASK;
 422         /* Accept short frames */
 423         tmp |= RCTRL_RSF;
 424
 425         iowrite32be(tmp, &regs->rctrl);
 426
 427         /* Assign a Phy Address to the TBI (TBIPA).
 428          * Done also in cases where TBI is not selected to avoid conflict with
 429          * the external PHY's Physical address
 430          */
 431         iowrite32be(tbi_addr, &regs->tbipa);
 432
 433         iowrite32be(0, &regs->tmr_ctrl);
 434
 435         if (cfg->ptp_tsu_en) {
 436                 tmp = 0;
 437                 tmp |= TMR_PEVENT_TSRE;
 438                 iowrite32be(tmp, &regs->tmr_pevent);
 439
 440                 if (cfg->ptp_exception_en) {
 441                         tmp = 0;
 442                         tmp |= TMR_PEMASK_TSREEN;
 443                         iowrite32be(tmp, &regs->tmr_pemask);
 444                 }
 445         }
 446
 447         tmp = 0;
 448         tmp |= MACCFG1_RX_FLOW;
 449         tmp |= MACCFG1_TX_FLOW;
 450         iowrite32be(tmp, &regs->maccfg1);
 451
 452         tmp = 0;
 453
 454         if (iface_speed < SPEED_1000)
 455                 tmp |= MACCFG2_NIBBLE_MODE;
 456         else if (iface_speed == SPEED_1000)
 457                 tmp |= MACCFG2_BYTE_MODE;
 458
 459         tmp |= (cfg->preamble_len << MACCFG2_PREAMBLE_LENGTH_SHIFT) &
 460                 MACCFG2_PREAMBLE_LENGTH_MASK;
 461         if (cfg->tx_pad_crc)
 462                 tmp |= MACCFG2_PAD_CRC_EN;
 463         /* Full Duplex */
 464         tmp |= MACCFG2_FULL_DUPLEX;
 465         iowrite32be(tmp, &regs->maccfg2);
 466
 467         tmp = (((cfg->non_back_to_back_ipg1 <<
 468                  IPGIFG_NON_BACK_TO_BACK_IPG_1_SHIFT)
 469                 & IPGIFG_NON_BACK_TO_BACK_IPG_1)
 470                | ((cfg->non_back_to_back_ipg2 <<
 471                    IPGIFG_NON_BACK_TO_BACK_IPG_2_SHIFT)
 472                  & IPGIFG_NON_BACK_TO_BACK_IPG_2)
 473                | ((cfg->min_ifg_enforcement << IPGIFG_MIN_IFG_ENFORCEMENT_SHIFT)
 474                  & IPGIFG_MIN_IFG_ENFORCEMENT)
 475                | (cfg->back_to_back_ipg & IPGIFG_BACK_TO_BACK_IPG));
 476         iowrite32be(tmp, &regs->ipgifg);
 477
 478         tmp = 0;
 479         tmp |= HAFDUP_EXCESS_DEFER;
 480         tmp |= ((cfg->halfdup_retransmit << HAFDUP_RETRANSMISSION_MAX_SHIFT)
 481                 & HAFDUP_RETRANSMISSION_MAX);
 482         tmp |= (cfg->halfdup_coll_window & HAFDUP_COLLISION_WINDOW);
 483
 484         iowrite32be(tmp, &regs->hafdup);
 485
 486         /* Initialize Maximum frame length */
 487         iowrite32be(cfg->maximum_frame, &regs->maxfrm);
 488
 489         iowrite32be(0xffffffff, &regs->cam1);
 490         iowrite32be(0xffffffff, &regs->cam2);
 491
 492         iowrite32be(exception_mask, &regs->imask);
 493
 494         iowrite32be(0xffffffff, &regs->ievent);
 495
 496         tmp = (u32)((macaddr[5] << 24) |
 497                     (macaddr[4] << 16) | (macaddr[3] << 8) | macaddr[2]);
 498         iowrite32be(tmp, &regs->macstnaddr1);
 499
 500         tmp = (u32)((macaddr[1] << 24) | (macaddr[0] << 16));
 501         iowrite32be(tmp, &regs->macstnaddr2);
 502
 503         /* HASH */
 504         for (i = 0; i < NUM_OF_HASH_REGS; i++) {
 505                 /* Initialize IADDRx */
 506                 iowrite32be(0, &regs->igaddr[i]);
 507                 /* Initialize GADDRx */
 508                 iowrite32be(0, &regs->gaddr[i]);
 509         }
 510
 511         return 0;
 512 }
 513
 514 static void set_mac_address(struct dtsec_regs __iomem *regs, u8 *adr)
 515 {
 516         u32 tmp;
 517
 518         tmp = (u32)((adr[5] << 24) |
 519                     (adr[4] << 16) | (adr[3] << 8) | adr[2]);
 520         iowrite32be(tmp, &regs->macstnaddr1);
 521
 522         tmp = (u32)((adr[1] << 24) | (adr[0] << 16));
 523         iowrite32be(tmp, &regs->macstnaddr2);
 524 }
 525
 526 static void set_bucket(struct dtsec_regs __iomem *regs, int bucket,
 527                        bool enable)
 528 {
 529         int reg_idx = (bucket >> 5) & 0xf;
 530         int bit_idx = bucket & 0x1f;
 531         u32 bit_mask = 0x80000000 >> bit_idx;
 532         u32 __iomem *reg;
 533
 534         if (reg_idx > 7)
 535                 reg = &regs->gaddr[reg_idx - 8];
 536         else
 537                 reg = &regs->igaddr[reg_idx];
 538
 539         if (enable)
 540                 iowrite32be(ioread32be(reg) | bit_mask, reg);
 541         else
 542                 iowrite32be(ioread32be(reg) & (~bit_mask), reg);
 543 }
 544
 545 static int check_init_parameters(struct fman_mac *dtsec)
 546 {
 547         if (dtsec->max_speed >= SPEED_10000) {
 548                 pr_err("1G MAC driver supports 1G or lower speeds\n");
 549                 return -EINVAL;
 550         }
 551         if (dtsec->addr == 0) {
 552                 pr_err("Ethernet MAC Must have a valid MAC Address\n");
 553                 return -EINVAL;
 554         }
 555         if ((dtsec->dtsec_drv_param)->rx_prepend >
 556             MAX_PACKET_ALIGNMENT) {
 557                 pr_err("packetAlignmentPadding can't be > than %d\n",
 558                        MAX_PACKET_ALIGNMENT);
 559                 return -EINVAL;
 560         }
 561         if (((dtsec->dtsec_drv_param)->non_back_to_back_ipg1 >
 562              MAX_INTER_PACKET_GAP) ||
 563             ((dtsec->dtsec_drv_param)->non_back_to_back_ipg2 >
 564              MAX_INTER_PACKET_GAP) ||
 565              ((dtsec->dtsec_drv_param)->back_to_back_ipg >
 566               MAX_INTER_PACKET_GAP)) {
 567                 pr_err("Inter packet gap can't be greater than %d\n",
 568                        MAX_INTER_PACKET_GAP);
 569                 return -EINVAL;
 570         }
 571         if ((dtsec->dtsec_drv_param)->halfdup_retransmit >
 572             MAX_RETRANSMISSION) {
 573                 pr_err("maxRetransmission can't be greater than %d\n",
 574                        MAX_RETRANSMISSION);
 575                 return -EINVAL;
 576         }
 577         if ((dtsec->dtsec_drv_param)->halfdup_coll_window >
 578             MAX_COLLISION_WINDOW) {
 579                 pr_err("collisionWindow can't be greater than %d\n",
 580                        MAX_COLLISION_WINDOW);
 581                 return -EINVAL;
 582         /* If Auto negotiation process is disabled, need to set up the PHY
 583          * using the MII Management Interface
 584          */
 585         }
 586         if (!dtsec->exception_cb) {
 587                 pr_err("uninitialized exception_cb\n");
 588                 return -EINVAL;
 589         }
 590         if (!dtsec->event_cb) {
 591                 pr_err("uninitialized event_cb\n");
 592                 return -EINVAL;
 593         }
 594
 595         return 0;
 596 }
 597
 598 static int get_exception_flag(enum fman_mac_exceptions exception)
 599 {
 600         u32 bit_mask;
 601
 602         switch (exception) {
 603         case FM_MAC_EX_1G_BAB_RX:
 604                 bit_mask = DTSEC_IMASK_BREN;
 605                 break;
 606         case FM_MAC_EX_1G_RX_CTL:
 607                 bit_mask = DTSEC_IMASK_RXCEN;
 608                 break;
 609         case FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET:
 610                 bit_mask = DTSEC_IMASK_GTSCEN;
 611                 break;
 612         case FM_MAC_EX_1G_BAB_TX:
 613                 bit_mask = DTSEC_IMASK_BTEN;
 614                 break;
 615         case FM_MAC_EX_1G_TX_CTL:
 616                 bit_mask = DTSEC_IMASK_TXCEN;
 617                 break;
 618         case FM_MAC_EX_1G_TX_ERR:
 619                 bit_mask = DTSEC_IMASK_TXEEN;
 620                 break;
 621         case FM_MAC_EX_1G_LATE_COL:
 622                 bit_mask = DTSEC_IMASK_LCEN;
 623                 break;
 624         case FM_MAC_EX_1G_COL_RET_LMT:
 625                 bit_mask = DTSEC_IMASK_CRLEN;
 626                 break;
 627         case FM_MAC_EX_1G_TX_FIFO_UNDRN:
 628                 bit_mask = DTSEC_IMASK_XFUNEN;
 629                 break;
 630         case FM_MAC_EX_1G_MAG_PCKT:
 631                 bit_mask = DTSEC_IMASK_MAGEN;
 632                 break;
 633         case FM_MAC_EX_1G_MII_MNG_RD_COMPLET:
 634                 bit_mask = DTSEC_IMASK_MMRDEN;
 635                 break;
 636         case FM_MAC_EX_1G_MII_MNG_WR_COMPLET:
 637                 bit_mask = DTSEC_IMASK_MMWREN;
 638                 break;
 639         case FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET:
 640                 bit_mask = DTSEC_IMASK_GRSCEN;
 641                 break;
 642         case FM_MAC_EX_1G_DATA_ERR:
 643                 bit_mask = DTSEC_IMASK_TDPEEN;
 644                 break;
 645         case FM_MAC_EX_1G_RX_MIB_CNT_OVFL:
 646                 bit_mask = DTSEC_IMASK_MSROEN;
 647                 break;
 648         default:
 649                 bit_mask = 0;
 650                 break;
 651         }
 652
 653         return bit_mask;
 654 }
 655
 656 static bool is_init_done(struct dtsec_cfg *dtsec_drv_params)
 657 {
 658         /* Checks if dTSEC driver parameters were initialized */
 659         if (!dtsec_drv_params)
 660                 return true;
 661
 662         return false;
 663 }
 664
 665 static u16 dtsec_get_max_frame_length(struct fman_mac *dtsec)
 666 {
 667         struct dtsec_regs __iomem *regs = dtsec->regs;
 668
 669         if (is_init_done(dtsec->dtsec_drv_param))
 670                 return 0;
 671
 672         return (u16)ioread32be(&regs->maxfrm);
 673 }
 674
 675 static void dtsec_isr(void *handle)
 676 {
 677         struct fman_mac *dtsec = (struct fman_mac *)handle;
 678         struct dtsec_regs __iomem *regs = dtsec->regs;
 679         u32 event;
 680
 681         /* do not handle MDIO events */
 682         event = ioread32be(&regs->ievent) &
 683                 (u32)(~(DTSEC_IMASK_MMRDEN | DTSEC_IMASK_MMWREN));
 684
 685         event &= ioread32be(&regs->imask);
 686
 687         iowrite32be(event, &regs->ievent);
 688
 689         if (event & DTSEC_IMASK_BREN)
 690                 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_BAB_RX);
 691         if (event & DTSEC_IMASK_RXCEN)
 692                 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_RX_CTL);
 693         if (event & DTSEC_IMASK_GTSCEN)
 694                 dtsec->exception_cb(dtsec->dev_id,
 695                                     FM_MAC_EX_1G_GRATEFUL_TX_STP_COMPLET);
 696         if (event & DTSEC_IMASK_BTEN)
 697                 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_BAB_TX);
 698         if (event & DTSEC_IMASK_TXCEN)
 699                 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_TX_CTL);
 700         if (event & DTSEC_IMASK_TXEEN)
 701                 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_TX_ERR);
 702         if (event & DTSEC_IMASK_LCEN)
 703                 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_LATE_COL);
 704         if (event & DTSEC_IMASK_CRLEN)
 705                 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_COL_RET_LMT);
 706         if (event & DTSEC_IMASK_XFUNEN) {
 707                 /* FM_TX_LOCKUP_ERRATA_DTSEC6 Errata workaround */
 708                 if (dtsec->fm_rev_info.major == 2) {
 709                         u32 tpkt1, tmp_reg1, tpkt2, tmp_reg2, i;
 710                         /* a. Write 0x00E0_0C00 to DTSEC_ID
 711                          *      This is a read only register
 712                          * b. Read and save the value of TPKT
 713                          */
 714                         tpkt1 = ioread32be(&regs->tpkt);
 715
 716                         /* c. Read the register at dTSEC address offset 0x32C */
 717                         tmp_reg1 = ioread32be(&regs->reserved02c0[27]);
 718
 719                         /* d. Compare bits [9:15] to bits [25:31] of the
 720                          * register at address offset 0x32C.
 721                          */
 722                         if ((tmp_reg1 & 0x007F0000) !=
 723                                 (tmp_reg1 & 0x0000007F)) {
 724                                 /* If they are not equal, save the value of
 725                                  * this register and wait for at least
 726                                  * MAXFRM*16 ns
 727                                  */
 728                                 usleep_range((u32)(min
 729                                         (dtsec_get_max_frame_length(dtsec) *
 730                                         16 / 1000, 1)), (u32)
 731                                         (min(dtsec_get_max_frame_length
 732                                         (dtsec) * 16 / 1000, 1) + 1));
 733                         }
 734
 735                         /* e. Read and save TPKT again and read the register
 736                          * at dTSEC address offset 0x32C again
 737                          */
 738                         tpkt2 = ioread32be(&regs->tpkt);
 739                         tmp_reg2 = ioread32be(&regs->reserved02c0[27]);
 740
 741                         /* f. Compare the value of TPKT saved in step b to
 742                          * value read in step e. Also compare bits [9:15] of
 743                          * the register at offset 0x32C saved in step d to the
 744                          * value of bits [9:15] saved in step e. If the two
 745                          * registers values are unchanged, then the transmit
 746                          * portion of the dTSEC controller is locked up and
 747                          * the user should proceed to the recover sequence.
 748                          */
 749                         if ((tpkt1 == tpkt2) && ((tmp_reg1 & 0x007F0000) ==
 750                                 (tmp_reg2 & 0x007F0000))) {
 751                                 /* recover sequence */
 752
 753                                 /* a.Write a 1 to RCTRL[GRS] */
 754
 755                                 iowrite32be(ioread32be(&regs->rctrl) |
 756                                             RCTRL_GRS, &regs->rctrl);
 757
 758                                 /* b.Wait until IEVENT[GRSC]=1, or at least
 759                                  * 100 us has elapsed.
 760                                  */
 761                                 for (i = 0; i < 100; i++) {
 762                                         if (ioread32be(&regs->ievent) &
 763                                             DTSEC_IMASK_GRSCEN)
 764                                                 break;
 765                                         udelay(1);
 766                                 }
 767                                 if (ioread32be(&regs->ievent) &
 768                                     DTSEC_IMASK_GRSCEN)
 769                                         iowrite32be(DTSEC_IMASK_GRSCEN,
 770                                                     &regs->ievent);
 771                                 else
 772                                         pr_debug("Rx lockup due to Tx lockup\n");
 773
 774                                 /* c.Write a 1 to bit n of FM_RSTC
 775                                  * (offset 0x0CC of FPM)
 776                                  */
 777                                 fman_reset_mac(dtsec->fm, dtsec->mac_id);
 778
 779                                 /* d.Wait 4 Tx clocks (32 ns) */
 780                                 udelay(1);
 781
 782                                 /* e.Write a 0 to bit n of FM_RSTC. */
 783                                 /* cleared by FMAN
 784                                  */
 785                         }
 786                 }
 787
 788                 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_TX_FIFO_UNDRN);
 789         }
 790         if (event & DTSEC_IMASK_MAGEN)
 791                 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_MAG_PCKT);
 792         if (event & DTSEC_IMASK_GRSCEN)
 793                 dtsec->exception_cb(dtsec->dev_id,
 794                                     FM_MAC_EX_1G_GRATEFUL_RX_STP_COMPLET);
 795         if (event & DTSEC_IMASK_TDPEEN)
 796                 dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_DATA_ERR);
 797         if (event & DTSEC_IMASK_RDPEEN)
 798                 dtsec->exception_cb(dtsec->dev_id, FM_MAC_1G_RX_DATA_ERR);
 799
 800         /* masked interrupts */
 801         WARN_ON(event & DTSEC_IMASK_ABRTEN);
 802         WARN_ON(event & DTSEC_IMASK_IFERREN);
 803 }
 804
 805 static void dtsec_1588_isr(void *handle)
 806 {
 807         struct fman_mac *dtsec = (struct fman_mac *)handle;
 808         struct dtsec_regs __iomem *regs = dtsec->regs;
 809         u32 event;
 810
 811         if (dtsec->ptp_tsu_enabled) {
 812                 event = ioread32be(&regs->tmr_pevent);
 813                 event &= ioread32be(&regs->tmr_pemask);
 814
 815                 if (event) {
 816                         iowrite32be(event, &regs->tmr_pevent);
 817                         WARN_ON(event & TMR_PEVENT_TSRE);
 818                         dtsec->exception_cb(dtsec->dev_id,
 819                                             FM_MAC_EX_1G_1588_TS_RX_ERR);
 820                 }
 821         }
 822 }
 823
 824 static void free_init_resources(struct fman_mac *dtsec)
 825 {
 826         fman_unregister_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id,
 827                              FMAN_INTR_TYPE_ERR);
 828         fman_unregister_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id,
 829                              FMAN_INTR_TYPE_NORMAL);
 830
 831         /* release the driver's group hash table */
 832         free_hash_table(dtsec->multicast_addr_hash);
 833         dtsec->multicast_addr_hash = NULL;
 834
 835         /* release the driver's individual hash table */
 836         free_hash_table(dtsec->unicast_addr_hash);
 837         dtsec->unicast_addr_hash = NULL;
 838 }
 839
 840 int dtsec_cfg_max_frame_len(struct fman_mac *dtsec, u16 new_val)
 841 {
 842         if (is_init_done(dtsec->dtsec_drv_param))
 843                 return -EINVAL;
 844
 845         dtsec->dtsec_drv_param->maximum_frame = new_val;
 846
 847         return 0;
 848 }
 849
 850 int dtsec_cfg_pad_and_crc(struct fman_mac *dtsec, bool new_val)
 851 {
 852         if (is_init_done(dtsec->dtsec_drv_param))
 853                 return -EINVAL;
 854
 855         dtsec->dtsec_drv_param->tx_pad_crc = new_val;
 856
 857         return 0;
 858 }
 859
 860 int dtsec_enable(struct fman_mac *dtsec, enum comm_mode mode)
 861 {
 862         struct dtsec_regs __iomem *regs = dtsec->regs;
 863         u32 tmp;
 864
 865         if (!is_init_done(dtsec->dtsec_drv_param))
 866                 return -EINVAL;
 867
 868         /* Enable */
 869         tmp = ioread32be(&regs->maccfg1);
 870         if (mode & COMM_MODE_RX)
 871                 tmp |= MACCFG1_RX_EN;
 872         if (mode & COMM_MODE_TX)
 873                 tmp |= MACCFG1_TX_EN;
 874
 875         iowrite32be(tmp, &regs->maccfg1);
 876
 877         /* Graceful start - clear the graceful receive stop bit */
 878         if (mode & COMM_MODE_TX)
 879                 iowrite32be(ioread32be(&regs->tctrl) & ~DTSEC_TCTRL_GTS,
 880                             &regs->tctrl);
 881         if (mode & COMM_MODE_RX)
 882                 iowrite32be(ioread32be(&regs->rctrl) & ~RCTRL_GRS,
 883                             &regs->rctrl);
 884
 885         return 0;
 886 }
 887
 888 int dtsec_disable(struct fman_mac *dtsec, enum comm_mode mode)
 889 {
 890         struct dtsec_regs __iomem *regs = dtsec->regs;
 891         u32 tmp;
 892
 893         if (!is_init_done(dtsec->dtsec_drv_param))
 894                 return -EINVAL;
 895
 896         /* Gracefull stop - Assert the graceful transmit stop bit */
 897         if (mode & COMM_MODE_RX) {
 898                 tmp = ioread32be(&regs->rctrl) | RCTRL_GRS;
 899                 iowrite32be(tmp, &regs->rctrl);
 900
 901                 if (dtsec->fm_rev_info.major == 2)
 902                         usleep_range(100, 200);
 903                 else
 904                         udelay(10);
 905         }
 906
 907         if (mode & COMM_MODE_TX) {
 908                 if (dtsec->fm_rev_info.major == 2)
 909                         pr_debug("GTS not supported due to DTSEC_A004 errata.\n");
 910                 else
 911                         pr_debug("GTS not supported due to DTSEC_A0014 errata.\n");
 912         }
 913
 914         tmp = ioread32be(&regs->maccfg1);
 915         if (mode & COMM_MODE_RX)
 916                 tmp &= ~MACCFG1_RX_EN;
 917         if (mode & COMM_MODE_TX)
 918                 tmp &= ~MACCFG1_TX_EN;
 919
 920         iowrite32be(tmp, &regs->maccfg1);
 921
 922         return 0;
 923 }
 924
 925 int dtsec_set_tx_pause_frames(struct fman_mac *dtsec,
 926                               u8 __maybe_unused priority,
 927                               u16 pause_time, u16 __maybe_unused thresh_time)
 928 {
 929         struct dtsec_regs __iomem *regs = dtsec->regs;
 930         u32 ptv = 0;
 931
 932         if (!is_init_done(dtsec->dtsec_drv_param))
 933                 return -EINVAL;
 934
 935         if (pause_time) {
 936                 /* FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 Errata workaround */
 937                 if (dtsec->fm_rev_info.major == 2 && pause_time <= 320) {
 938                         pr_warn("pause-time: %d illegal.Should be > 320\n",
 939                                 pause_time);
 940                         return -EINVAL;
 941                 }
 942
 943                 ptv = ioread32be(&regs->ptv);
 944                 ptv &= PTV_PTE_MASK;
 945                 ptv |= pause_time & PTV_PT_MASK;
 946                 iowrite32be(ptv, &regs->ptv);
 947
 948                 /* trigger the transmission of a flow-control pause frame */
 949                 iowrite32be(ioread32be(&regs->maccfg1) | MACCFG1_TX_FLOW,
 950                             &regs->maccfg1);
 951         } else
 952                 iowrite32be(ioread32be(&regs->maccfg1) & ~MACCFG1_TX_FLOW,
 953                             &regs->maccfg1);
 954
 955         return 0;
 956 }
 957
 958 int dtsec_accept_rx_pause_frames(struct fman_mac *dtsec, bool en)
 959 {
 960         struct dtsec_regs __iomem *regs = dtsec->regs;
 961         u32 tmp;
 962
 963         if (!is_init_done(dtsec->dtsec_drv_param))
 964                 return -EINVAL;
 965
 966         tmp = ioread32be(&regs->maccfg1);
 967         if (en)
 968                 tmp |= MACCFG1_RX_FLOW;
 969         else
 970                 tmp &= ~MACCFG1_RX_FLOW;
 971         iowrite32be(tmp, &regs->maccfg1);
 972
 973         return 0;
 974 }
 975
 976 int dtsec_modify_mac_address(struct fman_mac *dtsec, enet_addr_t *enet_addr)
 977 {
 978         if (!is_init_done(dtsec->dtsec_drv_param))
 979                 return -EINVAL;
 980
 981         /* Initialize MAC Station Address registers (1 & 2)
 982          * Station address have to be swapped (big endian to little endian
 983          */
 984         dtsec->addr = ENET_ADDR_TO_UINT64(*enet_addr);
 985         set_mac_address(dtsec->regs, (u8 *)(*enet_addr));
 986
 987         return 0;
 988 }
 989
 990 int dtsec_add_hash_mac_address(struct fman_mac *dtsec, enet_addr_t *eth_addr)
 991 {
 992         struct dtsec_regs __iomem *regs = dtsec->regs;
 993         struct eth_hash_entry *hash_entry;
 994         u64 addr;
 995         s32 bucket;
 996         u32 crc = 0xFFFFFFFF;
 997         bool mcast, ghtx;
 998
 999         if (!is_init_done(dtsec->dtsec_drv_param))
1000                 return -EINVAL;
1001
1002         addr = ENET_ADDR_TO_UINT64(*eth_addr);
1003
1004         ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);
1005         mcast = (bool)((addr & MAC_GROUP_ADDRESS) ? true : false);
1006
1007         /* Cannot handle unicast mac addr when GHTX is on */
1008         if (ghtx && !mcast) {
1009                 pr_err("Could not compute hash bucket\n");
1010                 return -EINVAL;
1011         }
1012         crc = crc32_le(crc, (u8 *)eth_addr, ETH_ALEN);
1013         crc = bitrev32(crc);
1014
1015         /* considering the 9 highest order bits in crc H[8:0]:
1016          *if ghtx = 0 H[8:6] (highest order 3 bits) identify the hash register
1017          *and H[5:1] (next 5 bits) identify the hash bit
1018          *if ghts = 1 H[8:5] (highest order 4 bits) identify the hash register
1019          *and H[4:0] (next 5 bits) identify the hash bit.
1020          *
1021          *In bucket index output the low 5 bits identify the hash register
1022          *bit, while the higher 4 bits identify the hash register
1023          */
1024
1025         if (ghtx) {
1026                 bucket = (s32)((crc >> 23) & 0x1ff);
1027         } else {
1028                 bucket = (s32)((crc >> 24) & 0xff);
1029                 /* if !ghtx and mcast the bit must be set in gaddr instead of
1030                  *igaddr.
1031                  */
1032                 if (mcast)
1033                         bucket += 0x100;
1034         }
1035
1036         set_bucket(dtsec->regs, bucket, true);
1037
1038         /* Create element to be added to the driver hash table */
1039         hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC);
1040         if (!hash_entry)
1041                 return -ENOMEM;
1042         hash_entry->addr = addr;
1043         INIT_LIST_HEAD(&hash_entry->node);
1044
1045         if (addr & MAC_GROUP_ADDRESS)
1046                 /* Group Address */
1047                 list_add_tail(&hash_entry->node,
1048                               &dtsec->multicast_addr_hash->lsts[bucket]);
1049         else
1050                 list_add_tail(&hash_entry->node,
1051                               &dtsec->unicast_addr_hash->lsts[bucket]);
1052
1053         return 0;
1054 }
1055
1056 int dtsec_del_hash_mac_address(struct fman_mac *dtsec, enet_addr_t *eth_addr)
1057 {
1058         struct dtsec_regs __iomem *regs = dtsec->regs;
1059         struct list_head *pos;
1060         struct eth_hash_entry *hash_entry = NULL;
1061         u64 addr;
1062         s32 bucket;
1063         u32 crc = 0xFFFFFFFF;
1064         bool mcast, ghtx;
1065
1066         if (!is_init_done(dtsec->dtsec_drv_param))
1067                 return -EINVAL;
1068
1069         addr = ENET_ADDR_TO_UINT64(*eth_addr);
1070
1071         ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);
1072         mcast = (bool)((addr & MAC_GROUP_ADDRESS) ? true : false);
1073
1074         /* Cannot handle unicast mac addr when GHTX is on */
1075         if (ghtx && !mcast) {
1076                 pr_err("Could not compute hash bucket\n");
1077                 return -EINVAL;
1078         }
1079         crc = crc32_le(crc, (u8 *)eth_addr, ETH_ALEN);
1080         crc = bitrev32(crc);
1081
1082         if (ghtx) {
1083                 bucket = (s32)((crc >> 23) & 0x1ff);
1084         } else {
1085                 bucket = (s32)((crc >> 24) & 0xff);
1086                 /* if !ghtx and mcast the bit must be set
1087                  * in gaddr instead of igaddr.
1088                  */
1089                 if (mcast)
1090                         bucket += 0x100;
1091         }
1092
1093         if (addr & MAC_GROUP_ADDRESS) {
1094                 /* Group Address */
1095                 list_for_each(pos,
1096                               &dtsec->multicast_addr_hash->lsts[bucket]) {
1097                         hash_entry = ETH_HASH_ENTRY_OBJ(pos);
1098                         if (hash_entry && hash_entry->addr == addr) {
1099                                 list_del_init(&hash_entry->node);
1100                                 kfree(hash_entry);
1101                                 break;
1102                         }
1103                 }
1104                 if (list_empty(&dtsec->multicast_addr_hash->lsts[bucket]))
1105                         set_bucket(dtsec->regs, bucket, false);
1106         } else {
1107                 /* Individual Address */
1108                 list_for_each(pos,
1109                               &dtsec->unicast_addr_hash->lsts[bucket]) {
1110                         hash_entry = ETH_HASH_ENTRY_OBJ(pos);
1111                         if (hash_entry && hash_entry->addr == addr) {
1112                                 list_del_init(&hash_entry->node);
1113                                 kfree(hash_entry);
1114                                 break;
1115                         }
1116                 }
1117                 if (list_empty(&dtsec->unicast_addr_hash->lsts[bucket]))
1118                         set_bucket(dtsec->regs, bucket, false);
1119         }
1120
1121         /* address does not exist */
1122         WARN_ON(!hash_entry);
1123
1124         return 0;
1125 }
1126
1127 int dtsec_set_promiscuous(struct fman_mac *dtsec, bool new_val)
1128 {
1129         struct dtsec_regs __iomem *regs = dtsec->regs;
1130         u32 tmp;
1131
1132         if (!is_init_done(dtsec->dtsec_drv_param))
1133                 return -EINVAL;
1134
1135         /* Set unicast promiscuous */
1136         tmp = ioread32be(&regs->rctrl);
1137         if (new_val)
1138                 tmp |= RCTRL_UPROM;
1139         else
1140                 tmp &= ~RCTRL_UPROM;
1141
1142         iowrite32be(tmp, &regs->rctrl);
1143
1144         /* Set multicast promiscuous */
1145         tmp = ioread32be(&regs->rctrl);
1146         if (new_val)
1147                 tmp |= RCTRL_MPROM;
1148         else
1149                 tmp &= ~RCTRL_MPROM;
1150
1151         iowrite32be(tmp, &regs->rctrl);
1152
1153         return 0;
1154 }
1155
1156 int dtsec_adjust_link(struct fman_mac *dtsec, u16 speed)
1157 {
1158         struct dtsec_regs __iomem *regs = dtsec->regs;
1159         u32 tmp;
1160
1161         if (!is_init_done(dtsec->dtsec_drv_param))
1162                 return -EINVAL;
1163
1164         tmp = ioread32be(&regs->maccfg2);
1165
1166         /* Full Duplex */
1167         tmp |= MACCFG2_FULL_DUPLEX;
1168
1169         tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE);
1170         if (speed < SPEED_1000)
1171                 tmp |= MACCFG2_NIBBLE_MODE;
1172         else if (speed == SPEED_1000)
1173                 tmp |= MACCFG2_BYTE_MODE;
1174         iowrite32be(tmp, &regs->maccfg2);
1175
1176         tmp = ioread32be(&regs->ecntrl);
1177         if (speed == SPEED_100)
1178                 tmp |= DTSEC_ECNTRL_R100M;
1179         else
1180                 tmp &= ~DTSEC_ECNTRL_R100M;
1181         iowrite32be(tmp, &regs->ecntrl);
1182
1183         return 0;
1184 }
1185
1186 int dtsec_restart_autoneg(struct fman_mac *dtsec)
1187 {
1188         u16 tmp_reg16;
1189
1190         if (!is_init_done(dtsec->dtsec_drv_param))
1191                 return -EINVAL;
1192
1193         tmp_reg16 = phy_read(dtsec->tbiphy, MII_BMCR);
1194
1195         tmp_reg16 &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
1196         tmp_reg16 |= (BMCR_ANENABLE | BMCR_ANRESTART |
1197                       BMCR_FULLDPLX | BMCR_SPEED1000);
1198
1199         phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
1200
1201         return 0;
1202 }
1203
1204 int dtsec_get_version(struct fman_mac *dtsec, u32 *mac_version)
1205 {
1206         struct dtsec_regs __iomem *regs = dtsec->regs;
1207
1208         if (!is_init_done(dtsec->dtsec_drv_param))
1209                 return -EINVAL;
1210
1211         *mac_version = ioread32be(&regs->tsec_id);
1212
1213         return 0;
1214 }
1215
1216 int dtsec_set_exception(struct fman_mac *dtsec,
1217                         enum fman_mac_exceptions exception, bool enable)
1218 {
1219         struct dtsec_regs __iomem *regs = dtsec->regs;
1220         u32 bit_mask = 0;
1221
1222         if (!is_init_done(dtsec->dtsec_drv_param))
1223                 return -EINVAL;
1224
1225         if (exception != FM_MAC_EX_1G_1588_TS_RX_ERR) {
1226                 bit_mask = get_exception_flag(exception);
1227                 if (bit_mask) {
1228                         if (enable)
1229                                 dtsec->exceptions |= bit_mask;
1230                         else
1231                                 dtsec->exceptions &= ~bit_mask;
1232                 } else {
1233                         pr_err("Undefined exception\n");
1234                         return -EINVAL;
1235                 }
1236                 if (enable)
1237                         iowrite32be(ioread32be(&regs->imask) | bit_mask,
1238                                     &regs->imask);
1239                 else
1240                         iowrite32be(ioread32be(&regs->imask) & ~bit_mask,
1241                                     &regs->imask);
1242         } else {
1243                 if (!dtsec->ptp_tsu_enabled) {
1244                         pr_err("Exception valid for 1588 only\n");
1245                         return -EINVAL;
1246                 }
1247                 switch (exception) {
1248                 case FM_MAC_EX_1G_1588_TS_RX_ERR:
1249                         if (enable) {
1250                                 dtsec->en_tsu_err_exeption = true;
1251                                 iowrite32be(ioread32be(&regs->tmr_pemask) |
1252                                             TMR_PEMASK_TSREEN,
1253                                             &regs->tmr_pemask);
1254                         } else {
1255                                 dtsec->en_tsu_err_exeption = false;
1256                                 iowrite32be(ioread32be(&regs->tmr_pemask) &
1257                                             ~TMR_PEMASK_TSREEN,
1258                                             &regs->tmr_pemask);
1259                         }
1260                         break;
1261                 default:
1262                         pr_err("Undefined exception\n");
1263                         return -EINVAL;
1264                 }
1265         }
1266
1267         return 0;
1268 }
1269
1270 int dtsec_init(struct fman_mac *dtsec)
1271 {
1272         struct dtsec_regs __iomem *regs = dtsec->regs;
1273         struct dtsec_cfg *dtsec_drv_param;
1274         int err;
1275         u16 max_frm_ln;
1276         enet_addr_t eth_addr;
1277
1278         if (is_init_done(dtsec->dtsec_drv_param))
1279                 return -EINVAL;
1280
1281         if (DEFAULT_RESET_ON_INIT &&
1282             (fman_reset_mac(dtsec->fm, dtsec->mac_id) != 0)) {
1283                 pr_err("Can't reset MAC!\n");
1284                 return -EINVAL;
1285         }
1286
1287         err = check_init_parameters(dtsec);
1288         if (err)
1289                 return err;
1290
1291         dtsec_drv_param = dtsec->dtsec_drv_param;
1292
1293         MAKE_ENET_ADDR_FROM_UINT64(dtsec->addr, eth_addr);
1294
1295         err = init(dtsec->regs, dtsec_drv_param, dtsec->phy_if,
1296                    dtsec->max_speed, (u8 *)eth_addr, dtsec->exceptions,
1297                    dtsec->tbiphy->mdio.addr);
1298         if (err) {
1299                 free_init_resources(dtsec);
1300                 pr_err("DTSEC version doesn't support this i/f mode\n");
1301                 return err;
1302         }
1303
1304         if (dtsec->phy_if == PHY_INTERFACE_MODE_SGMII) {
1305                 u16 tmp_reg16;
1306
1307                 /* Configure the TBI PHY Control Register */
1308                 tmp_reg16 = TBICON_CLK_SELECT | TBICON_SOFT_RESET;
1309                 phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);
1310
1311                 tmp_reg16 = TBICON_CLK_SELECT;
1312                 phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);
1313
1314                 tmp_reg16 = (BMCR_RESET | BMCR_ANENABLE |
1315                              BMCR_FULLDPLX | BMCR_SPEED1000);
1316                 phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
1317
1318                 if (dtsec->basex_if)
1319                         tmp_reg16 = TBIANA_1000X;
1320                 else
1321                         tmp_reg16 = TBIANA_SGMII;
1322                 phy_write(dtsec->tbiphy, MII_ADVERTISE, tmp_reg16);
1323
1324                 tmp_reg16 = (BMCR_ANENABLE | BMCR_ANRESTART |
1325                              BMCR_FULLDPLX | BMCR_SPEED1000);
1326
1327                 phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
1328         }
1329
1330         /* Max Frame Length */
1331         max_frm_ln = (u16)ioread32be(&regs->maxfrm);
1332         err = fman_set_mac_max_frame(dtsec->fm, dtsec->mac_id, max_frm_ln);
1333         if (err) {
1334                 pr_err("Setting max frame length failed\n");
1335                 free_init_resources(dtsec);
1336                 return -EINVAL;
1337         }
1338
1339         dtsec->multicast_addr_hash =
1340         alloc_hash_table(EXTENDED_HASH_TABLE_SIZE);
1341         if (!dtsec->multicast_addr_hash) {
1342                 free_init_resources(dtsec);
1343                 pr_err("MC hash table is failed\n");
1344                 return -ENOMEM;
1345         }
1346
1347         dtsec->unicast_addr_hash = alloc_hash_table(DTSEC_HASH_TABLE_SIZE);
1348         if (!dtsec->unicast_addr_hash) {
1349                 free_init_resources(dtsec);
1350                 pr_err("UC hash table is failed\n");
1351                 return -ENOMEM;
1352         }
1353
1354         /* register err intr handler for dtsec to FPM (err) */
1355         fman_register_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id,
1356                            FMAN_INTR_TYPE_ERR, dtsec_isr, dtsec);
1357         /* register 1588 intr handler for TMR to FPM (normal) */
1358         fman_register_intr(dtsec->fm, FMAN_MOD_MAC, dtsec->mac_id,
1359                            FMAN_INTR_TYPE_NORMAL, dtsec_1588_isr, dtsec);
1360
1361         kfree(dtsec_drv_param);
1362         dtsec->dtsec_drv_param = NULL;
1363
1364         return 0;
1365 }
1366
1367 int dtsec_free(struct fman_mac *dtsec)
1368 {
1369         free_init_resources(dtsec);
1370
1371         kfree(dtsec->dtsec_drv_param);
1372         dtsec->dtsec_drv_param = NULL;
1373         kfree(dtsec);
1374
1375         return 0;
1376 }
1377
1378 struct fman_mac *dtsec_config(struct fman_mac_params *params)
1379 {
1380         struct fman_mac *dtsec;
1381         struct dtsec_cfg *dtsec_drv_param;
1382         void __iomem *base_addr;
1383
1384         base_addr = params->base_addr;
1385
1386         /* allocate memory for the UCC GETH data structure. */
1387         dtsec = kzalloc(sizeof(*dtsec), GFP_KERNEL);
1388         if (!dtsec)
1389                 return NULL;
1390
1391         /* allocate memory for the d_tsec driver parameters data structure. */
1392         dtsec_drv_param = kzalloc(sizeof(*dtsec_drv_param), GFP_KERNEL);
1393         if (!dtsec_drv_param)
1394                 goto err_dtsec;
1395
1396         /* Plant parameter structure pointer */
1397         dtsec->dtsec_drv_param = dtsec_drv_param;
1398
1399         set_dflts(dtsec_drv_param);
1400
1401         dtsec->regs = base_addr;
1402         dtsec->addr = ENET_ADDR_TO_UINT64(params->addr);
1403         dtsec->max_speed = params->max_speed;
1404         dtsec->phy_if = params->phy_if;
1405         dtsec->mac_id = params->mac_id;
1406         dtsec->exceptions = (DTSEC_IMASK_BREN   |
1407                              DTSEC_IMASK_RXCEN  |
1408                              DTSEC_IMASK_BTEN   |
1409                              DTSEC_IMASK_TXCEN  |
1410                              DTSEC_IMASK_TXEEN  |
1411                              DTSEC_IMASK_ABRTEN |
1412                              DTSEC_IMASK_LCEN   |
1413                              DTSEC_IMASK_CRLEN  |
1414                              DTSEC_IMASK_XFUNEN |
1415                              DTSEC_IMASK_IFERREN |
1416                              DTSEC_IMASK_MAGEN  |
1417                              DTSEC_IMASK_TDPEEN |
1418                              DTSEC_IMASK_RDPEEN);
1419         dtsec->exception_cb = params->exception_cb;
1420         dtsec->event_cb = params->event_cb;
1421         dtsec->dev_id = params->dev_id;
1422         dtsec->ptp_tsu_enabled = dtsec->dtsec_drv_param->ptp_tsu_en;
1423         dtsec->en_tsu_err_exeption = dtsec->dtsec_drv_param->ptp_exception_en;
1424
1425         dtsec->fm = params->fm;
1426         dtsec->basex_if = params->basex_if;
1427
1428         if (!params->internal_phy_node) {
1429                 pr_err("TBI PHY node is not available\n");
1430                 goto err_dtsec_drv_param;
1431         }
1432
1433         dtsec->tbiphy = of_phy_find_device(params->internal_phy_node);
1434         if (!dtsec->tbiphy) {
1435                 pr_err("of_phy_find_device (TBI PHY) failed\n");
1436                 goto err_dtsec_drv_param;
1437         }
1438
1439         put_device(&dtsec->tbiphy->mdio.dev);
1440
1441         /* Save FMan revision */
1442         fman_get_revision(dtsec->fm, &dtsec->fm_rev_info);
1443
1444         return dtsec;
1445
1446 err_dtsec_drv_param:
1447         kfree(dtsec_drv_param);
1448 err_dtsec:
1449         kfree(dtsec);
1450         return NULL;
1451 }