drivers/net/ethernet/freescale/fman/fman.c

   1 /*
   2  * Copyright 2008-2015 Freescale Semiconductor Inc.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions are met:
   6  *     * Redistributions of source code must retain the above copyright
   7  *       notice, this list of conditions and the following disclaimer.
   8  *     * Redistributions in binary form must reproduce the above copyright
   9  *       notice, this list of conditions and the following disclaimer in the
  10  *       documentation and/or other materials provided with the distribution.
  11  *     * Neither the name of Freescale Semiconductor nor the
  12  *       names of its contributors may be used to endorse or promote products
  13  *       derived from this software without specific prior written permission.
  14  *
  15  *
  16  * ALTERNATIVELY, this software may be distributed under the terms of the
  17  * GNU General Public License ("GPL") as published by the Free Software
  18  * Foundation, either version 2 of that License or (at your option) any
  19  * later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  22  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  24  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  34
  35 #include "fman.h"
  36 #include "fman_muram.h"
  37
  38 #include <linux/fsl/guts.h>
  39 #include <linux/slab.h>
  40 #include <linux/delay.h>
  41 #include <linux/module.h>
  42 #include <linux/of_platform.h>
  43 #include <linux/clk.h>
  44 #include <linux/of_address.h>
  45 #include <linux/of_irq.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/libfdt_env.h>
  48
  49 /* General defines */
  50 #define FMAN_LIODN_TBL                  64      /* size of LIODN table */
  51 #define MAX_NUM_OF_MACS                 10
  52 #define FM_NUM_OF_FMAN_CTRL_EVENT_REGS  4
  53 #define BASE_RX_PORTID                  0x08
  54 #define BASE_TX_PORTID                  0x28
  55
  56 /* Modules registers offsets */
  57 #define BMI_OFFSET              0x00080000
  58 #define QMI_OFFSET              0x00080400
  59 #define DMA_OFFSET              0x000C2000
  60 #define FPM_OFFSET              0x000C3000
  61 #define IMEM_OFFSET             0x000C4000
  62 #define CGP_OFFSET              0x000DB000
  63
  64 /* Exceptions bit map */
  65 #define EX_DMA_BUS_ERROR                0x80000000
  66 #define EX_DMA_READ_ECC                 0x40000000
  67 #define EX_DMA_SYSTEM_WRITE_ECC 0x20000000
  68 #define EX_DMA_FM_WRITE_ECC             0x10000000
  69 #define EX_FPM_STALL_ON_TASKS           0x08000000
  70 #define EX_FPM_SINGLE_ECC               0x04000000
  71 #define EX_FPM_DOUBLE_ECC               0x02000000
  72 #define EX_QMI_SINGLE_ECC               0x01000000
  73 #define EX_QMI_DEQ_FROM_UNKNOWN_PORTID  0x00800000
  74 #define EX_QMI_DOUBLE_ECC               0x00400000
  75 #define EX_BMI_LIST_RAM_ECC             0x00200000
  76 #define EX_BMI_STORAGE_PROFILE_ECC      0x00100000
  77 #define EX_BMI_STATISTICS_RAM_ECC       0x00080000
  78 #define EX_IRAM_ECC                     0x00040000
  79 #define EX_MURAM_ECC                    0x00020000
  80 #define EX_BMI_DISPATCH_RAM_ECC 0x00010000
  81 #define EX_DMA_SINGLE_PORT_ECC          0x00008000
  82
  83 /* DMA defines */
  84 /* masks */
  85 #define DMA_MODE_BER                    0x00200000
  86 #define DMA_MODE_ECC                    0x00000020
  87 #define DMA_MODE_SECURE_PROT            0x00000800
  88 #define DMA_MODE_AXI_DBG_MASK           0x0F000000
  89
  90 #define DMA_TRANSFER_PORTID_MASK        0xFF000000
  91 #define DMA_TRANSFER_TNUM_MASK          0x00FF0000
  92 #define DMA_TRANSFER_LIODN_MASK 0x00000FFF
  93
  94 #define DMA_STATUS_BUS_ERR              0x08000000
  95 #define DMA_STATUS_READ_ECC             0x04000000
  96 #define DMA_STATUS_SYSTEM_WRITE_ECC     0x02000000
  97 #define DMA_STATUS_FM_WRITE_ECC 0x01000000
  98 #define DMA_STATUS_FM_SPDAT_ECC 0x00080000
  99
 100 #define DMA_MODE_CACHE_OR_SHIFT         30
 101 #define DMA_MODE_AXI_DBG_SHIFT                  24
 102 #define DMA_MODE_CEN_SHIFT                      13
 103 #define DMA_MODE_CEN_MASK                       0x00000007
 104 #define DMA_MODE_DBG_SHIFT                      7
 105 #define DMA_MODE_AID_MODE_SHIFT         4
 106
 107 #define DMA_THRESH_COMMQ_SHIFT                  24
 108 #define DMA_THRESH_READ_INT_BUF_SHIFT           16
 109 #define DMA_THRESH_READ_INT_BUF_MASK            0x0000003f
 110 #define DMA_THRESH_WRITE_INT_BUF_MASK           0x0000003f
 111
 112 #define DMA_TRANSFER_PORTID_SHIFT               24
 113 #define DMA_TRANSFER_TNUM_SHIFT         16
 114
 115 #define DMA_CAM_SIZEOF_ENTRY                    0x40
 116 #define DMA_CAM_UNITS                           8
 117
 118 #define DMA_LIODN_SHIFT         16
 119 #define DMA_LIODN_BASE_MASK     0x00000FFF
 120
 121 /* FPM defines */
 122 #define FPM_EV_MASK_DOUBLE_ECC          0x80000000
 123 #define FPM_EV_MASK_STALL               0x40000000
 124 #define FPM_EV_MASK_SINGLE_ECC          0x20000000
 125 #define FPM_EV_MASK_RELEASE_FM          0x00010000
 126 #define FPM_EV_MASK_DOUBLE_ECC_EN       0x00008000
 127 #define FPM_EV_MASK_STALL_EN            0x00004000
 128 #define FPM_EV_MASK_SINGLE_ECC_EN       0x00002000
 129 #define FPM_EV_MASK_EXTERNAL_HALT       0x00000008
 130 #define FPM_EV_MASK_ECC_ERR_HALT        0x00000004
 131
 132 #define FPM_RAM_MURAM_ECC               0x00008000
 133 #define FPM_RAM_IRAM_ECC                0x00004000
 134 #define FPM_IRAM_ECC_ERR_EX_EN          0x00020000
 135 #define FPM_MURAM_ECC_ERR_EX_EN 0x00040000
 136 #define FPM_RAM_IRAM_ECC_EN             0x40000000
 137 #define FPM_RAM_RAMS_ECC_EN             0x80000000
 138 #define FPM_RAM_RAMS_ECC_EN_SRC_SEL     0x08000000
 139
 140 #define FPM_REV1_MAJOR_MASK             0x0000FF00
 141 #define FPM_REV1_MINOR_MASK             0x000000FF
 142
 143 #define FPM_DISP_LIMIT_SHIFT            24
 144
 145 #define FPM_PRT_FM_CTL1                 0x00000001
 146 #define FPM_PRT_FM_CTL2                 0x00000002
 147 #define FPM_PORT_FM_CTL_PORTID_SHIFT    24
 148 #define FPM_PRC_ORA_FM_CTL_SEL_SHIFT    16
 149
 150 #define FPM_THR1_PRS_SHIFT              24
 151 #define FPM_THR1_KG_SHIFT               16
 152 #define FPM_THR1_PLCR_SHIFT             8
 153 #define FPM_THR1_BMI_SHIFT              0
 154
 155 #define FPM_THR2_QMI_ENQ_SHIFT          24
 156 #define FPM_THR2_QMI_DEQ_SHIFT          0
 157 #define FPM_THR2_FM_CTL1_SHIFT          16
 158 #define FPM_THR2_FM_CTL2_SHIFT          8
 159
 160 #define FPM_EV_MASK_CAT_ERR_SHIFT       1
 161 #define FPM_EV_MASK_DMA_ERR_SHIFT       0
 162
 163 #define FPM_REV1_MAJOR_SHIFT            8
 164
 165 #define FPM_RSTC_FM_RESET               0x80000000
 166 #define FPM_RSTC_MAC0_RESET             0x40000000
 167 #define FPM_RSTC_MAC1_RESET             0x20000000
 168 #define FPM_RSTC_MAC2_RESET             0x10000000
 169 #define FPM_RSTC_MAC3_RESET             0x08000000
 170 #define FPM_RSTC_MAC8_RESET             0x04000000
 171 #define FPM_RSTC_MAC4_RESET             0x02000000
 172 #define FPM_RSTC_MAC5_RESET             0x01000000
 173 #define FPM_RSTC_MAC6_RESET             0x00800000
 174 #define FPM_RSTC_MAC7_RESET             0x00400000
 175 #define FPM_RSTC_MAC9_RESET             0x00200000
 176
 177 #define FPM_TS_INT_SHIFT                16
 178 #define FPM_TS_CTL_EN                   0x80000000
 179
 180 /* BMI defines */
 181 #define BMI_INIT_START                          0x80000000
 182 #define BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC     0x80000000
 183 #define BMI_ERR_INTR_EN_LIST_RAM_ECC            0x40000000
 184 #define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC      0x20000000
 185 #define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC        0x10000000
 186 #define BMI_NUM_OF_TASKS_MASK                   0x3F000000
 187 #define BMI_NUM_OF_EXTRA_TASKS_MASK             0x000F0000
 188 #define BMI_NUM_OF_DMAS_MASK                    0x00000F00
 189 #define BMI_NUM_OF_EXTRA_DMAS_MASK              0x0000000F
 190 #define BMI_FIFO_SIZE_MASK                      0x000003FF
 191 #define BMI_EXTRA_FIFO_SIZE_MASK                0x03FF0000
 192 #define BMI_CFG2_DMAS_MASK                      0x0000003F
 193 #define BMI_CFG2_TASKS_MASK                     0x0000003F
 194
 195 #define BMI_CFG2_TASKS_SHIFT            16
 196 #define BMI_CFG2_DMAS_SHIFT             0
 197 #define BMI_CFG1_FIFO_SIZE_SHIFT        16
 198 #define BMI_NUM_OF_TASKS_SHIFT          24
 199 #define BMI_EXTRA_NUM_OF_TASKS_SHIFT    16
 200 #define BMI_NUM_OF_DMAS_SHIFT           8
 201 #define BMI_EXTRA_NUM_OF_DMAS_SHIFT     0
 202
 203 #define BMI_FIFO_ALIGN                  0x100
 204
 205 #define BMI_EXTRA_FIFO_SIZE_SHIFT       16
 206
 207 /* QMI defines */
 208 #define QMI_CFG_ENQ_EN                  0x80000000
 209 #define QMI_CFG_DEQ_EN                  0x40000000
 210 #define QMI_CFG_EN_COUNTERS             0x10000000
 211 #define QMI_CFG_DEQ_MASK                0x0000003F
 212 #define QMI_CFG_ENQ_MASK                0x00003F00
 213 #define QMI_CFG_ENQ_SHIFT               8
 214
 215 #define QMI_ERR_INTR_EN_DOUBLE_ECC      0x80000000
 216 #define QMI_ERR_INTR_EN_DEQ_FROM_DEF    0x40000000
 217 #define QMI_INTR_EN_SINGLE_ECC          0x80000000
 218
 219 #define QMI_GS_HALT_NOT_BUSY            0x00000002
 220
 221 /* IRAM defines */
 222 #define IRAM_IADD_AIE                   0x80000000
 223 #define IRAM_READY                      0x80000000
 224
 225 /* Default values */
 226 #define DEFAULT_CATASTROPHIC_ERR                0
 227 #define DEFAULT_DMA_ERR                         0
 228 #define DEFAULT_AID_MODE                        FMAN_DMA_AID_OUT_TNUM
 229 #define DEFAULT_DMA_COMM_Q_LOW                  0x2A
 230 #define DEFAULT_DMA_COMM_Q_HIGH         0x3F
 231 #define DEFAULT_CACHE_OVERRIDE                  0
 232 #define DEFAULT_DMA_CAM_NUM_OF_ENTRIES          64
 233 #define DEFAULT_DMA_DBG_CNT_MODE                0
 234 #define DEFAULT_DMA_SOS_EMERGENCY               0
 235 #define DEFAULT_DMA_WATCHDOG                    0
 236 #define DEFAULT_DISP_LIMIT                      0
 237 #define DEFAULT_PRS_DISP_TH                     16
 238 #define DEFAULT_PLCR_DISP_TH                    16
 239 #define DEFAULT_KG_DISP_TH                      16
 240 #define DEFAULT_BMI_DISP_TH                     16
 241 #define DEFAULT_QMI_ENQ_DISP_TH         16
 242 #define DEFAULT_QMI_DEQ_DISP_TH         16
 243 #define DEFAULT_FM_CTL1_DISP_TH         16
 244 #define DEFAULT_FM_CTL2_DISP_TH         16
 245
 246 #define DFLT_AXI_DBG_NUM_OF_BEATS               1
 247
 248 #define DFLT_DMA_READ_INT_BUF_LOW(dma_thresh_max_buf)   \
 249         ((dma_thresh_max_buf + 1) / 2)
 250 #define DFLT_DMA_READ_INT_BUF_HIGH(dma_thresh_max_buf)  \
 251         ((dma_thresh_max_buf + 1) * 3 / 4)
 252 #define DFLT_DMA_WRITE_INT_BUF_LOW(dma_thresh_max_buf)  \
 253         ((dma_thresh_max_buf + 1) / 2)
 254 #define DFLT_DMA_WRITE_INT_BUF_HIGH(dma_thresh_max_buf)\
 255         ((dma_thresh_max_buf + 1) * 3 / 4)
 256
 257 #define DMA_COMM_Q_LOW_FMAN_V3          0x2A
 258 #define DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq)            \
 259         ((dma_thresh_max_commq + 1) / 2)
 260 #define DFLT_DMA_COMM_Q_LOW(major, dma_thresh_max_commq)        \
 261         ((major == 6) ? DMA_COMM_Q_LOW_FMAN_V3 :                \
 262         DMA_COMM_Q_LOW_FMAN_V2(dma_thresh_max_commq))
 263
 264 #define DMA_COMM_Q_HIGH_FMAN_V3 0x3f
 265 #define DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq)           \
 266         ((dma_thresh_max_commq + 1) * 3 / 4)
 267 #define DFLT_DMA_COMM_Q_HIGH(major, dma_thresh_max_commq)       \
 268         ((major == 6) ? DMA_COMM_Q_HIGH_FMAN_V3 :               \
 269         DMA_COMM_Q_HIGH_FMAN_V2(dma_thresh_max_commq))
 270
 271 #define TOTAL_NUM_OF_TASKS_FMAN_V3L     59
 272 #define TOTAL_NUM_OF_TASKS_FMAN_V3H     124
 273 #define DFLT_TOTAL_NUM_OF_TASKS(major, minor, bmi_max_num_of_tasks)     \
 274         ((major == 6) ? ((minor == 1 || minor == 4) ?                   \
 275         TOTAL_NUM_OF_TASKS_FMAN_V3L : TOTAL_NUM_OF_TASKS_FMAN_V3H) :    \
 276         bmi_max_num_of_tasks)
 277
 278 #define DMA_CAM_NUM_OF_ENTRIES_FMAN_V3          64
 279 #define DMA_CAM_NUM_OF_ENTRIES_FMAN_V2          32
 280 #define DFLT_DMA_CAM_NUM_OF_ENTRIES(major)                      \
 281         (major == 6 ? DMA_CAM_NUM_OF_ENTRIES_FMAN_V3 :          \
 282         DMA_CAM_NUM_OF_ENTRIES_FMAN_V2)
 283
 284 #define FM_TIMESTAMP_1_USEC_BIT             8
 285
 286 /* Defines used for enabling/disabling FMan interrupts */
 287 #define ERR_INTR_EN_DMA         0x00010000
 288 #define ERR_INTR_EN_FPM         0x80000000
 289 #define ERR_INTR_EN_BMI         0x00800000
 290 #define ERR_INTR_EN_QMI         0x00400000
 291 #define ERR_INTR_EN_MURAM       0x00040000
 292 #define ERR_INTR_EN_MAC0        0x00004000
 293 #define ERR_INTR_EN_MAC1        0x00002000
 294 #define ERR_INTR_EN_MAC2        0x00001000
 295 #define ERR_INTR_EN_MAC3        0x00000800
 296 #define ERR_INTR_EN_MAC4        0x00000400
 297 #define ERR_INTR_EN_MAC5        0x00000200
 298 #define ERR_INTR_EN_MAC6        0x00000100
 299 #define ERR_INTR_EN_MAC7        0x00000080
 300 #define ERR_INTR_EN_MAC8        0x00008000
 301 #define ERR_INTR_EN_MAC9        0x00000040
 302
 303 #define INTR_EN_QMI             0x40000000
 304 #define INTR_EN_MAC0            0x00080000
 305 #define INTR_EN_MAC1            0x00040000
 306 #define INTR_EN_MAC2            0x00020000
 307 #define INTR_EN_MAC3            0x00010000
 308 #define INTR_EN_MAC4            0x00000040
 309 #define INTR_EN_MAC5            0x00000020
 310 #define INTR_EN_MAC6            0x00000008
 311 #define INTR_EN_MAC7            0x00000002
 312 #define INTR_EN_MAC8            0x00200000
 313 #define INTR_EN_MAC9            0x00100000
 314 #define INTR_EN_REV0            0x00008000
 315 #define INTR_EN_REV1            0x00004000
 316 #define INTR_EN_REV2            0x00002000
 317 #define INTR_EN_REV3            0x00001000
 318 #define INTR_EN_TMR             0x01000000
 319
 320 enum fman_dma_aid_mode {
 321         FMAN_DMA_AID_OUT_PORT_ID = 0,             /* 4 LSB of PORT_ID */
 322         FMAN_DMA_AID_OUT_TNUM                     /* 4 LSB of TNUM */
 323 };
 324
 325 struct fman_iram_regs {
 326         u32 iadd;       /* FM IRAM instruction address register */
 327         u32 idata;      /* FM IRAM instruction data register */
 328         u32 itcfg;      /* FM IRAM timing config register */
 329         u32 iready;     /* FM IRAM ready register */
 330 };
 331
 332 struct fman_fpm_regs {
 333         u32 fmfp_tnc;           /* FPM TNUM Control 0x00 */
 334         u32 fmfp_prc;           /* FPM Port_ID FmCtl Association 0x04 */
 335         u32 fmfp_brkc;          /* FPM Breakpoint Control 0x08 */
 336         u32 fmfp_mxd;           /* FPM Flush Control 0x0c */
 337         u32 fmfp_dist1;         /* FPM Dispatch Thresholds1 0x10 */
 338         u32 fmfp_dist2;         /* FPM Dispatch Thresholds2 0x14 */
 339         u32 fm_epi;             /* FM Error Pending Interrupts 0x18 */
 340         u32 fm_rie;             /* FM Error Interrupt Enable 0x1c */
 341         u32 fmfp_fcev[4];       /* FPM FMan-Controller Event 1-4 0x20-0x2f */
 342         u32 res0030[4];         /* res 0x30 - 0x3f */
 343         u32 fmfp_cee[4];        /* PM FMan-Controller Event 1-4 0x40-0x4f */
 344         u32 res0050[4];         /* res 0x50-0x5f */
 345         u32 fmfp_tsc1;          /* FPM TimeStamp Control1 0x60 */
 346         u32 fmfp_tsc2;          /* FPM TimeStamp Control2 0x64 */
 347         u32 fmfp_tsp;           /* FPM Time Stamp 0x68 */
 348         u32 fmfp_tsf;           /* FPM Time Stamp Fraction 0x6c */
 349         u32 fm_rcr;             /* FM Rams Control 0x70 */
 350         u32 fmfp_extc;          /* FPM External Requests Control 0x74 */
 351         u32 fmfp_ext1;          /* FPM External Requests Config1 0x78 */
 352         u32 fmfp_ext2;          /* FPM External Requests Config2 0x7c */
 353         u32 fmfp_drd[16];       /* FPM Data_Ram Data 0-15 0x80 - 0xbf */
 354         u32 fmfp_dra;           /* FPM Data Ram Access 0xc0 */
 355         u32 fm_ip_rev_1;        /* FM IP Block Revision 1 0xc4 */
 356         u32 fm_ip_rev_2;        /* FM IP Block Revision 2 0xc8 */
 357         u32 fm_rstc;            /* FM Reset Command 0xcc */
 358         u32 fm_cld;             /* FM Classifier Debug 0xd0 */
 359         u32 fm_npi;             /* FM Normal Pending Interrupts 0xd4 */
 360         u32 fmfp_exte;          /* FPM External Requests Enable 0xd8 */
 361         u32 fmfp_ee;            /* FPM Event&Mask 0xdc */
 362         u32 fmfp_cev[4];        /* FPM CPU Event 1-4 0xe0-0xef */
 363         u32 res00f0[4];         /* res 0xf0-0xff */
 364         u32 fmfp_ps[50];        /* FPM Port Status 0x100-0x1c7 */
 365         u32 res01c8[14];        /* res 0x1c8-0x1ff */
 366         u32 fmfp_clfabc;        /* FPM CLFABC 0x200 */
 367         u32 fmfp_clfcc;         /* FPM CLFCC 0x204 */
 368         u32 fmfp_clfaval;       /* FPM CLFAVAL 0x208 */
 369         u32 fmfp_clfbval;       /* FPM CLFBVAL 0x20c */
 370         u32 fmfp_clfcval;       /* FPM CLFCVAL 0x210 */
 371         u32 fmfp_clfamsk;       /* FPM CLFAMSK 0x214 */
 372         u32 fmfp_clfbmsk;       /* FPM CLFBMSK 0x218 */
 373         u32 fmfp_clfcmsk;       /* FPM CLFCMSK 0x21c */
 374         u32 fmfp_clfamc;        /* FPM CLFAMC 0x220 */
 375         u32 fmfp_clfbmc;        /* FPM CLFBMC 0x224 */
 376         u32 fmfp_clfcmc;        /* FPM CLFCMC 0x228 */
 377         u32 fmfp_decceh;        /* FPM DECCEH 0x22c */
 378         u32 res0230[116];       /* res 0x230 - 0x3ff */
 379         u32 fmfp_ts[128];       /* 0x400: FPM Task Status 0x400 - 0x5ff */
 380         u32 res0600[0x400 - 384];
 381 };
 382
 383 struct fman_bmi_regs {
 384         u32 fmbm_init;          /* BMI Initialization 0x00 */
 385         u32 fmbm_cfg1;          /* BMI Configuration 1 0x04 */
 386         u32 fmbm_cfg2;          /* BMI Configuration 2 0x08 */
 387         u32 res000c[5];         /* 0x0c - 0x1f */
 388         u32 fmbm_ievr;          /* Interrupt Event Register 0x20 */
 389         u32 fmbm_ier;           /* Interrupt Enable Register 0x24 */
 390         u32 fmbm_ifr;           /* Interrupt Force Register 0x28 */
 391         u32 res002c[5];         /* 0x2c - 0x3f */
 392         u32 fmbm_arb[8];        /* BMI Arbitration 0x40 - 0x5f */
 393         u32 res0060[12];        /* 0x60 - 0x8f */
 394         u32 fmbm_dtc[3];        /* Debug Trap Counter 0x90 - 0x9b */
 395         u32 res009c;            /* 0x9c */
 396         u32 fmbm_dcv[3][4];     /* Debug Compare val 0xa0-0xcf */
 397         u32 fmbm_dcm[3][4];     /* Debug Compare Mask 0xd0-0xff */
 398         u32 fmbm_gde;           /* BMI Global Debug Enable 0x100 */
 399         u32 fmbm_pp[63];        /* BMI Port Parameters 0x104 - 0x1ff */
 400         u32 res0200;            /* 0x200 */
 401         u32 fmbm_pfs[63];       /* BMI Port FIFO Size 0x204 - 0x2ff */
 402         u32 res0300;            /* 0x300 */
 403         u32 fmbm_spliodn[63];   /* Port Partition ID 0x304 - 0x3ff */
 404 };
 405
 406 struct fman_qmi_regs {
 407         u32 fmqm_gc;            /* General Configuration Register 0x00 */
 408         u32 res0004;            /* 0x04 */
 409         u32 fmqm_eie;           /* Error Interrupt Event Register 0x08 */
 410         u32 fmqm_eien;          /* Error Interrupt Enable Register 0x0c */
 411         u32 fmqm_eif;           /* Error Interrupt Force Register 0x10 */
 412         u32 fmqm_ie;            /* Interrupt Event Register 0x14 */
 413         u32 fmqm_ien;           /* Interrupt Enable Register 0x18 */
 414         u32 fmqm_if;            /* Interrupt Force Register 0x1c */
 415         u32 fmqm_gs;            /* Global Status Register 0x20 */
 416         u32 fmqm_ts;            /* Task Status Register 0x24 */
 417         u32 fmqm_etfc;          /* Enqueue Total Frame Counter 0x28 */
 418         u32 fmqm_dtfc;          /* Dequeue Total Frame Counter 0x2c */
 419         u32 fmqm_dc0;           /* Dequeue Counter 0 0x30 */
 420         u32 fmqm_dc1;           /* Dequeue Counter 1 0x34 */
 421         u32 fmqm_dc2;           /* Dequeue Counter 2 0x38 */
 422         u32 fmqm_dc3;           /* Dequeue Counter 3 0x3c */
 423         u32 fmqm_dfdc;          /* Dequeue FQID from Default Counter 0x40 */
 424         u32 fmqm_dfcc;          /* Dequeue FQID from Context Counter 0x44 */
 425         u32 fmqm_dffc;          /* Dequeue FQID from FD Counter 0x48 */
 426         u32 fmqm_dcc;           /* Dequeue Confirm Counter 0x4c */
 427         u32 res0050[7];         /* 0x50 - 0x6b */
 428         u32 fmqm_tapc;          /* Tnum Aging Period Control 0x6c */
 429         u32 fmqm_dmcvc;         /* Dequeue MAC Command Valid Counter 0x70 */
 430         u32 fmqm_difdcc;        /* Dequeue Invalid FD Command Counter 0x74 */
 431         u32 fmqm_da1v;          /* Dequeue A1 Valid Counter 0x78 */
 432         u32 res007c;            /* 0x7c */
 433         u32 fmqm_dtc;           /* 0x80 Debug Trap Counter 0x80 */
 434         u32 fmqm_efddd;         /* 0x84 Enqueue Frame desc Dynamic dbg 0x84 */
 435         u32 res0088[2];         /* 0x88 - 0x8f */
 436         struct {
 437                 u32 fmqm_dtcfg1;        /* 0x90 dbg trap cfg 1 Register 0x00 */
 438                 u32 fmqm_dtval1;        /* Debug Trap Value 1 Register 0x04 */
 439                 u32 fmqm_dtm1;          /* Debug Trap Mask 1 Register 0x08 */
 440                 u32 fmqm_dtc1;          /* Debug Trap Counter 1 Register 0x0c */
 441                 u32 fmqm_dtcfg2;        /* dbg Trap cfg 2 Register 0x10 */
 442                 u32 fmqm_dtval2;        /* Debug Trap Value 2 Register 0x14 */
 443                 u32 fmqm_dtm2;          /* Debug Trap Mask 2 Register 0x18 */
 444                 u32 res001c;            /* 0x1c */
 445         } dbg_traps[3];                 /* 0x90 - 0xef */
 446         u8 res00f0[0x400 - 0xf0];       /* 0xf0 - 0x3ff */
 447 };
 448
 449 struct fman_dma_regs {
 450         u32 fmdmsr;     /* FM DMA status register 0x00 */
 451         u32 fmdmmr;     /* FM DMA mode register 0x04 */
 452         u32 fmdmtr;     /* FM DMA bus threshold register 0x08 */
 453         u32 fmdmhy;     /* FM DMA bus hysteresis register 0x0c */
 454         u32 fmdmsetr;   /* FM DMA SOS emergency Threshold Register 0x10 */
 455         u32 fmdmtah;    /* FM DMA transfer bus address high reg 0x14 */
 456         u32 fmdmtal;    /* FM DMA transfer bus address low reg 0x18 */
 457         u32 fmdmtcid;   /* FM DMA transfer bus communication ID reg 0x1c */
 458         u32 fmdmra;     /* FM DMA bus internal ram address register 0x20 */
 459         u32 fmdmrd;     /* FM DMA bus internal ram data register 0x24 */
 460         u32 fmdmwcr;    /* FM DMA CAM watchdog counter value 0x28 */
 461         u32 fmdmebcr;   /* FM DMA CAM base in MURAM register 0x2c */
 462         u32 fmdmccqdr;  /* FM DMA CAM and CMD Queue Debug reg 0x30 */
 463         u32 fmdmccqvr1; /* FM DMA CAM and CMD Queue Value reg #1 0x34 */
 464         u32 fmdmccqvr2; /* FM DMA CAM and CMD Queue Value reg #2 0x38 */
 465         u32 fmdmcqvr3;  /* FM DMA CMD Queue Value register #3 0x3c */
 466         u32 fmdmcqvr4;  /* FM DMA CMD Queue Value register #4 0x40 */
 467         u32 fmdmcqvr5;  /* FM DMA CMD Queue Value register #5 0x44 */
 468         u32 fmdmsefrc;  /* FM DMA Semaphore Entry Full Reject Cntr 0x48 */
 469         u32 fmdmsqfrc;  /* FM DMA Semaphore Queue Full Reject Cntr 0x4c */
 470         u32 fmdmssrc;   /* FM DMA Semaphore SYNC Reject Counter 0x50 */
 471         u32 fmdmdcr;    /* FM DMA Debug Counter 0x54 */
 472         u32 fmdmemsr;   /* FM DMA Emergency Smoother Register 0x58 */
 473         u32 res005c;    /* 0x5c */
 474         u32 fmdmplr[FMAN_LIODN_TBL / 2];        /* DMA LIODN regs 0x60-0xdf */
 475         u32 res00e0[0x400 - 56];
 476 };
 477
 478 /* Structure that holds current FMan state.
 479  * Used for saving run time information.
 480  */
 481 struct fman_state_struct {
 482         u8 fm_id;
 483         u16 fm_clk_freq;
 484         struct fman_rev_info rev_info;
 485         bool enabled_time_stamp;
 486         u8 count1_micro_bit;
 487         u8 total_num_of_tasks;
 488         u8 accumulated_num_of_tasks;
 489         u32 accumulated_fifo_size;
 490         u8 accumulated_num_of_open_dmas;
 491         u8 accumulated_num_of_deq_tnums;
 492         u32 exceptions;
 493         u32 extra_fifo_pool_size;
 494         u8 extra_tasks_pool_size;
 495         u8 extra_open_dmas_pool_size;
 496         u16 port_mfl[MAX_NUM_OF_MACS];
 497         u16 mac_mfl[MAX_NUM_OF_MACS];
 498
 499         /* SOC specific */
 500         u32 fm_iram_size;
 501         /* DMA */
 502         u32 dma_thresh_max_commq;
 503         u32 dma_thresh_max_buf;
 504         u32 max_num_of_open_dmas;
 505         /* QMI */
 506         u32 qmi_max_num_of_tnums;
 507         u32 qmi_def_tnums_thresh;
 508         /* BMI */
 509         u32 bmi_max_num_of_tasks;
 510         u32 bmi_max_fifo_size;
 511         /* General */
 512         u32 fm_port_num_of_cg;
 513         u32 num_of_rx_ports;
 514         u32 total_fifo_size;
 515
 516         u32 qman_channel_base;
 517         u32 num_of_qman_channels;
 518
 519         struct resource *res;
 520 };
 521
 522 /* Structure that holds FMan initial configuration */
 523 struct fman_cfg {
 524         u8 disp_limit_tsh;
 525         u8 prs_disp_tsh;
 526         u8 plcr_disp_tsh;
 527         u8 kg_disp_tsh;
 528         u8 bmi_disp_tsh;
 529         u8 qmi_enq_disp_tsh;
 530         u8 qmi_deq_disp_tsh;
 531         u8 fm_ctl1_disp_tsh;
 532         u8 fm_ctl2_disp_tsh;
 533         int dma_cache_override;
 534         enum fman_dma_aid_mode dma_aid_mode;
 535         u32 dma_axi_dbg_num_of_beats;
 536         u32 dma_cam_num_of_entries;
 537         u32 dma_watchdog;
 538         u8 dma_comm_qtsh_asrt_emer;
 539         u32 dma_write_buf_tsh_asrt_emer;
 540         u32 dma_read_buf_tsh_asrt_emer;
 541         u8 dma_comm_qtsh_clr_emer;
 542         u32 dma_write_buf_tsh_clr_emer;
 543         u32 dma_read_buf_tsh_clr_emer;
 544         u32 dma_sos_emergency;
 545         int dma_dbg_cnt_mode;
 546         int catastrophic_err;
 547         int dma_err;
 548         u32 exceptions;
 549         u16 clk_freq;
 550         u32 cam_base_addr;
 551         u32 fifo_base_addr;
 552         u32 total_fifo_size;
 553         u32 total_num_of_tasks;
 554         u32 qmi_def_tnums_thresh;
 555 };
 556
 557 /* Structure that holds information received from device tree */
 558 struct fman_dts_params {
 559         void __iomem *base_addr;                /* FMan virtual address */
 560         struct resource *res;                   /* FMan memory resource */
 561         u8 id;                                  /* FMan ID */
 562
 563         int err_irq;                            /* FMan Error IRQ */
 564
 565         u16 clk_freq;                           /* FMan clock freq (In Mhz) */
 566
 567         u32 qman_channel_base;                  /* QMan channels base */
 568         u32 num_of_qman_channels;               /* Number of QMan channels */
 569
 570         struct resource muram_res;              /* MURAM resource */
 571 };
 572
 573 /** fman_exceptions_cb
 574  * fman         - Pointer to FMan
 575  * exception    - The exception.
 576  *
 577  * Exceptions user callback routine, will be called upon an exception
 578  * passing the exception identification.
 579  *
 580  * Return: irq status
 581  */
 582 typedef irqreturn_t (fman_exceptions_cb)(struct fman *fman,
 583                                          enum fman_exceptions exception);
 584
 585 /** fman_bus_error_cb
 586  * fman         - Pointer to FMan
 587  * port_id      - Port id
 588  * addr         - Address that caused the error
 589  * tnum         - Owner of error
 590  * liodn        - Logical IO device number
 591  *
 592  * Bus error user callback routine, will be called upon bus error,
 593  * passing parameters describing the errors and the owner.
 594  *
 595  * Return: IRQ status
 596  */
 597 typedef irqreturn_t (fman_bus_error_cb)(struct fman *fman, u8 port_id,
 598                                         u64 addr, u8 tnum, u16 liodn);
 599
 600 struct fman {
 601         struct device *dev;
 602         void __iomem *base_addr;
 603         struct fman_intr_src intr_mng[FMAN_EV_CNT];
 604
 605         struct fman_fpm_regs __iomem *fpm_regs;
 606         struct fman_bmi_regs __iomem *bmi_regs;
 607         struct fman_qmi_regs __iomem *qmi_regs;
 608         struct fman_dma_regs __iomem *dma_regs;
 609         fman_exceptions_cb *exception_cb;
 610         fman_bus_error_cb *bus_error_cb;
 611         /* Spinlock for FMan use */
 612         spinlock_t spinlock;
 613         struct fman_state_struct *state;
 614
 615         struct fman_cfg *cfg;
 616         struct muram_info *muram;
 617         /* cam section in muram */
 618         unsigned long cam_offset;
 619         size_t cam_size;
 620         /* Fifo in MURAM */
 621         unsigned long fifo_offset;
 622         size_t fifo_size;
 623
 624         u32 liodn_base[64];
 625         u32 liodn_offset[64];
 626
 627         struct fman_dts_params dts_params;
 628 };
 629
 630 static irqreturn_t fman_exceptions(struct fman *fman,
 631                                    enum fman_exceptions exception)
 632 {
 633         dev_dbg(fman->dev, "%s: FMan[%d] exception %d\n",
 634                 __func__, fman->state->fm_id, exception);
 635
 636         return IRQ_HANDLED;
 637 }
 638
 639 static irqreturn_t fman_bus_error(struct fman *fman, u8 __maybe_unused port_id,
 640                                   u64 __maybe_unused addr,
 641                                   u8 __maybe_unused tnum,
 642                                   u16 __maybe_unused liodn)
 643 {
 644         dev_dbg(fman->dev, "%s: FMan[%d] bus error: port_id[%d]\n",
 645                 __func__, fman->state->fm_id, port_id);
 646
 647         return IRQ_HANDLED;
 648 }
 649
 650 static inline irqreturn_t call_mac_isr(struct fman *fman, u8 id)
 651 {
 652         if (fman->intr_mng[id].isr_cb) {
 653                 fman->intr_mng[id].isr_cb(fman->intr_mng[id].src_handle);
 654
 655                 return IRQ_HANDLED;
 656         }
 657
 658         return IRQ_NONE;
 659 }
 660
 661 static inline u8 hw_port_id_to_sw_port_id(u8 major, u8 hw_port_id)
 662 {
 663         u8 sw_port_id = 0;
 664
 665         if (hw_port_id >= BASE_TX_PORTID)
 666                 sw_port_id = hw_port_id - BASE_TX_PORTID;
 667         else if (hw_port_id >= BASE_RX_PORTID)
 668                 sw_port_id = hw_port_id - BASE_RX_PORTID;
 669         else
 670                 sw_port_id = 0;
 671
 672         return sw_port_id;
 673 }
 674
 675 static void set_port_order_restoration(struct fman_fpm_regs __iomem *fpm_rg,
 676                                        u8 port_id)
 677 {
 678         u32 tmp = 0;
 679
 680         tmp = port_id << FPM_PORT_FM_CTL_PORTID_SHIFT;
 681
 682         tmp |= FPM_PRT_FM_CTL2 | FPM_PRT_FM_CTL1;
 683
 684         /* order restoration */
 685         if (port_id % 2)
 686                 tmp |= FPM_PRT_FM_CTL1 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT;
 687         else
 688                 tmp |= FPM_PRT_FM_CTL2 << FPM_PRC_ORA_FM_CTL_SEL_SHIFT;
 689
 690         iowrite32be(tmp, &fpm_rg->fmfp_prc);
 691 }
 692
 693 static void set_port_liodn(struct fman *fman, u8 port_id,
 694                            u32 liodn_base, u32 liodn_ofst)
 695 {
 696         u32 tmp;
 697
 698         /* set LIODN base for this port */
 699         tmp = ioread32be(&fman->dma_regs->fmdmplr[port_id / 2]);
 700         if (port_id % 2) {
 701                 tmp &= ~DMA_LIODN_BASE_MASK;
 702                 tmp |= liodn_base;
 703         } else {
 704                 tmp &= ~(DMA_LIODN_BASE_MASK << DMA_LIODN_SHIFT);
 705                 tmp |= liodn_base << DMA_LIODN_SHIFT;
 706         }
 707         iowrite32be(tmp, &fman->dma_regs->fmdmplr[port_id / 2]);
 708         iowrite32be(liodn_ofst, &fman->bmi_regs->fmbm_spliodn[port_id - 1]);
 709 }
 710
 711 static void enable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
 712 {
 713         u32 tmp;
 714
 715         tmp = ioread32be(&fpm_rg->fm_rcr);
 716         if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
 717                 iowrite32be(tmp | FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
 718         else
 719                 iowrite32be(tmp | FPM_RAM_RAMS_ECC_EN |
 720                             FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
 721 }
 722
 723 static void disable_rams_ecc(struct fman_fpm_regs __iomem *fpm_rg)
 724 {
 725         u32 tmp;
 726
 727         tmp = ioread32be(&fpm_rg->fm_rcr);
 728         if (tmp & FPM_RAM_RAMS_ECC_EN_SRC_SEL)
 729                 iowrite32be(tmp & ~FPM_RAM_IRAM_ECC_EN, &fpm_rg->fm_rcr);
 730         else
 731                 iowrite32be(tmp & ~(FPM_RAM_RAMS_ECC_EN | FPM_RAM_IRAM_ECC_EN),
 732                             &fpm_rg->fm_rcr);
 733 }
 734
 735 static void fman_defconfig(struct fman_cfg *cfg)
 736 {
 737         memset(cfg, 0, sizeof(struct fman_cfg));
 738
 739         cfg->catastrophic_err = DEFAULT_CATASTROPHIC_ERR;
 740         cfg->dma_err = DEFAULT_DMA_ERR;
 741         cfg->dma_aid_mode = DEFAULT_AID_MODE;
 742         cfg->dma_comm_qtsh_clr_emer = DEFAULT_DMA_COMM_Q_LOW;
 743         cfg->dma_comm_qtsh_asrt_emer = DEFAULT_DMA_COMM_Q_HIGH;
 744         cfg->dma_cache_override = DEFAULT_CACHE_OVERRIDE;
 745         cfg->dma_cam_num_of_entries = DEFAULT_DMA_CAM_NUM_OF_ENTRIES;
 746         cfg->dma_dbg_cnt_mode = DEFAULT_DMA_DBG_CNT_MODE;
 747         cfg->dma_sos_emergency = DEFAULT_DMA_SOS_EMERGENCY;
 748         cfg->dma_watchdog = DEFAULT_DMA_WATCHDOG;
 749         cfg->disp_limit_tsh = DEFAULT_DISP_LIMIT;
 750         cfg->prs_disp_tsh = DEFAULT_PRS_DISP_TH;
 751         cfg->plcr_disp_tsh = DEFAULT_PLCR_DISP_TH;
 752         cfg->kg_disp_tsh = DEFAULT_KG_DISP_TH;
 753         cfg->bmi_disp_tsh = DEFAULT_BMI_DISP_TH;
 754         cfg->qmi_enq_disp_tsh = DEFAULT_QMI_ENQ_DISP_TH;
 755         cfg->qmi_deq_disp_tsh = DEFAULT_QMI_DEQ_DISP_TH;
 756         cfg->fm_ctl1_disp_tsh = DEFAULT_FM_CTL1_DISP_TH;
 757         cfg->fm_ctl2_disp_tsh = DEFAULT_FM_CTL2_DISP_TH;
 758 }
 759
 760 static int dma_init(struct fman *fman)
 761 {
 762         struct fman_dma_regs __iomem *dma_rg = fman->dma_regs;
 763         struct fman_cfg *cfg = fman->cfg;
 764         u32 tmp_reg;
 765
 766         /* Init DMA Registers */
 767
 768         /* clear status reg events */
 769         tmp_reg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC |
 770                    DMA_STATUS_SYSTEM_WRITE_ECC | DMA_STATUS_FM_WRITE_ECC);
 771         iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg, &dma_rg->fmdmsr);
 772
 773         /* configure mode register */
 774         tmp_reg = 0;
 775         tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT;
 776         if (cfg->exceptions & EX_DMA_BUS_ERROR)
 777                 tmp_reg |= DMA_MODE_BER;
 778         if ((cfg->exceptions & EX_DMA_SYSTEM_WRITE_ECC) |
 779             (cfg->exceptions & EX_DMA_READ_ECC) |
 780             (cfg->exceptions & EX_DMA_FM_WRITE_ECC))
 781                 tmp_reg |= DMA_MODE_ECC;
 782         if (cfg->dma_axi_dbg_num_of_beats)
 783                 tmp_reg |= (DMA_MODE_AXI_DBG_MASK &
 784                         ((cfg->dma_axi_dbg_num_of_beats - 1)
 785                         << DMA_MODE_AXI_DBG_SHIFT));
 786
 787         tmp_reg |= (((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) &
 788                 DMA_MODE_CEN_MASK) << DMA_MODE_CEN_SHIFT;
 789         tmp_reg |= DMA_MODE_SECURE_PROT;
 790         tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT;
 791         tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT;
 792
 793         iowrite32be(tmp_reg, &dma_rg->fmdmmr);
 794
 795         /* configure thresholds register */
 796         tmp_reg = ((u32)cfg->dma_comm_qtsh_asrt_emer <<
 797                 DMA_THRESH_COMMQ_SHIFT);
 798         tmp_reg |= (cfg->dma_read_buf_tsh_asrt_emer &
 799                 DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT;
 800         tmp_reg |= cfg->dma_write_buf_tsh_asrt_emer &
 801                 DMA_THRESH_WRITE_INT_BUF_MASK;
 802
 803         iowrite32be(tmp_reg, &dma_rg->fmdmtr);
 804
 805         /* configure hysteresis register */
 806         tmp_reg = ((u32)cfg->dma_comm_qtsh_clr_emer <<
 807                 DMA_THRESH_COMMQ_SHIFT);
 808         tmp_reg |= (cfg->dma_read_buf_tsh_clr_emer &
 809                 DMA_THRESH_READ_INT_BUF_MASK) << DMA_THRESH_READ_INT_BUF_SHIFT;
 810         tmp_reg |= cfg->dma_write_buf_tsh_clr_emer &
 811                 DMA_THRESH_WRITE_INT_BUF_MASK;
 812
 813         iowrite32be(tmp_reg, &dma_rg->fmdmhy);
 814
 815         /* configure emergency threshold */
 816         iowrite32be(cfg->dma_sos_emergency, &dma_rg->fmdmsetr);
 817
 818         /* configure Watchdog */
 819         iowrite32be((cfg->dma_watchdog * cfg->clk_freq), &dma_rg->fmdmwcr);
 820
 821         iowrite32be(cfg->cam_base_addr, &dma_rg->fmdmebcr);
 822
 823         /* Allocate MURAM for CAM */
 824         fman->cam_size =
 825                 (u32)(fman->cfg->dma_cam_num_of_entries * DMA_CAM_SIZEOF_ENTRY);
 826         fman->cam_offset = fman_muram_alloc(fman->muram, fman->cam_size);
 827         if (IS_ERR_VALUE(fman->cam_offset)) {
 828                 dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n",
 829                         __func__);
 830                 return -ENOMEM;
 831         }
 832
 833         if (fman->state->rev_info.major == 2) {
 834                 u32 __iomem *cam_base_addr;
 835
 836                 fman_muram_free_mem(fman->muram, fman->cam_offset,
 837                                     fman->cam_size);
 838
 839                 fman->cam_size = fman->cfg->dma_cam_num_of_entries * 72 + 128;
 840                 fman->cam_offset = fman_muram_alloc(fman->muram,
 841                                                     fman->cam_size);
 842                 if (IS_ERR_VALUE(fman->cam_offset)) {
 843                         dev_err(fman->dev, "%s: MURAM alloc for DMA CAM failed\n",
 844                                 __func__);
 845                         return -ENOMEM;
 846                 }
 847
 848                 if (fman->cfg->dma_cam_num_of_entries % 8 ||
 849                     fman->cfg->dma_cam_num_of_entries > 32) {
 850                         dev_err(fman->dev, "%s: wrong dma_cam_num_of_entries\n",
 851                                 __func__);
 852                         return -EINVAL;
 853                 }
 854
 855                 cam_base_addr = (u32 __iomem *)
 856                         fman_muram_offset_to_vbase(fman->muram,
 857                                                    fman->cam_offset);
 858                 iowrite32be(~((1 <<
 859                             (32 - fman->cfg->dma_cam_num_of_entries)) - 1),
 860                             cam_base_addr);
 861         }
 862
 863         fman->cfg->cam_base_addr = fman->cam_offset;
 864
 865         return 0;
 866 }
 867
 868 static void fpm_init(struct fman_fpm_regs __iomem *fpm_rg, struct fman_cfg *cfg)
 869 {
 870         u32 tmp_reg;
 871         int i;
 872
 873         /* Init FPM Registers */
 874
 875         tmp_reg = (u32)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT);
 876         iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd);
 877
 878         tmp_reg = (((u32)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) |
 879                    ((u32)cfg->kg_disp_tsh << FPM_THR1_KG_SHIFT) |
 880                    ((u32)cfg->plcr_disp_tsh << FPM_THR1_PLCR_SHIFT) |
 881                    ((u32)cfg->bmi_disp_tsh << FPM_THR1_BMI_SHIFT));
 882         iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1);
 883
 884         tmp_reg =
 885                 (((u32)cfg->qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) |
 886                  ((u32)cfg->qmi_deq_disp_tsh << FPM_THR2_QMI_DEQ_SHIFT) |
 887                  ((u32)cfg->fm_ctl1_disp_tsh << FPM_THR2_FM_CTL1_SHIFT) |
 888                  ((u32)cfg->fm_ctl2_disp_tsh << FPM_THR2_FM_CTL2_SHIFT));
 889         iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2);
 890
 891         /* define exceptions and error behavior */
 892         tmp_reg = 0;
 893         /* Clear events */
 894         tmp_reg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC |
 895                     FPM_EV_MASK_SINGLE_ECC);
 896         /* enable interrupts */
 897         if (cfg->exceptions & EX_FPM_STALL_ON_TASKS)
 898                 tmp_reg |= FPM_EV_MASK_STALL_EN;
 899         if (cfg->exceptions & EX_FPM_SINGLE_ECC)
 900                 tmp_reg |= FPM_EV_MASK_SINGLE_ECC_EN;
 901         if (cfg->exceptions & EX_FPM_DOUBLE_ECC)
 902                 tmp_reg |= FPM_EV_MASK_DOUBLE_ECC_EN;
 903         tmp_reg |= (cfg->catastrophic_err << FPM_EV_MASK_CAT_ERR_SHIFT);
 904         tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT);
 905         /* FMan is not halted upon external halt activation */
 906         tmp_reg |= FPM_EV_MASK_EXTERNAL_HALT;
 907         /* Man is not halted upon  Unrecoverable ECC error behavior */
 908         tmp_reg |= FPM_EV_MASK_ECC_ERR_HALT;
 909         iowrite32be(tmp_reg, &fpm_rg->fmfp_ee);
 910
 911         /* clear all fmCtls event registers */
 912         for (i = 0; i < FM_NUM_OF_FMAN_CTRL_EVENT_REGS; i++)
 913                 iowrite32be(0xFFFFFFFF, &fpm_rg->fmfp_cev[i]);
 914
 915         /* RAM ECC -  enable and clear events */
 916         /* first we need to clear all parser memory,
 917          * as it is uninitialized and may cause ECC errors
 918          */
 919         /* event bits */
 920         tmp_reg = (FPM_RAM_MURAM_ECC | FPM_RAM_IRAM_ECC);
 921
 922         iowrite32be(tmp_reg, &fpm_rg->fm_rcr);
 923
 924         tmp_reg = 0;
 925         if (cfg->exceptions & EX_IRAM_ECC) {
 926                 tmp_reg |= FPM_IRAM_ECC_ERR_EX_EN;
 927                 enable_rams_ecc(fpm_rg);
 928         }
 929         if (cfg->exceptions & EX_MURAM_ECC) {
 930                 tmp_reg |= FPM_MURAM_ECC_ERR_EX_EN;
 931                 enable_rams_ecc(fpm_rg);
 932         }
 933         iowrite32be(tmp_reg, &fpm_rg->fm_rie);
 934 }
 935
 936 static void bmi_init(struct fman_bmi_regs __iomem *bmi_rg,
 937                      struct fman_cfg *cfg)
 938 {
 939         u32 tmp_reg;
 940
 941         /* Init BMI Registers */
 942
 943         /* define common resources */
 944         tmp_reg = cfg->fifo_base_addr;
 945         tmp_reg = tmp_reg / BMI_FIFO_ALIGN;
 946
 947         tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) <<
 948                     BMI_CFG1_FIFO_SIZE_SHIFT);
 949         iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1);
 950
 951         tmp_reg = ((cfg->total_num_of_tasks - 1) & BMI_CFG2_TASKS_MASK) <<
 952                    BMI_CFG2_TASKS_SHIFT;
 953         /* num of DMA's will be dynamically updated when each port is set */
 954         iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2);
 955
 956         /* define unmaskable exceptions, enable and clear events */
 957         tmp_reg = 0;
 958         iowrite32be(BMI_ERR_INTR_EN_LIST_RAM_ECC |
 959                     BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC |
 960                     BMI_ERR_INTR_EN_STATISTICS_RAM_ECC |
 961                     BMI_ERR_INTR_EN_DISPATCH_RAM_ECC, &bmi_rg->fmbm_ievr);
 962
 963         if (cfg->exceptions & EX_BMI_LIST_RAM_ECC)
 964                 tmp_reg |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
 965         if (cfg->exceptions & EX_BMI_STORAGE_PROFILE_ECC)
 966                 tmp_reg |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
 967         if (cfg->exceptions & EX_BMI_STATISTICS_RAM_ECC)
 968                 tmp_reg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
 969         if (cfg->exceptions & EX_BMI_DISPATCH_RAM_ECC)
 970                 tmp_reg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
 971         iowrite32be(tmp_reg, &bmi_rg->fmbm_ier);
 972 }
 973
 974 static void qmi_init(struct fman_qmi_regs __iomem *qmi_rg,
 975                      struct fman_cfg *cfg)
 976 {
 977         u32 tmp_reg;
 978
 979         /* Init QMI Registers */
 980
 981         /* Clear error interrupt events */
 982
 983         iowrite32be(QMI_ERR_INTR_EN_DOUBLE_ECC | QMI_ERR_INTR_EN_DEQ_FROM_DEF,
 984                     &qmi_rg->fmqm_eie);
 985         tmp_reg = 0;
 986         if (cfg->exceptions & EX_QMI_DEQ_FROM_UNKNOWN_PORTID)
 987                 tmp_reg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
 988         if (cfg->exceptions & EX_QMI_DOUBLE_ECC)
 989                 tmp_reg |= QMI_ERR_INTR_EN_DOUBLE_ECC;
 990         /* enable events */
 991         iowrite32be(tmp_reg, &qmi_rg->fmqm_eien);
 992
 993         tmp_reg = 0;
 994         /* Clear interrupt events */
 995         iowrite32be(QMI_INTR_EN_SINGLE_ECC, &qmi_rg->fmqm_ie);
 996         if (cfg->exceptions & EX_QMI_SINGLE_ECC)
 997                 tmp_reg |= QMI_INTR_EN_SINGLE_ECC;
 998         /* enable events */
 999         iowrite32be(tmp_reg, &qmi_rg->fmqm_ien);
1000 }
1001
1002 static int enable(struct fman *fman, struct fman_cfg *cfg)
1003 {
1004         u32 cfg_reg = 0;
1005
1006         /* Enable all modules */
1007
1008         /* clear&enable global counters - calculate reg and save for later,
1009          * because it's the same reg for QMI enable
1010          */
1011         cfg_reg = QMI_CFG_EN_COUNTERS;
1012
1013         /* Set enqueue and dequeue thresholds */
1014         cfg_reg |= (cfg->qmi_def_tnums_thresh << 8) | cfg->qmi_def_tnums_thresh;
1015
1016         iowrite32be(BMI_INIT_START, &fman->bmi_regs->fmbm_init);
1017         iowrite32be(cfg_reg | QMI_CFG_ENQ_EN | QMI_CFG_DEQ_EN,
1018                     &fman->qmi_regs->fmqm_gc);
1019
1020         return 0;
1021 }
1022
1023 static int set_exception(struct fman *fman,
1024                          enum fman_exceptions exception, bool enable)
1025 {
1026         u32 tmp;
1027
1028         switch (exception) {
1029         case FMAN_EX_DMA_BUS_ERROR:
1030                 tmp = ioread32be(&fman->dma_regs->fmdmmr);
1031                 if (enable)
1032                         tmp |= DMA_MODE_BER;
1033                 else
1034                         tmp &= ~DMA_MODE_BER;
1035                 /* disable bus error */
1036                 iowrite32be(tmp, &fman->dma_regs->fmdmmr);
1037                 break;
1038         case FMAN_EX_DMA_READ_ECC:
1039         case FMAN_EX_DMA_SYSTEM_WRITE_ECC:
1040         case FMAN_EX_DMA_FM_WRITE_ECC:
1041                 tmp = ioread32be(&fman->dma_regs->fmdmmr);
1042                 if (enable)
1043                         tmp |= DMA_MODE_ECC;
1044                 else
1045                         tmp &= ~DMA_MODE_ECC;
1046                 iowrite32be(tmp, &fman->dma_regs->fmdmmr);
1047                 break;
1048         case FMAN_EX_FPM_STALL_ON_TASKS:
1049                 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1050                 if (enable)
1051                         tmp |= FPM_EV_MASK_STALL_EN;
1052                 else
1053                         tmp &= ~FPM_EV_MASK_STALL_EN;
1054                 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1055                 break;
1056         case FMAN_EX_FPM_SINGLE_ECC:
1057                 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1058                 if (enable)
1059                         tmp |= FPM_EV_MASK_SINGLE_ECC_EN;
1060                 else
1061                         tmp &= ~FPM_EV_MASK_SINGLE_ECC_EN;
1062                 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1063                 break;
1064         case FMAN_EX_FPM_DOUBLE_ECC:
1065                 tmp = ioread32be(&fman->fpm_regs->fmfp_ee);
1066                 if (enable)
1067                         tmp |= FPM_EV_MASK_DOUBLE_ECC_EN;
1068                 else
1069                         tmp &= ~FPM_EV_MASK_DOUBLE_ECC_EN;
1070                 iowrite32be(tmp, &fman->fpm_regs->fmfp_ee);
1071                 break;
1072         case FMAN_EX_QMI_SINGLE_ECC:
1073                 tmp = ioread32be(&fman->qmi_regs->fmqm_ien);
1074                 if (enable)
1075                         tmp |= QMI_INTR_EN_SINGLE_ECC;
1076                 else
1077                         tmp &= ~QMI_INTR_EN_SINGLE_ECC;
1078                 iowrite32be(tmp, &fman->qmi_regs->fmqm_ien);
1079                 break;
1080         case FMAN_EX_QMI_DOUBLE_ECC:
1081                 tmp = ioread32be(&fman->qmi_regs->fmqm_eien);
1082                 if (enable)
1083                         tmp |= QMI_ERR_INTR_EN_DOUBLE_ECC;
1084                 else
1085                         tmp &= ~QMI_ERR_INTR_EN_DOUBLE_ECC;
1086                 iowrite32be(tmp, &fman->qmi_regs->fmqm_eien);
1087                 break;
1088         case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID:
1089                 tmp = ioread32be(&fman->qmi_regs->fmqm_eien);
1090                 if (enable)
1091                         tmp |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;
1092                 else
1093                         tmp &= ~QMI_ERR_INTR_EN_DEQ_FROM_DEF;
1094                 iowrite32be(tmp, &fman->qmi_regs->fmqm_eien);
1095                 break;
1096         case FMAN_EX_BMI_LIST_RAM_ECC:
1097                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1098                 if (enable)
1099                         tmp |= BMI_ERR_INTR_EN_LIST_RAM_ECC;
1100                 else
1101                         tmp &= ~BMI_ERR_INTR_EN_LIST_RAM_ECC;
1102                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1103                 break;
1104         case FMAN_EX_BMI_STORAGE_PROFILE_ECC:
1105                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1106                 if (enable)
1107                         tmp |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
1108                 else
1109                         tmp &= ~BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;
1110                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1111                 break;
1112         case FMAN_EX_BMI_STATISTICS_RAM_ECC:
1113                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1114                 if (enable)
1115                         tmp |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
1116                 else
1117                         tmp &= ~BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;
1118                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1119                 break;
1120         case FMAN_EX_BMI_DISPATCH_RAM_ECC:
1121                 tmp = ioread32be(&fman->bmi_regs->fmbm_ier);
1122                 if (enable)
1123                         tmp |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
1124                 else
1125                         tmp &= ~BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;
1126                 iowrite32be(tmp, &fman->bmi_regs->fmbm_ier);
1127                 break;
1128         case FMAN_EX_IRAM_ECC:
1129                 tmp = ioread32be(&fman->fpm_regs->fm_rie);
1130                 if (enable) {
1131                         /* enable ECC if not enabled */
1132                         enable_rams_ecc(fman->fpm_regs);
1133                         /* enable ECC interrupts */
1134                         tmp |= FPM_IRAM_ECC_ERR_EX_EN;
1135                 } else {
1136                         /* ECC mechanism may be disabled,
1137                          * depending on driver status
1138                          */
1139                         disable_rams_ecc(fman->fpm_regs);
1140                         tmp &= ~FPM_IRAM_ECC_ERR_EX_EN;
1141                 }
1142                 iowrite32be(tmp, &fman->fpm_regs->fm_rie);
1143                 break;
1144         case FMAN_EX_MURAM_ECC:
1145                 tmp = ioread32be(&fman->fpm_regs->fm_rie);
1146                 if (enable) {
1147                         /* enable ECC if not enabled */
1148                         enable_rams_ecc(fman->fpm_regs);
1149                         /* enable ECC interrupts */
1150                         tmp |= FPM_MURAM_ECC_ERR_EX_EN;
1151                 } else {
1152                         /* ECC mechanism may be disabled,
1153                          * depending on driver status
1154                          */
1155                         disable_rams_ecc(fman->fpm_regs);
1156                         tmp &= ~FPM_MURAM_ECC_ERR_EX_EN;
1157                 }
1158                 iowrite32be(tmp, &fman->fpm_regs->fm_rie);
1159                 break;
1160         default:
1161                 return -EINVAL;
1162         }
1163         return 0;
1164 }
1165
1166 static void resume(struct fman_fpm_regs __iomem *fpm_rg)
1167 {
1168         u32 tmp;
1169
1170         tmp = ioread32be(&fpm_rg->fmfp_ee);
1171         /* clear tmp_reg event bits in order not to clear standing events */
1172         tmp &= ~(FPM_EV_MASK_DOUBLE_ECC |
1173                  FPM_EV_MASK_STALL | FPM_EV_MASK_SINGLE_ECC);
1174         tmp |= FPM_EV_MASK_RELEASE_FM;
1175
1176         iowrite32be(tmp, &fpm_rg->fmfp_ee);
1177 }
1178
1179 static int fill_soc_specific_params(struct fman_state_struct *state)
1180 {
1181         u8 minor = state->rev_info.minor;
1182         /* P4080 - Major 2
1183          * P2041/P3041/P5020/P5040 - Major 3
1184          * Tx/Bx - Major 6
1185          */
1186         switch (state->rev_info.major) {
1187         case 3:
1188                 state->bmi_max_fifo_size        = 160 * 1024;
1189                 state->fm_iram_size             = 64 * 1024;
1190                 state->dma_thresh_max_commq     = 31;
1191                 state->dma_thresh_max_buf       = 127;
1192                 state->qmi_max_num_of_tnums     = 64;
1193                 state->qmi_def_tnums_thresh     = 48;
1194                 state->bmi_max_num_of_tasks     = 128;
1195                 state->max_num_of_open_dmas     = 32;
1196                 state->fm_port_num_of_cg        = 256;
1197                 state->num_of_rx_ports  = 6;
1198                 state->total_fifo_size  = 122 * 1024;
1199                 break;
1200
1201         case 2:
1202                 state->bmi_max_fifo_size        = 160 * 1024;
1203                 state->fm_iram_size             = 64 * 1024;
1204                 state->dma_thresh_max_commq     = 31;
1205                 state->dma_thresh_max_buf       = 127;
1206                 state->qmi_max_num_of_tnums     = 64;
1207                 state->qmi_def_tnums_thresh     = 48;
1208                 state->bmi_max_num_of_tasks     = 128;
1209                 state->max_num_of_open_dmas     = 32;
1210                 state->fm_port_num_of_cg        = 256;
1211                 state->num_of_rx_ports  = 5;
1212                 state->total_fifo_size  = 100 * 1024;
1213                 break;
1214
1215         case 6:
1216                 state->dma_thresh_max_commq     = 83;
1217                 state->dma_thresh_max_buf       = 127;
1218                 state->qmi_max_num_of_tnums     = 64;
1219                 state->qmi_def_tnums_thresh     = 32;
1220                 state->fm_port_num_of_cg        = 256;
1221
1222                 /* FManV3L */
1223                 if (minor == 1 || minor == 4) {
1224                         state->bmi_max_fifo_size        = 192 * 1024;
1225                         state->bmi_max_num_of_tasks     = 64;
1226                         state->max_num_of_open_dmas     = 32;
1227                         state->num_of_rx_ports          = 5;
1228                         if (minor == 1)
1229                                 state->fm_iram_size     = 32 * 1024;
1230                         else
1231                                 state->fm_iram_size     = 64 * 1024;
1232                         state->total_fifo_size          = 156 * 1024;
1233                 }
1234                 /* FManV3H */
1235                 else if (minor == 0 || minor == 2 || minor == 3) {
1236                         state->bmi_max_fifo_size        = 384 * 1024;
1237                         state->fm_iram_size             = 64 * 1024;
1238                         state->bmi_max_num_of_tasks     = 128;
1239                         state->max_num_of_open_dmas     = 84;
1240                         state->num_of_rx_ports          = 8;
1241                         state->total_fifo_size          = 295 * 1024;
1242                 } else {
1243                         pr_err("Unsupported FManv3 version\n");
1244                         return -EINVAL;
1245                 }
1246
1247                 break;
1248         default:
1249                 pr_err("Unsupported FMan version\n");
1250                 return -EINVAL;
1251         }
1252
1253         return 0;
1254 }
1255
1256 static bool is_init_done(struct fman_cfg *cfg)
1257 {
1258         /* Checks if FMan driver parameters were initialized */
1259         if (!cfg)
1260                 return true;
1261
1262         return false;
1263 }
1264
1265 static void free_init_resources(struct fman *fman)
1266 {
1267         if (fman->cam_offset)
1268                 fman_muram_free_mem(fman->muram, fman->cam_offset,
1269                                     fman->cam_size);
1270         if (fman->fifo_offset)
1271                 fman_muram_free_mem(fman->muram, fman->fifo_offset,
1272                                     fman->fifo_size);
1273 }
1274
1275 static irqreturn_t bmi_err_event(struct fman *fman)
1276 {
1277         u32 event, mask, force;
1278         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1279         irqreturn_t ret = IRQ_NONE;
1280
1281         event = ioread32be(&bmi_rg->fmbm_ievr);
1282         mask = ioread32be(&bmi_rg->fmbm_ier);
1283         event &= mask;
1284         /* clear the forced events */
1285         force = ioread32be(&bmi_rg->fmbm_ifr);
1286         if (force & event)
1287                 iowrite32be(force & ~event, &bmi_rg->fmbm_ifr);
1288         /* clear the acknowledged events */
1289         iowrite32be(event, &bmi_rg->fmbm_ievr);
1290
1291         if (event & BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC)
1292                 ret = fman->exception_cb(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC);
1293         if (event & BMI_ERR_INTR_EN_LIST_RAM_ECC)
1294                 ret = fman->exception_cb(fman, FMAN_EX_BMI_LIST_RAM_ECC);
1295         if (event & BMI_ERR_INTR_EN_STATISTICS_RAM_ECC)
1296                 ret = fman->exception_cb(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC);
1297         if (event & BMI_ERR_INTR_EN_DISPATCH_RAM_ECC)
1298                 ret = fman->exception_cb(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC);
1299
1300         return ret;
1301 }
1302
1303 static irqreturn_t qmi_err_event(struct fman *fman)
1304 {
1305         u32 event, mask, force;
1306         struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs;
1307         irqreturn_t ret = IRQ_NONE;
1308
1309         event = ioread32be(&qmi_rg->fmqm_eie);
1310         mask = ioread32be(&qmi_rg->fmqm_eien);
1311         event &= mask;
1312
1313         /* clear the forced events */
1314         force = ioread32be(&qmi_rg->fmqm_eif);
1315         if (force & event)
1316                 iowrite32be(force & ~event, &qmi_rg->fmqm_eif);
1317         /* clear the acknowledged events */
1318         iowrite32be(event, &qmi_rg->fmqm_eie);
1319
1320         if (event & QMI_ERR_INTR_EN_DOUBLE_ECC)
1321                 ret = fman->exception_cb(fman, FMAN_EX_QMI_DOUBLE_ECC);
1322         if (event & QMI_ERR_INTR_EN_DEQ_FROM_DEF)
1323                 ret = fman->exception_cb(fman,
1324                                          FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID);
1325
1326         return ret;
1327 }
1328
1329 static irqreturn_t dma_err_event(struct fman *fman)
1330 {
1331         u32 status, mask, com_id;
1332         u8 tnum, port_id, relative_port_id;
1333         u16 liodn;
1334         struct fman_dma_regs __iomem *dma_rg = fman->dma_regs;
1335         irqreturn_t ret = IRQ_NONE;
1336
1337         status = ioread32be(&dma_rg->fmdmsr);
1338         mask = ioread32be(&dma_rg->fmdmmr);
1339
1340         /* clear DMA_STATUS_BUS_ERR if mask has no DMA_MODE_BER */
1341         if ((mask & DMA_MODE_BER) != DMA_MODE_BER)
1342                 status &= ~DMA_STATUS_BUS_ERR;
1343
1344         /* clear relevant bits if mask has no DMA_MODE_ECC */
1345         if ((mask & DMA_MODE_ECC) != DMA_MODE_ECC)
1346                 status &= ~(DMA_STATUS_FM_SPDAT_ECC |
1347                             DMA_STATUS_READ_ECC |
1348                             DMA_STATUS_SYSTEM_WRITE_ECC |
1349                             DMA_STATUS_FM_WRITE_ECC);
1350
1351         /* clear set events */
1352         iowrite32be(status, &dma_rg->fmdmsr);
1353
1354         if (status & DMA_STATUS_BUS_ERR) {
1355                 u64 addr;
1356
1357                 addr = (u64)ioread32be(&dma_rg->fmdmtal);
1358                 addr |= ((u64)(ioread32be(&dma_rg->fmdmtah)) << 32);
1359
1360                 com_id = ioread32be(&dma_rg->fmdmtcid);
1361                 port_id = (u8)(((com_id & DMA_TRANSFER_PORTID_MASK) >>
1362                                DMA_TRANSFER_PORTID_SHIFT));
1363                 relative_port_id =
1364                 hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id);
1365                 tnum = (u8)((com_id & DMA_TRANSFER_TNUM_MASK) >>
1366                             DMA_TRANSFER_TNUM_SHIFT);
1367                 liodn = (u16)(com_id & DMA_TRANSFER_LIODN_MASK);
1368                 ret = fman->bus_error_cb(fman, relative_port_id, addr, tnum,
1369                                          liodn);
1370         }
1371         if (status & DMA_STATUS_FM_SPDAT_ECC)
1372                 ret = fman->exception_cb(fman, FMAN_EX_DMA_SINGLE_PORT_ECC);
1373         if (status & DMA_STATUS_READ_ECC)
1374                 ret = fman->exception_cb(fman, FMAN_EX_DMA_READ_ECC);
1375         if (status & DMA_STATUS_SYSTEM_WRITE_ECC)
1376                 ret = fman->exception_cb(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC);
1377         if (status & DMA_STATUS_FM_WRITE_ECC)
1378                 ret = fman->exception_cb(fman, FMAN_EX_DMA_FM_WRITE_ECC);
1379
1380         return ret;
1381 }
1382
1383 static irqreturn_t fpm_err_event(struct fman *fman)
1384 {
1385         u32 event;
1386         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1387         irqreturn_t ret = IRQ_NONE;
1388
1389         event = ioread32be(&fpm_rg->fmfp_ee);
1390         /* clear the all occurred events */
1391         iowrite32be(event, &fpm_rg->fmfp_ee);
1392
1393         if ((event & FPM_EV_MASK_DOUBLE_ECC) &&
1394             (event & FPM_EV_MASK_DOUBLE_ECC_EN))
1395                 ret = fman->exception_cb(fman, FMAN_EX_FPM_DOUBLE_ECC);
1396         if ((event & FPM_EV_MASK_STALL) && (event & FPM_EV_MASK_STALL_EN))
1397                 ret = fman->exception_cb(fman, FMAN_EX_FPM_STALL_ON_TASKS);
1398         if ((event & FPM_EV_MASK_SINGLE_ECC) &&
1399             (event & FPM_EV_MASK_SINGLE_ECC_EN))
1400                 ret = fman->exception_cb(fman, FMAN_EX_FPM_SINGLE_ECC);
1401
1402         return ret;
1403 }
1404
1405 static irqreturn_t muram_err_intr(struct fman *fman)
1406 {
1407         u32 event, mask;
1408         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1409         irqreturn_t ret = IRQ_NONE;
1410
1411         event = ioread32be(&fpm_rg->fm_rcr);
1412         mask = ioread32be(&fpm_rg->fm_rie);
1413
1414         /* clear MURAM event bit (do not clear IRAM event) */
1415         iowrite32be(event & ~FPM_RAM_IRAM_ECC, &fpm_rg->fm_rcr);
1416
1417         if ((mask & FPM_MURAM_ECC_ERR_EX_EN) && (event & FPM_RAM_MURAM_ECC))
1418                 ret = fman->exception_cb(fman, FMAN_EX_MURAM_ECC);
1419
1420         return ret;
1421 }
1422
1423 static irqreturn_t qmi_event(struct fman *fman)
1424 {
1425         u32 event, mask, force;
1426         struct fman_qmi_regs __iomem *qmi_rg = fman->qmi_regs;
1427         irqreturn_t ret = IRQ_NONE;
1428
1429         event = ioread32be(&qmi_rg->fmqm_ie);
1430         mask = ioread32be(&qmi_rg->fmqm_ien);
1431         event &= mask;
1432         /* clear the forced events */
1433         force = ioread32be(&qmi_rg->fmqm_if);
1434         if (force & event)
1435                 iowrite32be(force & ~event, &qmi_rg->fmqm_if);
1436         /* clear the acknowledged events */
1437         iowrite32be(event, &qmi_rg->fmqm_ie);
1438
1439         if (event & QMI_INTR_EN_SINGLE_ECC)
1440                 ret = fman->exception_cb(fman, FMAN_EX_QMI_SINGLE_ECC);
1441
1442         return ret;
1443 }
1444
1445 static void enable_time_stamp(struct fman *fman)
1446 {
1447         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
1448         u16 fm_clk_freq = fman->state->fm_clk_freq;
1449         u32 tmp, intgr, ts_freq, frac;
1450
1451         ts_freq = (u32)(1 << fman->state->count1_micro_bit);
1452         /* configure timestamp so that bit 8 will count 1 microsecond
1453          * Find effective count rate at TIMESTAMP least significant bits:
1454          * Effective_Count_Rate = 1MHz x 2^8 = 256MHz
1455          * Find frequency ratio between effective count rate and the clock:
1456          * Effective_Count_Rate / CLK e.g. for 600 MHz clock:
1457          * 256/600 = 0.4266666...
1458          */
1459
1460         intgr = ts_freq / fm_clk_freq;
1461         /* we multiply by 2^16 to keep the fraction of the division
1462          * we do not div back, since we write this value as a fraction
1463          * see spec
1464          */
1465
1466         frac = ((ts_freq << 16) - (intgr << 16) * fm_clk_freq) / fm_clk_freq;
1467         /* we check remainder of the division in order to round up if not int */
1468         if (((ts_freq << 16) - (intgr << 16) * fm_clk_freq) % fm_clk_freq)
1469                 frac++;
1470
1471         tmp = (intgr << FPM_TS_INT_SHIFT) | (u16)frac;
1472         iowrite32be(tmp, &fpm_rg->fmfp_tsc2);
1473
1474         /* enable timestamp with original clock */
1475         iowrite32be(FPM_TS_CTL_EN, &fpm_rg->fmfp_tsc1);
1476         fman->state->enabled_time_stamp = true;
1477 }
1478
1479 static int clear_iram(struct fman *fman)
1480 {
1481         struct fman_iram_regs __iomem *iram;
1482         int i, count;
1483
1484         iram = fman->base_addr + IMEM_OFFSET;
1485
1486         /* Enable the auto-increment */
1487         iowrite32be(IRAM_IADD_AIE, &iram->iadd);
1488         count = 100;
1489         do {
1490                 udelay(1);
1491         } while ((ioread32be(&iram->iadd) != IRAM_IADD_AIE) && --count);
1492         if (count == 0)
1493                 return -EBUSY;
1494
1495         for (i = 0; i < (fman->state->fm_iram_size / 4); i++)
1496                 iowrite32be(0xffffffff, &iram->idata);
1497
1498         iowrite32be(fman->state->fm_iram_size - 4, &iram->iadd);
1499         count = 100;
1500         do {
1501                 udelay(1);
1502         } while ((ioread32be(&iram->idata) != 0xffffffff) && --count);
1503         if (count == 0)
1504                 return -EBUSY;
1505
1506         return 0;
1507 }
1508
1509 static u32 get_exception_flag(enum fman_exceptions exception)
1510 {
1511         u32 bit_mask;
1512
1513         switch (exception) {
1514         case FMAN_EX_DMA_BUS_ERROR:
1515                 bit_mask = EX_DMA_BUS_ERROR;
1516                 break;
1517         case FMAN_EX_DMA_SINGLE_PORT_ECC:
1518                 bit_mask = EX_DMA_SINGLE_PORT_ECC;
1519                 break;
1520         case FMAN_EX_DMA_READ_ECC:
1521                 bit_mask = EX_DMA_READ_ECC;
1522                 break;
1523         case FMAN_EX_DMA_SYSTEM_WRITE_ECC:
1524                 bit_mask = EX_DMA_SYSTEM_WRITE_ECC;
1525                 break;
1526         case FMAN_EX_DMA_FM_WRITE_ECC:
1527                 bit_mask = EX_DMA_FM_WRITE_ECC;
1528                 break;
1529         case FMAN_EX_FPM_STALL_ON_TASKS:
1530                 bit_mask = EX_FPM_STALL_ON_TASKS;
1531                 break;
1532         case FMAN_EX_FPM_SINGLE_ECC:
1533                 bit_mask = EX_FPM_SINGLE_ECC;
1534                 break;
1535         case FMAN_EX_FPM_DOUBLE_ECC:
1536                 bit_mask = EX_FPM_DOUBLE_ECC;
1537                 break;
1538         case FMAN_EX_QMI_SINGLE_ECC:
1539                 bit_mask = EX_QMI_SINGLE_ECC;
1540                 break;
1541         case FMAN_EX_QMI_DOUBLE_ECC:
1542                 bit_mask = EX_QMI_DOUBLE_ECC;
1543                 break;
1544         case FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID:
1545                 bit_mask = EX_QMI_DEQ_FROM_UNKNOWN_PORTID;
1546                 break;
1547         case FMAN_EX_BMI_LIST_RAM_ECC:
1548                 bit_mask = EX_BMI_LIST_RAM_ECC;
1549                 break;
1550         case FMAN_EX_BMI_STORAGE_PROFILE_ECC:
1551                 bit_mask = EX_BMI_STORAGE_PROFILE_ECC;
1552                 break;
1553         case FMAN_EX_BMI_STATISTICS_RAM_ECC:
1554                 bit_mask = EX_BMI_STATISTICS_RAM_ECC;
1555                 break;
1556         case FMAN_EX_BMI_DISPATCH_RAM_ECC:
1557                 bit_mask = EX_BMI_DISPATCH_RAM_ECC;
1558                 break;
1559         case FMAN_EX_MURAM_ECC:
1560                 bit_mask = EX_MURAM_ECC;
1561                 break;
1562         default:
1563                 bit_mask = 0;
1564                 break;
1565         }
1566
1567         return bit_mask;
1568 }
1569
1570 static int get_module_event(enum fman_event_modules module, u8 mod_id,
1571                             enum fman_intr_type intr_type)
1572 {
1573         int event;
1574
1575         switch (module) {
1576         case FMAN_MOD_MAC:
1577                 if (intr_type == FMAN_INTR_TYPE_ERR)
1578                         event = FMAN_EV_ERR_MAC0 + mod_id;
1579                 else
1580                         event = FMAN_EV_MAC0 + mod_id;
1581                 break;
1582         case FMAN_MOD_FMAN_CTRL:
1583                 if (intr_type == FMAN_INTR_TYPE_ERR)
1584                         event = FMAN_EV_CNT;
1585                 else
1586                         event = (FMAN_EV_FMAN_CTRL_0 + mod_id);
1587                 break;
1588         case FMAN_MOD_DUMMY_LAST:
1589                 event = FMAN_EV_CNT;
1590                 break;
1591         default:
1592                 event = FMAN_EV_CNT;
1593                 break;
1594         }
1595
1596         return event;
1597 }
1598
1599 static int set_size_of_fifo(struct fman *fman, u8 port_id, u32 *size_of_fifo,
1600                             u32 *extra_size_of_fifo)
1601 {
1602         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1603         u32 fifo = *size_of_fifo;
1604         u32 extra_fifo = *extra_size_of_fifo;
1605         u32 tmp;
1606
1607         /* if this is the first time a port requires extra_fifo_pool_size,
1608          * the total extra_fifo_pool_size must be initialized to 1 buffer per
1609          * port
1610          */
1611         if (extra_fifo && !fman->state->extra_fifo_pool_size)
1612                 fman->state->extra_fifo_pool_size =
1613                         fman->state->num_of_rx_ports * FMAN_BMI_FIFO_UNITS;
1614
1615         fman->state->extra_fifo_pool_size =
1616                 max(fman->state->extra_fifo_pool_size, extra_fifo);
1617
1618         /* check that there are enough uncommitted fifo size */
1619         if ((fman->state->accumulated_fifo_size + fifo) >
1620             (fman->state->total_fifo_size -
1621             fman->state->extra_fifo_pool_size)) {
1622                 dev_err(fman->dev, "%s: Requested fifo size and extra size exceed total FIFO size.\n",
1623                         __func__);
1624                 return -EAGAIN;
1625         }
1626
1627         /* Read, modify and write to HW */
1628         tmp = (fifo / FMAN_BMI_FIFO_UNITS - 1) |
1629                ((extra_fifo / FMAN_BMI_FIFO_UNITS) <<
1630                BMI_EXTRA_FIFO_SIZE_SHIFT);
1631         iowrite32be(tmp, &bmi_rg->fmbm_pfs[port_id - 1]);
1632
1633         /* update accumulated */
1634         fman->state->accumulated_fifo_size += fifo;
1635
1636         return 0;
1637 }
1638
1639 static int set_num_of_tasks(struct fman *fman, u8 port_id, u8 *num_of_tasks,
1640                             u8 *num_of_extra_tasks)
1641 {
1642         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1643         u8 tasks = *num_of_tasks;
1644         u8 extra_tasks = *num_of_extra_tasks;
1645         u32 tmp;
1646
1647         if (extra_tasks)
1648                 fman->state->extra_tasks_pool_size =
1649                 max(fman->state->extra_tasks_pool_size, extra_tasks);
1650
1651         /* check that there are enough uncommitted tasks */
1652         if ((fman->state->accumulated_num_of_tasks + tasks) >
1653             (fman->state->total_num_of_tasks -
1654              fman->state->extra_tasks_pool_size)) {
1655                 dev_err(fman->dev, "%s: Requested num_of_tasks and extra tasks pool for fm%d exceed total num_of_tasks.\n",
1656                         __func__, fman->state->fm_id);
1657                 return -EAGAIN;
1658         }
1659         /* update accumulated */
1660         fman->state->accumulated_num_of_tasks += tasks;
1661
1662         /* Write to HW */
1663         tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) &
1664             ~(BMI_NUM_OF_TASKS_MASK | BMI_NUM_OF_EXTRA_TASKS_MASK);
1665         tmp |= ((u32)((tasks - 1) << BMI_NUM_OF_TASKS_SHIFT) |
1666                 (u32)(extra_tasks << BMI_EXTRA_NUM_OF_TASKS_SHIFT));
1667         iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]);
1668
1669         return 0;
1670 }
1671
1672 static int set_num_of_open_dmas(struct fman *fman, u8 port_id,
1673                                 u8 *num_of_open_dmas,
1674                                 u8 *num_of_extra_open_dmas)
1675 {
1676         struct fman_bmi_regs __iomem *bmi_rg = fman->bmi_regs;
1677         u8 open_dmas = *num_of_open_dmas;
1678         u8 extra_open_dmas = *num_of_extra_open_dmas;
1679         u8 total_num_dmas = 0, current_val = 0, current_extra_val = 0;
1680         u32 tmp;
1681
1682         if (!open_dmas) {
1683                 /* Configuration according to values in the HW.
1684                  * read the current number of open Dma's
1685                  */
1686                 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
1687                 current_extra_val = (u8)((tmp & BMI_NUM_OF_EXTRA_DMAS_MASK) >>
1688                                          BMI_EXTRA_NUM_OF_DMAS_SHIFT);
1689
1690                 tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]);
1691                 current_val = (u8)(((tmp & BMI_NUM_OF_DMAS_MASK) >>
1692                                    BMI_NUM_OF_DMAS_SHIFT) + 1);
1693
1694                 /* This is the first configuration and user did not
1695                  * specify value (!open_dmas), reset values will be used
1696                  * and we just save these values for resource management
1697                  */
1698                 fman->state->extra_open_dmas_pool_size =
1699                         (u8)max(fman->state->extra_open_dmas_pool_size,
1700                                 current_extra_val);
1701                 fman->state->accumulated_num_of_open_dmas += current_val;
1702                 *num_of_open_dmas = current_val;
1703                 *num_of_extra_open_dmas = current_extra_val;
1704                 return 0;
1705         }
1706
1707         if (extra_open_dmas > current_extra_val)
1708                 fman->state->extra_open_dmas_pool_size =
1709                     (u8)max(fman->state->extra_open_dmas_pool_size,
1710                             extra_open_dmas);
1711
1712         if ((fman->state->rev_info.major < 6) &&
1713             (fman->state->accumulated_num_of_open_dmas - current_val +
1714              open_dmas > fman->state->max_num_of_open_dmas)) {
1715                 dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds total num_of_open_dmas.\n",
1716                         __func__, fman->state->fm_id);
1717                 return -EAGAIN;
1718         } else if ((fman->state->rev_info.major >= 6) &&
1719                    !((fman->state->rev_info.major == 6) &&
1720                    (fman->state->rev_info.minor == 0)) &&
1721                    (fman->state->accumulated_num_of_open_dmas -
1722                    current_val + open_dmas >
1723                    fman->state->dma_thresh_max_commq + 1)) {
1724                 dev_err(fman->dev, "%s: Requested num_of_open_dmas for fm%d exceeds DMA Command queue (%d)\n",
1725                         __func__, fman->state->fm_id,
1726                        fman->state->dma_thresh_max_commq + 1);
1727                 return -EAGAIN;
1728         }
1729
1730         WARN_ON(fman->state->accumulated_num_of_open_dmas < current_val);
1731         /* update acummulated */
1732         fman->state->accumulated_num_of_open_dmas -= current_val;
1733         fman->state->accumulated_num_of_open_dmas += open_dmas;
1734
1735         if (fman->state->rev_info.major < 6)
1736                 total_num_dmas =
1737                     (u8)(fman->state->accumulated_num_of_open_dmas +
1738                     fman->state->extra_open_dmas_pool_size);
1739
1740         /* calculate reg */
1741         tmp = ioread32be(&bmi_rg->fmbm_pp[port_id - 1]) &
1742             ~(BMI_NUM_OF_DMAS_MASK | BMI_NUM_OF_EXTRA_DMAS_MASK);
1743         tmp |= (u32)(((open_dmas - 1) << BMI_NUM_OF_DMAS_SHIFT) |
1744                            (extra_open_dmas << BMI_EXTRA_NUM_OF_DMAS_SHIFT));
1745         iowrite32be(tmp, &bmi_rg->fmbm_pp[port_id - 1]);
1746
1747         /* update total num of DMA's with committed number of open DMAS,
1748          * and max uncommitted pool.
1749          */
1750         if (total_num_dmas) {
1751                 tmp = ioread32be(&bmi_rg->fmbm_cfg2) & ~BMI_CFG2_DMAS_MASK;
1752                 tmp |= (u32)(total_num_dmas - 1) << BMI_CFG2_DMAS_SHIFT;
1753                 iowrite32be(tmp, &bmi_rg->fmbm_cfg2);
1754         }
1755
1756         return 0;
1757 }
1758
1759 static int fman_config(struct fman *fman)
1760 {
1761         void __iomem *base_addr;
1762         int err;
1763
1764         base_addr = fman->dts_params.base_addr;
1765
1766         fman->state = kzalloc(sizeof(*fman->state), GFP_KERNEL);
1767         if (!fman->state)
1768                 goto err_fm_state;
1769
1770         /* Allocate the FM driver's parameters structure */
1771         fman->cfg = kzalloc(sizeof(*fman->cfg), GFP_KERNEL);
1772         if (!fman->cfg)
1773                 goto err_fm_drv;
1774
1775         /* Initialize MURAM block */
1776         fman->muram =
1777                 fman_muram_init(fman->dts_params.muram_res.start,
1778                                 resource_size(&fman->dts_params.muram_res));
1779         if (!fman->muram)
1780                 goto err_fm_soc_specific;
1781
1782         /* Initialize FM parameters which will be kept by the driver */
1783         fman->state->fm_id = fman->dts_params.id;
1784         fman->state->fm_clk_freq = fman->dts_params.clk_freq;
1785         fman->state->qman_channel_base = fman->dts_params.qman_channel_base;
1786         fman->state->num_of_qman_channels =
1787                 fman->dts_params.num_of_qman_channels;
1788         fman->state->res = fman->dts_params.res;
1789         fman->exception_cb = fman_exceptions;
1790         fman->bus_error_cb = fman_bus_error;
1791         fman->fpm_regs = base_addr + FPM_OFFSET;
1792         fman->bmi_regs = base_addr + BMI_OFFSET;
1793         fman->qmi_regs = base_addr + QMI_OFFSET;
1794         fman->dma_regs = base_addr + DMA_OFFSET;
1795         fman->base_addr = base_addr;
1796
1797         spin_lock_init(&fman->spinlock);
1798         fman_defconfig(fman->cfg);
1799
1800         fman->state->extra_fifo_pool_size = 0;
1801         fman->state->exceptions = (EX_DMA_BUS_ERROR                 |
1802                                         EX_DMA_READ_ECC              |
1803                                         EX_DMA_SYSTEM_WRITE_ECC      |
1804                                         EX_DMA_FM_WRITE_ECC          |
1805                                         EX_FPM_STALL_ON_TASKS        |
1806                                         EX_FPM_SINGLE_ECC            |
1807                                         EX_FPM_DOUBLE_ECC            |
1808                                         EX_QMI_DEQ_FROM_UNKNOWN_PORTID |
1809                                         EX_BMI_LIST_RAM_ECC          |
1810                                         EX_BMI_STORAGE_PROFILE_ECC   |
1811                                         EX_BMI_STATISTICS_RAM_ECC    |
1812                                         EX_MURAM_ECC                 |
1813                                         EX_BMI_DISPATCH_RAM_ECC      |
1814                                         EX_QMI_DOUBLE_ECC            |
1815                                         EX_QMI_SINGLE_ECC);
1816
1817         /* Read FMan revision for future use*/
1818         fman_get_revision(fman, &fman->state->rev_info);
1819
1820         err = fill_soc_specific_params(fman->state);
1821         if (err)
1822                 goto err_fm_soc_specific;
1823
1824         /* FM_AID_MODE_NO_TNUM_SW005 Errata workaround */
1825         if (fman->state->rev_info.major >= 6)
1826                 fman->cfg->dma_aid_mode = FMAN_DMA_AID_OUT_PORT_ID;
1827
1828         fman->cfg->qmi_def_tnums_thresh = fman->state->qmi_def_tnums_thresh;
1829
1830         fman->state->total_num_of_tasks =
1831         (u8)DFLT_TOTAL_NUM_OF_TASKS(fman->state->rev_info.major,
1832                                     fman->state->rev_info.minor,
1833                                     fman->state->bmi_max_num_of_tasks);
1834
1835         if (fman->state->rev_info.major < 6) {
1836                 fman->cfg->dma_comm_qtsh_clr_emer =
1837                 (u8)DFLT_DMA_COMM_Q_LOW(fman->state->rev_info.major,
1838                                         fman->state->dma_thresh_max_commq);
1839
1840                 fman->cfg->dma_comm_qtsh_asrt_emer =
1841                 (u8)DFLT_DMA_COMM_Q_HIGH(fman->state->rev_info.major,
1842                                          fman->state->dma_thresh_max_commq);
1843
1844                 fman->cfg->dma_cam_num_of_entries =
1845                 DFLT_DMA_CAM_NUM_OF_ENTRIES(fman->state->rev_info.major);
1846
1847                 fman->cfg->dma_read_buf_tsh_clr_emer =
1848                 DFLT_DMA_READ_INT_BUF_LOW(fman->state->dma_thresh_max_buf);
1849
1850                 fman->cfg->dma_read_buf_tsh_asrt_emer =
1851                 DFLT_DMA_READ_INT_BUF_HIGH(fman->state->dma_thresh_max_buf);
1852
1853                 fman->cfg->dma_write_buf_tsh_clr_emer =
1854                 DFLT_DMA_WRITE_INT_BUF_LOW(fman->state->dma_thresh_max_buf);
1855
1856                 fman->cfg->dma_write_buf_tsh_asrt_emer =
1857                 DFLT_DMA_WRITE_INT_BUF_HIGH(fman->state->dma_thresh_max_buf);
1858
1859                 fman->cfg->dma_axi_dbg_num_of_beats =
1860                 DFLT_AXI_DBG_NUM_OF_BEATS;
1861         }
1862
1863         return 0;
1864
1865 err_fm_soc_specific:
1866         kfree(fman->cfg);
1867 err_fm_drv:
1868         kfree(fman->state);
1869 err_fm_state:
1870         kfree(fman);
1871         return -EINVAL;
1872 }
1873
1874 static int fman_reset(struct fman *fman)
1875 {
1876         u32 count;
1877         int err = 0;
1878
1879         if (fman->state->rev_info.major < 6) {
1880                 iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc);
1881                 /* Wait for reset completion */
1882                 count = 100;
1883                 do {
1884                         udelay(1);
1885                 } while (((ioread32be(&fman->fpm_regs->fm_rstc)) &
1886                          FPM_RSTC_FM_RESET) && --count);
1887                 if (count == 0)
1888                         err = -EBUSY;
1889
1890                 goto _return;
1891         } else {
1892                 struct device_node *guts_node;
1893                 struct ccsr_guts __iomem *guts_regs;
1894                 u32 devdisr2, reg;
1895
1896                 /* Errata A007273 */
1897                 guts_node =
1898                         of_find_compatible_node(NULL, NULL,
1899                                                 "fsl,qoriq-device-config-2.0");
1900                 if (!guts_node) {
1901                         dev_err(fman->dev, "%s: Couldn't find guts node\n",
1902                                 __func__);
1903                         goto guts_node;
1904                 }
1905
1906                 guts_regs = of_iomap(guts_node, 0);
1907                 if (!guts_regs) {
1908                         dev_err(fman->dev, "%s: Couldn't map %s regs\n",
1909                                 __func__, guts_node->full_name);
1910                         goto guts_regs;
1911                 }
1912 #define FMAN1_ALL_MACS_MASK     0xFCC00000
1913 #define FMAN2_ALL_MACS_MASK     0x000FCC00
1914                 /* Read current state */
1915                 devdisr2 = ioread32be(&guts_regs->devdisr2);
1916                 if (fman->dts_params.id == 0)
1917                         reg = devdisr2 & ~FMAN1_ALL_MACS_MASK;
1918                 else
1919                         reg = devdisr2 & ~FMAN2_ALL_MACS_MASK;
1920
1921                 /* Enable all MACs */
1922                 iowrite32be(reg, &guts_regs->devdisr2);
1923
1924                 /* Perform FMan reset */
1925                 iowrite32be(FPM_RSTC_FM_RESET, &fman->fpm_regs->fm_rstc);
1926
1927                 /* Wait for reset completion */
1928                 count = 100;
1929                 do {
1930                         udelay(1);
1931                 } while (((ioread32be(&fman->fpm_regs->fm_rstc)) &
1932                          FPM_RSTC_FM_RESET) && --count);
1933                 if (count == 0) {
1934                         iounmap(guts_regs);
1935                         of_node_put(guts_node);
1936                         err = -EBUSY;
1937                         goto _return;
1938                 }
1939
1940                 /* Restore devdisr2 value */
1941                 iowrite32be(devdisr2, &guts_regs->devdisr2);
1942
1943                 iounmap(guts_regs);
1944                 of_node_put(guts_node);
1945
1946                 goto _return;
1947
1948 guts_regs:
1949                 of_node_put(guts_node);
1950 guts_node:
1951                 dev_dbg(fman->dev, "%s: Didn't perform FManV3 reset due to Errata A007273!\n",
1952                         __func__);
1953         }
1954 _return:
1955         return err;
1956 }
1957
1958 static int fman_init(struct fman *fman)
1959 {
1960         struct fman_cfg *cfg = NULL;
1961         int err = 0, i, count;
1962
1963         if (is_init_done(fman->cfg))
1964                 return -EINVAL;
1965
1966         fman->state->count1_micro_bit = FM_TIMESTAMP_1_USEC_BIT;
1967
1968         cfg = fman->cfg;
1969
1970         /* clear revision-dependent non existing exception */
1971         if (fman->state->rev_info.major < 6)
1972                 fman->state->exceptions &= ~FMAN_EX_BMI_DISPATCH_RAM_ECC;
1973
1974         if (fman->state->rev_info.major >= 6)
1975                 fman->state->exceptions &= ~FMAN_EX_QMI_SINGLE_ECC;
1976
1977         /* clear CPG */
1978         memset_io((void __iomem *)(fman->base_addr + CGP_OFFSET), 0,
1979                   fman->state->fm_port_num_of_cg);
1980
1981         /* Save LIODN info before FMan reset
1982          * Skipping non-existent port 0 (i = 1)
1983          */
1984         for (i = 1; i < FMAN_LIODN_TBL; i++) {
1985                 u32 liodn_base;
1986
1987                 fman->liodn_offset[i] =
1988                         ioread32be(&fman->bmi_regs->fmbm_spliodn[i - 1]);
1989                 liodn_base = ioread32be(&fman->dma_regs->fmdmplr[i / 2]);
1990                 if (i % 2) {
1991                         /* FMDM_PLR LSB holds LIODN base for odd ports */
1992                         liodn_base &= DMA_LIODN_BASE_MASK;
1993                 } else {
1994                         /* FMDM_PLR MSB holds LIODN base for even ports */
1995                         liodn_base >>= DMA_LIODN_SHIFT;
1996                         liodn_base &= DMA_LIODN_BASE_MASK;
1997                 }
1998                 fman->liodn_base[i] = liodn_base;
1999         }
2000
2001         err = fman_reset(fman);
2002         if (err)
2003                 return err;
2004
2005         if (ioread32be(&fman->qmi_regs->fmqm_gs) & QMI_GS_HALT_NOT_BUSY) {
2006                 resume(fman->fpm_regs);
2007                 /* Wait until QMI is not in halt not busy state */
2008                 count = 100;
2009                 do {
2010                         udelay(1);
2011                 } while (((ioread32be(&fman->qmi_regs->fmqm_gs)) &
2012                          QMI_GS_HALT_NOT_BUSY) && --count);
2013                 if (count == 0)
2014                         dev_warn(fman->dev, "%s: QMI is in halt not busy state\n",
2015                                  __func__);
2016         }
2017
2018         if (clear_iram(fman) != 0)
2019                 return -EINVAL;
2020
2021         cfg->exceptions = fman->state->exceptions;
2022
2023         /* Init DMA Registers */
2024
2025         err = dma_init(fman);
2026         if (err != 0) {
2027                 free_init_resources(fman);
2028                 return err;
2029         }
2030
2031         /* Init FPM Registers */
2032         fpm_init(fman->fpm_regs, fman->cfg);
2033
2034         /* define common resources */
2035         /* allocate MURAM for FIFO according to total size */
2036         fman->fifo_offset = fman_muram_alloc(fman->muram,
2037                                              fman->state->total_fifo_size);
2038         if (IS_ERR_VALUE(fman->fifo_offset)) {
2039                 free_init_resources(fman);
2040                 dev_err(fman->dev, "%s: MURAM alloc for BMI FIFO failed\n",
2041                         __func__);
2042                 return -ENOMEM;
2043         }
2044
2045         cfg->fifo_base_addr = fman->fifo_offset;
2046         cfg->total_fifo_size = fman->state->total_fifo_size;
2047         cfg->total_num_of_tasks = fman->state->total_num_of_tasks;
2048         cfg->clk_freq = fman->state->fm_clk_freq;
2049
2050         /* Init BMI Registers */
2051         bmi_init(fman->bmi_regs, fman->cfg);
2052
2053         /* Init QMI Registers */
2054         qmi_init(fman->qmi_regs, fman->cfg);
2055
2056         err = enable(fman, cfg);
2057         if (err != 0)
2058                 return err;
2059
2060         enable_time_stamp(fman);
2061
2062         kfree(fman->cfg);
2063         fman->cfg = NULL;
2064
2065         return 0;
2066 }
2067
2068 static int fman_set_exception(struct fman *fman,
2069                               enum fman_exceptions exception, bool enable)
2070 {
2071         u32 bit_mask = 0;
2072
2073         if (!is_init_done(fman->cfg))
2074                 return -EINVAL;
2075
2076         bit_mask = get_exception_flag(exception);
2077         if (bit_mask) {
2078                 if (enable)
2079                         fman->state->exceptions |= bit_mask;
2080                 else
2081                         fman->state->exceptions &= ~bit_mask;
2082         } else {
2083                 dev_err(fman->dev, "%s: Undefined exception (%d)\n",
2084                         __func__, exception);
2085                 return -EINVAL;
2086         }
2087
2088         return set_exception(fman, exception, enable);
2089 }
2090
2091 /**
2092  * fman_register_intr
2093  * @fman:       A Pointer to FMan device
2094  * @mod:        Calling module
2095  * @mod_id:     Module id (if more than 1 exists, '0' if not)
2096  * @intr_type:  Interrupt type (error/normal) selection.
2097  * @f_isr:      The interrupt service routine.
2098  * @h_src_arg:  Argument to be passed to f_isr.
2099  *
2100  * Used to register an event handler to be processed by FMan
2101  *
2102  * Return: 0 on success; Error code otherwise.
2103  */
2104 void fman_register_intr(struct fman *fman, enum fman_event_modules module,
2105                         u8 mod_id, enum fman_intr_type intr_type,
2106                         void (*isr_cb)(void *src_arg), void *src_arg)
2107 {
2108         int event = 0;
2109
2110         event = get_module_event(module, mod_id, intr_type);
2111         WARN_ON(event >= FMAN_EV_CNT);
2112
2113         /* register in local FM structure */
2114         fman->intr_mng[event].isr_cb = isr_cb;
2115         fman->intr_mng[event].src_handle = src_arg;
2116 }
2117 EXPORT_SYMBOL(fman_register_intr);
2118
2119 /**
2120  * fman_unregister_intr
2121  * @fman:       A Pointer to FMan device
2122  * @mod:        Calling module
2123  * @mod_id:     Module id (if more than 1 exists, '0' if not)
2124  * @intr_type:  Interrupt type (error/normal) selection.
2125  *
2126  * Used to unregister an event handler to be processed by FMan
2127  *
2128  * Return: 0 on success; Error code otherwise.
2129  */
2130 void fman_unregister_intr(struct fman *fman, enum fman_event_modules module,
2131                           u8 mod_id, enum fman_intr_type intr_type)
2132 {
2133         int event = 0;
2134
2135         event = get_module_event(module, mod_id, intr_type);
2136         WARN_ON(event >= FMAN_EV_CNT);
2137
2138         fman->intr_mng[event].isr_cb = NULL;
2139         fman->intr_mng[event].src_handle = NULL;
2140 }
2141 EXPORT_SYMBOL(fman_unregister_intr);
2142
2143 /**
2144  * fman_set_port_params
2145  * @fman:               A Pointer to FMan device
2146  * @port_params:        Port parameters
2147  *
2148  * Used by FMan Port to pass parameters to the FMan
2149  *
2150  * Return: 0 on success; Error code otherwise.
2151  */
2152 int fman_set_port_params(struct fman *fman,
2153                          struct fman_port_init_params *port_params)
2154 {
2155         int err;
2156         unsigned long flags;
2157         u8 port_id = port_params->port_id, mac_id;
2158
2159         spin_lock_irqsave(&fman->spinlock, flags);
2160
2161         err = set_num_of_tasks(fman, port_params->port_id,
2162                                &port_params->num_of_tasks,
2163                                &port_params->num_of_extra_tasks);
2164         if (err)
2165                 goto return_err;
2166
2167         /* TX Ports */
2168         if (port_params->port_type != FMAN_PORT_TYPE_RX) {
2169                 u32 enq_th, deq_th, reg;
2170
2171                 /* update qmi ENQ/DEQ threshold */
2172                 fman->state->accumulated_num_of_deq_tnums +=
2173                         port_params->deq_pipeline_depth;
2174                 enq_th = (ioread32be(&fman->qmi_regs->fmqm_gc) &
2175                           QMI_CFG_ENQ_MASK) >> QMI_CFG_ENQ_SHIFT;
2176                 /* if enq_th is too big, we reduce it to the max value
2177                  * that is still 0
2178                  */
2179                 if (enq_th >= (fman->state->qmi_max_num_of_tnums -
2180                     fman->state->accumulated_num_of_deq_tnums)) {
2181                         enq_th =
2182                         fman->state->qmi_max_num_of_tnums -
2183                         fman->state->accumulated_num_of_deq_tnums - 1;
2184
2185                         reg = ioread32be(&fman->qmi_regs->fmqm_gc);
2186                         reg &= ~QMI_CFG_ENQ_MASK;
2187                         reg |= (enq_th << QMI_CFG_ENQ_SHIFT);
2188                         iowrite32be(reg, &fman->qmi_regs->fmqm_gc);
2189                 }
2190
2191                 deq_th = ioread32be(&fman->qmi_regs->fmqm_gc) &
2192                                     QMI_CFG_DEQ_MASK;
2193                 /* if deq_th is too small, we enlarge it to the min
2194                  * value that is still 0.
2195                  * depTh may not be larger than 63
2196                  * (fman->state->qmi_max_num_of_tnums-1).
2197                  */
2198                 if ((deq_th <= fman->state->accumulated_num_of_deq_tnums) &&
2199                     (deq_th < fman->state->qmi_max_num_of_tnums - 1)) {
2200                         deq_th = fman->state->accumulated_num_of_deq_tnums + 1;
2201                         reg = ioread32be(&fman->qmi_regs->fmqm_gc);
2202                         reg &= ~QMI_CFG_DEQ_MASK;
2203                         reg |= deq_th;
2204                         iowrite32be(reg, &fman->qmi_regs->fmqm_gc);
2205                 }
2206         }
2207
2208         err = set_size_of_fifo(fman, port_params->port_id,
2209                                &port_params->size_of_fifo,
2210                                &port_params->extra_size_of_fifo);
2211         if (err)
2212                 goto return_err;
2213
2214         err = set_num_of_open_dmas(fman, port_params->port_id,
2215                                    &port_params->num_of_open_dmas,
2216                                    &port_params->num_of_extra_open_dmas);
2217         if (err)
2218                 goto return_err;
2219
2220         set_port_liodn(fman, port_id, fman->liodn_base[port_id],
2221                        fman->liodn_offset[port_id]);
2222
2223         if (fman->state->rev_info.major < 6)
2224                 set_port_order_restoration(fman->fpm_regs, port_id);
2225
2226         mac_id = hw_port_id_to_sw_port_id(fman->state->rev_info.major, port_id);
2227
2228         if (port_params->max_frame_length >= fman->state->mac_mfl[mac_id]) {
2229                 fman->state->port_mfl[mac_id] = port_params->max_frame_length;
2230         } else {
2231                 dev_warn(fman->dev, "%s: Port (%d) max_frame_length is smaller than MAC (%d) current MTU\n",
2232                          __func__, port_id, mac_id);
2233                 err = -EINVAL;
2234                 goto return_err;
2235         }
2236
2237         spin_unlock_irqrestore(&fman->spinlock, flags);
2238
2239         return 0;
2240
2241 return_err:
2242         spin_unlock_irqrestore(&fman->spinlock, flags);
2243         return err;
2244 }
2245 EXPORT_SYMBOL(fman_set_port_params);
2246
2247 /**
2248  * fman_reset_mac
2249  * @fman:       A Pointer to FMan device
2250  * @mac_id:     MAC id to be reset
2251  *
2252  * Reset a specific MAC
2253  *
2254  * Return: 0 on success; Error code otherwise.
2255  */
2256 int fman_reset_mac(struct fman *fman, u8 mac_id)
2257 {
2258         struct fman_fpm_regs __iomem *fpm_rg = fman->fpm_regs;
2259         u32 msk, timeout = 100;
2260
2261         if (fman->state->rev_info.major >= 6) {
2262                 dev_err(fman->dev, "%s: FMan MAC reset no available for FMan V3!\n",
2263                         __func__);
2264                 return -EINVAL;
2265         }
2266
2267         /* Get the relevant bit mask */
2268         switch (mac_id) {
2269         case 0:
2270                 msk = FPM_RSTC_MAC0_RESET;
2271                 break;
2272         case 1:
2273                 msk = FPM_RSTC_MAC1_RESET;
2274                 break;
2275         case 2:
2276                 msk = FPM_RSTC_MAC2_RESET;
2277                 break;
2278         case 3:
2279                 msk = FPM_RSTC_MAC3_RESET;
2280                 break;
2281         case 4:
2282                 msk = FPM_RSTC_MAC4_RESET;
2283                 break;
2284         case 5:
2285                 msk = FPM_RSTC_MAC5_RESET;
2286                 break;
2287         case 6:
2288                 msk = FPM_RSTC_MAC6_RESET;
2289                 break;
2290         case 7:
2291                 msk = FPM_RSTC_MAC7_RESET;
2292                 break;
2293         case 8:
2294                 msk = FPM_RSTC_MAC8_RESET;
2295                 break;
2296         case 9:
2297                 msk = FPM_RSTC_MAC9_RESET;
2298                 break;
2299         default:
2300                 dev_warn(fman->dev, "%s: Illegal MAC Id [%d]\n",
2301                          __func__, mac_id);
2302                 return -EINVAL;
2303         }
2304
2305         /* reset */
2306         iowrite32be(msk, &fpm_rg->fm_rstc);
2307         while ((ioread32be(&fpm_rg->fm_rstc) & msk) && --timeout)
2308                 udelay(10);
2309
2310         if (!timeout)
2311                 return -EIO;
2312
2313         return 0;
2314 }
2315 EXPORT_SYMBOL(fman_reset_mac);
2316
2317 /**
2318  * fman_set_mac_max_frame
2319  * @fman:       A Pointer to FMan device
2320  * @mac_id:     MAC id
2321  * @mfl:        Maximum frame length
2322  *
2323  * Set maximum frame length of specific MAC in FMan driver
2324  *
2325  * Return: 0 on success; Error code otherwise.
2326  */
2327 int fman_set_mac_max_frame(struct fman *fman, u8 mac_id, u16 mfl)
2328 {
2329         /* if port is already initialized, check that MaxFrameLength is smaller
2330          * or equal to the port's max
2331          */
2332         if ((!fman->state->port_mfl[mac_id]) ||
2333             (mfl <= fman->state->port_mfl[mac_id])) {
2334                 fman->state->mac_mfl[mac_id] = mfl;
2335         } else {
2336                 dev_warn(fman->dev, "%s: MAC max_frame_length is larger than Port max_frame_length\n",
2337                          __func__);
2338                 return -EINVAL;
2339         }
2340         return 0;
2341 }
2342 EXPORT_SYMBOL(fman_set_mac_max_frame);
2343
2344 /**
2345  * fman_get_clock_freq
2346  * @fman:       A Pointer to FMan device
2347  *
2348  * Get FMan clock frequency
2349  *
2350  * Return: FMan clock frequency
2351  */
2352 u16 fman_get_clock_freq(struct fman *fman)
2353 {
2354         return fman->state->fm_clk_freq;
2355 }
2356
2357 /**
2358  * fman_get_bmi_max_fifo_size
2359  * @fman:       A Pointer to FMan device
2360  *
2361  * Get FMan maximum FIFO size
2362  *
2363  * Return: FMan Maximum FIFO size
2364  */
2365 u32 fman_get_bmi_max_fifo_size(struct fman *fman)
2366 {
2367         return fman->state->bmi_max_fifo_size;
2368 }
2369 EXPORT_SYMBOL(fman_get_bmi_max_fifo_size);
2370
2371 /**
2372  * fman_get_revision
2373  * @fman                - Pointer to the FMan module
2374  * @rev_info            - A structure of revision information parameters.
2375  *
2376  * Returns the FM revision
2377  *
2378  * Allowed only following fman_init().
2379  *
2380  * Return: 0 on success; Error code otherwise.
2381  */
2382 void fman_get_revision(struct fman *fman, struct fman_rev_info *rev_info)
2383 {
2384         u32 tmp;
2385
2386         tmp = ioread32be(&fman->fpm_regs->fm_ip_rev_1);
2387         rev_info->major = (u8)((tmp & FPM_REV1_MAJOR_MASK) >>
2388                                 FPM_REV1_MAJOR_SHIFT);
2389         rev_info->minor = tmp & FPM_REV1_MINOR_MASK;
2390 }
2391 EXPORT_SYMBOL(fman_get_revision);
2392
2393 /**
2394  * fman_get_qman_channel_id
2395  * @fman:       A Pointer to FMan device
2396  * @port_id:    Port id
2397  *
2398  * Get QMan channel ID associated to the Port id
2399  *
2400  * Return: QMan channel ID
2401  */
2402 u32 fman_get_qman_channel_id(struct fman *fman, u32 port_id)
2403 {
2404         int i;
2405
2406         if (fman->state->rev_info.major >= 6) {
2407                 u32 port_ids[] = {0x30, 0x31, 0x28, 0x29, 0x2a, 0x2b,
2408                                   0x2c, 0x2d, 0x2, 0x3, 0x4, 0x5, 0x7, 0x7};
2409                 for (i = 0; i < fman->state->num_of_qman_channels; i++) {
2410                         if (port_ids[i] == port_id)
2411                                 break;
2412                 }
2413         } else {
2414                 u32 port_ids[] = {0x30, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x1,
2415                                   0x2, 0x3, 0x4, 0x5, 0x7, 0x7};
2416                 for (i = 0; i < fman->state->num_of_qman_channels; i++) {
2417                         if (port_ids[i] == port_id)
2418                                 break;
2419                 }
2420         }
2421
2422         if (i == fman->state->num_of_qman_channels)
2423                 return 0;
2424
2425         return fman->state->qman_channel_base + i;
2426 }
2427 EXPORT_SYMBOL(fman_get_qman_channel_id);
2428
2429 /**
2430  * fman_get_mem_region
2431  * @fman:       A Pointer to FMan device
2432  *
2433  * Get FMan memory region
2434  *
2435  * Return: A structure with FMan memory region information
2436  */
2437 struct resource *fman_get_mem_region(struct fman *fman)
2438 {
2439         return fman->state->res;
2440 }
2441 EXPORT_SYMBOL(fman_get_mem_region);
2442
2443 /* Bootargs defines */
2444 /* Extra headroom for RX buffers - Default, min and max */
2445 #define FSL_FM_RX_EXTRA_HEADROOM        64
2446 #define FSL_FM_RX_EXTRA_HEADROOM_MIN    16
2447 #define FSL_FM_RX_EXTRA_HEADROOM_MAX    384
2448
2449 /* Maximum frame length */
2450 #define FSL_FM_MAX_FRAME_SIZE                   1522
2451 #define FSL_FM_MAX_POSSIBLE_FRAME_SIZE          9600
2452 #define FSL_FM_MIN_POSSIBLE_FRAME_SIZE          64
2453
2454 /* Extra headroom for Rx buffers.
2455  * FMan is instructed to allocate, on the Rx path, this amount of
2456  * space at the beginning of a data buffer, beside the DPA private
2457  * data area and the IC fields.
2458  * Does not impact Tx buffer layout.
2459  * Configurable from bootargs. 64 by default, it's needed on
2460  * particular forwarding scenarios that add extra headers to the
2461  * forwarded frame.
2462  */
2463 static int fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM;
2464 module_param(fsl_fm_rx_extra_headroom, int, 0);
2465 MODULE_PARM_DESC(fsl_fm_rx_extra_headroom, "Extra headroom for Rx buffers");
2466
2467 /* Max frame size, across all interfaces.
2468  * Configurable from bootargs, to avoid allocating oversized (socket)
2469  * buffers when not using jumbo frames.
2470  * Must be large enough to accommodate the network MTU, but small enough
2471  * to avoid wasting skb memory.
2472  *
2473  * Could be overridden once, at boot-time, via the
2474  * fm_set_max_frm() callback.
2475  */
2476 static int fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE;
2477 module_param(fsl_fm_max_frm, int, 0);
2478 MODULE_PARM_DESC(fsl_fm_max_frm, "Maximum frame size, across all interfaces");
2479
2480 /**
2481  * fman_get_max_frm
2482  *
2483  * Return: Max frame length configured in the FM driver
2484  */
2485 u16 fman_get_max_frm(void)
2486 {
2487         static bool fm_check_mfl;
2488
2489         if (!fm_check_mfl) {
2490                 if (fsl_fm_max_frm > FSL_FM_MAX_POSSIBLE_FRAME_SIZE ||
2491                     fsl_fm_max_frm < FSL_FM_MIN_POSSIBLE_FRAME_SIZE) {
2492                         pr_warn("Invalid fsl_fm_max_frm value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n",
2493                                 fsl_fm_max_frm,
2494                                 FSL_FM_MIN_POSSIBLE_FRAME_SIZE,
2495                                 FSL_FM_MAX_POSSIBLE_FRAME_SIZE,
2496                                 FSL_FM_MAX_FRAME_SIZE);
2497                         fsl_fm_max_frm = FSL_FM_MAX_FRAME_SIZE;
2498                 }
2499                 fm_check_mfl = true;
2500         }
2501
2502         return fsl_fm_max_frm;
2503 }
2504 EXPORT_SYMBOL(fman_get_max_frm);
2505
2506 /**
2507  * fman_get_rx_extra_headroom
2508  *
2509  * Return: Extra headroom size configured in the FM driver
2510  */
2511 int fman_get_rx_extra_headroom(void)
2512 {
2513         static bool fm_check_rx_extra_headroom;
2514
2515         if (!fm_check_rx_extra_headroom) {
2516                 if (fsl_fm_rx_extra_headroom > FSL_FM_RX_EXTRA_HEADROOM_MAX ||
2517                     fsl_fm_rx_extra_headroom < FSL_FM_RX_EXTRA_HEADROOM_MIN) {
2518                         pr_warn("Invalid fsl_fm_rx_extra_headroom value (%d) in bootargs, valid range is %d-%d. Falling back to the default (%d)\n",
2519                                 fsl_fm_rx_extra_headroom,
2520                                 FSL_FM_RX_EXTRA_HEADROOM_MIN,
2521                                 FSL_FM_RX_EXTRA_HEADROOM_MAX,
2522                                 FSL_FM_RX_EXTRA_HEADROOM);
2523                         fsl_fm_rx_extra_headroom = FSL_FM_RX_EXTRA_HEADROOM;
2524                 }
2525
2526                 fm_check_rx_extra_headroom = true;
2527                 fsl_fm_rx_extra_headroom = ALIGN(fsl_fm_rx_extra_headroom, 16);
2528         }
2529
2530         return fsl_fm_rx_extra_headroom;
2531 }
2532 EXPORT_SYMBOL(fman_get_rx_extra_headroom);
2533
2534 /**
2535  * fman_bind
2536  * @dev:        FMan OF device pointer
2537  *
2538  * Bind to a specific FMan device.
2539  *
2540  * Allowed only after the port was created.
2541  *
2542  * Return: A pointer to the FMan device
2543  */
2544 struct fman *fman_bind(struct device *fm_dev)
2545 {
2546         return (struct fman *)(dev_get_drvdata(get_device(fm_dev)));
2547 }
2548 EXPORT_SYMBOL(fman_bind);
2549
2550 static irqreturn_t fman_err_irq(int irq, void *handle)
2551 {
2552         struct fman *fman = (struct fman *)handle;
2553         u32 pending;
2554         struct fman_fpm_regs __iomem *fpm_rg;
2555         irqreturn_t single_ret, ret = IRQ_NONE;
2556
2557         if (!is_init_done(fman->cfg))
2558                 return IRQ_NONE;
2559
2560         fpm_rg = fman->fpm_regs;
2561
2562         /* error interrupts */
2563         pending = ioread32be(&fpm_rg->fm_epi);
2564         if (!pending)
2565                 return IRQ_NONE;
2566
2567         if (pending & ERR_INTR_EN_BMI) {
2568                 single_ret = bmi_err_event(fman);
2569                 if (single_ret == IRQ_HANDLED)
2570                         ret = IRQ_HANDLED;
2571         }
2572         if (pending & ERR_INTR_EN_QMI) {
2573                 single_ret = qmi_err_event(fman);
2574                 if (single_ret == IRQ_HANDLED)
2575                         ret = IRQ_HANDLED;
2576         }
2577         if (pending & ERR_INTR_EN_FPM) {
2578                 single_ret = fpm_err_event(fman);
2579                 if (single_ret == IRQ_HANDLED)
2580                         ret = IRQ_HANDLED;
2581         }
2582         if (pending & ERR_INTR_EN_DMA) {
2583                 single_ret = dma_err_event(fman);
2584                 if (single_ret == IRQ_HANDLED)
2585                         ret = IRQ_HANDLED;
2586         }
2587         if (pending & ERR_INTR_EN_MURAM) {
2588                 single_ret = muram_err_intr(fman);
2589                 if (single_ret == IRQ_HANDLED)
2590                         ret = IRQ_HANDLED;
2591         }
2592
2593         /* MAC error interrupts */
2594         if (pending & ERR_INTR_EN_MAC0) {
2595                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 0);
2596                 if (single_ret == IRQ_HANDLED)
2597                         ret = IRQ_HANDLED;
2598         }
2599         if (pending & ERR_INTR_EN_MAC1) {
2600                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 1);
2601                 if (single_ret == IRQ_HANDLED)
2602                         ret = IRQ_HANDLED;
2603         }
2604         if (pending & ERR_INTR_EN_MAC2) {
2605                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 2);
2606                 if (single_ret == IRQ_HANDLED)
2607                         ret = IRQ_HANDLED;
2608         }
2609         if (pending & ERR_INTR_EN_MAC3) {
2610                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 3);
2611                 if (single_ret == IRQ_HANDLED)
2612                         ret = IRQ_HANDLED;
2613         }
2614         if (pending & ERR_INTR_EN_MAC4) {
2615                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 4);
2616                 if (single_ret == IRQ_HANDLED)
2617                         ret = IRQ_HANDLED;
2618         }
2619         if (pending & ERR_INTR_EN_MAC5) {
2620                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 5);
2621                 if (single_ret == IRQ_HANDLED)
2622                         ret = IRQ_HANDLED;
2623         }
2624         if (pending & ERR_INTR_EN_MAC6) {
2625                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 6);
2626                 if (single_ret == IRQ_HANDLED)
2627                         ret = IRQ_HANDLED;
2628         }
2629         if (pending & ERR_INTR_EN_MAC7) {
2630                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 7);
2631                 if (single_ret == IRQ_HANDLED)
2632                         ret = IRQ_HANDLED;
2633         }
2634         if (pending & ERR_INTR_EN_MAC8) {
2635                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 8);
2636                 if (single_ret == IRQ_HANDLED)
2637                         ret = IRQ_HANDLED;
2638         }
2639         if (pending & ERR_INTR_EN_MAC9) {
2640                 single_ret = call_mac_isr(fman, FMAN_EV_ERR_MAC0 + 9);
2641                 if (single_ret == IRQ_HANDLED)
2642                         ret = IRQ_HANDLED;
2643         }
2644
2645         return ret;
2646 }
2647
2648 static irqreturn_t fman_irq(int irq, void *handle)
2649 {
2650         struct fman *fman = (struct fman *)handle;
2651         u32 pending;
2652         struct fman_fpm_regs __iomem *fpm_rg;
2653         irqreturn_t single_ret, ret = IRQ_NONE;
2654
2655         if (!is_init_done(fman->cfg))
2656                 return IRQ_NONE;
2657
2658         fpm_rg = fman->fpm_regs;
2659
2660         /* normal interrupts */
2661         pending = ioread32be(&fpm_rg->fm_npi);
2662         if (!pending)
2663                 return IRQ_NONE;
2664
2665         if (pending & INTR_EN_QMI) {
2666                 single_ret = qmi_event(fman);
2667                 if (single_ret == IRQ_HANDLED)
2668                         ret = IRQ_HANDLED;
2669         }
2670
2671         /* MAC interrupts */
2672         if (pending & INTR_EN_MAC0) {
2673                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 0);
2674                 if (single_ret == IRQ_HANDLED)
2675                         ret = IRQ_HANDLED;
2676         }
2677         if (pending & INTR_EN_MAC1) {
2678                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 1);
2679                 if (single_ret == IRQ_HANDLED)
2680                         ret = IRQ_HANDLED;
2681         }
2682         if (pending & INTR_EN_MAC2) {
2683                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 2);
2684                 if (single_ret == IRQ_HANDLED)
2685                         ret = IRQ_HANDLED;
2686         }
2687         if (pending & INTR_EN_MAC3) {
2688                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 3);
2689                 if (single_ret == IRQ_HANDLED)
2690                         ret = IRQ_HANDLED;
2691         }
2692         if (pending & INTR_EN_MAC4) {
2693                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 4);
2694                 if (single_ret == IRQ_HANDLED)
2695                         ret = IRQ_HANDLED;
2696         }
2697         if (pending & INTR_EN_MAC5) {
2698                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 5);
2699                 if (single_ret == IRQ_HANDLED)
2700                         ret = IRQ_HANDLED;
2701         }
2702         if (pending & INTR_EN_MAC6) {
2703                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 6);
2704                 if (single_ret == IRQ_HANDLED)
2705                         ret = IRQ_HANDLED;
2706         }
2707         if (pending & INTR_EN_MAC7) {
2708                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 7);
2709                 if (single_ret == IRQ_HANDLED)
2710                         ret = IRQ_HANDLED;
2711         }
2712         if (pending & INTR_EN_MAC8) {
2713                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 8);
2714                 if (single_ret == IRQ_HANDLED)
2715                         ret = IRQ_HANDLED;
2716         }
2717         if (pending & INTR_EN_MAC9) {
2718                 single_ret = call_mac_isr(fman, FMAN_EV_MAC0 + 9);
2719                 if (single_ret == IRQ_HANDLED)
2720                         ret = IRQ_HANDLED;
2721         }
2722
2723         return ret;
2724 }
2725
2726 static const struct of_device_id fman_muram_match[] = {
2727         {
2728                 .compatible = "fsl,fman-muram"},
2729         {}
2730 };
2731 MODULE_DEVICE_TABLE(of, fman_muram_match);
2732
2733 static struct fman *read_dts_node(struct platform_device *of_dev)
2734 {
2735         struct fman *fman;
2736         struct device_node *fm_node, *muram_node;
2737         struct resource *res;
2738         u32 val, range[2];
2739         int err, irq;
2740         struct clk *clk;
2741         u32 clk_rate;
2742         phys_addr_t phys_base_addr;
2743         resource_size_t mem_size;
2744
2745         fman = kzalloc(sizeof(*fman), GFP_KERNEL);
2746         if (!fman)
2747                 return NULL;
2748
2749         fm_node = of_node_get(of_dev->dev.of_node);
2750
2751         err = of_property_read_u32(fm_node, "cell-index", &val);
2752         if (err) {
2753                 dev_err(&of_dev->dev, "%s: failed to read cell-index for %s\n",
2754                         __func__, fm_node->full_name);
2755                 goto fman_node_put;
2756         }
2757         fman->dts_params.id = (u8)val;
2758
2759         /* Get the FM interrupt */
2760         res = platform_get_resource(of_dev, IORESOURCE_IRQ, 0);
2761         if (!res) {
2762                 dev_err(&of_dev->dev, "%s: Can't get FMan IRQ resource\n",
2763                         __func__);
2764                 goto fman_node_put;
2765         }
2766         irq = res->start;
2767
2768         /* Get the FM error interrupt */
2769         res = platform_get_resource(of_dev, IORESOURCE_IRQ, 1);
2770         if (!res) {
2771                 dev_err(&of_dev->dev, "%s: Can't get FMan Error IRQ resource\n",
2772                         __func__);
2773                 goto fman_node_put;
2774         }
2775         fman->dts_params.err_irq = res->start;
2776
2777         /* Get the FM address */
2778         res = platform_get_resource(of_dev, IORESOURCE_MEM, 0);
2779         if (!res) {
2780                 dev_err(&of_dev->dev, "%s: Can't get FMan memory resource\n",
2781                         __func__);
2782                 goto fman_node_put;
2783         }
2784
2785         phys_base_addr = res->start;
2786         mem_size = resource_size(res);
2787
2788         clk = of_clk_get(fm_node, 0);
2789         if (IS_ERR(clk)) {
2790                 dev_err(&of_dev->dev, "%s: Failed to get FM%d clock structure\n",
2791                         __func__, fman->dts_params.id);
2792                 goto fman_node_put;
2793         }
2794
2795         clk_rate = clk_get_rate(clk);
2796         if (!clk_rate) {
2797                 dev_err(&of_dev->dev, "%s: Failed to determine FM%d clock rate\n",
2798                         __func__, fman->dts_params.id);
2799                 goto fman_node_put;
2800         }
2801         /* Rounding to MHz */
2802         fman->dts_params.clk_freq = DIV_ROUND_UP(clk_rate, 1000000);
2803
2804         err = of_property_read_u32_array(fm_node, "fsl,qman-channel-range",
2805                                          &range[0], 2);
2806         if (err) {
2807                 dev_err(&of_dev->dev, "%s: failed to read fsl,qman-channel-range for %s\n",
2808                         __func__, fm_node->full_name);
2809                 goto fman_node_put;
2810         }
2811         fman->dts_params.qman_channel_base = range[0];
2812         fman->dts_params.num_of_qman_channels = range[1];
2813
2814         /* Get the MURAM base address and size */
2815         muram_node = of_find_matching_node(fm_node, fman_muram_match);
2816         if (!muram_node) {
2817                 dev_err(&of_dev->dev, "%s: could not find MURAM node\n",
2818                         __func__);
2819                 goto fman_free;
2820         }
2821
2822         err = of_address_to_resource(muram_node, 0,
2823                                      &fman->dts_params.muram_res);
2824         if (err) {
2825                 of_node_put(muram_node);
2826                 dev_err(&of_dev->dev, "%s: of_address_to_resource() = %d\n",
2827                         __func__, err);
2828                 goto fman_free;
2829         }
2830
2831         of_node_put(muram_node);
2832
2833         err = devm_request_irq(&of_dev->dev, irq, fman_irq, 0, "fman", fman);
2834         if (err < 0) {
2835                 dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n",
2836                         __func__, irq, err);
2837                 goto fman_free;
2838         }
2839
2840         if (fman->dts_params.err_irq != 0) {
2841                 err = devm_request_irq(&of_dev->dev, fman->dts_params.err_irq,
2842                                        fman_err_irq, IRQF_SHARED,
2843                                        "fman-err", fman);
2844                 if (err < 0) {
2845                         dev_err(&of_dev->dev, "%s: irq %d allocation failed (error = %d)\n",
2846                                 __func__, fman->dts_params.err_irq, err);
2847                         goto fman_free;
2848                 }
2849         }
2850
2851         fman->dts_params.res =
2852                 devm_request_mem_region(&of_dev->dev, phys_base_addr,
2853                                         mem_size, "fman");
2854         if (!fman->dts_params.res) {
2855                 dev_err(&of_dev->dev, "%s: request_mem_region() failed\n",
2856                         __func__);
2857                 goto fman_free;
2858         }
2859
2860         fman->dts_params.base_addr =
2861                 devm_ioremap(&of_dev->dev, phys_base_addr, mem_size);
2862         if (!fman->dts_params.base_addr) {
2863                 dev_err(&of_dev->dev, "%s: devm_ioremap() failed\n", __func__);
2864                 goto fman_free;
2865         }
2866
2867         fman->dev = &of_dev->dev;
2868
2869         return fman;
2870
2871 fman_node_put:
2872         of_node_put(fm_node);
2873 fman_free:
2874         kfree(fman);
2875         return NULL;
2876 }
2877
2878 static int fman_probe(struct platform_device *of_dev)
2879 {
2880         struct fman *fman;
2881         struct device *dev;
2882         int err;
2883
2884         dev = &of_dev->dev;
2885
2886         fman = read_dts_node(of_dev);
2887         if (!fman)
2888                 return -EIO;
2889
2890         err = fman_config(fman);
2891         if (err) {
2892                 dev_err(dev, "%s: FMan config failed\n", __func__);
2893                 return -EINVAL;
2894         }
2895
2896         if (fman_init(fman) != 0) {
2897                 dev_err(dev, "%s: FMan init failed\n", __func__);
2898                 return -EINVAL;
2899         }
2900
2901         if (fman->dts_params.err_irq == 0) {
2902                 fman_set_exception(fman, FMAN_EX_DMA_BUS_ERROR, false);
2903                 fman_set_exception(fman, FMAN_EX_DMA_READ_ECC, false);
2904                 fman_set_exception(fman, FMAN_EX_DMA_SYSTEM_WRITE_ECC, false);
2905                 fman_set_exception(fman, FMAN_EX_DMA_FM_WRITE_ECC, false);
2906                 fman_set_exception(fman, FMAN_EX_DMA_SINGLE_PORT_ECC, false);
2907                 fman_set_exception(fman, FMAN_EX_FPM_STALL_ON_TASKS, false);
2908                 fman_set_exception(fman, FMAN_EX_FPM_SINGLE_ECC, false);
2909                 fman_set_exception(fman, FMAN_EX_FPM_DOUBLE_ECC, false);
2910                 fman_set_exception(fman, FMAN_EX_QMI_SINGLE_ECC, false);
2911                 fman_set_exception(fman, FMAN_EX_QMI_DOUBLE_ECC, false);
2912                 fman_set_exception(fman,
2913                                    FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID, false);
2914                 fman_set_exception(fman, FMAN_EX_BMI_LIST_RAM_ECC, false);
2915                 fman_set_exception(fman, FMAN_EX_BMI_STORAGE_PROFILE_ECC,
2916                                    false);
2917                 fman_set_exception(fman, FMAN_EX_BMI_STATISTICS_RAM_ECC, false);
2918                 fman_set_exception(fman, FMAN_EX_BMI_DISPATCH_RAM_ECC, false);
2919         }
2920
2921         dev_set_drvdata(dev, fman);
2922
2923         dev_dbg(dev, "FMan%d probed\n", fman->dts_params.id);
2924
2925         return 0;
2926 }
2927
2928 static const struct of_device_id fman_match[] = {
2929         {
2930                 .compatible = "fsl,fman"},
2931         {}
2932 };
2933
2934 MODULE_DEVICE_TABLE(of, fman_match);
2935
2936 static struct platform_driver fman_driver = {
2937         .driver = {
2938                 .name = "fsl-fman",
2939                 .of_match_table = fman_match,
2940         },
2941         .probe = fman_probe,
2942 };
2943
2944 static int __init fman_load(void)
2945 {
2946         int err;
2947
2948         pr_debug("FSL DPAA FMan driver\n");
2949
2950         err = platform_driver_register(&fman_driver);
2951         if (err < 0)
2952                 pr_err("Error, platform_driver_register() = %d\n", err);
2953
2954         return err;
2955 }
2956 module_init(fman_load);
2957
2958 static void __exit fman_unload(void)
2959 {
2960         platform_driver_unregister(&fman_driver);
2961 }
2962 module_exit(fman_unload);
2963
2964 MODULE_LICENSE("Dual BSD/GPL");
2965 MODULE_DESCRIPTION("Freescale DPAA Frame Manager driver");