1 // SPDX-License-Identifier: GPL-2.0+
3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
6 * Right now, I am very wasteful with the buffers. I allocate memory
7 * pages and then divide them into 2K frame buffers. This way I know I
8 * have buffers large enough to hold one frame within one buffer descriptor.
9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10 * will be much more memory efficient and will easily handle lots of
13 * Much better multiple PHY support by Magnus Damm.
14 * Copyright (c) 2000 Ericsson Radio Systems AB.
16 * Support for FEC controller of ColdFire processors.
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/ptrace.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/icmp.h>
45 #include <linux/spinlock.h>
46 #include <linux/workqueue.h>
47 #include <linux/bitops.h>
49 #include <linux/irq.h>
50 #include <linux/clk.h>
51 #include <linux/crc32.h>
52 #include <linux/platform_device.h>
53 #include <linux/mdio.h>
54 #include <linux/phy.h>
55 #include <linux/fec.h>
57 #include <linux/of_device.h>
58 #include <linux/of_gpio.h>
59 #include <linux/of_mdio.h>
60 #include <linux/of_net.h>
61 #include <linux/regulator/consumer.h>
62 #include <linux/if_vlan.h>
63 #include <linux/pinctrl/consumer.h>
64 #include <linux/prefetch.h>
65 #include <linux/mfd/syscon.h>
66 #include <linux/regmap.h>
67 #include <soc/imx/cpuidle.h>
69 #include <asm/cacheflush.h>
73 static void set_multicast_list(struct net_device *ndev);
74 static void fec_enet_itr_coal_init(struct net_device *ndev);
76 #define DRIVER_NAME "fec"
78 static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2};
80 /* Pause frame feild and FIFO threshold */
81 #define FEC_ENET_FCE (1 << 5)
82 #define FEC_ENET_RSEM_V 0x84
83 #define FEC_ENET_RSFL_V 16
84 #define FEC_ENET_RAEM_V 0x8
85 #define FEC_ENET_RAFL_V 0x8
86 #define FEC_ENET_OPD_V 0xFFF0
87 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
93 static const struct fec_devinfo fec_imx25_info = {
94 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
98 static const struct fec_devinfo fec_imx27_info = {
99 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG,
102 static const struct fec_devinfo fec_imx28_info = {
103 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
104 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
105 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII,
108 static const struct fec_devinfo fec_imx6q_info = {
109 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
110 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
111 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
112 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII,
115 static const struct fec_devinfo fec_mvf600_info = {
116 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
119 static const struct fec_devinfo fec_imx6x_info = {
120 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
121 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
122 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
123 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
124 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
125 FEC_QUIRK_CLEAR_SETUP_MII,
128 static const struct fec_devinfo fec_imx6ul_info = {
129 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
130 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
131 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
132 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
133 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII,
136 static struct platform_device_id fec_devtype[] = {
138 /* keep it for coldfire */
143 .driver_data = (kernel_ulong_t)&fec_imx25_info,
146 .driver_data = (kernel_ulong_t)&fec_imx27_info,
149 .driver_data = (kernel_ulong_t)&fec_imx28_info,
152 .driver_data = (kernel_ulong_t)&fec_imx6q_info,
154 .name = "mvf600-fec",
155 .driver_data = (kernel_ulong_t)&fec_mvf600_info,
157 .name = "imx6sx-fec",
158 .driver_data = (kernel_ulong_t)&fec_imx6x_info,
160 .name = "imx6ul-fec",
161 .driver_data = (kernel_ulong_t)&fec_imx6ul_info,
166 MODULE_DEVICE_TABLE(platform, fec_devtype);
169 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
170 IMX27_FEC, /* runs on i.mx27/35/51 */
178 static const struct of_device_id fec_dt_ids[] = {
179 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
180 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
181 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
182 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
183 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
184 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
185 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
188 MODULE_DEVICE_TABLE(of, fec_dt_ids);
190 static unsigned char macaddr[ETH_ALEN];
191 module_param_array(macaddr, byte, NULL, 0);
192 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
194 #if defined(CONFIG_M5272)
196 * Some hardware gets it MAC address out of local flash memory.
197 * if this is non-zero then assume it is the address to get MAC from.
199 #if defined(CONFIG_NETtel)
200 #define FEC_FLASHMAC 0xf0006006
201 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
202 #define FEC_FLASHMAC 0xf0006000
203 #elif defined(CONFIG_CANCam)
204 #define FEC_FLASHMAC 0xf0020000
205 #elif defined (CONFIG_M5272C3)
206 #define FEC_FLASHMAC (0xffe04000 + 4)
207 #elif defined(CONFIG_MOD5272)
208 #define FEC_FLASHMAC 0xffc0406b
210 #define FEC_FLASHMAC 0
212 #endif /* CONFIG_M5272 */
214 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
216 * 2048 byte skbufs are allocated. However, alignment requirements
217 * varies between FEC variants. Worst case is 64, so round down by 64.
219 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
220 #define PKT_MINBUF_SIZE 64
222 /* FEC receive acceleration */
223 #define FEC_RACC_IPDIS (1 << 1)
224 #define FEC_RACC_PRODIS (1 << 2)
225 #define FEC_RACC_SHIFT16 BIT(7)
226 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
228 /* MIB Control Register */
229 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
232 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
233 * size bits. Other FEC hardware does not, so we need to take that into
234 * account when setting it.
236 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
237 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
238 defined(CONFIG_ARM64)
239 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
241 #define OPT_FRAME_SIZE 0
244 /* FEC MII MMFR bits definition */
245 #define FEC_MMFR_ST (1 << 30)
246 #define FEC_MMFR_ST_C45 (0)
247 #define FEC_MMFR_OP_READ (2 << 28)
248 #define FEC_MMFR_OP_READ_C45 (3 << 28)
249 #define FEC_MMFR_OP_WRITE (1 << 28)
250 #define FEC_MMFR_OP_ADDR_WRITE (0)
251 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
252 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
253 #define FEC_MMFR_TA (2 << 16)
254 #define FEC_MMFR_DATA(v) (v & 0xffff)
255 /* FEC ECR bits definition */
256 #define FEC_ECR_MAGICEN (1 << 2)
257 #define FEC_ECR_SLEEP (1 << 3)
259 #define FEC_MII_TIMEOUT 30000 /* us */
261 /* Transmitter timeout */
262 #define TX_TIMEOUT (2 * HZ)
264 #define FEC_PAUSE_FLAG_AUTONEG 0x1
265 #define FEC_PAUSE_FLAG_ENABLE 0x2
266 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
267 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
268 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
270 #define COPYBREAK_DEFAULT 256
272 /* Max number of allowed TCP segments for software TSO */
273 #define FEC_MAX_TSO_SEGS 100
274 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
276 #define IS_TSO_HEADER(txq, addr) \
277 ((addr >= txq->tso_hdrs_dma) && \
278 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
282 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
283 struct bufdesc_prop *bd)
285 return (bdp >= bd->last) ? bd->base
286 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
289 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
290 struct bufdesc_prop *bd)
292 return (bdp <= bd->base) ? bd->last
293 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
296 static int fec_enet_get_bd_index(struct bufdesc *bdp,
297 struct bufdesc_prop *bd)
299 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
302 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
306 entries = (((const char *)txq->dirty_tx -
307 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
309 return entries >= 0 ? entries : entries + txq->bd.ring_size;
312 static void swap_buffer(void *bufaddr, int len)
315 unsigned int *buf = bufaddr;
317 for (i = 0; i < len; i += 4, buf++)
321 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
324 unsigned int *src = src_buf;
325 unsigned int *dst = dst_buf;
327 for (i = 0; i < len; i += 4, src++, dst++)
331 static void fec_dump(struct net_device *ndev)
333 struct fec_enet_private *fep = netdev_priv(ndev);
335 struct fec_enet_priv_tx_q *txq;
338 netdev_info(ndev, "TX ring dump\n");
339 pr_info("Nr SC addr len SKB\n");
341 txq = fep->tx_queue[0];
345 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
347 bdp == txq->bd.cur ? 'S' : ' ',
348 bdp == txq->dirty_tx ? 'H' : ' ',
349 fec16_to_cpu(bdp->cbd_sc),
350 fec32_to_cpu(bdp->cbd_bufaddr),
351 fec16_to_cpu(bdp->cbd_datlen),
352 txq->tx_skbuff[index]);
353 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
355 } while (bdp != txq->bd.base);
358 static inline bool is_ipv4_pkt(struct sk_buff *skb)
360 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
364 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
366 /* Only run for packets requiring a checksum. */
367 if (skb->ip_summed != CHECKSUM_PARTIAL)
370 if (unlikely(skb_cow_head(skb, 0)))
373 if (is_ipv4_pkt(skb))
374 ip_hdr(skb)->check = 0;
375 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
380 static struct bufdesc *
381 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
383 struct net_device *ndev)
385 struct fec_enet_private *fep = netdev_priv(ndev);
386 struct bufdesc *bdp = txq->bd.cur;
387 struct bufdesc_ex *ebdp;
388 int nr_frags = skb_shinfo(skb)->nr_frags;
390 unsigned short status;
391 unsigned int estatus = 0;
392 skb_frag_t *this_frag;
398 for (frag = 0; frag < nr_frags; frag++) {
399 this_frag = &skb_shinfo(skb)->frags[frag];
400 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
401 ebdp = (struct bufdesc_ex *)bdp;
403 status = fec16_to_cpu(bdp->cbd_sc);
404 status &= ~BD_ENET_TX_STATS;
405 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
406 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]);
408 /* Handle the last BD specially */
409 if (frag == nr_frags - 1) {
410 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
411 if (fep->bufdesc_ex) {
412 estatus |= BD_ENET_TX_INT;
413 if (unlikely(skb_shinfo(skb)->tx_flags &
414 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
415 estatus |= BD_ENET_TX_TS;
419 if (fep->bufdesc_ex) {
420 if (fep->quirks & FEC_QUIRK_HAS_AVB)
421 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
422 if (skb->ip_summed == CHECKSUM_PARTIAL)
423 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
425 ebdp->cbd_esc = cpu_to_fec32(estatus);
428 bufaddr = skb_frag_address(this_frag);
430 index = fec_enet_get_bd_index(bdp, &txq->bd);
431 if (((unsigned long) bufaddr) & fep->tx_align ||
432 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
433 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
434 bufaddr = txq->tx_bounce[index];
436 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
437 swap_buffer(bufaddr, frag_len);
440 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
442 if (dma_mapping_error(&fep->pdev->dev, addr)) {
444 netdev_err(ndev, "Tx DMA memory map failed\n");
445 goto dma_mapping_error;
448 bdp->cbd_bufaddr = cpu_to_fec32(addr);
449 bdp->cbd_datlen = cpu_to_fec16(frag_len);
450 /* Make sure the updates to rest of the descriptor are
451 * performed before transferring ownership.
454 bdp->cbd_sc = cpu_to_fec16(status);
460 for (i = 0; i < frag; i++) {
461 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
462 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
463 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
465 return ERR_PTR(-ENOMEM);
468 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
469 struct sk_buff *skb, struct net_device *ndev)
471 struct fec_enet_private *fep = netdev_priv(ndev);
472 int nr_frags = skb_shinfo(skb)->nr_frags;
473 struct bufdesc *bdp, *last_bdp;
476 unsigned short status;
477 unsigned short buflen;
478 unsigned int estatus = 0;
482 entries_free = fec_enet_get_free_txdesc_num(txq);
483 if (entries_free < MAX_SKB_FRAGS + 1) {
484 dev_kfree_skb_any(skb);
486 netdev_err(ndev, "NOT enough BD for SG!\n");
490 /* Protocol checksum off-load for TCP and UDP. */
491 if (fec_enet_clear_csum(skb, ndev)) {
492 dev_kfree_skb_any(skb);
496 /* Fill in a Tx ring entry */
499 status = fec16_to_cpu(bdp->cbd_sc);
500 status &= ~BD_ENET_TX_STATS;
502 /* Set buffer length and buffer pointer */
504 buflen = skb_headlen(skb);
506 index = fec_enet_get_bd_index(bdp, &txq->bd);
507 if (((unsigned long) bufaddr) & fep->tx_align ||
508 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
509 memcpy(txq->tx_bounce[index], skb->data, buflen);
510 bufaddr = txq->tx_bounce[index];
512 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
513 swap_buffer(bufaddr, buflen);
516 /* Push the data cache so the CPM does not get stale memory data. */
517 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
518 if (dma_mapping_error(&fep->pdev->dev, addr)) {
519 dev_kfree_skb_any(skb);
521 netdev_err(ndev, "Tx DMA memory map failed\n");
526 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
527 if (IS_ERR(last_bdp)) {
528 dma_unmap_single(&fep->pdev->dev, addr,
529 buflen, DMA_TO_DEVICE);
530 dev_kfree_skb_any(skb);
534 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
535 if (fep->bufdesc_ex) {
536 estatus = BD_ENET_TX_INT;
537 if (unlikely(skb_shinfo(skb)->tx_flags &
538 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
539 estatus |= BD_ENET_TX_TS;
542 bdp->cbd_bufaddr = cpu_to_fec32(addr);
543 bdp->cbd_datlen = cpu_to_fec16(buflen);
545 if (fep->bufdesc_ex) {
547 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
549 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
551 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
553 if (fep->quirks & FEC_QUIRK_HAS_AVB)
554 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
556 if (skb->ip_summed == CHECKSUM_PARTIAL)
557 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
560 ebdp->cbd_esc = cpu_to_fec32(estatus);
563 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
564 /* Save skb pointer */
565 txq->tx_skbuff[index] = skb;
567 /* Make sure the updates to rest of the descriptor are performed before
568 * transferring ownership.
572 /* Send it on its way. Tell FEC it's ready, interrupt when done,
573 * it's the last BD of the frame, and to put the CRC on the end.
575 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
576 bdp->cbd_sc = cpu_to_fec16(status);
578 /* If this was the last BD in the ring, start at the beginning again. */
579 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
581 skb_tx_timestamp(skb);
583 /* Make sure the update to bdp and tx_skbuff are performed before
589 /* Trigger transmission start */
590 writel(0, txq->bd.reg_desc_active);
596 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
597 struct net_device *ndev,
598 struct bufdesc *bdp, int index, char *data,
599 int size, bool last_tcp, bool is_last)
601 struct fec_enet_private *fep = netdev_priv(ndev);
602 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
603 unsigned short status;
604 unsigned int estatus = 0;
607 status = fec16_to_cpu(bdp->cbd_sc);
608 status &= ~BD_ENET_TX_STATS;
610 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
612 if (((unsigned long) data) & fep->tx_align ||
613 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
614 memcpy(txq->tx_bounce[index], data, size);
615 data = txq->tx_bounce[index];
617 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
618 swap_buffer(data, size);
621 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
622 if (dma_mapping_error(&fep->pdev->dev, addr)) {
623 dev_kfree_skb_any(skb);
625 netdev_err(ndev, "Tx DMA memory map failed\n");
626 return NETDEV_TX_BUSY;
629 bdp->cbd_datlen = cpu_to_fec16(size);
630 bdp->cbd_bufaddr = cpu_to_fec32(addr);
632 if (fep->bufdesc_ex) {
633 if (fep->quirks & FEC_QUIRK_HAS_AVB)
634 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
635 if (skb->ip_summed == CHECKSUM_PARTIAL)
636 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
638 ebdp->cbd_esc = cpu_to_fec32(estatus);
641 /* Handle the last BD specially */
643 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
645 status |= BD_ENET_TX_INTR;
647 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
650 bdp->cbd_sc = cpu_to_fec16(status);
656 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
657 struct sk_buff *skb, struct net_device *ndev,
658 struct bufdesc *bdp, int index)
660 struct fec_enet_private *fep = netdev_priv(ndev);
661 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
662 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
664 unsigned long dmabuf;
665 unsigned short status;
666 unsigned int estatus = 0;
668 status = fec16_to_cpu(bdp->cbd_sc);
669 status &= ~BD_ENET_TX_STATS;
670 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
672 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
673 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
674 if (((unsigned long)bufaddr) & fep->tx_align ||
675 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
676 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
677 bufaddr = txq->tx_bounce[index];
679 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
680 swap_buffer(bufaddr, hdr_len);
682 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
683 hdr_len, DMA_TO_DEVICE);
684 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
685 dev_kfree_skb_any(skb);
687 netdev_err(ndev, "Tx DMA memory map failed\n");
688 return NETDEV_TX_BUSY;
692 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
693 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
695 if (fep->bufdesc_ex) {
696 if (fep->quirks & FEC_QUIRK_HAS_AVB)
697 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
698 if (skb->ip_summed == CHECKSUM_PARTIAL)
699 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
701 ebdp->cbd_esc = cpu_to_fec32(estatus);
704 bdp->cbd_sc = cpu_to_fec16(status);
709 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
711 struct net_device *ndev)
713 struct fec_enet_private *fep = netdev_priv(ndev);
714 int hdr_len, total_len, data_left;
715 struct bufdesc *bdp = txq->bd.cur;
717 unsigned int index = 0;
720 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
721 dev_kfree_skb_any(skb);
723 netdev_err(ndev, "NOT enough BD for TSO!\n");
727 /* Protocol checksum off-load for TCP and UDP. */
728 if (fec_enet_clear_csum(skb, ndev)) {
729 dev_kfree_skb_any(skb);
733 /* Initialize the TSO handler, and prepare the first payload */
734 hdr_len = tso_start(skb, &tso);
736 total_len = skb->len - hdr_len;
737 while (total_len > 0) {
740 index = fec_enet_get_bd_index(bdp, &txq->bd);
741 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
742 total_len -= data_left;
744 /* prepare packet headers: MAC + IP + TCP */
745 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
746 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
747 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
751 while (data_left > 0) {
754 size = min_t(int, tso.size, data_left);
755 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
756 index = fec_enet_get_bd_index(bdp, &txq->bd);
757 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
766 tso_build_data(skb, &tso, size);
769 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
772 /* Save skb pointer */
773 txq->tx_skbuff[index] = skb;
775 skb_tx_timestamp(skb);
778 /* Trigger transmission start */
779 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
780 !readl(txq->bd.reg_desc_active) ||
781 !readl(txq->bd.reg_desc_active) ||
782 !readl(txq->bd.reg_desc_active) ||
783 !readl(txq->bd.reg_desc_active))
784 writel(0, txq->bd.reg_desc_active);
789 /* TODO: Release all used data descriptors for TSO */
794 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
796 struct fec_enet_private *fep = netdev_priv(ndev);
798 unsigned short queue;
799 struct fec_enet_priv_tx_q *txq;
800 struct netdev_queue *nq;
803 queue = skb_get_queue_mapping(skb);
804 txq = fep->tx_queue[queue];
805 nq = netdev_get_tx_queue(ndev, queue);
808 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
810 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
814 entries_free = fec_enet_get_free_txdesc_num(txq);
815 if (entries_free <= txq->tx_stop_threshold)
816 netif_tx_stop_queue(nq);
821 /* Init RX & TX buffer descriptors
823 static void fec_enet_bd_init(struct net_device *dev)
825 struct fec_enet_private *fep = netdev_priv(dev);
826 struct fec_enet_priv_tx_q *txq;
827 struct fec_enet_priv_rx_q *rxq;
832 for (q = 0; q < fep->num_rx_queues; q++) {
833 /* Initialize the receive buffer descriptors. */
834 rxq = fep->rx_queue[q];
837 for (i = 0; i < rxq->bd.ring_size; i++) {
839 /* Initialize the BD for every fragment in the page. */
840 if (bdp->cbd_bufaddr)
841 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
843 bdp->cbd_sc = cpu_to_fec16(0);
844 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
847 /* Set the last buffer to wrap */
848 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
849 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
851 rxq->bd.cur = rxq->bd.base;
854 for (q = 0; q < fep->num_tx_queues; q++) {
855 /* ...and the same for transmit */
856 txq = fep->tx_queue[q];
860 for (i = 0; i < txq->bd.ring_size; i++) {
861 /* Initialize the BD for every fragment in the page. */
862 bdp->cbd_sc = cpu_to_fec16(0);
863 if (bdp->cbd_bufaddr &&
864 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
865 dma_unmap_single(&fep->pdev->dev,
866 fec32_to_cpu(bdp->cbd_bufaddr),
867 fec16_to_cpu(bdp->cbd_datlen),
869 if (txq->tx_skbuff[i]) {
870 dev_kfree_skb_any(txq->tx_skbuff[i]);
871 txq->tx_skbuff[i] = NULL;
873 bdp->cbd_bufaddr = cpu_to_fec32(0);
874 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
877 /* Set the last buffer to wrap */
878 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
879 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
884 static void fec_enet_active_rxring(struct net_device *ndev)
886 struct fec_enet_private *fep = netdev_priv(ndev);
889 for (i = 0; i < fep->num_rx_queues; i++)
890 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
893 static void fec_enet_enable_ring(struct net_device *ndev)
895 struct fec_enet_private *fep = netdev_priv(ndev);
896 struct fec_enet_priv_tx_q *txq;
897 struct fec_enet_priv_rx_q *rxq;
900 for (i = 0; i < fep->num_rx_queues; i++) {
901 rxq = fep->rx_queue[i];
902 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
903 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
907 writel(RCMR_MATCHEN | RCMR_CMP(i),
908 fep->hwp + FEC_RCMR(i));
911 for (i = 0; i < fep->num_tx_queues; i++) {
912 txq = fep->tx_queue[i];
913 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
917 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
918 fep->hwp + FEC_DMA_CFG(i));
922 static void fec_enet_reset_skb(struct net_device *ndev)
924 struct fec_enet_private *fep = netdev_priv(ndev);
925 struct fec_enet_priv_tx_q *txq;
928 for (i = 0; i < fep->num_tx_queues; i++) {
929 txq = fep->tx_queue[i];
931 for (j = 0; j < txq->bd.ring_size; j++) {
932 if (txq->tx_skbuff[j]) {
933 dev_kfree_skb_any(txq->tx_skbuff[j]);
934 txq->tx_skbuff[j] = NULL;
941 * This function is called to start or restart the FEC during a link
942 * change, transmit timeout, or to reconfigure the FEC. The network
943 * packet processing for this device must be stopped before this call.
946 fec_restart(struct net_device *ndev)
948 struct fec_enet_private *fep = netdev_priv(ndev);
951 u32 rcntl = OPT_FRAME_SIZE | 0x04;
952 u32 ecntl = 0x2; /* ETHEREN */
954 /* Whack a reset. We should wait for this.
955 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
956 * instead of reset MAC itself.
958 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
959 writel(0, fep->hwp + FEC_ECNTRL);
961 writel(1, fep->hwp + FEC_ECNTRL);
966 * enet-mac reset will reset mac address registers too,
967 * so need to reconfigure it.
969 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
970 writel((__force u32)cpu_to_be32(temp_mac[0]),
971 fep->hwp + FEC_ADDR_LOW);
972 writel((__force u32)cpu_to_be32(temp_mac[1]),
973 fep->hwp + FEC_ADDR_HIGH);
975 /* Clear any outstanding interrupt, except MDIO. */
976 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT);
978 fec_enet_bd_init(ndev);
980 fec_enet_enable_ring(ndev);
982 /* Reset tx SKB buffers. */
983 fec_enet_reset_skb(ndev);
985 /* Enable MII mode */
986 if (fep->full_duplex == DUPLEX_FULL) {
988 writel(0x04, fep->hwp + FEC_X_CNTRL);
992 writel(0x0, fep->hwp + FEC_X_CNTRL);
996 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
998 #if !defined(CONFIG_M5272)
999 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1000 val = readl(fep->hwp + FEC_RACC);
1001 /* align IP header */
1002 val |= FEC_RACC_SHIFT16;
1003 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
1004 /* set RX checksum */
1005 val |= FEC_RACC_OPTIONS;
1007 val &= ~FEC_RACC_OPTIONS;
1008 writel(val, fep->hwp + FEC_RACC);
1009 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
1014 * The phy interface and speed need to get configured
1015 * differently on enet-mac.
1017 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1018 /* Enable flow control and length check */
1019 rcntl |= 0x40000000 | 0x00000020;
1021 /* RGMII, RMII or MII */
1022 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1023 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1024 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1025 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1027 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1032 /* 1G, 100M or 10M */
1034 if (ndev->phydev->speed == SPEED_1000)
1036 else if (ndev->phydev->speed == SPEED_100)
1042 #ifdef FEC_MIIGSK_ENR
1043 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1045 /* disable the gasket and wait */
1046 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1047 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1051 * configure the gasket:
1052 * RMII, 50 MHz, no loopback, no echo
1053 * MII, 25 MHz, no loopback, no echo
1055 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1056 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1057 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1058 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1059 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1061 /* re-enable the gasket */
1062 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1067 #if !defined(CONFIG_M5272)
1068 /* enable pause frame*/
1069 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1070 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1071 ndev->phydev && ndev->phydev->pause)) {
1072 rcntl |= FEC_ENET_FCE;
1074 /* set FIFO threshold parameter to reduce overrun */
1075 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1076 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1077 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1078 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1081 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1083 rcntl &= ~FEC_ENET_FCE;
1085 #endif /* !defined(CONFIG_M5272) */
1087 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1089 /* Setup multicast filter. */
1090 set_multicast_list(ndev);
1091 #ifndef CONFIG_M5272
1092 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1093 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1096 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1097 /* enable ENET endian swap */
1099 /* enable ENET store and forward mode */
1100 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1103 if (fep->bufdesc_ex)
1106 #ifndef CONFIG_M5272
1107 /* Enable the MIB statistic event counters */
1108 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1111 /* And last, enable the transmit and receive processing */
1112 writel(ecntl, fep->hwp + FEC_ECNTRL);
1113 fec_enet_active_rxring(ndev);
1115 if (fep->bufdesc_ex)
1116 fec_ptp_start_cyclecounter(ndev);
1118 /* Enable interrupts we wish to service */
1120 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1122 writel(0, fep->hwp + FEC_IMASK);
1124 /* Init the interrupt coalescing */
1125 fec_enet_itr_coal_init(ndev);
1129 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled)
1131 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1132 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr;
1134 if (stop_gpr->gpr) {
1136 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1138 BIT(stop_gpr->bit));
1140 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1141 BIT(stop_gpr->bit), 0);
1142 } else if (pdata && pdata->sleep_mode_enable) {
1143 pdata->sleep_mode_enable(enabled);
1148 fec_stop(struct net_device *ndev)
1150 struct fec_enet_private *fep = netdev_priv(ndev);
1151 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1154 /* We cannot expect a graceful transmit stop without link !!! */
1156 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1158 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1159 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1162 /* Whack a reset. We should wait for this.
1163 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1164 * instead of reset MAC itself.
1166 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1167 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1168 writel(0, fep->hwp + FEC_ECNTRL);
1170 writel(1, fep->hwp + FEC_ECNTRL);
1173 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1175 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1176 val = readl(fep->hwp + FEC_ECNTRL);
1177 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1178 writel(val, fep->hwp + FEC_ECNTRL);
1179 fec_enet_stop_mode(fep, true);
1181 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1183 /* We have to keep ENET enabled to have MII interrupt stay working */
1184 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1185 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1186 writel(2, fep->hwp + FEC_ECNTRL);
1187 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1193 fec_timeout(struct net_device *ndev, unsigned int txqueue)
1195 struct fec_enet_private *fep = netdev_priv(ndev);
1199 ndev->stats.tx_errors++;
1201 schedule_work(&fep->tx_timeout_work);
1204 static void fec_enet_timeout_work(struct work_struct *work)
1206 struct fec_enet_private *fep =
1207 container_of(work, struct fec_enet_private, tx_timeout_work);
1208 struct net_device *ndev = fep->netdev;
1211 if (netif_device_present(ndev) || netif_running(ndev)) {
1212 napi_disable(&fep->napi);
1213 netif_tx_lock_bh(ndev);
1215 netif_tx_wake_all_queues(ndev);
1216 netif_tx_unlock_bh(ndev);
1217 napi_enable(&fep->napi);
1223 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1224 struct skb_shared_hwtstamps *hwtstamps)
1226 unsigned long flags;
1229 spin_lock_irqsave(&fep->tmreg_lock, flags);
1230 ns = timecounter_cyc2time(&fep->tc, ts);
1231 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1233 memset(hwtstamps, 0, sizeof(*hwtstamps));
1234 hwtstamps->hwtstamp = ns_to_ktime(ns);
1238 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1240 struct fec_enet_private *fep;
1241 struct bufdesc *bdp;
1242 unsigned short status;
1243 struct sk_buff *skb;
1244 struct fec_enet_priv_tx_q *txq;
1245 struct netdev_queue *nq;
1249 fep = netdev_priv(ndev);
1251 txq = fep->tx_queue[queue_id];
1252 /* get next bdp of dirty_tx */
1253 nq = netdev_get_tx_queue(ndev, queue_id);
1254 bdp = txq->dirty_tx;
1256 /* get next bdp of dirty_tx */
1257 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1259 while (bdp != READ_ONCE(txq->bd.cur)) {
1260 /* Order the load of bd.cur and cbd_sc */
1262 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1263 if (status & BD_ENET_TX_READY)
1266 index = fec_enet_get_bd_index(bdp, &txq->bd);
1268 skb = txq->tx_skbuff[index];
1269 txq->tx_skbuff[index] = NULL;
1270 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1271 dma_unmap_single(&fep->pdev->dev,
1272 fec32_to_cpu(bdp->cbd_bufaddr),
1273 fec16_to_cpu(bdp->cbd_datlen),
1275 bdp->cbd_bufaddr = cpu_to_fec32(0);
1279 /* Check for errors. */
1280 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1281 BD_ENET_TX_RL | BD_ENET_TX_UN |
1283 ndev->stats.tx_errors++;
1284 if (status & BD_ENET_TX_HB) /* No heartbeat */
1285 ndev->stats.tx_heartbeat_errors++;
1286 if (status & BD_ENET_TX_LC) /* Late collision */
1287 ndev->stats.tx_window_errors++;
1288 if (status & BD_ENET_TX_RL) /* Retrans limit */
1289 ndev->stats.tx_aborted_errors++;
1290 if (status & BD_ENET_TX_UN) /* Underrun */
1291 ndev->stats.tx_fifo_errors++;
1292 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1293 ndev->stats.tx_carrier_errors++;
1295 ndev->stats.tx_packets++;
1296 ndev->stats.tx_bytes += skb->len;
1299 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who
1300 * are to time stamp the packet, so we still need to check time
1301 * stamping enabled flag.
1303 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS &&
1306 struct skb_shared_hwtstamps shhwtstamps;
1307 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1309 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1310 skb_tstamp_tx(skb, &shhwtstamps);
1313 /* Deferred means some collisions occurred during transmit,
1314 * but we eventually sent the packet OK.
1316 if (status & BD_ENET_TX_DEF)
1317 ndev->stats.collisions++;
1319 /* Free the sk buffer associated with this last transmit */
1320 dev_kfree_skb_any(skb);
1322 /* Make sure the update to bdp and tx_skbuff are performed
1326 txq->dirty_tx = bdp;
1328 /* Update pointer to next buffer descriptor to be transmitted */
1329 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1331 /* Since we have freed up a buffer, the ring is no longer full
1333 if (netif_tx_queue_stopped(nq)) {
1334 entries_free = fec_enet_get_free_txdesc_num(txq);
1335 if (entries_free >= txq->tx_wake_threshold)
1336 netif_tx_wake_queue(nq);
1340 /* ERR006358: Keep the transmitter going */
1341 if (bdp != txq->bd.cur &&
1342 readl(txq->bd.reg_desc_active) == 0)
1343 writel(0, txq->bd.reg_desc_active);
1346 static void fec_enet_tx(struct net_device *ndev)
1348 struct fec_enet_private *fep = netdev_priv(ndev);
1351 /* Make sure that AVB queues are processed first. */
1352 for (i = fep->num_tx_queues - 1; i >= 0; i--)
1353 fec_enet_tx_queue(ndev, i);
1357 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1359 struct fec_enet_private *fep = netdev_priv(ndev);
1362 off = ((unsigned long)skb->data) & fep->rx_align;
1364 skb_reserve(skb, fep->rx_align + 1 - off);
1366 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1367 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1368 if (net_ratelimit())
1369 netdev_err(ndev, "Rx DMA memory map failed\n");
1376 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1377 struct bufdesc *bdp, u32 length, bool swap)
1379 struct fec_enet_private *fep = netdev_priv(ndev);
1380 struct sk_buff *new_skb;
1382 if (length > fep->rx_copybreak)
1385 new_skb = netdev_alloc_skb(ndev, length);
1389 dma_sync_single_for_cpu(&fep->pdev->dev,
1390 fec32_to_cpu(bdp->cbd_bufaddr),
1391 FEC_ENET_RX_FRSIZE - fep->rx_align,
1394 memcpy(new_skb->data, (*skb)->data, length);
1396 swap_buffer2(new_skb->data, (*skb)->data, length);
1402 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1403 * When we update through the ring, if the next incoming buffer has
1404 * not been given to the system, we just set the empty indicator,
1405 * effectively tossing the packet.
1408 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1410 struct fec_enet_private *fep = netdev_priv(ndev);
1411 struct fec_enet_priv_rx_q *rxq;
1412 struct bufdesc *bdp;
1413 unsigned short status;
1414 struct sk_buff *skb_new = NULL;
1415 struct sk_buff *skb;
1418 int pkt_received = 0;
1419 struct bufdesc_ex *ebdp = NULL;
1420 bool vlan_packet_rcvd = false;
1424 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1429 rxq = fep->rx_queue[queue_id];
1431 /* First, grab all of the stats for the incoming packet.
1432 * These get messed up if we get called due to a busy condition.
1436 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1438 if (pkt_received >= budget)
1442 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT);
1444 /* Check for errors. */
1445 status ^= BD_ENET_RX_LAST;
1446 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1447 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1449 ndev->stats.rx_errors++;
1450 if (status & BD_ENET_RX_OV) {
1452 ndev->stats.rx_fifo_errors++;
1453 goto rx_processing_done;
1455 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1456 | BD_ENET_RX_LAST)) {
1457 /* Frame too long or too short. */
1458 ndev->stats.rx_length_errors++;
1459 if (status & BD_ENET_RX_LAST)
1460 netdev_err(ndev, "rcv is not +last\n");
1462 if (status & BD_ENET_RX_CR) /* CRC Error */
1463 ndev->stats.rx_crc_errors++;
1464 /* Report late collisions as a frame error. */
1465 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1466 ndev->stats.rx_frame_errors++;
1467 goto rx_processing_done;
1470 /* Process the incoming frame. */
1471 ndev->stats.rx_packets++;
1472 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1473 ndev->stats.rx_bytes += pkt_len;
1475 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1476 skb = rxq->rx_skbuff[index];
1478 /* The packet length includes FCS, but we don't want to
1479 * include that when passing upstream as it messes up
1480 * bridging applications.
1482 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1484 if (!is_copybreak) {
1485 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1486 if (unlikely(!skb_new)) {
1487 ndev->stats.rx_dropped++;
1488 goto rx_processing_done;
1490 dma_unmap_single(&fep->pdev->dev,
1491 fec32_to_cpu(bdp->cbd_bufaddr),
1492 FEC_ENET_RX_FRSIZE - fep->rx_align,
1496 prefetch(skb->data - NET_IP_ALIGN);
1497 skb_put(skb, pkt_len - 4);
1500 if (!is_copybreak && need_swap)
1501 swap_buffer(data, pkt_len);
1503 #if !defined(CONFIG_M5272)
1504 if (fep->quirks & FEC_QUIRK_HAS_RACC)
1505 data = skb_pull_inline(skb, 2);
1508 /* Extract the enhanced buffer descriptor */
1510 if (fep->bufdesc_ex)
1511 ebdp = (struct bufdesc_ex *)bdp;
1513 /* If this is a VLAN packet remove the VLAN Tag */
1514 vlan_packet_rcvd = false;
1515 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1517 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1518 /* Push and remove the vlan tag */
1519 struct vlan_hdr *vlan_header =
1520 (struct vlan_hdr *) (data + ETH_HLEN);
1521 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1523 vlan_packet_rcvd = true;
1525 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1526 skb_pull(skb, VLAN_HLEN);
1529 skb->protocol = eth_type_trans(skb, ndev);
1531 /* Get receive timestamp from the skb */
1532 if (fep->hwts_rx_en && fep->bufdesc_ex)
1533 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1534 skb_hwtstamps(skb));
1536 if (fep->bufdesc_ex &&
1537 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1538 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1539 /* don't check it */
1540 skb->ip_summed = CHECKSUM_UNNECESSARY;
1542 skb_checksum_none_assert(skb);
1546 /* Handle received VLAN packets */
1547 if (vlan_packet_rcvd)
1548 __vlan_hwaccel_put_tag(skb,
1552 skb_record_rx_queue(skb, queue_id);
1553 napi_gro_receive(&fep->napi, skb);
1556 dma_sync_single_for_device(&fep->pdev->dev,
1557 fec32_to_cpu(bdp->cbd_bufaddr),
1558 FEC_ENET_RX_FRSIZE - fep->rx_align,
1561 rxq->rx_skbuff[index] = skb_new;
1562 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1566 /* Clear the status flags for this buffer */
1567 status &= ~BD_ENET_RX_STATS;
1569 /* Mark the buffer empty */
1570 status |= BD_ENET_RX_EMPTY;
1572 if (fep->bufdesc_ex) {
1573 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1575 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1579 /* Make sure the updates to rest of the descriptor are
1580 * performed before transferring ownership.
1583 bdp->cbd_sc = cpu_to_fec16(status);
1585 /* Update BD pointer to next entry */
1586 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1588 /* Doing this here will keep the FEC running while we process
1589 * incoming frames. On a heavily loaded network, we should be
1590 * able to keep up at the expense of system resources.
1592 writel(0, rxq->bd.reg_desc_active);
1595 return pkt_received;
1598 static int fec_enet_rx(struct net_device *ndev, int budget)
1600 struct fec_enet_private *fep = netdev_priv(ndev);
1603 /* Make sure that AVB queues are processed first. */
1604 for (i = fep->num_rx_queues - 1; i >= 0; i--)
1605 done += fec_enet_rx_queue(ndev, budget - done, i);
1610 static bool fec_enet_collect_events(struct fec_enet_private *fep)
1614 int_events = readl(fep->hwp + FEC_IEVENT);
1616 /* Don't clear MDIO events, we poll for those */
1617 int_events &= ~FEC_ENET_MII;
1619 writel(int_events, fep->hwp + FEC_IEVENT);
1621 return int_events != 0;
1625 fec_enet_interrupt(int irq, void *dev_id)
1627 struct net_device *ndev = dev_id;
1628 struct fec_enet_private *fep = netdev_priv(ndev);
1629 irqreturn_t ret = IRQ_NONE;
1631 if (fec_enet_collect_events(fep) && fep->link) {
1634 if (napi_schedule_prep(&fep->napi)) {
1635 /* Disable interrupts */
1636 writel(0, fep->hwp + FEC_IMASK);
1637 __napi_schedule(&fep->napi);
1644 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1646 struct net_device *ndev = napi->dev;
1647 struct fec_enet_private *fep = netdev_priv(ndev);
1651 done += fec_enet_rx(ndev, budget - done);
1653 } while ((done < budget) && fec_enet_collect_events(fep));
1655 if (done < budget) {
1656 napi_complete_done(napi, done);
1657 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1663 /* ------------------------------------------------------------------------- */
1664 static void fec_get_mac(struct net_device *ndev)
1666 struct fec_enet_private *fep = netdev_priv(ndev);
1667 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1668 unsigned char *iap, tmpaddr[ETH_ALEN];
1671 * try to get mac address in following order:
1673 * 1) module parameter via kernel command line in form
1674 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1679 * 2) from device tree data
1681 if (!is_valid_ether_addr(iap)) {
1682 struct device_node *np = fep->pdev->dev.of_node;
1684 const char *mac = of_get_mac_address(np);
1686 iap = (unsigned char *) mac;
1691 * 3) from flash or fuse (via platform data)
1693 if (!is_valid_ether_addr(iap)) {
1696 iap = (unsigned char *)FEC_FLASHMAC;
1699 iap = (unsigned char *)&pdata->mac;
1704 * 4) FEC mac registers set by bootloader
1706 if (!is_valid_ether_addr(iap)) {
1707 *((__be32 *) &tmpaddr[0]) =
1708 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1709 *((__be16 *) &tmpaddr[4]) =
1710 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1715 * 5) random mac address
1717 if (!is_valid_ether_addr(iap)) {
1718 /* Report it and use a random ethernet address instead */
1719 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
1720 eth_hw_addr_random(ndev);
1721 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
1726 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1728 /* Adjust MAC if using macaddr */
1730 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1733 /* ------------------------------------------------------------------------- */
1738 static void fec_enet_adjust_link(struct net_device *ndev)
1740 struct fec_enet_private *fep = netdev_priv(ndev);
1741 struct phy_device *phy_dev = ndev->phydev;
1742 int status_change = 0;
1745 * If the netdev is down, or is going down, we're not interested
1746 * in link state events, so just mark our idea of the link as down
1747 * and ignore the event.
1749 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1751 } else if (phy_dev->link) {
1753 fep->link = phy_dev->link;
1757 if (fep->full_duplex != phy_dev->duplex) {
1758 fep->full_duplex = phy_dev->duplex;
1762 if (phy_dev->speed != fep->speed) {
1763 fep->speed = phy_dev->speed;
1767 /* if any of the above changed restart the FEC */
1768 if (status_change) {
1769 napi_disable(&fep->napi);
1770 netif_tx_lock_bh(ndev);
1772 netif_tx_wake_all_queues(ndev);
1773 netif_tx_unlock_bh(ndev);
1774 napi_enable(&fep->napi);
1778 napi_disable(&fep->napi);
1779 netif_tx_lock_bh(ndev);
1781 netif_tx_unlock_bh(ndev);
1782 napi_enable(&fep->napi);
1783 fep->link = phy_dev->link;
1789 phy_print_status(phy_dev);
1792 static int fec_enet_mdio_wait(struct fec_enet_private *fep)
1797 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent,
1798 ievent & FEC_ENET_MII, 2, 30000);
1801 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
1806 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1808 struct fec_enet_private *fep = bus->priv;
1809 struct device *dev = &fep->pdev->dev;
1810 int ret = 0, frame_start, frame_addr, frame_op;
1811 bool is_c45 = !!(regnum & MII_ADDR_C45);
1813 ret = pm_runtime_resume_and_get(dev);
1818 frame_start = FEC_MMFR_ST_C45;
1821 frame_addr = (regnum >> 16);
1822 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
1823 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1824 FEC_MMFR_TA | (regnum & 0xFFFF),
1825 fep->hwp + FEC_MII_DATA);
1827 /* wait for end of transfer */
1828 ret = fec_enet_mdio_wait(fep);
1830 netdev_err(fep->netdev, "MDIO address write timeout\n");
1834 frame_op = FEC_MMFR_OP_READ_C45;
1838 frame_op = FEC_MMFR_OP_READ;
1839 frame_start = FEC_MMFR_ST;
1840 frame_addr = regnum;
1843 /* start a read op */
1844 writel(frame_start | frame_op |
1845 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1846 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1848 /* wait for end of transfer */
1849 ret = fec_enet_mdio_wait(fep);
1851 netdev_err(fep->netdev, "MDIO read timeout\n");
1855 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1858 pm_runtime_mark_last_busy(dev);
1859 pm_runtime_put_autosuspend(dev);
1864 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1867 struct fec_enet_private *fep = bus->priv;
1868 struct device *dev = &fep->pdev->dev;
1869 int ret, frame_start, frame_addr;
1870 bool is_c45 = !!(regnum & MII_ADDR_C45);
1872 ret = pm_runtime_resume_and_get(dev);
1877 frame_start = FEC_MMFR_ST_C45;
1880 frame_addr = (regnum >> 16);
1881 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
1882 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1883 FEC_MMFR_TA | (regnum & 0xFFFF),
1884 fep->hwp + FEC_MII_DATA);
1886 /* wait for end of transfer */
1887 ret = fec_enet_mdio_wait(fep);
1889 netdev_err(fep->netdev, "MDIO address write timeout\n");
1894 frame_start = FEC_MMFR_ST;
1895 frame_addr = regnum;
1898 /* start a write op */
1899 writel(frame_start | FEC_MMFR_OP_WRITE |
1900 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1901 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1902 fep->hwp + FEC_MII_DATA);
1904 /* wait for end of transfer */
1905 ret = fec_enet_mdio_wait(fep);
1907 netdev_err(fep->netdev, "MDIO write timeout\n");
1910 pm_runtime_mark_last_busy(dev);
1911 pm_runtime_put_autosuspend(dev);
1916 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev)
1918 struct fec_enet_private *fep = netdev_priv(ndev);
1919 struct phy_device *phy_dev = ndev->phydev;
1922 phy_reset_after_clk_enable(phy_dev);
1923 } else if (fep->phy_node) {
1925 * If the PHY still is not bound to the MAC, but there is
1926 * OF PHY node and a matching PHY device instance already,
1927 * use the OF PHY node to obtain the PHY device instance,
1928 * and then use that PHY device instance when triggering
1931 phy_dev = of_phy_find_device(fep->phy_node);
1932 phy_reset_after_clk_enable(phy_dev);
1933 put_device(&phy_dev->mdio.dev);
1937 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1939 struct fec_enet_private *fep = netdev_priv(ndev);
1943 ret = clk_prepare_enable(fep->clk_enet_out);
1948 mutex_lock(&fep->ptp_clk_mutex);
1949 ret = clk_prepare_enable(fep->clk_ptp);
1951 mutex_unlock(&fep->ptp_clk_mutex);
1952 goto failed_clk_ptp;
1954 fep->ptp_clk_on = true;
1956 mutex_unlock(&fep->ptp_clk_mutex);
1959 ret = clk_prepare_enable(fep->clk_ref);
1961 goto failed_clk_ref;
1963 fec_enet_phy_reset_after_clk_enable(ndev);
1965 clk_disable_unprepare(fep->clk_enet_out);
1967 mutex_lock(&fep->ptp_clk_mutex);
1968 clk_disable_unprepare(fep->clk_ptp);
1969 fep->ptp_clk_on = false;
1970 mutex_unlock(&fep->ptp_clk_mutex);
1972 clk_disable_unprepare(fep->clk_ref);
1979 mutex_lock(&fep->ptp_clk_mutex);
1980 clk_disable_unprepare(fep->clk_ptp);
1981 fep->ptp_clk_on = false;
1982 mutex_unlock(&fep->ptp_clk_mutex);
1985 clk_disable_unprepare(fep->clk_enet_out);
1990 static int fec_enet_mii_probe(struct net_device *ndev)
1992 struct fec_enet_private *fep = netdev_priv(ndev);
1993 struct phy_device *phy_dev = NULL;
1994 char mdio_bus_id[MII_BUS_ID_SIZE];
1995 char phy_name[MII_BUS_ID_SIZE + 3];
1997 int dev_id = fep->dev_id;
1999 if (fep->phy_node) {
2000 phy_dev = of_phy_connect(ndev, fep->phy_node,
2001 &fec_enet_adjust_link, 0,
2002 fep->phy_interface);
2004 netdev_err(ndev, "Unable to connect to phy\n");
2008 /* check for attached phy */
2009 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
2010 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
2014 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
2018 if (phy_id >= PHY_MAX_ADDR) {
2019 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
2020 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
2024 snprintf(phy_name, sizeof(phy_name),
2025 PHY_ID_FMT, mdio_bus_id, phy_id);
2026 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
2027 fep->phy_interface);
2030 if (IS_ERR(phy_dev)) {
2031 netdev_err(ndev, "could not attach to PHY\n");
2032 return PTR_ERR(phy_dev);
2035 /* mask with MAC supported features */
2036 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
2037 phy_set_max_speed(phy_dev, 1000);
2038 phy_remove_link_mode(phy_dev,
2039 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
2040 #if !defined(CONFIG_M5272)
2041 phy_support_sym_pause(phy_dev);
2045 phy_set_max_speed(phy_dev, 100);
2048 fep->full_duplex = 0;
2050 phy_attached_info(phy_dev);
2055 static int fec_enet_mii_init(struct platform_device *pdev)
2057 static struct mii_bus *fec0_mii_bus;
2058 struct net_device *ndev = platform_get_drvdata(pdev);
2059 struct fec_enet_private *fep = netdev_priv(ndev);
2060 bool suppress_preamble = false;
2061 struct device_node *node;
2063 u32 mii_speed, holdtime;
2067 * The i.MX28 dual fec interfaces are not equal.
2068 * Here are the differences:
2070 * - fec0 supports MII & RMII modes while fec1 only supports RMII
2071 * - fec0 acts as the 1588 time master while fec1 is slave
2072 * - external phys can only be configured by fec0
2074 * That is to say fec1 can not work independently. It only works
2075 * when fec0 is working. The reason behind this design is that the
2076 * second interface is added primarily for Switch mode.
2078 * Because of the last point above, both phys are attached on fec0
2079 * mdio interface in board design, and need to be configured by
2082 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2083 /* fec1 uses fec0 mii_bus */
2084 if (mii_cnt && fec0_mii_bus) {
2085 fep->mii_bus = fec0_mii_bus;
2092 bus_freq = 2500000; /* 2.5MHz by default */
2093 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2095 of_property_read_u32(node, "clock-frequency", &bus_freq);
2096 suppress_preamble = of_property_read_bool(node,
2097 "suppress-preamble");
2101 * Set MII speed (= clk_get_rate() / 2 * phy_speed)
2103 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2104 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2105 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2108 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2);
2109 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2111 if (mii_speed > 63) {
2113 "fec clock (%lu) too fast to get right mii speed\n",
2114 clk_get_rate(fep->clk_ipg));
2120 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2121 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2122 * versions are RAZ there, so just ignore the difference and write the
2124 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2125 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2127 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2128 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2129 * holdtime cannot result in a value greater than 3.
2131 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2133 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2135 if (suppress_preamble)
2136 fep->phy_speed |= BIT(7);
2138 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) {
2139 /* Clear MMFR to avoid to generate MII event by writing MSCR.
2140 * MII event generation condition:
2142 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero &
2143 * mscr_reg_data_in[7:0] != 0
2145 * - mscr[7:0]_not_zero
2147 writel(0, fep->hwp + FEC_MII_DATA);
2150 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2152 /* Clear any pending transaction complete indication */
2153 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2155 fep->mii_bus = mdiobus_alloc();
2156 if (fep->mii_bus == NULL) {
2161 fep->mii_bus->name = "fec_enet_mii_bus";
2162 fep->mii_bus->read = fec_enet_mdio_read;
2163 fep->mii_bus->write = fec_enet_mdio_write;
2164 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2165 pdev->name, fep->dev_id + 1);
2166 fep->mii_bus->priv = fep;
2167 fep->mii_bus->parent = &pdev->dev;
2169 err = of_mdiobus_register(fep->mii_bus, node);
2171 goto err_out_free_mdiobus;
2176 /* save fec0 mii_bus */
2177 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2178 fec0_mii_bus = fep->mii_bus;
2182 err_out_free_mdiobus:
2183 mdiobus_free(fep->mii_bus);
2189 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2191 if (--mii_cnt == 0) {
2192 mdiobus_unregister(fep->mii_bus);
2193 mdiobus_free(fep->mii_bus);
2197 static void fec_enet_get_drvinfo(struct net_device *ndev,
2198 struct ethtool_drvinfo *info)
2200 struct fec_enet_private *fep = netdev_priv(ndev);
2202 strlcpy(info->driver, fep->pdev->dev.driver->name,
2203 sizeof(info->driver));
2204 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2207 static int fec_enet_get_regs_len(struct net_device *ndev)
2209 struct fec_enet_private *fep = netdev_priv(ndev);
2213 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2215 s = resource_size(r);
2220 /* List of registers that can be safety be read to dump them with ethtool */
2221 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2222 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2223 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2224 static __u32 fec_enet_register_version = 2;
2225 static u32 fec_enet_register_offset[] = {
2226 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2227 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2228 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2229 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2230 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2231 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2232 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2233 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2234 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2235 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2236 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2237 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2238 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2239 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2240 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2241 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2242 RMON_T_P_GTE2048, RMON_T_OCTETS,
2243 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2244 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2245 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2246 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2247 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2248 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2249 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2250 RMON_R_P_GTE2048, RMON_R_OCTETS,
2251 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2252 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2255 static u32 fec_enet_register_offset_6ul[] = {
2256 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2257 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2258 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0,
2259 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH,
2260 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0,
2261 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2262 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC,
2263 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2264 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2265 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2266 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2267 RMON_T_P_GTE2048, RMON_T_OCTETS,
2268 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2269 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2270 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2271 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2272 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2273 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2274 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2275 RMON_R_P_GTE2048, RMON_R_OCTETS,
2276 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2277 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2280 static __u32 fec_enet_register_version = 1;
2281 static u32 fec_enet_register_offset[] = {
2282 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2283 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2284 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2285 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2286 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2287 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2288 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2289 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2290 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2294 static void fec_enet_get_regs(struct net_device *ndev,
2295 struct ethtool_regs *regs, void *regbuf)
2297 struct fec_enet_private *fep = netdev_priv(ndev);
2298 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2299 struct device *dev = &fep->pdev->dev;
2300 u32 *buf = (u32 *)regbuf;
2303 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2304 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2305 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2309 if (!of_machine_is_compatible("fsl,imx6ul")) {
2310 reg_list = fec_enet_register_offset;
2311 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2313 reg_list = fec_enet_register_offset_6ul;
2314 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul);
2318 static u32 *reg_list = fec_enet_register_offset;
2319 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2321 ret = pm_runtime_resume_and_get(dev);
2325 regs->version = fec_enet_register_version;
2327 memset(buf, 0, regs->len);
2329 for (i = 0; i < reg_cnt; i++) {
2332 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2333 !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2337 buf[off] = readl(&theregs[off]);
2340 pm_runtime_mark_last_busy(dev);
2341 pm_runtime_put_autosuspend(dev);
2344 static int fec_enet_get_ts_info(struct net_device *ndev,
2345 struct ethtool_ts_info *info)
2347 struct fec_enet_private *fep = netdev_priv(ndev);
2349 if (fep->bufdesc_ex) {
2351 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2352 SOF_TIMESTAMPING_RX_SOFTWARE |
2353 SOF_TIMESTAMPING_SOFTWARE |
2354 SOF_TIMESTAMPING_TX_HARDWARE |
2355 SOF_TIMESTAMPING_RX_HARDWARE |
2356 SOF_TIMESTAMPING_RAW_HARDWARE;
2358 info->phc_index = ptp_clock_index(fep->ptp_clock);
2360 info->phc_index = -1;
2362 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2363 (1 << HWTSTAMP_TX_ON);
2365 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2366 (1 << HWTSTAMP_FILTER_ALL);
2369 return ethtool_op_get_ts_info(ndev, info);
2373 #if !defined(CONFIG_M5272)
2375 static void fec_enet_get_pauseparam(struct net_device *ndev,
2376 struct ethtool_pauseparam *pause)
2378 struct fec_enet_private *fep = netdev_priv(ndev);
2380 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2381 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2382 pause->rx_pause = pause->tx_pause;
2385 static int fec_enet_set_pauseparam(struct net_device *ndev,
2386 struct ethtool_pauseparam *pause)
2388 struct fec_enet_private *fep = netdev_priv(ndev);
2393 if (pause->tx_pause != pause->rx_pause) {
2395 "hardware only support enable/disable both tx and rx");
2399 fep->pause_flag = 0;
2401 /* tx pause must be same as rx pause */
2402 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2403 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2405 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2408 if (pause->autoneg) {
2409 if (netif_running(ndev))
2411 phy_start_aneg(ndev->phydev);
2413 if (netif_running(ndev)) {
2414 napi_disable(&fep->napi);
2415 netif_tx_lock_bh(ndev);
2417 netif_tx_wake_all_queues(ndev);
2418 netif_tx_unlock_bh(ndev);
2419 napi_enable(&fep->napi);
2425 static const struct fec_stat {
2426 char name[ETH_GSTRING_LEN];
2430 { "tx_dropped", RMON_T_DROP },
2431 { "tx_packets", RMON_T_PACKETS },
2432 { "tx_broadcast", RMON_T_BC_PKT },
2433 { "tx_multicast", RMON_T_MC_PKT },
2434 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2435 { "tx_undersize", RMON_T_UNDERSIZE },
2436 { "tx_oversize", RMON_T_OVERSIZE },
2437 { "tx_fragment", RMON_T_FRAG },
2438 { "tx_jabber", RMON_T_JAB },
2439 { "tx_collision", RMON_T_COL },
2440 { "tx_64byte", RMON_T_P64 },
2441 { "tx_65to127byte", RMON_T_P65TO127 },
2442 { "tx_128to255byte", RMON_T_P128TO255 },
2443 { "tx_256to511byte", RMON_T_P256TO511 },
2444 { "tx_512to1023byte", RMON_T_P512TO1023 },
2445 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2446 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2447 { "tx_octets", RMON_T_OCTETS },
2450 { "IEEE_tx_drop", IEEE_T_DROP },
2451 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2452 { "IEEE_tx_1col", IEEE_T_1COL },
2453 { "IEEE_tx_mcol", IEEE_T_MCOL },
2454 { "IEEE_tx_def", IEEE_T_DEF },
2455 { "IEEE_tx_lcol", IEEE_T_LCOL },
2456 { "IEEE_tx_excol", IEEE_T_EXCOL },
2457 { "IEEE_tx_macerr", IEEE_T_MACERR },
2458 { "IEEE_tx_cserr", IEEE_T_CSERR },
2459 { "IEEE_tx_sqe", IEEE_T_SQE },
2460 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2461 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2464 { "rx_packets", RMON_R_PACKETS },
2465 { "rx_broadcast", RMON_R_BC_PKT },
2466 { "rx_multicast", RMON_R_MC_PKT },
2467 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2468 { "rx_undersize", RMON_R_UNDERSIZE },
2469 { "rx_oversize", RMON_R_OVERSIZE },
2470 { "rx_fragment", RMON_R_FRAG },
2471 { "rx_jabber", RMON_R_JAB },
2472 { "rx_64byte", RMON_R_P64 },
2473 { "rx_65to127byte", RMON_R_P65TO127 },
2474 { "rx_128to255byte", RMON_R_P128TO255 },
2475 { "rx_256to511byte", RMON_R_P256TO511 },
2476 { "rx_512to1023byte", RMON_R_P512TO1023 },
2477 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2478 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2479 { "rx_octets", RMON_R_OCTETS },
2482 { "IEEE_rx_drop", IEEE_R_DROP },
2483 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2484 { "IEEE_rx_crc", IEEE_R_CRC },
2485 { "IEEE_rx_align", IEEE_R_ALIGN },
2486 { "IEEE_rx_macerr", IEEE_R_MACERR },
2487 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2488 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2491 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2493 static void fec_enet_update_ethtool_stats(struct net_device *dev)
2495 struct fec_enet_private *fep = netdev_priv(dev);
2498 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2499 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2502 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2503 struct ethtool_stats *stats, u64 *data)
2505 struct fec_enet_private *fep = netdev_priv(dev);
2507 if (netif_running(dev))
2508 fec_enet_update_ethtool_stats(dev);
2510 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2513 static void fec_enet_get_strings(struct net_device *netdev,
2514 u32 stringset, u8 *data)
2517 switch (stringset) {
2519 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2520 memcpy(data + i * ETH_GSTRING_LEN,
2521 fec_stats[i].name, ETH_GSTRING_LEN);
2526 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2530 return ARRAY_SIZE(fec_stats);
2536 static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2538 struct fec_enet_private *fep = netdev_priv(dev);
2541 /* Disable MIB statistics counters */
2542 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2544 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2545 writel(0, fep->hwp + fec_stats[i].offset);
2547 /* Don't disable MIB statistics counters */
2548 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2551 #else /* !defined(CONFIG_M5272) */
2552 #define FEC_STATS_SIZE 0
2553 static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2557 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2560 #endif /* !defined(CONFIG_M5272) */
2562 /* ITR clock source is enet system clock (clk_ahb).
2563 * TCTT unit is cycle_ns * 64 cycle
2564 * So, the ICTT value = X us / (cycle_ns * 64)
2566 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2568 struct fec_enet_private *fep = netdev_priv(ndev);
2570 return us * (fep->itr_clk_rate / 64000) / 1000;
2573 /* Set threshold for interrupt coalescing */
2574 static void fec_enet_itr_coal_set(struct net_device *ndev)
2576 struct fec_enet_private *fep = netdev_priv(ndev);
2579 /* Must be greater than zero to avoid unpredictable behavior */
2580 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2581 !fep->tx_time_itr || !fep->tx_pkts_itr)
2584 /* Select enet system clock as Interrupt Coalescing
2585 * timer Clock Source
2587 rx_itr = FEC_ITR_CLK_SEL;
2588 tx_itr = FEC_ITR_CLK_SEL;
2590 /* set ICFT and ICTT */
2591 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2592 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2593 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2594 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2596 rx_itr |= FEC_ITR_EN;
2597 tx_itr |= FEC_ITR_EN;
2599 writel(tx_itr, fep->hwp + FEC_TXIC0);
2600 writel(rx_itr, fep->hwp + FEC_RXIC0);
2601 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2602 writel(tx_itr, fep->hwp + FEC_TXIC1);
2603 writel(rx_itr, fep->hwp + FEC_RXIC1);
2604 writel(tx_itr, fep->hwp + FEC_TXIC2);
2605 writel(rx_itr, fep->hwp + FEC_RXIC2);
2610 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2612 struct fec_enet_private *fep = netdev_priv(ndev);
2614 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2617 ec->rx_coalesce_usecs = fep->rx_time_itr;
2618 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2620 ec->tx_coalesce_usecs = fep->tx_time_itr;
2621 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2627 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2629 struct fec_enet_private *fep = netdev_priv(ndev);
2630 struct device *dev = &fep->pdev->dev;
2633 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2636 if (ec->rx_max_coalesced_frames > 255) {
2637 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n");
2641 if (ec->tx_max_coalesced_frames > 255) {
2642 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n");
2646 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs);
2647 if (cycle > 0xFFFF) {
2648 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
2652 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs);
2653 if (cycle > 0xFFFF) {
2654 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n");
2658 fep->rx_time_itr = ec->rx_coalesce_usecs;
2659 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2661 fep->tx_time_itr = ec->tx_coalesce_usecs;
2662 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2664 fec_enet_itr_coal_set(ndev);
2669 static void fec_enet_itr_coal_init(struct net_device *ndev)
2671 struct ethtool_coalesce ec;
2673 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2674 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2676 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2677 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2679 fec_enet_set_coalesce(ndev, &ec);
2682 static int fec_enet_get_tunable(struct net_device *netdev,
2683 const struct ethtool_tunable *tuna,
2686 struct fec_enet_private *fep = netdev_priv(netdev);
2690 case ETHTOOL_RX_COPYBREAK:
2691 *(u32 *)data = fep->rx_copybreak;
2701 static int fec_enet_set_tunable(struct net_device *netdev,
2702 const struct ethtool_tunable *tuna,
2705 struct fec_enet_private *fep = netdev_priv(netdev);
2709 case ETHTOOL_RX_COPYBREAK:
2710 fep->rx_copybreak = *(u32 *)data;
2721 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2723 struct fec_enet_private *fep = netdev_priv(ndev);
2725 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2726 wol->supported = WAKE_MAGIC;
2727 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2729 wol->supported = wol->wolopts = 0;
2734 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2736 struct fec_enet_private *fep = netdev_priv(ndev);
2738 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2741 if (wol->wolopts & ~WAKE_MAGIC)
2744 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2745 if (device_may_wakeup(&ndev->dev)) {
2746 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2747 if (fep->irq[0] > 0)
2748 enable_irq_wake(fep->irq[0]);
2750 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2751 if (fep->irq[0] > 0)
2752 disable_irq_wake(fep->irq[0]);
2758 static const struct ethtool_ops fec_enet_ethtool_ops = {
2759 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2760 ETHTOOL_COALESCE_MAX_FRAMES,
2761 .get_drvinfo = fec_enet_get_drvinfo,
2762 .get_regs_len = fec_enet_get_regs_len,
2763 .get_regs = fec_enet_get_regs,
2764 .nway_reset = phy_ethtool_nway_reset,
2765 .get_link = ethtool_op_get_link,
2766 .get_coalesce = fec_enet_get_coalesce,
2767 .set_coalesce = fec_enet_set_coalesce,
2768 #ifndef CONFIG_M5272
2769 .get_pauseparam = fec_enet_get_pauseparam,
2770 .set_pauseparam = fec_enet_set_pauseparam,
2771 .get_strings = fec_enet_get_strings,
2772 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2773 .get_sset_count = fec_enet_get_sset_count,
2775 .get_ts_info = fec_enet_get_ts_info,
2776 .get_tunable = fec_enet_get_tunable,
2777 .set_tunable = fec_enet_set_tunable,
2778 .get_wol = fec_enet_get_wol,
2779 .set_wol = fec_enet_set_wol,
2780 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2781 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2784 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2786 struct fec_enet_private *fep = netdev_priv(ndev);
2787 struct phy_device *phydev = ndev->phydev;
2789 if (!netif_running(ndev))
2795 if (fep->bufdesc_ex) {
2796 bool use_fec_hwts = !phy_has_hwtstamp(phydev);
2798 if (cmd == SIOCSHWTSTAMP) {
2800 return fec_ptp_set(ndev, rq);
2801 fec_ptp_disable_hwts(ndev);
2802 } else if (cmd == SIOCGHWTSTAMP) {
2804 return fec_ptp_get(ndev, rq);
2808 return phy_mii_ioctl(phydev, rq, cmd);
2811 static void fec_enet_free_buffers(struct net_device *ndev)
2813 struct fec_enet_private *fep = netdev_priv(ndev);
2815 struct sk_buff *skb;
2816 struct bufdesc *bdp;
2817 struct fec_enet_priv_tx_q *txq;
2818 struct fec_enet_priv_rx_q *rxq;
2821 for (q = 0; q < fep->num_rx_queues; q++) {
2822 rxq = fep->rx_queue[q];
2824 for (i = 0; i < rxq->bd.ring_size; i++) {
2825 skb = rxq->rx_skbuff[i];
2826 rxq->rx_skbuff[i] = NULL;
2828 dma_unmap_single(&fep->pdev->dev,
2829 fec32_to_cpu(bdp->cbd_bufaddr),
2830 FEC_ENET_RX_FRSIZE - fep->rx_align,
2834 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2838 for (q = 0; q < fep->num_tx_queues; q++) {
2839 txq = fep->tx_queue[q];
2840 for (i = 0; i < txq->bd.ring_size; i++) {
2841 kfree(txq->tx_bounce[i]);
2842 txq->tx_bounce[i] = NULL;
2843 skb = txq->tx_skbuff[i];
2844 txq->tx_skbuff[i] = NULL;
2850 static void fec_enet_free_queue(struct net_device *ndev)
2852 struct fec_enet_private *fep = netdev_priv(ndev);
2854 struct fec_enet_priv_tx_q *txq;
2856 for (i = 0; i < fep->num_tx_queues; i++)
2857 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2858 txq = fep->tx_queue[i];
2859 dma_free_coherent(&fep->pdev->dev,
2860 txq->bd.ring_size * TSO_HEADER_SIZE,
2865 for (i = 0; i < fep->num_rx_queues; i++)
2866 kfree(fep->rx_queue[i]);
2867 for (i = 0; i < fep->num_tx_queues; i++)
2868 kfree(fep->tx_queue[i]);
2871 static int fec_enet_alloc_queue(struct net_device *ndev)
2873 struct fec_enet_private *fep = netdev_priv(ndev);
2876 struct fec_enet_priv_tx_q *txq;
2878 for (i = 0; i < fep->num_tx_queues; i++) {
2879 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2885 fep->tx_queue[i] = txq;
2886 txq->bd.ring_size = TX_RING_SIZE;
2887 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2889 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2890 txq->tx_wake_threshold =
2891 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2893 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
2894 txq->bd.ring_size * TSO_HEADER_SIZE,
2897 if (!txq->tso_hdrs) {
2903 for (i = 0; i < fep->num_rx_queues; i++) {
2904 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2906 if (!fep->rx_queue[i]) {
2911 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2912 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2917 fec_enet_free_queue(ndev);
2922 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2924 struct fec_enet_private *fep = netdev_priv(ndev);
2926 struct sk_buff *skb;
2927 struct bufdesc *bdp;
2928 struct fec_enet_priv_rx_q *rxq;
2930 rxq = fep->rx_queue[queue];
2932 for (i = 0; i < rxq->bd.ring_size; i++) {
2933 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2937 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2942 rxq->rx_skbuff[i] = skb;
2943 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2945 if (fep->bufdesc_ex) {
2946 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2947 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2950 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2953 /* Set the last buffer to wrap. */
2954 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2955 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2959 fec_enet_free_buffers(ndev);
2964 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2966 struct fec_enet_private *fep = netdev_priv(ndev);
2968 struct bufdesc *bdp;
2969 struct fec_enet_priv_tx_q *txq;
2971 txq = fep->tx_queue[queue];
2973 for (i = 0; i < txq->bd.ring_size; i++) {
2974 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2975 if (!txq->tx_bounce[i])
2978 bdp->cbd_sc = cpu_to_fec16(0);
2979 bdp->cbd_bufaddr = cpu_to_fec32(0);
2981 if (fep->bufdesc_ex) {
2982 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2983 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2986 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2989 /* Set the last buffer to wrap. */
2990 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2991 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2996 fec_enet_free_buffers(ndev);
3000 static int fec_enet_alloc_buffers(struct net_device *ndev)
3002 struct fec_enet_private *fep = netdev_priv(ndev);
3005 for (i = 0; i < fep->num_rx_queues; i++)
3006 if (fec_enet_alloc_rxq_buffers(ndev, i))
3009 for (i = 0; i < fep->num_tx_queues; i++)
3010 if (fec_enet_alloc_txq_buffers(ndev, i))
3016 fec_enet_open(struct net_device *ndev)
3018 struct fec_enet_private *fep = netdev_priv(ndev);
3022 ret = pm_runtime_resume_and_get(&fep->pdev->dev);
3026 pinctrl_pm_select_default_state(&fep->pdev->dev);
3027 ret = fec_enet_clk_enable(ndev, true);
3031 /* During the first fec_enet_open call the PHY isn't probed at this
3032 * point. Therefore the phy_reset_after_clk_enable() call within
3033 * fec_enet_clk_enable() fails. As we need this reset in order to be
3034 * sure the PHY is working correctly we check if we need to reset again
3035 * later when the PHY is probed
3037 if (ndev->phydev && ndev->phydev->drv)
3038 reset_again = false;
3042 /* I should reset the ring buffers here, but I don't yet know
3043 * a simple way to do that.
3046 ret = fec_enet_alloc_buffers(ndev);
3048 goto err_enet_alloc;
3050 /* Init MAC prior to mii bus probe */
3053 /* Call phy_reset_after_clk_enable() again if it failed during
3054 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
3057 fec_enet_phy_reset_after_clk_enable(ndev);
3059 /* Probe and connect to PHY when open the interface */
3060 ret = fec_enet_mii_probe(ndev);
3062 goto err_enet_mii_probe;
3064 if (fep->quirks & FEC_QUIRK_ERR006687)
3065 imx6q_cpuidle_fec_irqs_used();
3067 napi_enable(&fep->napi);
3068 phy_start(ndev->phydev);
3069 netif_tx_start_all_queues(ndev);
3071 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
3072 FEC_WOL_FLAG_ENABLE);
3077 fec_enet_free_buffers(ndev);
3079 fec_enet_clk_enable(ndev, false);
3081 pm_runtime_mark_last_busy(&fep->pdev->dev);
3082 pm_runtime_put_autosuspend(&fep->pdev->dev);
3083 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3088 fec_enet_close(struct net_device *ndev)
3090 struct fec_enet_private *fep = netdev_priv(ndev);
3092 phy_stop(ndev->phydev);
3094 if (netif_device_present(ndev)) {
3095 napi_disable(&fep->napi);
3096 netif_tx_disable(ndev);
3100 phy_disconnect(ndev->phydev);
3102 if (fep->quirks & FEC_QUIRK_ERR006687)
3103 imx6q_cpuidle_fec_irqs_unused();
3105 fec_enet_update_ethtool_stats(ndev);
3107 fec_enet_clk_enable(ndev, false);
3108 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3109 pm_runtime_mark_last_busy(&fep->pdev->dev);
3110 pm_runtime_put_autosuspend(&fep->pdev->dev);
3112 fec_enet_free_buffers(ndev);
3117 /* Set or clear the multicast filter for this adaptor.
3118 * Skeleton taken from sunlance driver.
3119 * The CPM Ethernet implementation allows Multicast as well as individual
3120 * MAC address filtering. Some of the drivers check to make sure it is
3121 * a group multicast address, and discard those that are not. I guess I
3122 * will do the same for now, but just remove the test if you want
3123 * individual filtering as well (do the upper net layers want or support
3124 * this kind of feature?).
3127 #define FEC_HASH_BITS 6 /* #bits in hash */
3129 static void set_multicast_list(struct net_device *ndev)
3131 struct fec_enet_private *fep = netdev_priv(ndev);
3132 struct netdev_hw_addr *ha;
3133 unsigned int crc, tmp;
3135 unsigned int hash_high = 0, hash_low = 0;
3137 if (ndev->flags & IFF_PROMISC) {
3138 tmp = readl(fep->hwp + FEC_R_CNTRL);
3140 writel(tmp, fep->hwp + FEC_R_CNTRL);
3144 tmp = readl(fep->hwp + FEC_R_CNTRL);
3146 writel(tmp, fep->hwp + FEC_R_CNTRL);
3148 if (ndev->flags & IFF_ALLMULTI) {
3149 /* Catch all multicast addresses, so set the
3152 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3153 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3158 /* Add the addresses in hash register */
3159 netdev_for_each_mc_addr(ha, ndev) {
3160 /* calculate crc32 value of mac address */
3161 crc = ether_crc_le(ndev->addr_len, ha->addr);
3163 /* only upper 6 bits (FEC_HASH_BITS) are used
3164 * which point to specific bit in the hash registers
3166 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3169 hash_high |= 1 << (hash - 32);
3171 hash_low |= 1 << hash;
3174 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3175 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3178 /* Set a MAC change in hardware. */
3180 fec_set_mac_address(struct net_device *ndev, void *p)
3182 struct fec_enet_private *fep = netdev_priv(ndev);
3183 struct sockaddr *addr = p;
3186 if (!is_valid_ether_addr(addr->sa_data))
3187 return -EADDRNOTAVAIL;
3188 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3191 /* Add netif status check here to avoid system hang in below case:
3192 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3193 * After ethx down, fec all clocks are gated off and then register
3194 * access causes system hang.
3196 if (!netif_running(ndev))
3199 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3200 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3201 fep->hwp + FEC_ADDR_LOW);
3202 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3203 fep->hwp + FEC_ADDR_HIGH);
3207 #ifdef CONFIG_NET_POLL_CONTROLLER
3209 * fec_poll_controller - FEC Poll controller function
3210 * @dev: The FEC network adapter
3212 * Polled functionality used by netconsole and others in non interrupt mode
3215 static void fec_poll_controller(struct net_device *dev)
3218 struct fec_enet_private *fep = netdev_priv(dev);
3220 for (i = 0; i < FEC_IRQ_NUM; i++) {
3221 if (fep->irq[i] > 0) {
3222 disable_irq(fep->irq[i]);
3223 fec_enet_interrupt(fep->irq[i], dev);
3224 enable_irq(fep->irq[i]);
3230 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3231 netdev_features_t features)
3233 struct fec_enet_private *fep = netdev_priv(netdev);
3234 netdev_features_t changed = features ^ netdev->features;
3236 netdev->features = features;
3238 /* Receive checksum has been changed */
3239 if (changed & NETIF_F_RXCSUM) {
3240 if (features & NETIF_F_RXCSUM)
3241 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3243 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3247 static int fec_set_features(struct net_device *netdev,
3248 netdev_features_t features)
3250 struct fec_enet_private *fep = netdev_priv(netdev);
3251 netdev_features_t changed = features ^ netdev->features;
3253 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3254 napi_disable(&fep->napi);
3255 netif_tx_lock_bh(netdev);
3257 fec_enet_set_netdev_features(netdev, features);
3258 fec_restart(netdev);
3259 netif_tx_wake_all_queues(netdev);
3260 netif_tx_unlock_bh(netdev);
3261 napi_enable(&fep->napi);
3263 fec_enet_set_netdev_features(netdev, features);
3269 static u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb)
3271 struct vlan_ethhdr *vhdr;
3272 unsigned short vlan_TCI = 0;
3274 if (skb->protocol == htons(ETH_P_ALL)) {
3275 vhdr = (struct vlan_ethhdr *)(skb->data);
3276 vlan_TCI = ntohs(vhdr->h_vlan_TCI);
3282 static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb,
3283 struct net_device *sb_dev)
3285 struct fec_enet_private *fep = netdev_priv(ndev);
3288 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
3289 return netdev_pick_tx(ndev, skb, NULL);
3291 vlan_tag = fec_enet_get_raw_vlan_tci(skb);
3295 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13];
3298 static const struct net_device_ops fec_netdev_ops = {
3299 .ndo_open = fec_enet_open,
3300 .ndo_stop = fec_enet_close,
3301 .ndo_start_xmit = fec_enet_start_xmit,
3302 .ndo_select_queue = fec_enet_select_queue,
3303 .ndo_set_rx_mode = set_multicast_list,
3304 .ndo_validate_addr = eth_validate_addr,
3305 .ndo_tx_timeout = fec_timeout,
3306 .ndo_set_mac_address = fec_set_mac_address,
3307 .ndo_do_ioctl = fec_enet_ioctl,
3308 #ifdef CONFIG_NET_POLL_CONTROLLER
3309 .ndo_poll_controller = fec_poll_controller,
3311 .ndo_set_features = fec_set_features,
3314 static const unsigned short offset_des_active_rxq[] = {
3315 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3318 static const unsigned short offset_des_active_txq[] = {
3319 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3323 * XXX: We need to clean up on failure exits here.
3326 static int fec_enet_init(struct net_device *ndev)
3328 struct fec_enet_private *fep = netdev_priv(ndev);
3329 struct bufdesc *cbd_base;
3333 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3334 sizeof(struct bufdesc);
3335 unsigned dsize_log2 = __fls(dsize);
3338 WARN_ON(dsize != (1 << dsize_log2));
3339 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
3340 fep->rx_align = 0xf;
3341 fep->tx_align = 0xf;
3343 fep->rx_align = 0x3;
3344 fep->tx_align = 0x3;
3347 /* Check mask of the streaming and coherent API */
3348 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
3350 dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
3354 ret = fec_enet_alloc_queue(ndev);
3358 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3360 /* Allocate memory for buffer descriptors. */
3361 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3365 goto free_queue_mem;
3368 /* Get the Ethernet address */
3370 /* make sure MAC we just acquired is programmed into the hw */
3371 fec_set_mac_address(ndev, NULL);
3373 /* Set receive and transmit descriptor base. */
3374 for (i = 0; i < fep->num_rx_queues; i++) {
3375 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3376 unsigned size = dsize * rxq->bd.ring_size;
3379 rxq->bd.base = cbd_base;
3380 rxq->bd.cur = cbd_base;
3381 rxq->bd.dma = bd_dma;
3382 rxq->bd.dsize = dsize;
3383 rxq->bd.dsize_log2 = dsize_log2;
3384 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3386 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3387 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3390 for (i = 0; i < fep->num_tx_queues; i++) {
3391 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3392 unsigned size = dsize * txq->bd.ring_size;
3395 txq->bd.base = cbd_base;
3396 txq->bd.cur = cbd_base;
3397 txq->bd.dma = bd_dma;
3398 txq->bd.dsize = dsize;
3399 txq->bd.dsize_log2 = dsize_log2;
3400 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3402 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3403 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3407 /* The FEC Ethernet specific entries in the device structure */
3408 ndev->watchdog_timeo = TX_TIMEOUT;
3409 ndev->netdev_ops = &fec_netdev_ops;
3410 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3412 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3413 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3415 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3416 /* enable hw VLAN support */
3417 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3419 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3420 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3422 /* enable hw accelerator */
3423 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3424 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3425 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3428 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3430 fep->rx_align = 0x3f;
3433 ndev->hw_features = ndev->features;
3437 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3438 fec_enet_clear_ethtool_stats(ndev);
3440 fec_enet_update_ethtool_stats(ndev);
3445 fec_enet_free_queue(ndev);
3450 static int fec_reset_phy(struct platform_device *pdev)
3453 bool active_high = false;
3454 int msec = 1, phy_post_delay = 0;
3455 struct device_node *np = pdev->dev.of_node;
3460 err = of_property_read_u32(np, "phy-reset-duration", &msec);
3461 /* A sane reset duration should not be longer than 1s */
3462 if (!err && msec > 1000)
3465 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3466 if (phy_reset == -EPROBE_DEFER)
3468 else if (!gpio_is_valid(phy_reset))
3471 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
3472 /* valid reset duration should be less than 1s */
3473 if (!err && phy_post_delay > 1000)
3476 active_high = of_property_read_bool(np, "phy-reset-active-high");
3478 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3479 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3482 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3489 usleep_range(msec * 1000, msec * 1000 + 1000);
3491 gpio_set_value_cansleep(phy_reset, !active_high);
3493 if (!phy_post_delay)
3496 if (phy_post_delay > 20)
3497 msleep(phy_post_delay);
3499 usleep_range(phy_post_delay * 1000,
3500 phy_post_delay * 1000 + 1000);
3504 #else /* CONFIG_OF */
3505 static int fec_reset_phy(struct platform_device *pdev)
3508 * In case of platform probe, the reset has been done
3513 #endif /* CONFIG_OF */
3516 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3518 struct device_node *np = pdev->dev.of_node;
3520 *num_tx = *num_rx = 1;
3522 if (!np || !of_device_is_available(np))
3525 /* parse the num of tx and rx queues */
3526 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3528 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3530 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3531 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3537 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3538 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3546 static int fec_enet_get_irq_cnt(struct platform_device *pdev)
3548 int irq_cnt = platform_irq_count(pdev);
3550 if (irq_cnt > FEC_IRQ_NUM)
3551 irq_cnt = FEC_IRQ_NUM; /* last for pps */
3552 else if (irq_cnt == 2)
3553 irq_cnt = 1; /* last for pps */
3554 else if (irq_cnt <= 0)
3555 irq_cnt = 1; /* At least 1 irq is needed */
3559 static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
3560 struct device_node *np)
3562 struct device_node *gpr_np;
3566 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0);
3570 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
3571 ARRAY_SIZE(out_val));
3573 dev_dbg(&fep->pdev->dev, "no stop mode property\n");
3577 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);
3578 if (IS_ERR(fep->stop_gpr.gpr)) {
3579 dev_err(&fep->pdev->dev, "could not find gpr regmap\n");
3580 ret = PTR_ERR(fep->stop_gpr.gpr);
3581 fep->stop_gpr.gpr = NULL;
3585 fep->stop_gpr.reg = out_val[1];
3586 fep->stop_gpr.bit = out_val[2];
3589 of_node_put(gpr_np);
3595 fec_probe(struct platform_device *pdev)
3597 struct fec_enet_private *fep;
3598 struct fec_platform_data *pdata;
3599 phy_interface_t interface;
3600 struct net_device *ndev;
3601 int i, irq, ret = 0;
3602 const struct of_device_id *of_id;
3604 struct device_node *np = pdev->dev.of_node, *phy_node;
3609 struct fec_devinfo *dev_info;
3611 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3613 /* Init network device */
3614 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
3615 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
3619 SET_NETDEV_DEV(ndev, &pdev->dev);
3621 /* setup board info structure */
3622 fep = netdev_priv(ndev);
3624 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3626 pdev->id_entry = of_id->data;
3627 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data;
3629 fep->quirks = dev_info->quirks;
3632 fep->num_rx_queues = num_rx_qs;
3633 fep->num_tx_queues = num_tx_qs;
3635 #if !defined(CONFIG_M5272)
3636 /* default enable pause frame auto negotiation */
3637 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3638 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3641 /* Select default pin state */
3642 pinctrl_pm_select_default_state(&pdev->dev);
3644 fep->hwp = devm_platform_ioremap_resource(pdev, 0);
3645 if (IS_ERR(fep->hwp)) {
3646 ret = PTR_ERR(fep->hwp);
3647 goto failed_ioremap;
3651 fep->dev_id = dev_id++;
3653 platform_set_drvdata(pdev, ndev);
3655 if ((of_machine_is_compatible("fsl,imx6q") ||
3656 of_machine_is_compatible("fsl,imx6dl")) &&
3657 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3658 fep->quirks |= FEC_QUIRK_ERR006687;
3660 if (of_get_property(np, "fsl,magic-packet", NULL))
3661 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3663 ret = fec_enet_init_stop_mode(fep, np);
3665 goto failed_stop_mode;
3667 phy_node = of_parse_phandle(np, "phy-handle", 0);
3668 if (!phy_node && of_phy_is_fixed_link(np)) {
3669 ret = of_phy_register_fixed_link(np);
3672 "broken fixed-link specification\n");
3675 phy_node = of_node_get(np);
3677 fep->phy_node = phy_node;
3679 ret = of_get_phy_mode(pdev->dev.of_node, &interface);
3681 pdata = dev_get_platdata(&pdev->dev);
3683 fep->phy_interface = pdata->phy;
3685 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3687 fep->phy_interface = interface;
3690 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3691 if (IS_ERR(fep->clk_ipg)) {
3692 ret = PTR_ERR(fep->clk_ipg);
3696 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3697 if (IS_ERR(fep->clk_ahb)) {
3698 ret = PTR_ERR(fep->clk_ahb);
3702 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3704 /* enet_out is optional, depends on board */
3705 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3706 if (IS_ERR(fep->clk_enet_out))
3707 fep->clk_enet_out = NULL;
3709 fep->ptp_clk_on = false;
3710 mutex_init(&fep->ptp_clk_mutex);
3712 /* clk_ref is optional, depends on board */
3713 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3714 if (IS_ERR(fep->clk_ref))
3715 fep->clk_ref = NULL;
3717 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3718 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3719 if (IS_ERR(fep->clk_ptp)) {
3720 fep->clk_ptp = NULL;
3721 fep->bufdesc_ex = false;
3724 ret = fec_enet_clk_enable(ndev, true);
3728 ret = clk_prepare_enable(fep->clk_ipg);
3730 goto failed_clk_ipg;
3731 ret = clk_prepare_enable(fep->clk_ahb);
3733 goto failed_clk_ahb;
3735 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
3736 if (!IS_ERR(fep->reg_phy)) {
3737 ret = regulator_enable(fep->reg_phy);
3740 "Failed to enable phy regulator: %d\n", ret);
3741 goto failed_regulator;
3744 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
3745 ret = -EPROBE_DEFER;
3746 goto failed_regulator;
3748 fep->reg_phy = NULL;
3751 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3752 pm_runtime_use_autosuspend(&pdev->dev);
3753 pm_runtime_get_noresume(&pdev->dev);
3754 pm_runtime_set_active(&pdev->dev);
3755 pm_runtime_enable(&pdev->dev);
3757 ret = fec_reset_phy(pdev);
3761 irq_cnt = fec_enet_get_irq_cnt(pdev);
3762 if (fep->bufdesc_ex)
3763 fec_ptp_init(pdev, irq_cnt);
3765 ret = fec_enet_init(ndev);
3769 for (i = 0; i < irq_cnt; i++) {
3770 snprintf(irq_name, sizeof(irq_name), "int%d", i);
3771 irq = platform_get_irq_byname_optional(pdev, irq_name);
3773 irq = platform_get_irq(pdev, i);
3778 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3779 0, pdev->name, ndev);
3786 ret = fec_enet_mii_init(pdev);
3788 goto failed_mii_init;
3790 /* Carrier starts down, phylib will bring it up */
3791 netif_carrier_off(ndev);
3792 fec_enet_clk_enable(ndev, false);
3793 pinctrl_pm_select_sleep_state(&pdev->dev);
3795 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN;
3797 ret = register_netdev(ndev);
3799 goto failed_register;
3801 device_init_wakeup(&ndev->dev, fep->wol_flag &
3802 FEC_WOL_HAS_MAGIC_PACKET);
3804 if (fep->bufdesc_ex && fep->ptp_clock)
3805 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3807 fep->rx_copybreak = COPYBREAK_DEFAULT;
3808 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3810 pm_runtime_mark_last_busy(&pdev->dev);
3811 pm_runtime_put_autosuspend(&pdev->dev);
3816 fec_enet_mii_remove(fep);
3822 pm_runtime_put_noidle(&pdev->dev);
3823 pm_runtime_disable(&pdev->dev);
3825 regulator_disable(fep->reg_phy);
3827 clk_disable_unprepare(fep->clk_ahb);
3829 clk_disable_unprepare(fep->clk_ipg);
3831 fec_enet_clk_enable(ndev, false);
3833 if (of_phy_is_fixed_link(np))
3834 of_phy_deregister_fixed_link(np);
3835 of_node_put(phy_node);
3846 fec_drv_remove(struct platform_device *pdev)
3848 struct net_device *ndev = platform_get_drvdata(pdev);
3849 struct fec_enet_private *fep = netdev_priv(ndev);
3850 struct device_node *np = pdev->dev.of_node;
3853 ret = pm_runtime_resume_and_get(&pdev->dev);
3857 cancel_work_sync(&fep->tx_timeout_work);
3859 unregister_netdev(ndev);
3860 fec_enet_mii_remove(fep);
3862 regulator_disable(fep->reg_phy);
3864 if (of_phy_is_fixed_link(np))
3865 of_phy_deregister_fixed_link(np);
3866 of_node_put(fep->phy_node);
3868 clk_disable_unprepare(fep->clk_ahb);
3869 clk_disable_unprepare(fep->clk_ipg);
3870 pm_runtime_put_noidle(&pdev->dev);
3871 pm_runtime_disable(&pdev->dev);
3877 static int __maybe_unused fec_suspend(struct device *dev)
3879 struct net_device *ndev = dev_get_drvdata(dev);
3880 struct fec_enet_private *fep = netdev_priv(ndev);
3883 if (netif_running(ndev)) {
3884 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3885 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3886 phy_stop(ndev->phydev);
3887 napi_disable(&fep->napi);
3888 netif_tx_lock_bh(ndev);
3889 netif_device_detach(ndev);
3890 netif_tx_unlock_bh(ndev);
3892 fec_enet_clk_enable(ndev, false);
3893 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3894 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3898 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3899 regulator_disable(fep->reg_phy);
3901 /* SOC supply clock to phy, when clock is disabled, phy link down
3902 * SOC control phy regulator, when regulator is disabled, phy link down
3904 if (fep->clk_enet_out || fep->reg_phy)
3910 static int __maybe_unused fec_resume(struct device *dev)
3912 struct net_device *ndev = dev_get_drvdata(dev);
3913 struct fec_enet_private *fep = netdev_priv(ndev);
3917 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3918 ret = regulator_enable(fep->reg_phy);
3924 if (netif_running(ndev)) {
3925 ret = fec_enet_clk_enable(ndev, true);
3930 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3931 fec_enet_stop_mode(fep, false);
3933 val = readl(fep->hwp + FEC_ECNTRL);
3934 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3935 writel(val, fep->hwp + FEC_ECNTRL);
3936 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3938 pinctrl_pm_select_default_state(&fep->pdev->dev);
3941 netif_tx_lock_bh(ndev);
3942 netif_device_attach(ndev);
3943 netif_tx_unlock_bh(ndev);
3944 napi_enable(&fep->napi);
3945 phy_start(ndev->phydev);
3953 regulator_disable(fep->reg_phy);
3957 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3959 struct net_device *ndev = dev_get_drvdata(dev);
3960 struct fec_enet_private *fep = netdev_priv(ndev);
3962 clk_disable_unprepare(fep->clk_ahb);
3963 clk_disable_unprepare(fep->clk_ipg);
3968 static int __maybe_unused fec_runtime_resume(struct device *dev)
3970 struct net_device *ndev = dev_get_drvdata(dev);
3971 struct fec_enet_private *fep = netdev_priv(ndev);
3974 ret = clk_prepare_enable(fep->clk_ahb);
3977 ret = clk_prepare_enable(fep->clk_ipg);
3979 goto failed_clk_ipg;
3984 clk_disable_unprepare(fep->clk_ahb);
3988 static const struct dev_pm_ops fec_pm_ops = {
3989 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3990 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3993 static struct platform_driver fec_driver = {
3995 .name = DRIVER_NAME,
3997 .of_match_table = fec_dt_ids,
3998 .suppress_bind_attrs = true,
4000 .id_table = fec_devtype,
4002 .remove = fec_drv_remove,
4005 module_platform_driver(fec_driver);
4007 MODULE_ALIAS("platform:"DRIVER_NAME);
4008 MODULE_LICENSE("GPL");