1 // SPDX-License-Identifier: GPL-2.0+
3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
6 * Right now, I am very wasteful with the buffers. I allocate memory
7 * pages and then divide them into 2K frame buffers. This way I know I
8 * have buffers large enough to hold one frame within one buffer descriptor.
9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10 * will be much more memory efficient and will easily handle lots of
13 * Much better multiple PHY support by Magnus Damm.
14 * Copyright (c) 2000 Ericsson Radio Systems AB.
16 * Support for FEC controller of ColdFire processors.
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/ptrace.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/icmp.h>
45 #include <linux/spinlock.h>
46 #include <linux/workqueue.h>
47 #include <linux/bitops.h>
49 #include <linux/irq.h>
50 #include <linux/clk.h>
51 #include <linux/crc32.h>
52 #include <linux/platform_device.h>
53 #include <linux/mdio.h>
54 #include <linux/phy.h>
55 #include <linux/fec.h>
57 #include <linux/of_device.h>
58 #include <linux/of_gpio.h>
59 #include <linux/of_mdio.h>
60 #include <linux/of_net.h>
61 #include <linux/regulator/consumer.h>
62 #include <linux/if_vlan.h>
63 #include <linux/pinctrl/consumer.h>
64 #include <linux/prefetch.h>
65 #include <linux/mfd/syscon.h>
66 #include <linux/regmap.h>
67 #include <soc/imx/cpuidle.h>
69 #include <asm/cacheflush.h>
73 static void set_multicast_list(struct net_device *ndev);
74 static void fec_enet_itr_coal_init(struct net_device *ndev);
76 #define DRIVER_NAME "fec"
78 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
80 /* Pause frame feild and FIFO threshold */
81 #define FEC_ENET_FCE (1 << 5)
82 #define FEC_ENET_RSEM_V 0x84
83 #define FEC_ENET_RSFL_V 16
84 #define FEC_ENET_RAEM_V 0x8
85 #define FEC_ENET_RAFL_V 0x8
86 #define FEC_ENET_OPD_V 0xFFF0
87 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
95 static const struct fec_devinfo fec_imx25_info = {
96 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
100 static const struct fec_devinfo fec_imx27_info = {
101 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG,
104 static const struct fec_devinfo fec_imx28_info = {
105 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
106 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
110 static const struct fec_devinfo fec_imx6q_info = {
111 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
112 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
113 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
115 .stop_gpr_reg = 0x34,
119 static const struct fec_devinfo fec_mvf600_info = {
120 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
123 static const struct fec_devinfo fec_imx6x_info = {
124 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
125 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
126 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
127 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
128 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
131 static const struct fec_devinfo fec_imx6ul_info = {
132 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
133 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
134 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
135 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
136 FEC_QUIRK_HAS_COALESCE,
139 static struct platform_device_id fec_devtype[] = {
141 /* keep it for coldfire */
146 .driver_data = (kernel_ulong_t)&fec_imx25_info,
149 .driver_data = (kernel_ulong_t)&fec_imx27_info,
152 .driver_data = (kernel_ulong_t)&fec_imx28_info,
155 .driver_data = (kernel_ulong_t)&fec_imx6q_info,
157 .name = "mvf600-fec",
158 .driver_data = (kernel_ulong_t)&fec_mvf600_info,
160 .name = "imx6sx-fec",
161 .driver_data = (kernel_ulong_t)&fec_imx6x_info,
163 .name = "imx6ul-fec",
164 .driver_data = (kernel_ulong_t)&fec_imx6ul_info,
169 MODULE_DEVICE_TABLE(platform, fec_devtype);
172 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
173 IMX27_FEC, /* runs on i.mx27/35/51 */
181 static const struct of_device_id fec_dt_ids[] = {
182 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
183 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
184 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
185 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
186 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
187 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
188 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
191 MODULE_DEVICE_TABLE(of, fec_dt_ids);
193 static unsigned char macaddr[ETH_ALEN];
194 module_param_array(macaddr, byte, NULL, 0);
195 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
197 #if defined(CONFIG_M5272)
199 * Some hardware gets it MAC address out of local flash memory.
200 * if this is non-zero then assume it is the address to get MAC from.
202 #if defined(CONFIG_NETtel)
203 #define FEC_FLASHMAC 0xf0006006
204 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
205 #define FEC_FLASHMAC 0xf0006000
206 #elif defined(CONFIG_CANCam)
207 #define FEC_FLASHMAC 0xf0020000
208 #elif defined (CONFIG_M5272C3)
209 #define FEC_FLASHMAC (0xffe04000 + 4)
210 #elif defined(CONFIG_MOD5272)
211 #define FEC_FLASHMAC 0xffc0406b
213 #define FEC_FLASHMAC 0
215 #endif /* CONFIG_M5272 */
217 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
219 * 2048 byte skbufs are allocated. However, alignment requirements
220 * varies between FEC variants. Worst case is 64, so round down by 64.
222 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
223 #define PKT_MINBUF_SIZE 64
225 /* FEC receive acceleration */
226 #define FEC_RACC_IPDIS (1 << 1)
227 #define FEC_RACC_PRODIS (1 << 2)
228 #define FEC_RACC_SHIFT16 BIT(7)
229 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
231 /* MIB Control Register */
232 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
235 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
236 * size bits. Other FEC hardware does not, so we need to take that into
237 * account when setting it.
239 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
240 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
241 defined(CONFIG_ARM64)
242 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
244 #define OPT_FRAME_SIZE 0
247 /* FEC MII MMFR bits definition */
248 #define FEC_MMFR_ST (1 << 30)
249 #define FEC_MMFR_OP_READ (2 << 28)
250 #define FEC_MMFR_OP_WRITE (1 << 28)
251 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
252 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
253 #define FEC_MMFR_TA (2 << 16)
254 #define FEC_MMFR_DATA(v) (v & 0xffff)
255 /* FEC ECR bits definition */
256 #define FEC_ECR_MAGICEN (1 << 2)
257 #define FEC_ECR_SLEEP (1 << 3)
259 #define FEC_MII_TIMEOUT 30000 /* us */
261 /* Transmitter timeout */
262 #define TX_TIMEOUT (2 * HZ)
264 #define FEC_PAUSE_FLAG_AUTONEG 0x1
265 #define FEC_PAUSE_FLAG_ENABLE 0x2
266 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
267 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
268 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
270 #define COPYBREAK_DEFAULT 256
272 /* Max number of allowed TCP segments for software TSO */
273 #define FEC_MAX_TSO_SEGS 100
274 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
276 #define IS_TSO_HEADER(txq, addr) \
277 ((addr >= txq->tso_hdrs_dma) && \
278 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
282 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
283 struct bufdesc_prop *bd)
285 return (bdp >= bd->last) ? bd->base
286 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
289 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
290 struct bufdesc_prop *bd)
292 return (bdp <= bd->base) ? bd->last
293 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
296 static int fec_enet_get_bd_index(struct bufdesc *bdp,
297 struct bufdesc_prop *bd)
299 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
302 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
306 entries = (((const char *)txq->dirty_tx -
307 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
309 return entries >= 0 ? entries : entries + txq->bd.ring_size;
312 static void swap_buffer(void *bufaddr, int len)
315 unsigned int *buf = bufaddr;
317 for (i = 0; i < len; i += 4, buf++)
321 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
324 unsigned int *src = src_buf;
325 unsigned int *dst = dst_buf;
327 for (i = 0; i < len; i += 4, src++, dst++)
331 static void fec_dump(struct net_device *ndev)
333 struct fec_enet_private *fep = netdev_priv(ndev);
335 struct fec_enet_priv_tx_q *txq;
338 netdev_info(ndev, "TX ring dump\n");
339 pr_info("Nr SC addr len SKB\n");
341 txq = fep->tx_queue[0];
345 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
347 bdp == txq->bd.cur ? 'S' : ' ',
348 bdp == txq->dirty_tx ? 'H' : ' ',
349 fec16_to_cpu(bdp->cbd_sc),
350 fec32_to_cpu(bdp->cbd_bufaddr),
351 fec16_to_cpu(bdp->cbd_datlen),
352 txq->tx_skbuff[index]);
353 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
355 } while (bdp != txq->bd.base);
358 static inline bool is_ipv4_pkt(struct sk_buff *skb)
360 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
364 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
366 /* Only run for packets requiring a checksum. */
367 if (skb->ip_summed != CHECKSUM_PARTIAL)
370 if (unlikely(skb_cow_head(skb, 0)))
373 if (is_ipv4_pkt(skb))
374 ip_hdr(skb)->check = 0;
375 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
380 static struct bufdesc *
381 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
383 struct net_device *ndev)
385 struct fec_enet_private *fep = netdev_priv(ndev);
386 struct bufdesc *bdp = txq->bd.cur;
387 struct bufdesc_ex *ebdp;
388 int nr_frags = skb_shinfo(skb)->nr_frags;
390 unsigned short status;
391 unsigned int estatus = 0;
392 skb_frag_t *this_frag;
398 for (frag = 0; frag < nr_frags; frag++) {
399 this_frag = &skb_shinfo(skb)->frags[frag];
400 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
401 ebdp = (struct bufdesc_ex *)bdp;
403 status = fec16_to_cpu(bdp->cbd_sc);
404 status &= ~BD_ENET_TX_STATS;
405 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
406 frag_len = skb_shinfo(skb)->frags[frag].size;
408 /* Handle the last BD specially */
409 if (frag == nr_frags - 1) {
410 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
411 if (fep->bufdesc_ex) {
412 estatus |= BD_ENET_TX_INT;
413 if (unlikely(skb_shinfo(skb)->tx_flags &
414 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
415 estatus |= BD_ENET_TX_TS;
419 if (fep->bufdesc_ex) {
420 if (fep->quirks & FEC_QUIRK_HAS_AVB)
421 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
422 if (skb->ip_summed == CHECKSUM_PARTIAL)
423 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
425 ebdp->cbd_esc = cpu_to_fec32(estatus);
428 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
430 index = fec_enet_get_bd_index(bdp, &txq->bd);
431 if (((unsigned long) bufaddr) & fep->tx_align ||
432 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
433 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
434 bufaddr = txq->tx_bounce[index];
436 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
437 swap_buffer(bufaddr, frag_len);
440 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
442 if (dma_mapping_error(&fep->pdev->dev, addr)) {
444 netdev_err(ndev, "Tx DMA memory map failed\n");
445 goto dma_mapping_error;
448 bdp->cbd_bufaddr = cpu_to_fec32(addr);
449 bdp->cbd_datlen = cpu_to_fec16(frag_len);
450 /* Make sure the updates to rest of the descriptor are
451 * performed before transferring ownership.
454 bdp->cbd_sc = cpu_to_fec16(status);
460 for (i = 0; i < frag; i++) {
461 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
462 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
463 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
465 return ERR_PTR(-ENOMEM);
468 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
469 struct sk_buff *skb, struct net_device *ndev)
471 struct fec_enet_private *fep = netdev_priv(ndev);
472 int nr_frags = skb_shinfo(skb)->nr_frags;
473 struct bufdesc *bdp, *last_bdp;
476 unsigned short status;
477 unsigned short buflen;
478 unsigned int estatus = 0;
482 entries_free = fec_enet_get_free_txdesc_num(txq);
483 if (entries_free < MAX_SKB_FRAGS + 1) {
484 dev_kfree_skb_any(skb);
486 netdev_err(ndev, "NOT enough BD for SG!\n");
490 /* Protocol checksum off-load for TCP and UDP. */
491 if (fec_enet_clear_csum(skb, ndev)) {
492 dev_kfree_skb_any(skb);
496 /* Fill in a Tx ring entry */
499 status = fec16_to_cpu(bdp->cbd_sc);
500 status &= ~BD_ENET_TX_STATS;
502 /* Set buffer length and buffer pointer */
504 buflen = skb_headlen(skb);
506 index = fec_enet_get_bd_index(bdp, &txq->bd);
507 if (((unsigned long) bufaddr) & fep->tx_align ||
508 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
509 memcpy(txq->tx_bounce[index], skb->data, buflen);
510 bufaddr = txq->tx_bounce[index];
512 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
513 swap_buffer(bufaddr, buflen);
516 /* Push the data cache so the CPM does not get stale memory data. */
517 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
518 if (dma_mapping_error(&fep->pdev->dev, addr)) {
519 dev_kfree_skb_any(skb);
521 netdev_err(ndev, "Tx DMA memory map failed\n");
526 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
527 if (IS_ERR(last_bdp)) {
528 dma_unmap_single(&fep->pdev->dev, addr,
529 buflen, DMA_TO_DEVICE);
530 dev_kfree_skb_any(skb);
534 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
535 if (fep->bufdesc_ex) {
536 estatus = BD_ENET_TX_INT;
537 if (unlikely(skb_shinfo(skb)->tx_flags &
538 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
539 estatus |= BD_ENET_TX_TS;
542 bdp->cbd_bufaddr = cpu_to_fec32(addr);
543 bdp->cbd_datlen = cpu_to_fec16(buflen);
545 if (fep->bufdesc_ex) {
547 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
549 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
551 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
553 if (fep->quirks & FEC_QUIRK_HAS_AVB)
554 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
556 if (skb->ip_summed == CHECKSUM_PARTIAL)
557 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
560 ebdp->cbd_esc = cpu_to_fec32(estatus);
563 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
564 /* Save skb pointer */
565 txq->tx_skbuff[index] = skb;
567 /* Make sure the updates to rest of the descriptor are performed before
568 * transferring ownership.
572 /* Send it on its way. Tell FEC it's ready, interrupt when done,
573 * it's the last BD of the frame, and to put the CRC on the end.
575 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
576 bdp->cbd_sc = cpu_to_fec16(status);
578 /* If this was the last BD in the ring, start at the beginning again. */
579 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
581 skb_tx_timestamp(skb);
583 /* Make sure the update to bdp and tx_skbuff are performed before
589 /* Trigger transmission start */
590 writel(0, txq->bd.reg_desc_active);
596 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
597 struct net_device *ndev,
598 struct bufdesc *bdp, int index, char *data,
599 int size, bool last_tcp, bool is_last)
601 struct fec_enet_private *fep = netdev_priv(ndev);
602 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
603 unsigned short status;
604 unsigned int estatus = 0;
607 status = fec16_to_cpu(bdp->cbd_sc);
608 status &= ~BD_ENET_TX_STATS;
610 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
612 if (((unsigned long) data) & fep->tx_align ||
613 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
614 memcpy(txq->tx_bounce[index], data, size);
615 data = txq->tx_bounce[index];
617 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
618 swap_buffer(data, size);
621 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
622 if (dma_mapping_error(&fep->pdev->dev, addr)) {
623 dev_kfree_skb_any(skb);
625 netdev_err(ndev, "Tx DMA memory map failed\n");
626 return NETDEV_TX_BUSY;
629 bdp->cbd_datlen = cpu_to_fec16(size);
630 bdp->cbd_bufaddr = cpu_to_fec32(addr);
632 if (fep->bufdesc_ex) {
633 if (fep->quirks & FEC_QUIRK_HAS_AVB)
634 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
635 if (skb->ip_summed == CHECKSUM_PARTIAL)
636 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
638 ebdp->cbd_esc = cpu_to_fec32(estatus);
641 /* Handle the last BD specially */
643 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
645 status |= BD_ENET_TX_INTR;
647 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
650 bdp->cbd_sc = cpu_to_fec16(status);
656 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
657 struct sk_buff *skb, struct net_device *ndev,
658 struct bufdesc *bdp, int index)
660 struct fec_enet_private *fep = netdev_priv(ndev);
661 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
662 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
664 unsigned long dmabuf;
665 unsigned short status;
666 unsigned int estatus = 0;
668 status = fec16_to_cpu(bdp->cbd_sc);
669 status &= ~BD_ENET_TX_STATS;
670 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
672 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
673 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
674 if (((unsigned long)bufaddr) & fep->tx_align ||
675 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
676 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
677 bufaddr = txq->tx_bounce[index];
679 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
680 swap_buffer(bufaddr, hdr_len);
682 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
683 hdr_len, DMA_TO_DEVICE);
684 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
685 dev_kfree_skb_any(skb);
687 netdev_err(ndev, "Tx DMA memory map failed\n");
688 return NETDEV_TX_BUSY;
692 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
693 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
695 if (fep->bufdesc_ex) {
696 if (fep->quirks & FEC_QUIRK_HAS_AVB)
697 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
698 if (skb->ip_summed == CHECKSUM_PARTIAL)
699 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
701 ebdp->cbd_esc = cpu_to_fec32(estatus);
704 bdp->cbd_sc = cpu_to_fec16(status);
709 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
711 struct net_device *ndev)
713 struct fec_enet_private *fep = netdev_priv(ndev);
714 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
715 int total_len, data_left;
716 struct bufdesc *bdp = txq->bd.cur;
718 unsigned int index = 0;
721 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
722 dev_kfree_skb_any(skb);
724 netdev_err(ndev, "NOT enough BD for TSO!\n");
728 /* Protocol checksum off-load for TCP and UDP. */
729 if (fec_enet_clear_csum(skb, ndev)) {
730 dev_kfree_skb_any(skb);
734 /* Initialize the TSO handler, and prepare the first payload */
735 tso_start(skb, &tso);
737 total_len = skb->len - hdr_len;
738 while (total_len > 0) {
741 index = fec_enet_get_bd_index(bdp, &txq->bd);
742 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
743 total_len -= data_left;
745 /* prepare packet headers: MAC + IP + TCP */
746 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
747 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
748 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
752 while (data_left > 0) {
755 size = min_t(int, tso.size, data_left);
756 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
757 index = fec_enet_get_bd_index(bdp, &txq->bd);
758 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
767 tso_build_data(skb, &tso, size);
770 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
773 /* Save skb pointer */
774 txq->tx_skbuff[index] = skb;
776 skb_tx_timestamp(skb);
779 /* Trigger transmission start */
780 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
781 !readl(txq->bd.reg_desc_active) ||
782 !readl(txq->bd.reg_desc_active) ||
783 !readl(txq->bd.reg_desc_active) ||
784 !readl(txq->bd.reg_desc_active))
785 writel(0, txq->bd.reg_desc_active);
790 /* TODO: Release all used data descriptors for TSO */
795 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
797 struct fec_enet_private *fep = netdev_priv(ndev);
799 unsigned short queue;
800 struct fec_enet_priv_tx_q *txq;
801 struct netdev_queue *nq;
804 queue = skb_get_queue_mapping(skb);
805 txq = fep->tx_queue[queue];
806 nq = netdev_get_tx_queue(ndev, queue);
809 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
811 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
815 entries_free = fec_enet_get_free_txdesc_num(txq);
816 if (entries_free <= txq->tx_stop_threshold)
817 netif_tx_stop_queue(nq);
822 /* Init RX & TX buffer descriptors
824 static void fec_enet_bd_init(struct net_device *dev)
826 struct fec_enet_private *fep = netdev_priv(dev);
827 struct fec_enet_priv_tx_q *txq;
828 struct fec_enet_priv_rx_q *rxq;
833 for (q = 0; q < fep->num_rx_queues; q++) {
834 /* Initialize the receive buffer descriptors. */
835 rxq = fep->rx_queue[q];
838 for (i = 0; i < rxq->bd.ring_size; i++) {
840 /* Initialize the BD for every fragment in the page. */
841 if (bdp->cbd_bufaddr)
842 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
844 bdp->cbd_sc = cpu_to_fec16(0);
845 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
848 /* Set the last buffer to wrap */
849 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
850 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
852 rxq->bd.cur = rxq->bd.base;
855 for (q = 0; q < fep->num_tx_queues; q++) {
856 /* ...and the same for transmit */
857 txq = fep->tx_queue[q];
861 for (i = 0; i < txq->bd.ring_size; i++) {
862 /* Initialize the BD for every fragment in the page. */
863 bdp->cbd_sc = cpu_to_fec16(0);
864 if (bdp->cbd_bufaddr &&
865 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
866 dma_unmap_single(&fep->pdev->dev,
867 fec32_to_cpu(bdp->cbd_bufaddr),
868 fec16_to_cpu(bdp->cbd_datlen),
870 if (txq->tx_skbuff[i]) {
871 dev_kfree_skb_any(txq->tx_skbuff[i]);
872 txq->tx_skbuff[i] = NULL;
874 bdp->cbd_bufaddr = cpu_to_fec32(0);
875 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
878 /* Set the last buffer to wrap */
879 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
880 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
885 static void fec_enet_active_rxring(struct net_device *ndev)
887 struct fec_enet_private *fep = netdev_priv(ndev);
890 for (i = 0; i < fep->num_rx_queues; i++)
891 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
894 static void fec_enet_enable_ring(struct net_device *ndev)
896 struct fec_enet_private *fep = netdev_priv(ndev);
897 struct fec_enet_priv_tx_q *txq;
898 struct fec_enet_priv_rx_q *rxq;
901 for (i = 0; i < fep->num_rx_queues; i++) {
902 rxq = fep->rx_queue[i];
903 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
904 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
908 writel(RCMR_MATCHEN | RCMR_CMP(i),
909 fep->hwp + FEC_RCMR(i));
912 for (i = 0; i < fep->num_tx_queues; i++) {
913 txq = fep->tx_queue[i];
914 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
918 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
919 fep->hwp + FEC_DMA_CFG(i));
923 static void fec_enet_reset_skb(struct net_device *ndev)
925 struct fec_enet_private *fep = netdev_priv(ndev);
926 struct fec_enet_priv_tx_q *txq;
929 for (i = 0; i < fep->num_tx_queues; i++) {
930 txq = fep->tx_queue[i];
932 for (j = 0; j < txq->bd.ring_size; j++) {
933 if (txq->tx_skbuff[j]) {
934 dev_kfree_skb_any(txq->tx_skbuff[j]);
935 txq->tx_skbuff[j] = NULL;
942 * This function is called to start or restart the FEC during a link
943 * change, transmit timeout, or to reconfigure the FEC. The network
944 * packet processing for this device must be stopped before this call.
947 fec_restart(struct net_device *ndev)
949 struct fec_enet_private *fep = netdev_priv(ndev);
952 u32 rcntl = OPT_FRAME_SIZE | 0x04;
953 u32 ecntl = 0x2; /* ETHEREN */
955 /* Whack a reset. We should wait for this.
956 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
957 * instead of reset MAC itself.
959 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
960 writel(0, fep->hwp + FEC_ECNTRL);
962 writel(1, fep->hwp + FEC_ECNTRL);
967 * enet-mac reset will reset mac address registers too,
968 * so need to reconfigure it.
970 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
971 writel((__force u32)cpu_to_be32(temp_mac[0]),
972 fep->hwp + FEC_ADDR_LOW);
973 writel((__force u32)cpu_to_be32(temp_mac[1]),
974 fep->hwp + FEC_ADDR_HIGH);
976 /* Clear any outstanding interrupt. */
977 writel(0xffffffff, fep->hwp + FEC_IEVENT);
979 fec_enet_bd_init(ndev);
981 fec_enet_enable_ring(ndev);
983 /* Reset tx SKB buffers. */
984 fec_enet_reset_skb(ndev);
986 /* Enable MII mode */
987 if (fep->full_duplex == DUPLEX_FULL) {
989 writel(0x04, fep->hwp + FEC_X_CNTRL);
993 writel(0x0, fep->hwp + FEC_X_CNTRL);
997 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
999 #if !defined(CONFIG_M5272)
1000 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1001 val = readl(fep->hwp + FEC_RACC);
1002 /* align IP header */
1003 val |= FEC_RACC_SHIFT16;
1004 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
1005 /* set RX checksum */
1006 val |= FEC_RACC_OPTIONS;
1008 val &= ~FEC_RACC_OPTIONS;
1009 writel(val, fep->hwp + FEC_RACC);
1010 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
1015 * The phy interface and speed need to get configured
1016 * differently on enet-mac.
1018 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1019 /* Enable flow control and length check */
1020 rcntl |= 0x40000000 | 0x00000020;
1022 /* RGMII, RMII or MII */
1023 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1024 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1025 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1026 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1028 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1033 /* 1G, 100M or 10M */
1035 if (ndev->phydev->speed == SPEED_1000)
1037 else if (ndev->phydev->speed == SPEED_100)
1043 #ifdef FEC_MIIGSK_ENR
1044 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1046 /* disable the gasket and wait */
1047 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1048 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1052 * configure the gasket:
1053 * RMII, 50 MHz, no loopback, no echo
1054 * MII, 25 MHz, no loopback, no echo
1056 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1057 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1058 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1059 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1060 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1062 /* re-enable the gasket */
1063 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1068 #if !defined(CONFIG_M5272)
1069 /* enable pause frame*/
1070 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1071 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1072 ndev->phydev && ndev->phydev->pause)) {
1073 rcntl |= FEC_ENET_FCE;
1075 /* set FIFO threshold parameter to reduce overrun */
1076 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1077 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1078 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1079 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1082 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1084 rcntl &= ~FEC_ENET_FCE;
1086 #endif /* !defined(CONFIG_M5272) */
1088 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1090 /* Setup multicast filter. */
1091 set_multicast_list(ndev);
1092 #ifndef CONFIG_M5272
1093 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1094 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1097 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1098 /* enable ENET endian swap */
1100 /* enable ENET store and forward mode */
1101 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1104 if (fep->bufdesc_ex)
1107 #ifndef CONFIG_M5272
1108 /* Enable the MIB statistic event counters */
1109 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1112 /* And last, enable the transmit and receive processing */
1113 writel(ecntl, fep->hwp + FEC_ECNTRL);
1114 fec_enet_active_rxring(ndev);
1116 if (fep->bufdesc_ex)
1117 fec_ptp_start_cyclecounter(ndev);
1119 /* Enable interrupts we wish to service */
1121 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1123 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1125 /* Init the interrupt coalescing */
1126 fec_enet_itr_coal_init(ndev);
1130 static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled)
1132 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1133 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr;
1135 if (stop_gpr->gpr) {
1137 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1139 BIT(stop_gpr->bit));
1141 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1142 BIT(stop_gpr->bit), 0);
1143 } else if (pdata && pdata->sleep_mode_enable) {
1144 pdata->sleep_mode_enable(enabled);
1149 fec_stop(struct net_device *ndev)
1151 struct fec_enet_private *fep = netdev_priv(ndev);
1152 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1155 /* We cannot expect a graceful transmit stop without link !!! */
1157 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1159 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1160 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1163 /* Whack a reset. We should wait for this.
1164 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1165 * instead of reset MAC itself.
1167 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1168 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1169 writel(0, fep->hwp + FEC_ECNTRL);
1171 writel(1, fep->hwp + FEC_ECNTRL);
1174 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1176 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1177 val = readl(fep->hwp + FEC_ECNTRL);
1178 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1179 writel(val, fep->hwp + FEC_ECNTRL);
1180 fec_enet_stop_mode(fep, true);
1182 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1184 /* We have to keep ENET enabled to have MII interrupt stay working */
1185 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1186 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1187 writel(2, fep->hwp + FEC_ECNTRL);
1188 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1194 fec_timeout(struct net_device *ndev)
1196 struct fec_enet_private *fep = netdev_priv(ndev);
1200 ndev->stats.tx_errors++;
1202 schedule_work(&fep->tx_timeout_work);
1205 static void fec_enet_timeout_work(struct work_struct *work)
1207 struct fec_enet_private *fep =
1208 container_of(work, struct fec_enet_private, tx_timeout_work);
1209 struct net_device *ndev = fep->netdev;
1212 if (netif_device_present(ndev) || netif_running(ndev)) {
1213 napi_disable(&fep->napi);
1214 netif_tx_lock_bh(ndev);
1216 netif_tx_wake_all_queues(ndev);
1217 netif_tx_unlock_bh(ndev);
1218 napi_enable(&fep->napi);
1224 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1225 struct skb_shared_hwtstamps *hwtstamps)
1227 unsigned long flags;
1230 spin_lock_irqsave(&fep->tmreg_lock, flags);
1231 ns = timecounter_cyc2time(&fep->tc, ts);
1232 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1234 memset(hwtstamps, 0, sizeof(*hwtstamps));
1235 hwtstamps->hwtstamp = ns_to_ktime(ns);
1239 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1241 struct fec_enet_private *fep;
1242 struct bufdesc *bdp;
1243 unsigned short status;
1244 struct sk_buff *skb;
1245 struct fec_enet_priv_tx_q *txq;
1246 struct netdev_queue *nq;
1250 fep = netdev_priv(ndev);
1252 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1254 txq = fep->tx_queue[queue_id];
1255 /* get next bdp of dirty_tx */
1256 nq = netdev_get_tx_queue(ndev, queue_id);
1257 bdp = txq->dirty_tx;
1259 /* get next bdp of dirty_tx */
1260 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1262 while (bdp != READ_ONCE(txq->bd.cur)) {
1263 /* Order the load of bd.cur and cbd_sc */
1265 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1266 if (status & BD_ENET_TX_READY)
1269 index = fec_enet_get_bd_index(bdp, &txq->bd);
1271 skb = txq->tx_skbuff[index];
1272 txq->tx_skbuff[index] = NULL;
1273 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1274 dma_unmap_single(&fep->pdev->dev,
1275 fec32_to_cpu(bdp->cbd_bufaddr),
1276 fec16_to_cpu(bdp->cbd_datlen),
1278 bdp->cbd_bufaddr = cpu_to_fec32(0);
1282 /* Check for errors. */
1283 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1284 BD_ENET_TX_RL | BD_ENET_TX_UN |
1286 ndev->stats.tx_errors++;
1287 if (status & BD_ENET_TX_HB) /* No heartbeat */
1288 ndev->stats.tx_heartbeat_errors++;
1289 if (status & BD_ENET_TX_LC) /* Late collision */
1290 ndev->stats.tx_window_errors++;
1291 if (status & BD_ENET_TX_RL) /* Retrans limit */
1292 ndev->stats.tx_aborted_errors++;
1293 if (status & BD_ENET_TX_UN) /* Underrun */
1294 ndev->stats.tx_fifo_errors++;
1295 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1296 ndev->stats.tx_carrier_errors++;
1298 ndev->stats.tx_packets++;
1299 ndev->stats.tx_bytes += skb->len;
1302 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1304 struct skb_shared_hwtstamps shhwtstamps;
1305 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1307 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1308 skb_tstamp_tx(skb, &shhwtstamps);
1311 /* Deferred means some collisions occurred during transmit,
1312 * but we eventually sent the packet OK.
1314 if (status & BD_ENET_TX_DEF)
1315 ndev->stats.collisions++;
1317 /* Free the sk buffer associated with this last transmit */
1318 dev_kfree_skb_any(skb);
1320 /* Make sure the update to bdp and tx_skbuff are performed
1324 txq->dirty_tx = bdp;
1326 /* Update pointer to next buffer descriptor to be transmitted */
1327 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1329 /* Since we have freed up a buffer, the ring is no longer full
1331 if (netif_tx_queue_stopped(nq)) {
1332 entries_free = fec_enet_get_free_txdesc_num(txq);
1333 if (entries_free >= txq->tx_wake_threshold)
1334 netif_tx_wake_queue(nq);
1338 /* ERR006358: Keep the transmitter going */
1339 if (bdp != txq->bd.cur &&
1340 readl(txq->bd.reg_desc_active) == 0)
1341 writel(0, txq->bd.reg_desc_active);
1345 fec_enet_tx(struct net_device *ndev)
1347 struct fec_enet_private *fep = netdev_priv(ndev);
1349 /* First process class A queue, then Class B and Best Effort queue */
1350 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1351 clear_bit(queue_id, &fep->work_tx);
1352 fec_enet_tx_queue(ndev, queue_id);
1358 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1360 struct fec_enet_private *fep = netdev_priv(ndev);
1363 off = ((unsigned long)skb->data) & fep->rx_align;
1365 skb_reserve(skb, fep->rx_align + 1 - off);
1367 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1368 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1369 if (net_ratelimit())
1370 netdev_err(ndev, "Rx DMA memory map failed\n");
1377 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1378 struct bufdesc *bdp, u32 length, bool swap)
1380 struct fec_enet_private *fep = netdev_priv(ndev);
1381 struct sk_buff *new_skb;
1383 if (length > fep->rx_copybreak)
1386 new_skb = netdev_alloc_skb(ndev, length);
1390 dma_sync_single_for_cpu(&fep->pdev->dev,
1391 fec32_to_cpu(bdp->cbd_bufaddr),
1392 FEC_ENET_RX_FRSIZE - fep->rx_align,
1395 memcpy(new_skb->data, (*skb)->data, length);
1397 swap_buffer2(new_skb->data, (*skb)->data, length);
1403 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1404 * When we update through the ring, if the next incoming buffer has
1405 * not been given to the system, we just set the empty indicator,
1406 * effectively tossing the packet.
1409 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1411 struct fec_enet_private *fep = netdev_priv(ndev);
1412 struct fec_enet_priv_rx_q *rxq;
1413 struct bufdesc *bdp;
1414 unsigned short status;
1415 struct sk_buff *skb_new = NULL;
1416 struct sk_buff *skb;
1419 int pkt_received = 0;
1420 struct bufdesc_ex *ebdp = NULL;
1421 bool vlan_packet_rcvd = false;
1425 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1430 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1431 rxq = fep->rx_queue[queue_id];
1433 /* First, grab all of the stats for the incoming packet.
1434 * These get messed up if we get called due to a busy condition.
1438 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1440 if (pkt_received >= budget)
1444 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1446 /* Check for errors. */
1447 status ^= BD_ENET_RX_LAST;
1448 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1449 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1451 ndev->stats.rx_errors++;
1452 if (status & BD_ENET_RX_OV) {
1454 ndev->stats.rx_fifo_errors++;
1455 goto rx_processing_done;
1457 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1458 | BD_ENET_RX_LAST)) {
1459 /* Frame too long or too short. */
1460 ndev->stats.rx_length_errors++;
1461 if (status & BD_ENET_RX_LAST)
1462 netdev_err(ndev, "rcv is not +last\n");
1464 if (status & BD_ENET_RX_CR) /* CRC Error */
1465 ndev->stats.rx_crc_errors++;
1466 /* Report late collisions as a frame error. */
1467 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1468 ndev->stats.rx_frame_errors++;
1469 goto rx_processing_done;
1472 /* Process the incoming frame. */
1473 ndev->stats.rx_packets++;
1474 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1475 ndev->stats.rx_bytes += pkt_len;
1477 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1478 skb = rxq->rx_skbuff[index];
1480 /* The packet length includes FCS, but we don't want to
1481 * include that when passing upstream as it messes up
1482 * bridging applications.
1484 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1486 if (!is_copybreak) {
1487 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1488 if (unlikely(!skb_new)) {
1489 ndev->stats.rx_dropped++;
1490 goto rx_processing_done;
1492 dma_unmap_single(&fep->pdev->dev,
1493 fec32_to_cpu(bdp->cbd_bufaddr),
1494 FEC_ENET_RX_FRSIZE - fep->rx_align,
1498 prefetch(skb->data - NET_IP_ALIGN);
1499 skb_put(skb, pkt_len - 4);
1502 if (!is_copybreak && need_swap)
1503 swap_buffer(data, pkt_len);
1505 #if !defined(CONFIG_M5272)
1506 if (fep->quirks & FEC_QUIRK_HAS_RACC)
1507 data = skb_pull_inline(skb, 2);
1510 /* Extract the enhanced buffer descriptor */
1512 if (fep->bufdesc_ex)
1513 ebdp = (struct bufdesc_ex *)bdp;
1515 /* If this is a VLAN packet remove the VLAN Tag */
1516 vlan_packet_rcvd = false;
1517 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1519 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1520 /* Push and remove the vlan tag */
1521 struct vlan_hdr *vlan_header =
1522 (struct vlan_hdr *) (data + ETH_HLEN);
1523 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1525 vlan_packet_rcvd = true;
1527 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1528 skb_pull(skb, VLAN_HLEN);
1531 skb->protocol = eth_type_trans(skb, ndev);
1533 /* Get receive timestamp from the skb */
1534 if (fep->hwts_rx_en && fep->bufdesc_ex)
1535 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1536 skb_hwtstamps(skb));
1538 if (fep->bufdesc_ex &&
1539 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1540 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1541 /* don't check it */
1542 skb->ip_summed = CHECKSUM_UNNECESSARY;
1544 skb_checksum_none_assert(skb);
1548 /* Handle received VLAN packets */
1549 if (vlan_packet_rcvd)
1550 __vlan_hwaccel_put_tag(skb,
1554 napi_gro_receive(&fep->napi, skb);
1557 dma_sync_single_for_device(&fep->pdev->dev,
1558 fec32_to_cpu(bdp->cbd_bufaddr),
1559 FEC_ENET_RX_FRSIZE - fep->rx_align,
1562 rxq->rx_skbuff[index] = skb_new;
1563 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1567 /* Clear the status flags for this buffer */
1568 status &= ~BD_ENET_RX_STATS;
1570 /* Mark the buffer empty */
1571 status |= BD_ENET_RX_EMPTY;
1573 if (fep->bufdesc_ex) {
1574 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1576 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1580 /* Make sure the updates to rest of the descriptor are
1581 * performed before transferring ownership.
1584 bdp->cbd_sc = cpu_to_fec16(status);
1586 /* Update BD pointer to next entry */
1587 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1589 /* Doing this here will keep the FEC running while we process
1590 * incoming frames. On a heavily loaded network, we should be
1591 * able to keep up at the expense of system resources.
1593 writel(0, rxq->bd.reg_desc_active);
1596 return pkt_received;
1600 fec_enet_rx(struct net_device *ndev, int budget)
1602 int pkt_received = 0;
1604 struct fec_enet_private *fep = netdev_priv(ndev);
1606 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1609 ret = fec_enet_rx_queue(ndev,
1610 budget - pkt_received, queue_id);
1612 if (ret < budget - pkt_received)
1613 clear_bit(queue_id, &fep->work_rx);
1615 pkt_received += ret;
1617 return pkt_received;
1621 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1623 if (int_events == 0)
1626 if (int_events & FEC_ENET_RXF_0)
1627 fep->work_rx |= (1 << 2);
1628 if (int_events & FEC_ENET_RXF_1)
1629 fep->work_rx |= (1 << 0);
1630 if (int_events & FEC_ENET_RXF_2)
1631 fep->work_rx |= (1 << 1);
1633 if (int_events & FEC_ENET_TXF_0)
1634 fep->work_tx |= (1 << 2);
1635 if (int_events & FEC_ENET_TXF_1)
1636 fep->work_tx |= (1 << 0);
1637 if (int_events & FEC_ENET_TXF_2)
1638 fep->work_tx |= (1 << 1);
1644 fec_enet_interrupt(int irq, void *dev_id)
1646 struct net_device *ndev = dev_id;
1647 struct fec_enet_private *fep = netdev_priv(ndev);
1649 irqreturn_t ret = IRQ_NONE;
1651 int_events = readl(fep->hwp + FEC_IEVENT);
1652 writel(int_events, fep->hwp + FEC_IEVENT);
1653 fec_enet_collect_events(fep, int_events);
1655 if ((fep->work_tx || fep->work_rx) && fep->link) {
1658 if (napi_schedule_prep(&fep->napi)) {
1659 /* Disable the NAPI interrupts */
1660 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
1661 __napi_schedule(&fep->napi);
1665 if (int_events & FEC_ENET_MII) {
1667 complete(&fep->mdio_done);
1672 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1674 struct net_device *ndev = napi->dev;
1675 struct fec_enet_private *fep = netdev_priv(ndev);
1678 pkts = fec_enet_rx(ndev, budget);
1682 if (pkts < budget) {
1683 napi_complete_done(napi, pkts);
1684 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1689 /* ------------------------------------------------------------------------- */
1690 static void fec_get_mac(struct net_device *ndev)
1692 struct fec_enet_private *fep = netdev_priv(ndev);
1693 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1694 unsigned char *iap, tmpaddr[ETH_ALEN];
1697 * try to get mac address in following order:
1699 * 1) module parameter via kernel command line in form
1700 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1705 * 2) from device tree data
1707 if (!is_valid_ether_addr(iap)) {
1708 struct device_node *np = fep->pdev->dev.of_node;
1710 const char *mac = of_get_mac_address(np);
1712 iap = (unsigned char *) mac;
1717 * 3) from flash or fuse (via platform data)
1719 if (!is_valid_ether_addr(iap)) {
1722 iap = (unsigned char *)FEC_FLASHMAC;
1725 iap = (unsigned char *)&pdata->mac;
1730 * 4) FEC mac registers set by bootloader
1732 if (!is_valid_ether_addr(iap)) {
1733 *((__be32 *) &tmpaddr[0]) =
1734 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1735 *((__be16 *) &tmpaddr[4]) =
1736 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1741 * 5) random mac address
1743 if (!is_valid_ether_addr(iap)) {
1744 /* Report it and use a random ethernet address instead */
1745 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
1746 eth_hw_addr_random(ndev);
1747 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
1752 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1754 /* Adjust MAC if using macaddr */
1756 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1759 /* ------------------------------------------------------------------------- */
1764 static void fec_enet_adjust_link(struct net_device *ndev)
1766 struct fec_enet_private *fep = netdev_priv(ndev);
1767 struct phy_device *phy_dev = ndev->phydev;
1768 int status_change = 0;
1770 /* Prevent a state halted on mii error */
1771 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1772 phy_dev->state = PHY_RESUMING;
1777 * If the netdev is down, or is going down, we're not interested
1778 * in link state events, so just mark our idea of the link as down
1779 * and ignore the event.
1781 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1783 } else if (phy_dev->link) {
1785 fep->link = phy_dev->link;
1789 if (fep->full_duplex != phy_dev->duplex) {
1790 fep->full_duplex = phy_dev->duplex;
1794 if (phy_dev->speed != fep->speed) {
1795 fep->speed = phy_dev->speed;
1799 /* if any of the above changed restart the FEC */
1800 if (status_change) {
1801 napi_disable(&fep->napi);
1802 netif_tx_lock_bh(ndev);
1804 netif_tx_wake_all_queues(ndev);
1805 netif_tx_unlock_bh(ndev);
1806 napi_enable(&fep->napi);
1810 napi_disable(&fep->napi);
1811 netif_tx_lock_bh(ndev);
1813 netif_tx_unlock_bh(ndev);
1814 napi_enable(&fep->napi);
1815 fep->link = phy_dev->link;
1821 phy_print_status(phy_dev);
1824 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1826 struct fec_enet_private *fep = bus->priv;
1827 struct device *dev = &fep->pdev->dev;
1828 unsigned long time_left;
1831 ret = pm_runtime_get_sync(dev);
1835 fep->mii_timeout = 0;
1836 reinit_completion(&fep->mdio_done);
1838 /* start a read op */
1839 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1840 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1841 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1843 /* wait for end of transfer */
1844 time_left = wait_for_completion_timeout(&fep->mdio_done,
1845 usecs_to_jiffies(FEC_MII_TIMEOUT));
1846 if (time_left == 0) {
1847 fep->mii_timeout = 1;
1848 netdev_err(fep->netdev, "MDIO read timeout\n");
1853 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1856 pm_runtime_mark_last_busy(dev);
1857 pm_runtime_put_autosuspend(dev);
1862 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1865 struct fec_enet_private *fep = bus->priv;
1866 struct device *dev = &fep->pdev->dev;
1867 unsigned long time_left;
1870 ret = pm_runtime_get_sync(dev);
1876 fep->mii_timeout = 0;
1877 reinit_completion(&fep->mdio_done);
1879 /* start a write op */
1880 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1881 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1882 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1883 fep->hwp + FEC_MII_DATA);
1885 /* wait for end of transfer */
1886 time_left = wait_for_completion_timeout(&fep->mdio_done,
1887 usecs_to_jiffies(FEC_MII_TIMEOUT));
1888 if (time_left == 0) {
1889 fep->mii_timeout = 1;
1890 netdev_err(fep->netdev, "MDIO write timeout\n");
1894 pm_runtime_mark_last_busy(dev);
1895 pm_runtime_put_autosuspend(dev);
1900 static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev)
1902 struct fec_enet_private *fep = netdev_priv(ndev);
1903 struct phy_device *phy_dev = ndev->phydev;
1906 phy_reset_after_clk_enable(phy_dev);
1907 } else if (fep->phy_node) {
1909 * If the PHY still is not bound to the MAC, but there is
1910 * OF PHY node and a matching PHY device instance already,
1911 * use the OF PHY node to obtain the PHY device instance,
1912 * and then use that PHY device instance when triggering
1915 phy_dev = of_phy_find_device(fep->phy_node);
1916 phy_reset_after_clk_enable(phy_dev);
1917 put_device(&phy_dev->mdio.dev);
1921 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1923 struct fec_enet_private *fep = netdev_priv(ndev);
1927 ret = clk_prepare_enable(fep->clk_enet_out);
1932 mutex_lock(&fep->ptp_clk_mutex);
1933 ret = clk_prepare_enable(fep->clk_ptp);
1935 mutex_unlock(&fep->ptp_clk_mutex);
1936 goto failed_clk_ptp;
1938 fep->ptp_clk_on = true;
1940 mutex_unlock(&fep->ptp_clk_mutex);
1943 ret = clk_prepare_enable(fep->clk_ref);
1945 goto failed_clk_ref;
1947 fec_enet_phy_reset_after_clk_enable(ndev);
1949 clk_disable_unprepare(fep->clk_enet_out);
1951 mutex_lock(&fep->ptp_clk_mutex);
1952 clk_disable_unprepare(fep->clk_ptp);
1953 fep->ptp_clk_on = false;
1954 mutex_unlock(&fep->ptp_clk_mutex);
1956 clk_disable_unprepare(fep->clk_ref);
1963 clk_disable_unprepare(fep->clk_ref);
1965 if (fep->clk_enet_out)
1966 clk_disable_unprepare(fep->clk_enet_out);
1971 static int fec_enet_mii_probe(struct net_device *ndev)
1973 struct fec_enet_private *fep = netdev_priv(ndev);
1974 struct phy_device *phy_dev = NULL;
1975 char mdio_bus_id[MII_BUS_ID_SIZE];
1976 char phy_name[MII_BUS_ID_SIZE + 3];
1978 int dev_id = fep->dev_id;
1980 if (fep->phy_node) {
1981 phy_dev = of_phy_connect(ndev, fep->phy_node,
1982 &fec_enet_adjust_link, 0,
1983 fep->phy_interface);
1985 netdev_err(ndev, "Unable to connect to phy\n");
1989 /* check for attached phy */
1990 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1991 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1995 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1999 if (phy_id >= PHY_MAX_ADDR) {
2000 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
2001 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
2005 snprintf(phy_name, sizeof(phy_name),
2006 PHY_ID_FMT, mdio_bus_id, phy_id);
2007 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
2008 fep->phy_interface);
2011 if (IS_ERR(phy_dev)) {
2012 netdev_err(ndev, "could not attach to PHY\n");
2013 return PTR_ERR(phy_dev);
2016 /* mask with MAC supported features */
2017 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
2018 phy_dev->supported &= PHY_GBIT_FEATURES;
2019 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
2020 #if !defined(CONFIG_M5272)
2021 phy_dev->supported |= SUPPORTED_Pause;
2025 phy_dev->supported &= PHY_BASIC_FEATURES;
2027 phy_dev->advertising = phy_dev->supported;
2030 fep->full_duplex = 0;
2032 phy_attached_info(phy_dev);
2037 static int fec_enet_mii_init(struct platform_device *pdev)
2039 static struct mii_bus *fec0_mii_bus;
2040 struct net_device *ndev = platform_get_drvdata(pdev);
2041 struct fec_enet_private *fep = netdev_priv(ndev);
2042 struct device_node *node;
2044 u32 mii_speed, holdtime;
2047 * The i.MX28 dual fec interfaces are not equal.
2048 * Here are the differences:
2050 * - fec0 supports MII & RMII modes while fec1 only supports RMII
2051 * - fec0 acts as the 1588 time master while fec1 is slave
2052 * - external phys can only be configured by fec0
2054 * That is to say fec1 can not work independently. It only works
2055 * when fec0 is working. The reason behind this design is that the
2056 * second interface is added primarily for Switch mode.
2058 * Because of the last point above, both phys are attached on fec0
2059 * mdio interface in board design, and need to be configured by
2062 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2063 /* fec1 uses fec0 mii_bus */
2064 if (mii_cnt && fec0_mii_bus) {
2065 fep->mii_bus = fec0_mii_bus;
2072 fep->mii_timeout = 0;
2075 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
2077 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2078 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2079 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2082 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2083 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2085 if (mii_speed > 63) {
2087 "fec clock (%lu) too fast to get right mii speed\n",
2088 clk_get_rate(fep->clk_ipg));
2094 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2095 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2096 * versions are RAZ there, so just ignore the difference and write the
2098 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2099 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2101 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2102 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2103 * holdtime cannot result in a value greater than 3.
2105 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2107 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2109 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2111 fep->mii_bus = mdiobus_alloc();
2112 if (fep->mii_bus == NULL) {
2117 fep->mii_bus->name = "fec_enet_mii_bus";
2118 fep->mii_bus->read = fec_enet_mdio_read;
2119 fep->mii_bus->write = fec_enet_mdio_write;
2120 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2121 pdev->name, fep->dev_id + 1);
2122 fep->mii_bus->priv = fep;
2123 fep->mii_bus->parent = &pdev->dev;
2125 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2126 err = of_mdiobus_register(fep->mii_bus, node);
2130 goto err_out_free_mdiobus;
2134 /* save fec0 mii_bus */
2135 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2136 fec0_mii_bus = fep->mii_bus;
2140 err_out_free_mdiobus:
2141 mdiobus_free(fep->mii_bus);
2146 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2148 if (--mii_cnt == 0) {
2149 mdiobus_unregister(fep->mii_bus);
2150 mdiobus_free(fep->mii_bus);
2154 static void fec_enet_get_drvinfo(struct net_device *ndev,
2155 struct ethtool_drvinfo *info)
2157 struct fec_enet_private *fep = netdev_priv(ndev);
2159 strlcpy(info->driver, fep->pdev->dev.driver->name,
2160 sizeof(info->driver));
2161 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2162 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2165 static int fec_enet_get_regs_len(struct net_device *ndev)
2167 struct fec_enet_private *fep = netdev_priv(ndev);
2171 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2173 s = resource_size(r);
2178 /* List of registers that can be safety be read to dump them with ethtool */
2179 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2180 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2181 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2182 static u32 fec_enet_register_offset[] = {
2183 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2184 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2185 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2186 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2187 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2188 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2189 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2190 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2191 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2192 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2193 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2194 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2195 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2196 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2197 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2198 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2199 RMON_T_P_GTE2048, RMON_T_OCTETS,
2200 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2201 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2202 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2203 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2204 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2205 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2206 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2207 RMON_R_P_GTE2048, RMON_R_OCTETS,
2208 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2209 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2212 static u32 fec_enet_register_offset[] = {
2213 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2214 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2215 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2216 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2217 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2218 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2219 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2220 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2221 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2225 static void fec_enet_get_regs(struct net_device *ndev,
2226 struct ethtool_regs *regs, void *regbuf)
2228 struct fec_enet_private *fep = netdev_priv(ndev);
2229 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2230 u32 *buf = (u32 *)regbuf;
2233 memset(buf, 0, regs->len);
2235 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2236 off = fec_enet_register_offset[i];
2238 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2239 !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2243 buf[off] = readl(&theregs[off]);
2247 static int fec_enet_get_ts_info(struct net_device *ndev,
2248 struct ethtool_ts_info *info)
2250 struct fec_enet_private *fep = netdev_priv(ndev);
2252 if (fep->bufdesc_ex) {
2254 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2255 SOF_TIMESTAMPING_RX_SOFTWARE |
2256 SOF_TIMESTAMPING_SOFTWARE |
2257 SOF_TIMESTAMPING_TX_HARDWARE |
2258 SOF_TIMESTAMPING_RX_HARDWARE |
2259 SOF_TIMESTAMPING_RAW_HARDWARE;
2261 info->phc_index = ptp_clock_index(fep->ptp_clock);
2263 info->phc_index = -1;
2265 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2266 (1 << HWTSTAMP_TX_ON);
2268 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2269 (1 << HWTSTAMP_FILTER_ALL);
2272 return ethtool_op_get_ts_info(ndev, info);
2276 #if !defined(CONFIG_M5272)
2278 static void fec_enet_get_pauseparam(struct net_device *ndev,
2279 struct ethtool_pauseparam *pause)
2281 struct fec_enet_private *fep = netdev_priv(ndev);
2283 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2284 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2285 pause->rx_pause = pause->tx_pause;
2288 static int fec_enet_set_pauseparam(struct net_device *ndev,
2289 struct ethtool_pauseparam *pause)
2291 struct fec_enet_private *fep = netdev_priv(ndev);
2296 if (pause->tx_pause != pause->rx_pause) {
2298 "hardware only support enable/disable both tx and rx");
2302 fep->pause_flag = 0;
2304 /* tx pause must be same as rx pause */
2305 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2306 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2308 if (pause->rx_pause || pause->autoneg) {
2309 ndev->phydev->supported |= ADVERTISED_Pause;
2310 ndev->phydev->advertising |= ADVERTISED_Pause;
2312 ndev->phydev->supported &= ~ADVERTISED_Pause;
2313 ndev->phydev->advertising &= ~ADVERTISED_Pause;
2316 if (pause->autoneg) {
2317 if (netif_running(ndev))
2319 phy_start_aneg(ndev->phydev);
2321 if (netif_running(ndev)) {
2322 napi_disable(&fep->napi);
2323 netif_tx_lock_bh(ndev);
2325 netif_tx_wake_all_queues(ndev);
2326 netif_tx_unlock_bh(ndev);
2327 napi_enable(&fep->napi);
2333 static const struct fec_stat {
2334 char name[ETH_GSTRING_LEN];
2338 { "tx_dropped", RMON_T_DROP },
2339 { "tx_packets", RMON_T_PACKETS },
2340 { "tx_broadcast", RMON_T_BC_PKT },
2341 { "tx_multicast", RMON_T_MC_PKT },
2342 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2343 { "tx_undersize", RMON_T_UNDERSIZE },
2344 { "tx_oversize", RMON_T_OVERSIZE },
2345 { "tx_fragment", RMON_T_FRAG },
2346 { "tx_jabber", RMON_T_JAB },
2347 { "tx_collision", RMON_T_COL },
2348 { "tx_64byte", RMON_T_P64 },
2349 { "tx_65to127byte", RMON_T_P65TO127 },
2350 { "tx_128to255byte", RMON_T_P128TO255 },
2351 { "tx_256to511byte", RMON_T_P256TO511 },
2352 { "tx_512to1023byte", RMON_T_P512TO1023 },
2353 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2354 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2355 { "tx_octets", RMON_T_OCTETS },
2358 { "IEEE_tx_drop", IEEE_T_DROP },
2359 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2360 { "IEEE_tx_1col", IEEE_T_1COL },
2361 { "IEEE_tx_mcol", IEEE_T_MCOL },
2362 { "IEEE_tx_def", IEEE_T_DEF },
2363 { "IEEE_tx_lcol", IEEE_T_LCOL },
2364 { "IEEE_tx_excol", IEEE_T_EXCOL },
2365 { "IEEE_tx_macerr", IEEE_T_MACERR },
2366 { "IEEE_tx_cserr", IEEE_T_CSERR },
2367 { "IEEE_tx_sqe", IEEE_T_SQE },
2368 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2369 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2372 { "rx_packets", RMON_R_PACKETS },
2373 { "rx_broadcast", RMON_R_BC_PKT },
2374 { "rx_multicast", RMON_R_MC_PKT },
2375 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2376 { "rx_undersize", RMON_R_UNDERSIZE },
2377 { "rx_oversize", RMON_R_OVERSIZE },
2378 { "rx_fragment", RMON_R_FRAG },
2379 { "rx_jabber", RMON_R_JAB },
2380 { "rx_64byte", RMON_R_P64 },
2381 { "rx_65to127byte", RMON_R_P65TO127 },
2382 { "rx_128to255byte", RMON_R_P128TO255 },
2383 { "rx_256to511byte", RMON_R_P256TO511 },
2384 { "rx_512to1023byte", RMON_R_P512TO1023 },
2385 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2386 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2387 { "rx_octets", RMON_R_OCTETS },
2390 { "IEEE_rx_drop", IEEE_R_DROP },
2391 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2392 { "IEEE_rx_crc", IEEE_R_CRC },
2393 { "IEEE_rx_align", IEEE_R_ALIGN },
2394 { "IEEE_rx_macerr", IEEE_R_MACERR },
2395 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2396 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2399 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2401 static void fec_enet_update_ethtool_stats(struct net_device *dev)
2403 struct fec_enet_private *fep = netdev_priv(dev);
2406 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2407 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2410 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2411 struct ethtool_stats *stats, u64 *data)
2413 struct fec_enet_private *fep = netdev_priv(dev);
2415 if (netif_running(dev))
2416 fec_enet_update_ethtool_stats(dev);
2418 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2421 static void fec_enet_get_strings(struct net_device *netdev,
2422 u32 stringset, u8 *data)
2425 switch (stringset) {
2427 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2428 memcpy(data + i * ETH_GSTRING_LEN,
2429 fec_stats[i].name, ETH_GSTRING_LEN);
2434 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2438 return ARRAY_SIZE(fec_stats);
2444 static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2446 struct fec_enet_private *fep = netdev_priv(dev);
2449 /* Disable MIB statistics counters */
2450 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2452 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2453 writel(0, fep->hwp + fec_stats[i].offset);
2455 /* Don't disable MIB statistics counters */
2456 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2459 #else /* !defined(CONFIG_M5272) */
2460 #define FEC_STATS_SIZE 0
2461 static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2465 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2468 #endif /* !defined(CONFIG_M5272) */
2470 /* ITR clock source is enet system clock (clk_ahb).
2471 * TCTT unit is cycle_ns * 64 cycle
2472 * So, the ICTT value = X us / (cycle_ns * 64)
2474 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2476 struct fec_enet_private *fep = netdev_priv(ndev);
2478 return us * (fep->itr_clk_rate / 64000) / 1000;
2481 /* Set threshold for interrupt coalescing */
2482 static void fec_enet_itr_coal_set(struct net_device *ndev)
2484 struct fec_enet_private *fep = netdev_priv(ndev);
2487 /* Must be greater than zero to avoid unpredictable behavior */
2488 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2489 !fep->tx_time_itr || !fep->tx_pkts_itr)
2492 /* Select enet system clock as Interrupt Coalescing
2493 * timer Clock Source
2495 rx_itr = FEC_ITR_CLK_SEL;
2496 tx_itr = FEC_ITR_CLK_SEL;
2498 /* set ICFT and ICTT */
2499 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2500 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2501 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2502 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2504 rx_itr |= FEC_ITR_EN;
2505 tx_itr |= FEC_ITR_EN;
2507 writel(tx_itr, fep->hwp + FEC_TXIC0);
2508 writel(rx_itr, fep->hwp + FEC_RXIC0);
2509 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2510 writel(tx_itr, fep->hwp + FEC_TXIC1);
2511 writel(rx_itr, fep->hwp + FEC_RXIC1);
2512 writel(tx_itr, fep->hwp + FEC_TXIC2);
2513 writel(rx_itr, fep->hwp + FEC_RXIC2);
2518 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2520 struct fec_enet_private *fep = netdev_priv(ndev);
2522 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2525 ec->rx_coalesce_usecs = fep->rx_time_itr;
2526 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2528 ec->tx_coalesce_usecs = fep->tx_time_itr;
2529 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2535 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2537 struct fec_enet_private *fep = netdev_priv(ndev);
2540 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2543 if (ec->rx_max_coalesced_frames > 255) {
2544 pr_err("Rx coalesced frames exceed hardware limitation\n");
2548 if (ec->tx_max_coalesced_frames > 255) {
2549 pr_err("Tx coalesced frame exceed hardware limitation\n");
2553 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs);
2554 if (cycle > 0xFFFF) {
2555 pr_err("Rx coalesced usec exceed hardware limitation\n");
2559 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs);
2560 if (cycle > 0xFFFF) {
2561 pr_err("Tx coalesced usec exceed hardware limitation\n");
2565 fep->rx_time_itr = ec->rx_coalesce_usecs;
2566 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2568 fep->tx_time_itr = ec->tx_coalesce_usecs;
2569 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2571 fec_enet_itr_coal_set(ndev);
2576 static void fec_enet_itr_coal_init(struct net_device *ndev)
2578 struct ethtool_coalesce ec;
2580 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2581 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2583 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2584 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2586 fec_enet_set_coalesce(ndev, &ec);
2589 static int fec_enet_get_tunable(struct net_device *netdev,
2590 const struct ethtool_tunable *tuna,
2593 struct fec_enet_private *fep = netdev_priv(netdev);
2597 case ETHTOOL_RX_COPYBREAK:
2598 *(u32 *)data = fep->rx_copybreak;
2608 static int fec_enet_set_tunable(struct net_device *netdev,
2609 const struct ethtool_tunable *tuna,
2612 struct fec_enet_private *fep = netdev_priv(netdev);
2616 case ETHTOOL_RX_COPYBREAK:
2617 fep->rx_copybreak = *(u32 *)data;
2628 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2630 struct fec_enet_private *fep = netdev_priv(ndev);
2632 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2633 wol->supported = WAKE_MAGIC;
2634 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2636 wol->supported = wol->wolopts = 0;
2641 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2643 struct fec_enet_private *fep = netdev_priv(ndev);
2645 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2648 if (wol->wolopts & ~WAKE_MAGIC)
2651 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2652 if (device_may_wakeup(&ndev->dev)) {
2653 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2654 if (fep->irq[0] > 0)
2655 enable_irq_wake(fep->irq[0]);
2657 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2658 if (fep->irq[0] > 0)
2659 disable_irq_wake(fep->irq[0]);
2665 static const struct ethtool_ops fec_enet_ethtool_ops = {
2666 .get_drvinfo = fec_enet_get_drvinfo,
2667 .get_regs_len = fec_enet_get_regs_len,
2668 .get_regs = fec_enet_get_regs,
2669 .nway_reset = phy_ethtool_nway_reset,
2670 .get_link = ethtool_op_get_link,
2671 .get_coalesce = fec_enet_get_coalesce,
2672 .set_coalesce = fec_enet_set_coalesce,
2673 #ifndef CONFIG_M5272
2674 .get_pauseparam = fec_enet_get_pauseparam,
2675 .set_pauseparam = fec_enet_set_pauseparam,
2676 .get_strings = fec_enet_get_strings,
2677 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2678 .get_sset_count = fec_enet_get_sset_count,
2680 .get_ts_info = fec_enet_get_ts_info,
2681 .get_tunable = fec_enet_get_tunable,
2682 .set_tunable = fec_enet_set_tunable,
2683 .get_wol = fec_enet_get_wol,
2684 .set_wol = fec_enet_set_wol,
2685 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2686 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2689 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2691 struct fec_enet_private *fep = netdev_priv(ndev);
2692 struct phy_device *phydev = ndev->phydev;
2694 if (!netif_running(ndev))
2700 if (fep->bufdesc_ex) {
2701 if (cmd == SIOCSHWTSTAMP)
2702 return fec_ptp_set(ndev, rq);
2703 if (cmd == SIOCGHWTSTAMP)
2704 return fec_ptp_get(ndev, rq);
2707 return phy_mii_ioctl(phydev, rq, cmd);
2710 static void fec_enet_free_buffers(struct net_device *ndev)
2712 struct fec_enet_private *fep = netdev_priv(ndev);
2714 struct sk_buff *skb;
2715 struct bufdesc *bdp;
2716 struct fec_enet_priv_tx_q *txq;
2717 struct fec_enet_priv_rx_q *rxq;
2720 for (q = 0; q < fep->num_rx_queues; q++) {
2721 rxq = fep->rx_queue[q];
2723 for (i = 0; i < rxq->bd.ring_size; i++) {
2724 skb = rxq->rx_skbuff[i];
2725 rxq->rx_skbuff[i] = NULL;
2727 dma_unmap_single(&fep->pdev->dev,
2728 fec32_to_cpu(bdp->cbd_bufaddr),
2729 FEC_ENET_RX_FRSIZE - fep->rx_align,
2733 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2737 for (q = 0; q < fep->num_tx_queues; q++) {
2738 txq = fep->tx_queue[q];
2740 for (i = 0; i < txq->bd.ring_size; i++) {
2741 kfree(txq->tx_bounce[i]);
2742 txq->tx_bounce[i] = NULL;
2743 skb = txq->tx_skbuff[i];
2744 txq->tx_skbuff[i] = NULL;
2750 static void fec_enet_free_queue(struct net_device *ndev)
2752 struct fec_enet_private *fep = netdev_priv(ndev);
2754 struct fec_enet_priv_tx_q *txq;
2756 for (i = 0; i < fep->num_tx_queues; i++)
2757 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2758 txq = fep->tx_queue[i];
2759 dma_free_coherent(&fep->pdev->dev,
2760 txq->bd.ring_size * TSO_HEADER_SIZE,
2765 for (i = 0; i < fep->num_rx_queues; i++)
2766 kfree(fep->rx_queue[i]);
2767 for (i = 0; i < fep->num_tx_queues; i++)
2768 kfree(fep->tx_queue[i]);
2771 static int fec_enet_alloc_queue(struct net_device *ndev)
2773 struct fec_enet_private *fep = netdev_priv(ndev);
2776 struct fec_enet_priv_tx_q *txq;
2778 for (i = 0; i < fep->num_tx_queues; i++) {
2779 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2785 fep->tx_queue[i] = txq;
2786 txq->bd.ring_size = TX_RING_SIZE;
2787 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2789 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2790 txq->tx_wake_threshold =
2791 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2793 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
2794 txq->bd.ring_size * TSO_HEADER_SIZE,
2797 if (!txq->tso_hdrs) {
2803 for (i = 0; i < fep->num_rx_queues; i++) {
2804 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2806 if (!fep->rx_queue[i]) {
2811 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2812 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2817 fec_enet_free_queue(ndev);
2822 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2824 struct fec_enet_private *fep = netdev_priv(ndev);
2826 struct sk_buff *skb;
2827 struct bufdesc *bdp;
2828 struct fec_enet_priv_rx_q *rxq;
2830 rxq = fep->rx_queue[queue];
2832 for (i = 0; i < rxq->bd.ring_size; i++) {
2833 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2837 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2842 rxq->rx_skbuff[i] = skb;
2843 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2845 if (fep->bufdesc_ex) {
2846 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2847 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2850 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2853 /* Set the last buffer to wrap. */
2854 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2855 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2859 fec_enet_free_buffers(ndev);
2864 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2866 struct fec_enet_private *fep = netdev_priv(ndev);
2868 struct bufdesc *bdp;
2869 struct fec_enet_priv_tx_q *txq;
2871 txq = fep->tx_queue[queue];
2873 for (i = 0; i < txq->bd.ring_size; i++) {
2874 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2875 if (!txq->tx_bounce[i])
2878 bdp->cbd_sc = cpu_to_fec16(0);
2879 bdp->cbd_bufaddr = cpu_to_fec32(0);
2881 if (fep->bufdesc_ex) {
2882 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2883 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2886 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2889 /* Set the last buffer to wrap. */
2890 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2891 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2896 fec_enet_free_buffers(ndev);
2900 static int fec_enet_alloc_buffers(struct net_device *ndev)
2902 struct fec_enet_private *fep = netdev_priv(ndev);
2905 for (i = 0; i < fep->num_rx_queues; i++)
2906 if (fec_enet_alloc_rxq_buffers(ndev, i))
2909 for (i = 0; i < fep->num_tx_queues; i++)
2910 if (fec_enet_alloc_txq_buffers(ndev, i))
2916 fec_enet_open(struct net_device *ndev)
2918 struct fec_enet_private *fep = netdev_priv(ndev);
2922 ret = pm_runtime_get_sync(&fep->pdev->dev);
2926 pinctrl_pm_select_default_state(&fep->pdev->dev);
2927 ret = fec_enet_clk_enable(ndev, true);
2931 /* During the first fec_enet_open call the PHY isn't probed at this
2932 * point. Therefore the phy_reset_after_clk_enable() call within
2933 * fec_enet_clk_enable() fails. As we need this reset in order to be
2934 * sure the PHY is working correctly we check if we need to reset again
2935 * later when the PHY is probed
2937 if (ndev->phydev && ndev->phydev->drv)
2938 reset_again = false;
2942 /* I should reset the ring buffers here, but I don't yet know
2943 * a simple way to do that.
2946 ret = fec_enet_alloc_buffers(ndev);
2948 goto err_enet_alloc;
2950 /* Init MAC prior to mii bus probe */
2953 /* Call phy_reset_after_clk_enable() again if it failed during
2954 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
2957 fec_enet_phy_reset_after_clk_enable(ndev);
2959 /* Probe and connect to PHY when open the interface */
2960 ret = fec_enet_mii_probe(ndev);
2962 goto err_enet_mii_probe;
2964 if (fep->quirks & FEC_QUIRK_ERR006687)
2965 imx6q_cpuidle_fec_irqs_used();
2967 napi_enable(&fep->napi);
2968 phy_start(ndev->phydev);
2969 netif_tx_start_all_queues(ndev);
2971 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2972 FEC_WOL_FLAG_ENABLE);
2977 fec_enet_free_buffers(ndev);
2979 fec_enet_clk_enable(ndev, false);
2981 pm_runtime_mark_last_busy(&fep->pdev->dev);
2982 pm_runtime_put_autosuspend(&fep->pdev->dev);
2983 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2988 fec_enet_close(struct net_device *ndev)
2990 struct fec_enet_private *fep = netdev_priv(ndev);
2992 phy_stop(ndev->phydev);
2994 if (netif_device_present(ndev)) {
2995 napi_disable(&fep->napi);
2996 netif_tx_disable(ndev);
3000 phy_disconnect(ndev->phydev);
3002 if (fep->quirks & FEC_QUIRK_ERR006687)
3003 imx6q_cpuidle_fec_irqs_unused();
3005 fec_enet_update_ethtool_stats(ndev);
3007 fec_enet_clk_enable(ndev, false);
3008 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3009 pm_runtime_mark_last_busy(&fep->pdev->dev);
3010 pm_runtime_put_autosuspend(&fep->pdev->dev);
3012 fec_enet_free_buffers(ndev);
3017 /* Set or clear the multicast filter for this adaptor.
3018 * Skeleton taken from sunlance driver.
3019 * The CPM Ethernet implementation allows Multicast as well as individual
3020 * MAC address filtering. Some of the drivers check to make sure it is
3021 * a group multicast address, and discard those that are not. I guess I
3022 * will do the same for now, but just remove the test if you want
3023 * individual filtering as well (do the upper net layers want or support
3024 * this kind of feature?).
3027 #define FEC_HASH_BITS 6 /* #bits in hash */
3029 static void set_multicast_list(struct net_device *ndev)
3031 struct fec_enet_private *fep = netdev_priv(ndev);
3032 struct netdev_hw_addr *ha;
3033 unsigned int crc, tmp;
3035 unsigned int hash_high = 0, hash_low = 0;
3037 if (ndev->flags & IFF_PROMISC) {
3038 tmp = readl(fep->hwp + FEC_R_CNTRL);
3040 writel(tmp, fep->hwp + FEC_R_CNTRL);
3044 tmp = readl(fep->hwp + FEC_R_CNTRL);
3046 writel(tmp, fep->hwp + FEC_R_CNTRL);
3048 if (ndev->flags & IFF_ALLMULTI) {
3049 /* Catch all multicast addresses, so set the
3052 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3053 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3058 /* Add the addresses in hash register */
3059 netdev_for_each_mc_addr(ha, ndev) {
3060 /* calculate crc32 value of mac address */
3061 crc = ether_crc_le(ndev->addr_len, ha->addr);
3063 /* only upper 6 bits (FEC_HASH_BITS) are used
3064 * which point to specific bit in the hash registers
3066 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3069 hash_high |= 1 << (hash - 32);
3071 hash_low |= 1 << hash;
3074 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3075 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3078 /* Set a MAC change in hardware. */
3080 fec_set_mac_address(struct net_device *ndev, void *p)
3082 struct fec_enet_private *fep = netdev_priv(ndev);
3083 struct sockaddr *addr = p;
3086 if (!is_valid_ether_addr(addr->sa_data))
3087 return -EADDRNOTAVAIL;
3088 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3091 /* Add netif status check here to avoid system hang in below case:
3092 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3093 * After ethx down, fec all clocks are gated off and then register
3094 * access causes system hang.
3096 if (!netif_running(ndev))
3099 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3100 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3101 fep->hwp + FEC_ADDR_LOW);
3102 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3103 fep->hwp + FEC_ADDR_HIGH);
3107 #ifdef CONFIG_NET_POLL_CONTROLLER
3109 * fec_poll_controller - FEC Poll controller function
3110 * @dev: The FEC network adapter
3112 * Polled functionality used by netconsole and others in non interrupt mode
3115 static void fec_poll_controller(struct net_device *dev)
3118 struct fec_enet_private *fep = netdev_priv(dev);
3120 for (i = 0; i < FEC_IRQ_NUM; i++) {
3121 if (fep->irq[i] > 0) {
3122 disable_irq(fep->irq[i]);
3123 fec_enet_interrupt(fep->irq[i], dev);
3124 enable_irq(fep->irq[i]);
3130 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3131 netdev_features_t features)
3133 struct fec_enet_private *fep = netdev_priv(netdev);
3134 netdev_features_t changed = features ^ netdev->features;
3136 netdev->features = features;
3138 /* Receive checksum has been changed */
3139 if (changed & NETIF_F_RXCSUM) {
3140 if (features & NETIF_F_RXCSUM)
3141 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3143 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3147 static int fec_set_features(struct net_device *netdev,
3148 netdev_features_t features)
3150 struct fec_enet_private *fep = netdev_priv(netdev);
3151 netdev_features_t changed = features ^ netdev->features;
3153 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3154 napi_disable(&fep->napi);
3155 netif_tx_lock_bh(netdev);
3157 fec_enet_set_netdev_features(netdev, features);
3158 fec_restart(netdev);
3159 netif_tx_wake_all_queues(netdev);
3160 netif_tx_unlock_bh(netdev);
3161 napi_enable(&fep->napi);
3163 fec_enet_set_netdev_features(netdev, features);
3169 static const struct net_device_ops fec_netdev_ops = {
3170 .ndo_open = fec_enet_open,
3171 .ndo_stop = fec_enet_close,
3172 .ndo_start_xmit = fec_enet_start_xmit,
3173 .ndo_set_rx_mode = set_multicast_list,
3174 .ndo_validate_addr = eth_validate_addr,
3175 .ndo_tx_timeout = fec_timeout,
3176 .ndo_set_mac_address = fec_set_mac_address,
3177 .ndo_do_ioctl = fec_enet_ioctl,
3178 #ifdef CONFIG_NET_POLL_CONTROLLER
3179 .ndo_poll_controller = fec_poll_controller,
3181 .ndo_set_features = fec_set_features,
3184 static const unsigned short offset_des_active_rxq[] = {
3185 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3188 static const unsigned short offset_des_active_txq[] = {
3189 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3193 * XXX: We need to clean up on failure exits here.
3196 static int fec_enet_init(struct net_device *ndev)
3198 struct fec_enet_private *fep = netdev_priv(ndev);
3199 struct bufdesc *cbd_base;
3203 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3204 sizeof(struct bufdesc);
3205 unsigned dsize_log2 = __fls(dsize);
3208 WARN_ON(dsize != (1 << dsize_log2));
3209 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
3210 fep->rx_align = 0xf;
3211 fep->tx_align = 0xf;
3213 fep->rx_align = 0x3;
3214 fep->tx_align = 0x3;
3217 /* Check mask of the streaming and coherent API */
3218 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
3220 dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
3224 ret = fec_enet_alloc_queue(ndev);
3228 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3230 /* Allocate memory for buffer descriptors. */
3231 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3235 goto free_queue_mem;
3238 memset(cbd_base, 0, bd_size);
3240 /* Get the Ethernet address */
3242 /* make sure MAC we just acquired is programmed into the hw */
3243 fec_set_mac_address(ndev, NULL);
3245 /* Set receive and transmit descriptor base. */
3246 for (i = 0; i < fep->num_rx_queues; i++) {
3247 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3248 unsigned size = dsize * rxq->bd.ring_size;
3251 rxq->bd.base = cbd_base;
3252 rxq->bd.cur = cbd_base;
3253 rxq->bd.dma = bd_dma;
3254 rxq->bd.dsize = dsize;
3255 rxq->bd.dsize_log2 = dsize_log2;
3256 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3258 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3259 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3262 for (i = 0; i < fep->num_tx_queues; i++) {
3263 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3264 unsigned size = dsize * txq->bd.ring_size;
3267 txq->bd.base = cbd_base;
3268 txq->bd.cur = cbd_base;
3269 txq->bd.dma = bd_dma;
3270 txq->bd.dsize = dsize;
3271 txq->bd.dsize_log2 = dsize_log2;
3272 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3274 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3275 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3279 /* The FEC Ethernet specific entries in the device structure */
3280 ndev->watchdog_timeo = TX_TIMEOUT;
3281 ndev->netdev_ops = &fec_netdev_ops;
3282 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3284 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3285 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3287 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3288 /* enable hw VLAN support */
3289 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3291 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3292 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3294 /* enable hw accelerator */
3295 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3296 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3297 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3300 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3302 fep->rx_align = 0x3f;
3305 ndev->hw_features = ndev->features;
3309 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3310 fec_enet_clear_ethtool_stats(ndev);
3312 fec_enet_update_ethtool_stats(ndev);
3317 fec_enet_free_queue(ndev);
3322 static int fec_reset_phy(struct platform_device *pdev)
3325 bool active_high = false;
3326 int msec = 1, phy_post_delay = 0;
3327 struct device_node *np = pdev->dev.of_node;
3332 err = of_property_read_u32(np, "phy-reset-duration", &msec);
3333 /* A sane reset duration should not be longer than 1s */
3334 if (!err && msec > 1000)
3337 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3338 if (phy_reset == -EPROBE_DEFER)
3340 else if (!gpio_is_valid(phy_reset))
3343 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
3344 /* valid reset duration should be less than 1s */
3345 if (!err && phy_post_delay > 1000)
3348 active_high = of_property_read_bool(np, "phy-reset-active-high");
3350 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3351 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3354 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3361 usleep_range(msec * 1000, msec * 1000 + 1000);
3363 gpio_set_value_cansleep(phy_reset, !active_high);
3365 if (!phy_post_delay)
3368 if (phy_post_delay > 20)
3369 msleep(phy_post_delay);
3371 usleep_range(phy_post_delay * 1000,
3372 phy_post_delay * 1000 + 1000);
3376 #else /* CONFIG_OF */
3377 static int fec_reset_phy(struct platform_device *pdev)
3380 * In case of platform probe, the reset has been done
3385 #endif /* CONFIG_OF */
3388 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3390 struct device_node *np = pdev->dev.of_node;
3392 *num_tx = *num_rx = 1;
3394 if (!np || !of_device_is_available(np))
3397 /* parse the num of tx and rx queues */
3398 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3400 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3402 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3403 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3409 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3410 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3418 static int fec_enet_get_irq_cnt(struct platform_device *pdev)
3420 int irq_cnt = platform_irq_count(pdev);
3422 if (irq_cnt > FEC_IRQ_NUM)
3423 irq_cnt = FEC_IRQ_NUM; /* last for pps */
3424 else if (irq_cnt == 2)
3425 irq_cnt = 1; /* last for pps */
3426 else if (irq_cnt <= 0)
3427 irq_cnt = 1; /* At least 1 irq is needed */
3431 static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
3432 struct fec_devinfo *dev_info,
3433 struct device_node *np)
3435 struct device_node *gpr_np;
3441 gpr_np = of_parse_phandle(np, "gpr", 0);
3445 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);
3446 if (IS_ERR(fep->stop_gpr.gpr)) {
3447 dev_err(&fep->pdev->dev, "could not find gpr regmap\n");
3448 ret = PTR_ERR(fep->stop_gpr.gpr);
3449 fep->stop_gpr.gpr = NULL;
3453 fep->stop_gpr.reg = dev_info->stop_gpr_reg;
3454 fep->stop_gpr.bit = dev_info->stop_gpr_bit;
3457 of_node_put(gpr_np);
3463 fec_probe(struct platform_device *pdev)
3465 struct fec_enet_private *fep;
3466 struct fec_platform_data *pdata;
3467 struct net_device *ndev;
3468 int i, irq, ret = 0;
3470 const struct of_device_id *of_id;
3472 struct device_node *np = pdev->dev.of_node, *phy_node;
3477 struct fec_devinfo *dev_info;
3479 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3481 /* Init network device */
3482 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
3483 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
3487 SET_NETDEV_DEV(ndev, &pdev->dev);
3489 /* setup board info structure */
3490 fep = netdev_priv(ndev);
3492 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3494 pdev->id_entry = of_id->data;
3495 dev_info = (struct fec_devinfo *)pdev->id_entry->driver_data;
3497 fep->quirks = dev_info->quirks;
3500 fep->num_rx_queues = num_rx_qs;
3501 fep->num_tx_queues = num_tx_qs;
3503 #if !defined(CONFIG_M5272)
3504 /* default enable pause frame auto negotiation */
3505 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3506 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3509 /* Select default pin state */
3510 pinctrl_pm_select_default_state(&pdev->dev);
3512 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3513 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3514 if (IS_ERR(fep->hwp)) {
3515 ret = PTR_ERR(fep->hwp);
3516 goto failed_ioremap;
3520 fep->dev_id = dev_id++;
3522 platform_set_drvdata(pdev, ndev);
3524 if ((of_machine_is_compatible("fsl,imx6q") ||
3525 of_machine_is_compatible("fsl,imx6dl")) &&
3526 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3527 fep->quirks |= FEC_QUIRK_ERR006687;
3529 if (of_get_property(np, "fsl,magic-packet", NULL))
3530 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3532 ret = fec_enet_init_stop_mode(fep, dev_info, np);
3534 goto failed_stop_mode;
3536 phy_node = of_parse_phandle(np, "phy-handle", 0);
3537 if (!phy_node && of_phy_is_fixed_link(np)) {
3538 ret = of_phy_register_fixed_link(np);
3541 "broken fixed-link specification\n");
3544 phy_node = of_node_get(np);
3546 fep->phy_node = phy_node;
3548 ret = of_get_phy_mode(pdev->dev.of_node);
3550 pdata = dev_get_platdata(&pdev->dev);
3552 fep->phy_interface = pdata->phy;
3554 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3556 fep->phy_interface = ret;
3559 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3560 if (IS_ERR(fep->clk_ipg)) {
3561 ret = PTR_ERR(fep->clk_ipg);
3565 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3566 if (IS_ERR(fep->clk_ahb)) {
3567 ret = PTR_ERR(fep->clk_ahb);
3571 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3573 /* enet_out is optional, depends on board */
3574 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3575 if (IS_ERR(fep->clk_enet_out))
3576 fep->clk_enet_out = NULL;
3578 fep->ptp_clk_on = false;
3579 mutex_init(&fep->ptp_clk_mutex);
3581 /* clk_ref is optional, depends on board */
3582 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3583 if (IS_ERR(fep->clk_ref))
3584 fep->clk_ref = NULL;
3586 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3587 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3588 if (IS_ERR(fep->clk_ptp)) {
3589 fep->clk_ptp = NULL;
3590 fep->bufdesc_ex = false;
3593 ret = fec_enet_clk_enable(ndev, true);
3597 ret = clk_prepare_enable(fep->clk_ipg);
3599 goto failed_clk_ipg;
3600 ret = clk_prepare_enable(fep->clk_ahb);
3602 goto failed_clk_ahb;
3604 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3605 if (!IS_ERR(fep->reg_phy)) {
3606 ret = regulator_enable(fep->reg_phy);
3609 "Failed to enable phy regulator: %d\n", ret);
3610 clk_disable_unprepare(fep->clk_ipg);
3611 goto failed_regulator;
3614 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
3615 ret = -EPROBE_DEFER;
3616 goto failed_regulator;
3618 fep->reg_phy = NULL;
3621 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3622 pm_runtime_use_autosuspend(&pdev->dev);
3623 pm_runtime_get_noresume(&pdev->dev);
3624 pm_runtime_set_active(&pdev->dev);
3625 pm_runtime_enable(&pdev->dev);
3627 ret = fec_reset_phy(pdev);
3631 irq_cnt = fec_enet_get_irq_cnt(pdev);
3632 if (fep->bufdesc_ex)
3633 fec_ptp_init(pdev, irq_cnt);
3635 ret = fec_enet_init(ndev);
3639 for (i = 0; i < irq_cnt; i++) {
3640 snprintf(irq_name, sizeof(irq_name), "int%d", i);
3641 irq = platform_get_irq_byname(pdev, irq_name);
3643 irq = platform_get_irq(pdev, i);
3648 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3649 0, pdev->name, ndev);
3656 init_completion(&fep->mdio_done);
3657 ret = fec_enet_mii_init(pdev);
3659 goto failed_mii_init;
3661 /* Carrier starts down, phylib will bring it up */
3662 netif_carrier_off(ndev);
3663 fec_enet_clk_enable(ndev, false);
3664 pinctrl_pm_select_sleep_state(&pdev->dev);
3666 ret = register_netdev(ndev);
3668 goto failed_register;
3670 device_init_wakeup(&ndev->dev, fep->wol_flag &
3671 FEC_WOL_HAS_MAGIC_PACKET);
3673 if (fep->bufdesc_ex && fep->ptp_clock)
3674 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3676 fep->rx_copybreak = COPYBREAK_DEFAULT;
3677 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3679 pm_runtime_mark_last_busy(&pdev->dev);
3680 pm_runtime_put_autosuspend(&pdev->dev);
3685 fec_enet_mii_remove(fep);
3691 pm_runtime_put_noidle(&pdev->dev);
3692 pm_runtime_disable(&pdev->dev);
3694 regulator_disable(fep->reg_phy);
3696 clk_disable_unprepare(fep->clk_ahb);
3698 clk_disable_unprepare(fep->clk_ipg);
3700 fec_enet_clk_enable(ndev, false);
3702 if (of_phy_is_fixed_link(np))
3703 of_phy_deregister_fixed_link(np);
3704 of_node_put(phy_node);
3715 fec_drv_remove(struct platform_device *pdev)
3717 struct net_device *ndev = platform_get_drvdata(pdev);
3718 struct fec_enet_private *fep = netdev_priv(ndev);
3719 struct device_node *np = pdev->dev.of_node;
3722 ret = pm_runtime_get_sync(&pdev->dev);
3726 cancel_work_sync(&fep->tx_timeout_work);
3728 unregister_netdev(ndev);
3729 fec_enet_mii_remove(fep);
3731 regulator_disable(fep->reg_phy);
3733 if (of_phy_is_fixed_link(np))
3734 of_phy_deregister_fixed_link(np);
3735 of_node_put(fep->phy_node);
3737 clk_disable_unprepare(fep->clk_ahb);
3738 clk_disable_unprepare(fep->clk_ipg);
3739 pm_runtime_put_noidle(&pdev->dev);
3740 pm_runtime_disable(&pdev->dev);
3746 static int __maybe_unused fec_suspend(struct device *dev)
3748 struct net_device *ndev = dev_get_drvdata(dev);
3749 struct fec_enet_private *fep = netdev_priv(ndev);
3752 if (netif_running(ndev)) {
3753 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3754 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3755 phy_stop(ndev->phydev);
3756 napi_disable(&fep->napi);
3757 netif_tx_lock_bh(ndev);
3758 netif_device_detach(ndev);
3759 netif_tx_unlock_bh(ndev);
3761 fec_enet_clk_enable(ndev, false);
3762 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3763 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3767 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3768 regulator_disable(fep->reg_phy);
3770 /* SOC supply clock to phy, when clock is disabled, phy link down
3771 * SOC control phy regulator, when regulator is disabled, phy link down
3773 if (fep->clk_enet_out || fep->reg_phy)
3779 static int __maybe_unused fec_resume(struct device *dev)
3781 struct net_device *ndev = dev_get_drvdata(dev);
3782 struct fec_enet_private *fep = netdev_priv(ndev);
3786 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3787 ret = regulator_enable(fep->reg_phy);
3793 if (netif_running(ndev)) {
3794 ret = fec_enet_clk_enable(ndev, true);
3799 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3800 fec_enet_stop_mode(fep, false);
3802 val = readl(fep->hwp + FEC_ECNTRL);
3803 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3804 writel(val, fep->hwp + FEC_ECNTRL);
3805 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3807 pinctrl_pm_select_default_state(&fep->pdev->dev);
3810 netif_tx_lock_bh(ndev);
3811 netif_device_attach(ndev);
3812 netif_tx_unlock_bh(ndev);
3813 napi_enable(&fep->napi);
3814 phy_start(ndev->phydev);
3822 regulator_disable(fep->reg_phy);
3826 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3828 struct net_device *ndev = dev_get_drvdata(dev);
3829 struct fec_enet_private *fep = netdev_priv(ndev);
3831 clk_disable_unprepare(fep->clk_ahb);
3832 clk_disable_unprepare(fep->clk_ipg);
3837 static int __maybe_unused fec_runtime_resume(struct device *dev)
3839 struct net_device *ndev = dev_get_drvdata(dev);
3840 struct fec_enet_private *fep = netdev_priv(ndev);
3843 ret = clk_prepare_enable(fep->clk_ahb);
3846 ret = clk_prepare_enable(fep->clk_ipg);
3848 goto failed_clk_ipg;
3853 clk_disable_unprepare(fep->clk_ahb);
3857 static const struct dev_pm_ops fec_pm_ops = {
3858 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3859 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3862 static struct platform_driver fec_driver = {
3864 .name = DRIVER_NAME,
3866 .of_match_table = fec_dt_ids,
3868 .id_table = fec_devtype,
3870 .remove = fec_drv_remove,
3873 module_platform_driver(fec_driver);
3875 MODULE_ALIAS("platform:"DRIVER_NAME);
3876 MODULE_LICENSE("GPL");