1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Faraday FTGMAC100 Gigabit Ethernet
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/etherdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/netdevice.h>
20 #include <linux/of_mdio.h>
21 #include <linux/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/property.h>
24 #include <linux/crc32.h>
25 #include <linux/if_vlan.h>
26 #include <linux/of_net.h>
30 #include "ftgmac100.h"
32 #define DRV_NAME "ftgmac100"
34 /* Arbitrary values, I am not sure the HW has limits */
35 #define MAX_RX_QUEUE_ENTRIES 1024
36 #define MAX_TX_QUEUE_ENTRIES 1024
37 #define MIN_RX_QUEUE_ENTRIES 32
38 #define MIN_TX_QUEUE_ENTRIES 32
41 #define DEF_RX_QUEUE_ENTRIES 128
42 #define DEF_TX_QUEUE_ENTRIES 128
44 #define MAX_PKT_SIZE 1536
45 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */
47 /* Min number of tx ring entries before stopping queue */
48 #define TX_THRESHOLD (MAX_SKB_FRAGS + 1)
50 #define FTGMAC_100MHZ 100000000
51 #define FTGMAC_25MHZ 25000000
59 unsigned int rx_q_entries;
60 struct ftgmac100_rxdes *rxdes;
62 struct sk_buff **rx_skbs;
63 unsigned int rx_pointer;
64 u32 rxdes0_edorr_mask;
67 unsigned int tx_q_entries;
68 struct ftgmac100_txdes *txdes;
70 struct sk_buff **tx_skbs;
71 unsigned int tx_clean_pointer;
72 unsigned int tx_pointer;
73 u32 txdes0_edotr_mask;
75 /* Used to signal the reset task of ring change request */
76 unsigned int new_rx_q_entries;
77 unsigned int new_tx_q_entries;
79 /* Scratch page to use when rx skb alloc fails */
81 dma_addr_t rx_scratch_dma;
83 /* Component structures */
84 struct net_device *netdev;
86 struct ncsi_dev *ndev;
87 struct napi_struct napi;
88 struct work_struct reset_task;
89 struct mii_bus *mii_bus;
92 /* AST2500/AST2600 RMII ref clock gate */
100 /* Multicast filter settings */
104 /* Flow control settings */
110 bool need_mac_restart;
114 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
116 struct net_device *netdev = priv->netdev;
119 /* NOTE: reset clears all registers */
120 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
121 iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
122 priv->base + FTGMAC100_OFFSET_MACCR);
123 for (i = 0; i < 200; i++) {
126 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
127 if (!(maccr & FTGMAC100_MACCR_SW_RST))
133 netdev_err(netdev, "Hardware reset failed\n");
137 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
141 switch (priv->cur_speed) {
143 case 0: /* no link */
147 maccr |= FTGMAC100_MACCR_FAST_MODE;
151 maccr |= FTGMAC100_MACCR_GIGA_MODE;
154 netdev_err(priv->netdev, "Unknown speed %d !\n",
159 /* (Re)initialize the queue pointers */
160 priv->rx_pointer = 0;
161 priv->tx_clean_pointer = 0;
162 priv->tx_pointer = 0;
164 /* The doc says reset twice with 10us interval */
165 if (ftgmac100_reset_mac(priv, maccr))
167 usleep_range(10, 1000);
168 return ftgmac100_reset_mac(priv, maccr);
171 static void ftgmac100_write_mac_addr(struct ftgmac100 *priv, const u8 *mac)
173 unsigned int maddr = mac[0] << 8 | mac[1];
174 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
176 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
177 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
180 static void ftgmac100_initial_mac(struct ftgmac100 *priv)
187 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN);
189 ether_addr_copy(priv->netdev->dev_addr, mac);
190 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
195 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
196 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
198 mac[0] = (m >> 8) & 0xff;
200 mac[2] = (l >> 24) & 0xff;
201 mac[3] = (l >> 16) & 0xff;
202 mac[4] = (l >> 8) & 0xff;
205 if (is_valid_ether_addr(mac)) {
206 ether_addr_copy(priv->netdev->dev_addr, mac);
207 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
209 eth_hw_addr_random(priv->netdev);
210 dev_info(priv->dev, "Generated random MAC address %pM\n",
211 priv->netdev->dev_addr);
215 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
219 ret = eth_prepare_mac_addr_change(dev, p);
223 eth_commit_mac_addr_change(dev, p);
224 ftgmac100_write_mac_addr(netdev_priv(dev), dev->dev_addr);
229 static void ftgmac100_config_pause(struct ftgmac100 *priv)
231 u32 fcr = FTGMAC100_FCR_PAUSE_TIME(16);
233 /* Throttle tx queue when receiving pause frames */
235 fcr |= FTGMAC100_FCR_FC_EN;
237 /* Enables sending pause frames when the RX queue is past a
241 fcr |= FTGMAC100_FCR_FCTHR_EN;
243 iowrite32(fcr, priv->base + FTGMAC100_OFFSET_FCR);
246 static void ftgmac100_init_hw(struct ftgmac100 *priv)
248 u32 reg, rfifo_sz, tfifo_sz;
250 /* Clear stale interrupts */
251 reg = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
252 iowrite32(reg, priv->base + FTGMAC100_OFFSET_ISR);
254 /* Setup RX ring buffer base */
255 iowrite32(priv->rxdes_dma, priv->base + FTGMAC100_OFFSET_RXR_BADR);
257 /* Setup TX ring buffer base */
258 iowrite32(priv->txdes_dma, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
260 /* Configure RX buffer size */
261 iowrite32(FTGMAC100_RBSR_SIZE(RX_BUF_SIZE),
262 priv->base + FTGMAC100_OFFSET_RBSR);
264 /* Set RX descriptor autopoll */
265 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1),
266 priv->base + FTGMAC100_OFFSET_APTC);
268 /* Write MAC address */
269 ftgmac100_write_mac_addr(priv, priv->netdev->dev_addr);
271 /* Write multicast filter */
272 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
273 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
275 /* Configure descriptor sizes and increase burst sizes according
276 * to values in Aspeed SDK. The FIFO arbitration is enabled and
277 * the thresholds set based on the recommended values in the
278 * AST2400 specification.
280 iowrite32(FTGMAC100_DBLAC_RXDES_SIZE(2) | /* 2*8 bytes RX descs */
281 FTGMAC100_DBLAC_TXDES_SIZE(2) | /* 2*8 bytes TX descs */
282 FTGMAC100_DBLAC_RXBURST_SIZE(3) | /* 512 bytes max RX bursts */
283 FTGMAC100_DBLAC_TXBURST_SIZE(3) | /* 512 bytes max TX bursts */
284 FTGMAC100_DBLAC_RX_THR_EN | /* Enable fifo threshold arb */
285 FTGMAC100_DBLAC_RXFIFO_HTHR(6) | /* 6/8 of FIFO high threshold */
286 FTGMAC100_DBLAC_RXFIFO_LTHR(2), /* 2/8 of FIFO low threshold */
287 priv->base + FTGMAC100_OFFSET_DBLAC);
289 /* Interrupt mitigation configured for 1 interrupt/packet. HW interrupt
290 * mitigation doesn't seem to provide any benefit with NAPI so leave
293 iowrite32(FTGMAC100_ITC_RXINT_THR(1) |
294 FTGMAC100_ITC_TXINT_THR(1),
295 priv->base + FTGMAC100_OFFSET_ITC);
297 /* Configure FIFO sizes in the TPAFCR register */
298 reg = ioread32(priv->base + FTGMAC100_OFFSET_FEAR);
299 rfifo_sz = reg & 0x00000007;
300 tfifo_sz = (reg >> 3) & 0x00000007;
301 reg = ioread32(priv->base + FTGMAC100_OFFSET_TPAFCR);
303 reg |= (tfifo_sz << 27);
304 reg |= (rfifo_sz << 24);
305 iowrite32(reg, priv->base + FTGMAC100_OFFSET_TPAFCR);
308 static void ftgmac100_start_hw(struct ftgmac100 *priv)
310 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
312 /* Keep the original GMAC and FAST bits */
313 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
315 /* Add all the main enable bits */
316 maccr |= FTGMAC100_MACCR_TXDMA_EN |
317 FTGMAC100_MACCR_RXDMA_EN |
318 FTGMAC100_MACCR_TXMAC_EN |
319 FTGMAC100_MACCR_RXMAC_EN |
320 FTGMAC100_MACCR_CRC_APD |
321 FTGMAC100_MACCR_PHY_LINK_LEVEL |
322 FTGMAC100_MACCR_RX_RUNT |
323 FTGMAC100_MACCR_RX_BROADPKT;
325 /* Add other bits as needed */
326 if (priv->cur_duplex == DUPLEX_FULL)
327 maccr |= FTGMAC100_MACCR_FULLDUP;
328 if (priv->netdev->flags & IFF_PROMISC)
329 maccr |= FTGMAC100_MACCR_RX_ALL;
330 if (priv->netdev->flags & IFF_ALLMULTI)
331 maccr |= FTGMAC100_MACCR_RX_MULTIPKT;
332 else if (netdev_mc_count(priv->netdev))
333 maccr |= FTGMAC100_MACCR_HT_MULTI_EN;
335 /* Vlan filtering enabled */
336 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
337 maccr |= FTGMAC100_MACCR_RM_VLAN;
340 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
343 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
345 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
348 static void ftgmac100_calc_mc_hash(struct ftgmac100 *priv)
350 struct netdev_hw_addr *ha;
354 netdev_for_each_mc_addr(ha, priv->netdev) {
355 u32 crc_val = ether_crc_le(ETH_ALEN, ha->addr);
357 crc_val = (~(crc_val >> 2)) & 0x3f;
359 priv->maht1 |= 1ul << (crc_val - 32);
361 priv->maht0 |= 1ul << (crc_val);
365 static void ftgmac100_set_rx_mode(struct net_device *netdev)
367 struct ftgmac100 *priv = netdev_priv(netdev);
369 /* Setup the hash filter */
370 ftgmac100_calc_mc_hash(priv);
372 /* Interface down ? that's all there is to do */
373 if (!netif_running(netdev))
377 iowrite32(priv->maht0, priv->base + FTGMAC100_OFFSET_MAHT0);
378 iowrite32(priv->maht1, priv->base + FTGMAC100_OFFSET_MAHT1);
380 /* Reconfigure MACCR */
381 ftgmac100_start_hw(priv);
384 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
385 struct ftgmac100_rxdes *rxdes, gfp_t gfp)
387 struct net_device *netdev = priv->netdev;
392 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
393 if (unlikely(!skb)) {
395 netdev_warn(netdev, "failed to allocate rx skb\n");
397 map = priv->rx_scratch_dma;
399 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
401 if (unlikely(dma_mapping_error(priv->dev, map))) {
403 netdev_err(netdev, "failed to map rx page\n");
404 dev_kfree_skb_any(skb);
405 map = priv->rx_scratch_dma;
412 priv->rx_skbs[entry] = skb;
414 /* Store DMA address into RX desc */
415 rxdes->rxdes3 = cpu_to_le32(map);
417 /* Ensure the above is ordered vs clearing the OWN bit */
420 /* Clean status (which resets own bit) */
421 if (entry == (priv->rx_q_entries - 1))
422 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
429 static unsigned int ftgmac100_next_rx_pointer(struct ftgmac100 *priv,
430 unsigned int pointer)
432 return (pointer + 1) & (priv->rx_q_entries - 1);
435 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
437 struct net_device *netdev = priv->netdev;
439 if (status & FTGMAC100_RXDES0_RX_ERR)
440 netdev->stats.rx_errors++;
442 if (status & FTGMAC100_RXDES0_CRC_ERR)
443 netdev->stats.rx_crc_errors++;
445 if (status & (FTGMAC100_RXDES0_FTL |
446 FTGMAC100_RXDES0_RUNT |
447 FTGMAC100_RXDES0_RX_ODD_NB))
448 netdev->stats.rx_length_errors++;
451 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
453 struct net_device *netdev = priv->netdev;
454 struct ftgmac100_rxdes *rxdes;
456 unsigned int pointer, size;
457 u32 status, csum_vlan;
460 /* Grab next RX descriptor */
461 pointer = priv->rx_pointer;
462 rxdes = &priv->rxdes[pointer];
464 /* Grab descriptor status */
465 status = le32_to_cpu(rxdes->rxdes0);
467 /* Do we have a packet ? */
468 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
471 /* Order subsequent reads with the test for the ready bit */
474 /* We don't cope with fragmented RX packets */
475 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
476 !(status & FTGMAC100_RXDES0_LRS)))
479 /* Grab received size and csum vlan field in the descriptor */
480 size = status & FTGMAC100_RXDES0_VDBC;
481 csum_vlan = le32_to_cpu(rxdes->rxdes1);
483 /* Any error (other than csum offload) flagged ? */
484 if (unlikely(status & RXDES0_ANY_ERROR)) {
485 /* Correct for incorrect flagging of runt packets
486 * with vlan tags... Just accept a runt packet that
487 * has been flagged as vlan and whose size is at
490 if ((status & FTGMAC100_RXDES0_RUNT) &&
491 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
493 status &= ~FTGMAC100_RXDES0_RUNT;
495 /* Any error still in there ? */
496 if (status & RXDES0_ANY_ERROR) {
497 ftgmac100_rx_packet_error(priv, status);
502 /* If the packet had no skb (failed to allocate earlier)
503 * then try to allocate one and skip
505 skb = priv->rx_skbs[pointer];
506 if (!unlikely(skb)) {
507 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
511 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
512 netdev->stats.multicast++;
514 /* If the HW found checksum errors, bounce it to software.
516 * If we didn't, we need to see if the packet was recognized
517 * by HW as one of the supported checksummed protocols before
518 * we accept the HW test results.
520 if (netdev->features & NETIF_F_RXCSUM) {
521 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
522 FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
523 FTGMAC100_RXDES1_IP_CHKSUM_ERR;
524 if ((csum_vlan & err_bits) ||
525 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
526 skb->ip_summed = CHECKSUM_NONE;
528 skb->ip_summed = CHECKSUM_UNNECESSARY;
531 /* Transfer received size to skb */
534 /* Extract vlan tag */
535 if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
536 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL))
537 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
540 /* Tear down DMA mapping, do necessary cache management */
541 map = le32_to_cpu(rxdes->rxdes3);
543 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
544 /* When we don't have an iommu, we can save cycles by not
545 * invalidating the cache for the part of the packet that
548 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
550 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
554 /* Resplenish rx ring */
555 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
556 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
558 skb->protocol = eth_type_trans(skb, netdev);
560 netdev->stats.rx_packets++;
561 netdev->stats.rx_bytes += size;
563 /* push packet to protocol stack */
564 if (skb->ip_summed == CHECKSUM_NONE)
565 netif_receive_skb(skb);
567 napi_gro_receive(&priv->napi, skb);
573 /* Clean rxdes0 (which resets own bit) */
574 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
575 priv->rx_pointer = ftgmac100_next_rx_pointer(priv, pointer);
576 netdev->stats.rx_dropped++;
580 static u32 ftgmac100_base_tx_ctlstat(struct ftgmac100 *priv,
583 if (index == (priv->tx_q_entries - 1))
584 return priv->txdes0_edotr_mask;
589 static unsigned int ftgmac100_next_tx_pointer(struct ftgmac100 *priv,
590 unsigned int pointer)
592 return (pointer + 1) & (priv->tx_q_entries - 1);
595 static u32 ftgmac100_tx_buf_avail(struct ftgmac100 *priv)
597 /* Returns the number of available slots in the TX queue
599 * This always leaves one free slot so we don't have to
600 * worry about empty vs. full, and this simplifies the
601 * test for ftgmac100_tx_buf_cleanable() below
603 return (priv->tx_clean_pointer - priv->tx_pointer - 1) &
604 (priv->tx_q_entries - 1);
607 static bool ftgmac100_tx_buf_cleanable(struct ftgmac100 *priv)
609 return priv->tx_pointer != priv->tx_clean_pointer;
612 static void ftgmac100_free_tx_packet(struct ftgmac100 *priv,
613 unsigned int pointer,
615 struct ftgmac100_txdes *txdes,
618 dma_addr_t map = le32_to_cpu(txdes->txdes3);
621 if (ctl_stat & FTGMAC100_TXDES0_FTS) {
622 len = skb_headlen(skb);
623 dma_unmap_single(priv->dev, map, len, DMA_TO_DEVICE);
625 len = FTGMAC100_TXDES0_TXBUF_SIZE(ctl_stat);
626 dma_unmap_page(priv->dev, map, len, DMA_TO_DEVICE);
629 /* Free SKB on last segment */
630 if (ctl_stat & FTGMAC100_TXDES0_LTS)
632 priv->tx_skbs[pointer] = NULL;
635 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
637 struct net_device *netdev = priv->netdev;
638 struct ftgmac100_txdes *txdes;
640 unsigned int pointer;
643 pointer = priv->tx_clean_pointer;
644 txdes = &priv->txdes[pointer];
646 ctl_stat = le32_to_cpu(txdes->txdes0);
647 if (ctl_stat & FTGMAC100_TXDES0_TXDMA_OWN)
650 skb = priv->tx_skbs[pointer];
651 netdev->stats.tx_packets++;
652 netdev->stats.tx_bytes += skb->len;
653 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
654 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
656 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv, pointer);
661 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
663 struct net_device *netdev = priv->netdev;
665 /* Process all completed packets */
666 while (ftgmac100_tx_buf_cleanable(priv) &&
667 ftgmac100_tx_complete_packet(priv))
670 /* Restart queue if needed */
672 if (unlikely(netif_queue_stopped(netdev) &&
673 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)) {
674 struct netdev_queue *txq;
676 txq = netdev_get_tx_queue(netdev, 0);
677 __netif_tx_lock(txq, smp_processor_id());
678 if (netif_queue_stopped(netdev) &&
679 ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
680 netif_wake_queue(netdev);
681 __netif_tx_unlock(txq);
685 static bool ftgmac100_prep_tx_csum(struct sk_buff *skb, u32 *csum_vlan)
687 if (skb->protocol == cpu_to_be16(ETH_P_IP)) {
688 u8 ip_proto = ip_hdr(skb)->protocol;
690 *csum_vlan |= FTGMAC100_TXDES1_IP_CHKSUM;
693 *csum_vlan |= FTGMAC100_TXDES1_TCP_CHKSUM;
696 *csum_vlan |= FTGMAC100_TXDES1_UDP_CHKSUM;
702 return skb_checksum_help(skb) == 0;
705 static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb,
706 struct net_device *netdev)
708 struct ftgmac100 *priv = netdev_priv(netdev);
709 struct ftgmac100_txdes *txdes, *first;
710 unsigned int pointer, nfrags, len, i, j;
711 u32 f_ctl_stat, ctl_stat, csum_vlan;
714 /* The HW doesn't pad small frames */
715 if (eth_skb_pad(skb)) {
716 netdev->stats.tx_dropped++;
720 /* Reject oversize packets */
721 if (unlikely(skb->len > MAX_PKT_SIZE)) {
723 netdev_dbg(netdev, "tx packet too big\n");
727 /* Do we have a limit on #fragments ? I yet have to get a reply
728 * from Aspeed. If there's one I haven't hit it.
730 nfrags = skb_shinfo(skb)->nr_frags;
732 /* Setup HW checksumming */
734 if (skb->ip_summed == CHECKSUM_PARTIAL &&
735 !ftgmac100_prep_tx_csum(skb, &csum_vlan))
739 if (skb_vlan_tag_present(skb)) {
740 csum_vlan |= FTGMAC100_TXDES1_INS_VLANTAG;
741 csum_vlan |= skb_vlan_tag_get(skb) & 0xffff;
745 len = skb_headlen(skb);
747 /* Map the packet head */
748 map = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE);
749 if (dma_mapping_error(priv->dev, map)) {
751 netdev_err(netdev, "map tx packet head failed\n");
755 /* Grab the next free tx descriptor */
756 pointer = priv->tx_pointer;
757 txdes = first = &priv->txdes[pointer];
759 /* Setup it up with the packet head. Don't write the head to the
762 priv->tx_skbs[pointer] = skb;
763 f_ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
764 f_ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
765 f_ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
766 f_ctl_stat |= FTGMAC100_TXDES0_FTS;
768 f_ctl_stat |= FTGMAC100_TXDES0_LTS;
769 txdes->txdes3 = cpu_to_le32(map);
770 txdes->txdes1 = cpu_to_le32(csum_vlan);
772 /* Next descriptor */
773 pointer = ftgmac100_next_tx_pointer(priv, pointer);
775 /* Add the fragments */
776 for (i = 0; i < nfrags; i++) {
777 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
779 len = skb_frag_size(frag);
782 map = skb_frag_dma_map(priv->dev, frag, 0, len,
784 if (dma_mapping_error(priv->dev, map))
787 /* Setup descriptor */
788 priv->tx_skbs[pointer] = skb;
789 txdes = &priv->txdes[pointer];
790 ctl_stat = ftgmac100_base_tx_ctlstat(priv, pointer);
791 ctl_stat |= FTGMAC100_TXDES0_TXDMA_OWN;
792 ctl_stat |= FTGMAC100_TXDES0_TXBUF_SIZE(len);
793 if (i == (nfrags - 1))
794 ctl_stat |= FTGMAC100_TXDES0_LTS;
795 txdes->txdes0 = cpu_to_le32(ctl_stat);
797 txdes->txdes3 = cpu_to_le32(map);
800 pointer = ftgmac100_next_tx_pointer(priv, pointer);
803 /* Order the previous packet and descriptor udpates
804 * before setting the OWN bit on the first descriptor.
807 first->txdes0 = cpu_to_le32(f_ctl_stat);
809 /* Update next TX pointer */
810 priv->tx_pointer = pointer;
812 /* If there isn't enough room for all the fragments of a new packet
813 * in the TX ring, stop the queue. The sequence below is race free
814 * vs. a concurrent restart in ftgmac100_poll()
816 if (unlikely(ftgmac100_tx_buf_avail(priv) < TX_THRESHOLD)) {
817 netif_stop_queue(netdev);
818 /* Order the queue stop with the test below */
820 if (ftgmac100_tx_buf_avail(priv) >= TX_THRESHOLD)
821 netif_wake_queue(netdev);
824 /* Poke transmitter to read the updated TX descriptors */
825 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
831 netdev_err(netdev, "map tx fragment failed\n");
834 pointer = priv->tx_pointer;
835 ftgmac100_free_tx_packet(priv, pointer, skb, first, f_ctl_stat);
836 first->txdes0 = cpu_to_le32(f_ctl_stat & priv->txdes0_edotr_mask);
838 /* Then all fragments */
839 for (j = 0; j < i; j++) {
840 pointer = ftgmac100_next_tx_pointer(priv, pointer);
841 txdes = &priv->txdes[pointer];
842 ctl_stat = le32_to_cpu(txdes->txdes0);
843 ftgmac100_free_tx_packet(priv, pointer, skb, txdes, ctl_stat);
844 txdes->txdes0 = cpu_to_le32(ctl_stat & priv->txdes0_edotr_mask);
847 /* This cannot be reached if we successfully mapped the
848 * last fragment, so we know ftgmac100_free_tx_packet()
849 * hasn't freed the skb yet.
852 /* Drop the packet */
853 dev_kfree_skb_any(skb);
854 netdev->stats.tx_dropped++;
859 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
863 /* Free all RX buffers */
864 for (i = 0; i < priv->rx_q_entries; i++) {
865 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
866 struct sk_buff *skb = priv->rx_skbs[i];
867 dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
872 priv->rx_skbs[i] = NULL;
873 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
874 dev_kfree_skb_any(skb);
877 /* Free all TX buffers */
878 for (i = 0; i < priv->tx_q_entries; i++) {
879 struct ftgmac100_txdes *txdes = &priv->txdes[i];
880 struct sk_buff *skb = priv->tx_skbs[i];
884 ftgmac100_free_tx_packet(priv, i, skb, txdes,
885 le32_to_cpu(txdes->txdes0));
889 static void ftgmac100_free_rings(struct ftgmac100 *priv)
891 /* Free skb arrays */
892 kfree(priv->rx_skbs);
893 kfree(priv->tx_skbs);
895 /* Free descriptors */
897 dma_free_coherent(priv->dev, MAX_RX_QUEUE_ENTRIES *
898 sizeof(struct ftgmac100_rxdes),
899 priv->rxdes, priv->rxdes_dma);
903 dma_free_coherent(priv->dev, MAX_TX_QUEUE_ENTRIES *
904 sizeof(struct ftgmac100_txdes),
905 priv->txdes, priv->txdes_dma);
908 /* Free scratch packet buffer */
909 if (priv->rx_scratch)
910 dma_free_coherent(priv->dev, RX_BUF_SIZE,
911 priv->rx_scratch, priv->rx_scratch_dma);
914 static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
916 /* Allocate skb arrays */
917 priv->rx_skbs = kcalloc(MAX_RX_QUEUE_ENTRIES, sizeof(void *),
921 priv->tx_skbs = kcalloc(MAX_TX_QUEUE_ENTRIES, sizeof(void *),
926 /* Allocate descriptors */
927 priv->rxdes = dma_alloc_coherent(priv->dev,
928 MAX_RX_QUEUE_ENTRIES * sizeof(struct ftgmac100_rxdes),
929 &priv->rxdes_dma, GFP_KERNEL);
932 priv->txdes = dma_alloc_coherent(priv->dev,
933 MAX_TX_QUEUE_ENTRIES * sizeof(struct ftgmac100_txdes),
934 &priv->txdes_dma, GFP_KERNEL);
938 /* Allocate scratch packet buffer */
939 priv->rx_scratch = dma_alloc_coherent(priv->dev,
941 &priv->rx_scratch_dma,
943 if (!priv->rx_scratch)
949 static void ftgmac100_init_rings(struct ftgmac100 *priv)
951 struct ftgmac100_rxdes *rxdes = NULL;
952 struct ftgmac100_txdes *txdes = NULL;
955 /* Update entries counts */
956 priv->rx_q_entries = priv->new_rx_q_entries;
957 priv->tx_q_entries = priv->new_tx_q_entries;
959 if (WARN_ON(priv->rx_q_entries < MIN_RX_QUEUE_ENTRIES))
962 /* Initialize RX ring */
963 for (i = 0; i < priv->rx_q_entries; i++) {
964 rxdes = &priv->rxdes[i];
966 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
968 /* Mark the end of the ring */
969 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
971 if (WARN_ON(priv->tx_q_entries < MIN_RX_QUEUE_ENTRIES))
974 /* Initialize TX ring */
975 for (i = 0; i < priv->tx_q_entries; i++) {
976 txdes = &priv->txdes[i];
979 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
982 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
986 for (i = 0; i < priv->rx_q_entries; i++) {
987 struct ftgmac100_rxdes *rxdes = &priv->rxdes[i];
989 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
995 static void ftgmac100_adjust_link(struct net_device *netdev)
997 struct ftgmac100 *priv = netdev_priv(netdev);
998 struct phy_device *phydev = netdev->phydev;
999 bool tx_pause, rx_pause;
1002 /* We store "no link" as speed 0 */
1006 new_speed = phydev->speed;
1008 /* Grab pause settings from PHY if configured to do so */
1009 if (priv->aneg_pause) {
1010 rx_pause = tx_pause = phydev->pause;
1011 if (phydev->asym_pause)
1012 tx_pause = !rx_pause;
1014 rx_pause = priv->rx_pause;
1015 tx_pause = priv->tx_pause;
1018 /* Link hasn't changed, do nothing */
1019 if (phydev->speed == priv->cur_speed &&
1020 phydev->duplex == priv->cur_duplex &&
1021 rx_pause == priv->rx_pause &&
1022 tx_pause == priv->tx_pause)
1025 /* Print status if we have a link or we had one and just lost it,
1026 * don't print otherwise.
1028 if (new_speed || priv->cur_speed)
1029 phy_print_status(phydev);
1031 priv->cur_speed = new_speed;
1032 priv->cur_duplex = phydev->duplex;
1033 priv->rx_pause = rx_pause;
1034 priv->tx_pause = tx_pause;
1036 /* Link is down, do nothing else */
1040 /* Disable all interrupts */
1041 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1043 /* Reset the adapter asynchronously */
1044 schedule_work(&priv->reset_task);
1047 static int ftgmac100_mii_probe(struct ftgmac100 *priv, phy_interface_t intf)
1049 struct net_device *netdev = priv->netdev;
1050 struct phy_device *phydev;
1052 phydev = phy_find_first(priv->mii_bus);
1054 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
1058 phydev = phy_connect(netdev, phydev_name(phydev),
1059 &ftgmac100_adjust_link, intf);
1061 if (IS_ERR(phydev)) {
1062 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
1063 return PTR_ERR(phydev);
1066 /* Indicate that we support PAUSE frames (see comment in
1067 * Documentation/networking/phy.rst)
1069 phy_support_asym_pause(phydev);
1071 /* Display what we found */
1072 phy_attached_info(phydev);
1077 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1079 struct net_device *netdev = bus->priv;
1080 struct ftgmac100 *priv = netdev_priv(netdev);
1084 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1086 /* preserve MDC cycle threshold */
1087 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1089 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1090 FTGMAC100_PHYCR_REGAD(regnum) |
1091 FTGMAC100_PHYCR_MIIRD;
1093 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1095 for (i = 0; i < 10; i++) {
1096 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1098 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
1101 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
1102 return FTGMAC100_PHYDATA_MIIRDATA(data);
1108 netdev_err(netdev, "mdio read timed out\n");
1112 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
1113 int regnum, u16 value)
1115 struct net_device *netdev = bus->priv;
1116 struct ftgmac100 *priv = netdev_priv(netdev);
1121 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1123 /* preserve MDC cycle threshold */
1124 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1126 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1127 FTGMAC100_PHYCR_REGAD(regnum) |
1128 FTGMAC100_PHYCR_MIIWR;
1130 data = FTGMAC100_PHYDATA_MIIWDATA(value);
1132 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
1133 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1135 for (i = 0; i < 10; i++) {
1136 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1138 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
1144 netdev_err(netdev, "mdio write timed out\n");
1148 static void ftgmac100_get_drvinfo(struct net_device *netdev,
1149 struct ethtool_drvinfo *info)
1151 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1152 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
1155 static void ftgmac100_get_ringparam(struct net_device *netdev,
1156 struct ethtool_ringparam *ering)
1158 struct ftgmac100 *priv = netdev_priv(netdev);
1160 memset(ering, 0, sizeof(*ering));
1161 ering->rx_max_pending = MAX_RX_QUEUE_ENTRIES;
1162 ering->tx_max_pending = MAX_TX_QUEUE_ENTRIES;
1163 ering->rx_pending = priv->rx_q_entries;
1164 ering->tx_pending = priv->tx_q_entries;
1167 static int ftgmac100_set_ringparam(struct net_device *netdev,
1168 struct ethtool_ringparam *ering)
1170 struct ftgmac100 *priv = netdev_priv(netdev);
1172 if (ering->rx_pending > MAX_RX_QUEUE_ENTRIES ||
1173 ering->tx_pending > MAX_TX_QUEUE_ENTRIES ||
1174 ering->rx_pending < MIN_RX_QUEUE_ENTRIES ||
1175 ering->tx_pending < MIN_TX_QUEUE_ENTRIES ||
1176 !is_power_of_2(ering->rx_pending) ||
1177 !is_power_of_2(ering->tx_pending))
1180 priv->new_rx_q_entries = ering->rx_pending;
1181 priv->new_tx_q_entries = ering->tx_pending;
1182 if (netif_running(netdev))
1183 schedule_work(&priv->reset_task);
1188 static void ftgmac100_get_pauseparam(struct net_device *netdev,
1189 struct ethtool_pauseparam *pause)
1191 struct ftgmac100 *priv = netdev_priv(netdev);
1193 pause->autoneg = priv->aneg_pause;
1194 pause->tx_pause = priv->tx_pause;
1195 pause->rx_pause = priv->rx_pause;
1198 static int ftgmac100_set_pauseparam(struct net_device *netdev,
1199 struct ethtool_pauseparam *pause)
1201 struct ftgmac100 *priv = netdev_priv(netdev);
1202 struct phy_device *phydev = netdev->phydev;
1204 priv->aneg_pause = pause->autoneg;
1205 priv->tx_pause = pause->tx_pause;
1206 priv->rx_pause = pause->rx_pause;
1209 phy_set_asym_pause(phydev, pause->rx_pause, pause->tx_pause);
1211 if (netif_running(netdev)) {
1212 if (!(phydev && priv->aneg_pause))
1213 ftgmac100_config_pause(priv);
1219 static const struct ethtool_ops ftgmac100_ethtool_ops = {
1220 .get_drvinfo = ftgmac100_get_drvinfo,
1221 .get_link = ethtool_op_get_link,
1222 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1223 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1224 .nway_reset = phy_ethtool_nway_reset,
1225 .get_ringparam = ftgmac100_get_ringparam,
1226 .set_ringparam = ftgmac100_set_ringparam,
1227 .get_pauseparam = ftgmac100_get_pauseparam,
1228 .set_pauseparam = ftgmac100_set_pauseparam,
1231 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
1233 struct net_device *netdev = dev_id;
1234 struct ftgmac100 *priv = netdev_priv(netdev);
1235 unsigned int status, new_mask = FTGMAC100_INT_BAD;
1237 /* Fetch and clear interrupt bits, process abnormal ones */
1238 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1239 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1240 if (unlikely(status & FTGMAC100_INT_BAD)) {
1242 /* RX buffer unavailable */
1243 if (status & FTGMAC100_INT_NO_RXBUF)
1244 netdev->stats.rx_over_errors++;
1246 /* received packet lost due to RX FIFO full */
1247 if (status & FTGMAC100_INT_RPKT_LOST)
1248 netdev->stats.rx_fifo_errors++;
1250 /* sent packet lost due to excessive TX collision */
1251 if (status & FTGMAC100_INT_XPKT_LOST)
1252 netdev->stats.tx_fifo_errors++;
1254 /* AHB error -> Reset the chip */
1255 if (status & FTGMAC100_INT_AHB_ERR) {
1256 if (net_ratelimit())
1258 "AHB bus error ! Resetting chip.\n");
1259 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1260 schedule_work(&priv->reset_task);
1264 /* We may need to restart the MAC after such errors, delay
1265 * this until after we have freed some Rx buffers though
1267 priv->need_mac_restart = true;
1269 /* Disable those errors until we restart */
1270 new_mask &= ~status;
1273 /* Only enable "bad" interrupts while NAPI is on */
1274 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1276 /* Schedule NAPI bh */
1277 napi_schedule_irqoff(&priv->napi);
1282 static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1284 struct ftgmac100_rxdes *rxdes = &priv->rxdes[priv->rx_pointer];
1286 /* Do we have a packet ? */
1287 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1290 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1292 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1296 /* Handle TX completions */
1297 if (ftgmac100_tx_buf_cleanable(priv))
1298 ftgmac100_tx_complete(priv);
1300 /* Handle RX packets */
1302 more = ftgmac100_rx_packet(priv, &work_done);
1303 } while (more && work_done < budget);
1306 /* The interrupt is telling us to kick the MAC back to life
1307 * after an RX overflow
1309 if (unlikely(priv->need_mac_restart)) {
1310 ftgmac100_start_hw(priv);
1311 priv->need_mac_restart = false;
1313 /* Re-enable "bad" interrupts */
1314 iowrite32(FTGMAC100_INT_BAD,
1315 priv->base + FTGMAC100_OFFSET_IER);
1318 /* As long as we are waiting for transmit packets to be
1319 * completed we keep NAPI going
1321 if (ftgmac100_tx_buf_cleanable(priv))
1324 if (work_done < budget) {
1325 /* We are about to re-enable all interrupts. However
1326 * the HW has been latching RX/TX packet interrupts while
1327 * they were masked. So we clear them first, then we need
1328 * to re-check if there's something to process
1330 iowrite32(FTGMAC100_INT_RXTX,
1331 priv->base + FTGMAC100_OFFSET_ISR);
1333 /* Push the above (and provides a barrier vs. subsequent
1334 * reads of the descriptor).
1336 ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1338 /* Check RX and TX descriptors for more work to do */
1339 if (ftgmac100_check_rx(priv) ||
1340 ftgmac100_tx_buf_cleanable(priv))
1343 /* deschedule NAPI */
1344 napi_complete(napi);
1346 /* enable all interrupts */
1347 iowrite32(FTGMAC100_INT_ALL,
1348 priv->base + FTGMAC100_OFFSET_IER);
1354 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1358 /* Re-init descriptors (adjust queue sizes) */
1359 ftgmac100_init_rings(priv);
1361 /* Realloc rx descriptors */
1362 err = ftgmac100_alloc_rx_buffers(priv);
1363 if (err && !ignore_alloc_err)
1366 /* Reinit and restart HW */
1367 ftgmac100_init_hw(priv);
1368 ftgmac100_config_pause(priv);
1369 ftgmac100_start_hw(priv);
1371 /* Re-enable the device */
1372 napi_enable(&priv->napi);
1373 netif_start_queue(priv->netdev);
1375 /* Enable all interrupts */
1376 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1381 static void ftgmac100_reset_task(struct work_struct *work)
1383 struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1385 struct net_device *netdev = priv->netdev;
1388 netdev_dbg(netdev, "Resetting NIC...\n");
1390 /* Lock the world */
1393 mutex_lock(&netdev->phydev->lock);
1395 mutex_lock(&priv->mii_bus->mdio_lock);
1398 /* Check if the interface is still up */
1399 if (!netif_running(netdev))
1402 /* Stop the network stack */
1403 netif_trans_update(netdev);
1404 napi_disable(&priv->napi);
1405 netif_tx_disable(netdev);
1407 /* Stop and reset the MAC */
1408 ftgmac100_stop_hw(priv);
1409 err = ftgmac100_reset_and_config_mac(priv);
1411 /* Not much we can do ... it might come back... */
1412 netdev_err(netdev, "attempting to continue...\n");
1415 /* Free all rx and tx buffers */
1416 ftgmac100_free_buffers(priv);
1418 /* Setup everything again and restart chip */
1419 ftgmac100_init_all(priv, true);
1421 netdev_dbg(netdev, "Reset done !\n");
1424 mutex_unlock(&priv->mii_bus->mdio_lock);
1426 mutex_unlock(&netdev->phydev->lock);
1430 static int ftgmac100_open(struct net_device *netdev)
1432 struct ftgmac100 *priv = netdev_priv(netdev);
1435 /* Allocate ring buffers */
1436 err = ftgmac100_alloc_rings(priv);
1438 netdev_err(netdev, "Failed to allocate descriptors\n");
1442 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1444 * Otherwise we leave it set to 0 (no link), the link
1445 * message from the PHY layer will handle setting it up to
1446 * something else if needed.
1448 if (priv->use_ncsi) {
1449 priv->cur_duplex = DUPLEX_FULL;
1450 priv->cur_speed = SPEED_100;
1452 priv->cur_duplex = 0;
1453 priv->cur_speed = 0;
1456 /* Reset the hardware */
1457 err = ftgmac100_reset_and_config_mac(priv);
1461 /* Initialize NAPI */
1462 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1464 /* Grab our interrupt */
1465 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1467 netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1471 /* Start things up */
1472 err = ftgmac100_init_all(priv, false);
1474 netdev_err(netdev, "Failed to allocate packet buffers\n");
1478 if (netdev->phydev) {
1479 /* If we have a PHY, start polling */
1480 phy_start(netdev->phydev);
1481 } else if (priv->use_ncsi) {
1482 /* If using NC-SI, set our carrier on and start the stack */
1483 netif_carrier_on(netdev);
1485 /* Start the NCSI device */
1486 err = ncsi_start_dev(priv->ndev);
1494 napi_disable(&priv->napi);
1495 netif_stop_queue(netdev);
1497 ftgmac100_free_buffers(priv);
1498 free_irq(netdev->irq, netdev);
1500 netif_napi_del(&priv->napi);
1502 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1503 ftgmac100_free_rings(priv);
1507 static int ftgmac100_stop(struct net_device *netdev)
1509 struct ftgmac100 *priv = netdev_priv(netdev);
1511 /* Note about the reset task: We are called with the rtnl lock
1512 * held, so we are synchronized against the core of the reset
1513 * task. We must not try to synchronously cancel it otherwise
1514 * we can deadlock. But since it will test for netif_running()
1515 * which has already been cleared by the net core, we don't
1516 * anything special to do.
1519 /* disable all interrupts */
1520 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1522 netif_stop_queue(netdev);
1523 napi_disable(&priv->napi);
1524 netif_napi_del(&priv->napi);
1526 phy_stop(netdev->phydev);
1527 else if (priv->use_ncsi)
1528 ncsi_stop_dev(priv->ndev);
1530 ftgmac100_stop_hw(priv);
1531 free_irq(netdev->irq, netdev);
1532 ftgmac100_free_buffers(priv);
1533 ftgmac100_free_rings(priv);
1538 static void ftgmac100_tx_timeout(struct net_device *netdev, unsigned int txqueue)
1540 struct ftgmac100 *priv = netdev_priv(netdev);
1542 /* Disable all interrupts */
1543 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1545 /* Do the reset outside of interrupt context */
1546 schedule_work(&priv->reset_task);
1549 static int ftgmac100_set_features(struct net_device *netdev,
1550 netdev_features_t features)
1552 struct ftgmac100 *priv = netdev_priv(netdev);
1553 netdev_features_t changed = netdev->features ^ features;
1555 if (!netif_running(netdev))
1558 /* Update the vlan filtering bit */
1559 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
1562 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
1563 if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
1564 maccr |= FTGMAC100_MACCR_RM_VLAN;
1566 maccr &= ~FTGMAC100_MACCR_RM_VLAN;
1567 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
1573 #ifdef CONFIG_NET_POLL_CONTROLLER
1574 static void ftgmac100_poll_controller(struct net_device *netdev)
1576 unsigned long flags;
1578 local_irq_save(flags);
1579 ftgmac100_interrupt(netdev->irq, netdev);
1580 local_irq_restore(flags);
1584 static const struct net_device_ops ftgmac100_netdev_ops = {
1585 .ndo_open = ftgmac100_open,
1586 .ndo_stop = ftgmac100_stop,
1587 .ndo_start_xmit = ftgmac100_hard_start_xmit,
1588 .ndo_set_mac_address = ftgmac100_set_mac_addr,
1589 .ndo_validate_addr = eth_validate_addr,
1590 .ndo_do_ioctl = phy_do_ioctl,
1591 .ndo_tx_timeout = ftgmac100_tx_timeout,
1592 .ndo_set_rx_mode = ftgmac100_set_rx_mode,
1593 .ndo_set_features = ftgmac100_set_features,
1594 #ifdef CONFIG_NET_POLL_CONTROLLER
1595 .ndo_poll_controller = ftgmac100_poll_controller,
1597 .ndo_vlan_rx_add_vid = ncsi_vlan_rx_add_vid,
1598 .ndo_vlan_rx_kill_vid = ncsi_vlan_rx_kill_vid,
1601 static int ftgmac100_setup_mdio(struct net_device *netdev)
1603 struct ftgmac100 *priv = netdev_priv(netdev);
1604 struct platform_device *pdev = to_platform_device(priv->dev);
1605 phy_interface_t phy_intf = PHY_INTERFACE_MODE_RGMII;
1606 struct device_node *np = pdev->dev.of_node;
1610 /* initialize mdio bus */
1611 priv->mii_bus = mdiobus_alloc();
1615 if (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1616 of_device_is_compatible(np, "aspeed,ast2500-mac")) {
1617 /* The AST2600 has a separate MDIO controller */
1619 /* For the AST2400 and AST2500 this driver only supports the
1620 * old MDIO interface
1622 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1623 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1624 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1627 /* Get PHY mode from device-tree */
1629 /* Default to RGMII. It's a gigabit part after all */
1630 err = of_get_phy_mode(np, &phy_intf);
1632 phy_intf = PHY_INTERFACE_MODE_RGMII;
1634 /* Aspeed only supports these. I don't know about other IP
1635 * block vendors so I'm going to just let them through for
1636 * now. Note that this is only a warning if for some obscure
1637 * reason the DT really means to lie about it or it's a newer
1638 * part we don't know about.
1640 * On the Aspeed SoC there are additionally straps and SCU
1641 * control bits that could tell us what the interface is
1642 * (or allow us to configure it while the IP block is held
1643 * in reset). For now I chose to keep this driver away from
1644 * those SoC specific bits and assume the device-tree is
1645 * right and the SCU has been configured properly by pinmux
1648 if (priv->is_aspeed &&
1649 phy_intf != PHY_INTERFACE_MODE_RMII &&
1650 phy_intf != PHY_INTERFACE_MODE_RGMII &&
1651 phy_intf != PHY_INTERFACE_MODE_RGMII_ID &&
1652 phy_intf != PHY_INTERFACE_MODE_RGMII_RXID &&
1653 phy_intf != PHY_INTERFACE_MODE_RGMII_TXID) {
1655 "Unsupported PHY mode %s !\n",
1656 phy_modes(phy_intf));
1660 priv->mii_bus->name = "ftgmac100_mdio";
1661 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1662 pdev->name, pdev->id);
1663 priv->mii_bus->parent = priv->dev;
1664 priv->mii_bus->priv = priv->netdev;
1665 priv->mii_bus->read = ftgmac100_mdiobus_read;
1666 priv->mii_bus->write = ftgmac100_mdiobus_write;
1668 for (i = 0; i < PHY_MAX_ADDR; i++)
1669 priv->mii_bus->irq[i] = PHY_POLL;
1671 err = mdiobus_register(priv->mii_bus);
1673 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1674 goto err_register_mdiobus;
1677 err = ftgmac100_mii_probe(priv, phy_intf);
1679 dev_err(priv->dev, "MII Probe failed!\n");
1686 mdiobus_unregister(priv->mii_bus);
1687 err_register_mdiobus:
1688 mdiobus_free(priv->mii_bus);
1692 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1694 struct ftgmac100 *priv = netdev_priv(netdev);
1696 if (!netdev->phydev)
1699 phy_disconnect(netdev->phydev);
1700 mdiobus_unregister(priv->mii_bus);
1701 mdiobus_free(priv->mii_bus);
1704 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1706 if (unlikely(nd->state != ncsi_dev_state_functional))
1709 netdev_dbg(nd->dev, "NCSI interface %s\n",
1710 nd->link_up ? "up" : "down");
1713 static int ftgmac100_setup_clk(struct ftgmac100 *priv)
1718 clk = devm_clk_get(priv->dev, NULL /* MACCLK */);
1720 return PTR_ERR(clk);
1722 rc = clk_prepare_enable(priv->clk);
1726 /* Aspeed specifies a 100MHz clock is required for up to
1727 * 1000Mbit link speeds. As NCSI is limited to 100Mbit, 25MHz
1730 rc = clk_set_rate(priv->clk, priv->use_ncsi ? FTGMAC_25MHZ :
1735 /* RCLK is for RMII, typically used for NCSI. Optional because it's not
1736 * necessary if it's the AST2400 MAC, or the MAC is configured for
1737 * RGMII, or the controller is not an ASPEED-based controller.
1739 priv->rclk = devm_clk_get_optional(priv->dev, "RCLK");
1740 rc = clk_prepare_enable(priv->rclk);
1745 clk_disable_unprepare(priv->clk);
1750 static bool ftgmac100_has_child_node(struct device_node *np, const char *name)
1752 struct device_node *child_np = of_get_child_by_name(np, name);
1757 of_node_put(child_np);
1763 static int ftgmac100_probe(struct platform_device *pdev)
1765 struct resource *res;
1767 struct net_device *netdev;
1768 struct ftgmac100 *priv;
1769 struct device_node *np;
1772 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1776 irq = platform_get_irq(pdev, 0);
1780 /* setup net_device */
1781 netdev = alloc_etherdev(sizeof(*priv));
1784 goto err_alloc_etherdev;
1787 SET_NETDEV_DEV(netdev, &pdev->dev);
1789 netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1790 netdev->netdev_ops = &ftgmac100_netdev_ops;
1791 netdev->watchdog_timeo = 5 * HZ;
1793 platform_set_drvdata(pdev, netdev);
1795 /* setup private data */
1796 priv = netdev_priv(netdev);
1797 priv->netdev = netdev;
1798 priv->dev = &pdev->dev;
1799 INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1802 priv->res = request_mem_region(res->start, resource_size(res),
1803 dev_name(&pdev->dev));
1805 dev_err(&pdev->dev, "Could not reserve memory region\n");
1810 priv->base = ioremap(res->start, resource_size(res));
1812 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1820 priv->tx_pause = true;
1821 priv->rx_pause = true;
1822 priv->aneg_pause = true;
1824 /* MAC address from chip or random one */
1825 ftgmac100_initial_mac(priv);
1827 np = pdev->dev.of_node;
1828 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") ||
1829 of_device_is_compatible(np, "aspeed,ast2500-mac") ||
1830 of_device_is_compatible(np, "aspeed,ast2600-mac"))) {
1831 priv->rxdes0_edorr_mask = BIT(30);
1832 priv->txdes0_edotr_mask = BIT(30);
1833 priv->is_aspeed = true;
1834 /* Disable ast2600 problematic HW arbitration */
1835 if (of_device_is_compatible(np, "aspeed,ast2600-mac")) {
1836 iowrite32(FTGMAC100_TM_DEFAULT,
1837 priv->base + FTGMAC100_OFFSET_TM);
1840 priv->rxdes0_edorr_mask = BIT(15);
1841 priv->txdes0_edotr_mask = BIT(15);
1844 if (np && of_get_property(np, "use-ncsi", NULL)) {
1845 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1846 dev_err(&pdev->dev, "NCSI stack not enabled\n");
1851 dev_info(&pdev->dev, "Using NCSI interface\n");
1852 priv->use_ncsi = true;
1853 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1858 } else if (np && of_get_property(np, "phy-handle", NULL)) {
1859 struct phy_device *phy;
1861 phy = of_phy_get_and_connect(priv->netdev, np,
1862 &ftgmac100_adjust_link);
1864 dev_err(&pdev->dev, "Failed to connect to phy\n");
1866 goto err_setup_mdio;
1869 /* Indicate that we support PAUSE frames (see comment in
1870 * Documentation/networking/phy.rst)
1872 phy_support_asym_pause(phy);
1874 /* Display what we found */
1875 phy_attached_info(phy);
1876 } else if (np && !ftgmac100_has_child_node(np, "mdio")) {
1877 /* Support legacy ASPEED devicetree descriptions that decribe a
1878 * MAC with an embedded MDIO controller but have no "mdio"
1879 * child node. Automatically scan the MDIO bus for available
1882 priv->use_ncsi = false;
1883 err = ftgmac100_setup_mdio(netdev);
1885 goto err_setup_mdio;
1888 if (priv->is_aspeed) {
1889 err = ftgmac100_setup_clk(priv);
1894 /* Default ring sizes */
1895 priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES;
1896 priv->tx_q_entries = priv->new_tx_q_entries = DEF_TX_QUEUE_ENTRIES;
1898 /* Base feature set */
1899 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM |
1900 NETIF_F_GRO | NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX |
1901 NETIF_F_HW_VLAN_CTAG_TX;
1904 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1906 /* AST2400 doesn't have working HW checksum generation */
1907 if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac")))
1908 netdev->hw_features &= ~NETIF_F_HW_CSUM;
1910 /* AST2600 tx checksum with NCSI is broken */
1911 if (priv->use_ncsi && of_device_is_compatible(np, "aspeed,ast2600-mac"))
1912 netdev->hw_features &= ~NETIF_F_HW_CSUM;
1914 if (np && of_get_property(np, "no-hw-checksum", NULL))
1915 netdev->hw_features &= ~(NETIF_F_HW_CSUM | NETIF_F_RXCSUM);
1916 netdev->features |= netdev->hw_features;
1918 /* register network device */
1919 err = register_netdev(netdev);
1921 dev_err(&pdev->dev, "Failed to register netdev\n");
1922 goto err_register_netdev;
1925 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1929 err_register_netdev:
1930 clk_disable_unprepare(priv->rclk);
1931 clk_disable_unprepare(priv->clk);
1934 ncsi_unregister_dev(priv->ndev);
1935 ftgmac100_destroy_mdio(netdev);
1937 iounmap(priv->base);
1939 release_resource(priv->res);
1941 free_netdev(netdev);
1946 static int ftgmac100_remove(struct platform_device *pdev)
1948 struct net_device *netdev;
1949 struct ftgmac100 *priv;
1951 netdev = platform_get_drvdata(pdev);
1952 priv = netdev_priv(netdev);
1955 ncsi_unregister_dev(priv->ndev);
1956 unregister_netdev(netdev);
1958 clk_disable_unprepare(priv->rclk);
1959 clk_disable_unprepare(priv->clk);
1961 /* There's a small chance the reset task will have been re-queued,
1962 * during stop, make sure it's gone before we free the structure.
1964 cancel_work_sync(&priv->reset_task);
1966 ftgmac100_destroy_mdio(netdev);
1968 iounmap(priv->base);
1969 release_resource(priv->res);
1971 netif_napi_del(&priv->napi);
1972 free_netdev(netdev);
1976 static const struct of_device_id ftgmac100_of_match[] = {
1977 { .compatible = "faraday,ftgmac100" },
1980 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1982 static struct platform_driver ftgmac100_driver = {
1983 .probe = ftgmac100_probe,
1984 .remove = ftgmac100_remove,
1987 .of_match_table = ftgmac100_of_match,
1990 module_platform_driver(ftgmac100_driver);
1992 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1993 MODULE_DESCRIPTION("FTGMAC100 driver");
1994 MODULE_LICENSE("GPL");