1 /* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux.
3 Copyright 2000,2001 The Linux Kernel Team
4 Written/copyright 1994-2001 by Donald Becker.
6 This software may be used and distributed according to the terms
7 of the GNU General Public License, incorporated herein by reference.
9 Please submit bugs to http://bugzilla.kernel.org/ .
12 #define pr_fmt(fmt) "tulip: " fmt
14 #define DRV_NAME "tulip"
15 #ifdef CONFIG_TULIP_NAPI
16 #define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */
18 #define DRV_VERSION "1.1.15"
20 #define DRV_RELDATE "Feb 27, 2007"
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/etherdevice.h>
30 #include <linux/delay.h>
31 #include <linux/mii.h>
32 #include <linux/crc32.h>
33 #include <asm/unaligned.h>
34 #include <asm/uaccess.h>
40 static char version[] =
41 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
43 /* A few user-configurable values. */
45 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
46 static unsigned int max_interrupt_work = 25;
49 /* Used to pass the full-duplex flag, etc. */
50 static int full_duplex[MAX_UNITS];
51 static int options[MAX_UNITS];
52 static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
54 /* The possible media types that can be set in options[] are: */
55 const char * const medianame[32] = {
56 "10baseT", "10base2", "AUI", "100baseTx",
57 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
58 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
59 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
60 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
61 "","","","", "","","","", "","","","Transceiver reset",
64 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
65 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
66 defined(CONFIG_SPARC) || defined(__ia64__) || \
67 defined(__sh__) || defined(__mips__)
68 static int rx_copybreak = 1518;
70 static int rx_copybreak = 100;
74 Set the bus performance register.
75 Typical: Set 16 longword cache alignment, no burst limit.
76 Cache alignment bits 15:14 Burst length 13:8
77 0000 No alignment 0x00000000 unlimited 0800 8 longwords
78 4000 8 longwords 0100 1 longword 1000 16 longwords
79 8000 16 longwords 0200 2 longwords 2000 32 longwords
80 C000 32 longwords 0400 4 longwords
81 Warning: many older 486 systems are broken and require setting 0x00A04800
82 8 longword cache alignment, 8 longword burst.
83 ToDo: Non-Intel setting could be better.
86 #if defined(__alpha__) || defined(__ia64__)
87 static int csr0 = 0x01A00000 | 0xE000;
88 #elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
89 static int csr0 = 0x01A00000 | 0x8000;
90 #elif defined(CONFIG_SPARC) || defined(__hppa__)
91 /* The UltraSparc PCI controllers will disconnect at every 64-byte
92 * crossing anyways so it makes no sense to tell Tulip to burst
95 static int csr0 = 0x01A00000 | 0x9000;
96 #elif defined(__arm__) || defined(__sh__)
97 static int csr0 = 0x01A00000 | 0x4800;
98 #elif defined(__mips__)
99 static int csr0 = 0x00200000 | 0x4000;
104 /* Operational parameters that usually are not changed. */
105 /* Time in jiffies before concluding the transmitter is hung. */
106 #define TX_TIMEOUT (4*HZ)
109 MODULE_AUTHOR("The Linux Kernel Team");
110 MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
111 MODULE_LICENSE("GPL");
112 MODULE_VERSION(DRV_VERSION);
113 module_param(tulip_debug, int, 0);
114 module_param(max_interrupt_work, int, 0);
115 module_param(rx_copybreak, int, 0);
116 module_param(csr0, int, 0);
117 module_param_array(options, int, NULL, 0);
118 module_param_array(full_duplex, int, NULL, 0);
121 int tulip_debug = TULIP_DEBUG;
126 static void tulip_timer(unsigned long data)
128 struct net_device *dev = (struct net_device *)data;
129 struct tulip_private *tp = netdev_priv(dev);
131 if (netif_running(dev))
132 schedule_work(&tp->media_work);
136 * This table use during operation for capabilities and media timer.
138 * It is indexed via the values in 'enum chips'
141 struct tulip_chip_table tulip_tbl[] = {
142 { }, /* placeholder for array, slot unused currently */
143 { }, /* placeholder for array, slot unused currently */
146 { "Digital DS21140 Tulip", 128, 0x0001ebef,
147 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
150 /* DC21142, DC21143 */
151 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
152 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
153 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
156 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
157 HAS_MII | HAS_PNICNWAY, pnic_timer, },
160 { "Macronix 98713 PMAC", 128, 0x0001ebef,
161 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
164 { "Macronix 98715 PMAC", 256, 0x0001ebef,
165 HAS_MEDIA_TABLE, mxic_timer, },
168 { "Macronix 98725 PMAC", 256, 0x0001ebef,
169 HAS_MEDIA_TABLE, mxic_timer, },
172 { "ASIX AX88140", 128, 0x0001fbff,
173 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
174 | IS_ASIX, tulip_timer, tulip_media_task },
177 { "Lite-On PNIC-II", 256, 0x0801fbff,
178 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
181 { "ADMtek Comet", 256, 0x0001abef,
182 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
185 { "Compex 9881 PMAC", 128, 0x0001ebef,
186 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
189 { "Intel DS21145 Tulip", 128, 0x0801fbff,
190 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
191 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
194 #ifdef CONFIG_TULIP_DM910X
195 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
196 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
197 tulip_timer, tulip_media_task },
203 { "Conexant LANfinity", 256, 0x0001ebef,
204 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
209 static const struct pci_device_id tulip_pci_tbl[] = {
210 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
211 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
212 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
213 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
214 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
215 /* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
216 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
217 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
218 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
219 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
220 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
221 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
222 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
229 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
230 #ifdef CONFIG_TULIP_DM910X
231 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
232 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
234 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
235 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
236 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
237 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
238 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
239 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
240 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
241 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
242 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
244 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
245 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
246 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
247 { 0x1414, 0x0001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Microsoft MN-120 */
248 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
249 { } /* terminate list */
251 MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
254 /* A full-duplex map for media types. */
255 const char tulip_media_cap[32] =
256 {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
258 static void tulip_tx_timeout(struct net_device *dev);
259 static void tulip_init_ring(struct net_device *dev);
260 static void tulip_free_ring(struct net_device *dev);
261 static netdev_tx_t tulip_start_xmit(struct sk_buff *skb,
262 struct net_device *dev);
263 static int tulip_open(struct net_device *dev);
264 static int tulip_close(struct net_device *dev);
265 static void tulip_up(struct net_device *dev);
266 static void tulip_down(struct net_device *dev);
267 static struct net_device_stats *tulip_get_stats(struct net_device *dev);
268 static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
269 static void set_rx_mode(struct net_device *dev);
270 static void tulip_set_wolopts(struct pci_dev *pdev, u32 wolopts);
271 #ifdef CONFIG_NET_POLL_CONTROLLER
272 static void poll_tulip(struct net_device *dev);
275 static void tulip_set_power_state (struct tulip_private *tp,
276 int sleep, int snooze)
278 if (tp->flags & HAS_ACPI) {
280 pci_read_config_dword (tp->pdev, CFDD, &tmp);
281 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
283 newtmp |= CFDD_Sleep;
285 newtmp |= CFDD_Snooze;
287 pci_write_config_dword (tp->pdev, CFDD, newtmp);
293 static void tulip_up(struct net_device *dev)
295 struct tulip_private *tp = netdev_priv(dev);
296 void __iomem *ioaddr = tp->base_addr;
297 int next_tick = 3*HZ;
301 #ifdef CONFIG_TULIP_NAPI
302 napi_enable(&tp->napi);
305 /* Wake the chip from sleep/snooze mode. */
306 tulip_set_power_state (tp, 0, 0);
308 /* Disable all WOL events */
309 pci_enable_wake(tp->pdev, PCI_D3hot, 0);
310 pci_enable_wake(tp->pdev, PCI_D3cold, 0);
311 tulip_set_wolopts(tp->pdev, 0);
313 /* On some chip revs we must set the MII/SYM port before the reset!? */
314 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
315 iowrite32(0x00040000, ioaddr + CSR6);
317 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
318 iowrite32(0x00000001, ioaddr + CSR0);
319 pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */
323 Wait the specified 50 PCI cycles after a reset by initializing
324 Tx and Rx queues and the address filter list. */
325 iowrite32(tp->csr0, ioaddr + CSR0);
326 pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */
330 netdev_dbg(dev, "tulip_up(), irq==%d\n", tp->pdev->irq);
332 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
333 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
334 tp->cur_rx = tp->cur_tx = 0;
335 tp->dirty_rx = tp->dirty_tx = 0;
337 if (tp->flags & MC_HASH_ONLY) {
338 u32 addr_low = get_unaligned_le32(dev->dev_addr);
339 u32 addr_high = get_unaligned_le16(dev->dev_addr + 4);
340 if (tp->chip_id == AX88140) {
341 iowrite32(0, ioaddr + CSR13);
342 iowrite32(addr_low, ioaddr + CSR14);
343 iowrite32(1, ioaddr + CSR13);
344 iowrite32(addr_high, ioaddr + CSR14);
345 } else if (tp->flags & COMET_MAC_ADDR) {
346 iowrite32(addr_low, ioaddr + 0xA4);
347 iowrite32(addr_high, ioaddr + 0xA8);
348 iowrite32(0, ioaddr + CSR27);
349 iowrite32(0, ioaddr + CSR28);
352 /* This is set_rx_mode(), but without starting the transmitter. */
353 u16 *eaddrs = (u16 *)dev->dev_addr;
354 u16 *setup_frm = &tp->setup_frame[15*6];
357 /* 21140 bug: you must add the broadcast address. */
358 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
359 /* Fill the final entry of the table with our physical address. */
360 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
361 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
362 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
364 mapping = pci_map_single(tp->pdev, tp->setup_frame,
365 sizeof(tp->setup_frame),
367 tp->tx_buffers[tp->cur_tx].skb = NULL;
368 tp->tx_buffers[tp->cur_tx].mapping = mapping;
370 /* Put the setup frame on the Tx list. */
371 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
372 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
373 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
378 tp->saved_if_port = dev->if_port;
379 if (dev->if_port == 0)
380 dev->if_port = tp->default_port;
382 /* Allow selecting a default media. */
384 if (tp->mtable == NULL)
387 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
388 (dev->if_port == 12 ? 0 : dev->if_port);
389 for (i = 0; i < tp->mtable->leafcount; i++)
390 if (tp->mtable->mleaf[i].media == looking_for) {
392 "Using user-specified media %s\n",
393 medianame[dev->if_port]);
397 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
398 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
399 for (i = 0; i < tp->mtable->leafcount; i++)
400 if (tp->mtable->mleaf[i].media == looking_for) {
402 "Using EEPROM-set media %s\n",
403 medianame[looking_for]);
407 /* Start sensing first non-full-duplex media. */
408 for (i = tp->mtable->leafcount - 1;
409 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
418 if (tp->chip_id == DC21143 &&
419 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
420 /* We must reset the media CSRs when we force-select MII mode. */
421 iowrite32(0x0000, ioaddr + CSR13);
422 iowrite32(0x0000, ioaddr + CSR14);
423 iowrite32(0x0008, ioaddr + CSR15);
425 tulip_select_media(dev, 1);
426 } else if (tp->chip_id == DC21142) {
428 tulip_select_media(dev, 1);
431 "Using MII transceiver %d, status %04x\n",
433 tulip_mdio_read(dev, tp->phys[0], 1));
434 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
435 tp->csr6 = csr6_mask_hdcap;
437 iowrite32(0x0000, ioaddr + CSR13);
438 iowrite32(0x0000, ioaddr + CSR14);
440 t21142_start_nway(dev);
441 } else if (tp->chip_id == PNIC2) {
442 /* for initial startup advertise 10/100 Full and Half */
443 tp->sym_advertise = 0x01E0;
444 /* enable autonegotiate end interrupt */
445 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
446 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
447 pnic2_start_nway(dev);
448 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
451 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
452 iowrite32(0x0001, ioaddr + CSR15);
453 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
456 /* Start with 10mbps to do autonegotiation. */
457 iowrite32(0x32, ioaddr + CSR12);
458 tp->csr6 = 0x00420000;
459 iowrite32(0x0001B078, ioaddr + 0xB8);
460 iowrite32(0x0201B078, ioaddr + 0xB8);
463 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881) &&
466 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
467 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
468 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
469 /* Provided by BOLO, Macronix - 12/10/1998. */
471 tp->csr6 = 0x01a80200;
472 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
473 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
474 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
475 /* Enable automatic Tx underrun recovery. */
476 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
477 dev->if_port = tp->mii_cnt ? 11 : 0;
478 tp->csr6 = 0x00040000;
479 } else if (tp->chip_id == AX88140) {
480 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
482 tulip_select_media(dev, 1);
484 /* Start the chip's Tx to process setup frame. */
488 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
490 /* Enable interrupts by setting the interrupt mask. */
491 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
492 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
493 tulip_start_rxtx(tp);
494 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
496 if (tulip_debug > 2) {
497 netdev_dbg(dev, "Done tulip_up(), CSR0 %08x, CSR5 %08x CSR6 %08x\n",
498 ioread32(ioaddr + CSR0),
499 ioread32(ioaddr + CSR5),
500 ioread32(ioaddr + CSR6));
503 /* Set the timer to switch to check for link beat and perhaps switch
504 to an alternate media type. */
505 tp->timer.expires = RUN_AT(next_tick);
506 add_timer(&tp->timer);
507 #ifdef CONFIG_TULIP_NAPI
508 init_timer(&tp->oom_timer);
509 tp->oom_timer.data = (unsigned long)dev;
510 tp->oom_timer.function = oom_timer;
515 tulip_open(struct net_device *dev)
517 struct tulip_private *tp = netdev_priv(dev);
520 tulip_init_ring (dev);
522 retval = request_irq(tp->pdev->irq, tulip_interrupt, IRQF_SHARED,
529 netif_start_queue (dev);
534 tulip_free_ring (dev);
539 static void tulip_tx_timeout(struct net_device *dev)
541 struct tulip_private *tp = netdev_priv(dev);
542 void __iomem *ioaddr = tp->base_addr;
545 spin_lock_irqsave (&tp->lock, flags);
547 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
548 /* Do nothing -- the media monitor should handle this. */
551 "Transmit timeout using MII device\n");
552 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142 ||
553 tp->chip_id == MX98713 || tp->chip_id == COMPEX9881 ||
554 tp->chip_id == DM910X) {
556 "21140 transmit timed out, status %08x, SIA %08x %08x %08x %08x, resetting...\n",
557 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
558 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14),
559 ioread32(ioaddr + CSR15));
560 tp->timeout_recovery = 1;
561 schedule_work(&tp->media_work);
563 } else if (tp->chip_id == PNIC2) {
565 "PNIC2 transmit timed out, status %08x, CSR6/7 %08x / %08x CSR12 %08x, resetting...\n",
566 (int)ioread32(ioaddr + CSR5),
567 (int)ioread32(ioaddr + CSR6),
568 (int)ioread32(ioaddr + CSR7),
569 (int)ioread32(ioaddr + CSR12));
572 "Transmit timed out, status %08x, CSR12 %08x, resetting...\n",
573 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
577 #if defined(way_too_many_messages)
578 if (tulip_debug > 3) {
580 for (i = 0; i < RX_RING_SIZE; i++) {
581 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
584 "%2d: %08x %08x %08x %08x %02x %02x %02x\n",
586 (unsigned int)tp->rx_ring[i].status,
587 (unsigned int)tp->rx_ring[i].length,
588 (unsigned int)tp->rx_ring[i].buffer1,
589 (unsigned int)tp->rx_ring[i].buffer2,
590 buf[0], buf[1], buf[2]);
591 for (j = 0; ((j < 1600) && buf[j] != 0xee); j++)
593 pr_cont(" %02x", buf[j]);
594 pr_cont(" j=%d\n", j);
596 printk(KERN_DEBUG " Rx ring %p: ", tp->rx_ring);
597 for (i = 0; i < RX_RING_SIZE; i++)
598 pr_cont(" %08x", (unsigned int)tp->rx_ring[i].status);
599 printk(KERN_DEBUG " Tx ring %p: ", tp->tx_ring);
600 for (i = 0; i < TX_RING_SIZE; i++)
601 pr_cont(" %08x", (unsigned int)tp->tx_ring[i].status);
606 tulip_tx_timeout_complete(tp, ioaddr);
609 spin_unlock_irqrestore (&tp->lock, flags);
610 dev->trans_start = jiffies; /* prevent tx timeout */
611 netif_wake_queue (dev);
615 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
616 static void tulip_init_ring(struct net_device *dev)
618 struct tulip_private *tp = netdev_priv(dev);
625 for (i = 0; i < RX_RING_SIZE; i++) {
626 tp->rx_ring[i].status = 0x00000000;
627 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
628 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
629 tp->rx_buffers[i].skb = NULL;
630 tp->rx_buffers[i].mapping = 0;
632 /* Mark the last entry as wrapping the ring. */
633 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
634 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
636 for (i = 0; i < RX_RING_SIZE; i++) {
639 /* Note the receive buffer must be longword aligned.
640 netdev_alloc_skb() provides 16 byte alignment. But do *not*
641 use skb_reserve() to align the IP header! */
642 struct sk_buff *skb = netdev_alloc_skb(dev, PKT_BUF_SZ);
643 tp->rx_buffers[i].skb = skb;
646 mapping = pci_map_single(tp->pdev, skb->data,
647 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
648 tp->rx_buffers[i].mapping = mapping;
649 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
650 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
652 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
654 /* The Tx buffer descriptor is filled in as needed, but we
655 do need to clear the ownership bit. */
656 for (i = 0; i < TX_RING_SIZE; i++) {
657 tp->tx_buffers[i].skb = NULL;
658 tp->tx_buffers[i].mapping = 0;
659 tp->tx_ring[i].status = 0x00000000;
660 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
662 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
666 tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
668 struct tulip_private *tp = netdev_priv(dev);
674 spin_lock_irqsave(&tp->lock, flags);
676 /* Calculate the next Tx descriptor entry. */
677 entry = tp->cur_tx % TX_RING_SIZE;
679 tp->tx_buffers[entry].skb = skb;
680 mapping = pci_map_single(tp->pdev, skb->data,
681 skb->len, PCI_DMA_TODEVICE);
682 tp->tx_buffers[entry].mapping = mapping;
683 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
685 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
686 flag = 0x60000000; /* No interrupt */
687 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
688 flag = 0xe0000000; /* Tx-done intr. */
689 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
690 flag = 0x60000000; /* No Tx-done intr. */
691 } else { /* Leave room for set_rx_mode() to fill entries. */
692 flag = 0xe0000000; /* Tx-done intr. */
693 netif_stop_queue(dev);
695 if (entry == TX_RING_SIZE-1)
696 flag = 0xe0000000 | DESC_RING_WRAP;
698 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
699 /* if we were using Transmit Automatic Polling, we would need a
701 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
706 /* Trigger an immediate transmit demand. */
707 iowrite32(0, tp->base_addr + CSR1);
709 spin_unlock_irqrestore(&tp->lock, flags);
714 static void tulip_clean_tx_ring(struct tulip_private *tp)
716 unsigned int dirty_tx;
718 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
720 int entry = dirty_tx % TX_RING_SIZE;
721 int status = le32_to_cpu(tp->tx_ring[entry].status);
724 tp->dev->stats.tx_errors++; /* It wasn't Txed */
725 tp->tx_ring[entry].status = 0;
728 /* Check for Tx filter setup frames. */
729 if (tp->tx_buffers[entry].skb == NULL) {
730 /* test because dummy frames not mapped */
731 if (tp->tx_buffers[entry].mapping)
732 pci_unmap_single(tp->pdev,
733 tp->tx_buffers[entry].mapping,
734 sizeof(tp->setup_frame),
739 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
740 tp->tx_buffers[entry].skb->len,
743 /* Free the original skb. */
744 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
745 tp->tx_buffers[entry].skb = NULL;
746 tp->tx_buffers[entry].mapping = 0;
750 static void tulip_down (struct net_device *dev)
752 struct tulip_private *tp = netdev_priv(dev);
753 void __iomem *ioaddr = tp->base_addr;
756 cancel_work_sync(&tp->media_work);
758 #ifdef CONFIG_TULIP_NAPI
759 napi_disable(&tp->napi);
762 del_timer_sync (&tp->timer);
763 #ifdef CONFIG_TULIP_NAPI
764 del_timer_sync (&tp->oom_timer);
766 spin_lock_irqsave (&tp->lock, flags);
768 /* Disable interrupts by clearing the interrupt mask. */
769 iowrite32 (0x00000000, ioaddr + CSR7);
771 /* Stop the Tx and Rx processes. */
774 /* prepare receive buffers */
775 tulip_refill_rx(dev);
777 /* release any unconsumed transmit buffers */
778 tulip_clean_tx_ring(tp);
780 if (ioread32(ioaddr + CSR6) != 0xffffffff)
781 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
783 spin_unlock_irqrestore (&tp->lock, flags);
785 init_timer(&tp->timer);
786 tp->timer.data = (unsigned long)dev;
787 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
789 dev->if_port = tp->saved_if_port;
791 /* Leave the driver in snooze, not sleep, mode. */
792 tulip_set_power_state (tp, 0, 1);
795 static void tulip_free_ring (struct net_device *dev)
797 struct tulip_private *tp = netdev_priv(dev);
800 /* Free all the skbuffs in the Rx queue. */
801 for (i = 0; i < RX_RING_SIZE; i++) {
802 struct sk_buff *skb = tp->rx_buffers[i].skb;
803 dma_addr_t mapping = tp->rx_buffers[i].mapping;
805 tp->rx_buffers[i].skb = NULL;
806 tp->rx_buffers[i].mapping = 0;
808 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
809 tp->rx_ring[i].length = 0;
810 /* An invalid address. */
811 tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0);
813 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
819 for (i = 0; i < TX_RING_SIZE; i++) {
820 struct sk_buff *skb = tp->tx_buffers[i].skb;
823 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
824 skb->len, PCI_DMA_TODEVICE);
827 tp->tx_buffers[i].skb = NULL;
828 tp->tx_buffers[i].mapping = 0;
832 static int tulip_close (struct net_device *dev)
834 struct tulip_private *tp = netdev_priv(dev);
835 void __iomem *ioaddr = tp->base_addr;
837 netif_stop_queue (dev);
842 netdev_dbg(dev, "Shutting down ethercard, status was %02x\n",
843 ioread32 (ioaddr + CSR5));
845 free_irq (tp->pdev->irq, dev);
847 tulip_free_ring (dev);
852 static struct net_device_stats *tulip_get_stats(struct net_device *dev)
854 struct tulip_private *tp = netdev_priv(dev);
855 void __iomem *ioaddr = tp->base_addr;
857 if (netif_running(dev)) {
860 spin_lock_irqsave (&tp->lock, flags);
862 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
864 spin_unlock_irqrestore(&tp->lock, flags);
871 static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
873 struct tulip_private *np = netdev_priv(dev);
874 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
875 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
876 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
880 static int tulip_ethtool_set_wol(struct net_device *dev,
881 struct ethtool_wolinfo *wolinfo)
883 struct tulip_private *tp = netdev_priv(dev);
885 if (wolinfo->wolopts & (~tp->wolinfo.supported))
888 tp->wolinfo.wolopts = wolinfo->wolopts;
889 device_set_wakeup_enable(&tp->pdev->dev, tp->wolinfo.wolopts);
893 static void tulip_ethtool_get_wol(struct net_device *dev,
894 struct ethtool_wolinfo *wolinfo)
896 struct tulip_private *tp = netdev_priv(dev);
898 wolinfo->supported = tp->wolinfo.supported;
899 wolinfo->wolopts = tp->wolinfo.wolopts;
904 static const struct ethtool_ops ops = {
905 .get_drvinfo = tulip_get_drvinfo,
906 .set_wol = tulip_ethtool_set_wol,
907 .get_wol = tulip_ethtool_get_wol,
910 /* Provide ioctl() calls to examine the MII xcvr state. */
911 static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
913 struct tulip_private *tp = netdev_priv(dev);
914 void __iomem *ioaddr = tp->base_addr;
915 struct mii_ioctl_data *data = if_mii(rq);
916 const unsigned int phy_idx = 0;
917 int phy = tp->phys[phy_idx] & 0x1f;
918 unsigned int regnum = data->reg_num;
921 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
924 else if (tp->flags & HAS_NWAY)
926 else if (tp->chip_id == COMET)
931 case SIOCGMIIREG: /* Read MII PHY register. */
932 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
933 int csr12 = ioread32 (ioaddr + CSR12);
934 int csr14 = ioread32 (ioaddr + CSR14);
937 if (((csr14<<5) & 0x1000) ||
938 (dev->if_port == 5 && tp->nwayset))
939 data->val_out = 0x1000;
941 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
942 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
947 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
948 ((csr12&0x06) == 6 ? 0 : 4);
949 data->val_out |= 0x6048;
952 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
954 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
955 ((csr14 >> 1) & 0x20) + 1;
956 data->val_out |= ((csr14 >> 9) & 0x03C0);
958 case 5: data->val_out = tp->lpar; break;
959 default: data->val_out = 0; break;
962 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
966 case SIOCSMIIREG: /* Write MII PHY register. */
969 if (data->phy_id == phy) {
970 u16 value = data->val_in;
972 case 0: /* Check for autonegotiation on or reset. */
973 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
974 if (tp->full_duplex_lock)
975 tp->full_duplex = (value & 0x0100) ? 1 : 0;
978 tp->advertising[phy_idx] =
979 tp->mii_advertise = data->val_in;
983 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
984 u16 value = data->val_in;
986 if ((value & 0x1200) == 0x1200) {
987 if (tp->chip_id == PNIC2) {
988 pnic2_start_nway (dev);
990 t21142_start_nway (dev);
993 } else if (regnum == 4)
994 tp->sym_advertise = value;
996 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
1007 /* Set or clear the multicast filter for this adaptor.
1008 Note that we only use exclusion around actually queueing the
1009 new frame, not around filling tp->setup_frame. This is non-deterministic
1010 when re-entered but still correct. */
1012 static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
1014 struct tulip_private *tp = netdev_priv(dev);
1016 struct netdev_hw_addr *ha;
1020 memset(hash_table, 0, sizeof(hash_table));
1021 __set_bit_le(255, hash_table); /* Broadcast entry */
1022 /* This should work on big-endian machines as well. */
1023 netdev_for_each_mc_addr(ha, dev) {
1024 int index = ether_crc_le(ETH_ALEN, ha->addr) & 0x1ff;
1026 __set_bit_le(index, hash_table);
1028 for (i = 0; i < 32; i++) {
1029 *setup_frm++ = hash_table[i];
1030 *setup_frm++ = hash_table[i];
1032 setup_frm = &tp->setup_frame[13*6];
1034 /* Fill the final entry with our physical address. */
1035 eaddrs = (u16 *)dev->dev_addr;
1036 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1037 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1038 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1041 static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
1043 struct tulip_private *tp = netdev_priv(dev);
1044 struct netdev_hw_addr *ha;
1047 /* We have <= 14 addresses so we can use the wonderful
1048 16 address perfect filtering of the Tulip. */
1049 netdev_for_each_mc_addr(ha, dev) {
1050 eaddrs = (u16 *) ha->addr;
1051 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1052 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1053 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1055 /* Fill the unused entries with the broadcast address. */
1056 memset(setup_frm, 0xff, (15 - netdev_mc_count(dev)) * 12);
1057 setup_frm = &tp->setup_frame[15*6];
1059 /* Fill the final entry with our physical address. */
1060 eaddrs = (u16 *)dev->dev_addr;
1061 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1062 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1063 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1067 static void set_rx_mode(struct net_device *dev)
1069 struct tulip_private *tp = netdev_priv(dev);
1070 void __iomem *ioaddr = tp->base_addr;
1073 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1075 tp->csr6 &= ~0x00D5;
1076 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1077 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1078 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1079 } else if ((netdev_mc_count(dev) > 1000) ||
1080 (dev->flags & IFF_ALLMULTI)) {
1081 /* Too many to filter well -- accept all multicasts. */
1082 tp->csr6 |= AcceptAllMulticast;
1083 csr6 |= AcceptAllMulticast;
1084 } else if (tp->flags & MC_HASH_ONLY) {
1085 /* Some work-alikes have only a 64-entry hash filter table. */
1086 /* Should verify correctness on big-endian/__powerpc__ */
1087 struct netdev_hw_addr *ha;
1088 if (netdev_mc_count(dev) > 64) {
1089 /* Arbitrary non-effective limit. */
1090 tp->csr6 |= AcceptAllMulticast;
1091 csr6 |= AcceptAllMulticast;
1093 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1095 netdev_for_each_mc_addr(ha, dev) {
1096 if (tp->flags & COMET_MAC_ADDR)
1097 filterbit = ether_crc_le(ETH_ALEN,
1100 filterbit = ether_crc(ETH_ALEN,
1103 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1104 if (tulip_debug > 2)
1106 "Added filter for %pM %08x bit %d\n",
1108 ether_crc(ETH_ALEN, ha->addr),
1111 if (mc_filter[0] == tp->mc_filter[0] &&
1112 mc_filter[1] == tp->mc_filter[1])
1114 else if (tp->flags & IS_ASIX) {
1115 iowrite32(2, ioaddr + CSR13);
1116 iowrite32(mc_filter[0], ioaddr + CSR14);
1117 iowrite32(3, ioaddr + CSR13);
1118 iowrite32(mc_filter[1], ioaddr + CSR14);
1119 } else if (tp->flags & COMET_MAC_ADDR) {
1120 iowrite32(mc_filter[0], ioaddr + CSR27);
1121 iowrite32(mc_filter[1], ioaddr + CSR28);
1123 tp->mc_filter[0] = mc_filter[0];
1124 tp->mc_filter[1] = mc_filter[1];
1127 unsigned long flags;
1128 u32 tx_flags = 0x08000000 | 192;
1130 /* Note that only the low-address shortword of setup_frame is valid!
1131 The values are doubled for big-endian architectures. */
1132 if (netdev_mc_count(dev) > 14) {
1133 /* Must use a multicast hash table. */
1134 build_setup_frame_hash(tp->setup_frame, dev);
1135 tx_flags = 0x08400000 | 192;
1137 build_setup_frame_perfect(tp->setup_frame, dev);
1140 spin_lock_irqsave(&tp->lock, flags);
1142 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1143 /* Same setup recently queued, we need not add it. */
1148 /* Now add this frame to the Tx list. */
1150 entry = tp->cur_tx++ % TX_RING_SIZE;
1153 /* Avoid a chip errata by prefixing a dummy entry. */
1154 tp->tx_buffers[entry].skb = NULL;
1155 tp->tx_buffers[entry].mapping = 0;
1156 tp->tx_ring[entry].length =
1157 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1158 tp->tx_ring[entry].buffer1 = 0;
1159 /* Must set DescOwned later to avoid race with chip */
1161 entry = tp->cur_tx++ % TX_RING_SIZE;
1165 tp->tx_buffers[entry].skb = NULL;
1166 tp->tx_buffers[entry].mapping =
1167 pci_map_single(tp->pdev, tp->setup_frame,
1168 sizeof(tp->setup_frame),
1170 /* Put the setup frame on the Tx list. */
1171 if (entry == TX_RING_SIZE-1)
1172 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1173 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1174 tp->tx_ring[entry].buffer1 =
1175 cpu_to_le32(tp->tx_buffers[entry].mapping);
1176 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1178 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1179 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1180 netif_stop_queue(dev);
1182 /* Trigger an immediate transmit demand. */
1183 iowrite32(0, ioaddr + CSR1);
1186 spin_unlock_irqrestore(&tp->lock, flags);
1189 iowrite32(csr6, ioaddr + CSR6);
1192 #ifdef CONFIG_TULIP_MWI
1193 static void tulip_mwi_config(struct pci_dev *pdev, struct net_device *dev)
1195 struct tulip_private *tp = netdev_priv(dev);
1200 if (tulip_debug > 3)
1201 netdev_dbg(dev, "tulip_mwi_config()\n");
1203 tp->csr0 = csr0 = 0;
1205 /* if we have any cache line size at all, we can do MRM and MWI */
1208 /* Enable MWI in the standard PCI command bit.
1209 * Check for the case where MWI is desired but not available
1211 pci_try_set_mwi(pdev);
1213 /* read result from hardware (in case bit refused to enable) */
1214 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1215 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1218 /* if cache line size hardwired to zero, no MWI */
1219 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1220 if ((csr0 & MWI) && (cache == 0)) {
1222 pci_clear_mwi(pdev);
1225 /* assign per-cacheline-size cache alignment and
1226 * burst length values
1230 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1233 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1236 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1243 /* if we have a good cache line size, we by now have a good
1244 * csr0, so save it and exit
1249 /* we don't have a good csr0 or cache line size, disable MWI */
1251 pci_clear_mwi(pdev);
1255 /* sane defaults for burst length and cache alignment
1256 * originally from de4x5 driver
1258 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1262 if (tulip_debug > 2)
1263 netdev_dbg(dev, "MWI config cacheline=%d, csr0=%08x\n",
1269 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1270 * is the DM910X and the on chip ULi devices
1273 static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1275 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1280 static const struct net_device_ops tulip_netdev_ops = {
1281 .ndo_open = tulip_open,
1282 .ndo_start_xmit = tulip_start_xmit,
1283 .ndo_tx_timeout = tulip_tx_timeout,
1284 .ndo_stop = tulip_close,
1285 .ndo_get_stats = tulip_get_stats,
1286 .ndo_do_ioctl = private_ioctl,
1287 .ndo_set_rx_mode = set_rx_mode,
1288 .ndo_change_mtu = eth_change_mtu,
1289 .ndo_set_mac_address = eth_mac_addr,
1290 .ndo_validate_addr = eth_validate_addr,
1291 #ifdef CONFIG_NET_POLL_CONTROLLER
1292 .ndo_poll_controller = poll_tulip,
1296 const struct pci_device_id early_486_chipsets[] = {
1297 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1298 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1302 static int tulip_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1304 struct tulip_private *tp;
1305 /* See note below on the multiport cards. */
1306 static unsigned char last_phys_addr[ETH_ALEN] = {
1307 0x00, 'L', 'i', 'n', 'u', 'x'
1309 static int last_irq;
1310 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1313 unsigned char *ee_data;
1314 struct net_device *dev;
1315 void __iomem *ioaddr;
1316 static int board_idx = -1;
1317 int chip_idx = ent->driver_data;
1318 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1319 unsigned int eeprom_missing = 0;
1320 unsigned int force_csr0 = 0;
1323 if (tulip_debug > 0)
1324 printk_once(KERN_INFO "%s", version);
1330 * Lan media wire a tulip chip to a wan interface. Needs a very
1331 * different driver (lmc driver)
1334 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1335 pr_err("skipping LMC card\n");
1337 } else if (pdev->subsystem_vendor == PCI_VENDOR_ID_SBE &&
1338 (pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_T3E3 ||
1339 pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P0 ||
1340 pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P1)) {
1341 pr_err("skipping SBE T3E3 port\n");
1346 * DM910x chips should be handled by the dmfe driver, except
1347 * on-board chips on SPARC systems. Also, early DM9100s need
1348 * software CRC which only the dmfe driver supports.
1351 #ifdef CONFIG_TULIP_DM910X
1352 if (chip_idx == DM910X) {
1353 struct device_node *dp;
1355 if (pdev->vendor == 0x1282 && pdev->device == 0x9100 &&
1356 pdev->revision < 0x30) {
1357 pr_info("skipping early DM9100 with Crc bug (use dmfe)\n");
1361 dp = pci_device_to_OF_node(pdev);
1362 if (!(dp && of_get_property(dp, "local-mac-address", NULL))) {
1363 pr_info("skipping DM910x expansion card (use dmfe)\n");
1370 * Looks for early PCI chipsets where people report hangs
1371 * without the workarounds being on.
1374 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
1375 aligned. Aries might need this too. The Saturn errata are not
1376 pretty reading but thankfully it's an old 486 chipset.
1378 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1382 if (pci_dev_present(early_486_chipsets)) {
1383 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1387 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1388 if (chip_idx == AX88140) {
1389 if ((csr0 & 0x3f00) == 0)
1393 /* PNIC doesn't have MWI/MRL/MRM... */
1394 if (chip_idx == LC82C168)
1395 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1397 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1398 if (tulip_uli_dm_quirk(pdev)) {
1399 csr0 &= ~0x01f100ff;
1400 #if defined(CONFIG_SPARC)
1401 csr0 = (csr0 & ~0xff00) | 0xe000;
1405 * And back to business
1408 i = pci_enable_device(pdev);
1410 pr_err("Cannot enable tulip board #%d, aborting\n", board_idx);
1416 /* alloc_etherdev ensures aligned and zeroed private structures */
1417 dev = alloc_etherdev (sizeof (*tp));
1421 SET_NETDEV_DEV(dev, &pdev->dev);
1422 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
1423 pr_err("%s: I/O region (0x%llx@0x%llx) too small, aborting\n",
1425 (unsigned long long)pci_resource_len (pdev, 0),
1426 (unsigned long long)pci_resource_start (pdev, 0));
1427 goto err_out_free_netdev;
1430 /* grab all resources from both PIO and MMIO regions, as we
1431 * don't want anyone else messing around with our hardware */
1432 if (pci_request_regions (pdev, DRV_NAME))
1433 goto err_out_free_netdev;
1435 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1438 goto err_out_free_res;
1441 * initialize private data structure 'tp'
1442 * it is zeroed and aligned in alloc_etherdev
1444 tp = netdev_priv(dev);
1447 tp->rx_ring = pci_alloc_consistent(pdev,
1448 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1449 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1452 goto err_out_mtable;
1453 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1454 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1456 tp->chip_id = chip_idx;
1457 tp->flags = tulip_tbl[chip_idx].flags;
1459 tp->wolinfo.supported = 0;
1460 tp->wolinfo.wolopts = 0;
1461 /* COMET: Enable power management only for AN983B */
1462 if (chip_idx == COMET ) {
1464 pci_read_config_dword (pdev, 0x80, &sig);
1465 if (sig == 0x09811317) {
1466 tp->flags |= COMET_PM;
1467 tp->wolinfo.supported = WAKE_PHY | WAKE_MAGIC;
1468 pr_info("%s: Enabled WOL support for AN983B\n",
1473 tp->base_addr = ioaddr;
1474 tp->revision = pdev->revision;
1476 spin_lock_init(&tp->lock);
1477 spin_lock_init(&tp->mii_lock);
1478 init_timer(&tp->timer);
1479 tp->timer.data = (unsigned long)dev;
1480 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1482 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
1484 #ifdef CONFIG_TULIP_MWI
1485 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1486 tulip_mwi_config (pdev, dev);
1489 /* Stop the chip's Tx and Rx processes. */
1490 tulip_stop_rxtx(tp);
1492 pci_set_master(pdev);
1495 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1496 switch (pdev->subsystem_device) {
1505 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1506 chip_name = "GSC DS21140 Tulip";
1511 /* Clear the missed-packet counter. */
1512 ioread32(ioaddr + CSR8);
1514 /* The station address ROM is read byte serially. The register must
1515 be polled, waiting for the value to be read bit serially from the
1518 ee_data = tp->eeprom;
1519 memset(ee_data, 0, sizeof(tp->eeprom));
1521 if (chip_idx == LC82C168) {
1522 for (i = 0; i < 3; i++) {
1523 int value, boguscnt = 100000;
1524 iowrite32(0x600 | i, ioaddr + 0x98);
1526 value = ioread32(ioaddr + CSR9);
1527 } while (value < 0 && --boguscnt > 0);
1528 put_unaligned_le16(value, ((__le16 *)dev->dev_addr) + i);
1529 sum += value & 0xffff;
1531 } else if (chip_idx == COMET) {
1532 /* No need to read the EEPROM. */
1533 put_unaligned_le32(ioread32(ioaddr + 0xA4), dev->dev_addr);
1534 put_unaligned_le16(ioread32(ioaddr + 0xA8), dev->dev_addr + 4);
1535 for (i = 0; i < 6; i ++)
1536 sum += dev->dev_addr[i];
1538 /* A serial EEPROM interface, we read now and sort it out later. */
1540 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1541 int ee_max_addr = ((1 << ee_addr_size) - 1) * sizeof(u16);
1543 if (ee_max_addr > sizeof(tp->eeprom))
1544 ee_max_addr = sizeof(tp->eeprom);
1546 for (i = 0; i < ee_max_addr ; i += sizeof(u16)) {
1547 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1548 ee_data[i] = data & 0xff;
1549 ee_data[i + 1] = data >> 8;
1552 /* DEC now has a specification (see Notes) but early board makers
1553 just put the address in the first EEPROM locations. */
1554 /* This does memcmp(ee_data, ee_data+16, 8) */
1555 for (i = 0; i < 8; i ++)
1556 if (ee_data[i] != ee_data[16+i])
1558 if (chip_idx == CONEXANT) {
1559 /* Check that the tuple type and length is correct. */
1560 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1562 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1564 sa_offset = 2; /* Grrr, damn Matrox boards. */
1567 #ifdef CONFIG_MIPS_COBALT
1568 if ((pdev->bus->number == 0) &&
1569 ((PCI_SLOT(pdev->devfn) == 7) ||
1570 (PCI_SLOT(pdev->devfn) == 12))) {
1571 /* Cobalt MAC address in first EEPROM locations. */
1573 /* Ensure our media table fixup get's applied */
1574 memcpy(ee_data + 16, ee_data, 8);
1578 /* Check to see if we have a broken srom */
1579 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1580 /* pci_vendor_id and subsystem_id are swapped */
1581 ee_data[0] = ee_data[2];
1582 ee_data[1] = ee_data[3];
1586 /* HSC-PCI boards need to be byte-swaped and shifted
1587 * up 1 word. This shift needs to happen at the end
1588 * of the MAC first because of the 2 byte overlap.
1590 for (i = 4; i >= 0; i -= 2) {
1591 ee_data[17 + i + 3] = ee_data[17 + i];
1592 ee_data[16 + i + 5] = ee_data[16 + i];
1597 for (i = 0; i < 6; i ++) {
1598 dev->dev_addr[i] = ee_data[i + sa_offset];
1599 sum += ee_data[i + sa_offset];
1602 /* Lite-On boards have the address byte-swapped. */
1603 if ((dev->dev_addr[0] == 0xA0 ||
1604 dev->dev_addr[0] == 0xC0 ||
1605 dev->dev_addr[0] == 0x02) &&
1606 dev->dev_addr[1] == 0x00)
1607 for (i = 0; i < 6; i+=2) {
1608 char tmp = dev->dev_addr[i];
1609 dev->dev_addr[i] = dev->dev_addr[i+1];
1610 dev->dev_addr[i+1] = tmp;
1612 /* On the Zynx 315 Etherarray and other multiport boards only the
1613 first Tulip has an EEPROM.
1614 On Sparc systems the mac address is held in the OBP property
1615 "local-mac-address".
1616 The addresses of the subsequent ports are derived from the first.
1617 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1618 that here as well. */
1619 if (sum == 0 || sum == 6*0xff) {
1620 #if defined(CONFIG_SPARC)
1621 struct device_node *dp = pci_device_to_OF_node(pdev);
1622 const unsigned char *addr;
1626 for (i = 0; i < 5; i++)
1627 dev->dev_addr[i] = last_phys_addr[i];
1628 dev->dev_addr[i] = last_phys_addr[i] + 1;
1629 #if defined(CONFIG_SPARC)
1630 addr = of_get_property(dp, "local-mac-address", &len);
1631 if (addr && len == ETH_ALEN)
1632 memcpy(dev->dev_addr, addr, ETH_ALEN);
1634 #if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1640 for (i = 0; i < 6; i++)
1641 last_phys_addr[i] = dev->dev_addr[i];
1644 /* The lower four bits are the media type. */
1645 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1646 if (options[board_idx] & MEDIA_MASK)
1647 tp->default_port = options[board_idx] & MEDIA_MASK;
1648 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1649 tp->full_duplex = 1;
1650 if (mtu[board_idx] > 0)
1651 dev->mtu = mtu[board_idx];
1653 if (dev->mem_start & MEDIA_MASK)
1654 tp->default_port = dev->mem_start & MEDIA_MASK;
1655 if (tp->default_port) {
1656 pr_info(DRV_NAME "%d: Transceiver selection forced to %s\n",
1657 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1659 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1660 tp->full_duplex = 1;
1662 if (tp->full_duplex)
1663 tp->full_duplex_lock = 1;
1665 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1666 static const u16 media2advert[] = {
1667 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200
1669 tp->mii_advertise = media2advert[tp->default_port - 9];
1670 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1673 if (tp->flags & HAS_MEDIA_TABLE) {
1674 sprintf(dev->name, DRV_NAME "%d", board_idx); /* hack */
1675 tulip_parse_eeprom(dev);
1676 strcpy(dev->name, "eth%d"); /* un-hack */
1679 if ((tp->flags & ALWAYS_CHECK_MII) ||
1680 (tp->mtable && tp->mtable->has_mii) ||
1681 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1682 if (tp->mtable && tp->mtable->has_mii) {
1683 for (i = 0; i < tp->mtable->leafcount; i++)
1684 if (tp->mtable->mleaf[i].media == 11) {
1686 tp->saved_if_port = dev->if_port;
1687 tulip_select_media(dev, 2);
1688 dev->if_port = tp->saved_if_port;
1693 /* Find the connected MII xcvrs.
1694 Doing this in open() would allow detecting external xcvrs
1695 later, but takes much time. */
1696 tulip_find_mii (dev, board_idx);
1699 /* The Tulip-specific entries in the device structure. */
1700 dev->netdev_ops = &tulip_netdev_ops;
1701 dev->watchdog_timeo = TX_TIMEOUT;
1702 #ifdef CONFIG_TULIP_NAPI
1703 netif_napi_add(dev, &tp->napi, tulip_poll, 16);
1705 dev->ethtool_ops = &ops;
1707 if (register_netdev(dev))
1708 goto err_out_free_ring;
1710 pci_set_drvdata(pdev, dev);
1713 #ifdef CONFIG_TULIP_MMIO
1714 "%s rev %d at MMIO %#llx,%s %pM, IRQ %d\n",
1716 "%s rev %d at Port %#llx,%s %pM, IRQ %d\n",
1718 chip_name, pdev->revision,
1719 (unsigned long long)pci_resource_start(pdev, TULIP_BAR),
1720 eeprom_missing ? " EEPROM not present," : "",
1721 dev->dev_addr, irq);
1723 if (tp->chip_id == PNIC2)
1724 tp->link_change = pnic2_lnk_change;
1725 else if (tp->flags & HAS_NWAY)
1726 tp->link_change = t21142_lnk_change;
1727 else if (tp->flags & HAS_PNICNWAY)
1728 tp->link_change = pnic_lnk_change;
1730 /* Reset the xcvr interface and turn on heartbeat. */
1736 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1739 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1740 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1741 iowrite32(0x0000, ioaddr + CSR13);
1742 iowrite32(0x0000, ioaddr + CSR14);
1743 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1745 t21142_start_nway(dev);
1748 /* just do a reset for sanity sake */
1749 iowrite32(0x0000, ioaddr + CSR13);
1750 iowrite32(0x0000, ioaddr + CSR14);
1753 if ( ! tp->mii_cnt) {
1756 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1757 iowrite32(0x30, ioaddr + CSR12);
1758 iowrite32(0x0001F078, ioaddr + CSR6);
1759 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1764 iowrite32(0x00000000, ioaddr + CSR6);
1765 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1766 iowrite32(0x00000001, ioaddr + CSR13);
1770 iowrite32(0x01a80000, ioaddr + CSR6);
1771 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1772 iowrite32(0x00001000, ioaddr + CSR12);
1775 /* No initialization necessary. */
1779 /* put the chip in snooze mode until opened */
1780 tulip_set_power_state (tp, 0, 1);
1785 pci_free_consistent (pdev,
1786 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1787 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1788 tp->rx_ring, tp->rx_ring_dma);
1792 pci_iounmap(pdev, ioaddr);
1795 pci_release_regions (pdev);
1797 err_out_free_netdev:
1803 /* set the registers according to the given wolopts */
1804 static void tulip_set_wolopts (struct pci_dev *pdev, u32 wolopts)
1806 struct net_device *dev = pci_get_drvdata(pdev);
1807 struct tulip_private *tp = netdev_priv(dev);
1808 void __iomem *ioaddr = tp->base_addr;
1810 if (tp->flags & COMET_PM) {
1814 tmp = ioread32(ioaddr + CSR18);
1815 tmp &= ~(comet_csr18_pmes_sticky | comet_csr18_apm_mode | comet_csr18_d3a);
1816 tmp |= comet_csr18_pm_mode;
1817 iowrite32(tmp, ioaddr + CSR18);
1819 /* Set the Wake-up Control/Status Register to the given WOL options*/
1820 tmp = ioread32(ioaddr + CSR13);
1821 tmp &= ~(comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_wfre | comet_csr13_lsce | comet_csr13_mpre);
1822 if (wolopts & WAKE_MAGIC)
1823 tmp |= comet_csr13_mpre;
1824 if (wolopts & WAKE_PHY)
1825 tmp |= comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_lsce;
1826 /* Clear the event flags */
1827 tmp |= comet_csr13_wfr | comet_csr13_mpr | comet_csr13_lsc;
1828 iowrite32(tmp, ioaddr + CSR13);
1835 static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1838 struct net_device *dev = pci_get_drvdata(pdev);
1839 struct tulip_private *tp = netdev_priv(dev);
1844 if (!netif_running(dev))
1849 netif_device_detach(dev);
1850 /* FIXME: it needlessly adds an error path. */
1851 free_irq(tp->pdev->irq, dev);
1854 pci_save_state(pdev);
1855 pci_disable_device(pdev);
1856 pstate = pci_choose_state(pdev, state);
1857 if (state.event == PM_EVENT_SUSPEND && pstate != PCI_D0) {
1860 tulip_set_wolopts(pdev, tp->wolinfo.wolopts);
1861 rc = pci_enable_wake(pdev, pstate, tp->wolinfo.wolopts);
1863 pr_err("pci_enable_wake failed (%d)\n", rc);
1865 pci_set_power_state(pdev, pstate);
1871 static int tulip_resume(struct pci_dev *pdev)
1873 struct net_device *dev = pci_get_drvdata(pdev);
1874 struct tulip_private *tp = netdev_priv(dev);
1875 void __iomem *ioaddr = tp->base_addr;
1882 pci_set_power_state(pdev, PCI_D0);
1883 pci_restore_state(pdev);
1885 if (!netif_running(dev))
1888 if ((retval = pci_enable_device(pdev))) {
1889 pr_err("pci_enable_device failed in resume\n");
1893 retval = request_irq(pdev->irq, tulip_interrupt, IRQF_SHARED,
1896 pr_err("request_irq failed in resume\n");
1900 if (tp->flags & COMET_PM) {
1901 pci_enable_wake(pdev, PCI_D3hot, 0);
1902 pci_enable_wake(pdev, PCI_D3cold, 0);
1904 /* Clear the PMES flag */
1905 tmp = ioread32(ioaddr + CSR20);
1906 tmp |= comet_csr20_pmes;
1907 iowrite32(tmp, ioaddr + CSR20);
1909 /* Disable all wake-up events */
1910 tulip_set_wolopts(pdev, 0);
1912 netif_device_attach(dev);
1914 if (netif_running(dev))
1920 #endif /* CONFIG_PM */
1923 static void tulip_remove_one(struct pci_dev *pdev)
1925 struct net_device *dev = pci_get_drvdata (pdev);
1926 struct tulip_private *tp;
1931 tp = netdev_priv(dev);
1932 unregister_netdev(dev);
1933 pci_free_consistent (pdev,
1934 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1935 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1936 tp->rx_ring, tp->rx_ring_dma);
1938 pci_iounmap(pdev, tp->base_addr);
1940 pci_release_regions (pdev);
1941 pci_disable_device(pdev);
1943 /* pci_power_off (pdev, -1); */
1946 #ifdef CONFIG_NET_POLL_CONTROLLER
1948 * Polling 'interrupt' - used by things like netconsole to send skbs
1949 * without having to re-enable interrupts. It's not called while
1950 * the interrupt routine is executing.
1953 static void poll_tulip (struct net_device *dev)
1955 struct tulip_private *tp = netdev_priv(dev);
1956 const int irq = tp->pdev->irq;
1958 /* disable_irq here is not very nice, but with the lockless
1959 interrupt handler we have no other choice. */
1961 tulip_interrupt (irq, dev);
1966 static struct pci_driver tulip_driver = {
1968 .id_table = tulip_pci_tbl,
1969 .probe = tulip_init_one,
1970 .remove = tulip_remove_one,
1972 .suspend = tulip_suspend,
1973 .resume = tulip_resume,
1974 #endif /* CONFIG_PM */
1978 static int __init tulip_init (void)
1981 pr_info("%s", version);
1985 pr_warn("tulip: unknown CPU architecture, using default csr0\n");
1986 /* default to 8 longword cache line alignment */
1987 csr0 = 0x00A00000 | 0x4800;
1990 /* copy module parms into globals */
1991 tulip_rx_copybreak = rx_copybreak;
1992 tulip_max_interrupt_work = max_interrupt_work;
1994 /* probe for and init boards */
1995 return pci_register_driver(&tulip_driver);
1999 static void __exit tulip_cleanup (void)
2001 pci_unregister_driver (&tulip_driver);
2005 module_init(tulip_init);
2006 module_exit(tulip_cleanup);