1 /* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux.
3 Copyright 2000,2001 The Linux Kernel Team
4 Written/copyright 1994-2001 by Donald Becker.
6 This software may be used and distributed according to the terms
7 of the GNU General Public License, incorporated herein by reference.
9 Please submit bugs to http://bugzilla.kernel.org/ .
12 #define pr_fmt(fmt) "tulip: " fmt
14 #define DRV_NAME "tulip"
15 #ifdef CONFIG_TULIP_NAPI
16 #define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */
18 #define DRV_VERSION "1.1.15"
20 #define DRV_RELDATE "Feb 27, 2007"
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/etherdevice.h>
30 #include <linux/delay.h>
31 #include <linux/mii.h>
32 #include <linux/crc32.h>
33 #include <asm/unaligned.h>
34 #include <linux/uaccess.h>
40 static char version[] =
41 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
43 /* A few user-configurable values. */
45 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
46 static unsigned int max_interrupt_work = 25;
49 /* Used to pass the full-duplex flag, etc. */
50 static int full_duplex[MAX_UNITS];
51 static int options[MAX_UNITS];
52 static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
54 /* The possible media types that can be set in options[] are: */
55 const char * const medianame[32] = {
56 "10baseT", "10base2", "AUI", "100baseTx",
57 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
58 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
59 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
60 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
61 "","","","", "","","","", "","","","Transceiver reset",
64 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
65 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
66 defined(CONFIG_SPARC) || defined(__ia64__) || \
67 defined(__sh__) || defined(__mips__)
68 static int rx_copybreak = 1518;
70 static int rx_copybreak = 100;
74 Set the bus performance register.
75 Typical: Set 16 longword cache alignment, no burst limit.
76 Cache alignment bits 15:14 Burst length 13:8
77 0000 No alignment 0x00000000 unlimited 0800 8 longwords
78 4000 8 longwords 0100 1 longword 1000 16 longwords
79 8000 16 longwords 0200 2 longwords 2000 32 longwords
80 C000 32 longwords 0400 4 longwords
81 Warning: many older 486 systems are broken and require setting 0x00A04800
82 8 longword cache alignment, 8 longword burst.
83 ToDo: Non-Intel setting could be better.
86 #if defined(__alpha__) || defined(__ia64__)
87 static int csr0 = 0x01A00000 | 0xE000;
88 #elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
89 static int csr0 = 0x01A00000 | 0x8000;
90 #elif defined(CONFIG_SPARC) || defined(__hppa__)
91 /* The UltraSparc PCI controllers will disconnect at every 64-byte
92 * crossing anyways so it makes no sense to tell Tulip to burst
95 static int csr0 = 0x01A00000 | 0x9000;
96 #elif defined(__arm__) || defined(__sh__)
97 static int csr0 = 0x01A00000 | 0x4800;
98 #elif defined(__mips__)
99 static int csr0 = 0x00200000 | 0x4000;
104 /* Operational parameters that usually are not changed. */
105 /* Time in jiffies before concluding the transmitter is hung. */
106 #define TX_TIMEOUT (4*HZ)
109 MODULE_AUTHOR("The Linux Kernel Team");
110 MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
111 MODULE_LICENSE("GPL");
112 MODULE_VERSION(DRV_VERSION);
113 module_param(tulip_debug, int, 0);
114 module_param(max_interrupt_work, int, 0);
115 module_param(rx_copybreak, int, 0);
116 module_param(csr0, int, 0);
117 module_param_array(options, int, NULL, 0);
118 module_param_array(full_duplex, int, NULL, 0);
121 int tulip_debug = TULIP_DEBUG;
126 static void tulip_timer(unsigned long data)
128 struct net_device *dev = (struct net_device *)data;
129 struct tulip_private *tp = netdev_priv(dev);
131 if (netif_running(dev))
132 schedule_work(&tp->media_work);
136 * This table use during operation for capabilities and media timer.
138 * It is indexed via the values in 'enum chips'
141 const struct tulip_chip_table tulip_tbl[] = {
142 { }, /* placeholder for array, slot unused currently */
143 { }, /* placeholder for array, slot unused currently */
146 { "Digital DS21140 Tulip", 128, 0x0001ebef,
147 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
150 /* DC21142, DC21143 */
151 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
152 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
153 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
156 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
157 HAS_MII | HAS_PNICNWAY, pnic_timer, },
160 { "Macronix 98713 PMAC", 128, 0x0001ebef,
161 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
164 { "Macronix 98715 PMAC", 256, 0x0001ebef,
165 HAS_MEDIA_TABLE, mxic_timer, },
168 { "Macronix 98725 PMAC", 256, 0x0001ebef,
169 HAS_MEDIA_TABLE, mxic_timer, },
172 { "ASIX AX88140", 128, 0x0001fbff,
173 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
174 | IS_ASIX, tulip_timer, tulip_media_task },
177 { "Lite-On PNIC-II", 256, 0x0801fbff,
178 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
181 { "ADMtek Comet", 256, 0x0001abef,
182 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
185 { "Compex 9881 PMAC", 128, 0x0001ebef,
186 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
189 { "Intel DS21145 Tulip", 128, 0x0801fbff,
190 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
191 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
194 #ifdef CONFIG_TULIP_DM910X
195 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
196 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
197 tulip_timer, tulip_media_task },
203 { "Conexant LANfinity", 256, 0x0001ebef,
204 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
209 static const struct pci_device_id tulip_pci_tbl[] = {
210 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
211 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
212 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
213 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
214 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
215 /* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
216 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
217 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
218 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
219 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
220 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
221 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
222 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
229 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
230 #ifdef CONFIG_TULIP_DM910X
231 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
232 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
234 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
235 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
236 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
237 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
238 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
239 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
240 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
241 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
242 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
244 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
245 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
246 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
247 { 0x1414, 0x0001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Microsoft MN-120 */
248 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
249 { } /* terminate list */
251 MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
254 /* A full-duplex map for media types. */
255 const char tulip_media_cap[32] =
256 {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
258 static void tulip_tx_timeout(struct net_device *dev);
259 static void tulip_init_ring(struct net_device *dev);
260 static void tulip_free_ring(struct net_device *dev);
261 static netdev_tx_t tulip_start_xmit(struct sk_buff *skb,
262 struct net_device *dev);
263 static int tulip_open(struct net_device *dev);
264 static int tulip_close(struct net_device *dev);
265 static void tulip_up(struct net_device *dev);
266 static void tulip_down(struct net_device *dev);
267 static struct net_device_stats *tulip_get_stats(struct net_device *dev);
268 static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
269 static void set_rx_mode(struct net_device *dev);
270 static void tulip_set_wolopts(struct pci_dev *pdev, u32 wolopts);
271 #ifdef CONFIG_NET_POLL_CONTROLLER
272 static void poll_tulip(struct net_device *dev);
275 static void tulip_set_power_state (struct tulip_private *tp,
276 int sleep, int snooze)
278 if (tp->flags & HAS_ACPI) {
280 pci_read_config_dword (tp->pdev, CFDD, &tmp);
281 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
283 newtmp |= CFDD_Sleep;
285 newtmp |= CFDD_Snooze;
287 pci_write_config_dword (tp->pdev, CFDD, newtmp);
293 static void tulip_up(struct net_device *dev)
295 struct tulip_private *tp = netdev_priv(dev);
296 void __iomem *ioaddr = tp->base_addr;
297 int next_tick = 3*HZ;
301 #ifdef CONFIG_TULIP_NAPI
302 napi_enable(&tp->napi);
305 /* Wake the chip from sleep/snooze mode. */
306 tulip_set_power_state (tp, 0, 0);
308 /* Disable all WOL events */
309 pci_enable_wake(tp->pdev, PCI_D3hot, 0);
310 pci_enable_wake(tp->pdev, PCI_D3cold, 0);
311 tulip_set_wolopts(tp->pdev, 0);
313 /* On some chip revs we must set the MII/SYM port before the reset!? */
314 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
315 iowrite32(0x00040000, ioaddr + CSR6);
317 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
318 iowrite32(0x00000001, ioaddr + CSR0);
319 pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */
323 Wait the specified 50 PCI cycles after a reset by initializing
324 Tx and Rx queues and the address filter list. */
325 iowrite32(tp->csr0, ioaddr + CSR0);
326 pci_read_config_dword(tp->pdev, PCI_COMMAND, ®); /* flush write */
330 netdev_dbg(dev, "tulip_up(), irq==%d\n", tp->pdev->irq);
332 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
333 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
334 tp->cur_rx = tp->cur_tx = 0;
335 tp->dirty_rx = tp->dirty_tx = 0;
337 if (tp->flags & MC_HASH_ONLY) {
338 u32 addr_low = get_unaligned_le32(dev->dev_addr);
339 u32 addr_high = get_unaligned_le16(dev->dev_addr + 4);
340 if (tp->chip_id == AX88140) {
341 iowrite32(0, ioaddr + CSR13);
342 iowrite32(addr_low, ioaddr + CSR14);
343 iowrite32(1, ioaddr + CSR13);
344 iowrite32(addr_high, ioaddr + CSR14);
345 } else if (tp->flags & COMET_MAC_ADDR) {
346 iowrite32(addr_low, ioaddr + 0xA4);
347 iowrite32(addr_high, ioaddr + 0xA8);
348 iowrite32(0, ioaddr + CSR27);
349 iowrite32(0, ioaddr + CSR28);
352 /* This is set_rx_mode(), but without starting the transmitter. */
353 u16 *eaddrs = (u16 *)dev->dev_addr;
354 u16 *setup_frm = &tp->setup_frame[15*6];
357 /* 21140 bug: you must add the broadcast address. */
358 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
359 /* Fill the final entry of the table with our physical address. */
360 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
361 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
362 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
364 mapping = pci_map_single(tp->pdev, tp->setup_frame,
365 sizeof(tp->setup_frame),
367 tp->tx_buffers[tp->cur_tx].skb = NULL;
368 tp->tx_buffers[tp->cur_tx].mapping = mapping;
370 /* Put the setup frame on the Tx list. */
371 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
372 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
373 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
378 tp->saved_if_port = dev->if_port;
379 if (dev->if_port == 0)
380 dev->if_port = tp->default_port;
382 /* Allow selecting a default media. */
384 if (tp->mtable == NULL)
387 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
388 (dev->if_port == 12 ? 0 : dev->if_port);
389 for (i = 0; i < tp->mtable->leafcount; i++)
390 if (tp->mtable->mleaf[i].media == looking_for) {
392 "Using user-specified media %s\n",
393 medianame[dev->if_port]);
397 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
398 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
399 for (i = 0; i < tp->mtable->leafcount; i++)
400 if (tp->mtable->mleaf[i].media == looking_for) {
402 "Using EEPROM-set media %s\n",
403 medianame[looking_for]);
407 /* Start sensing first non-full-duplex media. */
408 for (i = tp->mtable->leafcount - 1;
409 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
418 if (tp->chip_id == DC21143 &&
419 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
420 /* We must reset the media CSRs when we force-select MII mode. */
421 iowrite32(0x0000, ioaddr + CSR13);
422 iowrite32(0x0000, ioaddr + CSR14);
423 iowrite32(0x0008, ioaddr + CSR15);
425 tulip_select_media(dev, 1);
426 } else if (tp->chip_id == DC21142) {
428 tulip_select_media(dev, 1);
431 "Using MII transceiver %d, status %04x\n",
433 tulip_mdio_read(dev, tp->phys[0], 1));
434 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
435 tp->csr6 = csr6_mask_hdcap;
437 iowrite32(0x0000, ioaddr + CSR13);
438 iowrite32(0x0000, ioaddr + CSR14);
440 t21142_start_nway(dev);
441 } else if (tp->chip_id == PNIC2) {
442 /* for initial startup advertise 10/100 Full and Half */
443 tp->sym_advertise = 0x01E0;
444 /* enable autonegotiate end interrupt */
445 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
446 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
447 pnic2_start_nway(dev);
448 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
451 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
452 iowrite32(0x0001, ioaddr + CSR15);
453 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
456 /* Start with 10mbps to do autonegotiation. */
457 iowrite32(0x32, ioaddr + CSR12);
458 tp->csr6 = 0x00420000;
459 iowrite32(0x0001B078, ioaddr + 0xB8);
460 iowrite32(0x0201B078, ioaddr + 0xB8);
463 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881) &&
466 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
467 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
468 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
469 /* Provided by BOLO, Macronix - 12/10/1998. */
471 tp->csr6 = 0x01a80200;
472 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
473 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
474 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
475 /* Enable automatic Tx underrun recovery. */
476 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
477 dev->if_port = tp->mii_cnt ? 11 : 0;
478 tp->csr6 = 0x00040000;
479 } else if (tp->chip_id == AX88140) {
480 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
482 tulip_select_media(dev, 1);
484 /* Start the chip's Tx to process setup frame. */
488 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
490 /* Enable interrupts by setting the interrupt mask. */
491 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
492 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
493 tulip_start_rxtx(tp);
494 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
496 if (tulip_debug > 2) {
497 netdev_dbg(dev, "Done tulip_up(), CSR0 %08x, CSR5 %08x CSR6 %08x\n",
498 ioread32(ioaddr + CSR0),
499 ioread32(ioaddr + CSR5),
500 ioread32(ioaddr + CSR6));
503 /* Set the timer to switch to check for link beat and perhaps switch
504 to an alternate media type. */
505 tp->timer.expires = RUN_AT(next_tick);
506 add_timer(&tp->timer);
507 #ifdef CONFIG_TULIP_NAPI
508 setup_timer(&tp->oom_timer, oom_timer, (unsigned long)dev);
513 tulip_open(struct net_device *dev)
515 struct tulip_private *tp = netdev_priv(dev);
518 tulip_init_ring (dev);
520 retval = request_irq(tp->pdev->irq, tulip_interrupt, IRQF_SHARED,
527 netif_start_queue (dev);
532 tulip_free_ring (dev);
537 static void tulip_tx_timeout(struct net_device *dev)
539 struct tulip_private *tp = netdev_priv(dev);
540 void __iomem *ioaddr = tp->base_addr;
543 spin_lock_irqsave (&tp->lock, flags);
545 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
546 /* Do nothing -- the media monitor should handle this. */
549 "Transmit timeout using MII device\n");
550 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142 ||
551 tp->chip_id == MX98713 || tp->chip_id == COMPEX9881 ||
552 tp->chip_id == DM910X) {
554 "21140 transmit timed out, status %08x, SIA %08x %08x %08x %08x, resetting...\n",
555 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
556 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14),
557 ioread32(ioaddr + CSR15));
558 tp->timeout_recovery = 1;
559 schedule_work(&tp->media_work);
561 } else if (tp->chip_id == PNIC2) {
563 "PNIC2 transmit timed out, status %08x, CSR6/7 %08x / %08x CSR12 %08x, resetting...\n",
564 (int)ioread32(ioaddr + CSR5),
565 (int)ioread32(ioaddr + CSR6),
566 (int)ioread32(ioaddr + CSR7),
567 (int)ioread32(ioaddr + CSR12));
570 "Transmit timed out, status %08x, CSR12 %08x, resetting...\n",
571 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
575 #if defined(way_too_many_messages)
576 if (tulip_debug > 3) {
578 for (i = 0; i < RX_RING_SIZE; i++) {
579 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
582 "%2d: %08x %08x %08x %08x %02x %02x %02x\n",
584 (unsigned int)tp->rx_ring[i].status,
585 (unsigned int)tp->rx_ring[i].length,
586 (unsigned int)tp->rx_ring[i].buffer1,
587 (unsigned int)tp->rx_ring[i].buffer2,
588 buf[0], buf[1], buf[2]);
589 for (j = 0; ((j < 1600) && buf[j] != 0xee); j++)
591 pr_cont(" %02x", buf[j]);
592 pr_cont(" j=%d\n", j);
594 printk(KERN_DEBUG " Rx ring %p: ", tp->rx_ring);
595 for (i = 0; i < RX_RING_SIZE; i++)
596 pr_cont(" %08x", (unsigned int)tp->rx_ring[i].status);
597 printk(KERN_DEBUG " Tx ring %p: ", tp->tx_ring);
598 for (i = 0; i < TX_RING_SIZE; i++)
599 pr_cont(" %08x", (unsigned int)tp->tx_ring[i].status);
604 tulip_tx_timeout_complete(tp, ioaddr);
607 spin_unlock_irqrestore (&tp->lock, flags);
608 netif_trans_update(dev); /* prevent tx timeout */
609 netif_wake_queue (dev);
613 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
614 static void tulip_init_ring(struct net_device *dev)
616 struct tulip_private *tp = netdev_priv(dev);
623 for (i = 0; i < RX_RING_SIZE; i++) {
624 tp->rx_ring[i].status = 0x00000000;
625 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
626 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
627 tp->rx_buffers[i].skb = NULL;
628 tp->rx_buffers[i].mapping = 0;
630 /* Mark the last entry as wrapping the ring. */
631 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
632 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
634 for (i = 0; i < RX_RING_SIZE; i++) {
637 /* Note the receive buffer must be longword aligned.
638 netdev_alloc_skb() provides 16 byte alignment. But do *not*
639 use skb_reserve() to align the IP header! */
640 struct sk_buff *skb = netdev_alloc_skb(dev, PKT_BUF_SZ);
641 tp->rx_buffers[i].skb = skb;
644 mapping = pci_map_single(tp->pdev, skb->data,
645 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
646 tp->rx_buffers[i].mapping = mapping;
647 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
648 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
650 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
652 /* The Tx buffer descriptor is filled in as needed, but we
653 do need to clear the ownership bit. */
654 for (i = 0; i < TX_RING_SIZE; i++) {
655 tp->tx_buffers[i].skb = NULL;
656 tp->tx_buffers[i].mapping = 0;
657 tp->tx_ring[i].status = 0x00000000;
658 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
660 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
664 tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
666 struct tulip_private *tp = netdev_priv(dev);
672 spin_lock_irqsave(&tp->lock, flags);
674 /* Calculate the next Tx descriptor entry. */
675 entry = tp->cur_tx % TX_RING_SIZE;
677 tp->tx_buffers[entry].skb = skb;
678 mapping = pci_map_single(tp->pdev, skb->data,
679 skb->len, PCI_DMA_TODEVICE);
680 tp->tx_buffers[entry].mapping = mapping;
681 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
683 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
684 flag = 0x60000000; /* No interrupt */
685 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
686 flag = 0xe0000000; /* Tx-done intr. */
687 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
688 flag = 0x60000000; /* No Tx-done intr. */
689 } else { /* Leave room for set_rx_mode() to fill entries. */
690 flag = 0xe0000000; /* Tx-done intr. */
691 netif_stop_queue(dev);
693 if (entry == TX_RING_SIZE-1)
694 flag = 0xe0000000 | DESC_RING_WRAP;
696 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
697 /* if we were using Transmit Automatic Polling, we would need a
699 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
704 /* Trigger an immediate transmit demand. */
705 iowrite32(0, tp->base_addr + CSR1);
707 spin_unlock_irqrestore(&tp->lock, flags);
712 static void tulip_clean_tx_ring(struct tulip_private *tp)
714 unsigned int dirty_tx;
716 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
718 int entry = dirty_tx % TX_RING_SIZE;
719 int status = le32_to_cpu(tp->tx_ring[entry].status);
722 tp->dev->stats.tx_errors++; /* It wasn't Txed */
723 tp->tx_ring[entry].status = 0;
726 /* Check for Tx filter setup frames. */
727 if (tp->tx_buffers[entry].skb == NULL) {
728 /* test because dummy frames not mapped */
729 if (tp->tx_buffers[entry].mapping)
730 pci_unmap_single(tp->pdev,
731 tp->tx_buffers[entry].mapping,
732 sizeof(tp->setup_frame),
737 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
738 tp->tx_buffers[entry].skb->len,
741 /* Free the original skb. */
742 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
743 tp->tx_buffers[entry].skb = NULL;
744 tp->tx_buffers[entry].mapping = 0;
748 static void tulip_down (struct net_device *dev)
750 struct tulip_private *tp = netdev_priv(dev);
751 void __iomem *ioaddr = tp->base_addr;
754 cancel_work_sync(&tp->media_work);
756 #ifdef CONFIG_TULIP_NAPI
757 napi_disable(&tp->napi);
760 del_timer_sync (&tp->timer);
761 #ifdef CONFIG_TULIP_NAPI
762 del_timer_sync (&tp->oom_timer);
764 spin_lock_irqsave (&tp->lock, flags);
766 /* Disable interrupts by clearing the interrupt mask. */
767 iowrite32 (0x00000000, ioaddr + CSR7);
769 /* Stop the Tx and Rx processes. */
772 /* prepare receive buffers */
773 tulip_refill_rx(dev);
775 /* release any unconsumed transmit buffers */
776 tulip_clean_tx_ring(tp);
778 if (ioread32(ioaddr + CSR6) != 0xffffffff)
779 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
781 spin_unlock_irqrestore (&tp->lock, flags);
783 setup_timer(&tp->timer, tulip_tbl[tp->chip_id].media_timer,
786 dev->if_port = tp->saved_if_port;
788 /* Leave the driver in snooze, not sleep, mode. */
789 tulip_set_power_state (tp, 0, 1);
792 static void tulip_free_ring (struct net_device *dev)
794 struct tulip_private *tp = netdev_priv(dev);
797 /* Free all the skbuffs in the Rx queue. */
798 for (i = 0; i < RX_RING_SIZE; i++) {
799 struct sk_buff *skb = tp->rx_buffers[i].skb;
800 dma_addr_t mapping = tp->rx_buffers[i].mapping;
802 tp->rx_buffers[i].skb = NULL;
803 tp->rx_buffers[i].mapping = 0;
805 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
806 tp->rx_ring[i].length = 0;
807 /* An invalid address. */
808 tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0);
810 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
816 for (i = 0; i < TX_RING_SIZE; i++) {
817 struct sk_buff *skb = tp->tx_buffers[i].skb;
820 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
821 skb->len, PCI_DMA_TODEVICE);
824 tp->tx_buffers[i].skb = NULL;
825 tp->tx_buffers[i].mapping = 0;
829 static int tulip_close (struct net_device *dev)
831 struct tulip_private *tp = netdev_priv(dev);
832 void __iomem *ioaddr = tp->base_addr;
834 netif_stop_queue (dev);
839 netdev_dbg(dev, "Shutting down ethercard, status was %02x\n",
840 ioread32 (ioaddr + CSR5));
842 free_irq (tp->pdev->irq, dev);
844 tulip_free_ring (dev);
849 static struct net_device_stats *tulip_get_stats(struct net_device *dev)
851 struct tulip_private *tp = netdev_priv(dev);
852 void __iomem *ioaddr = tp->base_addr;
854 if (netif_running(dev)) {
857 spin_lock_irqsave (&tp->lock, flags);
859 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
861 spin_unlock_irqrestore(&tp->lock, flags);
868 static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
870 struct tulip_private *np = netdev_priv(dev);
871 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
872 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
873 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
877 static int tulip_ethtool_set_wol(struct net_device *dev,
878 struct ethtool_wolinfo *wolinfo)
880 struct tulip_private *tp = netdev_priv(dev);
882 if (wolinfo->wolopts & (~tp->wolinfo.supported))
885 tp->wolinfo.wolopts = wolinfo->wolopts;
886 device_set_wakeup_enable(&tp->pdev->dev, tp->wolinfo.wolopts);
890 static void tulip_ethtool_get_wol(struct net_device *dev,
891 struct ethtool_wolinfo *wolinfo)
893 struct tulip_private *tp = netdev_priv(dev);
895 wolinfo->supported = tp->wolinfo.supported;
896 wolinfo->wolopts = tp->wolinfo.wolopts;
901 static const struct ethtool_ops ops = {
902 .get_drvinfo = tulip_get_drvinfo,
903 .set_wol = tulip_ethtool_set_wol,
904 .get_wol = tulip_ethtool_get_wol,
907 /* Provide ioctl() calls to examine the MII xcvr state. */
908 static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
910 struct tulip_private *tp = netdev_priv(dev);
911 void __iomem *ioaddr = tp->base_addr;
912 struct mii_ioctl_data *data = if_mii(rq);
913 const unsigned int phy_idx = 0;
914 int phy = tp->phys[phy_idx] & 0x1f;
915 unsigned int regnum = data->reg_num;
918 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
921 else if (tp->flags & HAS_NWAY)
923 else if (tp->chip_id == COMET)
928 case SIOCGMIIREG: /* Read MII PHY register. */
929 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
930 int csr12 = ioread32 (ioaddr + CSR12);
931 int csr14 = ioread32 (ioaddr + CSR14);
934 if (((csr14<<5) & 0x1000) ||
935 (dev->if_port == 5 && tp->nwayset))
936 data->val_out = 0x1000;
938 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
939 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
944 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
945 ((csr12&0x06) == 6 ? 0 : 4);
946 data->val_out |= 0x6048;
949 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
951 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
952 ((csr14 >> 1) & 0x20) + 1;
953 data->val_out |= ((csr14 >> 9) & 0x03C0);
955 case 5: data->val_out = tp->lpar; break;
956 default: data->val_out = 0; break;
959 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
963 case SIOCSMIIREG: /* Write MII PHY register. */
966 if (data->phy_id == phy) {
967 u16 value = data->val_in;
969 case 0: /* Check for autonegotiation on or reset. */
970 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
971 if (tp->full_duplex_lock)
972 tp->full_duplex = (value & 0x0100) ? 1 : 0;
975 tp->advertising[phy_idx] =
976 tp->mii_advertise = data->val_in;
980 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
981 u16 value = data->val_in;
983 if ((value & 0x1200) == 0x1200) {
984 if (tp->chip_id == PNIC2) {
985 pnic2_start_nway (dev);
987 t21142_start_nway (dev);
990 } else if (regnum == 4)
991 tp->sym_advertise = value;
993 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
1004 /* Set or clear the multicast filter for this adaptor.
1005 Note that we only use exclusion around actually queueing the
1006 new frame, not around filling tp->setup_frame. This is non-deterministic
1007 when re-entered but still correct. */
1009 static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
1011 struct tulip_private *tp = netdev_priv(dev);
1013 struct netdev_hw_addr *ha;
1017 memset(hash_table, 0, sizeof(hash_table));
1018 __set_bit_le(255, hash_table); /* Broadcast entry */
1019 /* This should work on big-endian machines as well. */
1020 netdev_for_each_mc_addr(ha, dev) {
1021 int index = ether_crc_le(ETH_ALEN, ha->addr) & 0x1ff;
1023 __set_bit_le(index, hash_table);
1025 for (i = 0; i < 32; i++) {
1026 *setup_frm++ = hash_table[i];
1027 *setup_frm++ = hash_table[i];
1029 setup_frm = &tp->setup_frame[13*6];
1031 /* Fill the final entry with our physical address. */
1032 eaddrs = (u16 *)dev->dev_addr;
1033 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1034 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1035 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1038 static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
1040 struct tulip_private *tp = netdev_priv(dev);
1041 struct netdev_hw_addr *ha;
1044 /* We have <= 14 addresses so we can use the wonderful
1045 16 address perfect filtering of the Tulip. */
1046 netdev_for_each_mc_addr(ha, dev) {
1047 eaddrs = (u16 *) ha->addr;
1048 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1049 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1050 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1052 /* Fill the unused entries with the broadcast address. */
1053 memset(setup_frm, 0xff, (15 - netdev_mc_count(dev)) * 12);
1054 setup_frm = &tp->setup_frame[15*6];
1056 /* Fill the final entry with our physical address. */
1057 eaddrs = (u16 *)dev->dev_addr;
1058 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1059 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1060 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1064 static void set_rx_mode(struct net_device *dev)
1066 struct tulip_private *tp = netdev_priv(dev);
1067 void __iomem *ioaddr = tp->base_addr;
1070 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1072 tp->csr6 &= ~0x00D5;
1073 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1074 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1075 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1076 } else if ((netdev_mc_count(dev) > 1000) ||
1077 (dev->flags & IFF_ALLMULTI)) {
1078 /* Too many to filter well -- accept all multicasts. */
1079 tp->csr6 |= AcceptAllMulticast;
1080 csr6 |= AcceptAllMulticast;
1081 } else if (tp->flags & MC_HASH_ONLY) {
1082 /* Some work-alikes have only a 64-entry hash filter table. */
1083 /* Should verify correctness on big-endian/__powerpc__ */
1084 struct netdev_hw_addr *ha;
1085 if (netdev_mc_count(dev) > 64) {
1086 /* Arbitrary non-effective limit. */
1087 tp->csr6 |= AcceptAllMulticast;
1088 csr6 |= AcceptAllMulticast;
1090 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1092 netdev_for_each_mc_addr(ha, dev) {
1093 if (tp->flags & COMET_MAC_ADDR)
1094 filterbit = ether_crc_le(ETH_ALEN,
1097 filterbit = ether_crc(ETH_ALEN,
1100 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1101 if (tulip_debug > 2)
1103 "Added filter for %pM %08x bit %d\n",
1105 ether_crc(ETH_ALEN, ha->addr),
1108 if (mc_filter[0] == tp->mc_filter[0] &&
1109 mc_filter[1] == tp->mc_filter[1])
1111 else if (tp->flags & IS_ASIX) {
1112 iowrite32(2, ioaddr + CSR13);
1113 iowrite32(mc_filter[0], ioaddr + CSR14);
1114 iowrite32(3, ioaddr + CSR13);
1115 iowrite32(mc_filter[1], ioaddr + CSR14);
1116 } else if (tp->flags & COMET_MAC_ADDR) {
1117 iowrite32(mc_filter[0], ioaddr + CSR27);
1118 iowrite32(mc_filter[1], ioaddr + CSR28);
1120 tp->mc_filter[0] = mc_filter[0];
1121 tp->mc_filter[1] = mc_filter[1];
1124 unsigned long flags;
1125 u32 tx_flags = 0x08000000 | 192;
1127 /* Note that only the low-address shortword of setup_frame is valid!
1128 The values are doubled for big-endian architectures. */
1129 if (netdev_mc_count(dev) > 14) {
1130 /* Must use a multicast hash table. */
1131 build_setup_frame_hash(tp->setup_frame, dev);
1132 tx_flags = 0x08400000 | 192;
1134 build_setup_frame_perfect(tp->setup_frame, dev);
1137 spin_lock_irqsave(&tp->lock, flags);
1139 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1140 /* Same setup recently queued, we need not add it. */
1145 /* Now add this frame to the Tx list. */
1147 entry = tp->cur_tx++ % TX_RING_SIZE;
1150 /* Avoid a chip errata by prefixing a dummy entry. */
1151 tp->tx_buffers[entry].skb = NULL;
1152 tp->tx_buffers[entry].mapping = 0;
1153 tp->tx_ring[entry].length =
1154 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1155 tp->tx_ring[entry].buffer1 = 0;
1156 /* Must set DescOwned later to avoid race with chip */
1158 entry = tp->cur_tx++ % TX_RING_SIZE;
1162 tp->tx_buffers[entry].skb = NULL;
1163 tp->tx_buffers[entry].mapping =
1164 pci_map_single(tp->pdev, tp->setup_frame,
1165 sizeof(tp->setup_frame),
1167 /* Put the setup frame on the Tx list. */
1168 if (entry == TX_RING_SIZE-1)
1169 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1170 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1171 tp->tx_ring[entry].buffer1 =
1172 cpu_to_le32(tp->tx_buffers[entry].mapping);
1173 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1175 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1176 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1177 netif_stop_queue(dev);
1179 /* Trigger an immediate transmit demand. */
1180 iowrite32(0, ioaddr + CSR1);
1183 spin_unlock_irqrestore(&tp->lock, flags);
1186 iowrite32(csr6, ioaddr + CSR6);
1189 #ifdef CONFIG_TULIP_MWI
1190 static void tulip_mwi_config(struct pci_dev *pdev, struct net_device *dev)
1192 struct tulip_private *tp = netdev_priv(dev);
1197 if (tulip_debug > 3)
1198 netdev_dbg(dev, "tulip_mwi_config()\n");
1200 tp->csr0 = csr0 = 0;
1202 /* if we have any cache line size at all, we can do MRM and MWI */
1205 /* Enable MWI in the standard PCI command bit.
1206 * Check for the case where MWI is desired but not available
1208 pci_try_set_mwi(pdev);
1210 /* read result from hardware (in case bit refused to enable) */
1211 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1212 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1215 /* if cache line size hardwired to zero, no MWI */
1216 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1217 if ((csr0 & MWI) && (cache == 0)) {
1219 pci_clear_mwi(pdev);
1222 /* assign per-cacheline-size cache alignment and
1223 * burst length values
1227 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1230 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1233 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1240 /* if we have a good cache line size, we by now have a good
1241 * csr0, so save it and exit
1246 /* we don't have a good csr0 or cache line size, disable MWI */
1248 pci_clear_mwi(pdev);
1252 /* sane defaults for burst length and cache alignment
1253 * originally from de4x5 driver
1255 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1259 if (tulip_debug > 2)
1260 netdev_dbg(dev, "MWI config cacheline=%d, csr0=%08x\n",
1266 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1267 * is the DM910X and the on chip ULi devices
1270 static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1272 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1277 static const struct net_device_ops tulip_netdev_ops = {
1278 .ndo_open = tulip_open,
1279 .ndo_start_xmit = tulip_start_xmit,
1280 .ndo_tx_timeout = tulip_tx_timeout,
1281 .ndo_stop = tulip_close,
1282 .ndo_get_stats = tulip_get_stats,
1283 .ndo_do_ioctl = private_ioctl,
1284 .ndo_set_rx_mode = set_rx_mode,
1285 .ndo_set_mac_address = eth_mac_addr,
1286 .ndo_validate_addr = eth_validate_addr,
1287 #ifdef CONFIG_NET_POLL_CONTROLLER
1288 .ndo_poll_controller = poll_tulip,
1292 const struct pci_device_id early_486_chipsets[] = {
1293 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1294 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1298 static int tulip_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1300 struct tulip_private *tp;
1301 /* See note below on the multiport cards. */
1302 static unsigned char last_phys_addr[ETH_ALEN] = {
1303 0x00, 'L', 'i', 'n', 'u', 'x'
1305 static int last_irq;
1308 unsigned char *ee_data;
1309 struct net_device *dev;
1310 void __iomem *ioaddr;
1311 static int board_idx = -1;
1312 int chip_idx = ent->driver_data;
1313 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1314 unsigned int eeprom_missing = 0;
1315 unsigned int force_csr0 = 0;
1318 if (tulip_debug > 0)
1319 printk_once(KERN_INFO "%s", version);
1325 * Lan media wire a tulip chip to a wan interface. Needs a very
1326 * different driver (lmc driver)
1329 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1330 pr_err("skipping LMC card\n");
1332 } else if (pdev->subsystem_vendor == PCI_VENDOR_ID_SBE &&
1333 (pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_T3E3 ||
1334 pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P0 ||
1335 pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P1)) {
1336 pr_err("skipping SBE T3E3 port\n");
1341 * DM910x chips should be handled by the dmfe driver, except
1342 * on-board chips on SPARC systems. Also, early DM9100s need
1343 * software CRC which only the dmfe driver supports.
1346 #ifdef CONFIG_TULIP_DM910X
1347 if (chip_idx == DM910X) {
1348 struct device_node *dp;
1350 if (pdev->vendor == 0x1282 && pdev->device == 0x9100 &&
1351 pdev->revision < 0x30) {
1352 pr_info("skipping early DM9100 with Crc bug (use dmfe)\n");
1356 dp = pci_device_to_OF_node(pdev);
1357 if (!(dp && of_get_property(dp, "local-mac-address", NULL))) {
1358 pr_info("skipping DM910x expansion card (use dmfe)\n");
1365 * Looks for early PCI chipsets where people report hangs
1366 * without the workarounds being on.
1369 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
1370 aligned. Aries might need this too. The Saturn errata are not
1371 pretty reading but thankfully it's an old 486 chipset.
1373 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1377 if (pci_dev_present(early_486_chipsets)) {
1378 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1382 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1383 if (chip_idx == AX88140) {
1384 if ((csr0 & 0x3f00) == 0)
1388 /* PNIC doesn't have MWI/MRL/MRM... */
1389 if (chip_idx == LC82C168)
1390 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1392 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1393 if (tulip_uli_dm_quirk(pdev)) {
1394 csr0 &= ~0x01f100ff;
1395 #if defined(CONFIG_SPARC)
1396 csr0 = (csr0 & ~0xff00) | 0xe000;
1400 * And back to business
1403 i = pci_enable_device(pdev);
1405 pr_err("Cannot enable tulip board #%d, aborting\n", board_idx);
1411 /* alloc_etherdev ensures aligned and zeroed private structures */
1412 dev = alloc_etherdev (sizeof (*tp));
1416 SET_NETDEV_DEV(dev, &pdev->dev);
1417 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
1418 pr_err("%s: I/O region (0x%llx@0x%llx) too small, aborting\n",
1420 (unsigned long long)pci_resource_len (pdev, 0),
1421 (unsigned long long)pci_resource_start (pdev, 0));
1422 goto err_out_free_netdev;
1425 /* grab all resources from both PIO and MMIO regions, as we
1426 * don't want anyone else messing around with our hardware */
1427 if (pci_request_regions (pdev, DRV_NAME))
1428 goto err_out_free_netdev;
1430 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1433 goto err_out_free_res;
1436 * initialize private data structure 'tp'
1437 * it is zeroed and aligned in alloc_etherdev
1439 tp = netdev_priv(dev);
1442 tp->rx_ring = pci_alloc_consistent(pdev,
1443 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1444 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1447 goto err_out_mtable;
1448 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1449 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1451 tp->chip_id = chip_idx;
1452 tp->flags = tulip_tbl[chip_idx].flags;
1454 tp->wolinfo.supported = 0;
1455 tp->wolinfo.wolopts = 0;
1456 /* COMET: Enable power management only for AN983B */
1457 if (chip_idx == COMET ) {
1459 pci_read_config_dword (pdev, 0x80, &sig);
1460 if (sig == 0x09811317) {
1461 tp->flags |= COMET_PM;
1462 tp->wolinfo.supported = WAKE_PHY | WAKE_MAGIC;
1463 pr_info("%s: Enabled WOL support for AN983B\n",
1468 tp->base_addr = ioaddr;
1469 tp->revision = pdev->revision;
1471 spin_lock_init(&tp->lock);
1472 spin_lock_init(&tp->mii_lock);
1473 setup_timer(&tp->timer, tulip_tbl[tp->chip_id].media_timer,
1474 (unsigned long)dev);
1476 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
1478 #ifdef CONFIG_TULIP_MWI
1479 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1480 tulip_mwi_config (pdev, dev);
1483 /* Stop the chip's Tx and Rx processes. */
1484 tulip_stop_rxtx(tp);
1486 pci_set_master(pdev);
1489 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1490 switch (pdev->subsystem_device) {
1499 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1500 chip_name = "GSC DS21140 Tulip";
1505 /* Clear the missed-packet counter. */
1506 ioread32(ioaddr + CSR8);
1508 /* The station address ROM is read byte serially. The register must
1509 be polled, waiting for the value to be read bit serially from the
1512 ee_data = tp->eeprom;
1513 memset(ee_data, 0, sizeof(tp->eeprom));
1515 if (chip_idx == LC82C168) {
1516 for (i = 0; i < 3; i++) {
1517 int value, boguscnt = 100000;
1518 iowrite32(0x600 | i, ioaddr + 0x98);
1520 value = ioread32(ioaddr + CSR9);
1521 } while (value < 0 && --boguscnt > 0);
1522 put_unaligned_le16(value, ((__le16 *)dev->dev_addr) + i);
1523 sum += value & 0xffff;
1525 } else if (chip_idx == COMET) {
1526 /* No need to read the EEPROM. */
1527 put_unaligned_le32(ioread32(ioaddr + 0xA4), dev->dev_addr);
1528 put_unaligned_le16(ioread32(ioaddr + 0xA8), dev->dev_addr + 4);
1529 for (i = 0; i < 6; i ++)
1530 sum += dev->dev_addr[i];
1532 /* A serial EEPROM interface, we read now and sort it out later. */
1534 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1535 int ee_max_addr = ((1 << ee_addr_size) - 1) * sizeof(u16);
1537 if (ee_max_addr > sizeof(tp->eeprom))
1538 ee_max_addr = sizeof(tp->eeprom);
1540 for (i = 0; i < ee_max_addr ; i += sizeof(u16)) {
1541 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1542 ee_data[i] = data & 0xff;
1543 ee_data[i + 1] = data >> 8;
1546 /* DEC now has a specification (see Notes) but early board makers
1547 just put the address in the first EEPROM locations. */
1548 /* This does memcmp(ee_data, ee_data+16, 8) */
1549 for (i = 0; i < 8; i ++)
1550 if (ee_data[i] != ee_data[16+i])
1552 if (chip_idx == CONEXANT) {
1553 /* Check that the tuple type and length is correct. */
1554 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1556 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1558 sa_offset = 2; /* Grrr, damn Matrox boards. */
1560 #ifdef CONFIG_MIPS_COBALT
1561 if ((pdev->bus->number == 0) &&
1562 ((PCI_SLOT(pdev->devfn) == 7) ||
1563 (PCI_SLOT(pdev->devfn) == 12))) {
1564 /* Cobalt MAC address in first EEPROM locations. */
1566 /* Ensure our media table fixup get's applied */
1567 memcpy(ee_data + 16, ee_data, 8);
1571 /* Check to see if we have a broken srom */
1572 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1573 /* pci_vendor_id and subsystem_id are swapped */
1574 ee_data[0] = ee_data[2];
1575 ee_data[1] = ee_data[3];
1579 /* HSC-PCI boards need to be byte-swaped and shifted
1580 * up 1 word. This shift needs to happen at the end
1581 * of the MAC first because of the 2 byte overlap.
1583 for (i = 4; i >= 0; i -= 2) {
1584 ee_data[17 + i + 3] = ee_data[17 + i];
1585 ee_data[16 + i + 5] = ee_data[16 + i];
1590 for (i = 0; i < 6; i ++) {
1591 dev->dev_addr[i] = ee_data[i + sa_offset];
1592 sum += ee_data[i + sa_offset];
1595 /* Lite-On boards have the address byte-swapped. */
1596 if ((dev->dev_addr[0] == 0xA0 ||
1597 dev->dev_addr[0] == 0xC0 ||
1598 dev->dev_addr[0] == 0x02) &&
1599 dev->dev_addr[1] == 0x00)
1600 for (i = 0; i < 6; i+=2) {
1601 char tmp = dev->dev_addr[i];
1602 dev->dev_addr[i] = dev->dev_addr[i+1];
1603 dev->dev_addr[i+1] = tmp;
1605 /* On the Zynx 315 Etherarray and other multiport boards only the
1606 first Tulip has an EEPROM.
1607 On Sparc systems the mac address is held in the OBP property
1608 "local-mac-address".
1609 The addresses of the subsequent ports are derived from the first.
1610 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1611 that here as well. */
1612 if (sum == 0 || sum == 6*0xff) {
1613 #if defined(CONFIG_SPARC)
1614 struct device_node *dp = pci_device_to_OF_node(pdev);
1615 const unsigned char *addr;
1619 for (i = 0; i < 5; i++)
1620 dev->dev_addr[i] = last_phys_addr[i];
1621 dev->dev_addr[i] = last_phys_addr[i] + 1;
1622 #if defined(CONFIG_SPARC)
1623 addr = of_get_property(dp, "local-mac-address", &len);
1624 if (addr && len == ETH_ALEN)
1625 memcpy(dev->dev_addr, addr, ETH_ALEN);
1627 #if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1633 for (i = 0; i < 6; i++)
1634 last_phys_addr[i] = dev->dev_addr[i];
1637 /* The lower four bits are the media type. */
1638 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1639 if (options[board_idx] & MEDIA_MASK)
1640 tp->default_port = options[board_idx] & MEDIA_MASK;
1641 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1642 tp->full_duplex = 1;
1643 if (mtu[board_idx] > 0)
1644 dev->mtu = mtu[board_idx];
1646 if (dev->mem_start & MEDIA_MASK)
1647 tp->default_port = dev->mem_start & MEDIA_MASK;
1648 if (tp->default_port) {
1649 pr_info(DRV_NAME "%d: Transceiver selection forced to %s\n",
1650 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1652 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1653 tp->full_duplex = 1;
1655 if (tp->full_duplex)
1656 tp->full_duplex_lock = 1;
1658 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1659 static const u16 media2advert[] = {
1660 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200
1662 tp->mii_advertise = media2advert[tp->default_port - 9];
1663 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1666 if (tp->flags & HAS_MEDIA_TABLE) {
1667 sprintf(dev->name, DRV_NAME "%d", board_idx); /* hack */
1668 tulip_parse_eeprom(dev);
1669 strcpy(dev->name, "eth%d"); /* un-hack */
1672 if ((tp->flags & ALWAYS_CHECK_MII) ||
1673 (tp->mtable && tp->mtable->has_mii) ||
1674 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1675 if (tp->mtable && tp->mtable->has_mii) {
1676 for (i = 0; i < tp->mtable->leafcount; i++)
1677 if (tp->mtable->mleaf[i].media == 11) {
1679 tp->saved_if_port = dev->if_port;
1680 tulip_select_media(dev, 2);
1681 dev->if_port = tp->saved_if_port;
1686 /* Find the connected MII xcvrs.
1687 Doing this in open() would allow detecting external xcvrs
1688 later, but takes much time. */
1689 tulip_find_mii (dev, board_idx);
1692 /* The Tulip-specific entries in the device structure. */
1693 dev->netdev_ops = &tulip_netdev_ops;
1694 dev->watchdog_timeo = TX_TIMEOUT;
1695 #ifdef CONFIG_TULIP_NAPI
1696 netif_napi_add(dev, &tp->napi, tulip_poll, 16);
1698 dev->ethtool_ops = &ops;
1700 if (register_netdev(dev))
1701 goto err_out_free_ring;
1703 pci_set_drvdata(pdev, dev);
1706 #ifdef CONFIG_TULIP_MMIO
1707 "%s rev %d at MMIO %#llx,%s %pM, IRQ %d\n",
1709 "%s rev %d at Port %#llx,%s %pM, IRQ %d\n",
1711 chip_name, pdev->revision,
1712 (unsigned long long)pci_resource_start(pdev, TULIP_BAR),
1713 eeprom_missing ? " EEPROM not present," : "",
1714 dev->dev_addr, irq);
1716 if (tp->chip_id == PNIC2)
1717 tp->link_change = pnic2_lnk_change;
1718 else if (tp->flags & HAS_NWAY)
1719 tp->link_change = t21142_lnk_change;
1720 else if (tp->flags & HAS_PNICNWAY)
1721 tp->link_change = pnic_lnk_change;
1723 /* Reset the xcvr interface and turn on heartbeat. */
1729 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1732 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1733 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1734 iowrite32(0x0000, ioaddr + CSR13);
1735 iowrite32(0x0000, ioaddr + CSR14);
1736 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1738 t21142_start_nway(dev);
1741 /* just do a reset for sanity sake */
1742 iowrite32(0x0000, ioaddr + CSR13);
1743 iowrite32(0x0000, ioaddr + CSR14);
1746 if ( ! tp->mii_cnt) {
1749 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1750 iowrite32(0x30, ioaddr + CSR12);
1751 iowrite32(0x0001F078, ioaddr + CSR6);
1752 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1757 iowrite32(0x00000000, ioaddr + CSR6);
1758 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1759 iowrite32(0x00000001, ioaddr + CSR13);
1763 iowrite32(0x01a80000, ioaddr + CSR6);
1764 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1765 iowrite32(0x00001000, ioaddr + CSR12);
1768 /* No initialization necessary. */
1772 /* put the chip in snooze mode until opened */
1773 tulip_set_power_state (tp, 0, 1);
1778 pci_free_consistent (pdev,
1779 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1780 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1781 tp->rx_ring, tp->rx_ring_dma);
1785 pci_iounmap(pdev, ioaddr);
1788 pci_release_regions (pdev);
1790 err_out_free_netdev:
1796 /* set the registers according to the given wolopts */
1797 static void tulip_set_wolopts (struct pci_dev *pdev, u32 wolopts)
1799 struct net_device *dev = pci_get_drvdata(pdev);
1800 struct tulip_private *tp = netdev_priv(dev);
1801 void __iomem *ioaddr = tp->base_addr;
1803 if (tp->flags & COMET_PM) {
1807 tmp = ioread32(ioaddr + CSR18);
1808 tmp &= ~(comet_csr18_pmes_sticky | comet_csr18_apm_mode | comet_csr18_d3a);
1809 tmp |= comet_csr18_pm_mode;
1810 iowrite32(tmp, ioaddr + CSR18);
1812 /* Set the Wake-up Control/Status Register to the given WOL options*/
1813 tmp = ioread32(ioaddr + CSR13);
1814 tmp &= ~(comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_wfre | comet_csr13_lsce | comet_csr13_mpre);
1815 if (wolopts & WAKE_MAGIC)
1816 tmp |= comet_csr13_mpre;
1817 if (wolopts & WAKE_PHY)
1818 tmp |= comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_lsce;
1819 /* Clear the event flags */
1820 tmp |= comet_csr13_wfr | comet_csr13_mpr | comet_csr13_lsc;
1821 iowrite32(tmp, ioaddr + CSR13);
1828 static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1831 struct net_device *dev = pci_get_drvdata(pdev);
1832 struct tulip_private *tp = netdev_priv(dev);
1837 if (!netif_running(dev))
1842 netif_device_detach(dev);
1843 /* FIXME: it needlessly adds an error path. */
1844 free_irq(tp->pdev->irq, dev);
1847 pci_save_state(pdev);
1848 pci_disable_device(pdev);
1849 pstate = pci_choose_state(pdev, state);
1850 if (state.event == PM_EVENT_SUSPEND && pstate != PCI_D0) {
1853 tulip_set_wolopts(pdev, tp->wolinfo.wolopts);
1854 rc = pci_enable_wake(pdev, pstate, tp->wolinfo.wolopts);
1856 pr_err("pci_enable_wake failed (%d)\n", rc);
1858 pci_set_power_state(pdev, pstate);
1864 static int tulip_resume(struct pci_dev *pdev)
1866 struct net_device *dev = pci_get_drvdata(pdev);
1867 struct tulip_private *tp = netdev_priv(dev);
1868 void __iomem *ioaddr = tp->base_addr;
1875 pci_set_power_state(pdev, PCI_D0);
1876 pci_restore_state(pdev);
1878 if (!netif_running(dev))
1881 if ((retval = pci_enable_device(pdev))) {
1882 pr_err("pci_enable_device failed in resume\n");
1886 retval = request_irq(pdev->irq, tulip_interrupt, IRQF_SHARED,
1889 pr_err("request_irq failed in resume\n");
1893 if (tp->flags & COMET_PM) {
1894 pci_enable_wake(pdev, PCI_D3hot, 0);
1895 pci_enable_wake(pdev, PCI_D3cold, 0);
1897 /* Clear the PMES flag */
1898 tmp = ioread32(ioaddr + CSR20);
1899 tmp |= comet_csr20_pmes;
1900 iowrite32(tmp, ioaddr + CSR20);
1902 /* Disable all wake-up events */
1903 tulip_set_wolopts(pdev, 0);
1905 netif_device_attach(dev);
1907 if (netif_running(dev))
1913 #endif /* CONFIG_PM */
1916 static void tulip_remove_one(struct pci_dev *pdev)
1918 struct net_device *dev = pci_get_drvdata (pdev);
1919 struct tulip_private *tp;
1924 tp = netdev_priv(dev);
1925 unregister_netdev(dev);
1926 pci_free_consistent (pdev,
1927 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1928 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1929 tp->rx_ring, tp->rx_ring_dma);
1931 pci_iounmap(pdev, tp->base_addr);
1933 pci_release_regions (pdev);
1934 pci_disable_device(pdev);
1936 /* pci_power_off (pdev, -1); */
1939 #ifdef CONFIG_NET_POLL_CONTROLLER
1941 * Polling 'interrupt' - used by things like netconsole to send skbs
1942 * without having to re-enable interrupts. It's not called while
1943 * the interrupt routine is executing.
1946 static void poll_tulip (struct net_device *dev)
1948 struct tulip_private *tp = netdev_priv(dev);
1949 const int irq = tp->pdev->irq;
1951 /* disable_irq here is not very nice, but with the lockless
1952 interrupt handler we have no other choice. */
1954 tulip_interrupt (irq, dev);
1959 static struct pci_driver tulip_driver = {
1961 .id_table = tulip_pci_tbl,
1962 .probe = tulip_init_one,
1963 .remove = tulip_remove_one,
1965 .suspend = tulip_suspend,
1966 .resume = tulip_resume,
1967 #endif /* CONFIG_PM */
1971 static int __init tulip_init (void)
1974 pr_info("%s", version);
1978 pr_warn("tulip: unknown CPU architecture, using default csr0\n");
1979 /* default to 8 longword cache line alignment */
1980 csr0 = 0x00A00000 | 0x4800;
1983 /* copy module parms into globals */
1984 tulip_rx_copybreak = rx_copybreak;
1985 tulip_max_interrupt_work = max_interrupt_work;
1987 /* probe for and init boards */
1988 return pci_register_driver(&tulip_driver);
1992 static void __exit tulip_cleanup (void)
1994 pci_unregister_driver (&tulip_driver);
1998 module_init(tulip_init);
1999 module_exit(tulip_cleanup);