1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
4 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
7 #include <linux/kernel.h>
8 #include <linux/errno.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/delay.h>
12 #include <linux/if_ether.h>
14 #include "vnic_resource.h"
15 #include "vnic_devcmd.h"
18 #include "vnic_stats.h"
21 #define VNIC_MAX_RES_HDR_SIZE \
22 (sizeof(struct vnic_resource_header) + \
23 sizeof(struct vnic_resource) * RES_TYPE_MAX)
24 #define VNIC_RES_STRIDE 128
26 void *vnic_dev_priv(struct vnic_dev *vdev)
31 static int vnic_dev_discover_res(struct vnic_dev *vdev,
32 struct vnic_dev_bar *bar, unsigned int num_bars)
34 struct vnic_resource_header __iomem *rh;
35 struct mgmt_barmap_hdr __iomem *mrh;
36 struct vnic_resource __iomem *r;
42 if (bar->len < VNIC_MAX_RES_HDR_SIZE) {
43 vdev_err(vdev, "vNIC BAR0 res hdr length error\n");
50 vdev_err(vdev, "vNIC BAR0 res hdr not mem-mapped\n");
54 /* Check for mgmt vnic in addition to normal vnic */
55 if ((ioread32(&rh->magic) != VNIC_RES_MAGIC) ||
56 (ioread32(&rh->version) != VNIC_RES_VERSION)) {
57 if ((ioread32(&mrh->magic) != MGMTVNIC_MAGIC) ||
58 (ioread32(&mrh->version) != MGMTVNIC_VERSION)) {
59 vdev_err(vdev, "vNIC BAR0 res magic/version error exp (%lx/%lx) or (%lx/%lx), curr (%x/%x)\n",
60 VNIC_RES_MAGIC, VNIC_RES_VERSION,
61 MGMTVNIC_MAGIC, MGMTVNIC_VERSION,
62 ioread32(&rh->magic), ioread32(&rh->version));
67 if (ioread32(&mrh->magic) == MGMTVNIC_MAGIC)
68 r = (struct vnic_resource __iomem *)(mrh + 1);
70 r = (struct vnic_resource __iomem *)(rh + 1);
73 while ((type = ioread8(&r->type)) != RES_TYPE_EOL) {
75 u8 bar_num = ioread8(&r->bar);
76 u32 bar_offset = ioread32(&r->bar_offset);
77 u32 count = ioread32(&r->count);
82 if (bar_num >= num_bars)
85 if (!bar[bar_num].len || !bar[bar_num].vaddr)
92 case RES_TYPE_INTR_CTRL:
93 /* each count is stride bytes long */
94 len = count * VNIC_RES_STRIDE;
95 if (len + bar_offset > bar[bar_num].len) {
96 vdev_err(vdev, "vNIC BAR0 resource %d out-of-bounds, offset 0x%x + size 0x%x > bar len 0x%lx\n",
97 type, bar_offset, len,
102 case RES_TYPE_INTR_PBA_LEGACY:
103 case RES_TYPE_DEVCMD:
104 case RES_TYPE_DEVCMD2:
111 vdev->res[type].count = count;
112 vdev->res[type].vaddr = (char __iomem *)bar[bar_num].vaddr +
114 vdev->res[type].bus_addr = bar[bar_num].bus_addr + bar_offset;
120 unsigned int vnic_dev_get_res_count(struct vnic_dev *vdev,
121 enum vnic_res_type type)
123 return vdev->res[type].count;
125 EXPORT_SYMBOL(vnic_dev_get_res_count);
127 void __iomem *vnic_dev_get_res(struct vnic_dev *vdev, enum vnic_res_type type,
130 if (!vdev->res[type].vaddr)
137 case RES_TYPE_INTR_CTRL:
138 return (char __iomem *)vdev->res[type].vaddr +
139 index * VNIC_RES_STRIDE;
141 return (char __iomem *)vdev->res[type].vaddr;
144 EXPORT_SYMBOL(vnic_dev_get_res);
146 static unsigned int vnic_dev_desc_ring_size(struct vnic_dev_ring *ring,
147 unsigned int desc_count, unsigned int desc_size)
149 /* The base address of the desc rings must be 512 byte aligned.
150 * Descriptor count is aligned to groups of 32 descriptors. A
151 * count of 0 means the maximum 4096 descriptors. Descriptor
152 * size is aligned to 16 bytes.
155 unsigned int count_align = 32;
156 unsigned int desc_align = 16;
158 ring->base_align = 512;
163 ring->desc_count = ALIGN(desc_count, count_align);
165 ring->desc_size = ALIGN(desc_size, desc_align);
167 ring->size = ring->desc_count * ring->desc_size;
168 ring->size_unaligned = ring->size + ring->base_align;
170 return ring->size_unaligned;
173 void vnic_dev_clear_desc_ring(struct vnic_dev_ring *ring)
175 memset(ring->descs, 0, ring->size);
178 int vnic_dev_alloc_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring,
179 unsigned int desc_count, unsigned int desc_size)
181 vnic_dev_desc_ring_size(ring, desc_count, desc_size);
183 ring->descs_unaligned = dma_alloc_coherent(&vdev->pdev->dev,
184 ring->size_unaligned,
185 &ring->base_addr_unaligned,
188 if (!ring->descs_unaligned) {
189 vdev_err(vdev, "Failed to allocate ring (size=%d), aborting\n",
194 ring->base_addr = ALIGN(ring->base_addr_unaligned,
196 ring->descs = (u8 *)ring->descs_unaligned +
197 (ring->base_addr - ring->base_addr_unaligned);
199 vnic_dev_clear_desc_ring(ring);
201 ring->desc_avail = ring->desc_count - 1;
206 void vnic_dev_free_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring)
209 dma_free_coherent(&vdev->pdev->dev, ring->size_unaligned,
210 ring->descs_unaligned,
211 ring->base_addr_unaligned);
216 static int _vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
219 struct vnic_devcmd __iomem *devcmd = vdev->devcmd;
225 status = ioread32(&devcmd->status);
226 if (status == 0xFFFFFFFF) {
227 /* PCI-e target device is gone */
230 if (status & STAT_BUSY) {
231 vdev_neterr(vdev, "Busy devcmd %d\n", _CMD_N(cmd));
235 if (_CMD_DIR(cmd) & _CMD_DIR_WRITE) {
236 for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
237 writeq(vdev->args[i], &devcmd->args[i]);
241 iowrite32(cmd, &devcmd->cmd);
243 if ((_CMD_FLAGS(cmd) & _CMD_FLAGS_NOWAIT))
246 for (delay = 0; delay < wait; delay++) {
250 status = ioread32(&devcmd->status);
251 if (status == 0xFFFFFFFF) {
252 /* PCI-e target device is gone */
256 if (!(status & STAT_BUSY)) {
258 if (status & STAT_ERROR) {
259 err = (int)readq(&devcmd->args[0]);
260 if (err == ERR_EINVAL &&
261 cmd == CMD_CAPABILITY)
263 if (err != ERR_ECMDUNKNOWN ||
264 cmd != CMD_CAPABILITY)
265 vdev_neterr(vdev, "Error %d devcmd %d\n",
270 if (_CMD_DIR(cmd) & _CMD_DIR_READ) {
272 for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
273 vdev->args[i] = readq(&devcmd->args[i]);
280 vdev_neterr(vdev, "Timedout devcmd %d\n", _CMD_N(cmd));
284 static int _vnic_dev_cmd2(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
287 struct devcmd2_controller *dc2c = vdev->devcmd2;
288 struct devcmd2_result *result;
292 u32 fetch_index, new_posted;
293 u32 posted = dc2c->posted;
295 fetch_index = ioread32(&dc2c->wq_ctrl->fetch_index);
297 if (fetch_index == 0xFFFFFFFF)
300 new_posted = (posted + 1) % DEVCMD2_RING_SIZE;
302 if (new_posted == fetch_index) {
303 vdev_neterr(vdev, "devcmd2 %d: wq is full. fetch index: %u, posted index: %u\n",
304 _CMD_N(cmd), fetch_index, posted);
307 dc2c->cmd_ring[posted].cmd = cmd;
308 dc2c->cmd_ring[posted].flags = 0;
310 if ((_CMD_FLAGS(cmd) & _CMD_FLAGS_NOWAIT))
311 dc2c->cmd_ring[posted].flags |= DEVCMD2_FNORESULT;
312 if (_CMD_DIR(cmd) & _CMD_DIR_WRITE)
313 for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
314 dc2c->cmd_ring[posted].args[i] = vdev->args[i];
316 /* Adding write memory barrier prevents compiler and/or CPU reordering,
317 * thus avoiding descriptor posting before descriptor is initialized.
318 * Otherwise, hardware can read stale descriptor fields.
321 iowrite32(new_posted, &dc2c->wq_ctrl->posted_index);
322 dc2c->posted = new_posted;
324 if (dc2c->cmd_ring[posted].flags & DEVCMD2_FNORESULT)
327 result = dc2c->result + dc2c->next_result;
331 if (dc2c->next_result == dc2c->result_size) {
332 dc2c->next_result = 0;
333 dc2c->color = dc2c->color ? 0 : 1;
336 for (delay = 0; delay < wait; delay++) {
337 if (result->color == color) {
340 if (err != ERR_ECMDUNKNOWN ||
341 cmd != CMD_CAPABILITY)
342 vdev_neterr(vdev, "Error %d devcmd %d\n",
346 if (_CMD_DIR(cmd) & _CMD_DIR_READ)
347 for (i = 0; i < VNIC_DEVCMD2_NARGS; i++)
348 vdev->args[i] = result->results[i];
355 vdev_neterr(vdev, "devcmd %d timed out\n", _CMD_N(cmd));
360 static int vnic_dev_init_devcmd1(struct vnic_dev *vdev)
362 vdev->devcmd = vnic_dev_get_res(vdev, RES_TYPE_DEVCMD, 0);
365 vdev->devcmd_rtn = _vnic_dev_cmd;
370 static int vnic_dev_init_devcmd2(struct vnic_dev *vdev)
373 unsigned int fetch_index;
378 vdev->devcmd2 = kzalloc(sizeof(*vdev->devcmd2), GFP_KERNEL);
382 vdev->devcmd2->color = 1;
383 vdev->devcmd2->result_size = DEVCMD2_RING_SIZE;
384 err = enic_wq_devcmd2_alloc(vdev, &vdev->devcmd2->wq, DEVCMD2_RING_SIZE,
387 goto err_free_devcmd2;
389 fetch_index = ioread32(&vdev->devcmd2->wq.ctrl->fetch_index);
390 if (fetch_index == 0xFFFFFFFF) { /* check for hardware gone */
391 vdev_err(vdev, "Fatal error in devcmd2 init - hardware surprise removal\n");
396 enic_wq_init_start(&vdev->devcmd2->wq, 0, fetch_index, fetch_index, 0,
398 vdev->devcmd2->posted = fetch_index;
399 vnic_wq_enable(&vdev->devcmd2->wq);
401 err = vnic_dev_alloc_desc_ring(vdev, &vdev->devcmd2->results_ring,
402 DEVCMD2_RING_SIZE, DEVCMD2_DESC_SIZE);
406 vdev->devcmd2->result = vdev->devcmd2->results_ring.descs;
407 vdev->devcmd2->cmd_ring = vdev->devcmd2->wq.ring.descs;
408 vdev->devcmd2->wq_ctrl = vdev->devcmd2->wq.ctrl;
409 vdev->args[0] = (u64)vdev->devcmd2->results_ring.base_addr |
411 vdev->args[1] = DEVCMD2_RING_SIZE;
413 err = _vnic_dev_cmd2(vdev, CMD_INITIALIZE_DEVCMD2, 1000);
415 goto err_free_desc_ring;
417 vdev->devcmd_rtn = _vnic_dev_cmd2;
422 vnic_dev_free_desc_ring(vdev, &vdev->devcmd2->results_ring);
424 vnic_wq_disable(&vdev->devcmd2->wq);
426 vnic_wq_free(&vdev->devcmd2->wq);
428 kfree(vdev->devcmd2);
429 vdev->devcmd2 = NULL;
434 static void vnic_dev_deinit_devcmd2(struct vnic_dev *vdev)
436 vnic_dev_free_desc_ring(vdev, &vdev->devcmd2->results_ring);
437 vnic_wq_disable(&vdev->devcmd2->wq);
438 vnic_wq_free(&vdev->devcmd2->wq);
439 kfree(vdev->devcmd2);
442 static int vnic_dev_cmd_proxy(struct vnic_dev *vdev,
443 enum vnic_devcmd_cmd proxy_cmd, enum vnic_devcmd_cmd cmd,
444 u64 *a0, u64 *a1, int wait)
449 memset(vdev->args, 0, sizeof(vdev->args));
451 vdev->args[0] = vdev->proxy_index;
456 err = vdev->devcmd_rtn(vdev, proxy_cmd, wait);
460 status = (u32)vdev->args[0];
461 if (status & STAT_ERROR) {
462 err = (int)vdev->args[1];
463 if (err != ERR_ECMDUNKNOWN ||
464 cmd != CMD_CAPABILITY)
465 vdev_neterr(vdev, "Error %d proxy devcmd %d\n",
476 static int vnic_dev_cmd_no_proxy(struct vnic_dev *vdev,
477 enum vnic_devcmd_cmd cmd, u64 *a0, u64 *a1, int wait)
484 err = vdev->devcmd_rtn(vdev, cmd, wait);
492 void vnic_dev_cmd_proxy_by_index_start(struct vnic_dev *vdev, u16 index)
494 vdev->proxy = PROXY_BY_INDEX;
495 vdev->proxy_index = index;
498 void vnic_dev_cmd_proxy_end(struct vnic_dev *vdev)
500 vdev->proxy = PROXY_NONE;
501 vdev->proxy_index = 0;
504 int vnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
505 u64 *a0, u64 *a1, int wait)
507 memset(vdev->args, 0, sizeof(vdev->args));
509 switch (vdev->proxy) {
511 return vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_INDEX, cmd,
514 return vnic_dev_cmd_proxy(vdev, CMD_PROXY_BY_BDF, cmd,
518 return vnic_dev_cmd_no_proxy(vdev, cmd, a0, a1, wait);
522 static int vnic_dev_capable(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd)
524 u64 a0 = (u32)cmd, a1 = 0;
528 err = vnic_dev_cmd(vdev, CMD_CAPABILITY, &a0, &a1, wait);
533 int vnic_dev_fw_info(struct vnic_dev *vdev,
534 struct vnic_devcmd_fw_info **fw_info)
540 if (!vdev->fw_info) {
541 vdev->fw_info = dma_alloc_coherent(&vdev->pdev->dev,
542 sizeof(struct vnic_devcmd_fw_info),
543 &vdev->fw_info_pa, GFP_ATOMIC);
547 a0 = vdev->fw_info_pa;
548 a1 = sizeof(struct vnic_devcmd_fw_info);
550 /* only get fw_info once and cache it */
551 if (vnic_dev_capable(vdev, CMD_MCPU_FW_INFO))
552 err = vnic_dev_cmd(vdev, CMD_MCPU_FW_INFO,
555 err = vnic_dev_cmd(vdev, CMD_MCPU_FW_INFO_OLD,
559 *fw_info = vdev->fw_info;
564 int vnic_dev_spec(struct vnic_dev *vdev, unsigned int offset, unsigned int size,
574 err = vnic_dev_cmd(vdev, CMD_DEV_SPEC, &a0, &a1, wait);
577 case 1: *(u8 *)value = (u8)a0; break;
578 case 2: *(u16 *)value = (u16)a0; break;
579 case 4: *(u32 *)value = (u32)a0; break;
580 case 8: *(u64 *)value = a0; break;
581 default: BUG(); break;
587 int vnic_dev_stats_dump(struct vnic_dev *vdev, struct vnic_stats **stats)
593 vdev->stats = dma_alloc_coherent(&vdev->pdev->dev,
594 sizeof(struct vnic_stats),
595 &vdev->stats_pa, GFP_ATOMIC);
600 *stats = vdev->stats;
602 a1 = sizeof(struct vnic_stats);
604 return vnic_dev_cmd(vdev, CMD_STATS_DUMP, &a0, &a1, wait);
607 int vnic_dev_close(struct vnic_dev *vdev)
611 return vnic_dev_cmd(vdev, CMD_CLOSE, &a0, &a1, wait);
614 int vnic_dev_enable_wait(struct vnic_dev *vdev)
619 if (vnic_dev_capable(vdev, CMD_ENABLE_WAIT))
620 return vnic_dev_cmd(vdev, CMD_ENABLE_WAIT, &a0, &a1, wait);
622 return vnic_dev_cmd(vdev, CMD_ENABLE, &a0, &a1, wait);
625 int vnic_dev_disable(struct vnic_dev *vdev)
629 return vnic_dev_cmd(vdev, CMD_DISABLE, &a0, &a1, wait);
632 int vnic_dev_open(struct vnic_dev *vdev, int arg)
634 u64 a0 = (u32)arg, a1 = 0;
636 return vnic_dev_cmd(vdev, CMD_OPEN, &a0, &a1, wait);
639 int vnic_dev_open_done(struct vnic_dev *vdev, int *done)
647 err = vnic_dev_cmd(vdev, CMD_OPEN_STATUS, &a0, &a1, wait);
656 int vnic_dev_soft_reset(struct vnic_dev *vdev, int arg)
658 u64 a0 = (u32)arg, a1 = 0;
660 return vnic_dev_cmd(vdev, CMD_SOFT_RESET, &a0, &a1, wait);
663 int vnic_dev_soft_reset_done(struct vnic_dev *vdev, int *done)
671 err = vnic_dev_cmd(vdev, CMD_SOFT_RESET_STATUS, &a0, &a1, wait);
680 int vnic_dev_hang_reset(struct vnic_dev *vdev, int arg)
682 u64 a0 = (u32)arg, a1 = 0;
686 if (vnic_dev_capable(vdev, CMD_HANG_RESET)) {
687 return vnic_dev_cmd(vdev, CMD_HANG_RESET,
690 err = vnic_dev_soft_reset(vdev, arg);
693 return vnic_dev_init(vdev, 0);
697 int vnic_dev_hang_reset_done(struct vnic_dev *vdev, int *done)
705 if (vnic_dev_capable(vdev, CMD_HANG_RESET_STATUS)) {
706 err = vnic_dev_cmd(vdev, CMD_HANG_RESET_STATUS,
711 return vnic_dev_soft_reset_done(vdev, done);
719 int vnic_dev_hang_notify(struct vnic_dev *vdev)
723 return vnic_dev_cmd(vdev, CMD_HANG_NOTIFY, &a0, &a1, wait);
726 int vnic_dev_get_mac_addr(struct vnic_dev *vdev, u8 *mac_addr)
732 for (i = 0; i < ETH_ALEN; i++)
735 err = vnic_dev_cmd(vdev, CMD_GET_MAC_ADDR, &a0, &a1, wait);
739 for (i = 0; i < ETH_ALEN; i++)
740 mac_addr[i] = ((u8 *)&a0)[i];
745 int vnic_dev_packet_filter(struct vnic_dev *vdev, int directed, int multicast,
746 int broadcast, int promisc, int allmulti)
752 a0 = (directed ? CMD_PFILTER_DIRECTED : 0) |
753 (multicast ? CMD_PFILTER_MULTICAST : 0) |
754 (broadcast ? CMD_PFILTER_BROADCAST : 0) |
755 (promisc ? CMD_PFILTER_PROMISCUOUS : 0) |
756 (allmulti ? CMD_PFILTER_ALL_MULTICAST : 0);
758 err = vnic_dev_cmd(vdev, CMD_PACKET_FILTER, &a0, &a1, wait);
760 vdev_neterr(vdev, "Can't set packet filter\n");
765 int vnic_dev_add_addr(struct vnic_dev *vdev, const u8 *addr)
772 for (i = 0; i < ETH_ALEN; i++)
773 ((u8 *)&a0)[i] = addr[i];
775 err = vnic_dev_cmd(vdev, CMD_ADDR_ADD, &a0, &a1, wait);
777 vdev_neterr(vdev, "Can't add addr [%pM], %d\n", addr, err);
782 int vnic_dev_del_addr(struct vnic_dev *vdev, const u8 *addr)
789 for (i = 0; i < ETH_ALEN; i++)
790 ((u8 *)&a0)[i] = addr[i];
792 err = vnic_dev_cmd(vdev, CMD_ADDR_DEL, &a0, &a1, wait);
794 vdev_neterr(vdev, "Can't del addr [%pM], %d\n", addr, err);
799 int vnic_dev_set_ig_vlan_rewrite_mode(struct vnic_dev *vdev,
800 u8 ig_vlan_rewrite_mode)
802 u64 a0 = ig_vlan_rewrite_mode, a1 = 0;
805 if (vnic_dev_capable(vdev, CMD_IG_VLAN_REWRITE_MODE))
806 return vnic_dev_cmd(vdev, CMD_IG_VLAN_REWRITE_MODE,
812 static int vnic_dev_notify_setcmd(struct vnic_dev *vdev,
813 void *notify_addr, dma_addr_t notify_pa, u16 intr)
819 memset(notify_addr, 0, sizeof(struct vnic_devcmd_notify));
820 vdev->notify = notify_addr;
821 vdev->notify_pa = notify_pa;
824 a1 = ((u64)intr << 32) & 0x0000ffff00000000ULL;
825 a1 += sizeof(struct vnic_devcmd_notify);
827 r = vnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);
828 vdev->notify_sz = (r == 0) ? (u32)a1 : 0;
832 int vnic_dev_notify_set(struct vnic_dev *vdev, u16 intr)
835 dma_addr_t notify_pa;
837 if (vdev->notify || vdev->notify_pa) {
838 vdev_neterr(vdev, "notify block %p still allocated\n",
843 notify_addr = dma_alloc_coherent(&vdev->pdev->dev,
844 sizeof(struct vnic_devcmd_notify),
845 ¬ify_pa, GFP_ATOMIC);
849 return vnic_dev_notify_setcmd(vdev, notify_addr, notify_pa, intr);
852 static int vnic_dev_notify_unsetcmd(struct vnic_dev *vdev)
858 a0 = 0; /* paddr = 0 to unset notify buffer */
859 a1 = 0x0000ffff00000000ULL; /* intr num = -1 to unreg for intr */
860 a1 += sizeof(struct vnic_devcmd_notify);
862 err = vnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);
870 int vnic_dev_notify_unset(struct vnic_dev *vdev)
873 dma_free_coherent(&vdev->pdev->dev,
874 sizeof(struct vnic_devcmd_notify),
875 vdev->notify, vdev->notify_pa);
878 return vnic_dev_notify_unsetcmd(vdev);
881 static int vnic_dev_notify_ready(struct vnic_dev *vdev)
884 unsigned int nwords = vdev->notify_sz / 4;
888 if (!vdev->notify || !vdev->notify_sz)
893 memcpy(&vdev->notify_copy, vdev->notify, vdev->notify_sz);
894 words = (u32 *)&vdev->notify_copy;
895 for (i = 1; i < nwords; i++)
897 } while (csum != words[0]);
902 int vnic_dev_init(struct vnic_dev *vdev, int arg)
904 u64 a0 = (u32)arg, a1 = 0;
908 if (vnic_dev_capable(vdev, CMD_INIT))
909 r = vnic_dev_cmd(vdev, CMD_INIT, &a0, &a1, wait);
911 vnic_dev_cmd(vdev, CMD_INIT_v1, &a0, &a1, wait);
912 if (a0 & CMD_INITF_DEFAULT_MAC) {
913 /* Emulate these for old CMD_INIT_v1 which
914 * didn't pass a0 so no CMD_INITF_*.
916 vnic_dev_cmd(vdev, CMD_GET_MAC_ADDR, &a0, &a1, wait);
917 vnic_dev_cmd(vdev, CMD_ADDR_ADD, &a0, &a1, wait);
923 int vnic_dev_deinit(struct vnic_dev *vdev)
928 return vnic_dev_cmd(vdev, CMD_DEINIT, &a0, &a1, wait);
931 void vnic_dev_intr_coal_timer_info_default(struct vnic_dev *vdev)
933 /* Default: hardware intr coal timer is in units of 1.5 usecs */
934 vdev->intr_coal_timer_info.mul = 2;
935 vdev->intr_coal_timer_info.div = 3;
936 vdev->intr_coal_timer_info.max_usec =
937 vnic_dev_intr_coal_timer_hw_to_usec(vdev, 0xffff);
940 int vnic_dev_intr_coal_timer_info(struct vnic_dev *vdev)
945 memset(vdev->args, 0, sizeof(vdev->args));
947 if (vnic_dev_capable(vdev, CMD_INTR_COAL_CONVERT))
948 err = vdev->devcmd_rtn(vdev, CMD_INTR_COAL_CONVERT, wait);
950 err = ERR_ECMDUNKNOWN;
952 /* Use defaults when firmware doesn't support the devcmd at all or
953 * supports it for only specific hardware
955 if ((err == ERR_ECMDUNKNOWN) ||
956 (!err && !(vdev->args[0] && vdev->args[1] && vdev->args[2]))) {
957 vdev_netwarn(vdev, "Using default conversion factor for interrupt coalesce timer\n");
958 vnic_dev_intr_coal_timer_info_default(vdev);
963 vdev->intr_coal_timer_info.mul = (u32) vdev->args[0];
964 vdev->intr_coal_timer_info.div = (u32) vdev->args[1];
965 vdev->intr_coal_timer_info.max_usec = (u32) vdev->args[2];
971 int vnic_dev_link_status(struct vnic_dev *vdev)
973 if (!vnic_dev_notify_ready(vdev))
976 return vdev->notify_copy.link_state;
979 u32 vnic_dev_port_speed(struct vnic_dev *vdev)
981 if (!vnic_dev_notify_ready(vdev))
984 return vdev->notify_copy.port_speed;
987 u32 vnic_dev_msg_lvl(struct vnic_dev *vdev)
989 if (!vnic_dev_notify_ready(vdev))
992 return vdev->notify_copy.msglvl;
995 u32 vnic_dev_mtu(struct vnic_dev *vdev)
997 if (!vnic_dev_notify_ready(vdev))
1000 return vdev->notify_copy.mtu;
1003 void vnic_dev_set_intr_mode(struct vnic_dev *vdev,
1004 enum vnic_dev_intr_mode intr_mode)
1006 vdev->intr_mode = intr_mode;
1009 enum vnic_dev_intr_mode vnic_dev_get_intr_mode(
1010 struct vnic_dev *vdev)
1012 return vdev->intr_mode;
1015 u32 vnic_dev_intr_coal_timer_usec_to_hw(struct vnic_dev *vdev, u32 usec)
1017 return (usec * vdev->intr_coal_timer_info.mul) /
1018 vdev->intr_coal_timer_info.div;
1021 u32 vnic_dev_intr_coal_timer_hw_to_usec(struct vnic_dev *vdev, u32 hw_cycles)
1023 return (hw_cycles * vdev->intr_coal_timer_info.div) /
1024 vdev->intr_coal_timer_info.mul;
1027 u32 vnic_dev_get_intr_coal_timer_max(struct vnic_dev *vdev)
1029 return vdev->intr_coal_timer_info.max_usec;
1032 void vnic_dev_unregister(struct vnic_dev *vdev)
1036 dma_free_coherent(&vdev->pdev->dev,
1037 sizeof(struct vnic_devcmd_notify),
1038 vdev->notify, vdev->notify_pa);
1040 dma_free_coherent(&vdev->pdev->dev,
1041 sizeof(struct vnic_stats),
1042 vdev->stats, vdev->stats_pa);
1044 dma_free_coherent(&vdev->pdev->dev,
1045 sizeof(struct vnic_devcmd_fw_info),
1046 vdev->fw_info, vdev->fw_info_pa);
1048 vnic_dev_deinit_devcmd2(vdev);
1053 EXPORT_SYMBOL(vnic_dev_unregister);
1055 struct vnic_dev *vnic_dev_register(struct vnic_dev *vdev,
1056 void *priv, struct pci_dev *pdev, struct vnic_dev_bar *bar,
1057 unsigned int num_bars)
1060 vdev = kzalloc(sizeof(struct vnic_dev), GFP_KERNEL);
1068 if (vnic_dev_discover_res(vdev, bar, num_bars))
1074 vnic_dev_unregister(vdev);
1077 EXPORT_SYMBOL(vnic_dev_register);
1079 struct pci_dev *vnic_dev_get_pdev(struct vnic_dev *vdev)
1083 EXPORT_SYMBOL(vnic_dev_get_pdev);
1085 int vnic_devcmd_init(struct vnic_dev *vdev)
1090 res = vnic_dev_get_res(vdev, RES_TYPE_DEVCMD2, 0);
1092 err = vnic_dev_init_devcmd2(vdev);
1094 vdev_warn(vdev, "DEVCMD2 init failed: %d, Using DEVCMD1\n",
1099 vdev_warn(vdev, "DEVCMD2 resource not found (old firmware?) Using DEVCMD1\n");
1101 err = vnic_dev_init_devcmd1(vdev);
1103 vdev_err(vdev, "DEVCMD1 initialization failed: %d\n", err);
1108 int vnic_dev_init_prov2(struct vnic_dev *vdev, u8 *buf, u32 len)
1116 prov_buf = dma_alloc_coherent(&vdev->pdev->dev, len, &prov_pa, GFP_ATOMIC);
1120 memcpy(prov_buf, buf, len);
1124 ret = vnic_dev_cmd(vdev, CMD_INIT_PROV_INFO2, &a0, &a1, wait);
1126 dma_free_coherent(&vdev->pdev->dev, len, prov_buf, prov_pa);
1131 int vnic_dev_enable2(struct vnic_dev *vdev, int active)
1136 a0 = (active ? CMD_ENABLE2_ACTIVE : 0);
1138 return vnic_dev_cmd(vdev, CMD_ENABLE2, &a0, &a1, wait);
1141 static int vnic_dev_cmd_status(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
1144 u64 a0 = cmd, a1 = 0;
1148 ret = vnic_dev_cmd(vdev, CMD_STATUS, &a0, &a1, wait);
1155 int vnic_dev_enable2_done(struct vnic_dev *vdev, int *status)
1157 return vnic_dev_cmd_status(vdev, CMD_ENABLE2, status);
1160 int vnic_dev_deinit_done(struct vnic_dev *vdev, int *status)
1162 return vnic_dev_cmd_status(vdev, CMD_DEINIT, status);
1165 int vnic_dev_set_mac_addr(struct vnic_dev *vdev, u8 *mac_addr)
1171 for (i = 0; i < ETH_ALEN; i++)
1172 ((u8 *)&a0)[i] = mac_addr[i];
1174 return vnic_dev_cmd(vdev, CMD_SET_MAC_ADDR, &a0, &a1, wait);
1177 /* vnic_dev_classifier: Add/Delete classifier entries
1178 * @vdev: vdev of the device
1179 * @cmd: CLSF_ADD for Add filter
1180 * CLSF_DEL for Delete filter
1181 * @entry: In case of ADD filter, the caller passes the RQ number in this
1184 * This function stores the filter_id returned by the firmware in the
1185 * same variable before return;
1187 * In case of DEL filter, the caller passes the RQ number. Return
1188 * value is irrelevant.
1189 * @data: filter data
1191 int vnic_dev_classifier(struct vnic_dev *vdev, u8 cmd, u16 *entry,
1192 struct filter *data)
1198 struct filter_tlv *tlv, *tlv_va;
1199 struct filter_action *action;
1202 if (cmd == CLSF_ADD) {
1203 tlv_size = sizeof(struct filter) +
1204 sizeof(struct filter_action) +
1205 2 * sizeof(struct filter_tlv);
1206 tlv_va = dma_alloc_coherent(&vdev->pdev->dev, tlv_size,
1207 &tlv_pa, GFP_ATOMIC);
1213 memset(tlv, 0, tlv_size);
1214 tlv->type = CLSF_TLV_FILTER;
1215 tlv->length = sizeof(struct filter);
1216 *(struct filter *)&tlv->val = *data;
1218 tlv = (struct filter_tlv *)((char *)tlv +
1219 sizeof(struct filter_tlv) +
1220 sizeof(struct filter));
1222 tlv->type = CLSF_TLV_ACTION;
1223 tlv->length = sizeof(struct filter_action);
1224 action = (struct filter_action *)&tlv->val;
1225 action->type = FILTER_ACTION_RQ_STEERING;
1226 action->u.rq_idx = *entry;
1228 ret = vnic_dev_cmd(vdev, CMD_ADD_FILTER, &a0, &a1, wait);
1230 dma_free_coherent(&vdev->pdev->dev, tlv_size, tlv_va, tlv_pa);
1231 } else if (cmd == CLSF_DEL) {
1233 ret = vnic_dev_cmd(vdev, CMD_DEL_FILTER, &a0, &a1, wait);
1239 int vnic_dev_overlay_offload_ctrl(struct vnic_dev *vdev, u8 overlay, u8 config)
1245 return vnic_dev_cmd(vdev, CMD_OVERLAY_OFFLOAD_CTRL, &a0, &a1, wait);
1248 int vnic_dev_overlay_offload_cfg(struct vnic_dev *vdev, u8 overlay,
1249 u16 vxlan_udp_port_number)
1251 u64 a1 = vxlan_udp_port_number;
1255 return vnic_dev_cmd(vdev, CMD_OVERLAY_OFFLOAD_CFG, &a0, &a1, wait);
1258 int vnic_dev_get_supported_feature_ver(struct vnic_dev *vdev, u8 feature,
1259 u64 *supported_versions, u64 *a1)
1265 ret = vnic_dev_cmd(vdev, CMD_GET_SUPP_FEATURE_VER, &a0, a1, wait);
1267 *supported_versions = a0;
1272 int vnic_dev_capable_rss_hash_type(struct vnic_dev *vdev, u8 *rss_hash_type)
1274 u64 a0 = CMD_NIC_CFG, a1 = 0;
1278 err = vnic_dev_cmd(vdev, CMD_CAPABILITY, &a0, &a1, wait);
1279 /* rss_hash_type is valid only when a0 is 1. Adapter which does not
1280 * support CMD_CAPABILITY for rss_hash_type has a0 = 0
1282 if (err || (a0 != 1))
1285 a1 = (a1 >> NIC_CFG_RSS_HASH_TYPE_SHIFT) &
1286 NIC_CFG_RSS_HASH_TYPE_MASK_FIELD;
1288 *rss_hash_type = (u8)a1;