2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 #include "vnic_enet.h"
28 #include "vnic_intr.h"
29 #include "vnic_stats.h"
32 #include <linux/irq.h>
34 #define DRV_NAME "enic"
35 #define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver"
36 #define DRV_VERSION "2.3.0.20"
37 #define DRV_COPYRIGHT "Copyright 2008-2013 Cisco Systems, Inc"
39 #define ENIC_BARS_MAX 6
43 #define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX)
44 #define ENIC_INTR_MAX (ENIC_CQ_MAX + 2)
46 #define ENIC_AIC_LARGE_PKT_DIFF 3
48 struct enic_msix_entry {
50 char devname[IFNAMSIZ];
51 irqreturn_t (*isr)(int, void *);
53 cpumask_var_t affinity_mask;
56 /* Store only the lower range. Higher range is given by fw. */
57 struct enic_intr_mod_range {
58 u32 small_pkt_range_start;
59 u32 large_pkt_range_start;
62 struct enic_intr_mod_table {
67 #define ENIC_MAX_LINK_SPEEDS 3
68 #define ENIC_LINK_SPEED_10G 10000
69 #define ENIC_LINK_SPEED_4G 4000
70 #define ENIC_LINK_40G_INDEX 2
71 #define ENIC_LINK_10G_INDEX 1
72 #define ENIC_LINK_4G_INDEX 0
73 #define ENIC_RX_COALESCE_RANGE_END 125
74 #define ENIC_AIC_TS_BREAK 100
77 u32 small_pkt_range_start;
78 u32 large_pkt_range_start;
80 u32 use_adaptive_rx_coalesce;
84 #define ENIC_SRIOV_ENABLED (1 << 0)
86 /* enic port profile set flags */
87 #define ENIC_PORT_REQUEST_APPLIED (1 << 0)
88 #define ENIC_SET_REQUEST (1 << 1)
89 #define ENIC_SET_NAME (1 << 2)
90 #define ENIC_SET_INSTANCE (1 << 3)
91 #define ENIC_SET_HOST (1 << 4)
93 struct enic_port_profile {
96 char name[PORT_PROFILE_MAX];
97 u8 instance_uuid[PORT_UUID_MAX];
98 u8 host_uuid[PORT_UUID_MAX];
100 u8 mac_addr[ETH_ALEN];
103 /* enic_rfs_fltr_node - rfs filter node in hash table
104 * @@keys: IPv4 5 tuple
105 * @flow_id: flow_id of clsf filter provided by kernel
106 * @fltr_id: filter id of clsf filter returned by adaptor
107 * @rq_id: desired rq index
110 struct enic_rfs_fltr_node {
111 struct flow_keys keys;
115 struct hlist_node node;
118 /* enic_rfs_flw_tbl - rfs flow table
119 * @max: Maximum number of filters vNIC supports
120 * @free: Number of free filters available
121 * @toclean: hash table index to clean next
122 * @ht_head: hash table list head
124 * @rfs_may_expire: timer function for enic_rps_may_expire_flow
126 struct enic_rfs_flw_tbl {
130 #define ENIC_RFS_FLW_BITSHIFT (10)
131 #define ENIC_RFS_FLW_MASK ((1 << ENIC_RFS_FLW_BITSHIFT) - 1)
132 u16 toclean:ENIC_RFS_FLW_BITSHIFT;
133 struct hlist_head ht_head[1 << ENIC_RFS_FLW_BITSHIFT];
135 struct timer_list rfs_may_expire;
138 /* Per-instance private data structure */
140 struct net_device *netdev;
141 struct pci_dev *pdev;
142 struct vnic_enet_config config;
143 struct vnic_dev_bar bar[ENIC_BARS_MAX];
144 struct vnic_dev *vdev;
145 struct timer_list notify_timer;
146 struct work_struct reset;
147 struct work_struct tx_hang_reset;
148 struct work_struct change_mtu_work;
149 struct msix_entry msix_entry[ENIC_INTR_MAX];
150 struct enic_msix_entry msix[ENIC_INTR_MAX];
152 spinlock_t devcmd_lock;
153 u8 mac_addr[ETH_ALEN];
155 unsigned int priv_flags;
156 unsigned int mc_count;
157 unsigned int uc_count;
159 struct enic_rx_coal rx_coalesce_setting;
160 u32 rx_coalesce_usecs;
161 u32 tx_coalesce_usecs;
162 #ifdef CONFIG_PCI_IOV
165 spinlock_t enic_api_lock;
167 struct enic_port_profile *pp;
169 /* work queue cache line section */
170 ____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX];
171 spinlock_t wq_lock[ENIC_WQ_MAX];
172 unsigned int wq_count;
176 /* receive queue cache line section */
177 ____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX];
178 unsigned int rq_count;
179 u64 rq_truncated_pkts;
181 struct napi_struct napi[ENIC_RQ_MAX + ENIC_WQ_MAX];
183 /* interrupt resource cache line section */
184 ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX];
185 unsigned int intr_count;
186 u32 __iomem *legacy_pba; /* memory-mapped */
188 /* completion queue cache line section */
189 ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX];
190 unsigned int cq_count;
191 struct enic_rfs_flw_tbl rfs_h;
193 u8 rss_key[ENIC_RSS_LEN];
194 struct vnic_gen_stats gen_stats;
197 static inline struct net_device *vnic_get_netdev(struct vnic_dev *vdev)
199 struct enic *enic = vdev->priv;
204 /* wrappers function for kernel log
206 #define vdev_err(vdev, fmt, ...) \
207 dev_err(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
208 #define vdev_warn(vdev, fmt, ...) \
209 dev_warn(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
210 #define vdev_info(vdev, fmt, ...) \
211 dev_info(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
213 #define vdev_neterr(vdev, fmt, ...) \
214 netdev_err(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
215 #define vdev_netwarn(vdev, fmt, ...) \
216 netdev_warn(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
217 #define vdev_netinfo(vdev, fmt, ...) \
218 netdev_info(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
220 static inline struct device *enic_get_dev(struct enic *enic)
222 return &(enic->pdev->dev);
225 static inline unsigned int enic_cq_rq(struct enic *enic, unsigned int rq)
230 static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq)
232 return enic->rq_count + wq;
235 static inline unsigned int enic_legacy_io_intr(void)
240 static inline unsigned int enic_legacy_err_intr(void)
245 static inline unsigned int enic_legacy_notify_intr(void)
250 static inline unsigned int enic_msix_rq_intr(struct enic *enic,
253 return enic->cq[enic_cq_rq(enic, rq)].interrupt_offset;
256 static inline unsigned int enic_msix_wq_intr(struct enic *enic,
259 return enic->cq[enic_cq_wq(enic, wq)].interrupt_offset;
262 static inline unsigned int enic_msix_err_intr(struct enic *enic)
264 return enic->rq_count + enic->wq_count;
267 static inline unsigned int enic_msix_notify_intr(struct enic *enic)
269 return enic->rq_count + enic->wq_count + 1;
272 static inline bool enic_is_err_intr(struct enic *enic, int intr)
274 switch (vnic_dev_get_intr_mode(enic->vdev)) {
275 case VNIC_DEV_INTR_MODE_INTX:
276 return intr == enic_legacy_err_intr();
277 case VNIC_DEV_INTR_MODE_MSIX:
278 return intr == enic_msix_err_intr(enic);
279 case VNIC_DEV_INTR_MODE_MSI:
285 static inline bool enic_is_notify_intr(struct enic *enic, int intr)
287 switch (vnic_dev_get_intr_mode(enic->vdev)) {
288 case VNIC_DEV_INTR_MODE_INTX:
289 return intr == enic_legacy_notify_intr();
290 case VNIC_DEV_INTR_MODE_MSIX:
291 return intr == enic_msix_notify_intr(enic);
292 case VNIC_DEV_INTR_MODE_MSI:
298 static inline int enic_dma_map_check(struct enic *enic, dma_addr_t dma_addr)
300 if (unlikely(pci_dma_mapping_error(enic->pdev, dma_addr))) {
301 net_warn_ratelimited("%s: PCI dma mapping failed!\n",
303 enic->gen_stats.dma_map_error++;
311 void enic_reset_addr_lists(struct enic *enic);
312 int enic_sriov_enabled(struct enic *enic);
313 int enic_is_valid_vf(struct enic *enic, int vf);
314 int enic_is_dynamic(struct enic *enic);
315 void enic_set_ethtool_ops(struct net_device *netdev);
316 int __enic_set_rsskey(struct enic *enic);
318 #endif /* _ENIC_H_ */