2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
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13 * without modification, are permitted provided that the following
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17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
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23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #ifndef __T4_VALUES_H__
36 #define __T4_VALUES_H__
38 /* This file contains definitions for various T4 register value hardware
39 * constants. The types of values encoded here are predominantly those for
40 * register fields which control "modal" behavior. For the most part, we do
41 * not include definitions for register fields which are simple numeric
45 /* SGE register field values.
48 /* CONTROL1 register */
49 #define RXPKTCPLMODE_SPLIT_X 1
51 #define INGPCIEBOUNDARY_SHIFT_X 5
52 #define INGPCIEBOUNDARY_32B_X 0
54 #define INGPADBOUNDARY_SHIFT_X 5
56 #define T6_INGPADBOUNDARY_SHIFT_X 3
57 #define T6_INGPADBOUNDARY_8B_X 0
58 #define T6_INGPADBOUNDARY_32B_X 2
60 #define INGPADBOUNDARY_32B_X 0
62 /* CONTROL2 register */
63 #define INGPACKBOUNDARY_SHIFT_X 5
64 #define INGPACKBOUNDARY_16B_X 0
65 #define INGPACKBOUNDARY_64B_X 1
68 #define SGE_TIMERREGS 6
69 #define TIMERREG_COUNTER0_X 0
71 #define FETCHBURSTMIN_64B_X 2
72 #define FETCHBURSTMIN_128B_X 3
74 #define FETCHBURSTMAX_256B_X 2
75 #define FETCHBURSTMAX_512B_X 3
77 #define HOSTFCMODE_STATUS_PAGE_X 2
79 #define CIDXFLUSHTHRESH_32_X 5
81 #define UPDATEDELIVERY_INTERRUPT_X 1
83 #define RSPD_TYPE_FLBUF_X 0
84 #define RSPD_TYPE_CPL_X 1
85 #define RSPD_TYPE_INTR_X 2
87 /* Congestion Manager Definitions.
89 #define CONMCTXT_CNGTPMODE_S 19
90 #define CONMCTXT_CNGTPMODE_V(x) ((x) << CONMCTXT_CNGTPMODE_S)
91 #define CONMCTXT_CNGCHMAP_S 0
92 #define CONMCTXT_CNGCHMAP_V(x) ((x) << CONMCTXT_CNGCHMAP_S)
93 #define CONMCTXT_CNGTPMODE_CHANNEL_X 2
94 #define CONMCTXT_CNGTPMODE_QUEUE_X 1
96 /* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
97 * The User Doorbells are each 128 bytes in length with a Simple Doorbell at
98 * offsets 8x and a Write Combining single 64-byte Egress Queue Unit
99 * (IDXSIZE_UNIT_X) Gather Buffer interface at offset 64. For Ingress Queues,
100 * we have a Going To Sleep register at offsets 8x+4.
102 * As noted above, we have many instances of the Simple Doorbell and Going To
103 * Sleep registers at offsets 8x and 8x+4, respectively. We want to use a
104 * non-64-byte aligned offset for the Simple Doorbell in order to attempt to
105 * avoid buffering of the writes to the Simple Doorbell and we want to use a
106 * non-contiguous offset for the Going To Sleep writes in order to avoid
107 * possible combining between them.
109 #define SGE_UDB_SIZE 128
110 #define SGE_UDB_KDOORBELL 8
111 #define SGE_UDB_GTS 20
112 #define SGE_UDB_WCDOORBELL 64
114 /* CIM register field values.
116 #define X_MBOWNER_FW 1
117 #define X_MBOWNER_PL 2
119 /* PCI-E definitions */
120 #define WINDOW_SHIFT_X 10
121 #define PCIEOFST_SHIFT_X 10
123 /* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
124 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
125 * selects for a particular field being present. These fields, when present
126 * in the Compressed Filter Tuple, have the following widths in bits.
130 #define FT_VNIC_ID_W 17
133 #define FT_PROTOCOL_W 8
134 #define FT_ETHERTYPE_W 16
135 #define FT_MACMATCH_W 9
136 #define FT_MPSHITTYPE_W 3
137 #define FT_FRAGMENTATION_W 1
139 /* Some of the Compressed Filter Tuple fields have internal structure. These
140 * bit shifts/masks describe those structures. All shifts are relative to the
141 * base position of the fields within the Compressed Filter Tuple
143 #define FT_VLAN_VLD_S 16
144 #define FT_VLAN_VLD_V(x) ((x) << FT_VLAN_VLD_S)
145 #define FT_VLAN_VLD_F FT_VLAN_VLD_V(1U)
147 #define FT_VNID_ID_VF_S 0
148 #define FT_VNID_ID_VF_V(x) ((x) << FT_VNID_ID_VF_S)
150 #define FT_VNID_ID_PF_S 7
151 #define FT_VNID_ID_PF_V(x) ((x) << FT_VNID_ID_PF_S)
153 #define FT_VNID_ID_VLD_S 16
154 #define FT_VNID_ID_VLD_V(x) ((x) << FT_VNID_ID_VLD_S)
156 #endif /* __T4_VALUES_H__ */