drivers/net/ethernet/chelsio/cxgb4/t4_hw.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/delay.h>
  36 #include "cxgb4.h"
  37 #include "t4_regs.h"
  38 #include "t4_values.h"
  39 #include "t4fw_api.h"
  40 #include "t4fw_version.h"
  41
  42 /**
  43  *      t4_wait_op_done_val - wait until an operation is completed
  44  *      @adapter: the adapter performing the operation
  45  *      @reg: the register to check for completion
  46  *      @mask: a single-bit field within @reg that indicates completion
  47  *      @polarity: the value of the field when the operation is completed
  48  *      @attempts: number of check iterations
  49  *      @delay: delay in usecs between iterations
  50  *      @valp: where to store the value of the register at completion time
  51  *
  52  *      Wait until an operation is completed by checking a bit in a register
  53  *      up to @attempts times.  If @valp is not NULL the value of the register
  54  *      at the time it indicated completion is stored there.  Returns 0 if the
  55  *      operation completes and -EAGAIN otherwise.
  56  */
  57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                                int polarity, int attempts, int delay, u32 *valp)
  59 {
  60         while (1) {
  61                 u32 val = t4_read_reg(adapter, reg);
  62
  63                 if (!!(val & mask) == polarity) {
  64                         if (valp)
  65                                 *valp = val;
  66                         return 0;
  67                 }
  68                 if (--attempts == 0)
  69                         return -EAGAIN;
  70                 if (delay)
  71                         udelay(delay);
  72         }
  73 }
  74
  75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                   int polarity, int attempts, int delay)
  77 {
  78         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                    delay, NULL);
  80 }
  81
  82 /**
  83  *      t4_set_reg_field - set a register field to a value
  84  *      @adapter: the adapter to program
  85  *      @addr: the register address
  86  *      @mask: specifies the portion of the register to modify
  87  *      @val: the new value for the register field
  88  *
  89  *      Sets a register field specified by the supplied mask to the
  90  *      given value.
  91  */
  92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                       u32 val)
  94 {
  95         u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97         t4_write_reg(adapter, addr, v | val);
  98         (void) t4_read_reg(adapter, addr);      /* flush */
  99 }
 100
 101 /**
 102  *      t4_read_indirect - read indirectly addressed registers
 103  *      @adap: the adapter
 104  *      @addr_reg: register holding the indirect address
 105  *      @data_reg: register holding the value of the indirect register
 106  *      @vals: where the read register values are stored
 107  *      @nregs: how many indirect registers to read
 108  *      @start_idx: index of first indirect register to read
 109  *
 110  *      Reads registers that are accessed indirectly through an address/data
 111  *      register pair.
 112  */
 113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                              unsigned int data_reg, u32 *vals,
 115                              unsigned int nregs, unsigned int start_idx)
 116 {
 117         while (nregs--) {
 118                 t4_write_reg(adap, addr_reg, start_idx);
 119                 *vals++ = t4_read_reg(adap, data_reg);
 120                 start_idx++;
 121         }
 122 }
 123
 124 /**
 125  *      t4_write_indirect - write indirectly addressed registers
 126  *      @adap: the adapter
 127  *      @addr_reg: register holding the indirect addresses
 128  *      @data_reg: register holding the value for the indirect registers
 129  *      @vals: values to write
 130  *      @nregs: how many indirect registers to write
 131  *      @start_idx: address of first indirect register to write
 132  *
 133  *      Writes a sequential block of registers that are accessed indirectly
 134  *      through an address/data register pair.
 135  */
 136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                        unsigned int data_reg, const u32 *vals,
 138                        unsigned int nregs, unsigned int start_idx)
 139 {
 140         while (nregs--) {
 141                 t4_write_reg(adap, addr_reg, start_idx++);
 142                 t4_write_reg(adap, data_reg, *vals++);
 143         }
 144 }
 145
 146 /*
 147  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148  * mechanism.  This guarantees that we get the real value even if we're
 149  * operating within a Virtual Machine and the Hypervisor is trapping our
 150  * Configuration Space accesses.
 151  */
 152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153 {
 154         u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                 req |= ENABLE_F;
 158         else
 159                 req |= T6_ENABLE_F;
 160
 161         if (is_t4(adap->params.chip))
 162                 req |= LOCALCFG_F;
 163
 164         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165         *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167         /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168          * Configuration Space read.  (None of the other fields matter when
 169          * ENABLE is 0 so a simple register write is easier than a
 170          * read-modify-write via t4_set_reg_field().)
 171          */
 172         t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173 }
 174
 175 /*
 176  * t4_report_fw_error - report firmware error
 177  * @adap: the adapter
 178  *
 179  * The adapter firmware can indicate error conditions to the host.
 180  * If the firmware has indicated an error, print out the reason for
 181  * the firmware error.
 182  */
 183 static void t4_report_fw_error(struct adapter *adap)
 184 {
 185         static const char *const reason[] = {
 186                 "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                 "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                 "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                 "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                 "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                 "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                 "Reserved",                     /* reserved */
 194         };
 195         u32 pcie_fw;
 196
 197         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198         if (pcie_fw & PCIE_FW_ERR_F)
 199                 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                         reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201 }
 202
 203 /*
 204  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 205  */
 206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 207                          u32 mbox_addr)
 208 {
 209         for ( ; nflit; nflit--, mbox_addr += 8)
 210                 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 211 }
 212
 213 /*
 214  * Handle a FW assertion reported in a mailbox.
 215  */
 216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 217 {
 218         struct fw_debug_cmd asrt;
 219
 220         get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 221         dev_alert(adap->pdev_dev,
 222                   "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 223                   asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 224                   be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 225 }
 226
 227 /**
 228  *      t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
 229  *      @adapter: the adapter
 230  *      @cmd: the Firmware Mailbox Command or Reply
 231  *      @size: command length in bytes
 232  *      @access: the time (ms) needed to access the Firmware Mailbox
 233  *      @execute: the time (ms) the command spent being executed
 234  */
 235 static void t4_record_mbox(struct adapter *adapter,
 236                            const __be64 *cmd, unsigned int size,
 237                            int access, int execute)
 238 {
 239         struct mbox_cmd_log *log = adapter->mbox_log;
 240         struct mbox_cmd *entry;
 241         int i;
 242
 243         entry = mbox_cmd_log_entry(log, log->cursor++);
 244         if (log->cursor == log->size)
 245                 log->cursor = 0;
 246
 247         for (i = 0; i < size / 8; i++)
 248                 entry->cmd[i] = be64_to_cpu(cmd[i]);
 249         while (i < MBOX_LEN / 8)
 250                 entry->cmd[i++] = 0;
 251         entry->timestamp = jiffies;
 252         entry->seqno = log->seqno++;
 253         entry->access = access;
 254         entry->execute = execute;
 255 }
 256
 257 /**
 258  *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 259  *      @adap: the adapter
 260  *      @mbox: index of the mailbox to use
 261  *      @cmd: the command to write
 262  *      @size: command length in bytes
 263  *      @rpl: where to optionally store the reply
 264  *      @sleep_ok: if true we may sleep while awaiting command completion
 265  *      @timeout: time to wait for command to finish before timing out
 266  *
 267  *      Sends the given command to FW through the selected mailbox and waits
 268  *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 269  *      store the FW's reply to the command.  The command and its optional
 270  *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 271  *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 272  *      the response.  If sleeping is allowed we use progressive backoff
 273  *      otherwise we spin.
 274  *
 275  *      The return value is 0 on success or a negative errno on failure.  A
 276  *      failure can happen either because we are not able to execute the
 277  *      command or FW executes it but signals an error.  In the latter case
 278  *      the return value is the error code indicated by FW (negated).
 279  */
 280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 281                             int size, void *rpl, bool sleep_ok, int timeout)
 282 {
 283         static const int delay[] = {
 284                 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 285         };
 286
 287         struct mbox_list entry;
 288         u16 access = 0;
 289         u16 execute = 0;
 290         u32 v;
 291         u64 res;
 292         int i, ms, delay_idx, ret;
 293         const __be64 *p = cmd;
 294         u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 295         u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 296         __be64 cmd_rpl[MBOX_LEN / 8];
 297         u32 pcie_fw;
 298
 299         if ((size & 15) || size > MBOX_LEN)
 300                 return -EINVAL;
 301
 302         /*
 303          * If the device is off-line, as in EEH, commands will time out.
 304          * Fail them early so we don't waste time waiting.
 305          */
 306         if (adap->pdev->error_state != pci_channel_io_normal)
 307                 return -EIO;
 308
 309         /* If we have a negative timeout, that implies that we can't sleep. */
 310         if (timeout < 0) {
 311                 sleep_ok = false;
 312                 timeout = -timeout;
 313         }
 314
 315         /* Queue ourselves onto the mailbox access list.  When our entry is at
 316          * the front of the list, we have rights to access the mailbox.  So we
 317          * wait [for a while] till we're at the front [or bail out with an
 318          * EBUSY] ...
 319          */
 320         spin_lock(&adap->mbox_lock);
 321         list_add_tail(&entry.list, &adap->mlist.list);
 322         spin_unlock(&adap->mbox_lock);
 323
 324         delay_idx = 0;
 325         ms = delay[0];
 326
 327         for (i = 0; ; i += ms) {
 328                 /* If we've waited too long, return a busy indication.  This
 329                  * really ought to be based on our initial position in the
 330                  * mailbox access list but this is a start.  We very rearely
 331                  * contend on access to the mailbox ...
 332                  */
 333                 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 334                 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
 335                         spin_lock(&adap->mbox_lock);
 336                         list_del(&entry.list);
 337                         spin_unlock(&adap->mbox_lock);
 338                         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
 339                         t4_record_mbox(adap, cmd, size, access, ret);
 340                         return ret;
 341                 }
 342
 343                 /* If we're at the head, break out and start the mailbox
 344                  * protocol.
 345                  */
 346                 if (list_first_entry(&adap->mlist.list, struct mbox_list,
 347                                      list) == &entry)
 348                         break;
 349
 350                 /* Delay for a bit before checking again ... */
 351                 if (sleep_ok) {
 352                         ms = delay[delay_idx];  /* last element may repeat */
 353                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 354                                 delay_idx++;
 355                         msleep(ms);
 356                 } else {
 357                         mdelay(ms);
 358                 }
 359         }
 360
 361         /* Loop trying to get ownership of the mailbox.  Return an error
 362          * if we can't gain ownership.
 363          */
 364         v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 365         for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 366                 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 367         if (v != MBOX_OWNER_DRV) {
 368                 spin_lock(&adap->mbox_lock);
 369                 list_del(&entry.list);
 370                 spin_unlock(&adap->mbox_lock);
 371                 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
 372                 t4_record_mbox(adap, cmd, size, access, ret);
 373                 return ret;
 374         }
 375
 376         /* Copy in the new mailbox command and send it on its way ... */
 377         t4_record_mbox(adap, cmd, size, access, 0);
 378         for (i = 0; i < size; i += 8)
 379                 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 380
 381         t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 382         t4_read_reg(adap, ctl_reg);          /* flush write */
 383
 384         delay_idx = 0;
 385         ms = delay[0];
 386
 387         for (i = 0;
 388              !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
 389              i < timeout;
 390              i += ms) {
 391                 if (sleep_ok) {
 392                         ms = delay[delay_idx];  /* last element may repeat */
 393                         if (delay_idx < ARRAY_SIZE(delay) - 1)
 394                                 delay_idx++;
 395                         msleep(ms);
 396                 } else
 397                         mdelay(ms);
 398
 399                 v = t4_read_reg(adap, ctl_reg);
 400                 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 401                         if (!(v & MBMSGVALID_F)) {
 402                                 t4_write_reg(adap, ctl_reg, 0);
 403                                 continue;
 404                         }
 405
 406                         get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
 407                         res = be64_to_cpu(cmd_rpl[0]);
 408
 409                         if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 410                                 fw_asrt(adap, data_reg);
 411                                 res = FW_CMD_RETVAL_V(EIO);
 412                         } else if (rpl) {
 413                                 memcpy(rpl, cmd_rpl, size);
 414                         }
 415
 416                         t4_write_reg(adap, ctl_reg, 0);
 417
 418                         execute = i + ms;
 419                         t4_record_mbox(adap, cmd_rpl,
 420                                        MBOX_LEN, access, execute);
 421                         spin_lock(&adap->mbox_lock);
 422                         list_del(&entry.list);
 423                         spin_unlock(&adap->mbox_lock);
 424                         return -FW_CMD_RETVAL_G((int)res);
 425                 }
 426         }
 427
 428         ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
 429         t4_record_mbox(adap, cmd, size, access, ret);
 430         dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 431                 *(const u8 *)cmd, mbox);
 432         t4_report_fw_error(adap);
 433         spin_lock(&adap->mbox_lock);
 434         list_del(&entry.list);
 435         spin_unlock(&adap->mbox_lock);
 436         t4_fatal_err(adap);
 437         return ret;
 438 }
 439
 440 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 441                     void *rpl, bool sleep_ok)
 442 {
 443         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 444                                        FW_CMD_MAX_TIMEOUT);
 445 }
 446
 447 static int t4_edc_err_read(struct adapter *adap, int idx)
 448 {
 449         u32 edc_ecc_err_addr_reg;
 450         u32 rdata_reg;
 451
 452         if (is_t4(adap->params.chip)) {
 453                 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 454                 return 0;
 455         }
 456         if (idx != 0 && idx != 1) {
 457                 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 458                 return 0;
 459         }
 460
 461         edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 462         rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 463
 464         CH_WARN(adap,
 465                 "edc%d err addr 0x%x: 0x%x.\n",
 466                 idx, edc_ecc_err_addr_reg,
 467                 t4_read_reg(adap, edc_ecc_err_addr_reg));
 468         CH_WARN(adap,
 469                 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 470                 rdata_reg,
 471                 (unsigned long long)t4_read_reg64(adap, rdata_reg),
 472                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 473                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 474                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 475                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 476                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 477                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 478                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 479                 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 480
 481         return 0;
 482 }
 483
 484 /**
 485  *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 486  *      @adap: the adapter
 487  *      @win: PCI-E Memory Window to use
 488  *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 489  *      @addr: address within indicated memory type
 490  *      @len: amount of memory to transfer
 491  *      @hbuf: host memory buffer
 492  *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 493  *
 494  *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 495  *      firmware memory address and host buffer must be aligned on 32-bit
 496  *      boudaries; the length may be arbitrary.  The memory is transferred as
 497  *      a raw byte sequence from/to the firmware's memory.  If this memory
 498  *      contains data structures which contain multi-byte integers, it's the
 499  *      caller's responsibility to perform appropriate byte order conversions.
 500  */
 501 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 502                  u32 len, void *hbuf, int dir)
 503 {
 504         u32 pos, offset, resid, memoffset;
 505         u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
 506         u32 *buf;
 507
 508         /* Argument sanity checks ...
 509          */
 510         if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 511                 return -EINVAL;
 512         buf = (u32 *)hbuf;
 513
 514         /* It's convenient to be able to handle lengths which aren't a
 515          * multiple of 32-bits because we often end up transferring files to
 516          * the firmware.  So we'll handle that by normalizing the length here
 517          * and then handling any residual transfer at the end.
 518          */
 519         resid = len & 0x3;
 520         len -= resid;
 521
 522         /* Offset into the region of memory which is being accessed
 523          * MEM_EDC0 = 0
 524          * MEM_EDC1 = 1
 525          * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 526          * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 527          */
 528         edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 529         if (mtype != MEM_MC1)
 530                 memoffset = (mtype * (edc_size * 1024 * 1024));
 531         else {
 532                 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 533                                                       MA_EXT_MEMORY0_BAR_A));
 534                 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 535         }
 536
 537         /* Determine the PCIE_MEM_ACCESS_OFFSET */
 538         addr = addr + memoffset;
 539
 540         /* Each PCI-E Memory Window is programmed with a window size -- or
 541          * "aperture" -- which controls the granularity of its mapping onto
 542          * adapter memory.  We need to grab that aperture in order to know
 543          * how to use the specified window.  The window is also programmed
 544          * with the base address of the Memory Window in BAR0's address
 545          * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 546          * the address is relative to BAR0.
 547          */
 548         mem_reg = t4_read_reg(adap,
 549                               PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 550                                                   win));
 551         mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 552         mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 553         if (is_t4(adap->params.chip))
 554                 mem_base -= adap->t4_bar0;
 555         win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 556
 557         /* Calculate our initial PCI-E Memory Window Position and Offset into
 558          * that Window.
 559          */
 560         pos = addr & ~(mem_aperture-1);
 561         offset = addr - pos;
 562
 563         /* Set up initial PCI-E Memory Window to cover the start of our
 564          * transfer.  (Read it back to ensure that changes propagate before we
 565          * attempt to use the new value.)
 566          */
 567         t4_write_reg(adap,
 568                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 569                      pos | win_pf);
 570         t4_read_reg(adap,
 571                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 572
 573         /* Transfer data to/from the adapter as long as there's an integral
 574          * number of 32-bit transfers to complete.
 575          *
 576          * A note on Endianness issues:
 577          *
 578          * The "register" reads and writes below from/to the PCI-E Memory
 579          * Window invoke the standard adapter Big-Endian to PCI-E Link
 580          * Little-Endian "swizzel."  As a result, if we have the following
 581          * data in adapter memory:
 582          *
 583          *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 584          *     Address:      i+0  i+1  i+2  i+3
 585          *
 586          * Then a read of the adapter memory via the PCI-E Memory Window
 587          * will yield:
 588          *
 589          *     x = readl(i)
 590          *         31                  0
 591          *         [ b3 | b2 | b1 | b0 ]
 592          *
 593          * If this value is stored into local memory on a Little-Endian system
 594          * it will show up correctly in local memory as:
 595          *
 596          *     ( ..., b0, b1, b2, b3, ... )
 597          *
 598          * But on a Big-Endian system, the store will show up in memory
 599          * incorrectly swizzled as:
 600          *
 601          *     ( ..., b3, b2, b1, b0, ... )
 602          *
 603          * So we need to account for this in the reads and writes to the
 604          * PCI-E Memory Window below by undoing the register read/write
 605          * swizzels.
 606          */
 607         while (len > 0) {
 608                 if (dir == T4_MEMORY_READ)
 609                         *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 610                                                 mem_base + offset));
 611                 else
 612                         t4_write_reg(adap, mem_base + offset,
 613                                      (__force u32)cpu_to_le32(*buf++));
 614                 offset += sizeof(__be32);
 615                 len -= sizeof(__be32);
 616
 617                 /* If we've reached the end of our current window aperture,
 618                  * move the PCI-E Memory Window on to the next.  Note that
 619                  * doing this here after "len" may be 0 allows us to set up
 620                  * the PCI-E Memory Window for a possible final residual
 621                  * transfer below ...
 622                  */
 623                 if (offset == mem_aperture) {
 624                         pos += mem_aperture;
 625                         offset = 0;
 626                         t4_write_reg(adap,
 627                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 628                                                     win), pos | win_pf);
 629                         t4_read_reg(adap,
 630                                 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
 631                                                     win));
 632                 }
 633         }
 634
 635         /* If the original transfer had a length which wasn't a multiple of
 636          * 32-bits, now's where we need to finish off the transfer of the
 637          * residual amount.  The PCI-E Memory Window has already been moved
 638          * above (if necessary) to cover this final transfer.
 639          */
 640         if (resid) {
 641                 union {
 642                         u32 word;
 643                         char byte[4];
 644                 } last;
 645                 unsigned char *bp;
 646                 int i;
 647
 648                 if (dir == T4_MEMORY_READ) {
 649                         last.word = le32_to_cpu(
 650                                         (__force __le32)t4_read_reg(adap,
 651                                                 mem_base + offset));
 652                         for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
 653                                 bp[i] = last.byte[i];
 654                 } else {
 655                         last.word = *buf;
 656                         for (i = resid; i < 4; i++)
 657                                 last.byte[i] = 0;
 658                         t4_write_reg(adap, mem_base + offset,
 659                                      (__force u32)cpu_to_le32(last.word));
 660                 }
 661         }
 662
 663         return 0;
 664 }
 665
 666 /* Return the specified PCI-E Configuration Space register from our Physical
 667  * Function.  We try first via a Firmware LDST Command since we prefer to let
 668  * the firmware own all of these registers, but if that fails we go for it
 669  * directly ourselves.
 670  */
 671 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 672 {
 673         u32 val, ldst_addrspace;
 674
 675         /* If fw_attach != 0, construct and send the Firmware LDST Command to
 676          * retrieve the specified PCI-E Configuration Space register.
 677          */
 678         struct fw_ldst_cmd ldst_cmd;
 679         int ret;
 680
 681         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 682         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 683         ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 684                                                FW_CMD_REQUEST_F |
 685                                                FW_CMD_READ_F |
 686                                                ldst_addrspace);
 687         ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 688         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 689         ldst_cmd.u.pcie.ctrl_to_fn =
 690                 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 691         ldst_cmd.u.pcie.r = reg;
 692
 693         /* If the LDST Command succeeds, return the result, otherwise
 694          * fall through to reading it directly ourselves ...
 695          */
 696         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 697                          &ldst_cmd);
 698         if (ret == 0)
 699                 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 700         else
 701                 /* Read the desired Configuration Space register via the PCI-E
 702                  * Backdoor mechanism.
 703                  */
 704                 t4_hw_pci_read_cfg4(adap, reg, &val);
 705         return val;
 706 }
 707
 708 /* Get the window based on base passed to it.
 709  * Window aperture is currently unhandled, but there is no use case for it
 710  * right now
 711  */
 712 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 713                          u32 memwin_base)
 714 {
 715         u32 ret;
 716
 717         if (is_t4(adap->params.chip)) {
 718                 u32 bar0;
 719
 720                 /* Truncation intentional: we only read the bottom 32-bits of
 721                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 722                  * mechanism to read BAR0 instead of using
 723                  * pci_resource_start() because we could be operating from
 724                  * within a Virtual Machine which is trapping our accesses to
 725                  * our Configuration Space and we need to set up the PCI-E
 726                  * Memory Window decoders with the actual addresses which will
 727                  * be coming across the PCI-E link.
 728                  */
 729                 bar0 = t4_read_pcie_cfg4(adap, pci_base);
 730                 bar0 &= pci_mask;
 731                 adap->t4_bar0 = bar0;
 732
 733                 ret = bar0 + memwin_base;
 734         } else {
 735                 /* For T5, only relative offset inside the PCIe BAR is passed */
 736                 ret = memwin_base;
 737         }
 738         return ret;
 739 }
 740
 741 /* Get the default utility window (win0) used by everyone */
 742 u32 t4_get_util_window(struct adapter *adap)
 743 {
 744         return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 745                              PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 746 }
 747
 748 /* Set up memory window for accessing adapter memory ranges.  (Read
 749  * back MA register to ensure that changes propagate before we attempt
 750  * to use the new values.)
 751  */
 752 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 753 {
 754         t4_write_reg(adap,
 755                      PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 756                      memwin_base | BIR_V(0) |
 757                      WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 758         t4_read_reg(adap,
 759                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 760 }
 761
 762 /**
 763  *      t4_get_regs_len - return the size of the chips register set
 764  *      @adapter: the adapter
 765  *
 766  *      Returns the size of the chip's BAR0 register space.
 767  */
 768 unsigned int t4_get_regs_len(struct adapter *adapter)
 769 {
 770         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 771
 772         switch (chip_version) {
 773         case CHELSIO_T4:
 774                 return T4_REGMAP_SIZE;
 775
 776         case CHELSIO_T5:
 777         case CHELSIO_T6:
 778                 return T5_REGMAP_SIZE;
 779         }
 780
 781         dev_err(adapter->pdev_dev,
 782                 "Unsupported chip version %d\n", chip_version);
 783         return 0;
 784 }
 785
 786 /**
 787  *      t4_get_regs - read chip registers into provided buffer
 788  *      @adap: the adapter
 789  *      @buf: register buffer
 790  *      @buf_size: size (in bytes) of register buffer
 791  *
 792  *      If the provided register buffer isn't large enough for the chip's
 793  *      full register range, the register dump will be truncated to the
 794  *      register buffer's size.
 795  */
 796 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 797 {
 798         static const unsigned int t4_reg_ranges[] = {
 799                 0x1008, 0x1108,
 800                 0x1180, 0x1184,
 801                 0x1190, 0x1194,
 802                 0x11a0, 0x11a4,
 803                 0x11b0, 0x11b4,
 804                 0x11fc, 0x123c,
 805                 0x1300, 0x173c,
 806                 0x1800, 0x18fc,
 807                 0x3000, 0x30d8,
 808                 0x30e0, 0x30e4,
 809                 0x30ec, 0x5910,
 810                 0x5920, 0x5924,
 811                 0x5960, 0x5960,
 812                 0x5968, 0x5968,
 813                 0x5970, 0x5970,
 814                 0x5978, 0x5978,
 815                 0x5980, 0x5980,
 816                 0x5988, 0x5988,
 817                 0x5990, 0x5990,
 818                 0x5998, 0x5998,
 819                 0x59a0, 0x59d4,
 820                 0x5a00, 0x5ae0,
 821                 0x5ae8, 0x5ae8,
 822                 0x5af0, 0x5af0,
 823                 0x5af8, 0x5af8,
 824                 0x6000, 0x6098,
 825                 0x6100, 0x6150,
 826                 0x6200, 0x6208,
 827                 0x6240, 0x6248,
 828                 0x6280, 0x62b0,
 829                 0x62c0, 0x6338,
 830                 0x6370, 0x638c,
 831                 0x6400, 0x643c,
 832                 0x6500, 0x6524,
 833                 0x6a00, 0x6a04,
 834                 0x6a14, 0x6a38,
 835                 0x6a60, 0x6a70,
 836                 0x6a78, 0x6a78,
 837                 0x6b00, 0x6b0c,
 838                 0x6b1c, 0x6b84,
 839                 0x6bf0, 0x6bf8,
 840                 0x6c00, 0x6c0c,
 841                 0x6c1c, 0x6c84,
 842                 0x6cf0, 0x6cf8,
 843                 0x6d00, 0x6d0c,
 844                 0x6d1c, 0x6d84,
 845                 0x6df0, 0x6df8,
 846                 0x6e00, 0x6e0c,
 847                 0x6e1c, 0x6e84,
 848                 0x6ef0, 0x6ef8,
 849                 0x6f00, 0x6f0c,
 850                 0x6f1c, 0x6f84,
 851                 0x6ff0, 0x6ff8,
 852                 0x7000, 0x700c,
 853                 0x701c, 0x7084,
 854                 0x70f0, 0x70f8,
 855                 0x7100, 0x710c,
 856                 0x711c, 0x7184,
 857                 0x71f0, 0x71f8,
 858                 0x7200, 0x720c,
 859                 0x721c, 0x7284,
 860                 0x72f0, 0x72f8,
 861                 0x7300, 0x730c,
 862                 0x731c, 0x7384,
 863                 0x73f0, 0x73f8,
 864                 0x7400, 0x7450,
 865                 0x7500, 0x7530,
 866                 0x7600, 0x760c,
 867                 0x7614, 0x761c,
 868                 0x7680, 0x76cc,
 869                 0x7700, 0x7798,
 870                 0x77c0, 0x77fc,
 871                 0x7900, 0x79fc,
 872                 0x7b00, 0x7b58,
 873                 0x7b60, 0x7b84,
 874                 0x7b8c, 0x7c38,
 875                 0x7d00, 0x7d38,
 876                 0x7d40, 0x7d80,
 877                 0x7d8c, 0x7ddc,
 878                 0x7de4, 0x7e04,
 879                 0x7e10, 0x7e1c,
 880                 0x7e24, 0x7e38,
 881                 0x7e40, 0x7e44,
 882                 0x7e4c, 0x7e78,
 883                 0x7e80, 0x7ea4,
 884                 0x7eac, 0x7edc,
 885                 0x7ee8, 0x7efc,
 886                 0x8dc0, 0x8e04,
 887                 0x8e10, 0x8e1c,
 888                 0x8e30, 0x8e78,
 889                 0x8ea0, 0x8eb8,
 890                 0x8ec0, 0x8f6c,
 891                 0x8fc0, 0x9008,
 892                 0x9010, 0x9058,
 893                 0x9060, 0x9060,
 894                 0x9068, 0x9074,
 895                 0x90fc, 0x90fc,
 896                 0x9400, 0x9408,
 897                 0x9410, 0x9458,
 898                 0x9600, 0x9600,
 899                 0x9608, 0x9638,
 900                 0x9640, 0x96bc,
 901                 0x9800, 0x9808,
 902                 0x9820, 0x983c,
 903                 0x9850, 0x9864,
 904                 0x9c00, 0x9c6c,
 905                 0x9c80, 0x9cec,
 906                 0x9d00, 0x9d6c,
 907                 0x9d80, 0x9dec,
 908                 0x9e00, 0x9e6c,
 909                 0x9e80, 0x9eec,
 910                 0x9f00, 0x9f6c,
 911                 0x9f80, 0x9fec,
 912                 0xd004, 0xd004,
 913                 0xd010, 0xd03c,
 914                 0xdfc0, 0xdfe0,
 915                 0xe000, 0xea7c,
 916                 0xf000, 0x11110,
 917                 0x11118, 0x11190,
 918                 0x19040, 0x1906c,
 919                 0x19078, 0x19080,
 920                 0x1908c, 0x190e4,
 921                 0x190f0, 0x190f8,
 922                 0x19100, 0x19110,
 923                 0x19120, 0x19124,
 924                 0x19150, 0x19194,
 925                 0x1919c, 0x191b0,
 926                 0x191d0, 0x191e8,
 927                 0x19238, 0x1924c,
 928                 0x193f8, 0x1943c,
 929                 0x1944c, 0x19474,
 930                 0x19490, 0x194e0,
 931                 0x194f0, 0x194f8,
 932                 0x19800, 0x19c08,
 933                 0x19c10, 0x19c90,
 934                 0x19ca0, 0x19ce4,
 935                 0x19cf0, 0x19d40,
 936                 0x19d50, 0x19d94,
 937                 0x19da0, 0x19de8,
 938                 0x19df0, 0x19e40,
 939                 0x19e50, 0x19e90,
 940                 0x19ea0, 0x19f4c,
 941                 0x1a000, 0x1a004,
 942                 0x1a010, 0x1a06c,
 943                 0x1a0b0, 0x1a0e4,
 944                 0x1a0ec, 0x1a0f4,
 945                 0x1a100, 0x1a108,
 946                 0x1a114, 0x1a120,
 947                 0x1a128, 0x1a130,
 948                 0x1a138, 0x1a138,
 949                 0x1a190, 0x1a1c4,
 950                 0x1a1fc, 0x1a1fc,
 951                 0x1e040, 0x1e04c,
 952                 0x1e284, 0x1e28c,
 953                 0x1e2c0, 0x1e2c0,
 954                 0x1e2e0, 0x1e2e0,
 955                 0x1e300, 0x1e384,
 956                 0x1e3c0, 0x1e3c8,
 957                 0x1e440, 0x1e44c,
 958                 0x1e684, 0x1e68c,
 959                 0x1e6c0, 0x1e6c0,
 960                 0x1e6e0, 0x1e6e0,
 961                 0x1e700, 0x1e784,
 962                 0x1e7c0, 0x1e7c8,
 963                 0x1e840, 0x1e84c,
 964                 0x1ea84, 0x1ea8c,
 965                 0x1eac0, 0x1eac0,
 966                 0x1eae0, 0x1eae0,
 967                 0x1eb00, 0x1eb84,
 968                 0x1ebc0, 0x1ebc8,
 969                 0x1ec40, 0x1ec4c,
 970                 0x1ee84, 0x1ee8c,
 971                 0x1eec0, 0x1eec0,
 972                 0x1eee0, 0x1eee0,
 973                 0x1ef00, 0x1ef84,
 974                 0x1efc0, 0x1efc8,
 975                 0x1f040, 0x1f04c,
 976                 0x1f284, 0x1f28c,
 977                 0x1f2c0, 0x1f2c0,
 978                 0x1f2e0, 0x1f2e0,
 979                 0x1f300, 0x1f384,
 980                 0x1f3c0, 0x1f3c8,
 981                 0x1f440, 0x1f44c,
 982                 0x1f684, 0x1f68c,
 983                 0x1f6c0, 0x1f6c0,
 984                 0x1f6e0, 0x1f6e0,
 985                 0x1f700, 0x1f784,
 986                 0x1f7c0, 0x1f7c8,
 987                 0x1f840, 0x1f84c,
 988                 0x1fa84, 0x1fa8c,
 989                 0x1fac0, 0x1fac0,
 990                 0x1fae0, 0x1fae0,
 991                 0x1fb00, 0x1fb84,
 992                 0x1fbc0, 0x1fbc8,
 993                 0x1fc40, 0x1fc4c,
 994                 0x1fe84, 0x1fe8c,
 995                 0x1fec0, 0x1fec0,
 996                 0x1fee0, 0x1fee0,
 997                 0x1ff00, 0x1ff84,
 998                 0x1ffc0, 0x1ffc8,
 999                 0x20000, 0x2002c,
1000                 0x20100, 0x2013c,
1001                 0x20190, 0x201a0,
1002                 0x201a8, 0x201b8,
1003                 0x201c4, 0x201c8,
1004                 0x20200, 0x20318,
1005                 0x20400, 0x204b4,
1006                 0x204c0, 0x20528,
1007                 0x20540, 0x20614,
1008                 0x21000, 0x21040,
1009                 0x2104c, 0x21060,
1010                 0x210c0, 0x210ec,
1011                 0x21200, 0x21268,
1012                 0x21270, 0x21284,
1013                 0x212fc, 0x21388,
1014                 0x21400, 0x21404,
1015                 0x21500, 0x21500,
1016                 0x21510, 0x21518,
1017                 0x2152c, 0x21530,
1018                 0x2153c, 0x2153c,
1019                 0x21550, 0x21554,
1020                 0x21600, 0x21600,
1021                 0x21608, 0x2161c,
1022                 0x21624, 0x21628,
1023                 0x21630, 0x21634,
1024                 0x2163c, 0x2163c,
1025                 0x21700, 0x2171c,
1026                 0x21780, 0x2178c,
1027                 0x21800, 0x21818,
1028                 0x21820, 0x21828,
1029                 0x21830, 0x21848,
1030                 0x21850, 0x21854,
1031                 0x21860, 0x21868,
1032                 0x21870, 0x21870,
1033                 0x21878, 0x21898,
1034                 0x218a0, 0x218a8,
1035                 0x218b0, 0x218c8,
1036                 0x218d0, 0x218d4,
1037                 0x218e0, 0x218e8,
1038                 0x218f0, 0x218f0,
1039                 0x218f8, 0x21a18,
1040                 0x21a20, 0x21a28,
1041                 0x21a30, 0x21a48,
1042                 0x21a50, 0x21a54,
1043                 0x21a60, 0x21a68,
1044                 0x21a70, 0x21a70,
1045                 0x21a78, 0x21a98,
1046                 0x21aa0, 0x21aa8,
1047                 0x21ab0, 0x21ac8,
1048                 0x21ad0, 0x21ad4,
1049                 0x21ae0, 0x21ae8,
1050                 0x21af0, 0x21af0,
1051                 0x21af8, 0x21c18,
1052                 0x21c20, 0x21c20,
1053                 0x21c28, 0x21c30,
1054                 0x21c38, 0x21c38,
1055                 0x21c80, 0x21c98,
1056                 0x21ca0, 0x21ca8,
1057                 0x21cb0, 0x21cc8,
1058                 0x21cd0, 0x21cd4,
1059                 0x21ce0, 0x21ce8,
1060                 0x21cf0, 0x21cf0,
1061                 0x21cf8, 0x21d7c,
1062                 0x21e00, 0x21e04,
1063                 0x22000, 0x2202c,
1064                 0x22100, 0x2213c,
1065                 0x22190, 0x221a0,
1066                 0x221a8, 0x221b8,
1067                 0x221c4, 0x221c8,
1068                 0x22200, 0x22318,
1069                 0x22400, 0x224b4,
1070                 0x224c0, 0x22528,
1071                 0x22540, 0x22614,
1072                 0x23000, 0x23040,
1073                 0x2304c, 0x23060,
1074                 0x230c0, 0x230ec,
1075                 0x23200, 0x23268,
1076                 0x23270, 0x23284,
1077                 0x232fc, 0x23388,
1078                 0x23400, 0x23404,
1079                 0x23500, 0x23500,
1080                 0x23510, 0x23518,
1081                 0x2352c, 0x23530,
1082                 0x2353c, 0x2353c,
1083                 0x23550, 0x23554,
1084                 0x23600, 0x23600,
1085                 0x23608, 0x2361c,
1086                 0x23624, 0x23628,
1087                 0x23630, 0x23634,
1088                 0x2363c, 0x2363c,
1089                 0x23700, 0x2371c,
1090                 0x23780, 0x2378c,
1091                 0x23800, 0x23818,
1092                 0x23820, 0x23828,
1093                 0x23830, 0x23848,
1094                 0x23850, 0x23854,
1095                 0x23860, 0x23868,
1096                 0x23870, 0x23870,
1097                 0x23878, 0x23898,
1098                 0x238a0, 0x238a8,
1099                 0x238b0, 0x238c8,
1100                 0x238d0, 0x238d4,
1101                 0x238e0, 0x238e8,
1102                 0x238f0, 0x238f0,
1103                 0x238f8, 0x23a18,
1104                 0x23a20, 0x23a28,
1105                 0x23a30, 0x23a48,
1106                 0x23a50, 0x23a54,
1107                 0x23a60, 0x23a68,
1108                 0x23a70, 0x23a70,
1109                 0x23a78, 0x23a98,
1110                 0x23aa0, 0x23aa8,
1111                 0x23ab0, 0x23ac8,
1112                 0x23ad0, 0x23ad4,
1113                 0x23ae0, 0x23ae8,
1114                 0x23af0, 0x23af0,
1115                 0x23af8, 0x23c18,
1116                 0x23c20, 0x23c20,
1117                 0x23c28, 0x23c30,
1118                 0x23c38, 0x23c38,
1119                 0x23c80, 0x23c98,
1120                 0x23ca0, 0x23ca8,
1121                 0x23cb0, 0x23cc8,
1122                 0x23cd0, 0x23cd4,
1123                 0x23ce0, 0x23ce8,
1124                 0x23cf0, 0x23cf0,
1125                 0x23cf8, 0x23d7c,
1126                 0x23e00, 0x23e04,
1127                 0x24000, 0x2402c,
1128                 0x24100, 0x2413c,
1129                 0x24190, 0x241a0,
1130                 0x241a8, 0x241b8,
1131                 0x241c4, 0x241c8,
1132                 0x24200, 0x24318,
1133                 0x24400, 0x244b4,
1134                 0x244c0, 0x24528,
1135                 0x24540, 0x24614,
1136                 0x25000, 0x25040,
1137                 0x2504c, 0x25060,
1138                 0x250c0, 0x250ec,
1139                 0x25200, 0x25268,
1140                 0x25270, 0x25284,
1141                 0x252fc, 0x25388,
1142                 0x25400, 0x25404,
1143                 0x25500, 0x25500,
1144                 0x25510, 0x25518,
1145                 0x2552c, 0x25530,
1146                 0x2553c, 0x2553c,
1147                 0x25550, 0x25554,
1148                 0x25600, 0x25600,
1149                 0x25608, 0x2561c,
1150                 0x25624, 0x25628,
1151                 0x25630, 0x25634,
1152                 0x2563c, 0x2563c,
1153                 0x25700, 0x2571c,
1154                 0x25780, 0x2578c,
1155                 0x25800, 0x25818,
1156                 0x25820, 0x25828,
1157                 0x25830, 0x25848,
1158                 0x25850, 0x25854,
1159                 0x25860, 0x25868,
1160                 0x25870, 0x25870,
1161                 0x25878, 0x25898,
1162                 0x258a0, 0x258a8,
1163                 0x258b0, 0x258c8,
1164                 0x258d0, 0x258d4,
1165                 0x258e0, 0x258e8,
1166                 0x258f0, 0x258f0,
1167                 0x258f8, 0x25a18,
1168                 0x25a20, 0x25a28,
1169                 0x25a30, 0x25a48,
1170                 0x25a50, 0x25a54,
1171                 0x25a60, 0x25a68,
1172                 0x25a70, 0x25a70,
1173                 0x25a78, 0x25a98,
1174                 0x25aa0, 0x25aa8,
1175                 0x25ab0, 0x25ac8,
1176                 0x25ad0, 0x25ad4,
1177                 0x25ae0, 0x25ae8,
1178                 0x25af0, 0x25af0,
1179                 0x25af8, 0x25c18,
1180                 0x25c20, 0x25c20,
1181                 0x25c28, 0x25c30,
1182                 0x25c38, 0x25c38,
1183                 0x25c80, 0x25c98,
1184                 0x25ca0, 0x25ca8,
1185                 0x25cb0, 0x25cc8,
1186                 0x25cd0, 0x25cd4,
1187                 0x25ce0, 0x25ce8,
1188                 0x25cf0, 0x25cf0,
1189                 0x25cf8, 0x25d7c,
1190                 0x25e00, 0x25e04,
1191                 0x26000, 0x2602c,
1192                 0x26100, 0x2613c,
1193                 0x26190, 0x261a0,
1194                 0x261a8, 0x261b8,
1195                 0x261c4, 0x261c8,
1196                 0x26200, 0x26318,
1197                 0x26400, 0x264b4,
1198                 0x264c0, 0x26528,
1199                 0x26540, 0x26614,
1200                 0x27000, 0x27040,
1201                 0x2704c, 0x27060,
1202                 0x270c0, 0x270ec,
1203                 0x27200, 0x27268,
1204                 0x27270, 0x27284,
1205                 0x272fc, 0x27388,
1206                 0x27400, 0x27404,
1207                 0x27500, 0x27500,
1208                 0x27510, 0x27518,
1209                 0x2752c, 0x27530,
1210                 0x2753c, 0x2753c,
1211                 0x27550, 0x27554,
1212                 0x27600, 0x27600,
1213                 0x27608, 0x2761c,
1214                 0x27624, 0x27628,
1215                 0x27630, 0x27634,
1216                 0x2763c, 0x2763c,
1217                 0x27700, 0x2771c,
1218                 0x27780, 0x2778c,
1219                 0x27800, 0x27818,
1220                 0x27820, 0x27828,
1221                 0x27830, 0x27848,
1222                 0x27850, 0x27854,
1223                 0x27860, 0x27868,
1224                 0x27870, 0x27870,
1225                 0x27878, 0x27898,
1226                 0x278a0, 0x278a8,
1227                 0x278b0, 0x278c8,
1228                 0x278d0, 0x278d4,
1229                 0x278e0, 0x278e8,
1230                 0x278f0, 0x278f0,
1231                 0x278f8, 0x27a18,
1232                 0x27a20, 0x27a28,
1233                 0x27a30, 0x27a48,
1234                 0x27a50, 0x27a54,
1235                 0x27a60, 0x27a68,
1236                 0x27a70, 0x27a70,
1237                 0x27a78, 0x27a98,
1238                 0x27aa0, 0x27aa8,
1239                 0x27ab0, 0x27ac8,
1240                 0x27ad0, 0x27ad4,
1241                 0x27ae0, 0x27ae8,
1242                 0x27af0, 0x27af0,
1243                 0x27af8, 0x27c18,
1244                 0x27c20, 0x27c20,
1245                 0x27c28, 0x27c30,
1246                 0x27c38, 0x27c38,
1247                 0x27c80, 0x27c98,
1248                 0x27ca0, 0x27ca8,
1249                 0x27cb0, 0x27cc8,
1250                 0x27cd0, 0x27cd4,
1251                 0x27ce0, 0x27ce8,
1252                 0x27cf0, 0x27cf0,
1253                 0x27cf8, 0x27d7c,
1254                 0x27e00, 0x27e04,
1255         };
1256
1257         static const unsigned int t5_reg_ranges[] = {
1258                 0x1008, 0x10c0,
1259                 0x10cc, 0x10f8,
1260                 0x1100, 0x1100,
1261                 0x110c, 0x1148,
1262                 0x1180, 0x1184,
1263                 0x1190, 0x1194,
1264                 0x11a0, 0x11a4,
1265                 0x11b0, 0x11b4,
1266                 0x11fc, 0x123c,
1267                 0x1280, 0x173c,
1268                 0x1800, 0x18fc,
1269                 0x3000, 0x3028,
1270                 0x3060, 0x30b0,
1271                 0x30b8, 0x30d8,
1272                 0x30e0, 0x30fc,
1273                 0x3140, 0x357c,
1274                 0x35a8, 0x35cc,
1275                 0x35ec, 0x35ec,
1276                 0x3600, 0x5624,
1277                 0x56cc, 0x56ec,
1278                 0x56f4, 0x5720,
1279                 0x5728, 0x575c,
1280                 0x580c, 0x5814,
1281                 0x5890, 0x589c,
1282                 0x58a4, 0x58ac,
1283                 0x58b8, 0x58bc,
1284                 0x5940, 0x59c8,
1285                 0x59d0, 0x59dc,
1286                 0x59fc, 0x5a18,
1287                 0x5a60, 0x5a70,
1288                 0x5a80, 0x5a9c,
1289                 0x5b94, 0x5bfc,
1290                 0x6000, 0x6020,
1291                 0x6028, 0x6040,
1292                 0x6058, 0x609c,
1293                 0x60a8, 0x614c,
1294                 0x7700, 0x7798,
1295                 0x77c0, 0x78fc,
1296                 0x7b00, 0x7b58,
1297                 0x7b60, 0x7b84,
1298                 0x7b8c, 0x7c54,
1299                 0x7d00, 0x7d38,
1300                 0x7d40, 0x7d80,
1301                 0x7d8c, 0x7ddc,
1302                 0x7de4, 0x7e04,
1303                 0x7e10, 0x7e1c,
1304                 0x7e24, 0x7e38,
1305                 0x7e40, 0x7e44,
1306                 0x7e4c, 0x7e78,
1307                 0x7e80, 0x7edc,
1308                 0x7ee8, 0x7efc,
1309                 0x8dc0, 0x8de0,
1310                 0x8df8, 0x8e04,
1311                 0x8e10, 0x8e84,
1312                 0x8ea0, 0x8f84,
1313                 0x8fc0, 0x9058,
1314                 0x9060, 0x9060,
1315                 0x9068, 0x90f8,
1316                 0x9400, 0x9408,
1317                 0x9410, 0x9470,
1318                 0x9600, 0x9600,
1319                 0x9608, 0x9638,
1320                 0x9640, 0x96f4,
1321                 0x9800, 0x9808,
1322                 0x9820, 0x983c,
1323                 0x9850, 0x9864,
1324                 0x9c00, 0x9c6c,
1325                 0x9c80, 0x9cec,
1326                 0x9d00, 0x9d6c,
1327                 0x9d80, 0x9dec,
1328                 0x9e00, 0x9e6c,
1329                 0x9e80, 0x9eec,
1330                 0x9f00, 0x9f6c,
1331                 0x9f80, 0xa020,
1332                 0xd004, 0xd004,
1333                 0xd010, 0xd03c,
1334                 0xdfc0, 0xdfe0,
1335                 0xe000, 0x1106c,
1336                 0x11074, 0x11088,
1337                 0x1109c, 0x1117c,
1338                 0x11190, 0x11204,
1339                 0x19040, 0x1906c,
1340                 0x19078, 0x19080,
1341                 0x1908c, 0x190e8,
1342                 0x190f0, 0x190f8,
1343                 0x19100, 0x19110,
1344                 0x19120, 0x19124,
1345                 0x19150, 0x19194,
1346                 0x1919c, 0x191b0,
1347                 0x191d0, 0x191e8,
1348                 0x19238, 0x19290,
1349                 0x193f8, 0x19428,
1350                 0x19430, 0x19444,
1351                 0x1944c, 0x1946c,
1352                 0x19474, 0x19474,
1353                 0x19490, 0x194cc,
1354                 0x194f0, 0x194f8,
1355                 0x19c00, 0x19c08,
1356                 0x19c10, 0x19c60,
1357                 0x19c94, 0x19ce4,
1358                 0x19cf0, 0x19d40,
1359                 0x19d50, 0x19d94,
1360                 0x19da0, 0x19de8,
1361                 0x19df0, 0x19e10,
1362                 0x19e50, 0x19e90,
1363                 0x19ea0, 0x19f24,
1364                 0x19f34, 0x19f34,
1365                 0x19f40, 0x19f50,
1366                 0x19f90, 0x19fb4,
1367                 0x19fc4, 0x19fe4,
1368                 0x1a000, 0x1a004,
1369                 0x1a010, 0x1a06c,
1370                 0x1a0b0, 0x1a0e4,
1371                 0x1a0ec, 0x1a0f8,
1372                 0x1a100, 0x1a108,
1373                 0x1a114, 0x1a120,
1374                 0x1a128, 0x1a130,
1375                 0x1a138, 0x1a138,
1376                 0x1a190, 0x1a1c4,
1377                 0x1a1fc, 0x1a1fc,
1378                 0x1e008, 0x1e00c,
1379                 0x1e040, 0x1e044,
1380                 0x1e04c, 0x1e04c,
1381                 0x1e284, 0x1e290,
1382                 0x1e2c0, 0x1e2c0,
1383                 0x1e2e0, 0x1e2e0,
1384                 0x1e300, 0x1e384,
1385                 0x1e3c0, 0x1e3c8,
1386                 0x1e408, 0x1e40c,
1387                 0x1e440, 0x1e444,
1388                 0x1e44c, 0x1e44c,
1389                 0x1e684, 0x1e690,
1390                 0x1e6c0, 0x1e6c0,
1391                 0x1e6e0, 0x1e6e0,
1392                 0x1e700, 0x1e784,
1393                 0x1e7c0, 0x1e7c8,
1394                 0x1e808, 0x1e80c,
1395                 0x1e840, 0x1e844,
1396                 0x1e84c, 0x1e84c,
1397                 0x1ea84, 0x1ea90,
1398                 0x1eac0, 0x1eac0,
1399                 0x1eae0, 0x1eae0,
1400                 0x1eb00, 0x1eb84,
1401                 0x1ebc0, 0x1ebc8,
1402                 0x1ec08, 0x1ec0c,
1403                 0x1ec40, 0x1ec44,
1404                 0x1ec4c, 0x1ec4c,
1405                 0x1ee84, 0x1ee90,
1406                 0x1eec0, 0x1eec0,
1407                 0x1eee0, 0x1eee0,
1408                 0x1ef00, 0x1ef84,
1409                 0x1efc0, 0x1efc8,
1410                 0x1f008, 0x1f00c,
1411                 0x1f040, 0x1f044,
1412                 0x1f04c, 0x1f04c,
1413                 0x1f284, 0x1f290,
1414                 0x1f2c0, 0x1f2c0,
1415                 0x1f2e0, 0x1f2e0,
1416                 0x1f300, 0x1f384,
1417                 0x1f3c0, 0x1f3c8,
1418                 0x1f408, 0x1f40c,
1419                 0x1f440, 0x1f444,
1420                 0x1f44c, 0x1f44c,
1421                 0x1f684, 0x1f690,
1422                 0x1f6c0, 0x1f6c0,
1423                 0x1f6e0, 0x1f6e0,
1424                 0x1f700, 0x1f784,
1425                 0x1f7c0, 0x1f7c8,
1426                 0x1f808, 0x1f80c,
1427                 0x1f840, 0x1f844,
1428                 0x1f84c, 0x1f84c,
1429                 0x1fa84, 0x1fa90,
1430                 0x1fac0, 0x1fac0,
1431                 0x1fae0, 0x1fae0,
1432                 0x1fb00, 0x1fb84,
1433                 0x1fbc0, 0x1fbc8,
1434                 0x1fc08, 0x1fc0c,
1435                 0x1fc40, 0x1fc44,
1436                 0x1fc4c, 0x1fc4c,
1437                 0x1fe84, 0x1fe90,
1438                 0x1fec0, 0x1fec0,
1439                 0x1fee0, 0x1fee0,
1440                 0x1ff00, 0x1ff84,
1441                 0x1ffc0, 0x1ffc8,
1442                 0x30000, 0x30030,
1443                 0x30100, 0x30144,
1444                 0x30190, 0x301a0,
1445                 0x301a8, 0x301b8,
1446                 0x301c4, 0x301c8,
1447                 0x301d0, 0x301d0,
1448                 0x30200, 0x30318,
1449                 0x30400, 0x304b4,
1450                 0x304c0, 0x3052c,
1451                 0x30540, 0x3061c,
1452                 0x30800, 0x30828,
1453                 0x30834, 0x30834,
1454                 0x308c0, 0x30908,
1455                 0x30910, 0x309ac,
1456                 0x30a00, 0x30a14,
1457                 0x30a1c, 0x30a2c,
1458                 0x30a44, 0x30a50,
1459                 0x30a74, 0x30a74,
1460                 0x30a7c, 0x30afc,
1461                 0x30b08, 0x30c24,
1462                 0x30d00, 0x30d00,
1463                 0x30d08, 0x30d14,
1464                 0x30d1c, 0x30d20,
1465                 0x30d3c, 0x30d3c,
1466                 0x30d48, 0x30d50,
1467                 0x31200, 0x3120c,
1468                 0x31220, 0x31220,
1469                 0x31240, 0x31240,
1470                 0x31600, 0x3160c,
1471                 0x31a00, 0x31a1c,
1472                 0x31e00, 0x31e20,
1473                 0x31e38, 0x31e3c,
1474                 0x31e80, 0x31e80,
1475                 0x31e88, 0x31ea8,
1476                 0x31eb0, 0x31eb4,
1477                 0x31ec8, 0x31ed4,
1478                 0x31fb8, 0x32004,
1479                 0x32200, 0x32200,
1480                 0x32208, 0x32240,
1481                 0x32248, 0x32280,
1482                 0x32288, 0x322c0,
1483                 0x322c8, 0x322fc,
1484                 0x32600, 0x32630,
1485                 0x32a00, 0x32abc,
1486                 0x32b00, 0x32b10,
1487                 0x32b20, 0x32b30,
1488                 0x32b40, 0x32b50,
1489                 0x32b60, 0x32b70,
1490                 0x33000, 0x33028,
1491                 0x33030, 0x33048,
1492                 0x33060, 0x33068,
1493                 0x33070, 0x3309c,
1494                 0x330f0, 0x33128,
1495                 0x33130, 0x33148,
1496                 0x33160, 0x33168,
1497                 0x33170, 0x3319c,
1498                 0x331f0, 0x33238,
1499                 0x33240, 0x33240,
1500                 0x33248, 0x33250,
1501                 0x3325c, 0x33264,
1502                 0x33270, 0x332b8,
1503                 0x332c0, 0x332e4,
1504                 0x332f8, 0x33338,
1505                 0x33340, 0x33340,
1506                 0x33348, 0x33350,
1507                 0x3335c, 0x33364,
1508                 0x33370, 0x333b8,
1509                 0x333c0, 0x333e4,
1510                 0x333f8, 0x33428,
1511                 0x33430, 0x33448,
1512                 0x33460, 0x33468,
1513                 0x33470, 0x3349c,
1514                 0x334f0, 0x33528,
1515                 0x33530, 0x33548,
1516                 0x33560, 0x33568,
1517                 0x33570, 0x3359c,
1518                 0x335f0, 0x33638,
1519                 0x33640, 0x33640,
1520                 0x33648, 0x33650,
1521                 0x3365c, 0x33664,
1522                 0x33670, 0x336b8,
1523                 0x336c0, 0x336e4,
1524                 0x336f8, 0x33738,
1525                 0x33740, 0x33740,
1526                 0x33748, 0x33750,
1527                 0x3375c, 0x33764,
1528                 0x33770, 0x337b8,
1529                 0x337c0, 0x337e4,
1530                 0x337f8, 0x337fc,
1531                 0x33814, 0x33814,
1532                 0x3382c, 0x3382c,
1533                 0x33880, 0x3388c,
1534                 0x338e8, 0x338ec,
1535                 0x33900, 0x33928,
1536                 0x33930, 0x33948,
1537                 0x33960, 0x33968,
1538                 0x33970, 0x3399c,
1539                 0x339f0, 0x33a38,
1540                 0x33a40, 0x33a40,
1541                 0x33a48, 0x33a50,
1542                 0x33a5c, 0x33a64,
1543                 0x33a70, 0x33ab8,
1544                 0x33ac0, 0x33ae4,
1545                 0x33af8, 0x33b10,
1546                 0x33b28, 0x33b28,
1547                 0x33b3c, 0x33b50,
1548                 0x33bf0, 0x33c10,
1549                 0x33c28, 0x33c28,
1550                 0x33c3c, 0x33c50,
1551                 0x33cf0, 0x33cfc,
1552                 0x34000, 0x34030,
1553                 0x34100, 0x34144,
1554                 0x34190, 0x341a0,
1555                 0x341a8, 0x341b8,
1556                 0x341c4, 0x341c8,
1557                 0x341d0, 0x341d0,
1558                 0x34200, 0x34318,
1559                 0x34400, 0x344b4,
1560                 0x344c0, 0x3452c,
1561                 0x34540, 0x3461c,
1562                 0x34800, 0x34828,
1563                 0x34834, 0x34834,
1564                 0x348c0, 0x34908,
1565                 0x34910, 0x349ac,
1566                 0x34a00, 0x34a14,
1567                 0x34a1c, 0x34a2c,
1568                 0x34a44, 0x34a50,
1569                 0x34a74, 0x34a74,
1570                 0x34a7c, 0x34afc,
1571                 0x34b08, 0x34c24,
1572                 0x34d00, 0x34d00,
1573                 0x34d08, 0x34d14,
1574                 0x34d1c, 0x34d20,
1575                 0x34d3c, 0x34d3c,
1576                 0x34d48, 0x34d50,
1577                 0x35200, 0x3520c,
1578                 0x35220, 0x35220,
1579                 0x35240, 0x35240,
1580                 0x35600, 0x3560c,
1581                 0x35a00, 0x35a1c,
1582                 0x35e00, 0x35e20,
1583                 0x35e38, 0x35e3c,
1584                 0x35e80, 0x35e80,
1585                 0x35e88, 0x35ea8,
1586                 0x35eb0, 0x35eb4,
1587                 0x35ec8, 0x35ed4,
1588                 0x35fb8, 0x36004,
1589                 0x36200, 0x36200,
1590                 0x36208, 0x36240,
1591                 0x36248, 0x36280,
1592                 0x36288, 0x362c0,
1593                 0x362c8, 0x362fc,
1594                 0x36600, 0x36630,
1595                 0x36a00, 0x36abc,
1596                 0x36b00, 0x36b10,
1597                 0x36b20, 0x36b30,
1598                 0x36b40, 0x36b50,
1599                 0x36b60, 0x36b70,
1600                 0x37000, 0x37028,
1601                 0x37030, 0x37048,
1602                 0x37060, 0x37068,
1603                 0x37070, 0x3709c,
1604                 0x370f0, 0x37128,
1605                 0x37130, 0x37148,
1606                 0x37160, 0x37168,
1607                 0x37170, 0x3719c,
1608                 0x371f0, 0x37238,
1609                 0x37240, 0x37240,
1610                 0x37248, 0x37250,
1611                 0x3725c, 0x37264,
1612                 0x37270, 0x372b8,
1613                 0x372c0, 0x372e4,
1614                 0x372f8, 0x37338,
1615                 0x37340, 0x37340,
1616                 0x37348, 0x37350,
1617                 0x3735c, 0x37364,
1618                 0x37370, 0x373b8,
1619                 0x373c0, 0x373e4,
1620                 0x373f8, 0x37428,
1621                 0x37430, 0x37448,
1622                 0x37460, 0x37468,
1623                 0x37470, 0x3749c,
1624                 0x374f0, 0x37528,
1625                 0x37530, 0x37548,
1626                 0x37560, 0x37568,
1627                 0x37570, 0x3759c,
1628                 0x375f0, 0x37638,
1629                 0x37640, 0x37640,
1630                 0x37648, 0x37650,
1631                 0x3765c, 0x37664,
1632                 0x37670, 0x376b8,
1633                 0x376c0, 0x376e4,
1634                 0x376f8, 0x37738,
1635                 0x37740, 0x37740,
1636                 0x37748, 0x37750,
1637                 0x3775c, 0x37764,
1638                 0x37770, 0x377b8,
1639                 0x377c0, 0x377e4,
1640                 0x377f8, 0x377fc,
1641                 0x37814, 0x37814,
1642                 0x3782c, 0x3782c,
1643                 0x37880, 0x3788c,
1644                 0x378e8, 0x378ec,
1645                 0x37900, 0x37928,
1646                 0x37930, 0x37948,
1647                 0x37960, 0x37968,
1648                 0x37970, 0x3799c,
1649                 0x379f0, 0x37a38,
1650                 0x37a40, 0x37a40,
1651                 0x37a48, 0x37a50,
1652                 0x37a5c, 0x37a64,
1653                 0x37a70, 0x37ab8,
1654                 0x37ac0, 0x37ae4,
1655                 0x37af8, 0x37b10,
1656                 0x37b28, 0x37b28,
1657                 0x37b3c, 0x37b50,
1658                 0x37bf0, 0x37c10,
1659                 0x37c28, 0x37c28,
1660                 0x37c3c, 0x37c50,
1661                 0x37cf0, 0x37cfc,
1662                 0x38000, 0x38030,
1663                 0x38100, 0x38144,
1664                 0x38190, 0x381a0,
1665                 0x381a8, 0x381b8,
1666                 0x381c4, 0x381c8,
1667                 0x381d0, 0x381d0,
1668                 0x38200, 0x38318,
1669                 0x38400, 0x384b4,
1670                 0x384c0, 0x3852c,
1671                 0x38540, 0x3861c,
1672                 0x38800, 0x38828,
1673                 0x38834, 0x38834,
1674                 0x388c0, 0x38908,
1675                 0x38910, 0x389ac,
1676                 0x38a00, 0x38a14,
1677                 0x38a1c, 0x38a2c,
1678                 0x38a44, 0x38a50,
1679                 0x38a74, 0x38a74,
1680                 0x38a7c, 0x38afc,
1681                 0x38b08, 0x38c24,
1682                 0x38d00, 0x38d00,
1683                 0x38d08, 0x38d14,
1684                 0x38d1c, 0x38d20,
1685                 0x38d3c, 0x38d3c,
1686                 0x38d48, 0x38d50,
1687                 0x39200, 0x3920c,
1688                 0x39220, 0x39220,
1689                 0x39240, 0x39240,
1690                 0x39600, 0x3960c,
1691                 0x39a00, 0x39a1c,
1692                 0x39e00, 0x39e20,
1693                 0x39e38, 0x39e3c,
1694                 0x39e80, 0x39e80,
1695                 0x39e88, 0x39ea8,
1696                 0x39eb0, 0x39eb4,
1697                 0x39ec8, 0x39ed4,
1698                 0x39fb8, 0x3a004,
1699                 0x3a200, 0x3a200,
1700                 0x3a208, 0x3a240,
1701                 0x3a248, 0x3a280,
1702                 0x3a288, 0x3a2c0,
1703                 0x3a2c8, 0x3a2fc,
1704                 0x3a600, 0x3a630,
1705                 0x3aa00, 0x3aabc,
1706                 0x3ab00, 0x3ab10,
1707                 0x3ab20, 0x3ab30,
1708                 0x3ab40, 0x3ab50,
1709                 0x3ab60, 0x3ab70,
1710                 0x3b000, 0x3b028,
1711                 0x3b030, 0x3b048,
1712                 0x3b060, 0x3b068,
1713                 0x3b070, 0x3b09c,
1714                 0x3b0f0, 0x3b128,
1715                 0x3b130, 0x3b148,
1716                 0x3b160, 0x3b168,
1717                 0x3b170, 0x3b19c,
1718                 0x3b1f0, 0x3b238,
1719                 0x3b240, 0x3b240,
1720                 0x3b248, 0x3b250,
1721                 0x3b25c, 0x3b264,
1722                 0x3b270, 0x3b2b8,
1723                 0x3b2c0, 0x3b2e4,
1724                 0x3b2f8, 0x3b338,
1725                 0x3b340, 0x3b340,
1726                 0x3b348, 0x3b350,
1727                 0x3b35c, 0x3b364,
1728                 0x3b370, 0x3b3b8,
1729                 0x3b3c0, 0x3b3e4,
1730                 0x3b3f8, 0x3b428,
1731                 0x3b430, 0x3b448,
1732                 0x3b460, 0x3b468,
1733                 0x3b470, 0x3b49c,
1734                 0x3b4f0, 0x3b528,
1735                 0x3b530, 0x3b548,
1736                 0x3b560, 0x3b568,
1737                 0x3b570, 0x3b59c,
1738                 0x3b5f0, 0x3b638,
1739                 0x3b640, 0x3b640,
1740                 0x3b648, 0x3b650,
1741                 0x3b65c, 0x3b664,
1742                 0x3b670, 0x3b6b8,
1743                 0x3b6c0, 0x3b6e4,
1744                 0x3b6f8, 0x3b738,
1745                 0x3b740, 0x3b740,
1746                 0x3b748, 0x3b750,
1747                 0x3b75c, 0x3b764,
1748                 0x3b770, 0x3b7b8,
1749                 0x3b7c0, 0x3b7e4,
1750                 0x3b7f8, 0x3b7fc,
1751                 0x3b814, 0x3b814,
1752                 0x3b82c, 0x3b82c,
1753                 0x3b880, 0x3b88c,
1754                 0x3b8e8, 0x3b8ec,
1755                 0x3b900, 0x3b928,
1756                 0x3b930, 0x3b948,
1757                 0x3b960, 0x3b968,
1758                 0x3b970, 0x3b99c,
1759                 0x3b9f0, 0x3ba38,
1760                 0x3ba40, 0x3ba40,
1761                 0x3ba48, 0x3ba50,
1762                 0x3ba5c, 0x3ba64,
1763                 0x3ba70, 0x3bab8,
1764                 0x3bac0, 0x3bae4,
1765                 0x3baf8, 0x3bb10,
1766                 0x3bb28, 0x3bb28,
1767                 0x3bb3c, 0x3bb50,
1768                 0x3bbf0, 0x3bc10,
1769                 0x3bc28, 0x3bc28,
1770                 0x3bc3c, 0x3bc50,
1771                 0x3bcf0, 0x3bcfc,
1772                 0x3c000, 0x3c030,
1773                 0x3c100, 0x3c144,
1774                 0x3c190, 0x3c1a0,
1775                 0x3c1a8, 0x3c1b8,
1776                 0x3c1c4, 0x3c1c8,
1777                 0x3c1d0, 0x3c1d0,
1778                 0x3c200, 0x3c318,
1779                 0x3c400, 0x3c4b4,
1780                 0x3c4c0, 0x3c52c,
1781                 0x3c540, 0x3c61c,
1782                 0x3c800, 0x3c828,
1783                 0x3c834, 0x3c834,
1784                 0x3c8c0, 0x3c908,
1785                 0x3c910, 0x3c9ac,
1786                 0x3ca00, 0x3ca14,
1787                 0x3ca1c, 0x3ca2c,
1788                 0x3ca44, 0x3ca50,
1789                 0x3ca74, 0x3ca74,
1790                 0x3ca7c, 0x3cafc,
1791                 0x3cb08, 0x3cc24,
1792                 0x3cd00, 0x3cd00,
1793                 0x3cd08, 0x3cd14,
1794                 0x3cd1c, 0x3cd20,
1795                 0x3cd3c, 0x3cd3c,
1796                 0x3cd48, 0x3cd50,
1797                 0x3d200, 0x3d20c,
1798                 0x3d220, 0x3d220,
1799                 0x3d240, 0x3d240,
1800                 0x3d600, 0x3d60c,
1801                 0x3da00, 0x3da1c,
1802                 0x3de00, 0x3de20,
1803                 0x3de38, 0x3de3c,
1804                 0x3de80, 0x3de80,
1805                 0x3de88, 0x3dea8,
1806                 0x3deb0, 0x3deb4,
1807                 0x3dec8, 0x3ded4,
1808                 0x3dfb8, 0x3e004,
1809                 0x3e200, 0x3e200,
1810                 0x3e208, 0x3e240,
1811                 0x3e248, 0x3e280,
1812                 0x3e288, 0x3e2c0,
1813                 0x3e2c8, 0x3e2fc,
1814                 0x3e600, 0x3e630,
1815                 0x3ea00, 0x3eabc,
1816                 0x3eb00, 0x3eb10,
1817                 0x3eb20, 0x3eb30,
1818                 0x3eb40, 0x3eb50,
1819                 0x3eb60, 0x3eb70,
1820                 0x3f000, 0x3f028,
1821                 0x3f030, 0x3f048,
1822                 0x3f060, 0x3f068,
1823                 0x3f070, 0x3f09c,
1824                 0x3f0f0, 0x3f128,
1825                 0x3f130, 0x3f148,
1826                 0x3f160, 0x3f168,
1827                 0x3f170, 0x3f19c,
1828                 0x3f1f0, 0x3f238,
1829                 0x3f240, 0x3f240,
1830                 0x3f248, 0x3f250,
1831                 0x3f25c, 0x3f264,
1832                 0x3f270, 0x3f2b8,
1833                 0x3f2c0, 0x3f2e4,
1834                 0x3f2f8, 0x3f338,
1835                 0x3f340, 0x3f340,
1836                 0x3f348, 0x3f350,
1837                 0x3f35c, 0x3f364,
1838                 0x3f370, 0x3f3b8,
1839                 0x3f3c0, 0x3f3e4,
1840                 0x3f3f8, 0x3f428,
1841                 0x3f430, 0x3f448,
1842                 0x3f460, 0x3f468,
1843                 0x3f470, 0x3f49c,
1844                 0x3f4f0, 0x3f528,
1845                 0x3f530, 0x3f548,
1846                 0x3f560, 0x3f568,
1847                 0x3f570, 0x3f59c,
1848                 0x3f5f0, 0x3f638,
1849                 0x3f640, 0x3f640,
1850                 0x3f648, 0x3f650,
1851                 0x3f65c, 0x3f664,
1852                 0x3f670, 0x3f6b8,
1853                 0x3f6c0, 0x3f6e4,
1854                 0x3f6f8, 0x3f738,
1855                 0x3f740, 0x3f740,
1856                 0x3f748, 0x3f750,
1857                 0x3f75c, 0x3f764,
1858                 0x3f770, 0x3f7b8,
1859                 0x3f7c0, 0x3f7e4,
1860                 0x3f7f8, 0x3f7fc,
1861                 0x3f814, 0x3f814,
1862                 0x3f82c, 0x3f82c,
1863                 0x3f880, 0x3f88c,
1864                 0x3f8e8, 0x3f8ec,
1865                 0x3f900, 0x3f928,
1866                 0x3f930, 0x3f948,
1867                 0x3f960, 0x3f968,
1868                 0x3f970, 0x3f99c,
1869                 0x3f9f0, 0x3fa38,
1870                 0x3fa40, 0x3fa40,
1871                 0x3fa48, 0x3fa50,
1872                 0x3fa5c, 0x3fa64,
1873                 0x3fa70, 0x3fab8,
1874                 0x3fac0, 0x3fae4,
1875                 0x3faf8, 0x3fb10,
1876                 0x3fb28, 0x3fb28,
1877                 0x3fb3c, 0x3fb50,
1878                 0x3fbf0, 0x3fc10,
1879                 0x3fc28, 0x3fc28,
1880                 0x3fc3c, 0x3fc50,
1881                 0x3fcf0, 0x3fcfc,
1882                 0x40000, 0x4000c,
1883                 0x40040, 0x40050,
1884                 0x40060, 0x40068,
1885                 0x4007c, 0x4008c,
1886                 0x40094, 0x400b0,
1887                 0x400c0, 0x40144,
1888                 0x40180, 0x4018c,
1889                 0x40200, 0x40254,
1890                 0x40260, 0x40264,
1891                 0x40270, 0x40288,
1892                 0x40290, 0x40298,
1893                 0x402ac, 0x402c8,
1894                 0x402d0, 0x402e0,
1895                 0x402f0, 0x402f0,
1896                 0x40300, 0x4033c,
1897                 0x403f8, 0x403fc,
1898                 0x41304, 0x413c4,
1899                 0x41400, 0x4140c,
1900                 0x41414, 0x4141c,
1901                 0x41480, 0x414d0,
1902                 0x44000, 0x44054,
1903                 0x4405c, 0x44078,
1904                 0x440c0, 0x44174,
1905                 0x44180, 0x441ac,
1906                 0x441b4, 0x441b8,
1907                 0x441c0, 0x44254,
1908                 0x4425c, 0x44278,
1909                 0x442c0, 0x44374,
1910                 0x44380, 0x443ac,
1911                 0x443b4, 0x443b8,
1912                 0x443c0, 0x44454,
1913                 0x4445c, 0x44478,
1914                 0x444c0, 0x44574,
1915                 0x44580, 0x445ac,
1916                 0x445b4, 0x445b8,
1917                 0x445c0, 0x44654,
1918                 0x4465c, 0x44678,
1919                 0x446c0, 0x44774,
1920                 0x44780, 0x447ac,
1921                 0x447b4, 0x447b8,
1922                 0x447c0, 0x44854,
1923                 0x4485c, 0x44878,
1924                 0x448c0, 0x44974,
1925                 0x44980, 0x449ac,
1926                 0x449b4, 0x449b8,
1927                 0x449c0, 0x449fc,
1928                 0x45000, 0x45004,
1929                 0x45010, 0x45030,
1930                 0x45040, 0x45060,
1931                 0x45068, 0x45068,
1932                 0x45080, 0x45084,
1933                 0x450a0, 0x450b0,
1934                 0x45200, 0x45204,
1935                 0x45210, 0x45230,
1936                 0x45240, 0x45260,
1937                 0x45268, 0x45268,
1938                 0x45280, 0x45284,
1939                 0x452a0, 0x452b0,
1940                 0x460c0, 0x460e4,
1941                 0x47000, 0x4703c,
1942                 0x47044, 0x4708c,
1943                 0x47200, 0x47250,
1944                 0x47400, 0x47408,
1945                 0x47414, 0x47420,
1946                 0x47600, 0x47618,
1947                 0x47800, 0x47814,
1948                 0x48000, 0x4800c,
1949                 0x48040, 0x48050,
1950                 0x48060, 0x48068,
1951                 0x4807c, 0x4808c,
1952                 0x48094, 0x480b0,
1953                 0x480c0, 0x48144,
1954                 0x48180, 0x4818c,
1955                 0x48200, 0x48254,
1956                 0x48260, 0x48264,
1957                 0x48270, 0x48288,
1958                 0x48290, 0x48298,
1959                 0x482ac, 0x482c8,
1960                 0x482d0, 0x482e0,
1961                 0x482f0, 0x482f0,
1962                 0x48300, 0x4833c,
1963                 0x483f8, 0x483fc,
1964                 0x49304, 0x493c4,
1965                 0x49400, 0x4940c,
1966                 0x49414, 0x4941c,
1967                 0x49480, 0x494d0,
1968                 0x4c000, 0x4c054,
1969                 0x4c05c, 0x4c078,
1970                 0x4c0c0, 0x4c174,
1971                 0x4c180, 0x4c1ac,
1972                 0x4c1b4, 0x4c1b8,
1973                 0x4c1c0, 0x4c254,
1974                 0x4c25c, 0x4c278,
1975                 0x4c2c0, 0x4c374,
1976                 0x4c380, 0x4c3ac,
1977                 0x4c3b4, 0x4c3b8,
1978                 0x4c3c0, 0x4c454,
1979                 0x4c45c, 0x4c478,
1980                 0x4c4c0, 0x4c574,
1981                 0x4c580, 0x4c5ac,
1982                 0x4c5b4, 0x4c5b8,
1983                 0x4c5c0, 0x4c654,
1984                 0x4c65c, 0x4c678,
1985                 0x4c6c0, 0x4c774,
1986                 0x4c780, 0x4c7ac,
1987                 0x4c7b4, 0x4c7b8,
1988                 0x4c7c0, 0x4c854,
1989                 0x4c85c, 0x4c878,
1990                 0x4c8c0, 0x4c974,
1991                 0x4c980, 0x4c9ac,
1992                 0x4c9b4, 0x4c9b8,
1993                 0x4c9c0, 0x4c9fc,
1994                 0x4d000, 0x4d004,
1995                 0x4d010, 0x4d030,
1996                 0x4d040, 0x4d060,
1997                 0x4d068, 0x4d068,
1998                 0x4d080, 0x4d084,
1999                 0x4d0a0, 0x4d0b0,
2000                 0x4d200, 0x4d204,
2001                 0x4d210, 0x4d230,
2002                 0x4d240, 0x4d260,
2003                 0x4d268, 0x4d268,
2004                 0x4d280, 0x4d284,
2005                 0x4d2a0, 0x4d2b0,
2006                 0x4e0c0, 0x4e0e4,
2007                 0x4f000, 0x4f03c,
2008                 0x4f044, 0x4f08c,
2009                 0x4f200, 0x4f250,
2010                 0x4f400, 0x4f408,
2011                 0x4f414, 0x4f420,
2012                 0x4f600, 0x4f618,
2013                 0x4f800, 0x4f814,
2014                 0x50000, 0x50084,
2015                 0x50090, 0x500cc,
2016                 0x50400, 0x50400,
2017                 0x50800, 0x50884,
2018                 0x50890, 0x508cc,
2019                 0x50c00, 0x50c00,
2020                 0x51000, 0x5101c,
2021                 0x51300, 0x51308,
2022         };
2023
2024         static const unsigned int t6_reg_ranges[] = {
2025                 0x1008, 0x101c,
2026                 0x1024, 0x10a8,
2027                 0x10b4, 0x10f8,
2028                 0x1100, 0x1114,
2029                 0x111c, 0x112c,
2030                 0x1138, 0x113c,
2031                 0x1144, 0x114c,
2032                 0x1180, 0x1184,
2033                 0x1190, 0x1194,
2034                 0x11a0, 0x11a4,
2035                 0x11b0, 0x11b4,
2036                 0x11fc, 0x1274,
2037                 0x1280, 0x133c,
2038                 0x1800, 0x18fc,
2039                 0x3000, 0x302c,
2040                 0x3060, 0x30b0,
2041                 0x30b8, 0x30d8,
2042                 0x30e0, 0x30fc,
2043                 0x3140, 0x357c,
2044                 0x35a8, 0x35cc,
2045                 0x35ec, 0x35ec,
2046                 0x3600, 0x5624,
2047                 0x56cc, 0x56ec,
2048                 0x56f4, 0x5720,
2049                 0x5728, 0x575c,
2050                 0x580c, 0x5814,
2051                 0x5890, 0x589c,
2052                 0x58a4, 0x58ac,
2053                 0x58b8, 0x58bc,
2054                 0x5940, 0x595c,
2055                 0x5980, 0x598c,
2056                 0x59b0, 0x59c8,
2057                 0x59d0, 0x59dc,
2058                 0x59fc, 0x5a18,
2059                 0x5a60, 0x5a6c,
2060                 0x5a80, 0x5a8c,
2061                 0x5a94, 0x5a9c,
2062                 0x5b94, 0x5bfc,
2063                 0x5c10, 0x5e48,
2064                 0x5e50, 0x5e94,
2065                 0x5ea0, 0x5eb0,
2066                 0x5ec0, 0x5ec0,
2067                 0x5ec8, 0x5ed0,
2068                 0x5ee0, 0x5ee0,
2069                 0x5ef0, 0x5ef0,
2070                 0x5f00, 0x5f00,
2071                 0x6000, 0x6020,
2072                 0x6028, 0x6040,
2073                 0x6058, 0x609c,
2074                 0x60a8, 0x619c,
2075                 0x7700, 0x7798,
2076                 0x77c0, 0x7880,
2077                 0x78cc, 0x78fc,
2078                 0x7b00, 0x7b58,
2079                 0x7b60, 0x7b84,
2080                 0x7b8c, 0x7c54,
2081                 0x7d00, 0x7d38,
2082                 0x7d40, 0x7d84,
2083                 0x7d8c, 0x7ddc,
2084                 0x7de4, 0x7e04,
2085                 0x7e10, 0x7e1c,
2086                 0x7e24, 0x7e38,
2087                 0x7e40, 0x7e44,
2088                 0x7e4c, 0x7e78,
2089                 0x7e80, 0x7edc,
2090                 0x7ee8, 0x7efc,
2091                 0x8dc0, 0x8de4,
2092                 0x8df8, 0x8e04,
2093                 0x8e10, 0x8e84,
2094                 0x8ea0, 0x8f88,
2095                 0x8fb8, 0x9058,
2096                 0x9060, 0x9060,
2097                 0x9068, 0x90f8,
2098                 0x9100, 0x9124,
2099                 0x9400, 0x9470,
2100                 0x9600, 0x9600,
2101                 0x9608, 0x9638,
2102                 0x9640, 0x9704,
2103                 0x9710, 0x971c,
2104                 0x9800, 0x9808,
2105                 0x9820, 0x983c,
2106                 0x9850, 0x9864,
2107                 0x9c00, 0x9c6c,
2108                 0x9c80, 0x9cec,
2109                 0x9d00, 0x9d6c,
2110                 0x9d80, 0x9dec,
2111                 0x9e00, 0x9e6c,
2112                 0x9e80, 0x9eec,
2113                 0x9f00, 0x9f6c,
2114                 0x9f80, 0xa020,
2115                 0xd004, 0xd03c,
2116                 0xd100, 0xd118,
2117                 0xd200, 0xd214,
2118                 0xd220, 0xd234,
2119                 0xd240, 0xd254,
2120                 0xd260, 0xd274,
2121                 0xd280, 0xd294,
2122                 0xd2a0, 0xd2b4,
2123                 0xd2c0, 0xd2d4,
2124                 0xd2e0, 0xd2f4,
2125                 0xd300, 0xd31c,
2126                 0xdfc0, 0xdfe0,
2127                 0xe000, 0xf008,
2128                 0xf010, 0xf018,
2129                 0xf020, 0xf028,
2130                 0x11000, 0x11014,
2131                 0x11048, 0x1106c,
2132                 0x11074, 0x11088,
2133                 0x11098, 0x11120,
2134                 0x1112c, 0x1117c,
2135                 0x11190, 0x112e0,
2136                 0x11300, 0x1130c,
2137                 0x12000, 0x1206c,
2138                 0x19040, 0x1906c,
2139                 0x19078, 0x19080,
2140                 0x1908c, 0x190e8,
2141                 0x190f0, 0x190f8,
2142                 0x19100, 0x19110,
2143                 0x19120, 0x19124,
2144                 0x19150, 0x19194,
2145                 0x1919c, 0x191b0,
2146                 0x191d0, 0x191e8,
2147                 0x19238, 0x19290,
2148                 0x192a4, 0x192b0,
2149                 0x192bc, 0x192bc,
2150                 0x19348, 0x1934c,
2151                 0x193f8, 0x19418,
2152                 0x19420, 0x19428,
2153                 0x19430, 0x19444,
2154                 0x1944c, 0x1946c,
2155                 0x19474, 0x19474,
2156                 0x19490, 0x194cc,
2157                 0x194f0, 0x194f8,
2158                 0x19c00, 0x19c48,
2159                 0x19c50, 0x19c80,
2160                 0x19c94, 0x19c98,
2161                 0x19ca0, 0x19cbc,
2162                 0x19ce4, 0x19ce4,
2163                 0x19cf0, 0x19cf8,
2164                 0x19d00, 0x19d28,
2165                 0x19d50, 0x19d78,
2166                 0x19d94, 0x19d98,
2167                 0x19da0, 0x19dc8,
2168                 0x19df0, 0x19e10,
2169                 0x19e50, 0x19e6c,
2170                 0x19ea0, 0x19ebc,
2171                 0x19ec4, 0x19ef4,
2172                 0x19f04, 0x19f2c,
2173                 0x19f34, 0x19f34,
2174                 0x19f40, 0x19f50,
2175                 0x19f90, 0x19fac,
2176                 0x19fc4, 0x19fc8,
2177                 0x19fd0, 0x19fe4,
2178                 0x1a000, 0x1a004,
2179                 0x1a010, 0x1a06c,
2180                 0x1a0b0, 0x1a0e4,
2181                 0x1a0ec, 0x1a0f8,
2182                 0x1a100, 0x1a108,
2183                 0x1a114, 0x1a120,
2184                 0x1a128, 0x1a130,
2185                 0x1a138, 0x1a138,
2186                 0x1a190, 0x1a1c4,
2187                 0x1a1fc, 0x1a1fc,
2188                 0x1e008, 0x1e00c,
2189                 0x1e040, 0x1e044,
2190                 0x1e04c, 0x1e04c,
2191                 0x1e284, 0x1e290,
2192                 0x1e2c0, 0x1e2c0,
2193                 0x1e2e0, 0x1e2e0,
2194                 0x1e300, 0x1e384,
2195                 0x1e3c0, 0x1e3c8,
2196                 0x1e408, 0x1e40c,
2197                 0x1e440, 0x1e444,
2198                 0x1e44c, 0x1e44c,
2199                 0x1e684, 0x1e690,
2200                 0x1e6c0, 0x1e6c0,
2201                 0x1e6e0, 0x1e6e0,
2202                 0x1e700, 0x1e784,
2203                 0x1e7c0, 0x1e7c8,
2204                 0x1e808, 0x1e80c,
2205                 0x1e840, 0x1e844,
2206                 0x1e84c, 0x1e84c,
2207                 0x1ea84, 0x1ea90,
2208                 0x1eac0, 0x1eac0,
2209                 0x1eae0, 0x1eae0,
2210                 0x1eb00, 0x1eb84,
2211                 0x1ebc0, 0x1ebc8,
2212                 0x1ec08, 0x1ec0c,
2213                 0x1ec40, 0x1ec44,
2214                 0x1ec4c, 0x1ec4c,
2215                 0x1ee84, 0x1ee90,
2216                 0x1eec0, 0x1eec0,
2217                 0x1eee0, 0x1eee0,
2218                 0x1ef00, 0x1ef84,
2219                 0x1efc0, 0x1efc8,
2220                 0x1f008, 0x1f00c,
2221                 0x1f040, 0x1f044,
2222                 0x1f04c, 0x1f04c,
2223                 0x1f284, 0x1f290,
2224                 0x1f2c0, 0x1f2c0,
2225                 0x1f2e0, 0x1f2e0,
2226                 0x1f300, 0x1f384,
2227                 0x1f3c0, 0x1f3c8,
2228                 0x1f408, 0x1f40c,
2229                 0x1f440, 0x1f444,
2230                 0x1f44c, 0x1f44c,
2231                 0x1f684, 0x1f690,
2232                 0x1f6c0, 0x1f6c0,
2233                 0x1f6e0, 0x1f6e0,
2234                 0x1f700, 0x1f784,
2235                 0x1f7c0, 0x1f7c8,
2236                 0x1f808, 0x1f80c,
2237                 0x1f840, 0x1f844,
2238                 0x1f84c, 0x1f84c,
2239                 0x1fa84, 0x1fa90,
2240                 0x1fac0, 0x1fac0,
2241                 0x1fae0, 0x1fae0,
2242                 0x1fb00, 0x1fb84,
2243                 0x1fbc0, 0x1fbc8,
2244                 0x1fc08, 0x1fc0c,
2245                 0x1fc40, 0x1fc44,
2246                 0x1fc4c, 0x1fc4c,
2247                 0x1fe84, 0x1fe90,
2248                 0x1fec0, 0x1fec0,
2249                 0x1fee0, 0x1fee0,
2250                 0x1ff00, 0x1ff84,
2251                 0x1ffc0, 0x1ffc8,
2252                 0x30000, 0x30030,
2253                 0x30100, 0x30168,
2254                 0x30190, 0x301a0,
2255                 0x301a8, 0x301b8,
2256                 0x301c4, 0x301c8,
2257                 0x301d0, 0x301d0,
2258                 0x30200, 0x30320,
2259                 0x30400, 0x304b4,
2260                 0x304c0, 0x3052c,
2261                 0x30540, 0x3061c,
2262                 0x30800, 0x308a0,
2263                 0x308c0, 0x30908,
2264                 0x30910, 0x309b8,
2265                 0x30a00, 0x30a04,
2266                 0x30a0c, 0x30a14,
2267                 0x30a1c, 0x30a2c,
2268                 0x30a44, 0x30a50,
2269                 0x30a74, 0x30a74,
2270                 0x30a7c, 0x30afc,
2271                 0x30b08, 0x30c24,
2272                 0x30d00, 0x30d14,
2273                 0x30d1c, 0x30d3c,
2274                 0x30d44, 0x30d4c,
2275                 0x30d54, 0x30d74,
2276                 0x30d7c, 0x30d7c,
2277                 0x30de0, 0x30de0,
2278                 0x30e00, 0x30ed4,
2279                 0x30f00, 0x30fa4,
2280                 0x30fc0, 0x30fc4,
2281                 0x31000, 0x31004,
2282                 0x31080, 0x310fc,
2283                 0x31208, 0x31220,
2284                 0x3123c, 0x31254,
2285                 0x31300, 0x31300,
2286                 0x31308, 0x3131c,
2287                 0x31338, 0x3133c,
2288                 0x31380, 0x31380,
2289                 0x31388, 0x313a8,
2290                 0x313b4, 0x313b4,
2291                 0x31400, 0x31420,
2292                 0x31438, 0x3143c,
2293                 0x31480, 0x31480,
2294                 0x314a8, 0x314a8,
2295                 0x314b0, 0x314b4,
2296                 0x314c8, 0x314d4,
2297                 0x31a40, 0x31a4c,
2298                 0x31af0, 0x31b20,
2299                 0x31b38, 0x31b3c,
2300                 0x31b80, 0x31b80,
2301                 0x31ba8, 0x31ba8,
2302                 0x31bb0, 0x31bb4,
2303                 0x31bc8, 0x31bd4,
2304                 0x32140, 0x3218c,
2305                 0x321f0, 0x321f4,
2306                 0x32200, 0x32200,
2307                 0x32218, 0x32218,
2308                 0x32400, 0x32400,
2309                 0x32408, 0x3241c,
2310                 0x32618, 0x32620,
2311                 0x32664, 0x32664,
2312                 0x326a8, 0x326a8,
2313                 0x326ec, 0x326ec,
2314                 0x32a00, 0x32abc,
2315                 0x32b00, 0x32b18,
2316                 0x32b20, 0x32b38,
2317                 0x32b40, 0x32b58,
2318                 0x32b60, 0x32b78,
2319                 0x32c00, 0x32c00,
2320                 0x32c08, 0x32c3c,
2321                 0x33000, 0x3302c,
2322                 0x33034, 0x33050,
2323                 0x33058, 0x33058,
2324                 0x33060, 0x3308c,
2325                 0x3309c, 0x330ac,
2326                 0x330c0, 0x330c0,
2327                 0x330c8, 0x330d0,
2328                 0x330d8, 0x330e0,
2329                 0x330ec, 0x3312c,
2330                 0x33134, 0x33150,
2331                 0x33158, 0x33158,
2332                 0x33160, 0x3318c,
2333                 0x3319c, 0x331ac,
2334                 0x331c0, 0x331c0,
2335                 0x331c8, 0x331d0,
2336                 0x331d8, 0x331e0,
2337                 0x331ec, 0x33290,
2338                 0x33298, 0x332c4,
2339                 0x332e4, 0x33390,
2340                 0x33398, 0x333c4,
2341                 0x333e4, 0x3342c,
2342                 0x33434, 0x33450,
2343                 0x33458, 0x33458,
2344                 0x33460, 0x3348c,
2345                 0x3349c, 0x334ac,
2346                 0x334c0, 0x334c0,
2347                 0x334c8, 0x334d0,
2348                 0x334d8, 0x334e0,
2349                 0x334ec, 0x3352c,
2350                 0x33534, 0x33550,
2351                 0x33558, 0x33558,
2352                 0x33560, 0x3358c,
2353                 0x3359c, 0x335ac,
2354                 0x335c0, 0x335c0,
2355                 0x335c8, 0x335d0,
2356                 0x335d8, 0x335e0,
2357                 0x335ec, 0x33690,
2358                 0x33698, 0x336c4,
2359                 0x336e4, 0x33790,
2360                 0x33798, 0x337c4,
2361                 0x337e4, 0x337fc,
2362                 0x33814, 0x33814,
2363                 0x33854, 0x33868,
2364                 0x33880, 0x3388c,
2365                 0x338c0, 0x338d0,
2366                 0x338e8, 0x338ec,
2367                 0x33900, 0x3392c,
2368                 0x33934, 0x33950,
2369                 0x33958, 0x33958,
2370                 0x33960, 0x3398c,
2371                 0x3399c, 0x339ac,
2372                 0x339c0, 0x339c0,
2373                 0x339c8, 0x339d0,
2374                 0x339d8, 0x339e0,
2375                 0x339ec, 0x33a90,
2376                 0x33a98, 0x33ac4,
2377                 0x33ae4, 0x33b10,
2378                 0x33b24, 0x33b28,
2379                 0x33b38, 0x33b50,
2380                 0x33bf0, 0x33c10,
2381                 0x33c24, 0x33c28,
2382                 0x33c38, 0x33c50,
2383                 0x33cf0, 0x33cfc,
2384                 0x34000, 0x34030,
2385                 0x34100, 0x34168,
2386                 0x34190, 0x341a0,
2387                 0x341a8, 0x341b8,
2388                 0x341c4, 0x341c8,
2389                 0x341d0, 0x341d0,
2390                 0x34200, 0x34320,
2391                 0x34400, 0x344b4,
2392                 0x344c0, 0x3452c,
2393                 0x34540, 0x3461c,
2394                 0x34800, 0x348a0,
2395                 0x348c0, 0x34908,
2396                 0x34910, 0x349b8,
2397                 0x34a00, 0x34a04,
2398                 0x34a0c, 0x34a14,
2399                 0x34a1c, 0x34a2c,
2400                 0x34a44, 0x34a50,
2401                 0x34a74, 0x34a74,
2402                 0x34a7c, 0x34afc,
2403                 0x34b08, 0x34c24,
2404                 0x34d00, 0x34d14,
2405                 0x34d1c, 0x34d3c,
2406                 0x34d44, 0x34d4c,
2407                 0x34d54, 0x34d74,
2408                 0x34d7c, 0x34d7c,
2409                 0x34de0, 0x34de0,
2410                 0x34e00, 0x34ed4,
2411                 0x34f00, 0x34fa4,
2412                 0x34fc0, 0x34fc4,
2413                 0x35000, 0x35004,
2414                 0x35080, 0x350fc,
2415                 0x35208, 0x35220,
2416                 0x3523c, 0x35254,
2417                 0x35300, 0x35300,
2418                 0x35308, 0x3531c,
2419                 0x35338, 0x3533c,
2420                 0x35380, 0x35380,
2421                 0x35388, 0x353a8,
2422                 0x353b4, 0x353b4,
2423                 0x35400, 0x35420,
2424                 0x35438, 0x3543c,
2425                 0x35480, 0x35480,
2426                 0x354a8, 0x354a8,
2427                 0x354b0, 0x354b4,
2428                 0x354c8, 0x354d4,
2429                 0x35a40, 0x35a4c,
2430                 0x35af0, 0x35b20,
2431                 0x35b38, 0x35b3c,
2432                 0x35b80, 0x35b80,
2433                 0x35ba8, 0x35ba8,
2434                 0x35bb0, 0x35bb4,
2435                 0x35bc8, 0x35bd4,
2436                 0x36140, 0x3618c,
2437                 0x361f0, 0x361f4,
2438                 0x36200, 0x36200,
2439                 0x36218, 0x36218,
2440                 0x36400, 0x36400,
2441                 0x36408, 0x3641c,
2442                 0x36618, 0x36620,
2443                 0x36664, 0x36664,
2444                 0x366a8, 0x366a8,
2445                 0x366ec, 0x366ec,
2446                 0x36a00, 0x36abc,
2447                 0x36b00, 0x36b18,
2448                 0x36b20, 0x36b38,
2449                 0x36b40, 0x36b58,
2450                 0x36b60, 0x36b78,
2451                 0x36c00, 0x36c00,
2452                 0x36c08, 0x36c3c,
2453                 0x37000, 0x3702c,
2454                 0x37034, 0x37050,
2455                 0x37058, 0x37058,
2456                 0x37060, 0x3708c,
2457                 0x3709c, 0x370ac,
2458                 0x370c0, 0x370c0,
2459                 0x370c8, 0x370d0,
2460                 0x370d8, 0x370e0,
2461                 0x370ec, 0x3712c,
2462                 0x37134, 0x37150,
2463                 0x37158, 0x37158,
2464                 0x37160, 0x3718c,
2465                 0x3719c, 0x371ac,
2466                 0x371c0, 0x371c0,
2467                 0x371c8, 0x371d0,
2468                 0x371d8, 0x371e0,
2469                 0x371ec, 0x37290,
2470                 0x37298, 0x372c4,
2471                 0x372e4, 0x37390,
2472                 0x37398, 0x373c4,
2473                 0x373e4, 0x3742c,
2474                 0x37434, 0x37450,
2475                 0x37458, 0x37458,
2476                 0x37460, 0x3748c,
2477                 0x3749c, 0x374ac,
2478                 0x374c0, 0x374c0,
2479                 0x374c8, 0x374d0,
2480                 0x374d8, 0x374e0,
2481                 0x374ec, 0x3752c,
2482                 0x37534, 0x37550,
2483                 0x37558, 0x37558,
2484                 0x37560, 0x3758c,
2485                 0x3759c, 0x375ac,
2486                 0x375c0, 0x375c0,
2487                 0x375c8, 0x375d0,
2488                 0x375d8, 0x375e0,
2489                 0x375ec, 0x37690,
2490                 0x37698, 0x376c4,
2491                 0x376e4, 0x37790,
2492                 0x37798, 0x377c4,
2493                 0x377e4, 0x377fc,
2494                 0x37814, 0x37814,
2495                 0x37854, 0x37868,
2496                 0x37880, 0x3788c,
2497                 0x378c0, 0x378d0,
2498                 0x378e8, 0x378ec,
2499                 0x37900, 0x3792c,
2500                 0x37934, 0x37950,
2501                 0x37958, 0x37958,
2502                 0x37960, 0x3798c,
2503                 0x3799c, 0x379ac,
2504                 0x379c0, 0x379c0,
2505                 0x379c8, 0x379d0,
2506                 0x379d8, 0x379e0,
2507                 0x379ec, 0x37a90,
2508                 0x37a98, 0x37ac4,
2509                 0x37ae4, 0x37b10,
2510                 0x37b24, 0x37b28,
2511                 0x37b38, 0x37b50,
2512                 0x37bf0, 0x37c10,
2513                 0x37c24, 0x37c28,
2514                 0x37c38, 0x37c50,
2515                 0x37cf0, 0x37cfc,
2516                 0x40040, 0x40040,
2517                 0x40080, 0x40084,
2518                 0x40100, 0x40100,
2519                 0x40140, 0x401bc,
2520                 0x40200, 0x40214,
2521                 0x40228, 0x40228,
2522                 0x40240, 0x40258,
2523                 0x40280, 0x40280,
2524                 0x40304, 0x40304,
2525                 0x40330, 0x4033c,
2526                 0x41304, 0x413c8,
2527                 0x413d0, 0x413dc,
2528                 0x413f0, 0x413f0,
2529                 0x41400, 0x4140c,
2530                 0x41414, 0x4141c,
2531                 0x41480, 0x414d0,
2532                 0x44000, 0x4407c,
2533                 0x440c0, 0x441ac,
2534                 0x441b4, 0x4427c,
2535                 0x442c0, 0x443ac,
2536                 0x443b4, 0x4447c,
2537                 0x444c0, 0x445ac,
2538                 0x445b4, 0x4467c,
2539                 0x446c0, 0x447ac,
2540                 0x447b4, 0x4487c,
2541                 0x448c0, 0x449ac,
2542                 0x449b4, 0x44a7c,
2543                 0x44ac0, 0x44bac,
2544                 0x44bb4, 0x44c7c,
2545                 0x44cc0, 0x44dac,
2546                 0x44db4, 0x44e7c,
2547                 0x44ec0, 0x44fac,
2548                 0x44fb4, 0x4507c,
2549                 0x450c0, 0x451ac,
2550                 0x451b4, 0x451fc,
2551                 0x45800, 0x45804,
2552                 0x45810, 0x45830,
2553                 0x45840, 0x45860,
2554                 0x45868, 0x45868,
2555                 0x45880, 0x45884,
2556                 0x458a0, 0x458b0,
2557                 0x45a00, 0x45a04,
2558                 0x45a10, 0x45a30,
2559                 0x45a40, 0x45a60,
2560                 0x45a68, 0x45a68,
2561                 0x45a80, 0x45a84,
2562                 0x45aa0, 0x45ab0,
2563                 0x460c0, 0x460e4,
2564                 0x47000, 0x4703c,
2565                 0x47044, 0x4708c,
2566                 0x47200, 0x47250,
2567                 0x47400, 0x47408,
2568                 0x47414, 0x47420,
2569                 0x47600, 0x47618,
2570                 0x47800, 0x47814,
2571                 0x47820, 0x4782c,
2572                 0x50000, 0x50084,
2573                 0x50090, 0x500cc,
2574                 0x50300, 0x50384,
2575                 0x50400, 0x50400,
2576                 0x50800, 0x50884,
2577                 0x50890, 0x508cc,
2578                 0x50b00, 0x50b84,
2579                 0x50c00, 0x50c00,
2580                 0x51000, 0x51020,
2581                 0x51028, 0x510b0,
2582                 0x51300, 0x51324,
2583         };
2584
2585         u32 *buf_end = (u32 *)((char *)buf + buf_size);
2586         const unsigned int *reg_ranges;
2587         int reg_ranges_size, range;
2588         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2589
2590         /* Select the right set of register ranges to dump depending on the
2591          * adapter chip type.
2592          */
2593         switch (chip_version) {
2594         case CHELSIO_T4:
2595                 reg_ranges = t4_reg_ranges;
2596                 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2597                 break;
2598
2599         case CHELSIO_T5:
2600                 reg_ranges = t5_reg_ranges;
2601                 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2602                 break;
2603
2604         case CHELSIO_T6:
2605                 reg_ranges = t6_reg_ranges;
2606                 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2607                 break;
2608
2609         default:
2610                 dev_err(adap->pdev_dev,
2611                         "Unsupported chip version %d\n", chip_version);
2612                 return;
2613         }
2614
2615         /* Clear the register buffer and insert the appropriate register
2616          * values selected by the above register ranges.
2617          */
2618         memset(buf, 0, buf_size);
2619         for (range = 0; range < reg_ranges_size; range += 2) {
2620                 unsigned int reg = reg_ranges[range];
2621                 unsigned int last_reg = reg_ranges[range + 1];
2622                 u32 *bufp = (u32 *)((char *)buf + reg);
2623
2624                 /* Iterate across the register range filling in the register
2625                  * buffer but don't write past the end of the register buffer.
2626                  */
2627                 while (reg <= last_reg && bufp < buf_end) {
2628                         *bufp++ = t4_read_reg(adap, reg);
2629                         reg += sizeof(u32);
2630                 }
2631         }
2632 }
2633
2634 #define EEPROM_STAT_ADDR   0x7bfc
2635 #define VPD_BASE           0x400
2636 #define VPD_BASE_OLD       0
2637 #define VPD_LEN            1024
2638 #define CHELSIO_VPD_UNIQUE_ID 0x82
2639
2640 /**
2641  *      t4_seeprom_wp - enable/disable EEPROM write protection
2642  *      @adapter: the adapter
2643  *      @enable: whether to enable or disable write protection
2644  *
2645  *      Enables or disables write protection on the serial EEPROM.
2646  */
2647 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2648 {
2649         unsigned int v = enable ? 0xc : 0;
2650         int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2651         return ret < 0 ? ret : 0;
2652 }
2653
2654 /**
2655  *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2656  *      @adapter: adapter to read
2657  *      @p: where to store the parameters
2658  *
2659  *      Reads card parameters stored in VPD EEPROM.
2660  */
2661 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2662 {
2663         int i, ret = 0, addr;
2664         int ec, sn, pn, na;
2665         u8 *vpd, csum;
2666         unsigned int vpdr_len, kw_offset, id_len;
2667
2668         vpd = vmalloc(VPD_LEN);
2669         if (!vpd)
2670                 return -ENOMEM;
2671
2672         /* Card information normally starts at VPD_BASE but early cards had
2673          * it at 0.
2674          */
2675         ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2676         if (ret < 0)
2677                 goto out;
2678
2679         /* The VPD shall have a unique identifier specified by the PCI SIG.
2680          * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2681          * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2682          * is expected to automatically put this entry at the
2683          * beginning of the VPD.
2684          */
2685         addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2686
2687         ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2688         if (ret < 0)
2689                 goto out;
2690
2691         if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2692                 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2693                 ret = -EINVAL;
2694                 goto out;
2695         }
2696
2697         id_len = pci_vpd_lrdt_size(vpd);
2698         if (id_len > ID_LEN)
2699                 id_len = ID_LEN;
2700
2701         i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2702         if (i < 0) {
2703                 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2704                 ret = -EINVAL;
2705                 goto out;
2706         }
2707
2708         vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2709         kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2710         if (vpdr_len + kw_offset > VPD_LEN) {
2711                 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2712                 ret = -EINVAL;
2713                 goto out;
2714         }
2715
2716 #define FIND_VPD_KW(var, name) do { \
2717         var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2718         if (var < 0) { \
2719                 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2720                 ret = -EINVAL; \
2721                 goto out; \
2722         } \
2723         var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2724 } while (0)
2725
2726         FIND_VPD_KW(i, "RV");
2727         for (csum = 0; i >= 0; i--)
2728                 csum += vpd[i];
2729
2730         if (csum) {
2731                 dev_err(adapter->pdev_dev,
2732                         "corrupted VPD EEPROM, actual csum %u\n", csum);
2733                 ret = -EINVAL;
2734                 goto out;
2735         }
2736
2737         FIND_VPD_KW(ec, "EC");
2738         FIND_VPD_KW(sn, "SN");
2739         FIND_VPD_KW(pn, "PN");
2740         FIND_VPD_KW(na, "NA");
2741 #undef FIND_VPD_KW
2742
2743         memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2744         strim(p->id);
2745         memcpy(p->ec, vpd + ec, EC_LEN);
2746         strim(p->ec);
2747         i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2748         memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2749         strim(p->sn);
2750         i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2751         memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2752         strim(p->pn);
2753         memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2754         strim((char *)p->na);
2755
2756 out:
2757         vfree(vpd);
2758         return ret < 0 ? ret : 0;
2759 }
2760
2761 /**
2762  *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2763  *      @adapter: adapter to read
2764  *      @p: where to store the parameters
2765  *
2766  *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2767  *      Clock.  This can only be called after a connection to the firmware
2768  *      is established.
2769  */
2770 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2771 {
2772         u32 cclk_param, cclk_val;
2773         int ret;
2774
2775         /* Grab the raw VPD parameters.
2776          */
2777         ret = t4_get_raw_vpd_params(adapter, p);
2778         if (ret)
2779                 return ret;
2780
2781         /* Ask firmware for the Core Clock since it knows how to translate the
2782          * Reference Clock ('V2') VPD field into a Core Clock value ...
2783          */
2784         cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2785                       FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2786         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2787                               1, &cclk_param, &cclk_val);
2788
2789         if (ret)
2790                 return ret;
2791         p->cclk = cclk_val;
2792
2793         return 0;
2794 }
2795
2796 /* serial flash and firmware constants */
2797 enum {
2798         SF_ATTEMPTS = 10,             /* max retries for SF operations */
2799
2800         /* flash command opcodes */
2801         SF_PROG_PAGE    = 2,          /* program page */
2802         SF_WR_DISABLE   = 4,          /* disable writes */
2803         SF_RD_STATUS    = 5,          /* read status register */
2804         SF_WR_ENABLE    = 6,          /* enable writes */
2805         SF_RD_DATA_FAST = 0xb,        /* read flash */
2806         SF_RD_ID        = 0x9f,       /* read ID */
2807         SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2808
2809         FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2810 };
2811
2812 /**
2813  *      sf1_read - read data from the serial flash
2814  *      @adapter: the adapter
2815  *      @byte_cnt: number of bytes to read
2816  *      @cont: whether another operation will be chained
2817  *      @lock: whether to lock SF for PL access only
2818  *      @valp: where to store the read data
2819  *
2820  *      Reads up to 4 bytes of data from the serial flash.  The location of
2821  *      the read needs to be specified prior to calling this by issuing the
2822  *      appropriate commands to the serial flash.
2823  */
2824 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2825                     int lock, u32 *valp)
2826 {
2827         int ret;
2828
2829         if (!byte_cnt || byte_cnt > 4)
2830                 return -EINVAL;
2831         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2832                 return -EBUSY;
2833         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2834                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2835         ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2836         if (!ret)
2837                 *valp = t4_read_reg(adapter, SF_DATA_A);
2838         return ret;
2839 }
2840
2841 /**
2842  *      sf1_write - write data to the serial flash
2843  *      @adapter: the adapter
2844  *      @byte_cnt: number of bytes to write
2845  *      @cont: whether another operation will be chained
2846  *      @lock: whether to lock SF for PL access only
2847  *      @val: value to write
2848  *
2849  *      Writes up to 4 bytes of data to the serial flash.  The location of
2850  *      the write needs to be specified prior to calling this by issuing the
2851  *      appropriate commands to the serial flash.
2852  */
2853 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2854                      int lock, u32 val)
2855 {
2856         if (!byte_cnt || byte_cnt > 4)
2857                 return -EINVAL;
2858         if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2859                 return -EBUSY;
2860         t4_write_reg(adapter, SF_DATA_A, val);
2861         t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2862                      SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2863         return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2864 }
2865
2866 /**
2867  *      flash_wait_op - wait for a flash operation to complete
2868  *      @adapter: the adapter
2869  *      @attempts: max number of polls of the status register
2870  *      @delay: delay between polls in ms
2871  *
2872  *      Wait for a flash operation to complete by polling the status register.
2873  */
2874 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2875 {
2876         int ret;
2877         u32 status;
2878
2879         while (1) {
2880                 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2881                     (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2882                         return ret;
2883                 if (!(status & 1))
2884                         return 0;
2885                 if (--attempts == 0)
2886                         return -EAGAIN;
2887                 if (delay)
2888                         msleep(delay);
2889         }
2890 }
2891
2892 /**
2893  *      t4_read_flash - read words from serial flash
2894  *      @adapter: the adapter
2895  *      @addr: the start address for the read
2896  *      @nwords: how many 32-bit words to read
2897  *      @data: where to store the read data
2898  *      @byte_oriented: whether to store data as bytes or as words
2899  *
2900  *      Read the specified number of 32-bit words from the serial flash.
2901  *      If @byte_oriented is set the read data is stored as a byte array
2902  *      (i.e., big-endian), otherwise as 32-bit words in the platform's
2903  *      natural endianness.
2904  */
2905 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2906                   unsigned int nwords, u32 *data, int byte_oriented)
2907 {
2908         int ret;
2909
2910         if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2911                 return -EINVAL;
2912
2913         addr = swab32(addr) | SF_RD_DATA_FAST;
2914
2915         if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2916             (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2917                 return ret;
2918
2919         for ( ; nwords; nwords--, data++) {
2920                 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2921                 if (nwords == 1)
2922                         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2923                 if (ret)
2924                         return ret;
2925                 if (byte_oriented)
2926                         *data = (__force __u32)(cpu_to_be32(*data));
2927         }
2928         return 0;
2929 }
2930
2931 /**
2932  *      t4_write_flash - write up to a page of data to the serial flash
2933  *      @adapter: the adapter
2934  *      @addr: the start address to write
2935  *      @n: length of data to write in bytes
2936  *      @data: the data to write
2937  *
2938  *      Writes up to a page of data (256 bytes) to the serial flash starting
2939  *      at the given address.  All the data must be written to the same page.
2940  */
2941 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2942                           unsigned int n, const u8 *data)
2943 {
2944         int ret;
2945         u32 buf[64];
2946         unsigned int i, c, left, val, offset = addr & 0xff;
2947
2948         if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2949                 return -EINVAL;
2950
2951         val = swab32(addr) | SF_PROG_PAGE;
2952
2953         if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2954             (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2955                 goto unlock;
2956
2957         for (left = n; left; left -= c) {
2958                 c = min(left, 4U);
2959                 for (val = 0, i = 0; i < c; ++i)
2960                         val = (val << 8) + *data++;
2961
2962                 ret = sf1_write(adapter, c, c != left, 1, val);
2963                 if (ret)
2964                         goto unlock;
2965         }
2966         ret = flash_wait_op(adapter, 8, 1);
2967         if (ret)
2968                 goto unlock;
2969
2970         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2971
2972         /* Read the page to verify the write succeeded */
2973         ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2974         if (ret)
2975                 return ret;
2976
2977         if (memcmp(data - n, (u8 *)buf + offset, n)) {
2978                 dev_err(adapter->pdev_dev,
2979                         "failed to correctly write the flash page at %#x\n",
2980                         addr);
2981                 return -EIO;
2982         }
2983         return 0;
2984
2985 unlock:
2986         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
2987         return ret;
2988 }
2989
2990 /**
2991  *      t4_get_fw_version - read the firmware version
2992  *      @adapter: the adapter
2993  *      @vers: where to place the version
2994  *
2995  *      Reads the FW version from flash.
2996  */
2997 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2998 {
2999         return t4_read_flash(adapter, FLASH_FW_START +
3000                              offsetof(struct fw_hdr, fw_ver), 1,
3001                              vers, 0);
3002 }
3003
3004 /**
3005  *      t4_get_bs_version - read the firmware bootstrap version
3006  *      @adapter: the adapter
3007  *      @vers: where to place the version
3008  *
3009  *      Reads the FW Bootstrap version from flash.
3010  */
3011 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3012 {
3013         return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3014                              offsetof(struct fw_hdr, fw_ver), 1,
3015                              vers, 0);
3016 }
3017
3018 /**
3019  *      t4_get_tp_version - read the TP microcode version
3020  *      @adapter: the adapter
3021  *      @vers: where to place the version
3022  *
3023  *      Reads the TP microcode version from flash.
3024  */
3025 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3026 {
3027         return t4_read_flash(adapter, FLASH_FW_START +
3028                              offsetof(struct fw_hdr, tp_microcode_ver),
3029                              1, vers, 0);
3030 }
3031
3032 /**
3033  *      t4_get_exprom_version - return the Expansion ROM version (if any)
3034  *      @adapter: the adapter
3035  *      @vers: where to place the version
3036  *
3037  *      Reads the Expansion ROM header from FLASH and returns the version
3038  *      number (if present) through the @vers return value pointer.  We return
3039  *      this in the Firmware Version Format since it's convenient.  Return
3040  *      0 on success, -ENOENT if no Expansion ROM is present.
3041  */
3042 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3043 {
3044         struct exprom_header {
3045                 unsigned char hdr_arr[16];      /* must start with 0x55aa */
3046                 unsigned char hdr_ver[4];       /* Expansion ROM version */
3047         } *hdr;
3048         u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3049                                            sizeof(u32))];
3050         int ret;
3051
3052         ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3053                             ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3054                             0);
3055         if (ret)
3056                 return ret;
3057
3058         hdr = (struct exprom_header *)exprom_header_buf;
3059         if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3060                 return -ENOENT;
3061
3062         *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3063                  FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3064                  FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3065                  FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3066         return 0;
3067 }
3068
3069 /**
3070  *      t4_get_vpd_version - return the VPD version
3071  *      @adapter: the adapter
3072  *      @vers: where to place the version
3073  *
3074  *      Reads the VPD via the Firmware interface (thus this can only be called
3075  *      once we're ready to issue Firmware commands).  The format of the
3076  *      VPD version is adapter specific.  Returns 0 on success, an error on
3077  *      failure.
3078  *
3079  *      Note that early versions of the Firmware didn't include the ability
3080  *      to retrieve the VPD version, so we zero-out the return-value parameter
3081  *      in that case to avoid leaving it with garbage in it.
3082  *
3083  *      Also note that the Firmware will return its cached copy of the VPD
3084  *      Revision ID, not the actual Revision ID as written in the Serial
3085  *      EEPROM.  This is only an issue if a new VPD has been written and the
3086  *      Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3087  *      to defer calling this routine till after a FW_RESET_CMD has been issued
3088  *      if the Host Driver will be performing a full adapter initialization.
3089  */
3090 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3091 {
3092         u32 vpdrev_param;
3093         int ret;
3094
3095         vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3096                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3097         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3098                               1, &vpdrev_param, vers);
3099         if (ret)
3100                 *vers = 0;
3101         return ret;
3102 }
3103
3104 /**
3105  *      t4_get_scfg_version - return the Serial Configuration version
3106  *      @adapter: the adapter
3107  *      @vers: where to place the version
3108  *
3109  *      Reads the Serial Configuration Version via the Firmware interface
3110  *      (thus this can only be called once we're ready to issue Firmware
3111  *      commands).  The format of the Serial Configuration version is
3112  *      adapter specific.  Returns 0 on success, an error on failure.
3113  *
3114  *      Note that early versions of the Firmware didn't include the ability
3115  *      to retrieve the Serial Configuration version, so we zero-out the
3116  *      return-value parameter in that case to avoid leaving it with
3117  *      garbage in it.
3118  *
3119  *      Also note that the Firmware will return its cached copy of the Serial
3120  *      Initialization Revision ID, not the actual Revision ID as written in
3121  *      the Serial EEPROM.  This is only an issue if a new VPD has been written
3122  *      and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3123  *      it's best to defer calling this routine till after a FW_RESET_CMD has
3124  *      been issued if the Host Driver will be performing a full adapter
3125  *      initialization.
3126  */
3127 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3128 {
3129         u32 scfgrev_param;
3130         int ret;
3131
3132         scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3133                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3134         ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3135                               1, &scfgrev_param, vers);
3136         if (ret)
3137                 *vers = 0;
3138         return ret;
3139 }
3140
3141 /**
3142  *      t4_get_version_info - extract various chip/firmware version information
3143  *      @adapter: the adapter
3144  *
3145  *      Reads various chip/firmware version numbers and stores them into the
3146  *      adapter Adapter Parameters structure.  If any of the efforts fails
3147  *      the first failure will be returned, but all of the version numbers
3148  *      will be read.
3149  */
3150 int t4_get_version_info(struct adapter *adapter)
3151 {
3152         int ret = 0;
3153
3154         #define FIRST_RET(__getvinfo) \
3155         do { \
3156                 int __ret = __getvinfo; \
3157                 if (__ret && !ret) \
3158                         ret = __ret; \
3159         } while (0)
3160
3161         FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3162         FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3163         FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3164         FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3165         FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3166         FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3167
3168         #undef FIRST_RET
3169         return ret;
3170 }
3171
3172 /**
3173  *      t4_dump_version_info - dump all of the adapter configuration IDs
3174  *      @adapter: the adapter
3175  *
3176  *      Dumps all of the various bits of adapter configuration version/revision
3177  *      IDs information.  This is typically called at some point after
3178  *      t4_get_version_info() has been called.
3179  */
3180 void t4_dump_version_info(struct adapter *adapter)
3181 {
3182         /* Device information */
3183         dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3184                  adapter->params.vpd.id,
3185                  CHELSIO_CHIP_RELEASE(adapter->params.chip));
3186         dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3187                  adapter->params.vpd.sn, adapter->params.vpd.pn);
3188
3189         /* Firmware Version */
3190         if (!adapter->params.fw_vers)
3191                 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3192         else
3193                 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3194                          FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3195                          FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3196                          FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3197                          FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3198
3199         /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3200          * Firmware, so dev_info() is more appropriate here.)
3201          */
3202         if (!adapter->params.bs_vers)
3203                 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3204         else
3205                 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3206                          FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3207                          FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3208                          FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3209                          FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3210
3211         /* TP Microcode Version */
3212         if (!adapter->params.tp_vers)
3213                 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3214         else
3215                 dev_info(adapter->pdev_dev,
3216                          "TP Microcode version: %u.%u.%u.%u\n",
3217                          FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3218                          FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3219                          FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3220                          FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3221
3222         /* Expansion ROM version */
3223         if (!adapter->params.er_vers)
3224                 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3225         else
3226                 dev_info(adapter->pdev_dev,
3227                          "Expansion ROM version: %u.%u.%u.%u\n",
3228                          FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3229                          FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3230                          FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3231                          FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3232
3233         /* Serial Configuration version */
3234         dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3235                  adapter->params.scfg_vers);
3236
3237         /* VPD Version */
3238         dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3239                  adapter->params.vpd_vers);
3240 }
3241
3242 /**
3243  *      t4_check_fw_version - check if the FW is supported with this driver
3244  *      @adap: the adapter
3245  *
3246  *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3247  *      if there's exact match, a negative error if the version could not be
3248  *      read or there's a major version mismatch
3249  */
3250 int t4_check_fw_version(struct adapter *adap)
3251 {
3252         int i, ret, major, minor, micro;
3253         int exp_major, exp_minor, exp_micro;
3254         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3255
3256         ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3257         /* Try multiple times before returning error */
3258         for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3259                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3260
3261         if (ret)
3262                 return ret;
3263
3264         major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3265         minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3266         micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3267
3268         switch (chip_version) {
3269         case CHELSIO_T4:
3270                 exp_major = T4FW_MIN_VERSION_MAJOR;
3271                 exp_minor = T4FW_MIN_VERSION_MINOR;
3272                 exp_micro = T4FW_MIN_VERSION_MICRO;
3273                 break;
3274         case CHELSIO_T5:
3275                 exp_major = T5FW_MIN_VERSION_MAJOR;
3276                 exp_minor = T5FW_MIN_VERSION_MINOR;
3277                 exp_micro = T5FW_MIN_VERSION_MICRO;
3278                 break;
3279         case CHELSIO_T6:
3280                 exp_major = T6FW_MIN_VERSION_MAJOR;
3281                 exp_minor = T6FW_MIN_VERSION_MINOR;
3282                 exp_micro = T6FW_MIN_VERSION_MICRO;
3283                 break;
3284         default:
3285                 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3286                         adap->chip);
3287                 return -EINVAL;
3288         }
3289
3290         if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3291             (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3292                 dev_err(adap->pdev_dev,
3293                         "Card has firmware version %u.%u.%u, minimum "
3294                         "supported firmware is %u.%u.%u.\n", major, minor,
3295                         micro, exp_major, exp_minor, exp_micro);
3296                 return -EFAULT;
3297         }
3298         return 0;
3299 }
3300
3301 /* Is the given firmware API compatible with the one the driver was compiled
3302  * with?
3303  */
3304 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3305 {
3306
3307         /* short circuit if it's the exact same firmware version */
3308         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3309                 return 1;
3310
3311 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3312         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3313             SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3314                 return 1;
3315 #undef SAME_INTF
3316
3317         return 0;
3318 }
3319
3320 /* The firmware in the filesystem is usable, but should it be installed?
3321  * This routine explains itself in detail if it indicates the filesystem
3322  * firmware should be installed.
3323  */
3324 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3325                                 int k, int c)
3326 {
3327         const char *reason;
3328
3329         if (!card_fw_usable) {
3330                 reason = "incompatible or unusable";
3331                 goto install;
3332         }
3333
3334         if (k > c) {
3335                 reason = "older than the version supported with this driver";
3336                 goto install;
3337         }
3338
3339         return 0;
3340
3341 install:
3342         dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3343                 "installing firmware %u.%u.%u.%u on card.\n",
3344                 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3345                 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3346                 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3347                 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3348
3349         return 1;
3350 }
3351
3352 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3353                const u8 *fw_data, unsigned int fw_size,
3354                struct fw_hdr *card_fw, enum dev_state state,
3355                int *reset)
3356 {
3357         int ret, card_fw_usable, fs_fw_usable;
3358         const struct fw_hdr *fs_fw;
3359         const struct fw_hdr *drv_fw;
3360
3361         drv_fw = &fw_info->fw_hdr;
3362
3363         /* Read the header of the firmware on the card */
3364         ret = t4_read_flash(adap, FLASH_FW_START,
3365                             sizeof(*card_fw) / sizeof(uint32_t),
3366                             (uint32_t *)card_fw, 1);
3367         if (ret == 0) {
3368                 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3369         } else {
3370                 dev_err(adap->pdev_dev,
3371                         "Unable to read card's firmware header: %d\n", ret);
3372                 card_fw_usable = 0;
3373         }
3374
3375         if (fw_data != NULL) {
3376                 fs_fw = (const void *)fw_data;
3377                 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3378         } else {
3379                 fs_fw = NULL;
3380                 fs_fw_usable = 0;
3381         }
3382
3383         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3384             (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3385                 /* Common case: the firmware on the card is an exact match and
3386                  * the filesystem one is an exact match too, or the filesystem
3387                  * one is absent/incompatible.
3388                  */
3389         } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3390                    should_install_fs_fw(adap, card_fw_usable,
3391                                         be32_to_cpu(fs_fw->fw_ver),
3392                                         be32_to_cpu(card_fw->fw_ver))) {
3393                 ret = t4_fw_upgrade(adap, adap->mbox, fw_data,
3394                                     fw_size, 0);
3395                 if (ret != 0) {
3396                         dev_err(adap->pdev_dev,
3397                                 "failed to install firmware: %d\n", ret);
3398                         goto bye;
3399                 }
3400
3401                 /* Installed successfully, update the cached header too. */
3402                 *card_fw = *fs_fw;
3403                 card_fw_usable = 1;
3404                 *reset = 0;     /* already reset as part of load_fw */
3405         }
3406
3407         if (!card_fw_usable) {
3408                 uint32_t d, c, k;
3409
3410                 d = be32_to_cpu(drv_fw->fw_ver);
3411                 c = be32_to_cpu(card_fw->fw_ver);
3412                 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3413
3414                 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3415                         "chip state %d, "
3416                         "driver compiled with %d.%d.%d.%d, "
3417                         "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3418                         state,
3419                         FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3420                         FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3421                         FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3422                         FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3423                         FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3424                         FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3425                 ret = -EINVAL;
3426                 goto bye;
3427         }
3428
3429         /* We're using whatever's on the card and it's known to be good. */
3430         adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3431         adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3432
3433 bye:
3434         return ret;
3435 }
3436
3437 /**
3438  *      t4_flash_erase_sectors - erase a range of flash sectors
3439  *      @adapter: the adapter
3440  *      @start: the first sector to erase
3441  *      @end: the last sector to erase
3442  *
3443  *      Erases the sectors in the given inclusive range.
3444  */
3445 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3446 {
3447         int ret = 0;
3448
3449         if (end >= adapter->params.sf_nsec)
3450                 return -EINVAL;
3451
3452         while (start <= end) {
3453                 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3454                     (ret = sf1_write(adapter, 4, 0, 1,
3455                                      SF_ERASE_SECTOR | (start << 8))) != 0 ||
3456                     (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3457                         dev_err(adapter->pdev_dev,
3458                                 "erase of flash sector %d failed, error %d\n",
3459                                 start, ret);
3460                         break;
3461                 }
3462                 start++;
3463         }
3464         t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3465         return ret;
3466 }
3467
3468 /**
3469  *      t4_flash_cfg_addr - return the address of the flash configuration file
3470  *      @adapter: the adapter
3471  *
3472  *      Return the address within the flash where the Firmware Configuration
3473  *      File is stored.
3474  */
3475 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3476 {
3477         if (adapter->params.sf_size == 0x100000)
3478                 return FLASH_FPGA_CFG_START;
3479         else
3480                 return FLASH_CFG_START;
3481 }
3482
3483 /* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3484  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3485  * and emit an error message for mismatched firmware to save our caller the
3486  * effort ...
3487  */
3488 static bool t4_fw_matches_chip(const struct adapter *adap,
3489                                const struct fw_hdr *hdr)
3490 {
3491         /* The expression below will return FALSE for any unsupported adapter
3492          * which will keep us "honest" in the future ...
3493          */
3494         if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3495             (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3496             (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3497                 return true;
3498
3499         dev_err(adap->pdev_dev,
3500                 "FW image (%d) is not suitable for this adapter (%d)\n",
3501                 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3502         return false;
3503 }
3504
3505 /**
3506  *      t4_load_fw - download firmware
3507  *      @adap: the adapter
3508  *      @fw_data: the firmware image to write
3509  *      @size: image size
3510  *
3511  *      Write the supplied firmware image to the card's serial flash.
3512  */
3513 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3514 {
3515         u32 csum;
3516         int ret, addr;
3517         unsigned int i;
3518         u8 first_page[SF_PAGE_SIZE];
3519         const __be32 *p = (const __be32 *)fw_data;
3520         const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3521         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3522         unsigned int fw_img_start = adap->params.sf_fw_start;
3523         unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3524
3525         if (!size) {
3526                 dev_err(adap->pdev_dev, "FW image has no data\n");
3527                 return -EINVAL;
3528         }
3529         if (size & 511) {
3530                 dev_err(adap->pdev_dev,
3531                         "FW image size not multiple of 512 bytes\n");
3532                 return -EINVAL;
3533         }
3534         if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3535                 dev_err(adap->pdev_dev,
3536                         "FW image size differs from size in FW header\n");
3537                 return -EINVAL;
3538         }
3539         if (size > FW_MAX_SIZE) {
3540                 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3541                         FW_MAX_SIZE);
3542                 return -EFBIG;
3543         }
3544         if (!t4_fw_matches_chip(adap, hdr))
3545                 return -EINVAL;
3546
3547         for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3548                 csum += be32_to_cpu(p[i]);
3549
3550         if (csum != 0xffffffff) {
3551                 dev_err(adap->pdev_dev,
3552                         "corrupted firmware image, checksum %#x\n", csum);
3553                 return -EINVAL;
3554         }
3555
3556         i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3557         ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3558         if (ret)
3559                 goto out;
3560
3561         /*
3562          * We write the correct version at the end so the driver can see a bad
3563          * version if the FW write fails.  Start by writing a copy of the
3564          * first page with a bad version.
3565          */
3566         memcpy(first_page, fw_data, SF_PAGE_SIZE);
3567         ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3568         ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3569         if (ret)
3570                 goto out;
3571
3572         addr = fw_img_start;
3573         for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3574                 addr += SF_PAGE_SIZE;
3575                 fw_data += SF_PAGE_SIZE;
3576                 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3577                 if (ret)
3578                         goto out;
3579         }
3580
3581         ret = t4_write_flash(adap,
3582                              fw_img_start + offsetof(struct fw_hdr, fw_ver),
3583                              sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3584 out:
3585         if (ret)
3586                 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3587                         ret);
3588         else
3589                 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3590         return ret;
3591 }
3592
3593 /**
3594  *      t4_phy_fw_ver - return current PHY firmware version
3595  *      @adap: the adapter
3596  *      @phy_fw_ver: return value buffer for PHY firmware version
3597  *
3598  *      Returns the current version of external PHY firmware on the
3599  *      adapter.
3600  */
3601 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3602 {
3603         u32 param, val;
3604         int ret;
3605
3606         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3607                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3608                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3609                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3610         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3611                               &param, &val);
3612         if (ret)
3613                 return ret;
3614         *phy_fw_ver = val;
3615         return 0;
3616 }
3617
3618 /**
3619  *      t4_load_phy_fw - download port PHY firmware
3620  *      @adap: the adapter
3621  *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3622  *      @win_lock: the lock to use to guard the memory copy
3623  *      @phy_fw_version: function to check PHY firmware versions
3624  *      @phy_fw_data: the PHY firmware image to write
3625  *      @phy_fw_size: image size
3626  *
3627  *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3628  *      @phy_fw_version is supplied, then it will be used to determine if
3629  *      it's necessary to perform the transfer by comparing the version
3630  *      of any existing adapter PHY firmware with that of the passed in
3631  *      PHY firmware image.  If @win_lock is non-NULL then it will be used
3632  *      around the call to t4_memory_rw() which transfers the PHY firmware
3633  *      to the adapter.
3634  *
3635  *      A negative error number will be returned if an error occurs.  If
3636  *      version number support is available and there's no need to upgrade
3637  *      the firmware, 0 will be returned.  If firmware is successfully
3638  *      transferred to the adapter, 1 will be retured.
3639  *
3640  *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3641  *      a result, a RESET of the adapter would cause that RAM to lose its
3642  *      contents.  Thus, loading PHY firmware on such adapters must happen
3643  *      after any FW_RESET_CMDs ...
3644  */
3645 int t4_load_phy_fw(struct adapter *adap,
3646                    int win, spinlock_t *win_lock,
3647                    int (*phy_fw_version)(const u8 *, size_t),
3648                    const u8 *phy_fw_data, size_t phy_fw_size)
3649 {
3650         unsigned long mtype = 0, maddr = 0;
3651         u32 param, val;
3652         int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3653         int ret;
3654
3655         /* If we have version number support, then check to see if the adapter
3656          * already has up-to-date PHY firmware loaded.
3657          */
3658          if (phy_fw_version) {
3659                 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3660                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3661                 if (ret < 0)
3662                         return ret;
3663
3664                 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3665                         CH_WARN(adap, "PHY Firmware already up-to-date, "
3666                                 "version %#x\n", cur_phy_fw_ver);
3667                         return 0;
3668                 }
3669         }
3670
3671         /* Ask the firmware where it wants us to copy the PHY firmware image.
3672          * The size of the file requires a special version of the READ coommand
3673          * which will pass the file size via the values field in PARAMS_CMD and
3674          * retrieve the return value from firmware and place it in the same
3675          * buffer values
3676          */
3677         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3678                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3679                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3680                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3681         val = phy_fw_size;
3682         ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3683                                  &param, &val, 1, true);
3684         if (ret < 0)
3685                 return ret;
3686         mtype = val >> 8;
3687         maddr = (val & 0xff) << 16;
3688
3689         /* Copy the supplied PHY Firmware image to the adapter memory location
3690          * allocated by the adapter firmware.
3691          */
3692         if (win_lock)
3693                 spin_lock_bh(win_lock);
3694         ret = t4_memory_rw(adap, win, mtype, maddr,
3695                            phy_fw_size, (__be32 *)phy_fw_data,
3696                            T4_MEMORY_WRITE);
3697         if (win_lock)
3698                 spin_unlock_bh(win_lock);
3699         if (ret)
3700                 return ret;
3701
3702         /* Tell the firmware that the PHY firmware image has been written to
3703          * RAM and it can now start copying it over to the PHYs.  The chip
3704          * firmware will RESET the affected PHYs as part of this operation
3705          * leaving them running the new PHY firmware image.
3706          */
3707         param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3708                  FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3709                  FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3710                  FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3711         ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3712                                     &param, &val, 30000);
3713         if (ret)
3714                 return ret;
3715
3716         /* If we have version number support, then check to see that the new
3717          * firmware got loaded properly.
3718          */
3719         if (phy_fw_version) {
3720                 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3721                 if (ret < 0)
3722                         return ret;
3723
3724                 if (cur_phy_fw_ver != new_phy_fw_vers) {
3725                         CH_WARN(adap, "PHY Firmware did not update: "
3726                                 "version on adapter %#x, "
3727                                 "version flashed %#x\n",
3728                                 cur_phy_fw_ver, new_phy_fw_vers);
3729                         return -ENXIO;
3730                 }
3731         }
3732
3733         return 1;
3734 }
3735
3736 /**
3737  *      t4_fwcache - firmware cache operation
3738  *      @adap: the adapter
3739  *      @op  : the operation (flush or flush and invalidate)
3740  */
3741 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3742 {
3743         struct fw_params_cmd c;
3744
3745         memset(&c, 0, sizeof(c));
3746         c.op_to_vfn =
3747                 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3748                             FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3749                             FW_PARAMS_CMD_PFN_V(adap->pf) |
3750                             FW_PARAMS_CMD_VFN_V(0));
3751         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3752         c.param[0].mnem =
3753                 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3754                             FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3755         c.param[0].val = cpu_to_be32(op);
3756
3757         return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3758 }
3759
3760 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3761                         unsigned int *pif_req_wrptr,
3762                         unsigned int *pif_rsp_wrptr)
3763 {
3764         int i, j;
3765         u32 cfg, val, req, rsp;
3766
3767         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3768         if (cfg & LADBGEN_F)
3769                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3770
3771         val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3772         req = POLADBGWRPTR_G(val);
3773         rsp = PILADBGWRPTR_G(val);
3774         if (pif_req_wrptr)
3775                 *pif_req_wrptr = req;
3776         if (pif_rsp_wrptr)
3777                 *pif_rsp_wrptr = rsp;
3778
3779         for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3780                 for (j = 0; j < 6; j++) {
3781                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3782                                      PILADBGRDPTR_V(rsp));
3783                         *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3784                         *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3785                         req++;
3786                         rsp++;
3787                 }
3788                 req = (req + 2) & POLADBGRDPTR_M;
3789                 rsp = (rsp + 2) & PILADBGRDPTR_M;
3790         }
3791         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3792 }
3793
3794 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3795 {
3796         u32 cfg;
3797         int i, j, idx;
3798
3799         cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3800         if (cfg & LADBGEN_F)
3801                 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3802
3803         for (i = 0; i < CIM_MALA_SIZE; i++) {
3804                 for (j = 0; j < 5; j++) {
3805                         idx = 8 * i + j;
3806                         t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3807                                      PILADBGRDPTR_V(idx));
3808                         *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3809                         *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3810                 }
3811         }
3812         t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3813 }
3814
3815 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3816 {
3817         unsigned int i, j;
3818
3819         for (i = 0; i < 8; i++) {
3820                 u32 *p = la_buf + i;
3821
3822                 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3823                 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3824                 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3825                 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3826                         *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3827         }
3828 }
3829
3830 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3831                      FW_PORT_CAP32_ANEG)
3832
3833 /**
3834  *      fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3835  *      @caps16: a 16-bit Port Capabilities value
3836  *
3837  *      Returns the equivalent 32-bit Port Capabilities value.
3838  */
3839 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3840 {
3841         fw_port_cap32_t caps32 = 0;
3842
3843         #define CAP16_TO_CAP32(__cap) \
3844                 do { \
3845                         if (caps16 & FW_PORT_CAP_##__cap) \
3846                                 caps32 |= FW_PORT_CAP32_##__cap; \
3847                 } while (0)
3848
3849         CAP16_TO_CAP32(SPEED_100M);
3850         CAP16_TO_CAP32(SPEED_1G);
3851         CAP16_TO_CAP32(SPEED_25G);
3852         CAP16_TO_CAP32(SPEED_10G);
3853         CAP16_TO_CAP32(SPEED_40G);
3854         CAP16_TO_CAP32(SPEED_100G);
3855         CAP16_TO_CAP32(FC_RX);
3856         CAP16_TO_CAP32(FC_TX);
3857         CAP16_TO_CAP32(ANEG);
3858         CAP16_TO_CAP32(MDIX);
3859         CAP16_TO_CAP32(MDIAUTO);
3860         CAP16_TO_CAP32(FEC_RS);
3861         CAP16_TO_CAP32(FEC_BASER_RS);
3862         CAP16_TO_CAP32(802_3_PAUSE);
3863         CAP16_TO_CAP32(802_3_ASM_DIR);
3864
3865         #undef CAP16_TO_CAP32
3866
3867         return caps32;
3868 }
3869
3870 /**
3871  *      fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3872  *      @caps32: a 32-bit Port Capabilities value
3873  *
3874  *      Returns the equivalent 16-bit Port Capabilities value.  Note that
3875  *      not all 32-bit Port Capabilities can be represented in the 16-bit
3876  *      Port Capabilities and some fields/values may not make it.
3877  */
3878 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
3879 {
3880         fw_port_cap16_t caps16 = 0;
3881
3882         #define CAP32_TO_CAP16(__cap) \
3883                 do { \
3884                         if (caps32 & FW_PORT_CAP32_##__cap) \
3885                                 caps16 |= FW_PORT_CAP_##__cap; \
3886                 } while (0)
3887
3888         CAP32_TO_CAP16(SPEED_100M);
3889         CAP32_TO_CAP16(SPEED_1G);
3890         CAP32_TO_CAP16(SPEED_10G);
3891         CAP32_TO_CAP16(SPEED_25G);
3892         CAP32_TO_CAP16(SPEED_40G);
3893         CAP32_TO_CAP16(SPEED_100G);
3894         CAP32_TO_CAP16(FC_RX);
3895         CAP32_TO_CAP16(FC_TX);
3896         CAP32_TO_CAP16(802_3_PAUSE);
3897         CAP32_TO_CAP16(802_3_ASM_DIR);
3898         CAP32_TO_CAP16(ANEG);
3899         CAP32_TO_CAP16(MDIX);
3900         CAP32_TO_CAP16(MDIAUTO);
3901         CAP32_TO_CAP16(FEC_RS);
3902         CAP32_TO_CAP16(FEC_BASER_RS);
3903
3904         #undef CAP32_TO_CAP16
3905
3906         return caps16;
3907 }
3908
3909 /* Translate Firmware Port Capabilities Pause specification to Common Code */
3910 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
3911 {
3912         enum cc_pause cc_pause = 0;
3913
3914         if (fw_pause & FW_PORT_CAP32_FC_RX)
3915                 cc_pause |= PAUSE_RX;
3916         if (fw_pause & FW_PORT_CAP32_FC_TX)
3917                 cc_pause |= PAUSE_TX;
3918
3919         return cc_pause;
3920 }
3921
3922 /* Translate Common Code Pause specification into Firmware Port Capabilities */
3923 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
3924 {
3925         fw_port_cap32_t fw_pause = 0;
3926
3927         if (cc_pause & PAUSE_RX)
3928                 fw_pause |= FW_PORT_CAP32_FC_RX;
3929         if (cc_pause & PAUSE_TX)
3930                 fw_pause |= FW_PORT_CAP32_FC_TX;
3931
3932         return fw_pause;
3933 }
3934
3935 /* Translate Firmware Forward Error Correction specification to Common Code */
3936 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
3937 {
3938         enum cc_fec cc_fec = 0;
3939
3940         if (fw_fec & FW_PORT_CAP32_FEC_RS)
3941                 cc_fec |= FEC_RS;
3942         if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
3943                 cc_fec |= FEC_BASER_RS;
3944
3945         return cc_fec;
3946 }
3947
3948 /* Translate Common Code Forward Error Correction specification to Firmware */
3949 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
3950 {
3951         fw_port_cap32_t fw_fec = 0;
3952
3953         if (cc_fec & FEC_RS)
3954                 fw_fec |= FW_PORT_CAP32_FEC_RS;
3955         if (cc_fec & FEC_BASER_RS)
3956                 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
3957
3958         return fw_fec;
3959 }
3960
3961 /**
3962  *      t4_link_l1cfg - apply link configuration to MAC/PHY
3963  *      @adapter: the adapter
3964  *      @mbox: the Firmware Mailbox to use
3965  *      @port: the Port ID
3966  *      @lc: the Port's Link Configuration
3967  *
3968  *      Set up a port's MAC and PHY according to a desired link configuration.
3969  *      - If the PHY can auto-negotiate first decide what to advertise, then
3970  *        enable/disable auto-negotiation as desired, and reset.
3971  *      - If the PHY does not auto-negotiate just reset it.
3972  *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3973  *        otherwise do it later based on the outcome of auto-negotiation.
3974  */
3975 int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
3976                   unsigned int port, struct link_config *lc)
3977 {
3978         unsigned int fw_caps = adapter->params.fw_caps_support;
3979         struct fw_port_cmd cmd;
3980         unsigned int fw_mdi = FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO);
3981         fw_port_cap32_t fw_fc, cc_fec, fw_fec, rcap;
3982
3983         lc->link_ok = 0;
3984
3985         /* Convert driver coding of Pause Frame Flow Control settings into the
3986          * Firmware's API.
3987          */
3988         fw_fc = cc_to_fwcap_pause(lc->requested_fc);
3989
3990         /* Convert Common Code Forward Error Control settings into the
3991          * Firmware's API.  If the current Requested FEC has "Automatic"
3992          * (IEEE 802.3) specified, then we use whatever the Firmware
3993          * sent us as part of it's IEEE 802.3-based interpratation of
3994          * the Transceiver Module EPROM FEC parameters.  Otherwise we
3995          * use whatever is in the current Requested FEC settings.
3996          */
3997         if (lc->requested_fec & FEC_AUTO)
3998                 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
3999         else
4000                 cc_fec = lc->requested_fec;
4001         fw_fec = cc_to_fwcap_fec(cc_fec);
4002
4003         /* Figure out what our Requested Port Capabilities are going to be.
4004          */
4005         if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4006                 rcap = (lc->pcaps & ADVERT_MASK) | fw_fc | fw_fec;
4007                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4008                 lc->fec = cc_fec;
4009         } else if (lc->autoneg == AUTONEG_DISABLE) {
4010                 rcap = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4011                 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4012                 lc->fec = cc_fec;
4013         } else {
4014                 rcap = lc->acaps | fw_fc | fw_fec | fw_mdi;
4015         }
4016
4017         /* And send that on to the Firmware ...
4018          */
4019         memset(&cmd, 0, sizeof(cmd));
4020         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4021                                        FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4022                                        FW_PORT_CMD_PORTID_V(port));
4023         cmd.action_to_len16 =
4024                 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4025                                                  ? FW_PORT_ACTION_L1_CFG
4026                                                  : FW_PORT_ACTION_L1_CFG32) |
4027                             FW_LEN16(cmd));
4028         if (fw_caps == FW_CAPS16)
4029                 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4030         else
4031                 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4032         return t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4033 }
4034
4035 /**
4036  *      t4_restart_aneg - restart autonegotiation
4037  *      @adap: the adapter
4038  *      @mbox: mbox to use for the FW command
4039  *      @port: the port id
4040  *
4041  *      Restarts autonegotiation for the selected port.
4042  */
4043 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4044 {
4045         struct fw_port_cmd c;
4046
4047         memset(&c, 0, sizeof(c));
4048         c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4049                                      FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4050                                      FW_PORT_CMD_PORTID_V(port));
4051         c.action_to_len16 =
4052                 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
4053                             FW_LEN16(c));
4054         c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP32_ANEG);
4055         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4056 }
4057
4058 typedef void (*int_handler_t)(struct adapter *adap);
4059
4060 struct intr_info {
4061         unsigned int mask;       /* bits to check in interrupt status */
4062         const char *msg;         /* message to print or NULL */
4063         short stat_idx;          /* stat counter to increment or -1 */
4064         unsigned short fatal;    /* whether the condition reported is fatal */
4065         int_handler_t int_handler; /* platform-specific int handler */
4066 };
4067
4068 /**
4069  *      t4_handle_intr_status - table driven interrupt handler
4070  *      @adapter: the adapter that generated the interrupt
4071  *      @reg: the interrupt status register to process
4072  *      @acts: table of interrupt actions
4073  *
4074  *      A table driven interrupt handler that applies a set of masks to an
4075  *      interrupt status word and performs the corresponding actions if the
4076  *      interrupts described by the mask have occurred.  The actions include
4077  *      optionally emitting a warning or alert message.  The table is terminated
4078  *      by an entry specifying mask 0.  Returns the number of fatal interrupt
4079  *      conditions.
4080  */
4081 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4082                                  const struct intr_info *acts)
4083 {
4084         int fatal = 0;
4085         unsigned int mask = 0;
4086         unsigned int status = t4_read_reg(adapter, reg);
4087
4088         for ( ; acts->mask; ++acts) {
4089                 if (!(status & acts->mask))
4090                         continue;
4091                 if (acts->fatal) {
4092                         fatal++;
4093                         dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4094                                   status & acts->mask);
4095                 } else if (acts->msg && printk_ratelimit())
4096                         dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4097                                  status & acts->mask);
4098                 if (acts->int_handler)
4099                         acts->int_handler(adapter);
4100                 mask |= acts->mask;
4101         }
4102         status &= mask;
4103         if (status)                           /* clear processed interrupts */
4104                 t4_write_reg(adapter, reg, status);
4105         return fatal;
4106 }
4107
4108 /*
4109  * Interrupt handler for the PCIE module.
4110  */
4111 static void pcie_intr_handler(struct adapter *adapter)
4112 {
4113         static const struct intr_info sysbus_intr_info[] = {
4114                 { RNPP_F, "RXNP array parity error", -1, 1 },
4115                 { RPCP_F, "RXPC array parity error", -1, 1 },
4116                 { RCIP_F, "RXCIF array parity error", -1, 1 },
4117                 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4118                 { RFTP_F, "RXFT array parity error", -1, 1 },
4119                 { 0 }
4120         };
4121         static const struct intr_info pcie_port_intr_info[] = {
4122                 { TPCP_F, "TXPC array parity error", -1, 1 },
4123                 { TNPP_F, "TXNP array parity error", -1, 1 },
4124                 { TFTP_F, "TXFT array parity error", -1, 1 },
4125                 { TCAP_F, "TXCA array parity error", -1, 1 },
4126                 { TCIP_F, "TXCIF array parity error", -1, 1 },
4127                 { RCAP_F, "RXCA array parity error", -1, 1 },
4128                 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4129                 { RDPE_F, "Rx data parity error", -1, 1 },
4130                 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4131                 { 0 }
4132         };
4133         static const struct intr_info pcie_intr_info[] = {
4134                 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4135                 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4136                 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4137                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4138                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4139                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4140                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4141                 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4142                 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4143                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4144                 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4145                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4146                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4147                 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4148                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4149                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4150                 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4151                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4152                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4153                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4154                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4155                 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4156                 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4157                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4158                 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4159                 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4160                 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4161                 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4162                 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4163                 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4164                   -1, 0 },
4165                 { 0 }
4166         };
4167
4168         static struct intr_info t5_pcie_intr_info[] = {
4169                 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4170                   -1, 1 },
4171                 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4172                 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4173                 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4174                 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4175                 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4176                 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4177                 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4178                   -1, 1 },
4179                 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4180                   -1, 1 },
4181                 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4182                 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4183                 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4184                 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4185                 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4186                   -1, 1 },
4187                 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4188                 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4189                 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4190                 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4191                 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4192                 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4193                 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4194                 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4195                 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4196                 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4197                 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4198                   -1, 1 },
4199                 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4200                   -1, 1 },
4201                 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4202                 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4203                 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4204                 { READRSPERR_F, "Outbound read error", -1, 0 },
4205                 { 0 }
4206         };
4207
4208         int fat;
4209
4210         if (is_t4(adapter->params.chip))
4211                 fat = t4_handle_intr_status(adapter,
4212                                 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4213                                 sysbus_intr_info) +
4214                         t4_handle_intr_status(adapter,
4215                                         PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4216                                         pcie_port_intr_info) +
4217                         t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4218                                               pcie_intr_info);
4219         else
4220                 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4221                                             t5_pcie_intr_info);
4222
4223         if (fat)
4224                 t4_fatal_err(adapter);
4225 }
4226
4227 /*
4228  * TP interrupt handler.
4229  */
4230 static void tp_intr_handler(struct adapter *adapter)
4231 {
4232         static const struct intr_info tp_intr_info[] = {
4233                 { 0x3fffffff, "TP parity error", -1, 1 },
4234                 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4235                 { 0 }
4236         };
4237
4238         if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4239                 t4_fatal_err(adapter);
4240 }
4241
4242 /*
4243  * SGE interrupt handler.
4244  */
4245 static void sge_intr_handler(struct adapter *adapter)
4246 {
4247         u64 v;
4248         u32 err;
4249
4250         static const struct intr_info sge_intr_info[] = {
4251                 { ERR_CPL_EXCEED_IQE_SIZE_F,
4252                   "SGE received CPL exceeding IQE size", -1, 1 },
4253                 { ERR_INVALID_CIDX_INC_F,
4254                   "SGE GTS CIDX increment too large", -1, 0 },
4255                 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4256                 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4257                 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4258                   "SGE IQID > 1023 received CPL for FL", -1, 0 },
4259                 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4260                   0 },
4261                 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4262                   0 },
4263                 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4264                   0 },
4265                 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4266                   0 },
4267                 { ERR_ING_CTXT_PRIO_F,
4268                   "SGE too many priority ingress contexts", -1, 0 },
4269                 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4270                 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4271                 { 0 }
4272         };
4273
4274         static struct intr_info t4t5_sge_intr_info[] = {
4275                 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4276                 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4277                 { ERR_EGR_CTXT_PRIO_F,
4278                   "SGE too many priority egress contexts", -1, 0 },
4279                 { 0 }
4280         };
4281
4282         v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
4283                 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
4284         if (v) {
4285                 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
4286                                 (unsigned long long)v);
4287                 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
4288                 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
4289         }
4290
4291         v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4292         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4293                 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4294                                            t4t5_sge_intr_info);
4295
4296         err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4297         if (err & ERROR_QID_VALID_F) {
4298                 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4299                         ERROR_QID_G(err));
4300                 if (err & UNCAPTURED_ERROR_F)
4301                         dev_err(adapter->pdev_dev,
4302                                 "SGE UNCAPTURED_ERROR set (clearing)\n");
4303                 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4304                              UNCAPTURED_ERROR_F);
4305         }
4306
4307         if (v != 0)
4308                 t4_fatal_err(adapter);
4309 }
4310
4311 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4312                       OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4313 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4314                       IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4315
4316 /*
4317  * CIM interrupt handler.
4318  */
4319 static void cim_intr_handler(struct adapter *adapter)
4320 {
4321         static const struct intr_info cim_intr_info[] = {
4322                 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4323                 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4324                 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4325                 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4326                 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4327                 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4328                 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4329                 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4330                 { 0 }
4331         };
4332         static const struct intr_info cim_upintr_info[] = {
4333                 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4334                 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4335                 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4336                 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4337                 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4338                 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4339                 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4340                 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4341                 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4342                 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4343                 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4344                 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4345                 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4346                 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4347                 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4348                 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4349                 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4350                 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4351                 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4352                 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4353                 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4354                 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4355                 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4356                 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4357                 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4358                 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4359                 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4360                 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4361                 { 0 }
4362         };
4363
4364         u32 val, fw_err;
4365         int fat;
4366
4367         fw_err = t4_read_reg(adapter, PCIE_FW_A);
4368         if (fw_err & PCIE_FW_ERR_F)
4369                 t4_report_fw_error(adapter);
4370
4371         /* When the Firmware detects an internal error which normally
4372          * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4373          * in order to make sure the Host sees the Firmware Crash.  So
4374          * if we have a Timer0 interrupt and don't see a Firmware Crash,
4375          * ignore the Timer0 interrupt.
4376          */
4377
4378         val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4379         if (val & TIMER0INT_F)
4380                 if (!(fw_err & PCIE_FW_ERR_F) ||
4381                     (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4382                         t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4383                                      TIMER0INT_F);
4384
4385         fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4386                                     cim_intr_info) +
4387               t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4388                                     cim_upintr_info);
4389         if (fat)
4390                 t4_fatal_err(adapter);
4391 }
4392
4393 /*
4394  * ULP RX interrupt handler.
4395  */
4396 static void ulprx_intr_handler(struct adapter *adapter)
4397 {
4398         static const struct intr_info ulprx_intr_info[] = {
4399                 { 0x1800000, "ULPRX context error", -1, 1 },
4400                 { 0x7fffff, "ULPRX parity error", -1, 1 },
4401                 { 0 }
4402         };
4403
4404         if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4405                 t4_fatal_err(adapter);
4406 }
4407
4408 /*
4409  * ULP TX interrupt handler.
4410  */
4411 static void ulptx_intr_handler(struct adapter *adapter)
4412 {
4413         static const struct intr_info ulptx_intr_info[] = {
4414                 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4415                   0 },
4416                 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4417                   0 },
4418                 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4419                   0 },
4420                 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4421                   0 },
4422                 { 0xfffffff, "ULPTX parity error", -1, 1 },
4423                 { 0 }
4424         };
4425
4426         if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4427                 t4_fatal_err(adapter);
4428 }
4429
4430 /*
4431  * PM TX interrupt handler.
4432  */
4433 static void pmtx_intr_handler(struct adapter *adapter)
4434 {
4435         static const struct intr_info pmtx_intr_info[] = {
4436                 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4437                 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4438                 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4439                 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4440                 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4441                 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4442                 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4443                   -1, 1 },
4444                 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4445                 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4446                 { 0 }
4447         };
4448
4449         if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4450                 t4_fatal_err(adapter);
4451 }
4452
4453 /*
4454  * PM RX interrupt handler.
4455  */
4456 static void pmrx_intr_handler(struct adapter *adapter)
4457 {
4458         static const struct intr_info pmrx_intr_info[] = {
4459                 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4460                 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4461                 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4462                 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4463                   -1, 1 },
4464                 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4465                 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4466                 { 0 }
4467         };
4468
4469         if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4470                 t4_fatal_err(adapter);
4471 }
4472
4473 /*
4474  * CPL switch interrupt handler.
4475  */
4476 static void cplsw_intr_handler(struct adapter *adapter)
4477 {
4478         static const struct intr_info cplsw_intr_info[] = {
4479                 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4480                 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4481                 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4482                 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4483                 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4484                 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4485                 { 0 }
4486         };
4487
4488         if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4489                 t4_fatal_err(adapter);
4490 }
4491
4492 /*
4493  * LE interrupt handler.
4494  */
4495 static void le_intr_handler(struct adapter *adap)
4496 {
4497         enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4498         static const struct intr_info le_intr_info[] = {
4499                 { LIPMISS_F, "LE LIP miss", -1, 0 },
4500                 { LIP0_F, "LE 0 LIP error", -1, 0 },
4501                 { PARITYERR_F, "LE parity error", -1, 1 },
4502                 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4503                 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4504                 { 0 }
4505         };
4506
4507         static struct intr_info t6_le_intr_info[] = {
4508                 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4509                 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4510                 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4511                 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4512                 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4513                 { 0 }
4514         };
4515
4516         if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4517                                   (chip <= CHELSIO_T5) ?
4518                                   le_intr_info : t6_le_intr_info))
4519                 t4_fatal_err(adap);
4520 }
4521
4522 /*
4523  * MPS interrupt handler.
4524  */
4525 static void mps_intr_handler(struct adapter *adapter)
4526 {
4527         static const struct intr_info mps_rx_intr_info[] = {
4528                 { 0xffffff, "MPS Rx parity error", -1, 1 },
4529                 { 0 }
4530         };
4531         static const struct intr_info mps_tx_intr_info[] = {
4532                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4533                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4534                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4535                   -1, 1 },
4536                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4537                   -1, 1 },
4538                 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4539                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4540                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4541                 { 0 }
4542         };
4543         static const struct intr_info t6_mps_tx_intr_info[] = {
4544                 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4545                 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4546                 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4547                   -1, 1 },
4548                 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4549                   -1, 1 },
4550                 /* MPS Tx Bubble is normal for T6 */
4551                 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4552                 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4553                 { 0 }
4554         };
4555         static const struct intr_info mps_trc_intr_info[] = {
4556                 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4557                 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4558                   -1, 1 },
4559                 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4560                 { 0 }
4561         };
4562         static const struct intr_info mps_stat_sram_intr_info[] = {
4563                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4564                 { 0 }
4565         };
4566         static const struct intr_info mps_stat_tx_intr_info[] = {
4567                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4568                 { 0 }
4569         };
4570         static const struct intr_info mps_stat_rx_intr_info[] = {
4571                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4572                 { 0 }
4573         };
4574         static const struct intr_info mps_cls_intr_info[] = {
4575                 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4576                 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4577                 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4578                 { 0 }
4579         };
4580
4581         int fat;
4582
4583         fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4584                                     mps_rx_intr_info) +
4585               t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4586                                     is_t6(adapter->params.chip)
4587                                     ? t6_mps_tx_intr_info
4588                                     : mps_tx_intr_info) +
4589               t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4590                                     mps_trc_intr_info) +
4591               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4592                                     mps_stat_sram_intr_info) +
4593               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4594                                     mps_stat_tx_intr_info) +
4595               t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4596                                     mps_stat_rx_intr_info) +
4597               t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4598                                     mps_cls_intr_info);
4599
4600         t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4601         t4_read_reg(adapter, MPS_INT_CAUSE_A);                    /* flush */
4602         if (fat)
4603                 t4_fatal_err(adapter);
4604 }
4605
4606 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4607                       ECC_UE_INT_CAUSE_F)
4608
4609 /*
4610  * EDC/MC interrupt handler.
4611  */
4612 static void mem_intr_handler(struct adapter *adapter, int idx)
4613 {
4614         static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4615
4616         unsigned int addr, cnt_addr, v;
4617
4618         if (idx <= MEM_EDC1) {
4619                 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4620                 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4621         } else if (idx == MEM_MC) {
4622                 if (is_t4(adapter->params.chip)) {
4623                         addr = MC_INT_CAUSE_A;
4624                         cnt_addr = MC_ECC_STATUS_A;
4625                 } else {
4626                         addr = MC_P_INT_CAUSE_A;
4627                         cnt_addr = MC_P_ECC_STATUS_A;
4628                 }
4629         } else {
4630                 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4631                 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4632         }
4633
4634         v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4635         if (v & PERR_INT_CAUSE_F)
4636                 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4637                           name[idx]);
4638         if (v & ECC_CE_INT_CAUSE_F) {
4639                 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4640
4641                 t4_edc_err_read(adapter, idx);
4642
4643                 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4644                 if (printk_ratelimit())
4645                         dev_warn(adapter->pdev_dev,
4646                                  "%u %s correctable ECC data error%s\n",
4647                                  cnt, name[idx], cnt > 1 ? "s" : "");
4648         }
4649         if (v & ECC_UE_INT_CAUSE_F)
4650                 dev_alert(adapter->pdev_dev,
4651                           "%s uncorrectable ECC data error\n", name[idx]);
4652
4653         t4_write_reg(adapter, addr, v);
4654         if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4655                 t4_fatal_err(adapter);
4656 }
4657
4658 /*
4659  * MA interrupt handler.
4660  */
4661 static void ma_intr_handler(struct adapter *adap)
4662 {
4663         u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4664
4665         if (status & MEM_PERR_INT_CAUSE_F) {
4666                 dev_alert(adap->pdev_dev,
4667                           "MA parity error, parity status %#x\n",
4668                           t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4669                 if (is_t5(adap->params.chip))
4670                         dev_alert(adap->pdev_dev,
4671                                   "MA parity error, parity status %#x\n",
4672                                   t4_read_reg(adap,
4673                                               MA_PARITY_ERROR_STATUS2_A));
4674         }
4675         if (status & MEM_WRAP_INT_CAUSE_F) {
4676                 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4677                 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4678                           "client %u to address %#x\n",
4679                           MEM_WRAP_CLIENT_NUM_G(v),
4680                           MEM_WRAP_ADDRESS_G(v) << 4);
4681         }
4682         t4_write_reg(adap, MA_INT_CAUSE_A, status);
4683         t4_fatal_err(adap);
4684 }
4685
4686 /*
4687  * SMB interrupt handler.
4688  */
4689 static void smb_intr_handler(struct adapter *adap)
4690 {
4691         static const struct intr_info smb_intr_info[] = {
4692                 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4693                 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4694                 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4695                 { 0 }
4696         };
4697
4698         if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4699                 t4_fatal_err(adap);
4700 }
4701
4702 /*
4703  * NC-SI interrupt handler.
4704  */
4705 static void ncsi_intr_handler(struct adapter *adap)
4706 {
4707         static const struct intr_info ncsi_intr_info[] = {
4708                 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4709                 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4710                 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4711                 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4712                 { 0 }
4713         };
4714
4715         if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4716                 t4_fatal_err(adap);
4717 }
4718
4719 /*
4720  * XGMAC interrupt handler.
4721  */
4722 static void xgmac_intr_handler(struct adapter *adap, int port)
4723 {
4724         u32 v, int_cause_reg;
4725
4726         if (is_t4(adap->params.chip))
4727                 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4728         else
4729                 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4730
4731         v = t4_read_reg(adap, int_cause_reg);
4732
4733         v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4734         if (!v)
4735                 return;
4736
4737         if (v & TXFIFO_PRTY_ERR_F)
4738                 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4739                           port);
4740         if (v & RXFIFO_PRTY_ERR_F)
4741                 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4742                           port);
4743         t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4744         t4_fatal_err(adap);
4745 }
4746
4747 /*
4748  * PL interrupt handler.
4749  */
4750 static void pl_intr_handler(struct adapter *adap)
4751 {
4752         static const struct intr_info pl_intr_info[] = {
4753                 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4754                 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4755                 { 0 }
4756         };
4757
4758         if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4759                 t4_fatal_err(adap);
4760 }
4761
4762 #define PF_INTR_MASK (PFSW_F)
4763 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4764                 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4765                 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
4766
4767 /**
4768  *      t4_slow_intr_handler - control path interrupt handler
4769  *      @adapter: the adapter
4770  *
4771  *      T4 interrupt handler for non-data global interrupt events, e.g., errors.
4772  *      The designation 'slow' is because it involves register reads, while
4773  *      data interrupts typically don't involve any MMIOs.
4774  */
4775 int t4_slow_intr_handler(struct adapter *adapter)
4776 {
4777         u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4778
4779         if (!(cause & GLBL_INTR_MASK))
4780                 return 0;
4781         if (cause & CIM_F)
4782                 cim_intr_handler(adapter);
4783         if (cause & MPS_F)
4784                 mps_intr_handler(adapter);
4785         if (cause & NCSI_F)
4786                 ncsi_intr_handler(adapter);
4787         if (cause & PL_F)
4788                 pl_intr_handler(adapter);
4789         if (cause & SMB_F)
4790                 smb_intr_handler(adapter);
4791         if (cause & XGMAC0_F)
4792                 xgmac_intr_handler(adapter, 0);
4793         if (cause & XGMAC1_F)
4794                 xgmac_intr_handler(adapter, 1);
4795         if (cause & XGMAC_KR0_F)
4796                 xgmac_intr_handler(adapter, 2);
4797         if (cause & XGMAC_KR1_F)
4798                 xgmac_intr_handler(adapter, 3);
4799         if (cause & PCIE_F)
4800                 pcie_intr_handler(adapter);
4801         if (cause & MC_F)
4802                 mem_intr_handler(adapter, MEM_MC);
4803         if (is_t5(adapter->params.chip) && (cause & MC1_F))
4804                 mem_intr_handler(adapter, MEM_MC1);
4805         if (cause & EDC0_F)
4806                 mem_intr_handler(adapter, MEM_EDC0);
4807         if (cause & EDC1_F)
4808                 mem_intr_handler(adapter, MEM_EDC1);
4809         if (cause & LE_F)
4810                 le_intr_handler(adapter);
4811         if (cause & TP_F)
4812                 tp_intr_handler(adapter);
4813         if (cause & MA_F)
4814                 ma_intr_handler(adapter);
4815         if (cause & PM_TX_F)
4816                 pmtx_intr_handler(adapter);
4817         if (cause & PM_RX_F)
4818                 pmrx_intr_handler(adapter);
4819         if (cause & ULP_RX_F)
4820                 ulprx_intr_handler(adapter);
4821         if (cause & CPL_SWITCH_F)
4822                 cplsw_intr_handler(adapter);
4823         if (cause & SGE_F)
4824                 sge_intr_handler(adapter);
4825         if (cause & ULP_TX_F)
4826                 ulptx_intr_handler(adapter);
4827
4828         /* Clear the interrupts just processed for which we are the master. */
4829         t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4830         (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4831         return 1;
4832 }
4833
4834 /**
4835  *      t4_intr_enable - enable interrupts
4836  *      @adapter: the adapter whose interrupts should be enabled
4837  *
4838  *      Enable PF-specific interrupts for the calling function and the top-level
4839  *      interrupt concentrator for global interrupts.  Interrupts are already
4840  *      enabled at each module, here we just enable the roots of the interrupt
4841  *      hierarchies.
4842  *
4843  *      Note: this function should be called only when the driver manages
4844  *      non PF-specific interrupts from the various HW modules.  Only one PCI
4845  *      function at a time should be doing this.
4846  */
4847 void t4_intr_enable(struct adapter *adapter)
4848 {
4849         u32 val = 0;
4850         u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4851         u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4852                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4853
4854         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4855                 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4856         t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4857                      ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4858                      ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4859                      ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4860                      ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4861                      ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4862                      DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4863         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4864         t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4865 }
4866
4867 /**
4868  *      t4_intr_disable - disable interrupts
4869  *      @adapter: the adapter whose interrupts should be disabled
4870  *
4871  *      Disable interrupts.  We only disable the top-level interrupt
4872  *      concentrators.  The caller must be a PCI function managing global
4873  *      interrupts.
4874  */
4875 void t4_intr_disable(struct adapter *adapter)
4876 {
4877         u32 whoami, pf;
4878
4879         if (pci_channel_offline(adapter->pdev))
4880                 return;
4881
4882         whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4883         pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4884                         SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4885
4886         t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4887         t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4888 }
4889
4890 /**
4891  *      t4_config_rss_range - configure a portion of the RSS mapping table
4892  *      @adapter: the adapter
4893  *      @mbox: mbox to use for the FW command
4894  *      @viid: virtual interface whose RSS subtable is to be written
4895  *      @start: start entry in the table to write
4896  *      @n: how many table entries to write
4897  *      @rspq: values for the response queue lookup table
4898  *      @nrspq: number of values in @rspq
4899  *
4900  *      Programs the selected part of the VI's RSS mapping table with the
4901  *      provided values.  If @nrspq < @n the supplied values are used repeatedly
4902  *      until the full table range is populated.
4903  *
4904  *      The caller must ensure the values in @rspq are in the range allowed for
4905  *      @viid.
4906  */
4907 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4908                         int start, int n, const u16 *rspq, unsigned int nrspq)
4909 {
4910         int ret;
4911         const u16 *rsp = rspq;
4912         const u16 *rsp_end = rspq + nrspq;
4913         struct fw_rss_ind_tbl_cmd cmd;
4914
4915         memset(&cmd, 0, sizeof(cmd));
4916         cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4917                                FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4918                                FW_RSS_IND_TBL_CMD_VIID_V(viid));
4919         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4920
4921         /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4922         while (n > 0) {
4923                 int nq = min(n, 32);
4924                 __be32 *qp = &cmd.iq0_to_iq2;
4925
4926                 cmd.niqid = cpu_to_be16(nq);
4927                 cmd.startidx = cpu_to_be16(start);
4928
4929                 start += nq;
4930                 n -= nq;
4931
4932                 while (nq > 0) {
4933                         unsigned int v;
4934
4935                         v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4936                         if (++rsp >= rsp_end)
4937                                 rsp = rspq;
4938                         v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4939                         if (++rsp >= rsp_end)
4940                                 rsp = rspq;
4941                         v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4942                         if (++rsp >= rsp_end)
4943                                 rsp = rspq;
4944
4945                         *qp++ = cpu_to_be32(v);
4946                         nq -= 3;
4947                 }
4948
4949                 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4950                 if (ret)
4951                         return ret;
4952         }
4953         return 0;
4954 }
4955
4956 /**
4957  *      t4_config_glbl_rss - configure the global RSS mode
4958  *      @adapter: the adapter
4959  *      @mbox: mbox to use for the FW command
4960  *      @mode: global RSS mode
4961  *      @flags: mode-specific flags
4962  *
4963  *      Sets the global RSS mode.
4964  */
4965 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4966                        unsigned int flags)
4967 {
4968         struct fw_rss_glb_config_cmd c;
4969
4970         memset(&c, 0, sizeof(c));
4971         c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4972                                     FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4973         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4974         if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4975                 c.u.manual.mode_pkd =
4976                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4977         } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4978                 c.u.basicvirtual.mode_pkd =
4979                         cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4980                 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4981         } else
4982                 return -EINVAL;
4983         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4984 }
4985
4986 /**
4987  *      t4_config_vi_rss - configure per VI RSS settings
4988  *      @adapter: the adapter
4989  *      @mbox: mbox to use for the FW command
4990  *      @viid: the VI id
4991  *      @flags: RSS flags
4992  *      @defq: id of the default RSS queue for the VI.
4993  *
4994  *      Configures VI-specific RSS properties.
4995  */
4996 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4997                      unsigned int flags, unsigned int defq)
4998 {
4999         struct fw_rss_vi_config_cmd c;
5000
5001         memset(&c, 0, sizeof(c));
5002         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5003                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5004                                    FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5005         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5006         c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5007                                         FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5008         return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5009 }
5010
5011 /* Read an RSS table row */
5012 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5013 {
5014         t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5015         return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5016                                    5, 0, val);
5017 }
5018
5019 /**
5020  *      t4_read_rss - read the contents of the RSS mapping table
5021  *      @adapter: the adapter
5022  *      @map: holds the contents of the RSS mapping table
5023  *
5024  *      Reads the contents of the RSS hash->queue mapping table.
5025  */
5026 int t4_read_rss(struct adapter *adapter, u16 *map)
5027 {
5028         u32 val;
5029         int i, ret;
5030
5031         for (i = 0; i < RSS_NENTRIES / 2; ++i) {
5032                 ret = rd_rss_row(adapter, i, &val);
5033                 if (ret)
5034                         return ret;
5035                 *map++ = LKPTBLQUEUE0_G(val);
5036                 *map++ = LKPTBLQUEUE1_G(val);
5037         }
5038         return 0;
5039 }
5040
5041 static unsigned int t4_use_ldst(struct adapter *adap)
5042 {
5043         return (adap->flags & FW_OK) || !adap->use_bd;
5044 }
5045
5046 /**
5047  *      t4_fw_tp_pio_rw - Access TP PIO through LDST
5048  *      @adap: the adapter
5049  *      @vals: where the indirect register values are stored/written
5050  *      @nregs: how many indirect registers to read/write
5051  *      @start_idx: index of first indirect register to read/write
5052  *      @rw: Read (1) or Write (0)
5053  *
5054  *      Access TP PIO registers through LDST
5055  */
5056 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
5057                             unsigned int start_index, unsigned int rw)
5058 {
5059         int ret, i;
5060         int cmd = FW_LDST_ADDRSPC_TP_PIO;
5061         struct fw_ldst_cmd c;
5062
5063         for (i = 0 ; i < nregs; i++) {
5064                 memset(&c, 0, sizeof(c));
5065                 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5066                                                 FW_CMD_REQUEST_F |
5067                                                 (rw ? FW_CMD_READ_F :
5068                                                       FW_CMD_WRITE_F) |
5069                                                 FW_LDST_CMD_ADDRSPACE_V(cmd));
5070                 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5071
5072                 c.u.addrval.addr = cpu_to_be32(start_index + i);
5073                 c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
5074                 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
5075                 if (!ret && rw)
5076                         vals[i] = be32_to_cpu(c.u.addrval.val);
5077         }
5078 }
5079
5080 /**
5081  *      t4_read_rss_key - read the global RSS key
5082  *      @adap: the adapter
5083  *      @key: 10-entry array holding the 320-bit RSS key
5084  *
5085  *      Reads the global 320-bit RSS key.
5086  */
5087 void t4_read_rss_key(struct adapter *adap, u32 *key)
5088 {
5089         if (t4_use_ldst(adap))
5090                 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
5091         else
5092                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
5093                                  TP_RSS_SECRET_KEY0_A);
5094 }
5095
5096 /**
5097  *      t4_write_rss_key - program one of the RSS keys
5098  *      @adap: the adapter
5099  *      @key: 10-entry array holding the 320-bit RSS key
5100  *      @idx: which RSS key to write
5101  *
5102  *      Writes one of the RSS keys with the given 320-bit value.  If @idx is
5103  *      0..15 the corresponding entry in the RSS key table is written,
5104  *      otherwise the global RSS key is written.
5105  */
5106 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
5107 {
5108         u8 rss_key_addr_cnt = 16;
5109         u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5110
5111         /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5112          * allows access to key addresses 16-63 by using KeyWrAddrX
5113          * as index[5:4](upper 2) into key table
5114          */
5115         if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5116             (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5117                 rss_key_addr_cnt = 32;
5118
5119         if (t4_use_ldst(adap))
5120                 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
5121         else
5122                 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
5123                                   TP_RSS_SECRET_KEY0_A);
5124
5125         if (idx >= 0 && idx < rss_key_addr_cnt) {
5126                 if (rss_key_addr_cnt > 16)
5127                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5128                                      KEYWRADDRX_V(idx >> 4) |
5129                                      T6_VFWRADDR_V(idx) | KEYWREN_F);
5130                 else
5131                         t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5132                                      KEYWRADDR_V(idx) | KEYWREN_F);
5133         }
5134 }
5135
5136 /**
5137  *      t4_read_rss_pf_config - read PF RSS Configuration Table
5138  *      @adapter: the adapter
5139  *      @index: the entry in the PF RSS table to read
5140  *      @valp: where to store the returned value
5141  *
5142  *      Reads the PF RSS Configuration Table at the specified index and returns
5143  *      the value found there.
5144  */
5145 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5146                            u32 *valp)
5147 {
5148         if (t4_use_ldst(adapter))
5149                 t4_fw_tp_pio_rw(adapter, valp, 1,
5150                                 TP_RSS_PF0_CONFIG_A + index, 1);
5151         else
5152                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5153                                  valp, 1, TP_RSS_PF0_CONFIG_A + index);
5154 }
5155
5156 /**
5157  *      t4_read_rss_vf_config - read VF RSS Configuration Table
5158  *      @adapter: the adapter
5159  *      @index: the entry in the VF RSS table to read
5160  *      @vfl: where to store the returned VFL
5161  *      @vfh: where to store the returned VFH
5162  *
5163  *      Reads the VF RSS Configuration Table at the specified index and returns
5164  *      the (VFL, VFH) values found there.
5165  */
5166 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5167                            u32 *vfl, u32 *vfh)
5168 {
5169         u32 vrt, mask, data;
5170
5171         if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5172                 mask = VFWRADDR_V(VFWRADDR_M);
5173                 data = VFWRADDR_V(index);
5174         } else {
5175                  mask =  T6_VFWRADDR_V(T6_VFWRADDR_M);
5176                  data = T6_VFWRADDR_V(index);
5177         }
5178
5179         /* Request that the index'th VF Table values be read into VFL/VFH.
5180          */
5181         vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5182         vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5183         vrt |= data | VFRDEN_F;
5184         t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5185
5186         /* Grab the VFL/VFH values ...
5187          */
5188         if (t4_use_ldst(adapter)) {
5189                 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
5190                 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
5191         } else {
5192                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5193                                  vfl, 1, TP_RSS_VFL_CONFIG_A);
5194                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5195                                  vfh, 1, TP_RSS_VFH_CONFIG_A);
5196         }
5197 }
5198
5199 /**
5200  *      t4_read_rss_pf_map - read PF RSS Map
5201  *      @adapter: the adapter
5202  *
5203  *      Reads the PF RSS Map register and returns its value.
5204  */
5205 u32 t4_read_rss_pf_map(struct adapter *adapter)
5206 {
5207         u32 pfmap;
5208
5209         if (t4_use_ldst(adapter))
5210                 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
5211         else
5212                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5213                                  &pfmap, 1, TP_RSS_PF_MAP_A);
5214         return pfmap;
5215 }
5216
5217 /**
5218  *      t4_read_rss_pf_mask - read PF RSS Mask
5219  *      @adapter: the adapter
5220  *
5221  *      Reads the PF RSS Mask register and returns its value.
5222  */
5223 u32 t4_read_rss_pf_mask(struct adapter *adapter)
5224 {
5225         u32 pfmask;
5226
5227         if (t4_use_ldst(adapter))
5228                 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
5229         else
5230                 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5231                                  &pfmask, 1, TP_RSS_PF_MSK_A);
5232         return pfmask;
5233 }
5234
5235 /**
5236  *      t4_tp_get_tcp_stats - read TP's TCP MIB counters
5237  *      @adap: the adapter
5238  *      @v4: holds the TCP/IP counter values
5239  *      @v6: holds the TCP/IPv6 counter values
5240  *
5241  *      Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5242  *      Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5243  */
5244 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5245                          struct tp_tcp_stats *v6)
5246 {
5247         u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5248
5249 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5250 #define STAT(x)     val[STAT_IDX(x)]
5251 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5252
5253         if (v4) {
5254                 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5255                                  ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
5256                 v4->tcp_out_rsts = STAT(OUT_RST);
5257                 v4->tcp_in_segs  = STAT64(IN_SEG);
5258                 v4->tcp_out_segs = STAT64(OUT_SEG);
5259                 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5260         }
5261         if (v6) {
5262                 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5263                                  ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
5264                 v6->tcp_out_rsts = STAT(OUT_RST);
5265                 v6->tcp_in_segs  = STAT64(IN_SEG);
5266                 v6->tcp_out_segs = STAT64(OUT_SEG);
5267                 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5268         }
5269 #undef STAT64
5270 #undef STAT
5271 #undef STAT_IDX
5272 }
5273
5274 /**
5275  *      t4_tp_get_err_stats - read TP's error MIB counters
5276  *      @adap: the adapter
5277  *      @st: holds the counter values
5278  *
5279  *      Returns the values of TP's error counters.
5280  */
5281 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
5282 {
5283         int nchan = adap->params.arch.nchan;
5284
5285         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5286                          st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
5287         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5288                          st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
5289         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5290                          st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
5291         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5292                          st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
5293         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5294                          st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
5295         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5296                          st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
5297         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5298                          st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
5299         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5300                          st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
5301
5302         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
5303                          &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
5304 }
5305
5306 /**
5307  *      t4_tp_get_cpl_stats - read TP's CPL MIB counters
5308  *      @adap: the adapter
5309  *      @st: holds the counter values
5310  *
5311  *      Returns the values of TP's CPL counters.
5312  */
5313 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
5314 {
5315         int nchan = adap->params.arch.nchan;
5316
5317         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
5318                          nchan, TP_MIB_CPL_IN_REQ_0_A);
5319         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
5320                          nchan, TP_MIB_CPL_OUT_RSP_0_A);
5321
5322 }
5323
5324 /**
5325  *      t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5326  *      @adap: the adapter
5327  *      @st: holds the counter values
5328  *
5329  *      Returns the values of TP's RDMA counters.
5330  */
5331 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
5332 {
5333         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
5334                          2, TP_MIB_RQE_DFR_PKT_A);
5335 }
5336
5337 /**
5338  *      t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5339  *      @adap: the adapter
5340  *      @idx: the port index
5341  *      @st: holds the counter values
5342  *
5343  *      Returns the values of TP's FCoE counters for the selected port.
5344  */
5345 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5346                        struct tp_fcoe_stats *st)
5347 {
5348         u32 val[2];
5349
5350         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
5351                          1, TP_MIB_FCOE_DDP_0_A + idx);
5352         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
5353                          1, TP_MIB_FCOE_DROP_0_A + idx);
5354         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
5355                          2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
5356         st->octets_ddp = ((u64)val[0] << 32) | val[1];
5357 }
5358
5359 /**
5360  *      t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5361  *      @adap: the adapter
5362  *      @st: holds the counter values
5363  *
5364  *      Returns the values of TP's counters for non-TCP directly-placed packets.
5365  */
5366 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
5367 {
5368         u32 val[4];
5369
5370         t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
5371                          TP_MIB_USM_PKTS_A);
5372         st->frames = val[0];
5373         st->drops = val[1];
5374         st->octets = ((u64)val[2] << 32) | val[3];
5375 }
5376
5377 /**
5378  *      t4_read_mtu_tbl - returns the values in the HW path MTU table
5379  *      @adap: the adapter
5380  *      @mtus: where to store the MTU values
5381  *      @mtu_log: where to store the MTU base-2 log (may be %NULL)
5382  *
5383  *      Reads the HW path MTU table.
5384  */
5385 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5386 {
5387         u32 v;
5388         int i;
5389
5390         for (i = 0; i < NMTUS; ++i) {
5391                 t4_write_reg(adap, TP_MTU_TABLE_A,
5392                              MTUINDEX_V(0xff) | MTUVALUE_V(i));
5393                 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5394                 mtus[i] = MTUVALUE_G(v);
5395                 if (mtu_log)
5396                         mtu_log[i] = MTUWIDTH_G(v);
5397         }
5398 }
5399
5400 /**
5401  *      t4_read_cong_tbl - reads the congestion control table
5402  *      @adap: the adapter
5403  *      @incr: where to store the alpha values
5404  *
5405  *      Reads the additive increments programmed into the HW congestion
5406  *      control table.
5407  */
5408 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5409 {
5410         unsigned int mtu, w;
5411
5412         for (mtu = 0; mtu < NMTUS; ++mtu)
5413                 for (w = 0; w < NCCTRL_WIN; ++w) {
5414                         t4_write_reg(adap, TP_CCTRL_TABLE_A,
5415                                      ROWINDEX_V(0xffff) | (mtu << 5) | w);
5416                         incr[mtu][w] = (u16)t4_read_reg(adap,
5417                                                 TP_CCTRL_TABLE_A) & 0x1fff;
5418                 }
5419 }
5420
5421 /**
5422  *      t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5423  *      @adap: the adapter
5424  *      @addr: the indirect TP register address
5425  *      @mask: specifies the field within the register to modify
5426  *      @val: new value for the field
5427  *
5428  *      Sets a field of an indirect TP register to the given value.
5429  */
5430 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5431                             unsigned int mask, unsigned int val)
5432 {
5433         t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5434         val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5435         t4_write_reg(adap, TP_PIO_DATA_A, val);
5436 }
5437
5438 /**
5439  *      init_cong_ctrl - initialize congestion control parameters
5440  *      @a: the alpha values for congestion control
5441  *      @b: the beta values for congestion control
5442  *
5443  *      Initialize the congestion control parameters.
5444  */
5445 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5446 {
5447         a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5448         a[9] = 2;
5449         a[10] = 3;
5450         a[11] = 4;
5451         a[12] = 5;
5452         a[13] = 6;
5453         a[14] = 7;
5454         a[15] = 8;
5455         a[16] = 9;
5456         a[17] = 10;
5457         a[18] = 14;
5458         a[19] = 17;
5459         a[20] = 21;
5460         a[21] = 25;
5461         a[22] = 30;
5462         a[23] = 35;
5463         a[24] = 45;
5464         a[25] = 60;
5465         a[26] = 80;
5466         a[27] = 100;
5467         a[28] = 200;
5468         a[29] = 300;
5469         a[30] = 400;
5470         a[31] = 500;
5471
5472         b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5473         b[9] = b[10] = 1;
5474         b[11] = b[12] = 2;
5475         b[13] = b[14] = b[15] = b[16] = 3;
5476         b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5477         b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5478         b[28] = b[29] = 6;
5479         b[30] = b[31] = 7;
5480 }
5481
5482 /* The minimum additive increment value for the congestion control table */
5483 #define CC_MIN_INCR 2U
5484
5485 /**
5486  *      t4_load_mtus - write the MTU and congestion control HW tables
5487  *      @adap: the adapter
5488  *      @mtus: the values for the MTU table
5489  *      @alpha: the values for the congestion control alpha parameter
5490  *      @beta: the values for the congestion control beta parameter
5491  *
5492  *      Write the HW MTU table with the supplied MTUs and the high-speed
5493  *      congestion control table with the supplied alpha, beta, and MTUs.
5494  *      We write the two tables together because the additive increments
5495  *      depend on the MTUs.
5496  */
5497 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5498                   const unsigned short *alpha, const unsigned short *beta)
5499 {
5500         static const unsigned int avg_pkts[NCCTRL_WIN] = {
5501                 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5502                 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5503                 28672, 40960, 57344, 81920, 114688, 163840, 229376
5504         };
5505
5506         unsigned int i, w;
5507
5508         for (i = 0; i < NMTUS; ++i) {
5509                 unsigned int mtu = mtus[i];
5510                 unsigned int log2 = fls(mtu);
5511
5512                 if (!(mtu & ((1 << log2) >> 2)))     /* round */
5513                         log2--;
5514                 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5515                              MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5516
5517                 for (w = 0; w < NCCTRL_WIN; ++w) {
5518                         unsigned int inc;
5519
5520                         inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5521                                   CC_MIN_INCR);
5522
5523                         t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5524                                      (w << 16) | (beta[w] << 13) | inc);
5525                 }
5526         }
5527 }
5528
5529 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5530  * clocks.  The formula is
5531  *
5532  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5533  *
5534  * which is equivalent to
5535  *
5536  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5537  */
5538 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5539 {
5540         u64 v = bytes256 * adap->params.vpd.cclk;
5541
5542         return v * 62 + v / 2;
5543 }
5544
5545 /**
5546  *      t4_get_chan_txrate - get the current per channel Tx rates
5547  *      @adap: the adapter
5548  *      @nic_rate: rates for NIC traffic
5549  *      @ofld_rate: rates for offloaded traffic
5550  *
5551  *      Return the current Tx rates in bytes/s for NIC and offloaded traffic
5552  *      for each channel.
5553  */
5554 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5555 {
5556         u32 v;
5557
5558         v = t4_read_reg(adap, TP_TX_TRATE_A);
5559         nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5560         nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5561         if (adap->params.arch.nchan == NCHAN) {
5562                 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5563                 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5564         }
5565
5566         v = t4_read_reg(adap, TP_TX_ORATE_A);
5567         ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5568         ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5569         if (adap->params.arch.nchan == NCHAN) {
5570                 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5571                 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5572         }
5573 }
5574
5575 /**
5576  *      t4_set_trace_filter - configure one of the tracing filters
5577  *      @adap: the adapter
5578  *      @tp: the desired trace filter parameters
5579  *      @idx: which filter to configure
5580  *      @enable: whether to enable or disable the filter
5581  *
5582  *      Configures one of the tracing filters available in HW.  If @enable is
5583  *      %0 @tp is not examined and may be %NULL. The user is responsible to
5584  *      set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5585  */
5586 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5587                         int idx, int enable)
5588 {
5589         int i, ofst = idx * 4;
5590         u32 data_reg, mask_reg, cfg;
5591         u32 multitrc = TRCMULTIFILTER_F;
5592
5593         if (!enable) {
5594                 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5595                 return 0;
5596         }
5597
5598         cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5599         if (cfg & TRCMULTIFILTER_F) {
5600                 /* If multiple tracers are enabled, then maximum
5601                  * capture size is 2.5KB (FIFO size of a single channel)
5602                  * minus 2 flits for CPL_TRACE_PKT header.
5603                  */
5604                 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5605                         return -EINVAL;
5606         } else {
5607                 /* If multiple tracers are disabled, to avoid deadlocks
5608                  * maximum packet capture size of 9600 bytes is recommended.
5609                  * Also in this mode, only trace0 can be enabled and running.
5610                  */
5611                 multitrc = 0;
5612                 if (tp->snap_len > 9600 || idx)
5613                         return -EINVAL;
5614         }
5615
5616         if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5617             tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5618             tp->min_len > TFMINPKTSIZE_M)
5619                 return -EINVAL;
5620
5621         /* stop the tracer we'll be changing */
5622         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5623
5624         idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5625         data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5626         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5627
5628         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5629                 t4_write_reg(adap, data_reg, tp->data[i]);
5630                 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5631         }
5632         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5633                      TFCAPTUREMAX_V(tp->snap_len) |
5634                      TFMINPKTSIZE_V(tp->min_len));
5635         t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5636                      TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5637                      (is_t4(adap->params.chip) ?
5638                      TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5639                      T5_TFPORT_V(tp->port) | T5_TFEN_F |
5640                      T5_TFINVERTMATCH_V(tp->invert)));
5641
5642         return 0;
5643 }
5644
5645 /**
5646  *      t4_get_trace_filter - query one of the tracing filters
5647  *      @adap: the adapter
5648  *      @tp: the current trace filter parameters
5649  *      @idx: which trace filter to query
5650  *      @enabled: non-zero if the filter is enabled
5651  *
5652  *      Returns the current settings of one of the HW tracing filters.
5653  */
5654 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5655                          int *enabled)
5656 {
5657         u32 ctla, ctlb;
5658         int i, ofst = idx * 4;
5659         u32 data_reg, mask_reg;
5660
5661         ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5662         ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5663
5664         if (is_t4(adap->params.chip)) {
5665                 *enabled = !!(ctla & TFEN_F);
5666                 tp->port =  TFPORT_G(ctla);
5667                 tp->invert = !!(ctla & TFINVERTMATCH_F);
5668         } else {
5669                 *enabled = !!(ctla & T5_TFEN_F);
5670                 tp->port = T5_TFPORT_G(ctla);
5671                 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5672         }
5673         tp->snap_len = TFCAPTUREMAX_G(ctlb);
5674         tp->min_len = TFMINPKTSIZE_G(ctlb);
5675         tp->skip_ofst = TFOFFSET_G(ctla);
5676         tp->skip_len = TFLENGTH_G(ctla);
5677
5678         ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5679         data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5680         mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5681
5682         for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5683                 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5684                 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5685         }
5686 }
5687
5688 /**
5689  *      t4_pmtx_get_stats - returns the HW stats from PMTX
5690  *      @adap: the adapter
5691  *      @cnt: where to store the count statistics
5692  *      @cycles: where to store the cycle statistics
5693  *
5694  *      Returns performance statistics from PMTX.
5695  */
5696 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5697 {
5698         int i;
5699         u32 data[2];
5700
5701         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5702                 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5703                 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5704                 if (is_t4(adap->params.chip)) {
5705                         cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5706                 } else {
5707                         t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5708                                          PM_TX_DBG_DATA_A, data, 2,
5709                                          PM_TX_DBG_STAT_MSB_A);
5710                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5711                 }
5712         }
5713 }
5714
5715 /**
5716  *      t4_pmrx_get_stats - returns the HW stats from PMRX
5717  *      @adap: the adapter
5718  *      @cnt: where to store the count statistics
5719  *      @cycles: where to store the cycle statistics
5720  *
5721  *      Returns performance statistics from PMRX.
5722  */
5723 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5724 {
5725         int i;
5726         u32 data[2];
5727
5728         for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5729                 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5730                 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5731                 if (is_t4(adap->params.chip)) {
5732                         cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5733                 } else {
5734                         t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5735                                          PM_RX_DBG_DATA_A, data, 2,
5736                                          PM_RX_DBG_STAT_MSB_A);
5737                         cycles[i] = (((u64)data[0] << 32) | data[1]);
5738                 }
5739         }
5740 }
5741
5742 /**
5743  *      compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
5744  *      @adap: the adapter
5745  *      @pidx: the port index
5746  *
5747  *      Computes and returns a bitmap indicating which MPS buffer groups are
5748  *      associated with the given Port.  Bit i is set if buffer group i is
5749  *      used by the Port.
5750  */
5751 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
5752                                               int pidx)
5753 {
5754         unsigned int chip_version, nports;
5755
5756         chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5757         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5758
5759         switch (chip_version) {
5760         case CHELSIO_T4:
5761         case CHELSIO_T5:
5762                 switch (nports) {
5763                 case 1: return 0xf;
5764                 case 2: return 3 << (2 * pidx);
5765                 case 4: return 1 << pidx;
5766                 }
5767                 break;
5768
5769         case CHELSIO_T6:
5770                 switch (nports) {
5771                 case 2: return 1 << (2 * pidx);
5772                 }
5773                 break;
5774         }
5775
5776         dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
5777                 chip_version, nports);
5778
5779         return 0;
5780 }
5781
5782 /**
5783  *      t4_get_mps_bg_map - return the buffer groups associated with a port
5784  *      @adapter: the adapter
5785  *      @pidx: the port index
5786  *
5787  *      Returns a bitmap indicating which MPS buffer groups are associated
5788  *      with the given Port.  Bit i is set if buffer group i is used by the
5789  *      Port.
5790  */
5791 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
5792 {
5793         u8 *mps_bg_map;
5794         unsigned int nports;
5795
5796         nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
5797         if (pidx >= nports) {
5798                 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
5799                         pidx, nports);
5800                 return 0;
5801         }
5802
5803         /* If we've already retrieved/computed this, just return the result.
5804          */
5805         mps_bg_map = adapter->params.mps_bg_map;
5806         if (mps_bg_map[pidx])
5807                 return mps_bg_map[pidx];
5808
5809         /* Newer Firmware can tell us what the MPS Buffer Group Map is.
5810          * If we're talking to such Firmware, let it tell us.  If the new
5811          * API isn't supported, revert back to old hardcoded way.  The value
5812          * obtained from Firmware is encoded in below format:
5813          *
5814          * val = (( MPSBGMAP[Port 3] << 24 ) |
5815          *        ( MPSBGMAP[Port 2] << 16 ) |
5816          *        ( MPSBGMAP[Port 1] <<  8 ) |
5817          *        ( MPSBGMAP[Port 0] <<  0 ))
5818          */
5819         if (adapter->flags & FW_OK) {
5820                 u32 param, val;
5821                 int ret;
5822
5823                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
5824                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
5825                 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
5826                                          0, 1, &param, &val);
5827                 if (!ret) {
5828                         int p;
5829
5830                         /* Store the BG Map for all of the Ports in order to
5831                          * avoid more calls to the Firmware in the future.
5832                          */
5833                         for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
5834                                 mps_bg_map[p] = val & 0xff;
5835
5836                         return mps_bg_map[pidx];
5837                 }
5838         }
5839
5840         /* Either we're not talking to the Firmware or we're dealing with
5841          * older Firmware which doesn't support the new API to get the MPS
5842          * Buffer Group Map.  Fall back to computing it ourselves.
5843          */
5844         mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
5845         return mps_bg_map[pidx];
5846 }
5847
5848 /**
5849  *      t4_get_tp_ch_map - return TP ingress channels associated with a port
5850  *      @adapter: the adapter
5851  *      @pidx: the port index
5852  *
5853  *      Returns a bitmap indicating which TP Ingress Channels are associated
5854  *      with a given Port.  Bit i is set if TP Ingress Channel i is used by
5855  *      the Port.
5856  */
5857 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
5858 {
5859         unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
5860         unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5861
5862         if (pidx >= nports) {
5863                 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
5864                          pidx, nports);
5865                 return 0;
5866         }
5867
5868         switch (chip_version) {
5869         case CHELSIO_T4:
5870         case CHELSIO_T5:
5871                 /* Note that this happens to be the same values as the MPS
5872                  * Buffer Group Map for these Chips.  But we replicate the code
5873                  * here because they're really separate concepts.
5874                  */
5875                 switch (nports) {
5876                 case 1: return 0xf;
5877                 case 2: return 3 << (2 * pidx);
5878                 case 4: return 1 << pidx;
5879                 }
5880                 break;
5881
5882         case CHELSIO_T6:
5883                 switch (nports) {
5884                 case 2: return 1 << pidx;
5885                 }
5886                 break;
5887         }
5888
5889         dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
5890                 chip_version, nports);
5891         return 0;
5892 }
5893
5894 /**
5895  *      t4_get_port_type_description - return Port Type string description
5896  *      @port_type: firmware Port Type enumeration
5897  */
5898 const char *t4_get_port_type_description(enum fw_port_type port_type)
5899 {
5900         static const char *const port_type_description[] = {
5901                 "Fiber_XFI",
5902                 "Fiber_XAUI",
5903                 "BT_SGMII",
5904                 "BT_XFI",
5905                 "BT_XAUI",
5906                 "KX4",
5907                 "CX4",
5908                 "KX",
5909                 "KR",
5910                 "SFP",
5911                 "BP_AP",
5912                 "BP4_AP",
5913                 "QSFP_10G",
5914                 "QSA",
5915                 "QSFP",
5916                 "BP40_BA",
5917                 "KR4_100G",
5918                 "CR4_QSFP",
5919                 "CR_QSFP",
5920                 "CR2_QSFP",
5921                 "SFP28",
5922                 "KR_SFP28",
5923         };
5924
5925         if (port_type < ARRAY_SIZE(port_type_description))
5926                 return port_type_description[port_type];
5927         return "UNKNOWN";
5928 }
5929
5930 /**
5931  *      t4_get_port_stats_offset - collect port stats relative to a previous
5932  *                                 snapshot
5933  *      @adap: The adapter
5934  *      @idx: The port
5935  *      @stats: Current stats to fill
5936  *      @offset: Previous stats snapshot
5937  */
5938 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5939                               struct port_stats *stats,
5940                               struct port_stats *offset)
5941 {
5942         u64 *s, *o;
5943         int i;
5944
5945         t4_get_port_stats(adap, idx, stats);
5946         for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5947                         i < (sizeof(struct port_stats) / sizeof(u64));
5948                         i++, s++, o++)
5949                 *s -= *o;
5950 }
5951
5952 /**
5953  *      t4_get_port_stats - collect port statistics
5954  *      @adap: the adapter
5955  *      @idx: the port index
5956  *      @p: the stats structure to fill
5957  *
5958  *      Collect statistics related to the given port from HW.
5959  */
5960 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5961 {
5962         u32 bgmap = t4_get_mps_bg_map(adap, idx);
5963         u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
5964
5965 #define GET_STAT(name) \
5966         t4_read_reg64(adap, \
5967         (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5968         T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5969 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5970
5971         p->tx_octets           = GET_STAT(TX_PORT_BYTES);
5972         p->tx_frames           = GET_STAT(TX_PORT_FRAMES);
5973         p->tx_bcast_frames     = GET_STAT(TX_PORT_BCAST);
5974         p->tx_mcast_frames     = GET_STAT(TX_PORT_MCAST);
5975         p->tx_ucast_frames     = GET_STAT(TX_PORT_UCAST);
5976         p->tx_error_frames     = GET_STAT(TX_PORT_ERROR);
5977         p->tx_frames_64        = GET_STAT(TX_PORT_64B);
5978         p->tx_frames_65_127    = GET_STAT(TX_PORT_65B_127B);
5979         p->tx_frames_128_255   = GET_STAT(TX_PORT_128B_255B);
5980         p->tx_frames_256_511   = GET_STAT(TX_PORT_256B_511B);
5981         p->tx_frames_512_1023  = GET_STAT(TX_PORT_512B_1023B);
5982         p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5983         p->tx_frames_1519_max  = GET_STAT(TX_PORT_1519B_MAX);
5984         p->tx_drop             = GET_STAT(TX_PORT_DROP);
5985         p->tx_pause            = GET_STAT(TX_PORT_PAUSE);
5986         p->tx_ppp0             = GET_STAT(TX_PORT_PPP0);
5987         p->tx_ppp1             = GET_STAT(TX_PORT_PPP1);
5988         p->tx_ppp2             = GET_STAT(TX_PORT_PPP2);
5989         p->tx_ppp3             = GET_STAT(TX_PORT_PPP3);
5990         p->tx_ppp4             = GET_STAT(TX_PORT_PPP4);
5991         p->tx_ppp5             = GET_STAT(TX_PORT_PPP5);
5992         p->tx_ppp6             = GET_STAT(TX_PORT_PPP6);
5993         p->tx_ppp7             = GET_STAT(TX_PORT_PPP7);
5994
5995         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
5996                 if (stat_ctl & COUNTPAUSESTATTX_F)
5997                         p->tx_frames_64 -= p->tx_pause;
5998                 if (stat_ctl & COUNTPAUSEMCTX_F)
5999                         p->tx_mcast_frames -= p->tx_pause;
6000         }
6001         p->rx_octets           = GET_STAT(RX_PORT_BYTES);
6002         p->rx_frames           = GET_STAT(RX_PORT_FRAMES);
6003         p->rx_bcast_frames     = GET_STAT(RX_PORT_BCAST);
6004         p->rx_mcast_frames     = GET_STAT(RX_PORT_MCAST);
6005         p->rx_ucast_frames     = GET_STAT(RX_PORT_UCAST);
6006         p->rx_too_long         = GET_STAT(RX_PORT_MTU_ERROR);
6007         p->rx_jabber           = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6008         p->rx_fcs_err          = GET_STAT(RX_PORT_CRC_ERROR);
6009         p->rx_len_err          = GET_STAT(RX_PORT_LEN_ERROR);
6010         p->rx_symbol_err       = GET_STAT(RX_PORT_SYM_ERROR);
6011         p->rx_runt             = GET_STAT(RX_PORT_LESS_64B);
6012         p->rx_frames_64        = GET_STAT(RX_PORT_64B);
6013         p->rx_frames_65_127    = GET_STAT(RX_PORT_65B_127B);
6014         p->rx_frames_128_255   = GET_STAT(RX_PORT_128B_255B);
6015         p->rx_frames_256_511   = GET_STAT(RX_PORT_256B_511B);
6016         p->rx_frames_512_1023  = GET_STAT(RX_PORT_512B_1023B);
6017         p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6018         p->rx_frames_1519_max  = GET_STAT(RX_PORT_1519B_MAX);
6019         p->rx_pause            = GET_STAT(RX_PORT_PAUSE);
6020         p->rx_ppp0             = GET_STAT(RX_PORT_PPP0);
6021         p->rx_ppp1             = GET_STAT(RX_PORT_PPP1);
6022         p->rx_ppp2             = GET_STAT(RX_PORT_PPP2);
6023         p->rx_ppp3             = GET_STAT(RX_PORT_PPP3);
6024         p->rx_ppp4             = GET_STAT(RX_PORT_PPP4);
6025         p->rx_ppp5             = GET_STAT(RX_PORT_PPP5);
6026         p->rx_ppp6             = GET_STAT(RX_PORT_PPP6);
6027         p->rx_ppp7             = GET_STAT(RX_PORT_PPP7);
6028
6029         if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6030                 if (stat_ctl & COUNTPAUSESTATRX_F)
6031                         p->rx_frames_64 -= p->rx_pause;
6032                 if (stat_ctl & COUNTPAUSEMCRX_F)
6033                         p->rx_mcast_frames -= p->rx_pause;
6034         }
6035
6036         p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6037         p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6038         p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6039         p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6040         p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6041         p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6042         p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6043         p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6044
6045 #undef GET_STAT
6046 #undef GET_STAT_COM
6047 }
6048
6049 /**
6050  *      t4_get_lb_stats - collect loopback port statistics
6051  *      @adap: the adapter
6052  *      @idx: the loopback port index
6053  *      @p: the stats structure to fill
6054  *
6055  *      Return HW statistics for the given loopback port.
6056  */
6057 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6058 {
6059         u32 bgmap = t4_get_mps_bg_map(adap, idx);
6060
6061 #define GET_STAT(name) \
6062         t4_read_reg64(adap, \
6063         (is_t4(adap->params.chip) ? \
6064         PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6065         T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6066 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6067
6068         p->octets           = GET_STAT(BYTES);
6069         p->frames           = GET_STAT(FRAMES);
6070         p->bcast_frames     = GET_STAT(BCAST);
6071         p->mcast_frames     = GET_STAT(MCAST);
6072         p->ucast_frames     = GET_STAT(UCAST);
6073         p->error_frames     = GET_STAT(ERROR);
6074
6075         p->frames_64        = GET_STAT(64B);
6076         p->frames_65_127    = GET_STAT(65B_127B);
6077         p->frames_128_255   = GET_STAT(128B_255B);
6078         p->frames_256_511   = GET_STAT(256B_511B);
6079         p->frames_512_1023  = GET_STAT(512B_1023B);
6080         p->frames_1024_1518 = GET_STAT(1024B_1518B);
6081         p->frames_1519_max  = GET_STAT(1519B_MAX);
6082         p->drop             = GET_STAT(DROP_FRAMES);
6083
6084         p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6085         p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6086         p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6087         p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6088         p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6089         p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6090         p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6091         p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6092
6093 #undef GET_STAT
6094 #undef GET_STAT_COM
6095 }
6096
6097 /*     t4_mk_filtdelwr - create a delete filter WR
6098  *     @ftid: the filter ID
6099  *     @wr: the filter work request to populate
6100  *     @qid: ingress queue to receive the delete notification
6101  *
6102  *     Creates a filter work request to delete the supplied filter.  If @qid is
6103  *     negative the delete notification is suppressed.
6104  */
6105 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6106 {
6107         memset(wr, 0, sizeof(*wr));
6108         wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6109         wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6110         wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6111                                     FW_FILTER_WR_NOREPLY_V(qid < 0));
6112         wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6113         if (qid >= 0)
6114                 wr->rx_chan_rx_rpl_iq =
6115                         cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6116 }
6117
6118 #define INIT_CMD(var, cmd, rd_wr) do { \
6119         (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6120                                         FW_CMD_REQUEST_F | \
6121                                         FW_CMD_##rd_wr##_F); \
6122         (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6123 } while (0)
6124
6125 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6126                           u32 addr, u32 val)
6127 {
6128         u32 ldst_addrspace;
6129         struct fw_ldst_cmd c;
6130
6131         memset(&c, 0, sizeof(c));
6132         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6133         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6134                                         FW_CMD_REQUEST_F |
6135                                         FW_CMD_WRITE_F |
6136                                         ldst_addrspace);
6137         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6138         c.u.addrval.addr = cpu_to_be32(addr);
6139         c.u.addrval.val = cpu_to_be32(val);
6140
6141         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6142 }
6143
6144 /**
6145  *      t4_mdio_rd - read a PHY register through MDIO
6146  *      @adap: the adapter
6147  *      @mbox: mailbox to use for the FW command
6148  *      @phy_addr: the PHY address
6149  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6150  *      @reg: the register to read
6151  *      @valp: where to store the value
6152  *
6153  *      Issues a FW command through the given mailbox to read a PHY register.
6154  */
6155 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6156                unsigned int mmd, unsigned int reg, u16 *valp)
6157 {
6158         int ret;
6159         u32 ldst_addrspace;
6160         struct fw_ldst_cmd c;
6161
6162         memset(&c, 0, sizeof(c));
6163         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6164         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6165                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6166                                         ldst_addrspace);
6167         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6168         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6169                                          FW_LDST_CMD_MMD_V(mmd));
6170         c.u.mdio.raddr = cpu_to_be16(reg);
6171
6172         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6173         if (ret == 0)
6174                 *valp = be16_to_cpu(c.u.mdio.rval);
6175         return ret;
6176 }
6177
6178 /**
6179  *      t4_mdio_wr - write a PHY register through MDIO
6180  *      @adap: the adapter
6181  *      @mbox: mailbox to use for the FW command
6182  *      @phy_addr: the PHY address
6183  *      @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6184  *      @reg: the register to write
6185  *      @valp: value to write
6186  *
6187  *      Issues a FW command through the given mailbox to write a PHY register.
6188  */
6189 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6190                unsigned int mmd, unsigned int reg, u16 val)
6191 {
6192         u32 ldst_addrspace;
6193         struct fw_ldst_cmd c;
6194
6195         memset(&c, 0, sizeof(c));
6196         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6197         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6198                                         FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6199                                         ldst_addrspace);
6200         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6201         c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6202                                          FW_LDST_CMD_MMD_V(mmd));
6203         c.u.mdio.raddr = cpu_to_be16(reg);
6204         c.u.mdio.rval = cpu_to_be16(val);
6205
6206         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6207 }
6208
6209 /**
6210  *      t4_sge_decode_idma_state - decode the idma state
6211  *      @adap: the adapter
6212  *      @state: the state idma is stuck in
6213  */
6214 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6215 {
6216         static const char * const t4_decode[] = {
6217                 "IDMA_IDLE",
6218                 "IDMA_PUSH_MORE_CPL_FIFO",
6219                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6220                 "Not used",
6221                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6222                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6223                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6224                 "IDMA_SEND_FIFO_TO_IMSG",
6225                 "IDMA_FL_REQ_DATA_FL_PREP",
6226                 "IDMA_FL_REQ_DATA_FL",
6227                 "IDMA_FL_DROP",
6228                 "IDMA_FL_H_REQ_HEADER_FL",
6229                 "IDMA_FL_H_SEND_PCIEHDR",
6230                 "IDMA_FL_H_PUSH_CPL_FIFO",
6231                 "IDMA_FL_H_SEND_CPL",
6232                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6233                 "IDMA_FL_H_SEND_IP_HDR",
6234                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6235                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6236                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6237                 "IDMA_FL_D_SEND_PCIEHDR",
6238                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6239                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6240                 "IDMA_FL_SEND_PCIEHDR",
6241                 "IDMA_FL_PUSH_CPL_FIFO",
6242                 "IDMA_FL_SEND_CPL",
6243                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6244                 "IDMA_FL_SEND_PAYLOAD",
6245                 "IDMA_FL_REQ_NEXT_DATA_FL",
6246                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6247                 "IDMA_FL_SEND_PADDING",
6248                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6249                 "IDMA_FL_SEND_FIFO_TO_IMSG",
6250                 "IDMA_FL_REQ_DATAFL_DONE",
6251                 "IDMA_FL_REQ_HEADERFL_DONE",
6252         };
6253         static const char * const t5_decode[] = {
6254                 "IDMA_IDLE",
6255                 "IDMA_ALMOST_IDLE",
6256                 "IDMA_PUSH_MORE_CPL_FIFO",
6257                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6258                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6259                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6260                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6261                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6262                 "IDMA_SEND_FIFO_TO_IMSG",
6263                 "IDMA_FL_REQ_DATA_FL",
6264                 "IDMA_FL_DROP",
6265                 "IDMA_FL_DROP_SEND_INC",
6266                 "IDMA_FL_H_REQ_HEADER_FL",
6267                 "IDMA_FL_H_SEND_PCIEHDR",
6268                 "IDMA_FL_H_PUSH_CPL_FIFO",
6269                 "IDMA_FL_H_SEND_CPL",
6270                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6271                 "IDMA_FL_H_SEND_IP_HDR",
6272                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6273                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6274                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6275                 "IDMA_FL_D_SEND_PCIEHDR",
6276                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6277                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6278                 "IDMA_FL_SEND_PCIEHDR",
6279                 "IDMA_FL_PUSH_CPL_FIFO",
6280                 "IDMA_FL_SEND_CPL",
6281                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6282                 "IDMA_FL_SEND_PAYLOAD",
6283                 "IDMA_FL_REQ_NEXT_DATA_FL",
6284                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6285                 "IDMA_FL_SEND_PADDING",
6286                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6287         };
6288         static const char * const t6_decode[] = {
6289                 "IDMA_IDLE",
6290                 "IDMA_PUSH_MORE_CPL_FIFO",
6291                 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6292                 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6293                 "IDMA_PHYSADDR_SEND_PCIEHDR",
6294                 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6295                 "IDMA_PHYSADDR_SEND_PAYLOAD",
6296                 "IDMA_FL_REQ_DATA_FL",
6297                 "IDMA_FL_DROP",
6298                 "IDMA_FL_DROP_SEND_INC",
6299                 "IDMA_FL_H_REQ_HEADER_FL",
6300                 "IDMA_FL_H_SEND_PCIEHDR",
6301                 "IDMA_FL_H_PUSH_CPL_FIFO",
6302                 "IDMA_FL_H_SEND_CPL",
6303                 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6304                 "IDMA_FL_H_SEND_IP_HDR",
6305                 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6306                 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6307                 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6308                 "IDMA_FL_D_SEND_PCIEHDR",
6309                 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6310                 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6311                 "IDMA_FL_SEND_PCIEHDR",
6312                 "IDMA_FL_PUSH_CPL_FIFO",
6313                 "IDMA_FL_SEND_CPL",
6314                 "IDMA_FL_SEND_PAYLOAD_FIRST",
6315                 "IDMA_FL_SEND_PAYLOAD",
6316                 "IDMA_FL_REQ_NEXT_DATA_FL",
6317                 "IDMA_FL_SEND_NEXT_PCIEHDR",
6318                 "IDMA_FL_SEND_PADDING",
6319                 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6320         };
6321         static const u32 sge_regs[] = {
6322                 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6323                 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6324                 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6325         };
6326         const char **sge_idma_decode;
6327         int sge_idma_decode_nstates;
6328         int i;
6329         unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6330
6331         /* Select the right set of decode strings to dump depending on the
6332          * adapter chip type.
6333          */
6334         switch (chip_version) {
6335         case CHELSIO_T4:
6336                 sge_idma_decode = (const char **)t4_decode;
6337                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6338                 break;
6339
6340         case CHELSIO_T5:
6341                 sge_idma_decode = (const char **)t5_decode;
6342                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6343                 break;
6344
6345         case CHELSIO_T6:
6346                 sge_idma_decode = (const char **)t6_decode;
6347                 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6348                 break;
6349
6350         default:
6351                 dev_err(adapter->pdev_dev,
6352                         "Unsupported chip version %d\n", chip_version);
6353                 return;
6354         }
6355
6356         if (is_t4(adapter->params.chip)) {
6357                 sge_idma_decode = (const char **)t4_decode;
6358                 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6359         } else {
6360                 sge_idma_decode = (const char **)t5_decode;
6361                 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6362         }
6363
6364         if (state < sge_idma_decode_nstates)
6365                 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6366         else
6367                 CH_WARN(adapter, "idma state %d unknown\n", state);
6368
6369         for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6370                 CH_WARN(adapter, "SGE register %#x value %#x\n",
6371                         sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6372 }
6373
6374 /**
6375  *      t4_sge_ctxt_flush - flush the SGE context cache
6376  *      @adap: the adapter
6377  *      @mbox: mailbox to use for the FW command
6378  *
6379  *      Issues a FW command through the given mailbox to flush the
6380  *      SGE context cache.
6381  */
6382 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
6383 {
6384         int ret;
6385         u32 ldst_addrspace;
6386         struct fw_ldst_cmd c;
6387
6388         memset(&c, 0, sizeof(c));
6389         ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
6390         c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6391                                         FW_CMD_REQUEST_F | FW_CMD_READ_F |
6392                                         ldst_addrspace);
6393         c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6394         c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6395
6396         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6397         return ret;
6398 }
6399
6400 /**
6401  *      t4_fw_hello - establish communication with FW
6402  *      @adap: the adapter
6403  *      @mbox: mailbox to use for the FW command
6404  *      @evt_mbox: mailbox to receive async FW events
6405  *      @master: specifies the caller's willingness to be the device master
6406  *      @state: returns the current device state (if non-NULL)
6407  *
6408  *      Issues a command to establish communication with FW.  Returns either
6409  *      an error (negative integer) or the mailbox of the Master PF.
6410  */
6411 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6412                 enum dev_master master, enum dev_state *state)
6413 {
6414         int ret;
6415         struct fw_hello_cmd c;
6416         u32 v;
6417         unsigned int master_mbox;
6418         int retries = FW_CMD_HELLO_RETRIES;
6419
6420 retry:
6421         memset(&c, 0, sizeof(c));
6422         INIT_CMD(c, HELLO, WRITE);
6423         c.err_to_clearinit = cpu_to_be32(
6424                 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6425                 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6426                 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6427                                         mbox : FW_HELLO_CMD_MBMASTER_M) |
6428                 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6429                 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6430                 FW_HELLO_CMD_CLEARINIT_F);
6431
6432         /*
6433          * Issue the HELLO command to the firmware.  If it's not successful
6434          * but indicates that we got a "busy" or "timeout" condition, retry
6435          * the HELLO until we exhaust our retry limit.  If we do exceed our
6436          * retry limit, check to see if the firmware left us any error
6437          * information and report that if so.
6438          */
6439         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6440         if (ret < 0) {
6441                 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6442                         goto retry;
6443                 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6444                         t4_report_fw_error(adap);
6445                 return ret;
6446         }
6447
6448         v = be32_to_cpu(c.err_to_clearinit);
6449         master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6450         if (state) {
6451                 if (v & FW_HELLO_CMD_ERR_F)
6452                         *state = DEV_STATE_ERR;
6453                 else if (v & FW_HELLO_CMD_INIT_F)
6454                         *state = DEV_STATE_INIT;
6455                 else
6456                         *state = DEV_STATE_UNINIT;
6457         }
6458
6459         /*
6460          * If we're not the Master PF then we need to wait around for the
6461          * Master PF Driver to finish setting up the adapter.
6462          *
6463          * Note that we also do this wait if we're a non-Master-capable PF and
6464          * there is no current Master PF; a Master PF may show up momentarily
6465          * and we wouldn't want to fail pointlessly.  (This can happen when an
6466          * OS loads lots of different drivers rapidly at the same time).  In
6467          * this case, the Master PF returned by the firmware will be
6468          * PCIE_FW_MASTER_M so the test below will work ...
6469          */
6470         if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6471             master_mbox != mbox) {
6472                 int waiting = FW_CMD_HELLO_TIMEOUT;
6473
6474                 /*
6475                  * Wait for the firmware to either indicate an error or
6476                  * initialized state.  If we see either of these we bail out
6477                  * and report the issue to the caller.  If we exhaust the
6478                  * "hello timeout" and we haven't exhausted our retries, try
6479                  * again.  Otherwise bail with a timeout error.
6480                  */
6481                 for (;;) {
6482                         u32 pcie_fw;
6483
6484                         msleep(50);
6485                         waiting -= 50;
6486
6487                         /*
6488                          * If neither Error nor Initialialized are indicated
6489                          * by the firmware keep waiting till we exaust our
6490                          * timeout ... and then retry if we haven't exhausted
6491                          * our retries ...
6492                          */
6493                         pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6494                         if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6495                                 if (waiting <= 0) {
6496                                         if (retries-- > 0)
6497                                                 goto retry;
6498
6499                                         return -ETIMEDOUT;
6500                                 }
6501                                 continue;
6502                         }
6503
6504                         /*
6505                          * We either have an Error or Initialized condition
6506                          * report errors preferentially.
6507                          */
6508                         if (state) {
6509                                 if (pcie_fw & PCIE_FW_ERR_F)
6510                                         *state = DEV_STATE_ERR;
6511                                 else if (pcie_fw & PCIE_FW_INIT_F)
6512                                         *state = DEV_STATE_INIT;
6513                         }
6514
6515                         /*
6516                          * If we arrived before a Master PF was selected and
6517                          * there's not a valid Master PF, grab its identity
6518                          * for our caller.
6519                          */
6520                         if (master_mbox == PCIE_FW_MASTER_M &&
6521                             (pcie_fw & PCIE_FW_MASTER_VLD_F))
6522                                 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6523                         break;
6524                 }
6525         }
6526
6527         return master_mbox;
6528 }
6529
6530 /**
6531  *      t4_fw_bye - end communication with FW
6532  *      @adap: the adapter
6533  *      @mbox: mailbox to use for the FW command
6534  *
6535  *      Issues a command to terminate communication with FW.
6536  */
6537 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6538 {
6539         struct fw_bye_cmd c;
6540
6541         memset(&c, 0, sizeof(c));
6542         INIT_CMD(c, BYE, WRITE);
6543         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6544 }
6545
6546 /**
6547  *      t4_init_cmd - ask FW to initialize the device
6548  *      @adap: the adapter
6549  *      @mbox: mailbox to use for the FW command
6550  *
6551  *      Issues a command to FW to partially initialize the device.  This
6552  *      performs initialization that generally doesn't depend on user input.
6553  */
6554 int t4_early_init(struct adapter *adap, unsigned int mbox)
6555 {
6556         struct fw_initialize_cmd c;
6557
6558         memset(&c, 0, sizeof(c));
6559         INIT_CMD(c, INITIALIZE, WRITE);
6560         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6561 }
6562
6563 /**
6564  *      t4_fw_reset - issue a reset to FW
6565  *      @adap: the adapter
6566  *      @mbox: mailbox to use for the FW command
6567  *      @reset: specifies the type of reset to perform
6568  *
6569  *      Issues a reset command of the specified type to FW.
6570  */
6571 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6572 {
6573         struct fw_reset_cmd c;
6574
6575         memset(&c, 0, sizeof(c));
6576         INIT_CMD(c, RESET, WRITE);
6577         c.val = cpu_to_be32(reset);
6578         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6579 }
6580
6581 /**
6582  *      t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6583  *      @adap: the adapter
6584  *      @mbox: mailbox to use for the FW RESET command (if desired)
6585  *      @force: force uP into RESET even if FW RESET command fails
6586  *
6587  *      Issues a RESET command to firmware (if desired) with a HALT indication
6588  *      and then puts the microprocessor into RESET state.  The RESET command
6589  *      will only be issued if a legitimate mailbox is provided (mbox <=
6590  *      PCIE_FW_MASTER_M).
6591  *
6592  *      This is generally used in order for the host to safely manipulate the
6593  *      adapter without fear of conflicting with whatever the firmware might
6594  *      be doing.  The only way out of this state is to RESTART the firmware
6595  *      ...
6596  */
6597 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6598 {
6599         int ret = 0;
6600
6601         /*
6602          * If a legitimate mailbox is provided, issue a RESET command
6603          * with a HALT indication.
6604          */
6605         if (mbox <= PCIE_FW_MASTER_M) {
6606                 struct fw_reset_cmd c;
6607
6608                 memset(&c, 0, sizeof(c));
6609                 INIT_CMD(c, RESET, WRITE);
6610                 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6611                 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6612                 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6613         }
6614
6615         /*
6616          * Normally we won't complete the operation if the firmware RESET
6617          * command fails but if our caller insists we'll go ahead and put the
6618          * uP into RESET.  This can be useful if the firmware is hung or even
6619          * missing ...  We'll have to take the risk of putting the uP into
6620          * RESET without the cooperation of firmware in that case.
6621          *
6622          * We also force the firmware's HALT flag to be on in case we bypassed
6623          * the firmware RESET command above or we're dealing with old firmware
6624          * which doesn't have the HALT capability.  This will serve as a flag
6625          * for the incoming firmware to know that it's coming out of a HALT
6626          * rather than a RESET ... if it's new enough to understand that ...
6627          */
6628         if (ret == 0 || force) {
6629                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6630                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6631                                  PCIE_FW_HALT_F);
6632         }
6633
6634         /*
6635          * And we always return the result of the firmware RESET command
6636          * even when we force the uP into RESET ...
6637          */
6638         return ret;
6639 }
6640
6641 /**
6642  *      t4_fw_restart - restart the firmware by taking the uP out of RESET
6643  *      @adap: the adapter
6644  *      @reset: if we want to do a RESET to restart things
6645  *
6646  *      Restart firmware previously halted by t4_fw_halt().  On successful
6647  *      return the previous PF Master remains as the new PF Master and there
6648  *      is no need to issue a new HELLO command, etc.
6649  *
6650  *      We do this in two ways:
6651  *
6652  *       1. If we're dealing with newer firmware we'll simply want to take
6653  *          the chip's microprocessor out of RESET.  This will cause the
6654  *          firmware to start up from its start vector.  And then we'll loop
6655  *          until the firmware indicates it's started again (PCIE_FW.HALT
6656  *          reset to 0) or we timeout.
6657  *
6658  *       2. If we're dealing with older firmware then we'll need to RESET
6659  *          the chip since older firmware won't recognize the PCIE_FW.HALT
6660  *          flag and automatically RESET itself on startup.
6661  */
6662 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6663 {
6664         if (reset) {
6665                 /*
6666                  * Since we're directing the RESET instead of the firmware
6667                  * doing it automatically, we need to clear the PCIE_FW.HALT
6668                  * bit.
6669                  */
6670                 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6671
6672                 /*
6673                  * If we've been given a valid mailbox, first try to get the
6674                  * firmware to do the RESET.  If that works, great and we can
6675                  * return success.  Otherwise, if we haven't been given a
6676                  * valid mailbox or the RESET command failed, fall back to
6677                  * hitting the chip with a hammer.
6678                  */
6679                 if (mbox <= PCIE_FW_MASTER_M) {
6680                         t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6681                         msleep(100);
6682                         if (t4_fw_reset(adap, mbox,
6683                                         PIORST_F | PIORSTMODE_F) == 0)
6684                                 return 0;
6685                 }
6686
6687                 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6688                 msleep(2000);
6689         } else {
6690                 int ms;
6691
6692                 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6693                 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6694                         if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6695                                 return 0;
6696                         msleep(100);
6697                         ms += 100;
6698                 }
6699                 return -ETIMEDOUT;
6700         }
6701         return 0;
6702 }
6703
6704 /**
6705  *      t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6706  *      @adap: the adapter
6707  *      @mbox: mailbox to use for the FW RESET command (if desired)
6708  *      @fw_data: the firmware image to write
6709  *      @size: image size
6710  *      @force: force upgrade even if firmware doesn't cooperate
6711  *
6712  *      Perform all of the steps necessary for upgrading an adapter's
6713  *      firmware image.  Normally this requires the cooperation of the
6714  *      existing firmware in order to halt all existing activities
6715  *      but if an invalid mailbox token is passed in we skip that step
6716  *      (though we'll still put the adapter microprocessor into RESET in
6717  *      that case).
6718  *
6719  *      On successful return the new firmware will have been loaded and
6720  *      the adapter will have been fully RESET losing all previous setup
6721  *      state.  On unsuccessful return the adapter may be completely hosed ...
6722  *      positive errno indicates that the adapter is ~probably~ intact, a
6723  *      negative errno indicates that things are looking bad ...
6724  */
6725 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6726                   const u8 *fw_data, unsigned int size, int force)
6727 {
6728         const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6729         int reset, ret;
6730
6731         if (!t4_fw_matches_chip(adap, fw_hdr))
6732                 return -EINVAL;
6733
6734         /* Disable FW_OK flag so that mbox commands with FW_OK flag set
6735          * wont be sent when we are flashing FW.
6736          */
6737         adap->flags &= ~FW_OK;
6738
6739         ret = t4_fw_halt(adap, mbox, force);
6740         if (ret < 0 && !force)
6741                 goto out;
6742
6743         ret = t4_load_fw(adap, fw_data, size);
6744         if (ret < 0)
6745                 goto out;
6746
6747         /*
6748          * If there was a Firmware Configuration File stored in FLASH,
6749          * there's a good chance that it won't be compatible with the new
6750          * Firmware.  In order to prevent difficult to diagnose adapter
6751          * initialization issues, we clear out the Firmware Configuration File
6752          * portion of the FLASH .  The user will need to re-FLASH a new
6753          * Firmware Configuration File which is compatible with the new
6754          * Firmware if that's desired.
6755          */
6756         (void)t4_load_cfg(adap, NULL, 0);
6757
6758         /*
6759          * Older versions of the firmware don't understand the new
6760          * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6761          * restart.  So for newly loaded older firmware we'll have to do the
6762          * RESET for it so it starts up on a clean slate.  We can tell if
6763          * the newly loaded firmware will handle this right by checking
6764          * its header flags to see if it advertises the capability.
6765          */
6766         reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6767         ret = t4_fw_restart(adap, mbox, reset);
6768
6769         /* Grab potentially new Firmware Device Log parameters so we can see
6770          * how healthy the new Firmware is.  It's okay to contact the new
6771          * Firmware for these parameters even though, as far as it's
6772          * concerned, we've never said "HELLO" to it ...
6773          */
6774         (void)t4_init_devlog_params(adap);
6775 out:
6776         adap->flags |= FW_OK;
6777         return ret;
6778 }
6779
6780 /**
6781  *      t4_fl_pkt_align - return the fl packet alignment
6782  *      @adap: the adapter
6783  *
6784  *      T4 has a single field to specify the packing and padding boundary.
6785  *      T5 onwards has separate fields for this and hence the alignment for
6786  *      next packet offset is maximum of these two.
6787  *
6788  */
6789 int t4_fl_pkt_align(struct adapter *adap)
6790 {
6791         u32 sge_control, sge_control2;
6792         unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6793
6794         sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6795
6796         /* T4 uses a single control field to specify both the PCIe Padding and
6797          * Packing Boundary.  T5 introduced the ability to specify these
6798          * separately.  The actual Ingress Packet Data alignment boundary
6799          * within Packed Buffer Mode is the maximum of these two
6800          * specifications.  (Note that it makes no real practical sense to
6801          * have the Pading Boudary be larger than the Packing Boundary but you
6802          * could set the chip up that way and, in fact, legacy T4 code would
6803          * end doing this because it would initialize the Padding Boundary and
6804          * leave the Packing Boundary initialized to 0 (16 bytes).)
6805          * Padding Boundary values in T6 starts from 8B,
6806          * where as it is 32B for T4 and T5.
6807          */
6808         if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6809                 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6810         else
6811                 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6812
6813         ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6814
6815         fl_align = ingpadboundary;
6816         if (!is_t4(adap->params.chip)) {
6817                 /* T5 has a weird interpretation of one of the PCIe Packing
6818                  * Boundary values.  No idea why ...
6819                  */
6820                 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6821                 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6822                 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6823                         ingpackboundary = 16;
6824                 else
6825                         ingpackboundary = 1 << (ingpackboundary +
6826                                                 INGPACKBOUNDARY_SHIFT_X);
6827
6828                 fl_align = max(ingpadboundary, ingpackboundary);
6829         }
6830         return fl_align;
6831 }
6832
6833 /**
6834  *      t4_fixup_host_params - fix up host-dependent parameters
6835  *      @adap: the adapter
6836  *      @page_size: the host's Base Page Size
6837  *      @cache_line_size: the host's Cache Line Size
6838  *
6839  *      Various registers in T4 contain values which are dependent on the
6840  *      host's Base Page and Cache Line Sizes.  This function will fix all of
6841  *      those registers with the appropriate values as passed in ...
6842  */
6843 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6844                          unsigned int cache_line_size)
6845 {
6846         unsigned int page_shift = fls(page_size) - 1;
6847         unsigned int sge_hps = page_shift - 10;
6848         unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6849         unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6850         unsigned int fl_align_log = fls(fl_align) - 1;
6851
6852         t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6853                      HOSTPAGESIZEPF0_V(sge_hps) |
6854                      HOSTPAGESIZEPF1_V(sge_hps) |
6855                      HOSTPAGESIZEPF2_V(sge_hps) |
6856                      HOSTPAGESIZEPF3_V(sge_hps) |
6857                      HOSTPAGESIZEPF4_V(sge_hps) |
6858                      HOSTPAGESIZEPF5_V(sge_hps) |
6859                      HOSTPAGESIZEPF6_V(sge_hps) |
6860                      HOSTPAGESIZEPF7_V(sge_hps));
6861
6862         if (is_t4(adap->params.chip)) {
6863                 t4_set_reg_field(adap, SGE_CONTROL_A,
6864                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6865                                  EGRSTATUSPAGESIZE_F,
6866                                  INGPADBOUNDARY_V(fl_align_log -
6867                                                   INGPADBOUNDARY_SHIFT_X) |
6868                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
6869         } else {
6870                 unsigned int pack_align;
6871                 unsigned int ingpad, ingpack;
6872                 unsigned int pcie_cap;
6873
6874                 /* T5 introduced the separation of the Free List Padding and
6875                  * Packing Boundaries.  Thus, we can select a smaller Padding
6876                  * Boundary to avoid uselessly chewing up PCIe Link and Memory
6877                  * Bandwidth, and use a Packing Boundary which is large enough
6878                  * to avoid false sharing between CPUs, etc.
6879                  *
6880                  * For the PCI Link, the smaller the Padding Boundary the
6881                  * better.  For the Memory Controller, a smaller Padding
6882                  * Boundary is better until we cross under the Memory Line
6883                  * Size (the minimum unit of transfer to/from Memory).  If we
6884                  * have a Padding Boundary which is smaller than the Memory
6885                  * Line Size, that'll involve a Read-Modify-Write cycle on the
6886                  * Memory Controller which is never good.
6887                  */
6888
6889                 /* We want the Packing Boundary to be based on the Cache Line
6890                  * Size in order to help avoid False Sharing performance
6891                  * issues between CPUs, etc.  We also want the Packing
6892                  * Boundary to incorporate the PCI-E Maximum Payload Size.  We
6893                  * get best performance when the Packing Boundary is a
6894                  * multiple of the Maximum Payload Size.
6895                  */
6896                 pack_align = fl_align;
6897                 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP);
6898                 if (pcie_cap) {
6899                         unsigned int mps, mps_log;
6900                         u16 devctl;
6901
6902                         /* The PCIe Device Control Maximum Payload Size field
6903                          * [bits 7:5] encodes sizes as powers of 2 starting at
6904                          * 128 bytes.
6905                          */
6906                         pci_read_config_word(adap->pdev,
6907                                              pcie_cap + PCI_EXP_DEVCTL,
6908                                              &devctl);
6909                         mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
6910                         mps = 1 << mps_log;
6911                         if (mps > pack_align)
6912                                 pack_align = mps;
6913                 }
6914
6915                 /* N.B. T5/T6 have a crazy special interpretation of the "0"
6916                  * value for the Packing Boundary.  This corresponds to 16
6917                  * bytes instead of the expected 32 bytes.  So if we want 32
6918                  * bytes, the best we can really do is 64 bytes ...
6919                  */
6920                 if (pack_align <= 16) {
6921                         ingpack = INGPACKBOUNDARY_16B_X;
6922                         fl_align = 16;
6923                 } else if (pack_align == 32) {
6924                         ingpack = INGPACKBOUNDARY_64B_X;
6925                         fl_align = 64;
6926                 } else {
6927                         unsigned int pack_align_log = fls(pack_align) - 1;
6928
6929                         ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
6930                         fl_align = pack_align;
6931                 }
6932
6933                 /* Use the smallest Ingress Padding which isn't smaller than
6934                  * the Memory Controller Read/Write Size.  We'll take that as
6935                  * being 8 bytes since we don't know of any system with a
6936                  * wider Memory Controller Bus Width.
6937                  */
6938                 if (is_t5(adap->params.chip))
6939                         ingpad = INGPADBOUNDARY_32B_X;
6940                 else
6941                         ingpad = T6_INGPADBOUNDARY_8B_X;
6942
6943                 t4_set_reg_field(adap, SGE_CONTROL_A,
6944                                  INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6945                                  EGRSTATUSPAGESIZE_F,
6946                                  INGPADBOUNDARY_V(ingpad) |
6947                                  EGRSTATUSPAGESIZE_V(stat_len != 64));
6948                 t4_set_reg_field(adap, SGE_CONTROL2_A,
6949                                  INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6950                                  INGPACKBOUNDARY_V(ingpack));
6951         }
6952         /*
6953          * Adjust various SGE Free List Host Buffer Sizes.
6954          *
6955          * This is something of a crock since we're using fixed indices into
6956          * the array which are also known by the sge.c code and the T4
6957          * Firmware Configuration File.  We need to come up with a much better
6958          * approach to managing this array.  For now, the first four entries
6959          * are:
6960          *
6961          *   0: Host Page Size
6962          *   1: 64KB
6963          *   2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6964          *   3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6965          *
6966          * For the single-MTU buffers in unpacked mode we need to include
6967          * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6968          * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6969          * Padding boundary.  All of these are accommodated in the Factory
6970          * Default Firmware Configuration File but we need to adjust it for
6971          * this host's cache line size.
6972          */
6973         t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6974         t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6975                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6976                      & ~(fl_align-1));
6977         t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6978                      (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6979                      & ~(fl_align-1));
6980
6981         t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6982
6983         return 0;
6984 }
6985
6986 /**
6987  *      t4_fw_initialize - ask FW to initialize the device
6988  *      @adap: the adapter
6989  *      @mbox: mailbox to use for the FW command
6990  *
6991  *      Issues a command to FW to partially initialize the device.  This
6992  *      performs initialization that generally doesn't depend on user input.
6993  */
6994 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6995 {
6996         struct fw_initialize_cmd c;
6997
6998         memset(&c, 0, sizeof(c));
6999         INIT_CMD(c, INITIALIZE, WRITE);
7000         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7001 }
7002
7003 /**
7004  *      t4_query_params_rw - query FW or device parameters
7005  *      @adap: the adapter
7006  *      @mbox: mailbox to use for the FW command
7007  *      @pf: the PF
7008  *      @vf: the VF
7009  *      @nparams: the number of parameters
7010  *      @params: the parameter names
7011  *      @val: the parameter values
7012  *      @rw: Write and read flag
7013  *      @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7014  *
7015  *      Reads the value of FW or device parameters.  Up to 7 parameters can be
7016  *      queried at once.
7017  */
7018 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7019                        unsigned int vf, unsigned int nparams, const u32 *params,
7020                        u32 *val, int rw, bool sleep_ok)
7021 {
7022         int i, ret;
7023         struct fw_params_cmd c;
7024         __be32 *p = &c.param[0].mnem;
7025
7026         if (nparams > 7)
7027                 return -EINVAL;
7028
7029         memset(&c, 0, sizeof(c));
7030         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7031                                   FW_CMD_REQUEST_F | FW_CMD_READ_F |
7032                                   FW_PARAMS_CMD_PFN_V(pf) |
7033                                   FW_PARAMS_CMD_VFN_V(vf));
7034         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7035
7036         for (i = 0; i < nparams; i++) {
7037                 *p++ = cpu_to_be32(*params++);
7038                 if (rw)
7039                         *p = cpu_to_be32(*(val + i));
7040                 p++;
7041         }
7042
7043         ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7044         if (ret == 0)
7045                 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7046                         *val++ = be32_to_cpu(*p);
7047         return ret;
7048 }
7049
7050 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7051                     unsigned int vf, unsigned int nparams, const u32 *params,
7052                     u32 *val)
7053 {
7054         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7055                                   true);
7056 }
7057
7058 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7059                        unsigned int vf, unsigned int nparams, const u32 *params,
7060                        u32 *val)
7061 {
7062         return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7063                                   false);
7064 }
7065
7066 /**
7067  *      t4_set_params_timeout - sets FW or device parameters
7068  *      @adap: the adapter
7069  *      @mbox: mailbox to use for the FW command
7070  *      @pf: the PF
7071  *      @vf: the VF
7072  *      @nparams: the number of parameters
7073  *      @params: the parameter names
7074  *      @val: the parameter values
7075  *      @timeout: the timeout time
7076  *
7077  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7078  *      specified at once.
7079  */
7080 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7081                           unsigned int pf, unsigned int vf,
7082                           unsigned int nparams, const u32 *params,
7083                           const u32 *val, int timeout)
7084 {
7085         struct fw_params_cmd c;
7086         __be32 *p = &c.param[0].mnem;
7087
7088         if (nparams > 7)
7089                 return -EINVAL;
7090
7091         memset(&c, 0, sizeof(c));
7092         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7093                                   FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7094                                   FW_PARAMS_CMD_PFN_V(pf) |
7095                                   FW_PARAMS_CMD_VFN_V(vf));
7096         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7097
7098         while (nparams--) {
7099                 *p++ = cpu_to_be32(*params++);
7100                 *p++ = cpu_to_be32(*val++);
7101         }
7102
7103         return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7104 }
7105
7106 /**
7107  *      t4_set_params - sets FW or device parameters
7108  *      @adap: the adapter
7109  *      @mbox: mailbox to use for the FW command
7110  *      @pf: the PF
7111  *      @vf: the VF
7112  *      @nparams: the number of parameters
7113  *      @params: the parameter names
7114  *      @val: the parameter values
7115  *
7116  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7117  *      specified at once.
7118  */
7119 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7120                   unsigned int vf, unsigned int nparams, const u32 *params,
7121                   const u32 *val)
7122 {
7123         return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7124                                      FW_CMD_MAX_TIMEOUT);
7125 }
7126
7127 /**
7128  *      t4_cfg_pfvf - configure PF/VF resource limits
7129  *      @adap: the adapter
7130  *      @mbox: mailbox to use for the FW command
7131  *      @pf: the PF being configured
7132  *      @vf: the VF being configured
7133  *      @txq: the max number of egress queues
7134  *      @txq_eth_ctrl: the max number of egress Ethernet or control queues
7135  *      @rxqi: the max number of interrupt-capable ingress queues
7136  *      @rxq: the max number of interruptless ingress queues
7137  *      @tc: the PCI traffic class
7138  *      @vi: the max number of virtual interfaces
7139  *      @cmask: the channel access rights mask for the PF/VF
7140  *      @pmask: the port access rights mask for the PF/VF
7141  *      @nexact: the maximum number of exact MPS filters
7142  *      @rcaps: read capabilities
7143  *      @wxcaps: write/execute capabilities
7144  *
7145  *      Configures resource limits and capabilities for a physical or virtual
7146  *      function.
7147  */
7148 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7149                 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7150                 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7151                 unsigned int vi, unsigned int cmask, unsigned int pmask,
7152                 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7153 {
7154         struct fw_pfvf_cmd c;
7155
7156         memset(&c, 0, sizeof(c));
7157         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7158                                   FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7159                                   FW_PFVF_CMD_VFN_V(vf));
7160         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7161         c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7162                                      FW_PFVF_CMD_NIQ_V(rxq));
7163         c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7164                                     FW_PFVF_CMD_PMASK_V(pmask) |
7165                                     FW_PFVF_CMD_NEQ_V(txq));
7166         c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7167                                       FW_PFVF_CMD_NVI_V(vi) |
7168                                       FW_PFVF_CMD_NEXACTF_V(nexact));
7169         c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7170                                         FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7171                                         FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7172         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7173 }
7174
7175 /**
7176  *      t4_alloc_vi - allocate a virtual interface
7177  *      @adap: the adapter
7178  *      @mbox: mailbox to use for the FW command
7179  *      @port: physical port associated with the VI
7180  *      @pf: the PF owning the VI
7181  *      @vf: the VF owning the VI
7182  *      @nmac: number of MAC addresses needed (1 to 5)
7183  *      @mac: the MAC addresses of the VI
7184  *      @rss_size: size of RSS table slice associated with this VI
7185  *
7186  *      Allocates a virtual interface for the given physical port.  If @mac is
7187  *      not %NULL it contains the MAC addresses of the VI as assigned by FW.
7188  *      @mac should be large enough to hold @nmac Ethernet addresses, they are
7189  *      stored consecutively so the space needed is @nmac * 6 bytes.
7190  *      Returns a negative error number or the non-negative VI id.
7191  */
7192 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7193                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7194                 unsigned int *rss_size)
7195 {
7196         int ret;
7197         struct fw_vi_cmd c;
7198
7199         memset(&c, 0, sizeof(c));
7200         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7201                                   FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7202                                   FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7203         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7204         c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7205         c.nmac = nmac - 1;
7206
7207         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7208         if (ret)
7209                 return ret;
7210
7211         if (mac) {
7212                 memcpy(mac, c.mac, sizeof(c.mac));
7213                 switch (nmac) {
7214                 case 5:
7215                         memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7216                 case 4:
7217                         memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7218                 case 3:
7219                         memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7220                 case 2:
7221                         memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
7222                 }
7223         }
7224         if (rss_size)
7225                 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7226         return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7227 }
7228
7229 /**
7230  *      t4_free_vi - free a virtual interface
7231  *      @adap: the adapter
7232  *      @mbox: mailbox to use for the FW command
7233  *      @pf: the PF owning the VI
7234  *      @vf: the VF owning the VI
7235  *      @viid: virtual interface identifiler
7236  *
7237  *      Free a previously allocated virtual interface.
7238  */
7239 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7240                unsigned int vf, unsigned int viid)
7241 {
7242         struct fw_vi_cmd c;
7243
7244         memset(&c, 0, sizeof(c));
7245         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7246                                   FW_CMD_REQUEST_F |
7247                                   FW_CMD_EXEC_F |
7248                                   FW_VI_CMD_PFN_V(pf) |
7249                                   FW_VI_CMD_VFN_V(vf));
7250         c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7251         c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7252
7253         return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7254 }
7255
7256 /**
7257  *      t4_set_rxmode - set Rx properties of a virtual interface
7258  *      @adap: the adapter
7259  *      @mbox: mailbox to use for the FW command
7260  *      @viid: the VI id
7261  *      @mtu: the new MTU or -1
7262  *      @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7263  *      @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7264  *      @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7265  *      @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7266  *      @sleep_ok: if true we may sleep while awaiting command completion
7267  *
7268  *      Sets Rx properties of a virtual interface.
7269  */
7270 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7271                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
7272                   bool sleep_ok)
7273 {
7274         struct fw_vi_rxmode_cmd c;
7275
7276         /* convert to FW values */
7277         if (mtu < 0)
7278                 mtu = FW_RXMODE_MTU_NO_CHG;
7279         if (promisc < 0)
7280                 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7281         if (all_multi < 0)
7282                 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7283         if (bcast < 0)
7284                 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7285         if (vlanex < 0)
7286                 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7287
7288         memset(&c, 0, sizeof(c));
7289         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7290                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7291                                    FW_VI_RXMODE_CMD_VIID_V(viid));
7292         c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7293         c.mtu_to_vlanexen =
7294                 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7295                             FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7296                             FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7297                             FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7298                             FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7299         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7300 }
7301
7302 /**
7303  *      t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7304  *      @adap: the adapter
7305  *      @mbox: mailbox to use for the FW command
7306  *      @viid: the VI id
7307  *      @free: if true any existing filters for this VI id are first removed
7308  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7309  *      @addr: the MAC address(es)
7310  *      @idx: where to store the index of each allocated filter
7311  *      @hash: pointer to hash address filter bitmap
7312  *      @sleep_ok: call is allowed to sleep
7313  *
7314  *      Allocates an exact-match filter for each of the supplied addresses and
7315  *      sets it to the corresponding address.  If @idx is not %NULL it should
7316  *      have at least @naddr entries, each of which will be set to the index of
7317  *      the filter allocated for the corresponding MAC address.  If a filter
7318  *      could not be allocated for an address its index is set to 0xffff.
7319  *      If @hash is not %NULL addresses that fail to allocate an exact filter
7320  *      are hashed and update the hash filter bitmap pointed at by @hash.
7321  *
7322  *      Returns a negative error number or the number of filters allocated.
7323  */
7324 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7325                       unsigned int viid, bool free, unsigned int naddr,
7326                       const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7327 {
7328         int offset, ret = 0;
7329         struct fw_vi_mac_cmd c;
7330         unsigned int nfilters = 0;
7331         unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7332         unsigned int rem = naddr;
7333
7334         if (naddr > max_naddr)
7335                 return -EINVAL;
7336
7337         for (offset = 0; offset < naddr ; /**/) {
7338                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
7339                                          rem : ARRAY_SIZE(c.u.exact));
7340                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7341                                                      u.exact[fw_naddr]), 16);
7342                 struct fw_vi_mac_exact *p;
7343                 int i;
7344
7345                 memset(&c, 0, sizeof(c));
7346                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7347                                            FW_CMD_REQUEST_F |
7348                                            FW_CMD_WRITE_F |
7349                                            FW_CMD_EXEC_V(free) |
7350                                            FW_VI_MAC_CMD_VIID_V(viid));
7351                 c.freemacs_to_len16 =
7352                         cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
7353                                     FW_CMD_LEN16_V(len16));
7354
7355                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7356                         p->valid_to_idx =
7357                                 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7358                                             FW_VI_MAC_CMD_IDX_V(
7359                                                     FW_VI_MAC_ADD_MAC));
7360                         memcpy(p->macaddr, addr[offset + i],
7361                                sizeof(p->macaddr));
7362                 }
7363
7364                 /* It's okay if we run out of space in our MAC address arena.
7365                  * Some of the addresses we submit may get stored so we need
7366                  * to run through the reply to see what the results were ...
7367                  */
7368                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7369                 if (ret && ret != -FW_ENOMEM)
7370                         break;
7371
7372                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7373                         u16 index = FW_VI_MAC_CMD_IDX_G(
7374                                         be16_to_cpu(p->valid_to_idx));
7375
7376                         if (idx)
7377                                 idx[offset + i] = (index >= max_naddr ?
7378                                                    0xffff : index);
7379                         if (index < max_naddr)
7380                                 nfilters++;
7381                         else if (hash)
7382                                 *hash |= (1ULL <<
7383                                           hash_mac_addr(addr[offset + i]));
7384                 }
7385
7386                 free = false;
7387                 offset += fw_naddr;
7388                 rem -= fw_naddr;
7389         }
7390
7391         if (ret == 0 || ret == -FW_ENOMEM)
7392                 ret = nfilters;
7393         return ret;
7394 }
7395
7396 /**
7397  *      t4_free_mac_filt - frees exact-match filters of given MAC addresses
7398  *      @adap: the adapter
7399  *      @mbox: mailbox to use for the FW command
7400  *      @viid: the VI id
7401  *      @naddr: the number of MAC addresses to allocate filters for (up to 7)
7402  *      @addr: the MAC address(es)
7403  *      @sleep_ok: call is allowed to sleep
7404  *
7405  *      Frees the exact-match filter for each of the supplied addresses
7406  *
7407  *      Returns a negative error number or the number of filters freed.
7408  */
7409 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
7410                      unsigned int viid, unsigned int naddr,
7411                      const u8 **addr, bool sleep_ok)
7412 {
7413         int offset, ret = 0;
7414         struct fw_vi_mac_cmd c;
7415         unsigned int nfilters = 0;
7416         unsigned int max_naddr = is_t4(adap->params.chip) ?
7417                                        NUM_MPS_CLS_SRAM_L_INSTANCES :
7418                                        NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7419         unsigned int rem = naddr;
7420
7421         if (naddr > max_naddr)
7422                 return -EINVAL;
7423
7424         for (offset = 0; offset < (int)naddr ; /**/) {
7425                 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
7426                                          ? rem
7427                                          : ARRAY_SIZE(c.u.exact));
7428                 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7429                                                      u.exact[fw_naddr]), 16);
7430                 struct fw_vi_mac_exact *p;
7431                 int i;
7432
7433                 memset(&c, 0, sizeof(c));
7434                 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7435                                      FW_CMD_REQUEST_F |
7436                                      FW_CMD_WRITE_F |
7437                                      FW_CMD_EXEC_V(0) |
7438                                      FW_VI_MAC_CMD_VIID_V(viid));
7439                 c.freemacs_to_len16 =
7440                                 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7441                                             FW_CMD_LEN16_V(len16));
7442
7443                 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
7444                         p->valid_to_idx = cpu_to_be16(
7445                                 FW_VI_MAC_CMD_VALID_F |
7446                                 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
7447                         memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
7448                 }
7449
7450                 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7451                 if (ret)
7452                         break;
7453
7454                 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7455                         u16 index = FW_VI_MAC_CMD_IDX_G(
7456                                                 be16_to_cpu(p->valid_to_idx));
7457
7458                         if (index < max_naddr)
7459                                 nfilters++;
7460                 }
7461
7462                 offset += fw_naddr;
7463                 rem -= fw_naddr;
7464         }
7465
7466         if (ret == 0)
7467                 ret = nfilters;
7468         return ret;
7469 }
7470
7471 /**
7472  *      t4_change_mac - modifies the exact-match filter for a MAC address
7473  *      @adap: the adapter
7474  *      @mbox: mailbox to use for the FW command
7475  *      @viid: the VI id
7476  *      @idx: index of existing filter for old value of MAC address, or -1
7477  *      @addr: the new MAC address value
7478  *      @persist: whether a new MAC allocation should be persistent
7479  *      @add_smt: if true also add the address to the HW SMT
7480  *
7481  *      Modifies an exact-match filter and sets it to the new MAC address.
7482  *      Note that in general it is not possible to modify the value of a given
7483  *      filter so the generic way to modify an address filter is to free the one
7484  *      being used by the old address value and allocate a new filter for the
7485  *      new address value.  @idx can be -1 if the address is a new addition.
7486  *
7487  *      Returns a negative error number or the index of the filter with the new
7488  *      MAC value.
7489  */
7490 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7491                   int idx, const u8 *addr, bool persist, bool add_smt)
7492 {
7493         int ret, mode;
7494         struct fw_vi_mac_cmd c;
7495         struct fw_vi_mac_exact *p = c.u.exact;
7496         unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
7497
7498         if (idx < 0)                             /* new allocation */
7499                 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7500         mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7501
7502         memset(&c, 0, sizeof(c));
7503         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7504                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7505                                    FW_VI_MAC_CMD_VIID_V(viid));
7506         c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
7507         p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7508                                       FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
7509                                       FW_VI_MAC_CMD_IDX_V(idx));
7510         memcpy(p->macaddr, addr, sizeof(p->macaddr));
7511
7512         ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7513         if (ret == 0) {
7514                 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7515                 if (ret >= max_mac_addr)
7516                         ret = -ENOMEM;
7517         }
7518         return ret;
7519 }
7520
7521 /**
7522  *      t4_set_addr_hash - program the MAC inexact-match hash filter
7523  *      @adap: the adapter
7524  *      @mbox: mailbox to use for the FW command
7525  *      @viid: the VI id
7526  *      @ucast: whether the hash filter should also match unicast addresses
7527  *      @vec: the value to be written to the hash filter
7528  *      @sleep_ok: call is allowed to sleep
7529  *
7530  *      Sets the 64-bit inexact-match hash filter for a virtual interface.
7531  */
7532 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7533                      bool ucast, u64 vec, bool sleep_ok)
7534 {
7535         struct fw_vi_mac_cmd c;
7536
7537         memset(&c, 0, sizeof(c));
7538         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7539                                    FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7540                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7541         c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
7542                                           FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
7543                                           FW_CMD_LEN16_V(1));
7544         c.u.hash.hashvec = cpu_to_be64(vec);
7545         return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7546 }
7547
7548 /**
7549  *      t4_enable_vi_params - enable/disable a virtual interface
7550  *      @adap: the adapter
7551  *      @mbox: mailbox to use for the FW command
7552  *      @viid: the VI id
7553  *      @rx_en: 1=enable Rx, 0=disable Rx
7554  *      @tx_en: 1=enable Tx, 0=disable Tx
7555  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
7556  *
7557  *      Enables/disables a virtual interface.  Note that setting DCB Enable
7558  *      only makes sense when enabling a Virtual Interface ...
7559  */
7560 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7561                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7562 {
7563         struct fw_vi_enable_cmd c;
7564
7565         memset(&c, 0, sizeof(c));
7566         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7567                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7568                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7569         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
7570                                      FW_VI_ENABLE_CMD_EEN_V(tx_en) |
7571                                      FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
7572                                      FW_LEN16(c));
7573         return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7574 }
7575
7576 /**
7577  *      t4_enable_vi - enable/disable a virtual interface
7578  *      @adap: the adapter
7579  *      @mbox: mailbox to use for the FW command
7580  *      @viid: the VI id
7581  *      @rx_en: 1=enable Rx, 0=disable Rx
7582  *      @tx_en: 1=enable Tx, 0=disable Tx
7583  *
7584  *      Enables/disables a virtual interface.
7585  */
7586 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7587                  bool rx_en, bool tx_en)
7588 {
7589         return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7590 }
7591
7592 /**
7593  *      t4_identify_port - identify a VI's port by blinking its LED
7594  *      @adap: the adapter
7595  *      @mbox: mailbox to use for the FW command
7596  *      @viid: the VI id
7597  *      @nblinks: how many times to blink LED at 2.5 Hz
7598  *
7599  *      Identifies a VI's port by blinking its LED.
7600  */
7601 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7602                      unsigned int nblinks)
7603 {
7604         struct fw_vi_enable_cmd c;
7605
7606         memset(&c, 0, sizeof(c));
7607         c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
7608                                    FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7609                                    FW_VI_ENABLE_CMD_VIID_V(viid));
7610         c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
7611         c.blinkdur = cpu_to_be16(nblinks);
7612         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7613 }
7614
7615 /**
7616  *      t4_iq_stop - stop an ingress queue and its FLs
7617  *      @adap: the adapter
7618  *      @mbox: mailbox to use for the FW command
7619  *      @pf: the PF owning the queues
7620  *      @vf: the VF owning the queues
7621  *      @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7622  *      @iqid: ingress queue id
7623  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7624  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7625  *
7626  *      Stops an ingress queue and its associated FLs, if any.  This causes
7627  *      any current or future data/messages destined for these queues to be
7628  *      tossed.
7629  */
7630 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7631                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7632                unsigned int fl0id, unsigned int fl1id)
7633 {
7634         struct fw_iq_cmd c;
7635
7636         memset(&c, 0, sizeof(c));
7637         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7638                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7639                                   FW_IQ_CMD_VFN_V(vf));
7640         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
7641         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7642         c.iqid = cpu_to_be16(iqid);
7643         c.fl0id = cpu_to_be16(fl0id);
7644         c.fl1id = cpu_to_be16(fl1id);
7645         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7646 }
7647
7648 /**
7649  *      t4_iq_free - free an ingress queue and its FLs
7650  *      @adap: the adapter
7651  *      @mbox: mailbox to use for the FW command
7652  *      @pf: the PF owning the queues
7653  *      @vf: the VF owning the queues
7654  *      @iqtype: the ingress queue type
7655  *      @iqid: ingress queue id
7656  *      @fl0id: FL0 queue id or 0xffff if no attached FL0
7657  *      @fl1id: FL1 queue id or 0xffff if no attached FL1
7658  *
7659  *      Frees an ingress queue and its associated FLs, if any.
7660  */
7661 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7662                unsigned int vf, unsigned int iqtype, unsigned int iqid,
7663                unsigned int fl0id, unsigned int fl1id)
7664 {
7665         struct fw_iq_cmd c;
7666
7667         memset(&c, 0, sizeof(c));
7668         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7669                                   FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7670                                   FW_IQ_CMD_VFN_V(vf));
7671         c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7672         c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7673         c.iqid = cpu_to_be16(iqid);
7674         c.fl0id = cpu_to_be16(fl0id);
7675         c.fl1id = cpu_to_be16(fl1id);
7676         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7677 }
7678
7679 /**
7680  *      t4_eth_eq_free - free an Ethernet egress queue
7681  *      @adap: the adapter
7682  *      @mbox: mailbox to use for the FW command
7683  *      @pf: the PF owning the queue
7684  *      @vf: the VF owning the queue
7685  *      @eqid: egress queue id
7686  *
7687  *      Frees an Ethernet egress queue.
7688  */
7689 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7690                    unsigned int vf, unsigned int eqid)
7691 {
7692         struct fw_eq_eth_cmd c;
7693
7694         memset(&c, 0, sizeof(c));
7695         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7696                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7697                                   FW_EQ_ETH_CMD_PFN_V(pf) |
7698                                   FW_EQ_ETH_CMD_VFN_V(vf));
7699         c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7700         c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7701         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7702 }
7703
7704 /**
7705  *      t4_ctrl_eq_free - free a control egress queue
7706  *      @adap: the adapter
7707  *      @mbox: mailbox to use for the FW command
7708  *      @pf: the PF owning the queue
7709  *      @vf: the VF owning the queue
7710  *      @eqid: egress queue id
7711  *
7712  *      Frees a control egress queue.
7713  */
7714 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7715                     unsigned int vf, unsigned int eqid)
7716 {
7717         struct fw_eq_ctrl_cmd c;
7718
7719         memset(&c, 0, sizeof(c));
7720         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7721                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7722                                   FW_EQ_CTRL_CMD_PFN_V(pf) |
7723                                   FW_EQ_CTRL_CMD_VFN_V(vf));
7724         c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7725         c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7726         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7727 }
7728
7729 /**
7730  *      t4_ofld_eq_free - free an offload egress queue
7731  *      @adap: the adapter
7732  *      @mbox: mailbox to use for the FW command
7733  *      @pf: the PF owning the queue
7734  *      @vf: the VF owning the queue
7735  *      @eqid: egress queue id
7736  *
7737  *      Frees a control egress queue.
7738  */
7739 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7740                     unsigned int vf, unsigned int eqid)
7741 {
7742         struct fw_eq_ofld_cmd c;
7743
7744         memset(&c, 0, sizeof(c));
7745         c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7746                                   FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7747                                   FW_EQ_OFLD_CMD_PFN_V(pf) |
7748                                   FW_EQ_OFLD_CMD_VFN_V(vf));
7749         c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7750         c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7751         return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7752 }
7753
7754 /**
7755  *      t4_link_down_rc_str - return a string for a Link Down Reason Code
7756  *      @adap: the adapter
7757  *      @link_down_rc: Link Down Reason Code
7758  *
7759  *      Returns a string representation of the Link Down Reason Code.
7760  */
7761 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
7762 {
7763         static const char * const reason[] = {
7764                 "Link Down",
7765                 "Remote Fault",
7766                 "Auto-negotiation Failure",
7767                 "Reserved",
7768                 "Insufficient Airflow",
7769                 "Unable To Determine Reason",
7770                 "No RX Signal Detected",
7771                 "Reserved",
7772         };
7773
7774         if (link_down_rc >= ARRAY_SIZE(reason))
7775                 return "Bad Reason Code";
7776
7777         return reason[link_down_rc];
7778 }
7779
7780 /**
7781  * Return the highest speed set in the port capabilities, in Mb/s.
7782  */
7783 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
7784 {
7785         #define TEST_SPEED_RETURN(__caps_speed, __speed) \
7786                 do { \
7787                         if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
7788                                 return __speed; \
7789                 } while (0)
7790
7791         TEST_SPEED_RETURN(400G, 400000);
7792         TEST_SPEED_RETURN(200G, 200000);
7793         TEST_SPEED_RETURN(100G, 100000);
7794         TEST_SPEED_RETURN(50G,   50000);
7795         TEST_SPEED_RETURN(40G,   40000);
7796         TEST_SPEED_RETURN(25G,   25000);
7797         TEST_SPEED_RETURN(10G,   10000);
7798         TEST_SPEED_RETURN(1G,     1000);
7799         TEST_SPEED_RETURN(100M,    100);
7800
7801         #undef TEST_SPEED_RETURN
7802
7803         return 0;
7804 }
7805
7806 /**
7807  *      fwcap_to_fwspeed - return highest speed in Port Capabilities
7808  *      @acaps: advertised Port Capabilities
7809  *
7810  *      Get the highest speed for the port from the advertised Port
7811  *      Capabilities.  It will be either the highest speed from the list of
7812  *      speeds or whatever user has set using ethtool.
7813  */
7814 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
7815 {
7816         #define TEST_SPEED_RETURN(__caps_speed) \
7817                 do { \
7818                         if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
7819                                 return FW_PORT_CAP32_SPEED_##__caps_speed; \
7820                 } while (0)
7821
7822         TEST_SPEED_RETURN(400G);
7823         TEST_SPEED_RETURN(200G);
7824         TEST_SPEED_RETURN(100G);
7825         TEST_SPEED_RETURN(50G);
7826         TEST_SPEED_RETURN(40G);
7827         TEST_SPEED_RETURN(25G);
7828         TEST_SPEED_RETURN(10G);
7829         TEST_SPEED_RETURN(1G);
7830         TEST_SPEED_RETURN(100M);
7831
7832         #undef TEST_SPEED_RETURN
7833
7834         return 0;
7835 }
7836
7837 /**
7838  *      lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
7839  *      @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
7840  *
7841  *      Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
7842  *      32-bit Port Capabilities value.
7843  */
7844 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
7845 {
7846         fw_port_cap32_t linkattr = 0;
7847
7848         /* Unfortunately the format of the Link Status in the old
7849          * 16-bit Port Information message isn't the same as the
7850          * 16-bit Port Capabilities bitfield used everywhere else ...
7851          */
7852         if (lstatus & FW_PORT_CMD_RXPAUSE_F)
7853                 linkattr |= FW_PORT_CAP32_FC_RX;
7854         if (lstatus & FW_PORT_CMD_TXPAUSE_F)
7855                 linkattr |= FW_PORT_CAP32_FC_TX;
7856         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7857                 linkattr |= FW_PORT_CAP32_SPEED_100M;
7858         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7859                 linkattr |= FW_PORT_CAP32_SPEED_1G;
7860         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7861                 linkattr |= FW_PORT_CAP32_SPEED_10G;
7862         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
7863                 linkattr |= FW_PORT_CAP32_SPEED_25G;
7864         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7865                 linkattr |= FW_PORT_CAP32_SPEED_40G;
7866         if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
7867                 linkattr |= FW_PORT_CAP32_SPEED_100G;
7868
7869         return linkattr;
7870 }
7871
7872 /**
7873  *      t4_handle_get_port_info - process a FW reply message
7874  *      @pi: the port info
7875  *      @rpl: start of the FW message
7876  *
7877  *      Processes a GET_PORT_INFO FW reply message.
7878  */
7879 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
7880 {
7881         const struct fw_port_cmd *cmd = (const void *)rpl;
7882         int action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
7883         struct adapter *adapter = pi->adapter;
7884         struct link_config *lc = &pi->link_cfg;
7885         int link_ok, linkdnrc;
7886         enum fw_port_type port_type;
7887         enum fw_port_module_type mod_type;
7888         unsigned int speed, fc, fec;
7889         fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
7890
7891         /* Extract the various fields from the Port Information message.
7892          */
7893         switch (action) {
7894         case FW_PORT_ACTION_GET_PORT_INFO: {
7895                 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
7896
7897                 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
7898                 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
7899                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
7900                 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
7901                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
7902                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
7903                 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
7904                 linkattr = lstatus_to_fwcap(lstatus);
7905                 break;
7906         }
7907
7908         case FW_PORT_ACTION_GET_PORT_INFO32: {
7909                 u32 lstatus32;
7910
7911                 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
7912                 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
7913                 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
7914                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
7915                 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
7916                 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
7917                 acaps = be32_to_cpu(cmd->u.info32.acaps32);
7918                 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
7919                 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
7920                 break;
7921         }
7922
7923         default:
7924                 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
7925                         be32_to_cpu(cmd->action_to_len16));
7926                 return;
7927         }
7928
7929         fec = fwcap_to_cc_fec(acaps);
7930         fc = fwcap_to_cc_pause(linkattr);
7931         speed = fwcap_to_speed(linkattr);
7932
7933         if (mod_type != pi->mod_type) {
7934                 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
7935                  * various fundamental Port Capabilities which used to be
7936                  * immutable can now change radically.  We can now have
7937                  * Speeds, Auto-Negotiation, Forward Error Correction, etc.
7938                  * all change based on what Transceiver Module is inserted.
7939                  * So we need to record the Physical "Port" Capabilities on
7940                  * every Transceiver Module change.
7941                  */
7942                 lc->pcaps = pcaps;
7943
7944                 /* When a new Transceiver Module is inserted, the Firmware
7945                  * will examine its i2c EPROM to determine its type and
7946                  * general operating parameters including things like Forward
7947                  * Error Control, etc.  Various IEEE 802.3 standards dictate
7948                  * how to interpret these i2c values to determine default
7949                  * "sutomatic" settings.  We record these for future use when
7950                  * the user explicitly requests these standards-based values.
7951                  */
7952                 lc->def_acaps = acaps;
7953
7954                 /* Some versions of the early T6 Firmware "cheated" when
7955                  * handling different Transceiver Modules by changing the
7956                  * underlaying Port Type reported to the Host Drivers.  As
7957                  * such we need to capture whatever Port Type the Firmware
7958                  * sends us and record it in case it's different from what we
7959                  * were told earlier.  Unfortunately, since Firmware is
7960                  * forever, we'll need to keep this code here forever, but in
7961                  * later T6 Firmware it should just be an assignment of the
7962                  * same value already recorded.
7963                  */
7964                 pi->port_type = port_type;
7965
7966                 pi->mod_type = mod_type;
7967                 t4_os_portmod_changed(adapter, pi->port_id);
7968         }
7969
7970         if (link_ok != lc->link_ok || speed != lc->speed ||
7971             fc != lc->fc || fec != lc->fec) {   /* something changed */
7972                 if (!link_ok && lc->link_ok) {
7973                         lc->link_down_rc = linkdnrc;
7974                         dev_warn(adapter->pdev_dev, "Port %d link down, reason: %s\n",
7975                                  pi->tx_chan, t4_link_down_rc_str(linkdnrc));
7976                 }
7977                 lc->link_ok = link_ok;
7978                 lc->speed = speed;
7979                 lc->fc = fc;
7980                 lc->fec = fec;
7981
7982                 lc->lpacaps = lpacaps;
7983                 lc->acaps = acaps & ADVERT_MASK;
7984
7985                 if (lc->acaps & FW_PORT_CAP32_ANEG) {
7986                         lc->autoneg = AUTONEG_ENABLE;
7987                 } else {
7988                         /* When Autoneg is disabled, user needs to set
7989                          * single speed.
7990                          * Similar to cxgb4_ethtool.c: set_link_ksettings
7991                          */
7992                         lc->acaps = 0;
7993                         lc->speed_caps = fwcap_to_fwspeed(acaps);
7994                         lc->autoneg = AUTONEG_DISABLE;
7995                 }
7996
7997                 t4_os_link_changed(adapter, pi->port_id, link_ok);
7998         }
7999 }
8000
8001 /**
8002  *      t4_update_port_info - retrieve and update port information if changed
8003  *      @pi: the port_info
8004  *
8005  *      We issue a Get Port Information Command to the Firmware and, if
8006  *      successful, we check to see if anything is different from what we
8007  *      last recorded and update things accordingly.
8008  */
8009 int t4_update_port_info(struct port_info *pi)
8010 {
8011         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8012         struct fw_port_cmd port_cmd;
8013         int ret;
8014
8015         memset(&port_cmd, 0, sizeof(port_cmd));
8016         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8017                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8018                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8019         port_cmd.action_to_len16 = cpu_to_be32(
8020                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8021                                      ? FW_PORT_ACTION_GET_PORT_INFO
8022                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
8023                 FW_LEN16(port_cmd));
8024         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8025                          &port_cmd, sizeof(port_cmd), &port_cmd);
8026         if (ret)
8027                 return ret;
8028
8029         t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8030         return 0;
8031 }
8032
8033 /**
8034  *      t4_get_link_params - retrieve basic link parameters for given port
8035  *      @pi: the port
8036  *      @link_okp: value return pointer for link up/down
8037  *      @speedp: value return pointer for speed (Mb/s)
8038  *      @mtup: value return pointer for mtu
8039  *
8040  *      Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8041  *      and MTU for a specified port.  A negative error is returned on
8042  *      failure; 0 on success.
8043  */
8044 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8045                        unsigned int *speedp, unsigned int *mtup)
8046 {
8047         unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8048         struct fw_port_cmd port_cmd;
8049         unsigned int action, link_ok, speed, mtu;
8050         fw_port_cap32_t linkattr;
8051         int ret;
8052
8053         memset(&port_cmd, 0, sizeof(port_cmd));
8054         port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8055                                             FW_CMD_REQUEST_F | FW_CMD_READ_F |
8056                                             FW_PORT_CMD_PORTID_V(pi->tx_chan));
8057         action = (fw_caps == FW_CAPS16
8058                   ? FW_PORT_ACTION_GET_PORT_INFO
8059                   : FW_PORT_ACTION_GET_PORT_INFO32);
8060         port_cmd.action_to_len16 = cpu_to_be32(
8061                 FW_PORT_CMD_ACTION_V(action) |
8062                 FW_LEN16(port_cmd));
8063         ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8064                          &port_cmd, sizeof(port_cmd), &port_cmd);
8065         if (ret)
8066                 return ret;
8067
8068         if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8069                 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8070
8071                 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8072                 linkattr = lstatus_to_fwcap(lstatus);
8073                 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8074         } else {
8075                 u32 lstatus32 =
8076                            be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8077
8078                 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8079                 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8080                 mtu = FW_PORT_CMD_MTU32_G(
8081                         be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8082         }
8083         speed = fwcap_to_speed(linkattr);
8084
8085         *link_okp = link_ok;
8086         *speedp = fwcap_to_speed(linkattr);
8087         *mtup = mtu;
8088
8089         return 0;
8090 }
8091
8092 /**
8093  *      t4_handle_fw_rpl - process a FW reply message
8094  *      @adap: the adapter
8095  *      @rpl: start of the FW message
8096  *
8097  *      Processes a FW message, such as link state change messages.
8098  */
8099 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8100 {
8101         u8 opcode = *(const u8 *)rpl;
8102
8103         /* This might be a port command ... this simplifies the following
8104          * conditionals ...  We can get away with pre-dereferencing
8105          * action_to_len16 because it's in the first 16 bytes and all messages
8106          * will be at least that long.
8107          */
8108         const struct fw_port_cmd *p = (const void *)rpl;
8109         unsigned int action =
8110                 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8111
8112         if (opcode == FW_PORT_CMD &&
8113             (action == FW_PORT_ACTION_GET_PORT_INFO ||
8114              action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8115                 int i;
8116                 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8117                 struct port_info *pi = NULL;
8118
8119                 for_each_port(adap, i) {
8120                         pi = adap2pinfo(adap, i);
8121                         if (pi->tx_chan == chan)
8122                                 break;
8123                 }
8124
8125                 t4_handle_get_port_info(pi, rpl);
8126         } else {
8127                 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8128                          opcode);
8129                 return -EINVAL;
8130         }
8131         return 0;
8132 }
8133
8134 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8135 {
8136         u16 val;
8137
8138         if (pci_is_pcie(adapter->pdev)) {
8139                 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8140                 p->speed = val & PCI_EXP_LNKSTA_CLS;
8141                 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8142         }
8143 }
8144
8145 /**
8146  *      init_link_config - initialize a link's SW state
8147  *      @lc: pointer to structure holding the link state
8148  *      @pcaps: link Port Capabilities
8149  *      @acaps: link current Advertised Port Capabilities
8150  *
8151  *      Initializes the SW state maintained for each link, including the link's
8152  *      capabilities and default speed/flow-control/autonegotiation settings.
8153  */
8154 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8155                              fw_port_cap32_t acaps)
8156 {
8157         lc->pcaps = pcaps;
8158         lc->def_acaps = acaps;
8159         lc->lpacaps = 0;
8160         lc->speed_caps = 0;
8161         lc->speed = 0;
8162         lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8163
8164         /* For Forward Error Control, we default to whatever the Firmware
8165          * tells us the Link is currently advertising.
8166          */
8167         lc->requested_fec = FEC_AUTO;
8168         lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8169
8170         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8171                 lc->acaps = lc->pcaps & ADVERT_MASK;
8172                 lc->autoneg = AUTONEG_ENABLE;
8173                 lc->requested_fc |= PAUSE_AUTONEG;
8174         } else {
8175                 lc->acaps = 0;
8176                 lc->autoneg = AUTONEG_DISABLE;
8177         }
8178 }
8179
8180 #define CIM_PF_NOACCESS 0xeeeeeeee
8181
8182 int t4_wait_dev_ready(void __iomem *regs)
8183 {
8184         u32 whoami;
8185
8186         whoami = readl(regs + PL_WHOAMI_A);
8187         if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8188                 return 0;
8189
8190         msleep(500);
8191         whoami = readl(regs + PL_WHOAMI_A);
8192         return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8193 }
8194
8195 struct flash_desc {
8196         u32 vendor_and_model_id;
8197         u32 size_mb;
8198 };
8199
8200 static int get_flash_params(struct adapter *adap)
8201 {
8202         /* Table for non-Numonix supported flash parts.  Numonix parts are left
8203          * to the preexisting code.  All flash parts have 64KB sectors.
8204          */
8205         static struct flash_desc supported_flash[] = {
8206                 { 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
8207         };
8208
8209         int ret;
8210         u32 info;
8211
8212         ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8213         if (!ret)
8214                 ret = sf1_read(adap, 3, 0, 1, &info);
8215         t4_write_reg(adap, SF_OP_A, 0);                    /* unlock SF */
8216         if (ret)
8217                 return ret;
8218
8219         for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
8220                 if (supported_flash[ret].vendor_and_model_id == info) {
8221                         adap->params.sf_size = supported_flash[ret].size_mb;
8222                         adap->params.sf_nsec =
8223                                 adap->params.sf_size / SF_SEC_SIZE;
8224                         return 0;
8225                 }
8226
8227         if ((info & 0xff) != 0x20)             /* not a Numonix flash */
8228                 return -EINVAL;
8229         info >>= 16;                           /* log2 of size */
8230         if (info >= 0x14 && info < 0x18)
8231                 adap->params.sf_nsec = 1 << (info - 16);
8232         else if (info == 0x18)
8233                 adap->params.sf_nsec = 64;
8234         else
8235                 return -EINVAL;
8236         adap->params.sf_size = 1 << info;
8237         adap->params.sf_fw_start =
8238                 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
8239
8240         if (adap->params.sf_size < FLASH_MIN_SIZE)
8241                 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
8242                          adap->params.sf_size, FLASH_MIN_SIZE);
8243         return 0;
8244 }
8245
8246 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
8247 {
8248         u16 val;
8249         u32 pcie_cap;
8250
8251         pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
8252         if (pcie_cap) {
8253                 pci_read_config_word(adapter->pdev,
8254                                      pcie_cap + PCI_EXP_DEVCTL2, &val);
8255                 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
8256                 val |= range;
8257                 pci_write_config_word(adapter->pdev,
8258                                       pcie_cap + PCI_EXP_DEVCTL2, val);
8259         }
8260 }
8261
8262 /**
8263  *      t4_prep_adapter - prepare SW and HW for operation
8264  *      @adapter: the adapter
8265  *      @reset: if true perform a HW reset
8266  *
8267  *      Initialize adapter SW state for the various HW modules, set initial
8268  *      values for some adapter tunables, take PHYs out of reset, and
8269  *      initialize the MDIO interface.
8270  */
8271 int t4_prep_adapter(struct adapter *adapter)
8272 {
8273         int ret, ver;
8274         uint16_t device_id;
8275         u32 pl_rev;
8276
8277         get_pci_mode(adapter, &adapter->params.pci);
8278         pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
8279
8280         ret = get_flash_params(adapter);
8281         if (ret < 0) {
8282                 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
8283                 return ret;
8284         }
8285
8286         /* Retrieve adapter's device ID
8287          */
8288         pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
8289         ver = device_id >> 12;
8290         adapter->params.chip = 0;
8291         switch (ver) {
8292         case CHELSIO_T4:
8293                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
8294                 adapter->params.arch.sge_fl_db = DBPRIO_F;
8295                 adapter->params.arch.mps_tcam_size =
8296                                  NUM_MPS_CLS_SRAM_L_INSTANCES;
8297                 adapter->params.arch.mps_rplc_size = 128;
8298                 adapter->params.arch.nchan = NCHAN;
8299                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8300                 adapter->params.arch.vfcount = 128;
8301                 /* Congestion map is for 4 channels so that
8302                  * MPS can have 4 priority per port.
8303                  */
8304                 adapter->params.arch.cng_ch_bits_log = 2;
8305                 break;
8306         case CHELSIO_T5:
8307                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
8308                 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
8309                 adapter->params.arch.mps_tcam_size =
8310                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8311                 adapter->params.arch.mps_rplc_size = 128;
8312                 adapter->params.arch.nchan = NCHAN;
8313                 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
8314                 adapter->params.arch.vfcount = 128;
8315                 adapter->params.arch.cng_ch_bits_log = 2;
8316                 break;
8317         case CHELSIO_T6:
8318                 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
8319                 adapter->params.arch.sge_fl_db = 0;
8320                 adapter->params.arch.mps_tcam_size =
8321                                  NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8322                 adapter->params.arch.mps_rplc_size = 256;
8323                 adapter->params.arch.nchan = 2;
8324                 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
8325                 adapter->params.arch.vfcount = 256;
8326                 /* Congestion map will be for 2 channels so that
8327                  * MPS can have 8 priority per port.
8328                  */
8329                 adapter->params.arch.cng_ch_bits_log = 3;
8330                 break;
8331         default:
8332                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
8333                         device_id);
8334                 return -EINVAL;
8335         }
8336
8337         adapter->params.cim_la_size = CIMLA_SIZE;
8338         init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
8339
8340         /*
8341          * Default port for debugging in case we can't reach FW.
8342          */
8343         adapter->params.nports = 1;
8344         adapter->params.portvec = 1;
8345         adapter->params.vpd.cclk = 50000;
8346
8347         /* Set pci completion timeout value to 4 seconds. */
8348         set_pcie_completion_timeout(adapter, 0xd);
8349         return 0;
8350 }
8351
8352 /**
8353  *      t4_shutdown_adapter - shut down adapter, host & wire
8354  *      @adapter: the adapter
8355  *
8356  *      Perform an emergency shutdown of the adapter and stop it from
8357  *      continuing any further communication on the ports or DMA to the
8358  *      host.  This is typically used when the adapter and/or firmware
8359  *      have crashed and we want to prevent any further accidental
8360  *      communication with the rest of the world.  This will also force
8361  *      the port Link Status to go down -- if register writes work --
8362  *      which should help our peers figure out that we're down.
8363  */
8364 int t4_shutdown_adapter(struct adapter *adapter)
8365 {
8366         int port;
8367
8368         t4_intr_disable(adapter);
8369         t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
8370         for_each_port(adapter, port) {
8371                 u32 a_port_cfg = is_t4(adapter->params.chip) ?
8372                                        PORT_REG(port, XGMAC_PORT_CFG_A) :
8373                                        T5_PORT_REG(port, MAC_PORT_CFG_A);
8374
8375                 t4_write_reg(adapter, a_port_cfg,
8376                              t4_read_reg(adapter, a_port_cfg)
8377                              & ~SIGNAL_DET_V(1));
8378         }
8379         t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
8380
8381         return 0;
8382 }
8383
8384 /**
8385  *      t4_bar2_sge_qregs - return BAR2 SGE Queue register information
8386  *      @adapter: the adapter
8387  *      @qid: the Queue ID
8388  *      @qtype: the Ingress or Egress type for @qid
8389  *      @user: true if this request is for a user mode queue
8390  *      @pbar2_qoffset: BAR2 Queue Offset
8391  *      @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
8392  *
8393  *      Returns the BAR2 SGE Queue Registers information associated with the
8394  *      indicated Absolute Queue ID.  These are passed back in return value
8395  *      pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
8396  *      and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
8397  *
8398  *      This may return an error which indicates that BAR2 SGE Queue
8399  *      registers aren't available.  If an error is not returned, then the
8400  *      following values are returned:
8401  *
8402  *        *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
8403  *        *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
8404  *
8405  *      If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
8406  *      require the "Inferred Queue ID" ability may be used.  E.g. the
8407  *      Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
8408  *      then these "Inferred Queue ID" register may not be used.
8409  */
8410 int t4_bar2_sge_qregs(struct adapter *adapter,
8411                       unsigned int qid,
8412                       enum t4_bar2_qtype qtype,
8413                       int user,
8414                       u64 *pbar2_qoffset,
8415                       unsigned int *pbar2_qid)
8416 {
8417         unsigned int page_shift, page_size, qpp_shift, qpp_mask;
8418         u64 bar2_page_offset, bar2_qoffset;
8419         unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
8420
8421         /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
8422         if (!user && is_t4(adapter->params.chip))
8423                 return -EINVAL;
8424
8425         /* Get our SGE Page Size parameters.
8426          */
8427         page_shift = adapter->params.sge.hps + 10;
8428         page_size = 1 << page_shift;
8429
8430         /* Get the right Queues per Page parameters for our Queue.
8431          */
8432         qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
8433                      ? adapter->params.sge.eq_qpp
8434                      : adapter->params.sge.iq_qpp);
8435         qpp_mask = (1 << qpp_shift) - 1;
8436
8437         /*  Calculate the basics of the BAR2 SGE Queue register area:
8438          *  o The BAR2 page the Queue registers will be in.
8439          *  o The BAR2 Queue ID.
8440          *  o The BAR2 Queue ID Offset into the BAR2 page.
8441          */
8442         bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
8443         bar2_qid = qid & qpp_mask;
8444         bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
8445
8446         /* If the BAR2 Queue ID Offset is less than the Page Size, then the
8447          * hardware will infer the Absolute Queue ID simply from the writes to
8448          * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
8449          * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
8450          * write to the first BAR2 SGE Queue Area within the BAR2 Page with
8451          * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
8452          * from the BAR2 Page and BAR2 Queue ID.
8453          *
8454          * One important censequence of this is that some BAR2 SGE registers
8455          * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
8456          * there.  But other registers synthesize the SGE Queue ID purely
8457          * from the writes to the registers -- the Write Combined Doorbell
8458          * Buffer is a good example.  These BAR2 SGE Registers are only
8459          * available for those BAR2 SGE Register areas where the SGE Absolute
8460          * Queue ID can be inferred from simple writes.
8461          */
8462         bar2_qoffset = bar2_page_offset;
8463         bar2_qinferred = (bar2_qid_offset < page_size);
8464         if (bar2_qinferred) {
8465                 bar2_qoffset += bar2_qid_offset;
8466                 bar2_qid = 0;
8467         }
8468
8469         *pbar2_qoffset = bar2_qoffset;
8470         *pbar2_qid = bar2_qid;
8471         return 0;
8472 }
8473
8474 /**
8475  *      t4_init_devlog_params - initialize adapter->params.devlog
8476  *      @adap: the adapter
8477  *
8478  *      Initialize various fields of the adapter's Firmware Device Log
8479  *      Parameters structure.
8480  */
8481 int t4_init_devlog_params(struct adapter *adap)
8482 {
8483         struct devlog_params *dparams = &adap->params.devlog;
8484         u32 pf_dparams;
8485         unsigned int devlog_meminfo;
8486         struct fw_devlog_cmd devlog_cmd;
8487         int ret;
8488
8489         /* If we're dealing with newer firmware, the Device Log Paramerters
8490          * are stored in a designated register which allows us to access the
8491          * Device Log even if we can't talk to the firmware.
8492          */
8493         pf_dparams =
8494                 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
8495         if (pf_dparams) {
8496                 unsigned int nentries, nentries128;
8497
8498                 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
8499                 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
8500
8501                 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
8502                 nentries = (nentries128 + 1) * 128;
8503                 dparams->size = nentries * sizeof(struct fw_devlog_e);
8504
8505                 return 0;
8506         }
8507
8508         /* Otherwise, ask the firmware for it's Device Log Parameters.
8509          */
8510         memset(&devlog_cmd, 0, sizeof(devlog_cmd));
8511         devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
8512                                              FW_CMD_REQUEST_F | FW_CMD_READ_F);
8513         devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
8514         ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
8515                          &devlog_cmd);
8516         if (ret)
8517                 return ret;
8518
8519         devlog_meminfo =
8520                 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
8521         dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
8522         dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
8523         dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
8524
8525         return 0;
8526 }
8527
8528 /**
8529  *      t4_init_sge_params - initialize adap->params.sge
8530  *      @adapter: the adapter
8531  *
8532  *      Initialize various fields of the adapter's SGE Parameters structure.
8533  */
8534 int t4_init_sge_params(struct adapter *adapter)
8535 {
8536         struct sge_params *sge_params = &adapter->params.sge;
8537         u32 hps, qpp;
8538         unsigned int s_hps, s_qpp;
8539
8540         /* Extract the SGE Page Size for our PF.
8541          */
8542         hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
8543         s_hps = (HOSTPAGESIZEPF0_S +
8544                  (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
8545         sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
8546
8547         /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
8548          */
8549         s_qpp = (QUEUESPERPAGEPF0_S +
8550                 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
8551         qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
8552         sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8553         qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
8554         sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
8555
8556         return 0;
8557 }
8558
8559 /**
8560  *      t4_init_tp_params - initialize adap->params.tp
8561  *      @adap: the adapter
8562  *
8563  *      Initialize various fields of the adapter's TP Parameters structure.
8564  */
8565 int t4_init_tp_params(struct adapter *adap)
8566 {
8567         int chan;
8568         u32 v;
8569
8570         v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
8571         adap->params.tp.tre = TIMERRESOLUTION_G(v);
8572         adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
8573
8574         /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
8575         for (chan = 0; chan < NCHAN; chan++)
8576                 adap->params.tp.tx_modq[chan] = chan;
8577
8578         /* Cache the adapter's Compressed Filter Mode and global Incress
8579          * Configuration.
8580          */
8581         if (t4_use_ldst(adap)) {
8582                 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
8583                                 TP_VLAN_PRI_MAP_A, 1);
8584                 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
8585                                 TP_INGRESS_CONFIG_A, 1);
8586         } else {
8587                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
8588                                  &adap->params.tp.vlan_pri_map, 1,
8589                                  TP_VLAN_PRI_MAP_A);
8590                 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
8591                                  &adap->params.tp.ingress_config, 1,
8592                                  TP_INGRESS_CONFIG_A);
8593         }
8594         /* For T6, cache the adapter's compressed error vector
8595          * and passing outer header info for encapsulated packets.
8596          */
8597         if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
8598                 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
8599                 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
8600         }
8601
8602         /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
8603          * shift positions of several elements of the Compressed Filter Tuple
8604          * for this adapter which we need frequently ...
8605          */
8606         adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
8607         adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
8608         adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
8609         adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
8610                                                                PROTOCOL_F);
8611
8612         /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
8613          * represents the presence of an Outer VLAN instead of a VNIC ID.
8614          */
8615         if ((adap->params.tp.ingress_config & VNIC_F) == 0)
8616                 adap->params.tp.vnic_shift = -1;
8617
8618         return 0;
8619 }
8620
8621 /**
8622  *      t4_filter_field_shift - calculate filter field shift
8623  *      @adap: the adapter
8624  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
8625  *
8626  *      Return the shift position of a filter field within the Compressed
8627  *      Filter Tuple.  The filter field is specified via its selection bit
8628  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
8629  */
8630 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
8631 {
8632         unsigned int filter_mode = adap->params.tp.vlan_pri_map;
8633         unsigned int sel;
8634         int field_shift;
8635
8636         if ((filter_mode & filter_sel) == 0)
8637                 return -1;
8638
8639         for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
8640                 switch (filter_mode & sel) {
8641                 case FCOE_F:
8642                         field_shift += FT_FCOE_W;
8643                         break;
8644                 case PORT_F:
8645                         field_shift += FT_PORT_W;
8646                         break;
8647                 case VNIC_ID_F:
8648                         field_shift += FT_VNIC_ID_W;
8649                         break;
8650                 case VLAN_F:
8651                         field_shift += FT_VLAN_W;
8652                         break;
8653                 case TOS_F:
8654                         field_shift += FT_TOS_W;
8655                         break;
8656                 case PROTOCOL_F:
8657                         field_shift += FT_PROTOCOL_W;
8658                         break;
8659                 case ETHERTYPE_F:
8660                         field_shift += FT_ETHERTYPE_W;
8661                         break;
8662                 case MACMATCH_F:
8663                         field_shift += FT_MACMATCH_W;
8664                         break;
8665                 case MPSHITTYPE_F:
8666                         field_shift += FT_MPSHITTYPE_W;
8667                         break;
8668                 case FRAGMENTATION_F:
8669                         field_shift += FT_FRAGMENTATION_W;
8670                         break;
8671                 }
8672         }
8673         return field_shift;
8674 }
8675
8676 int t4_init_rss_mode(struct adapter *adap, int mbox)
8677 {
8678         int i, ret;
8679         struct fw_rss_vi_config_cmd rvc;
8680
8681         memset(&rvc, 0, sizeof(rvc));
8682
8683         for_each_port(adap, i) {
8684                 struct port_info *p = adap2pinfo(adap, i);
8685
8686                 rvc.op_to_viid =
8687                         cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
8688                                     FW_CMD_REQUEST_F | FW_CMD_READ_F |
8689                                     FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
8690                 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
8691                 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
8692                 if (ret)
8693                         return ret;
8694                 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
8695         }
8696         return 0;
8697 }
8698
8699 /**
8700  *      t4_init_portinfo - allocate a virtual interface and initialize port_info
8701  *      @pi: the port_info
8702  *      @mbox: mailbox to use for the FW command
8703  *      @port: physical port associated with the VI
8704  *      @pf: the PF owning the VI
8705  *      @vf: the VF owning the VI
8706  *      @mac: the MAC address of the VI
8707  *
8708  *      Allocates a virtual interface for the given physical port.  If @mac is
8709  *      not %NULL it contains the MAC address of the VI as assigned by FW.
8710  *      @mac should be large enough to hold an Ethernet address.
8711  *      Returns < 0 on error.
8712  */
8713 int t4_init_portinfo(struct port_info *pi, int mbox,
8714                      int port, int pf, int vf, u8 mac[])
8715 {
8716         struct adapter *adapter = pi->adapter;
8717         unsigned int fw_caps = adapter->params.fw_caps_support;
8718         struct fw_port_cmd cmd;
8719         unsigned int rss_size;
8720         enum fw_port_type port_type;
8721         int mdio_addr;
8722         fw_port_cap32_t pcaps, acaps;
8723         int ret;
8724
8725         /* If we haven't yet determined whether we're talking to Firmware
8726          * which knows the new 32-bit Port Capabilities, it's time to find
8727          * out now.  This will also tell new Firmware to send us Port Status
8728          * Updates using the new 32-bit Port Capabilities version of the
8729          * Port Information message.
8730          */
8731         if (fw_caps == FW_CAPS_UNKNOWN) {
8732                 u32 param, val;
8733
8734                 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
8735                          FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
8736                 val = 1;
8737                 ret = t4_set_params(adapter, mbox, pf, vf, 1, &param, &val);
8738                 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
8739                 adapter->params.fw_caps_support = fw_caps;
8740         }
8741
8742         memset(&cmd, 0, sizeof(cmd));
8743         cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8744                                        FW_CMD_REQUEST_F | FW_CMD_READ_F |
8745                                        FW_PORT_CMD_PORTID_V(port));
8746         cmd.action_to_len16 = cpu_to_be32(
8747                 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8748                                      ? FW_PORT_ACTION_GET_PORT_INFO
8749                                      : FW_PORT_ACTION_GET_PORT_INFO32) |
8750                 FW_LEN16(cmd));
8751         ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
8752         if (ret)
8753                 return ret;
8754
8755         /* Extract the various fields from the Port Information message.
8756          */
8757         if (fw_caps == FW_CAPS16) {
8758                 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
8759
8760                 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8761                 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
8762                              ? FW_PORT_CMD_MDIOADDR_G(lstatus)
8763                              : -1);
8764                 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
8765                 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
8766         } else {
8767                 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
8768
8769                 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8770                 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
8771                              ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
8772                              : -1);
8773                 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
8774                 acaps = be32_to_cpu(cmd.u.info32.acaps32);
8775         }
8776
8777         ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
8778         if (ret < 0)
8779                 return ret;
8780
8781         pi->viid = ret;
8782         pi->tx_chan = port;
8783         pi->lport = port;
8784         pi->rss_size = rss_size;
8785
8786         pi->port_type = port_type;
8787         pi->mdio_addr = mdio_addr;
8788         pi->mod_type = FW_PORT_MOD_TYPE_NA;
8789
8790         init_link_config(&pi->link_cfg, pcaps, acaps);
8791         return 0;
8792 }
8793
8794 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
8795 {
8796         u8 addr[6];
8797         int ret, i, j = 0;
8798
8799         for_each_port(adap, i) {
8800                 struct port_info *pi = adap2pinfo(adap, i);
8801
8802                 while ((adap->params.portvec & (1 << j)) == 0)
8803                         j++;
8804
8805                 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
8806                 if (ret)
8807                         return ret;
8808
8809                 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
8810                 j++;
8811         }
8812         return 0;
8813 }
8814
8815 /**
8816  *      t4_read_cimq_cfg - read CIM queue configuration
8817  *      @adap: the adapter
8818  *      @base: holds the queue base addresses in bytes
8819  *      @size: holds the queue sizes in bytes
8820  *      @thres: holds the queue full thresholds in bytes
8821  *
8822  *      Returns the current configuration of the CIM queues, starting with
8823  *      the IBQs, then the OBQs.
8824  */
8825 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
8826 {
8827         unsigned int i, v;
8828         int cim_num_obq = is_t4(adap->params.chip) ?
8829                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8830
8831         for (i = 0; i < CIM_NUM_IBQ; i++) {
8832                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
8833                              QUENUMSELECT_V(i));
8834                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8835                 /* value is in 256-byte units */
8836                 *base++ = CIMQBASE_G(v) * 256;
8837                 *size++ = CIMQSIZE_G(v) * 256;
8838                 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
8839         }
8840         for (i = 0; i < cim_num_obq; i++) {
8841                 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8842                              QUENUMSELECT_V(i));
8843                 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8844                 /* value is in 256-byte units */
8845                 *base++ = CIMQBASE_G(v) * 256;
8846                 *size++ = CIMQSIZE_G(v) * 256;
8847         }
8848 }
8849
8850 /**
8851  *      t4_read_cim_ibq - read the contents of a CIM inbound queue
8852  *      @adap: the adapter
8853  *      @qid: the queue index
8854  *      @data: where to store the queue contents
8855  *      @n: capacity of @data in 32-bit words
8856  *
8857  *      Reads the contents of the selected CIM queue starting at address 0 up
8858  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8859  *      error and the number of 32-bit words actually read on success.
8860  */
8861 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8862 {
8863         int i, err, attempts;
8864         unsigned int addr;
8865         const unsigned int nwords = CIM_IBQ_SIZE * 4;
8866
8867         if (qid > 5 || (n & 3))
8868                 return -EINVAL;
8869
8870         addr = qid * nwords;
8871         if (n > nwords)
8872                 n = nwords;
8873
8874         /* It might take 3-10ms before the IBQ debug read access is allowed.
8875          * Wait for 1 Sec with a delay of 1 usec.
8876          */
8877         attempts = 1000000;
8878
8879         for (i = 0; i < n; i++, addr++) {
8880                 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
8881                              IBQDBGEN_F);
8882                 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
8883                                       attempts, 1);
8884                 if (err)
8885                         return err;
8886                 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
8887         }
8888         t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
8889         return i;
8890 }
8891
8892 /**
8893  *      t4_read_cim_obq - read the contents of a CIM outbound queue
8894  *      @adap: the adapter
8895  *      @qid: the queue index
8896  *      @data: where to store the queue contents
8897  *      @n: capacity of @data in 32-bit words
8898  *
8899  *      Reads the contents of the selected CIM queue starting at address 0 up
8900  *      to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8901  *      error and the number of 32-bit words actually read on success.
8902  */
8903 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8904 {
8905         int i, err;
8906         unsigned int addr, v, nwords;
8907         int cim_num_obq = is_t4(adap->params.chip) ?
8908                                 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
8909
8910         if ((qid > (cim_num_obq - 1)) || (n & 3))
8911                 return -EINVAL;
8912
8913         t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
8914                      QUENUMSELECT_V(qid));
8915         v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
8916
8917         addr = CIMQBASE_G(v) * 64;    /* muliple of 256 -> muliple of 4 */
8918         nwords = CIMQSIZE_G(v) * 64;  /* same */
8919         if (n > nwords)
8920                 n = nwords;
8921
8922         for (i = 0; i < n; i++, addr++) {
8923                 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
8924                              OBQDBGEN_F);
8925                 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
8926                                       2, 1);
8927                 if (err)
8928                         return err;
8929                 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
8930         }
8931         t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
8932         return i;
8933 }
8934
8935 /**
8936  *      t4_cim_read - read a block from CIM internal address space
8937  *      @adap: the adapter
8938  *      @addr: the start address within the CIM address space
8939  *      @n: number of words to read
8940  *      @valp: where to store the result
8941  *
8942  *      Reads a block of 4-byte words from the CIM intenal address space.
8943  */
8944 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
8945                 unsigned int *valp)
8946 {
8947         int ret = 0;
8948
8949         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8950                 return -EBUSY;
8951
8952         for ( ; !ret && n--; addr += 4) {
8953                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
8954                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8955                                       0, 5, 2);
8956                 if (!ret)
8957                         *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
8958         }
8959         return ret;
8960 }
8961
8962 /**
8963  *      t4_cim_write - write a block into CIM internal address space
8964  *      @adap: the adapter
8965  *      @addr: the start address within the CIM address space
8966  *      @n: number of words to write
8967  *      @valp: set of values to write
8968  *
8969  *      Writes a block of 4-byte words into the CIM intenal address space.
8970  */
8971 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8972                  const unsigned int *valp)
8973 {
8974         int ret = 0;
8975
8976         if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
8977                 return -EBUSY;
8978
8979         for ( ; !ret && n--; addr += 4) {
8980                 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
8981                 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
8982                 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
8983                                       0, 5, 2);
8984         }
8985         return ret;
8986 }
8987
8988 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8989                          unsigned int val)
8990 {
8991         return t4_cim_write(adap, addr, 1, &val);
8992 }
8993
8994 /**
8995  *      t4_cim_read_la - read CIM LA capture buffer
8996  *      @adap: the adapter
8997  *      @la_buf: where to store the LA data
8998  *      @wrptr: the HW write pointer within the capture buffer
8999  *
9000  *      Reads the contents of the CIM LA buffer with the most recent entry at
9001  *      the end of the returned data and with the entry at @wrptr first.
9002  *      We try to leave the LA in the running state we find it in.
9003  */
9004 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9005 {
9006         int i, ret;
9007         unsigned int cfg, val, idx;
9008
9009         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9010         if (ret)
9011                 return ret;
9012
9013         if (cfg & UPDBGLAEN_F) {        /* LA is running, freeze it */
9014                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9015                 if (ret)
9016                         return ret;
9017         }
9018
9019         ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9020         if (ret)
9021                 goto restart;
9022
9023         idx = UPDBGLAWRPTR_G(val);
9024         if (wrptr)
9025                 *wrptr = idx;
9026
9027         for (i = 0; i < adap->params.cim_la_size; i++) {
9028                 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9029                                     UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9030                 if (ret)
9031                         break;
9032                 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9033                 if (ret)
9034                         break;
9035                 if (val & UPDBGLARDEN_F) {
9036                         ret = -ETIMEDOUT;
9037                         break;
9038                 }
9039                 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9040                 if (ret)
9041                         break;
9042
9043                 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9044                  * identify the 32-bit portion of the full 312-bit data
9045                  */
9046                 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9047                         idx = (idx & 0xff0) + 0x10;
9048                 else
9049                         idx++;
9050                 /* address can't exceed 0xfff */
9051                 idx &= UPDBGLARDPTR_M;
9052         }
9053 restart:
9054         if (cfg & UPDBGLAEN_F) {
9055                 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9056                                       cfg & ~UPDBGLARDEN_F);
9057                 if (!ret)
9058                         ret = r;
9059         }
9060         return ret;
9061 }
9062
9063 /**
9064  *      t4_tp_read_la - read TP LA capture buffer
9065  *      @adap: the adapter
9066  *      @la_buf: where to store the LA data
9067  *      @wrptr: the HW write pointer within the capture buffer
9068  *
9069  *      Reads the contents of the TP LA buffer with the most recent entry at
9070  *      the end of the returned data and with the entry at @wrptr first.
9071  *      We leave the LA in the running state we find it in.
9072  */
9073 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9074 {
9075         bool last_incomplete;
9076         unsigned int i, cfg, val, idx;
9077
9078         cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
9079         if (cfg & DBGLAENABLE_F)                        /* freeze LA */
9080                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9081                              adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
9082
9083         val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
9084         idx = DBGLAWPTR_G(val);
9085         last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
9086         if (last_incomplete)
9087                 idx = (idx + 1) & DBGLARPTR_M;
9088         if (wrptr)
9089                 *wrptr = idx;
9090
9091         val &= 0xffff;
9092         val &= ~DBGLARPTR_V(DBGLARPTR_M);
9093         val |= adap->params.tp.la_mask;
9094
9095         for (i = 0; i < TPLA_SIZE; i++) {
9096                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
9097                 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
9098                 idx = (idx + 1) & DBGLARPTR_M;
9099         }
9100
9101         /* Wipe out last entry if it isn't valid */
9102         if (last_incomplete)
9103                 la_buf[TPLA_SIZE - 1] = ~0ULL;
9104
9105         if (cfg & DBGLAENABLE_F)                    /* restore running state */
9106                 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9107                              cfg | adap->params.tp.la_mask);
9108 }
9109
9110 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9111  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
9112  * state for more than the Warning Threshold then we'll issue a warning about
9113  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
9114  * appears to be hung every Warning Repeat second till the situation clears.
9115  * If the situation clears, we'll note that as well.
9116  */
9117 #define SGE_IDMA_WARN_THRESH 1
9118 #define SGE_IDMA_WARN_REPEAT 300
9119
9120 /**
9121  *      t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9122  *      @adapter: the adapter
9123  *      @idma: the adapter IDMA Monitor state
9124  *
9125  *      Initialize the state of an SGE Ingress DMA Monitor.
9126  */
9127 void t4_idma_monitor_init(struct adapter *adapter,
9128                           struct sge_idma_monitor_state *idma)
9129 {
9130         /* Initialize the state variables for detecting an SGE Ingress DMA
9131          * hang.  The SGE has internal counters which count up on each clock
9132          * tick whenever the SGE finds its Ingress DMA State Engines in the
9133          * same state they were on the previous clock tick.  The clock used is
9134          * the Core Clock so we have a limit on the maximum "time" they can
9135          * record; typically a very small number of seconds.  For instance,
9136          * with a 600MHz Core Clock, we can only count up to a bit more than
9137          * 7s.  So we'll synthesize a larger counter in order to not run the
9138          * risk of having the "timers" overflow and give us the flexibility to
9139          * maintain a Hung SGE State Machine of our own which operates across
9140          * a longer time frame.
9141          */
9142         idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
9143         idma->idma_stalled[0] = 0;
9144         idma->idma_stalled[1] = 0;
9145 }
9146
9147 /**
9148  *      t4_idma_monitor - monitor SGE Ingress DMA state
9149  *      @adapter: the adapter
9150  *      @idma: the adapter IDMA Monitor state
9151  *      @hz: number of ticks/second
9152  *      @ticks: number of ticks since the last IDMA Monitor call
9153  */
9154 void t4_idma_monitor(struct adapter *adapter,
9155                      struct sge_idma_monitor_state *idma,
9156                      int hz, int ticks)
9157 {
9158         int i, idma_same_state_cnt[2];
9159
9160          /* Read the SGE Debug Ingress DMA Same State Count registers.  These
9161           * are counters inside the SGE which count up on each clock when the
9162           * SGE finds its Ingress DMA State Engines in the same states they
9163           * were in the previous clock.  The counters will peg out at
9164           * 0xffffffff without wrapping around so once they pass the 1s
9165           * threshold they'll stay above that till the IDMA state changes.
9166           */
9167         t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
9168         idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
9169         idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9170
9171         for (i = 0; i < 2; i++) {
9172                 u32 debug0, debug11;
9173
9174                 /* If the Ingress DMA Same State Counter ("timer") is less
9175                  * than 1s, then we can reset our synthesized Stall Timer and
9176                  * continue.  If we have previously emitted warnings about a
9177                  * potential stalled Ingress Queue, issue a note indicating
9178                  * that the Ingress Queue has resumed forward progress.
9179                  */
9180                 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
9181                         if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
9182                                 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
9183                                          "resumed after %d seconds\n",
9184                                          i, idma->idma_qid[i],
9185                                          idma->idma_stalled[i] / hz);
9186                         idma->idma_stalled[i] = 0;
9187                         continue;
9188                 }
9189
9190                 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9191                  * domain.  The first time we get here it'll be because we
9192                  * passed the 1s Threshold; each additional time it'll be
9193                  * because the RX Timer Callback is being fired on its regular
9194                  * schedule.
9195                  *
9196                  * If the stall is below our Potential Hung Ingress Queue
9197                  * Warning Threshold, continue.
9198                  */
9199                 if (idma->idma_stalled[i] == 0) {
9200                         idma->idma_stalled[i] = hz;
9201                         idma->idma_warn[i] = 0;
9202                 } else {
9203                         idma->idma_stalled[i] += ticks;
9204                         idma->idma_warn[i] -= ticks;
9205                 }
9206
9207                 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
9208                         continue;
9209
9210                 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9211                  */
9212                 if (idma->idma_warn[i] > 0)
9213                         continue;
9214                 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
9215
9216                 /* Read and save the SGE IDMA State and Queue ID information.
9217                  * We do this every time in case it changes across time ...
9218                  * can't be too careful ...
9219                  */
9220                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
9221                 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9222                 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
9223
9224                 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
9225                 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
9226                 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
9227
9228                 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
9229                          "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
9230                          i, idma->idma_qid[i], idma->idma_state[i],
9231                          idma->idma_stalled[i] / hz,
9232                          debug0, debug11);
9233                 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
9234         }
9235 }
9236
9237 /**
9238  *      t4_load_cfg - download config file
9239  *      @adap: the adapter
9240  *      @cfg_data: the cfg text file to write
9241  *      @size: text file size
9242  *
9243  *      Write the supplied config text file to the card's serial flash.
9244  */
9245 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
9246 {
9247         int ret, i, n, cfg_addr;
9248         unsigned int addr;
9249         unsigned int flash_cfg_start_sec;
9250         unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9251
9252         cfg_addr = t4_flash_cfg_addr(adap);
9253         if (cfg_addr < 0)
9254                 return cfg_addr;
9255
9256         addr = cfg_addr;
9257         flash_cfg_start_sec = addr / SF_SEC_SIZE;
9258
9259         if (size > FLASH_CFG_MAX_SIZE) {
9260                 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
9261                         FLASH_CFG_MAX_SIZE);
9262                 return -EFBIG;
9263         }
9264
9265         i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,    /* # of sectors spanned */
9266                          sf_sec_size);
9267         ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9268                                      flash_cfg_start_sec + i - 1);
9269         /* If size == 0 then we're simply erasing the FLASH sectors associated
9270          * with the on-adapter Firmware Configuration File.
9271          */
9272         if (ret || size == 0)
9273                 goto out;
9274
9275         /* this will write to the flash up to SF_PAGE_SIZE at a time */
9276         for (i = 0; i < size; i += SF_PAGE_SIZE) {
9277                 if ((size - i) <  SF_PAGE_SIZE)
9278                         n = size - i;
9279                 else
9280                         n = SF_PAGE_SIZE;
9281                 ret = t4_write_flash(adap, addr, n, cfg_data);
9282                 if (ret)
9283                         goto out;
9284
9285                 addr += SF_PAGE_SIZE;
9286                 cfg_data += SF_PAGE_SIZE;
9287         }
9288
9289 out:
9290         if (ret)
9291                 dev_err(adap->pdev_dev, "config file %s failed %d\n",
9292                         (size == 0 ? "clear" : "download"), ret);
9293         return ret;
9294 }
9295
9296 /**
9297  *      t4_set_vf_mac - Set MAC address for the specified VF
9298  *      @adapter: The adapter
9299  *      @vf: one of the VFs instantiated by the specified PF
9300  *      @naddr: the number of MAC addresses
9301  *      @addr: the MAC address(es) to be set to the specified VF
9302  */
9303 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
9304                       unsigned int naddr, u8 *addr)
9305 {
9306         struct fw_acl_mac_cmd cmd;
9307
9308         memset(&cmd, 0, sizeof(cmd));
9309         cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
9310                                     FW_CMD_REQUEST_F |
9311                                     FW_CMD_WRITE_F |
9312                                     FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
9313                                     FW_ACL_MAC_CMD_VFN_V(vf));
9314
9315         /* Note: Do not enable the ACL */
9316         cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
9317         cmd.nmac = naddr;
9318
9319         switch (adapter->pf) {
9320         case 3:
9321                 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
9322                 break;
9323         case 2:
9324                 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
9325                 break;
9326         case 1:
9327                 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
9328                 break;
9329         case 0:
9330                 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
9331                 break;
9332         }
9333
9334         return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
9335 }
9336
9337 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
9338                     int rateunit, int ratemode, int channel, int class,
9339                     int minrate, int maxrate, int weight, int pktsize)
9340 {
9341         struct fw_sched_cmd cmd;
9342
9343         memset(&cmd, 0, sizeof(cmd));
9344         cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
9345                                       FW_CMD_REQUEST_F |
9346                                       FW_CMD_WRITE_F);
9347         cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9348
9349         cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9350         cmd.u.params.type = type;
9351         cmd.u.params.level = level;
9352         cmd.u.params.mode = mode;
9353         cmd.u.params.ch = channel;
9354         cmd.u.params.cl = class;
9355         cmd.u.params.unit = rateunit;
9356         cmd.u.params.rate = ratemode;
9357         cmd.u.params.min = cpu_to_be32(minrate);
9358         cmd.u.params.max = cpu_to_be32(maxrate);
9359         cmd.u.params.weight = cpu_to_be16(weight);
9360         cmd.u.params.pktsize = cpu_to_be16(pktsize);
9361
9362         return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
9363                                NULL, 1);
9364 }